From ddacba74a8a4cf026275dc3f1023a29461f3cb66 Mon Sep 17 00:00:00 2001 From: Prashant Kumar Date: Wed, 10 Jul 2024 17:53:48 +0530 Subject: [PATCH] [LLVMGPU][ROCm] Add MFMA_F32_16x16x4_F32 instruction --- .../Codegen/Dialect/GPU/IR/IREEGPUAttrs.cpp | 38 +++++++++++++++++++ .../Codegen/Dialect/GPU/IR/IREEGPUEnums.td | 14 ++++--- .../Dialect/GPU/TargetUtils/KnownTargets.cpp | 5 +-- tests/e2e/matmul/CMakeLists.txt | 28 ++++++++++++++ tests/e2e/matmul/generate_e2e_matmul_tests.py | 5 +++ 5 files changed, 81 insertions(+), 9 deletions(-) diff --git a/compiler/src/iree/compiler/Codegen/Dialect/GPU/IR/IREEGPUAttrs.cpp b/compiler/src/iree/compiler/Codegen/Dialect/GPU/IR/IREEGPUAttrs.cpp index cbca1009b1474..bb1fc14381cd0 100644 --- a/compiler/src/iree/compiler/Codegen/Dialect/GPU/IR/IREEGPUAttrs.cpp +++ b/compiler/src/iree/compiler/Codegen/Dialect/GPU/IR/IREEGPUAttrs.cpp @@ -210,6 +210,9 @@ static OpaqueMmaLayout getOpaqueMFMALayout(MLIRContext *context, Type i32 = IntegerType::get(context, 32); switch (type) { + case MMAIntrinsic::MFMA_F32_16x16x4_F32: { + return OpaqueMmaLayout{16, 16, 4, f32, f32, f32}; + } case MMAIntrinsic::MFMA_F16_16x16x16_F32: { return OpaqueMmaLayout{16, 16, 16, f16, f16, f32}; } @@ -251,6 +254,23 @@ static ConcreteMmaLayout getConcreteMFMALayout(MLIRContext *context, LayoutDimensionAttr::get(context, LayoutDimension::VECTORZ); (void)laneZ, (void)vectorZ; switch (type) { + case MMAIntrinsic::MFMA_F32_16x16x4_F32: { + // #outer = #iree_vector_ext.per_dim_layout<[LANEX], [16]> + // #inner = #iree_vector_ext.per_dim_layout<[LANEY, VECTORX], [4, 1]> + // #layout_a = #iree_vector_ext.layout<#outer, #inner> + // #layout_b = #iree_vector_ext.layout<#inner, #outer> + + auto outer = PerDimLayoutAttr::get(context, {laneX}, {16}); + auto inner = PerDimLayoutAttr::get(context, {laneY, vectorX}, {4, 1}); + auto aMLayout = outer; + auto aKLayout = inner; + auto bKLayout = inner; + auto bNLayout = outer; + auto cMLayout = PerDimLayoutAttr::get(context, {laneY, vectorX}, {4, 4}); + auto cNLayout = outer; + return ConcreteMmaLayout{opaqueLayout, aMLayout, aKLayout, bKLayout, + bNLayout, cMLayout, cNLayout}; + } case MMAIntrinsic::MFMA_F16_16x16x16_F32: { // #outer = #iree_vector_ext.per_dim_layout<[LANEX], [16]> // #inner = #iree_vector_ext.per_dim_layout<[LANEY, VECTORX], [4, 4]> @@ -404,6 +424,12 @@ MMAAttr::getABCVectorTypes() const { // amd_matrix_instruction_calculator tells us about the number of 32-bit // registers. So need to adjust accordingly. All vectors should be 1-D. switch (getIntrinsic().getValue()) { + case MMAIntrinsic::MFMA_F32_16x16x4_F32: { + auto aType = VectorType::get({4}, getAType()); + auto bType = VectorType::get({4}, getBType()); + auto cType = VectorType::get({16}, getCType()); + return std::make_tuple(aType, bType, cType); + } case MMAIntrinsic::MFMA_F16_16x16x16_F32: { auto aType = VectorType::get({4}, getAType()); auto bType = VectorType::get({4}, getBType()); @@ -450,6 +476,7 @@ MMAAttr::getContractionLayout(vector::ContractionOp contract) const { int64_t MMAAttr::getBlockSize() const { switch (getIntrinsic().getValue()) { + case MMAIntrinsic::MFMA_F32_16x16x4_F32: case MMAIntrinsic::MFMA_F16_16x16x16_F32: case MMAIntrinsic::MFMA_F16_32x32x8_F32: case MMAIntrinsic::MFMA_I8_16x16x32_I32: @@ -465,6 +492,7 @@ int64_t MMAAttr::getBlockSize() const { int64_t MMAAttr::getSubgroupSize() const { switch (getIntrinsic().getValue()) { + case MMAIntrinsic::MFMA_F32_16x16x4_F32: case MMAIntrinsic::MFMA_F16_16x16x16_F32: case MMAIntrinsic::MFMA_F16_32x32x8_F32: case MMAIntrinsic::MFMA_I8_16x16x32_I32: @@ -482,6 +510,10 @@ int64_t MMAAttr::getSubgroupSize() const { MMAAttr::SingleSubgroupLayout MMAAttr::getASingleSubgroupLayout() const { switch (getIntrinsic().getValue()) { + case MMAIntrinsic::MFMA_F32_16x16x4_F32: { + return {/*outer=*/{1, 1}, /*thread=*/{16, 4}, /*strides=*/{1, 16}, + /*element=*/{1, 4}}; + } case MMAIntrinsic::MFMA_F16_16x16x16_F32: { return {/*outer=*/{1, 1}, /*thread=*/{16, 4}, /*strides=*/{1, 16}, /*element=*/{1, 4}}; @@ -509,6 +541,10 @@ MMAAttr::SingleSubgroupLayout MMAAttr::getASingleSubgroupLayout() const { MMAAttr::SingleSubgroupLayout MMAAttr::getBSingleSubgroupLayout() const { switch (getIntrinsic().getValue()) { + case MMAIntrinsic::MFMA_F32_16x16x4_F32: { + return {/*outer=*/{1, 1}, /*thread=*/{4, 16}, /*strides=*/{16, 1}, + /*element=*/{4, 1}}; + } case MMAIntrinsic::MFMA_F16_16x16x16_F32: { return {/*outer=*/{1, 1}, /*thread=*/{4, 16}, /*strides=*/{16, 1}, /*element=*/{4, 1}}; @@ -536,6 +572,7 @@ MMAAttr::SingleSubgroupLayout MMAAttr::getBSingleSubgroupLayout() const { MMAAttr::SingleSubgroupLayout MMAAttr::getCSingleSubgroupLayout() const { switch (getIntrinsic().getValue()) { + case MMAIntrinsic::MFMA_F32_16x16x4_F32: case MMAIntrinsic::MFMA_F16_16x16x16_F32: case MMAIntrinsic::MFMA_I8_16x16x32_I32: { return {/*outer=*/{1, 1}, /*thread=*/{4, 16}, /*strides=*/{16, 1}, @@ -571,6 +608,7 @@ FailureOr MMAAttr::buildMmaOperation(OpBuilder &builder, Location loc, return failure(); } switch (getIntrinsic().getValue()) { + case MMAIntrinsic::MFMA_F32_16x16x4_F32: case MMAIntrinsic::MFMA_F16_16x16x16_F32: case MMAIntrinsic::MFMA_F16_32x32x8_F32: case MMAIntrinsic::MFMA_I8_16x16x32_I32: diff --git a/compiler/src/iree/compiler/Codegen/Dialect/GPU/IR/IREEGPUEnums.td b/compiler/src/iree/compiler/Codegen/Dialect/GPU/IR/IREEGPUEnums.td index 0423c2f6e9fa2..6633ead21c75d 100644 --- a/compiler/src/iree/compiler/Codegen/Dialect/GPU/IR/IREEGPUEnums.td +++ b/compiler/src/iree/compiler/Codegen/Dialect/GPU/IR/IREEGPUEnums.td @@ -99,16 +99,18 @@ class IREEGPU_I32MmaEnumAttr } // Format: __xx_ -def MFMA_F16_16x16x16_F32 : I32EnumAttrCase<"MFMA_F16_16x16x16_F32", 0>; -def MFMA_F16_32x32x8_F32 : I32EnumAttrCase<"MFMA_F16_32x32x8_F32", 1>; -def MFMA_I8_16x16x32_I32 : I32EnumAttrCase<"MFMA_I8_16x16x32_I32", 2>; -def MFMA_I8_32x32x16_I32 : I32EnumAttrCase<"MFMA_I8_32x32x16_I32", 3>; +def MFMA_F32_16x16x4_F32 : I32EnumAttrCase<"MFMA_F32_16x16x4_F32", 0>; +def MFMA_F16_16x16x16_F32 : I32EnumAttrCase<"MFMA_F16_16x16x16_F32", 1>; +def MFMA_F16_32x32x8_F32 : I32EnumAttrCase<"MFMA_F16_32x32x8_F32", 2>; +def MFMA_I8_16x16x32_I32 : I32EnumAttrCase<"MFMA_I8_16x16x32_I32", 3>; +def MFMA_I8_32x32x16_I32 : I32EnumAttrCase<"MFMA_I8_32x32x16_I32", 4>; // TODO: Create separate WMMA ops for AMD and NVIDIA GPUs -def WMMA_F16_16x16x16_F32 : I32EnumAttrCase<"WMMA_F16_16x16x16_F32", 4>; -def WMMA_F16_16x16x16_F16 : I32EnumAttrCase<"WMMA_F16_16x16x16_F16", 5>; +def WMMA_F16_16x16x16_F32 : I32EnumAttrCase<"WMMA_F16_16x16x16_F32", 5>; +def WMMA_F16_16x16x16_F16 : I32EnumAttrCase<"WMMA_F16_16x16x16_F16", 6>; def IREEGPU_MMAIntrinsic : IREEGPU_I32MmaEnumAttr<"MMAIntrinsic", "Descriptor for different MMA intrinsics", [ + MFMA_F32_16x16x4_F32, MFMA_F16_16x16x16_F32, MFMA_F16_32x32x8_F32, MFMA_I8_16x16x32_I32, diff --git a/compiler/src/iree/compiler/Codegen/Dialect/GPU/TargetUtils/KnownTargets.cpp b/compiler/src/iree/compiler/Codegen/Dialect/GPU/TargetUtils/KnownTargets.cpp index 993963c739df5..af9adcac00858 100644 --- a/compiler/src/iree/compiler/Codegen/Dialect/GPU/TargetUtils/KnownTargets.cpp +++ b/compiler/src/iree/compiler/Codegen/Dialect/GPU/TargetUtils/KnownTargets.cpp @@ -122,9 +122,8 @@ TargetAttr createTargetAttr(const TargetDetails &details, StringRef arch, const WgpDetails *getCDNA3WgpDetails() { static const MMAIntrinsic cdna3MMAOps[] = { - MMAIntrinsic::MFMA_F16_16x16x16_F32, - MMAIntrinsic::MFMA_F16_32x32x8_F32, - MMAIntrinsic::MFMA_I8_16x16x32_I32, + MMAIntrinsic::MFMA_F32_16x16x4_F32, MMAIntrinsic::MFMA_F16_16x16x16_F32, + MMAIntrinsic::MFMA_F16_32x32x8_F32, MMAIntrinsic::MFMA_I8_16x16x32_I32, MMAIntrinsic::MFMA_I8_32x32x16_I32, }; static const WgpDetails cdna3Wgp = { diff --git a/tests/e2e/matmul/CMakeLists.txt b/tests/e2e/matmul/CMakeLists.txt index 9347cc2734639..94157f1a7eaaf 100644 --- a/tests/e2e/matmul/CMakeLists.txt +++ b/tests/e2e/matmul/CMakeLists.txt @@ -2193,6 +2193,34 @@ iree_generated_e2e_runner_test( "requires-gpu-cdna3" ) +iree_generated_e2e_runner_test( + NAME + e2e_matmul_rocm_f32_large_cdna3_mfma + TEST_TYPE + matmul + GENERATOR + "generate_e2e_matmul_tests.py" + GENERATOR_ARGS + "--lhs_rhs_type=f32" + "--acc_type=f32" + "--shapes=gpu_large_aligned" + "--compilation_info=LLVMGPUVectorDistributeMFMA" + TEST_RUNNER + iree_tools_testing_e2e_iree-e2e-matmul-test + TARGET_BACKENDS + "rocm" + DRIVERS + "hip" + COMPILER_FLAGS + ${IREE_HIP_TEST_COMPILER_FLAGS} + LABELS + "noasan" + "nomsan" + "notsan" + "noubsan" + "requires-gpu-cdna3" +) + iree_generated_e2e_runner_test( NAME e2e_matmul_rocm_f16_large_cdna3_mfma_tb diff --git a/tests/e2e/matmul/generate_e2e_matmul_tests.py b/tests/e2e/matmul/generate_e2e_matmul_tests.py index 003f3de84e22a..462afd30e55fa 100644 --- a/tests/e2e/matmul/generate_e2e_matmul_tests.py +++ b/tests/e2e/matmul/generate_e2e_matmul_tests.py @@ -260,6 +260,7 @@ def get_rocm_test_compilation_infos( schedules = [] if intrinsic == "MFMA": schedules = [ + MMASchedule("MFMA_F32_16x16x4_F32", 1, 1, 1, 1, 1), MMASchedule("MFMA_F16_16x16x16_F32", 1, 1, 1, 1, 1), MMASchedule("MFMA_F16_16x16x16_F32", 1, 1, 1, 1, 2), MMASchedule("MFMA_F16_16x16x16_F32", 1, 1, 1, 2, 1), @@ -302,6 +303,10 @@ def get_rocm_test_compilation_infos( if lhs_rhs_type.value.upper() not in schedule.intrinsic: continue + if schedule.intrinsic == "MFMA_F32_16x16x4_F32": + wg_tile_m = schedule.m_count * schedule.m_tile_count * 16 + wg_tile_n = schedule.n_count * schedule.n_tile_count * 16 + wg_tile_k = schedule.k_tile_count * 4 if schedule.intrinsic == "MFMA_F16_16x16x16_F32": wg_tile_m = schedule.m_count * schedule.m_tile_count * 16 wg_tile_n = schedule.n_count * schedule.n_tile_count * 16