From 2f9fdbb63dc3c74d36635267176369b495362541 Mon Sep 17 00:00:00 2001 From: Li Zhijian Date: Wed, 16 Oct 2024 09:52:13 +0800 Subject: [PATCH] testing/cxl: Fix abused pci_bus_read_config_word() on platform device The cxl_region_shared_upstream_bandwidth_update() in clx_core works on PCI/PCIe CXL device only while cxl_test was implemeneted by platform device. Mock a cxl_region_shared_upstream_bandwidth_update() which does nothing for cxl_core so that the cxl_test goes well. Abuse cxl_region_shared_upstream_bandwidth_update() on platform device will cause a kernel panic with calltrace: platform cxl_host_bridge.3: host supports CXL (restricted) Oops: general protection fault, probably for non-canonical address 0x3ef17856fcae4fbd: 0000 [#1] PREEMPT SMP PTI CPU: 1 UID: 0 PID: 9167 Comm: cxl Kdump: loaded Tainted: G OE 6.12.0-rc3-master+ #66 Tainted: [O]=OOT_MODULE, [E]=UNSIGNED_MODULE Hardware name: LENOVO 90CXCTO1WW/, BIOS FCKT70AUS 04/23/2015 RIP: 0010:pci_bus_read_config_word+0x1c/0x60 Code: 90 90 90 90 90 90 90 90 90 90 90 90 90 90 0f 1f 44 00 00 53 b8 87 00 00 00 48 83 ec 08 c7 44 24 04 00 00 00 00 f6 c2 01 75 29 <48> 8b 87 c0 00 00 00 48 89 cb 4c 8d 44 24 04 b9 02 00 00 00 48 8b RSP: 0018:ffffa115034dfbb8 EFLAGS: 00010246 RAX: 0000000000000087 RBX: 0000000000000012 RCX: ffffa115034dfbfe RDX: 0000000000000016 RSI: 000000006f4e2f4e RDI: 3ef17856fcae4efd RBP: ffff8cc229121b48 R08: 0000000000000010 R09: 0000000000000000 R10: 0000000000000001 R11: ffff8cc225434360 R12: ffffa115034dfbfe R13: 0000000000000000 R14: ffff8cc2f119a080 R15: ffffa115034dfc50 FS: 00007f31d93537c0(0000) GS:ffff8cc510a80000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: 00007f31d95f3370 CR3: 00000001163ea001 CR4: 00000000001726f0 Call Trace: ? __die_body.cold+0x19/0x27 ? die_addr+0x38/0x60 ? exc_general_protection+0x1f5/0x4b0 ? asm_exc_general_protection+0x22/0x30 ? pci_bus_read_config_word+0x1c/0x60 pcie_capability_read_word+0x93/0xb0 pcie_link_speed_mbps+0x18/0x50 cxl_pci_get_bandwidth+0x18/0x60 [cxl_core] cxl_endpoint_gather_bandwidth.constprop.0+0xf4/0x230 [cxl_core] ? xas_store+0x54/0x660 ? preempt_count_add+0x69/0xa0 ? _raw_spin_lock+0x13/0x40 ? __kmalloc_cache_noprof+0xe7/0x270 cxl_region_shared_upstream_bandwidth_update+0x9c/0x790 [cxl_core] cxl_region_attach+0x520/0x7e0 [cxl_core] store_targetN+0xf2/0x120 [cxl_core] kernfs_fop_write_iter+0x13a/0x1f0 vfs_write+0x23b/0x410 ksys_write+0x53/0xd0 do_syscall_64+0x62/0x180 entry_SYSCALL_64_after_hwframe+0x76/0x7e And Ying also reported a KASAN error with similar calltrace. Reported-by: "Huang, Ying" Closes: https://lore.kernel.org/linux-cxl/87y12w9vp5.fsf@yhuang6-desk2.ccr.corp.intel.com/ Fixes: a5ab0de0ebaa ("cxl: Calculate region bandwidth of targets with shared upstream link") Signed-off-by: Li Zhijian --- tools/testing/cxl/Kbuild | 2 ++ tools/testing/cxl/mock_cdat.c | 8 ++++++++ 2 files changed, 10 insertions(+) create mode 100644 tools/testing/cxl/mock_cdat.c diff --git a/tools/testing/cxl/Kbuild b/tools/testing/cxl/Kbuild index b1256fee3567fc..ed9f50dee3f55a 100644 --- a/tools/testing/cxl/Kbuild +++ b/tools/testing/cxl/Kbuild @@ -15,6 +15,7 @@ ldflags-y += --wrap=devm_cxl_add_rch_dport ldflags-y += --wrap=cxl_rcd_component_reg_phys ldflags-y += --wrap=cxl_endpoint_parse_cdat ldflags-y += --wrap=cxl_dport_init_ras_reporting +ldflags-y += --wrap=cxl_region_shared_upstream_bandwidth_update DRIVERS := ../../../drivers CXL_SRC := $(DRIVERS)/cxl @@ -61,6 +62,7 @@ cxl_core-y += $(CXL_CORE_SRC)/pci.o cxl_core-y += $(CXL_CORE_SRC)/hdm.o cxl_core-y += $(CXL_CORE_SRC)/pmu.o cxl_core-y += $(CXL_CORE_SRC)/cdat.o +cxl_core-y += mock_cdat.o cxl_core-$(CONFIG_TRACING) += $(CXL_CORE_SRC)/trace.o cxl_core-$(CONFIG_CXL_REGION) += $(CXL_CORE_SRC)/region.o cxl_core-y += config_check.o diff --git a/tools/testing/cxl/mock_cdat.c b/tools/testing/cxl/mock_cdat.c new file mode 100644 index 00000000000000..99974153b3f68e --- /dev/null +++ b/tools/testing/cxl/mock_cdat.c @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Copyright (c) 2024 FUJITSU LIMITED. All rights reserved. */ + +#include + +void __wrap_cxl_region_shared_upstream_bandwidth_update(struct cxl_region *cxlr) +{ +}