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MokaExporter.fir
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;buildInfoPackage: chisel3, version: 3.2.4, scalaVersion: 2.12.10, sbtVersion: 1.3.2
circuit MokaExporter :
module RiscvCompressedDecoder :
input clock : Clock
input reset : Reset
output io : {flip instructionCompressed : UInt<32>, instructionDecompressed : UInt<32>}
wire fullInstruction : UInt<32> @[RiscvCompressedDecoder.scala 29:45]
node _T = bits(io.instructionCompressed, 1, 0) @[RiscvCompressedDecoder.scala 30:56]
node _T_1 = eq(_T, UInt<2>("h00")) @[RiscvCompressedDecoder.scala 35:17]
when _T_1 : @[RiscvCompressedDecoder.scala 35:31]
wire _T_2 : UInt<32> @[RiscvCompressedDecoder.scala 63:37]
node _T_3 = bits(io.instructionCompressed, 15, 13) @[RiscvCompressedDecoder.scala 64:32]
node _T_4 = bits(io.instructionCompressed, 10, 7) @[RiscvCompressedDecoder.scala 66:39]
node _T_5 = bits(io.instructionCompressed, 12, 11) @[RiscvCompressedDecoder.scala 66:54]
node _T_6 = bits(io.instructionCompressed, 5, 5) @[RiscvCompressedDecoder.scala 66:70]
node _T_7 = bits(io.instructionCompressed, 6, 6) @[RiscvCompressedDecoder.scala 66:81]
node _T_8 = cat(_T_7, UInt<2>("h00")) @[Cat.scala 29:58]
node _T_9 = cat(_T_4, _T_5) @[Cat.scala 29:58]
node _T_10 = cat(_T_9, _T_6) @[Cat.scala 29:58]
node _T_11 = cat(_T_10, _T_8) @[Cat.scala 29:58]
node _T_12 = bits(io.instructionCompressed, 6, 5) @[RiscvCompressedDecoder.scala 67:33]
node _T_13 = bits(io.instructionCompressed, 12, 10) @[RiscvCompressedDecoder.scala 67:47]
node _T_14 = cat(_T_12, _T_13) @[Cat.scala 29:58]
node _T_15 = cat(_T_14, UInt<3>("h00")) @[Cat.scala 29:58]
node _T_16 = bits(io.instructionCompressed, 5, 5) @[RiscvCompressedDecoder.scala 68:33]
node _T_17 = bits(io.instructionCompressed, 12, 10) @[RiscvCompressedDecoder.scala 68:44]
node _T_18 = bits(io.instructionCompressed, 6, 6) @[RiscvCompressedDecoder.scala 68:60]
node _T_19 = cat(_T_18, UInt<2>("h00")) @[Cat.scala 29:58]
node _T_20 = cat(_T_16, _T_17) @[Cat.scala 29:58]
node _T_21 = cat(_T_20, _T_19) @[Cat.scala 29:58]
node _T_22 = bits(io.instructionCompressed, 4, 2) @[RiscvCompressedDecoder.scala 70:45]
node _T_23 = cat(UInt<2>("h01"), _T_22) @[Cat.scala 29:58]
node _T_24 = bits(io.instructionCompressed, 9, 7) @[RiscvCompressedDecoder.scala 71:46]
node _T_25 = cat(UInt<2>("h01"), _T_24) @[Cat.scala 29:58]
node _T_26 = eq(_T_3, UInt<3>("h00")) @[RiscvCompressedDecoder.scala 74:19]
when _T_26 : @[RiscvCompressedDecoder.scala 74:33]
node _T_27 = bits(io.instructionCompressed, 12, 5) @[RiscvCompressedDecoder.scala 76:34]
node _T_28 = neq(_T_27, UInt<1>("h00")) @[RiscvCompressedDecoder.scala 76:42]
node _T_29 = mux(_T_28, UInt<7>("h013"), UInt<7>("h01f")) @[RiscvCompressedDecoder.scala 76:27]
node _T_30 = cat(_T_23, _T_29) @[Cat.scala 29:58]
node _T_31 = cat(_T_11, UInt<5>("h02")) @[Cat.scala 29:58]
node _T_32 = cat(_T_31, UInt<3>("h00")) @[Cat.scala 29:58]
node _T_33 = cat(_T_32, _T_30) @[Cat.scala 29:58]
_T_2 <= _T_33 @[RiscvCompressedDecoder.scala 81:23]
skip @[RiscvCompressedDecoder.scala 74:33]
else : @[RiscvCompressedDecoder.scala 83:39]
node _T_34 = eq(_T_3, UInt<3>("h01")) @[RiscvCompressedDecoder.scala 83:25]
when _T_34 : @[RiscvCompressedDecoder.scala 83:39]
node _T_35 = cat(_T_23, UInt<7>("h07")) @[Cat.scala 29:58]
node _T_36 = cat(_T_15, _T_25) @[Cat.scala 29:58]
node _T_37 = cat(_T_36, UInt<3>("h03")) @[Cat.scala 29:58]
node _T_38 = cat(_T_37, _T_35) @[Cat.scala 29:58]
_T_2 <= _T_38 @[RiscvCompressedDecoder.scala 87:23]
skip @[RiscvCompressedDecoder.scala 83:39]
else : @[RiscvCompressedDecoder.scala 89:39]
node _T_39 = eq(_T_3, UInt<3>("h02")) @[RiscvCompressedDecoder.scala 89:25]
when _T_39 : @[RiscvCompressedDecoder.scala 89:39]
node _T_40 = cat(_T_23, UInt<7>("h03")) @[Cat.scala 29:58]
node _T_41 = cat(_T_21, _T_25) @[Cat.scala 29:58]
node _T_42 = cat(_T_41, UInt<3>("h02")) @[Cat.scala 29:58]
node _T_43 = cat(_T_42, _T_40) @[Cat.scala 29:58]
_T_2 <= _T_43 @[RiscvCompressedDecoder.scala 93:23]
skip @[RiscvCompressedDecoder.scala 89:39]
else : @[RiscvCompressedDecoder.scala 95:39]
node _T_44 = eq(_T_3, UInt<3>("h03")) @[RiscvCompressedDecoder.scala 95:25]
when _T_44 : @[RiscvCompressedDecoder.scala 95:39]
node _T_45 = cat(_T_23, UInt<7>("h03")) @[Cat.scala 29:58]
node _T_46 = cat(_T_15, _T_25) @[Cat.scala 29:58]
node _T_47 = cat(_T_46, UInt<3>("h03")) @[Cat.scala 29:58]
node _T_48 = cat(_T_47, _T_45) @[Cat.scala 29:58]
_T_2 <= _T_48 @[RiscvCompressedDecoder.scala 99:23]
skip @[RiscvCompressedDecoder.scala 95:39]
else : @[RiscvCompressedDecoder.scala 101:39]
node _T_49 = eq(_T_3, UInt<3>("h04")) @[RiscvCompressedDecoder.scala 101:25]
when _T_49 : @[RiscvCompressedDecoder.scala 101:39]
_T_2 <= UInt<32>("h013") @[RiscvCompressedDecoder.scala 104:23]
skip @[RiscvCompressedDecoder.scala 101:39]
else : @[RiscvCompressedDecoder.scala 106:39]
node _T_50 = eq(_T_3, UInt<3>("h05")) @[RiscvCompressedDecoder.scala 106:25]
when _T_50 : @[RiscvCompressedDecoder.scala 106:39]
node _T_51 = shr(_T_15, 5) @[RiscvCompressedDecoder.scala 110:42]
node _T_52 = bits(_T_15, 4, 0) @[RiscvCompressedDecoder.scala 110:104]
node _T_53 = cat(UInt<3>("h03"), _T_52) @[Cat.scala 29:58]
node _T_54 = cat(_T_53, UInt<7>("h027")) @[Cat.scala 29:58]
node _T_55 = cat(_T_51, _T_23) @[Cat.scala 29:58]
node _T_56 = cat(_T_55, _T_25) @[Cat.scala 29:58]
node _T_57 = cat(_T_56, _T_54) @[Cat.scala 29:58]
_T_2 <= _T_57 @[RiscvCompressedDecoder.scala 110:23]
skip @[RiscvCompressedDecoder.scala 106:39]
else : @[RiscvCompressedDecoder.scala 112:39]
node _T_58 = eq(_T_3, UInt<3>("h06")) @[RiscvCompressedDecoder.scala 112:25]
when _T_58 : @[RiscvCompressedDecoder.scala 112:39]
node _T_59 = shr(_T_21, 5) @[RiscvCompressedDecoder.scala 116:42]
node _T_60 = bits(_T_21, 4, 0) @[RiscvCompressedDecoder.scala 116:104]
node _T_61 = cat(UInt<3>("h02"), _T_60) @[Cat.scala 29:58]
node _T_62 = cat(_T_61, UInt<7>("h023")) @[Cat.scala 29:58]
node _T_63 = cat(_T_59, _T_23) @[Cat.scala 29:58]
node _T_64 = cat(_T_63, _T_25) @[Cat.scala 29:58]
node _T_65 = cat(_T_64, _T_62) @[Cat.scala 29:58]
_T_2 <= _T_65 @[RiscvCompressedDecoder.scala 116:23]
skip @[RiscvCompressedDecoder.scala 112:39]
else : @[RiscvCompressedDecoder.scala 118:39]
node _T_66 = eq(_T_3, UInt<3>("h07")) @[RiscvCompressedDecoder.scala 118:25]
when _T_66 : @[RiscvCompressedDecoder.scala 118:39]
node _T_67 = shr(_T_21, 5) @[RiscvCompressedDecoder.scala 122:42]
node _T_68 = bits(_T_21, 4, 0) @[RiscvCompressedDecoder.scala 122:104]
node _T_69 = cat(UInt<3>("h03"), _T_68) @[Cat.scala 29:58]
node _T_70 = cat(_T_69, UInt<7>("h023")) @[Cat.scala 29:58]
node _T_71 = cat(_T_67, _T_23) @[Cat.scala 29:58]
node _T_72 = cat(_T_71, _T_25) @[Cat.scala 29:58]
node _T_73 = cat(_T_72, _T_70) @[Cat.scala 29:58]
_T_2 <= _T_73 @[RiscvCompressedDecoder.scala 122:23]
skip @[RiscvCompressedDecoder.scala 118:39]
else : @[RiscvCompressedDecoder.scala 124:17]
_T_2 <= UInt<32>("h013") @[RiscvCompressedDecoder.scala 127:23]
skip @[RiscvCompressedDecoder.scala 124:17]
fullInstruction <= _T_2 @[RiscvCompressedDecoder.scala 37:21]
skip @[RiscvCompressedDecoder.scala 35:31]
else : @[RiscvCompressedDecoder.scala 38:37]
node _T_74 = eq(_T, UInt<2>("h01")) @[RiscvCompressedDecoder.scala 38:23]
when _T_74 : @[RiscvCompressedDecoder.scala 38:37]
wire _T_75 : UInt<32> @[RiscvCompressedDecoder.scala 135:37]
node _T_76 = bits(io.instructionCompressed, 15, 13) @[RiscvCompressedDecoder.scala 136:32]
node _T_77 = bits(io.instructionCompressed, 12, 12) @[RiscvCompressedDecoder.scala 138:43]
node _T_78 = bits(_T_77, 0, 0) @[Bitwise.scala 71:15]
node _T_79 = mux(_T_78, UInt<7>("h07f"), UInt<7>("h00")) @[Bitwise.scala 71:12]
node _T_80 = bits(io.instructionCompressed, 6, 2) @[RiscvCompressedDecoder.scala 138:56]
node _T_81 = cat(_T_79, _T_80) @[Cat.scala 29:58]
node _T_82 = bits(io.instructionCompressed, 4, 2) @[RiscvCompressedDecoder.scala 140:45]
node _T_83 = cat(UInt<2>("h01"), _T_82) @[Cat.scala 29:58]
node _T_84 = bits(io.instructionCompressed, 9, 7) @[RiscvCompressedDecoder.scala 141:46]
node _T_85 = cat(UInt<2>("h01"), _T_84) @[Cat.scala 29:58]
node _T_86 = bits(io.instructionCompressed, 11, 7) @[RiscvCompressedDecoder.scala 142:37]
node _T_87 = eq(_T_76, UInt<3>("h00")) @[RiscvCompressedDecoder.scala 146:19]
when _T_87 : @[RiscvCompressedDecoder.scala 146:33]
node _T_88 = cat(_T_86, UInt<7>("h013")) @[Cat.scala 29:58]
node _T_89 = cat(_T_81, _T_86) @[Cat.scala 29:58]
node _T_90 = cat(_T_89, UInt<3>("h00")) @[Cat.scala 29:58]
node _T_91 = cat(_T_90, _T_88) @[Cat.scala 29:58]
_T_75 <= _T_91 @[RiscvCompressedDecoder.scala 150:23]
skip @[RiscvCompressedDecoder.scala 146:33]
else : @[RiscvCompressedDecoder.scala 152:39]
node _T_92 = eq(_T_76, UInt<3>("h01")) @[RiscvCompressedDecoder.scala 152:25]
when _T_92 : @[RiscvCompressedDecoder.scala 152:39]
node _T_93 = neq(_T_86, UInt<1>("h00")) @[RiscvCompressedDecoder.scala 154:48]
node _T_94 = mux(_T_93, UInt<7>("h01b"), UInt<7>("h01f")) @[RiscvCompressedDecoder.scala 154:27]
node _T_95 = cat(_T_86, _T_94) @[Cat.scala 29:58]
node _T_96 = cat(_T_81, _T_86) @[Cat.scala 29:58]
node _T_97 = cat(_T_96, UInt<3>("h00")) @[Cat.scala 29:58]
node _T_98 = cat(_T_97, _T_95) @[Cat.scala 29:58]
_T_75 <= _T_98 @[RiscvCompressedDecoder.scala 159:23]
skip @[RiscvCompressedDecoder.scala 152:39]
else : @[RiscvCompressedDecoder.scala 161:39]
node _T_99 = eq(_T_76, UInt<3>("h02")) @[RiscvCompressedDecoder.scala 161:25]
when _T_99 : @[RiscvCompressedDecoder.scala 161:39]
node _T_100 = cat(_T_86, UInt<7>("h013")) @[Cat.scala 29:58]
node _T_101 = cat(_T_81, UInt<5>("h00")) @[Cat.scala 29:58]
node _T_102 = cat(_T_101, UInt<3>("h00")) @[Cat.scala 29:58]
node _T_103 = cat(_T_102, _T_100) @[Cat.scala 29:58]
_T_75 <= _T_103 @[RiscvCompressedDecoder.scala 165:23]
skip @[RiscvCompressedDecoder.scala 161:39]
else : @[RiscvCompressedDecoder.scala 167:39]
node _T_104 = eq(_T_76, UInt<3>("h03")) @[RiscvCompressedDecoder.scala 167:25]
when _T_104 : @[RiscvCompressedDecoder.scala 167:39]
node _T_105 = neq(_T_81, UInt<1>("h00")) @[RiscvCompressedDecoder.scala 169:50]
node _T_106 = mux(_T_105, UInt<7>("h013"), UInt<7>("h01f")) @[RiscvCompressedDecoder.scala 169:35]
node _T_107 = neq(_T_81, UInt<1>("h00")) @[RiscvCompressedDecoder.scala 174:45]
node _T_108 = mux(_T_107, UInt<7>("h037"), UInt<7>("h03f")) @[RiscvCompressedDecoder.scala 174:30]
node _T_109 = bits(io.instructionCompressed, 12, 12) @[RiscvCompressedDecoder.scala 178:45]
node _T_110 = bits(_T_109, 0, 0) @[Bitwise.scala 71:15]
node _T_111 = mux(_T_110, UInt<15>("h07fff"), UInt<15>("h00")) @[Bitwise.scala 71:12]
node _T_112 = bits(io.instructionCompressed, 6, 2) @[RiscvCompressedDecoder.scala 178:58]
node _T_113 = cat(_T_111, _T_112) @[Cat.scala 29:58]
node _T_114 = eq(_T_86, UInt<5>("h00")) @[RiscvCompressedDecoder.scala 179:50]
node _T_115 = eq(_T_86, UInt<5>("h02")) @[RiscvCompressedDecoder.scala 179:90]
node _T_116 = or(_T_114, _T_115) @[RiscvCompressedDecoder.scala 179:67]
node _T_117 = cat(_T_86, _T_106) @[Cat.scala 29:58]
node _T_118 = cat(_T_81, _T_86) @[Cat.scala 29:58]
node _T_119 = cat(_T_118, UInt<3>("h00")) @[Cat.scala 29:58]
node _T_120 = cat(_T_119, _T_117) @[Cat.scala 29:58]
node _T_121 = cat(_T_113, _T_86) @[Cat.scala 29:58]
node _T_122 = cat(_T_121, _T_108) @[Cat.scala 29:58]
node _T_123 = mux(_T_116, _T_120, _T_122) @[RiscvCompressedDecoder.scala 179:29]
_T_75 <= _T_123 @[RiscvCompressedDecoder.scala 179:23]
skip @[RiscvCompressedDecoder.scala 167:39]
else : @[RiscvCompressedDecoder.scala 184:39]
node _T_124 = eq(_T_76, UInt<3>("h04")) @[RiscvCompressedDecoder.scala 184:25]
when _T_124 : @[RiscvCompressedDecoder.scala 184:39]
wire _T_125 : UInt<32> @[RiscvCompressedDecoder.scala 186:43]
node _T_126 = bits(io.instructionCompressed, 11, 10) @[RiscvCompressedDecoder.scala 187:40]
node _T_127 = bits(io.instructionCompressed, 12, 12) @[RiscvCompressedDecoder.scala 188:43]
node _T_128 = bits(io.instructionCompressed, 6, 2) @[RiscvCompressedDecoder.scala 188:55]
node _T_129 = cat(_T_127, _T_128) @[Cat.scala 29:58]
node _T_130 = eq(_T_126, UInt<2>("h00")) @[RiscvCompressedDecoder.scala 189:27]
when _T_130 : @[RiscvCompressedDecoder.scala 189:41]
node _T_131 = cat(_T_85, UInt<7>("h013")) @[Cat.scala 29:58]
node _T_132 = cat(_T_129, _T_85) @[Cat.scala 29:58]
node _T_133 = cat(_T_132, UInt<3>("h05")) @[Cat.scala 29:58]
node _T_134 = cat(_T_133, _T_131) @[Cat.scala 29:58]
_T_125 <= _T_134 @[RiscvCompressedDecoder.scala 191:29]
skip @[RiscvCompressedDecoder.scala 189:41]
else : @[RiscvCompressedDecoder.scala 192:47]
node _T_135 = eq(_T_126, UInt<2>("h01")) @[RiscvCompressedDecoder.scala 192:33]
when _T_135 : @[RiscvCompressedDecoder.scala 192:47]
node _T_136 = cat(_T_85, UInt<7>("h013")) @[Cat.scala 29:58]
node _T_137 = cat(_T_129, _T_85) @[Cat.scala 29:58]
node _T_138 = cat(_T_137, UInt<3>("h05")) @[Cat.scala 29:58]
node _T_139 = cat(_T_138, _T_136) @[Cat.scala 29:58]
node _T_140 = or(UInt<32>("h040000000"), _T_139) @[RiscvCompressedDecoder.scala 194:50]
_T_125 <= _T_140 @[RiscvCompressedDecoder.scala 194:29]
skip @[RiscvCompressedDecoder.scala 192:47]
else : @[RiscvCompressedDecoder.scala 195:47]
node _T_141 = eq(_T_126, UInt<2>("h02")) @[RiscvCompressedDecoder.scala 195:33]
when _T_141 : @[RiscvCompressedDecoder.scala 195:47]
node _T_142 = cat(_T_85, UInt<7>("h013")) @[Cat.scala 29:58]
node _T_143 = cat(_T_129, _T_85) @[Cat.scala 29:58]
node _T_144 = cat(_T_143, UInt<3>("h07")) @[Cat.scala 29:58]
node _T_145 = cat(_T_144, _T_142) @[Cat.scala 29:58]
_T_125 <= _T_145 @[RiscvCompressedDecoder.scala 197:29]
skip @[RiscvCompressedDecoder.scala 195:47]
else : @[RiscvCompressedDecoder.scala 198:47]
node _T_146 = eq(_T_126, UInt<2>("h03")) @[RiscvCompressedDecoder.scala 198:33]
when _T_146 : @[RiscvCompressedDecoder.scala 198:47]
wire _T_147 : UInt<32> @[RiscvCompressedDecoder.scala 200:48]
node _T_148 = bits(io.instructionCompressed, 12, 12) @[RiscvCompressedDecoder.scala 201:46]
node _T_149 = bits(io.instructionCompressed, 6, 5) @[RiscvCompressedDecoder.scala 201:58]
node _T_150 = cat(_T_148, _T_149) @[Cat.scala 29:58]
node _T_151 = eq(_T_150, UInt<3>("h00")) @[RiscvCompressedDecoder.scala 202:29]
when _T_151 : @[RiscvCompressedDecoder.scala 202:43]
node _T_152 = cat(_T_85, UInt<7>("h033")) @[Cat.scala 29:58]
node _T_153 = cat(_T_83, _T_85) @[Cat.scala 29:58]
node _T_154 = cat(_T_153, UInt<3>("h00")) @[Cat.scala 29:58]
node _T_155 = cat(_T_154, _T_152) @[Cat.scala 29:58]
node _T_156 = or(UInt<32>("h040000000"), _T_155) @[RiscvCompressedDecoder.scala 204:55]
_T_147 <= _T_156 @[RiscvCompressedDecoder.scala 204:34]
skip @[RiscvCompressedDecoder.scala 202:43]
else : @[RiscvCompressedDecoder.scala 205:49]
node _T_157 = eq(_T_150, UInt<3>("h01")) @[RiscvCompressedDecoder.scala 205:35]
when _T_157 : @[RiscvCompressedDecoder.scala 205:49]
node _T_158 = cat(_T_85, UInt<7>("h033")) @[Cat.scala 29:58]
node _T_159 = cat(_T_83, _T_85) @[Cat.scala 29:58]
node _T_160 = cat(_T_159, UInt<3>("h04")) @[Cat.scala 29:58]
node _T_161 = cat(_T_160, _T_158) @[Cat.scala 29:58]
_T_147 <= _T_161 @[RiscvCompressedDecoder.scala 207:34]
skip @[RiscvCompressedDecoder.scala 205:49]
else : @[RiscvCompressedDecoder.scala 208:49]
node _T_162 = eq(_T_150, UInt<3>("h02")) @[RiscvCompressedDecoder.scala 208:35]
when _T_162 : @[RiscvCompressedDecoder.scala 208:49]
node _T_163 = cat(_T_85, UInt<7>("h033")) @[Cat.scala 29:58]
node _T_164 = cat(_T_83, _T_85) @[Cat.scala 29:58]
node _T_165 = cat(_T_164, UInt<3>("h06")) @[Cat.scala 29:58]
node _T_166 = cat(_T_165, _T_163) @[Cat.scala 29:58]
_T_147 <= _T_166 @[RiscvCompressedDecoder.scala 210:34]
skip @[RiscvCompressedDecoder.scala 208:49]
else : @[RiscvCompressedDecoder.scala 211:49]
node _T_167 = eq(_T_150, UInt<3>("h03")) @[RiscvCompressedDecoder.scala 211:35]
when _T_167 : @[RiscvCompressedDecoder.scala 211:49]
node _T_168 = cat(_T_85, UInt<7>("h033")) @[Cat.scala 29:58]
node _T_169 = cat(_T_83, _T_85) @[Cat.scala 29:58]
node _T_170 = cat(_T_169, UInt<3>("h07")) @[Cat.scala 29:58]
node _T_171 = cat(_T_170, _T_168) @[Cat.scala 29:58]
_T_147 <= _T_171 @[RiscvCompressedDecoder.scala 213:34]
skip @[RiscvCompressedDecoder.scala 211:49]
else : @[RiscvCompressedDecoder.scala 214:49]
node _T_172 = eq(_T_150, UInt<3>("h04")) @[RiscvCompressedDecoder.scala 214:35]
when _T_172 : @[RiscvCompressedDecoder.scala 214:49]
node _T_173 = cat(_T_85, UInt<7>("h03b")) @[Cat.scala 29:58]
node _T_174 = cat(_T_83, _T_85) @[Cat.scala 29:58]
node _T_175 = cat(_T_174, UInt<3>("h00")) @[Cat.scala 29:58]
node _T_176 = cat(_T_175, _T_173) @[Cat.scala 29:58]
node _T_177 = or(UInt<32>("h040000000"), _T_176) @[RiscvCompressedDecoder.scala 216:55]
_T_147 <= _T_177 @[RiscvCompressedDecoder.scala 216:34]
skip @[RiscvCompressedDecoder.scala 214:49]
else : @[RiscvCompressedDecoder.scala 217:49]
node _T_178 = eq(_T_150, UInt<3>("h05")) @[RiscvCompressedDecoder.scala 217:35]
when _T_178 : @[RiscvCompressedDecoder.scala 217:49]
node _T_179 = cat(_T_85, UInt<7>("h03b")) @[Cat.scala 29:58]
node _T_180 = cat(_T_83, _T_85) @[Cat.scala 29:58]
node _T_181 = cat(_T_180, UInt<3>("h00")) @[Cat.scala 29:58]
node _T_182 = cat(_T_181, _T_179) @[Cat.scala 29:58]
_T_147 <= _T_182 @[RiscvCompressedDecoder.scala 219:34]
skip @[RiscvCompressedDecoder.scala 217:49]
else : @[RiscvCompressedDecoder.scala 220:49]
node _T_183 = eq(_T_150, UInt<3>("h06")) @[RiscvCompressedDecoder.scala 220:35]
when _T_183 : @[RiscvCompressedDecoder.scala 220:49]
_T_147 <= UInt<32>("h013") @[RiscvCompressedDecoder.scala 223:34]
skip @[RiscvCompressedDecoder.scala 220:49]
else : @[RiscvCompressedDecoder.scala 224:49]
node _T_184 = eq(_T_150, UInt<3>("h07")) @[RiscvCompressedDecoder.scala 224:35]
when _T_184 : @[RiscvCompressedDecoder.scala 224:49]
_T_147 <= UInt<32>("h013") @[RiscvCompressedDecoder.scala 227:34]
skip @[RiscvCompressedDecoder.scala 224:49]
else : @[RiscvCompressedDecoder.scala 228:21]
_T_147 <= UInt<32>("h013") @[RiscvCompressedDecoder.scala 231:34]
skip @[RiscvCompressedDecoder.scala 228:21]
_T_125 <= _T_147 @[RiscvCompressedDecoder.scala 233:29]
skip @[RiscvCompressedDecoder.scala 198:47]
else : @[RiscvCompressedDecoder.scala 234:19]
_T_125 <= UInt<32>("h013") @[RiscvCompressedDecoder.scala 237:29]
skip @[RiscvCompressedDecoder.scala 234:19]
_T_75 <= _T_125 @[RiscvCompressedDecoder.scala 239:23]
skip @[RiscvCompressedDecoder.scala 184:39]
else : @[RiscvCompressedDecoder.scala 241:39]
node _T_185 = eq(_T_76, UInt<3>("h05")) @[RiscvCompressedDecoder.scala 241:25]
when _T_185 : @[RiscvCompressedDecoder.scala 241:39]
node _T_186 = bits(io.instructionCompressed, 12, 12) @[RiscvCompressedDecoder.scala 243:46]
node _T_187 = bits(_T_186, 0, 0) @[Bitwise.scala 71:15]
node _T_188 = mux(_T_187, UInt<10>("h03ff"), UInt<10>("h00")) @[Bitwise.scala 71:12]
node _T_189 = bits(io.instructionCompressed, 8, 8) @[RiscvCompressedDecoder.scala 243:59]
node _T_190 = bits(io.instructionCompressed, 10, 9) @[RiscvCompressedDecoder.scala 243:70]
node _T_191 = bits(io.instructionCompressed, 6, 6) @[RiscvCompressedDecoder.scala 243:85]
node _T_192 = bits(io.instructionCompressed, 7, 7) @[RiscvCompressedDecoder.scala 243:96]
node _T_193 = bits(io.instructionCompressed, 2, 2) @[RiscvCompressedDecoder.scala 243:107]
node _T_194 = bits(io.instructionCompressed, 11, 11) @[RiscvCompressedDecoder.scala 243:118]
node _T_195 = bits(io.instructionCompressed, 5, 3) @[RiscvCompressedDecoder.scala 243:130]
node _T_196 = cat(_T_195, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_197 = cat(_T_193, _T_194) @[Cat.scala 29:58]
node _T_198 = cat(_T_197, _T_196) @[Cat.scala 29:58]
node _T_199 = cat(_T_191, _T_192) @[Cat.scala 29:58]
node _T_200 = cat(_T_188, _T_189) @[Cat.scala 29:58]
node _T_201 = cat(_T_200, _T_190) @[Cat.scala 29:58]
node _T_202 = cat(_T_201, _T_199) @[Cat.scala 29:58]
node _T_203 = cat(_T_202, _T_198) @[Cat.scala 29:58]
node _T_204 = bits(_T_203, 20, 20) @[RiscvCompressedDecoder.scala 245:43]
node _T_205 = bits(_T_203, 10, 1) @[RiscvCompressedDecoder.scala 245:62]
node _T_206 = bits(_T_203, 11, 11) @[RiscvCompressedDecoder.scala 245:84]
node _T_207 = bits(_T_203, 19, 12) @[RiscvCompressedDecoder.scala 245:103]
node _T_208 = cat(_T_207, UInt<5>("h00")) @[Cat.scala 29:58]
node _T_209 = cat(_T_208, UInt<7>("h06f")) @[Cat.scala 29:58]
node _T_210 = cat(_T_204, _T_205) @[Cat.scala 29:58]
node _T_211 = cat(_T_210, _T_206) @[Cat.scala 29:58]
node _T_212 = cat(_T_211, _T_209) @[Cat.scala 29:58]
_T_75 <= _T_212 @[RiscvCompressedDecoder.scala 245:23]
skip @[RiscvCompressedDecoder.scala 241:39]
else : @[RiscvCompressedDecoder.scala 247:39]
node _T_213 = eq(_T_76, UInt<3>("h06")) @[RiscvCompressedDecoder.scala 247:25]
when _T_213 : @[RiscvCompressedDecoder.scala 247:39]
node _T_214 = bits(io.instructionCompressed, 12, 12) @[RiscvCompressedDecoder.scala 249:47]
node _T_215 = bits(_T_214, 0, 0) @[Bitwise.scala 71:15]
node _T_216 = mux(_T_215, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 71:12]
node _T_217 = bits(io.instructionCompressed, 6, 5) @[RiscvCompressedDecoder.scala 249:60]
node _T_218 = bits(io.instructionCompressed, 2, 2) @[RiscvCompressedDecoder.scala 249:74]
node _T_219 = bits(io.instructionCompressed, 11, 10) @[RiscvCompressedDecoder.scala 249:85]
node _T_220 = bits(io.instructionCompressed, 4, 3) @[RiscvCompressedDecoder.scala 249:101]
node _T_221 = cat(_T_219, _T_220) @[Cat.scala 29:58]
node _T_222 = cat(_T_221, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_223 = cat(_T_216, _T_217) @[Cat.scala 29:58]
node _T_224 = cat(_T_223, _T_218) @[Cat.scala 29:58]
node _T_225 = cat(_T_224, _T_222) @[Cat.scala 29:58]
node _T_226 = bits(_T_225, 12, 12) @[RiscvCompressedDecoder.scala 252:45]
node _T_227 = bits(_T_225, 10, 5) @[RiscvCompressedDecoder.scala 252:66]
node _T_228 = bits(_T_225, 4, 1) @[RiscvCompressedDecoder.scala 252:134]
node _T_229 = bits(_T_225, 11, 11) @[RiscvCompressedDecoder.scala 252:157]
node _T_230 = cat(_T_229, UInt<7>("h063")) @[Cat.scala 29:58]
node _T_231 = cat(UInt<3>("h00"), _T_228) @[Cat.scala 29:58]
node _T_232 = cat(_T_231, _T_230) @[Cat.scala 29:58]
node _T_233 = cat(UInt<5>("h00"), _T_85) @[Cat.scala 29:58]
node _T_234 = cat(_T_226, _T_227) @[Cat.scala 29:58]
node _T_235 = cat(_T_234, _T_233) @[Cat.scala 29:58]
node _T_236 = cat(_T_235, _T_232) @[Cat.scala 29:58]
_T_75 <= _T_236 @[RiscvCompressedDecoder.scala 252:23]
skip @[RiscvCompressedDecoder.scala 247:39]
else : @[RiscvCompressedDecoder.scala 254:39]
node _T_237 = eq(_T_76, UInt<3>("h07")) @[RiscvCompressedDecoder.scala 254:25]
when _T_237 : @[RiscvCompressedDecoder.scala 254:39]
node _T_238 = bits(io.instructionCompressed, 12, 12) @[RiscvCompressedDecoder.scala 256:47]
node _T_239 = bits(_T_238, 0, 0) @[Bitwise.scala 71:15]
node _T_240 = mux(_T_239, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 71:12]
node _T_241 = bits(io.instructionCompressed, 6, 5) @[RiscvCompressedDecoder.scala 256:60]
node _T_242 = bits(io.instructionCompressed, 2, 2) @[RiscvCompressedDecoder.scala 256:74]
node _T_243 = bits(io.instructionCompressed, 11, 10) @[RiscvCompressedDecoder.scala 256:85]
node _T_244 = bits(io.instructionCompressed, 4, 3) @[RiscvCompressedDecoder.scala 256:101]
node _T_245 = cat(_T_243, _T_244) @[Cat.scala 29:58]
node _T_246 = cat(_T_245, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_247 = cat(_T_240, _T_241) @[Cat.scala 29:58]
node _T_248 = cat(_T_247, _T_242) @[Cat.scala 29:58]
node _T_249 = cat(_T_248, _T_246) @[Cat.scala 29:58]
node _T_250 = bits(_T_249, 12, 12) @[RiscvCompressedDecoder.scala 259:45]
node _T_251 = bits(_T_249, 10, 5) @[RiscvCompressedDecoder.scala 259:66]
node _T_252 = bits(_T_249, 4, 1) @[RiscvCompressedDecoder.scala 259:134]
node _T_253 = bits(_T_249, 11, 11) @[RiscvCompressedDecoder.scala 259:157]
node _T_254 = cat(_T_253, UInt<7>("h063")) @[Cat.scala 29:58]
node _T_255 = cat(UInt<3>("h01"), _T_252) @[Cat.scala 29:58]
node _T_256 = cat(_T_255, _T_254) @[Cat.scala 29:58]
node _T_257 = cat(UInt<5>("h00"), _T_85) @[Cat.scala 29:58]
node _T_258 = cat(_T_250, _T_251) @[Cat.scala 29:58]
node _T_259 = cat(_T_258, _T_257) @[Cat.scala 29:58]
node _T_260 = cat(_T_259, _T_256) @[Cat.scala 29:58]
_T_75 <= _T_260 @[RiscvCompressedDecoder.scala 259:23]
skip @[RiscvCompressedDecoder.scala 254:39]
else : @[RiscvCompressedDecoder.scala 261:17]
_T_75 <= UInt<32>("h013") @[RiscvCompressedDecoder.scala 264:23]
skip @[RiscvCompressedDecoder.scala 261:17]
fullInstruction <= _T_75 @[RiscvCompressedDecoder.scala 40:21]
skip @[RiscvCompressedDecoder.scala 38:37]
else : @[RiscvCompressedDecoder.scala 41:37]
node _T_261 = eq(_T, UInt<2>("h02")) @[RiscvCompressedDecoder.scala 41:23]
when _T_261 : @[RiscvCompressedDecoder.scala 41:37]
wire _T_262 : UInt<32> @[RiscvCompressedDecoder.scala 272:37]
node _T_263 = bits(io.instructionCompressed, 15, 13) @[RiscvCompressedDecoder.scala 273:32]
node _T_264 = bits(io.instructionCompressed, 6, 2) @[RiscvCompressedDecoder.scala 275:33]
node _T_265 = bits(io.instructionCompressed, 11, 7) @[RiscvCompressedDecoder.scala 276:34]
node _T_266 = eq(_T_263, UInt<3>("h00")) @[RiscvCompressedDecoder.scala 282:19]
when _T_266 : @[RiscvCompressedDecoder.scala 282:33]
node _T_267 = bits(io.instructionCompressed, 12, 12) @[RiscvCompressedDecoder.scala 286:35]
node _T_268 = bits(io.instructionCompressed, 6, 2) @[RiscvCompressedDecoder.scala 286:47]
node _T_269 = cat(_T_267, _T_268) @[Cat.scala 29:58]
node _T_270 = cat(_T_265, UInt<7>("h013")) @[Cat.scala 29:58]
node _T_271 = cat(_T_269, _T_265) @[Cat.scala 29:58]
node _T_272 = cat(_T_271, UInt<3>("h01")) @[Cat.scala 29:58]
node _T_273 = cat(_T_272, _T_270) @[Cat.scala 29:58]
_T_262 <= _T_273 @[RiscvCompressedDecoder.scala 287:23]
skip @[RiscvCompressedDecoder.scala 282:33]
else : @[RiscvCompressedDecoder.scala 289:39]
node _T_274 = eq(_T_263, UInt<3>("h01")) @[RiscvCompressedDecoder.scala 289:25]
when _T_274 : @[RiscvCompressedDecoder.scala 289:39]
node _T_275 = bits(io.instructionCompressed, 4, 2) @[RiscvCompressedDecoder.scala 293:33]
node _T_276 = bits(io.instructionCompressed, 12, 12) @[RiscvCompressedDecoder.scala 293:47]
node _T_277 = bits(io.instructionCompressed, 6, 5) @[RiscvCompressedDecoder.scala 293:59]
node _T_278 = cat(_T_277, UInt<3>("h00")) @[Cat.scala 29:58]
node _T_279 = cat(_T_275, _T_276) @[Cat.scala 29:58]
node _T_280 = cat(_T_279, _T_278) @[Cat.scala 29:58]
node _T_281 = cat(_T_265, UInt<7>("h07")) @[Cat.scala 29:58]
node _T_282 = cat(_T_280, UInt<5>("h02")) @[Cat.scala 29:58]
node _T_283 = cat(_T_282, UInt<3>("h03")) @[Cat.scala 29:58]
node _T_284 = cat(_T_283, _T_281) @[Cat.scala 29:58]
_T_262 <= _T_284 @[RiscvCompressedDecoder.scala 294:23]
skip @[RiscvCompressedDecoder.scala 289:39]
else : @[RiscvCompressedDecoder.scala 296:39]
node _T_285 = eq(_T_263, UInt<3>("h02")) @[RiscvCompressedDecoder.scala 296:25]
when _T_285 : @[RiscvCompressedDecoder.scala 296:39]
node _T_286 = neq(_T_265, UInt<1>("h00")) @[RiscvCompressedDecoder.scala 298:45]
node _T_287 = mux(_T_286, UInt<7>("h03"), UInt<7>("h01f")) @[RiscvCompressedDecoder.scala 298:27]
node _T_288 = bits(io.instructionCompressed, 3, 2) @[RiscvCompressedDecoder.scala 303:33]
node _T_289 = bits(io.instructionCompressed, 12, 12) @[RiscvCompressedDecoder.scala 303:47]
node _T_290 = bits(io.instructionCompressed, 6, 4) @[RiscvCompressedDecoder.scala 303:59]
node _T_291 = cat(_T_290, UInt<2>("h00")) @[Cat.scala 29:58]
node _T_292 = cat(_T_288, _T_289) @[Cat.scala 29:58]
node _T_293 = cat(_T_292, _T_291) @[Cat.scala 29:58]
node _T_294 = cat(_T_265, _T_287) @[Cat.scala 29:58]
node _T_295 = cat(_T_293, UInt<5>("h02")) @[Cat.scala 29:58]
node _T_296 = cat(_T_295, UInt<3>("h02")) @[Cat.scala 29:58]
node _T_297 = cat(_T_296, _T_294) @[Cat.scala 29:58]
_T_262 <= _T_297 @[RiscvCompressedDecoder.scala 304:23]
skip @[RiscvCompressedDecoder.scala 296:39]
else : @[RiscvCompressedDecoder.scala 306:39]
node _T_298 = eq(_T_263, UInt<3>("h03")) @[RiscvCompressedDecoder.scala 306:25]
when _T_298 : @[RiscvCompressedDecoder.scala 306:39]
node _T_299 = neq(_T_265, UInt<1>("h00")) @[RiscvCompressedDecoder.scala 308:45]
node _T_300 = mux(_T_299, UInt<7>("h03"), UInt<7>("h01f")) @[RiscvCompressedDecoder.scala 308:27]
node _T_301 = bits(io.instructionCompressed, 4, 2) @[RiscvCompressedDecoder.scala 313:33]
node _T_302 = bits(io.instructionCompressed, 12, 12) @[RiscvCompressedDecoder.scala 313:47]
node _T_303 = bits(io.instructionCompressed, 6, 5) @[RiscvCompressedDecoder.scala 313:59]
node _T_304 = cat(_T_303, UInt<3>("h00")) @[Cat.scala 29:58]
node _T_305 = cat(_T_301, _T_302) @[Cat.scala 29:58]
node _T_306 = cat(_T_305, _T_304) @[Cat.scala 29:58]
node _T_307 = cat(_T_265, _T_300) @[Cat.scala 29:58]
node _T_308 = cat(_T_306, UInt<5>("h02")) @[Cat.scala 29:58]
node _T_309 = cat(_T_308, UInt<3>("h03")) @[Cat.scala 29:58]
node _T_310 = cat(_T_309, _T_307) @[Cat.scala 29:58]
_T_262 <= _T_310 @[RiscvCompressedDecoder.scala 314:23]
skip @[RiscvCompressedDecoder.scala 306:39]
else : @[RiscvCompressedDecoder.scala 316:39]
node _T_311 = eq(_T_263, UInt<3>("h04")) @[RiscvCompressedDecoder.scala 316:25]
when _T_311 : @[RiscvCompressedDecoder.scala 316:39]
wire _T_312 : UInt<32> @[RiscvCompressedDecoder.scala 318:43]
node _T_313 = bits(io.instructionCompressed, 12, 12) @[RiscvCompressedDecoder.scala 319:35]
node _T_314 = eq(_T_313, UInt<1>("h00")) @[RiscvCompressedDecoder.scala 320:22]
when _T_314 : @[RiscvCompressedDecoder.scala 320:36]
node _T_315 = neq(_T_264, UInt<1>("h00")) @[RiscvCompressedDecoder.scala 322:52]
node _T_316 = cat(_T_265, UInt<7>("h033")) @[Cat.scala 29:58]
node _T_317 = cat(_T_264, UInt<5>("h00")) @[Cat.scala 29:58]
node _T_318 = cat(_T_317, UInt<3>("h00")) @[Cat.scala 29:58]
node _T_319 = cat(_T_318, _T_316) @[Cat.scala 29:58]
node _T_320 = neq(_T_265, UInt<1>("h00")) @[RiscvCompressedDecoder.scala 324:32]
node _T_321 = cat(UInt<5>("h00"), UInt<7>("h067")) @[Cat.scala 29:58]
node _T_322 = cat(_T_264, _T_265) @[Cat.scala 29:58]
node _T_323 = cat(_T_322, UInt<3>("h00")) @[Cat.scala 29:58]
node _T_324 = cat(_T_323, _T_321) @[Cat.scala 29:58]
node _T_325 = mux(_T_320, _T_324, UInt<32>("h013")) @[RiscvCompressedDecoder.scala 324:14]
node _T_326 = mux(_T_315, _T_319, _T_325) @[RiscvCompressedDecoder.scala 322:35]
_T_312 <= _T_326 @[RiscvCompressedDecoder.scala 322:29]
skip @[RiscvCompressedDecoder.scala 320:36]
else : @[RiscvCompressedDecoder.scala 329:42]
node _T_327 = eq(_T_313, UInt<1>("h01")) @[RiscvCompressedDecoder.scala 329:28]
when _T_327 : @[RiscvCompressedDecoder.scala 329:42]
node _T_328 = neq(_T_264, UInt<1>("h00")) @[RiscvCompressedDecoder.scala 331:52]
node _T_329 = cat(_T_265, UInt<7>("h033")) @[Cat.scala 29:58]
node _T_330 = cat(_T_264, _T_265) @[Cat.scala 29:58]
node _T_331 = cat(_T_330, UInt<3>("h00")) @[Cat.scala 29:58]
node _T_332 = cat(_T_331, _T_329) @[Cat.scala 29:58]
node _T_333 = neq(_T_265, UInt<1>("h00")) @[RiscvCompressedDecoder.scala 333:32]
node _T_334 = cat(UInt<5>("h01"), UInt<7>("h067")) @[Cat.scala 29:58]
node _T_335 = cat(_T_264, _T_265) @[Cat.scala 29:58]
node _T_336 = cat(_T_335, UInt<3>("h00")) @[Cat.scala 29:58]
node _T_337 = cat(_T_336, _T_334) @[Cat.scala 29:58]
node _T_338 = cat(UInt<5>("h00"), UInt<7>("h073")) @[Cat.scala 29:58]
node _T_339 = cat(_T_264, _T_265) @[Cat.scala 29:58]
node _T_340 = cat(_T_339, UInt<3>("h00")) @[Cat.scala 29:58]
node _T_341 = cat(_T_340, _T_338) @[Cat.scala 29:58]
node _T_342 = or(UInt<32>("h0100000"), _T_341) @[RiscvCompressedDecoder.scala 335:31]
node _T_343 = mux(_T_333, _T_337, _T_342) @[RiscvCompressedDecoder.scala 333:14]
node _T_344 = mux(_T_328, _T_332, _T_343) @[RiscvCompressedDecoder.scala 331:35]
_T_312 <= _T_344 @[RiscvCompressedDecoder.scala 331:29]
skip @[RiscvCompressedDecoder.scala 329:42]
else : @[RiscvCompressedDecoder.scala 338:19]
_T_312 <= UInt<32>("h013") @[RiscvCompressedDecoder.scala 341:29]
skip @[RiscvCompressedDecoder.scala 338:19]
_T_262 <= _T_312 @[RiscvCompressedDecoder.scala 343:23]
skip @[RiscvCompressedDecoder.scala 316:39]
else : @[RiscvCompressedDecoder.scala 345:39]
node _T_345 = eq(_T_263, UInt<3>("h05")) @[RiscvCompressedDecoder.scala 345:25]
when _T_345 : @[RiscvCompressedDecoder.scala 345:39]
node _T_346 = bits(io.instructionCompressed, 9, 7) @[RiscvCompressedDecoder.scala 349:33]
node _T_347 = bits(io.instructionCompressed, 12, 10) @[RiscvCompressedDecoder.scala 349:47]
node _T_348 = cat(_T_346, _T_347) @[Cat.scala 29:58]
node _T_349 = cat(_T_348, UInt<3>("h00")) @[Cat.scala 29:58]
node _T_350 = shr(_T_349, 5) @[RiscvCompressedDecoder.scala 350:40]
node _T_351 = bits(_T_349, 4, 0) @[RiscvCompressedDecoder.scala 350:98]
node _T_352 = cat(UInt<3>("h03"), _T_351) @[Cat.scala 29:58]
node _T_353 = cat(_T_352, UInt<7>("h027")) @[Cat.scala 29:58]
node _T_354 = cat(_T_350, _T_264) @[Cat.scala 29:58]
node _T_355 = cat(_T_354, UInt<5>("h02")) @[Cat.scala 29:58]
node _T_356 = cat(_T_355, _T_353) @[Cat.scala 29:58]
_T_262 <= _T_356 @[RiscvCompressedDecoder.scala 350:23]
skip @[RiscvCompressedDecoder.scala 345:39]
else : @[RiscvCompressedDecoder.scala 352:39]
node _T_357 = eq(_T_263, UInt<3>("h06")) @[RiscvCompressedDecoder.scala 352:25]
when _T_357 : @[RiscvCompressedDecoder.scala 352:39]
node _T_358 = bits(io.instructionCompressed, 8, 7) @[RiscvCompressedDecoder.scala 356:33]
node _T_359 = bits(io.instructionCompressed, 12, 9) @[RiscvCompressedDecoder.scala 356:47]
node _T_360 = cat(_T_358, _T_359) @[Cat.scala 29:58]
node _T_361 = cat(_T_360, UInt<2>("h00")) @[Cat.scala 29:58]
node _T_362 = shr(_T_361, 5) @[RiscvCompressedDecoder.scala 357:40]
node _T_363 = bits(_T_361, 4, 0) @[RiscvCompressedDecoder.scala 357:98]
node _T_364 = cat(UInt<3>("h02"), _T_363) @[Cat.scala 29:58]
node _T_365 = cat(_T_364, UInt<7>("h023")) @[Cat.scala 29:58]
node _T_366 = cat(_T_362, _T_264) @[Cat.scala 29:58]
node _T_367 = cat(_T_366, UInt<5>("h02")) @[Cat.scala 29:58]
node _T_368 = cat(_T_367, _T_365) @[Cat.scala 29:58]
_T_262 <= _T_368 @[RiscvCompressedDecoder.scala 357:23]
skip @[RiscvCompressedDecoder.scala 352:39]
else : @[RiscvCompressedDecoder.scala 359:39]
node _T_369 = eq(_T_263, UInt<3>("h07")) @[RiscvCompressedDecoder.scala 359:25]
when _T_369 : @[RiscvCompressedDecoder.scala 359:39]
node _T_370 = bits(io.instructionCompressed, 9, 7) @[RiscvCompressedDecoder.scala 363:33]
node _T_371 = bits(io.instructionCompressed, 12, 10) @[RiscvCompressedDecoder.scala 363:47]
node _T_372 = cat(_T_370, _T_371) @[Cat.scala 29:58]
node _T_373 = cat(_T_372, UInt<3>("h00")) @[Cat.scala 29:58]
node _T_374 = shr(_T_373, 5) @[RiscvCompressedDecoder.scala 364:40]
node _T_375 = bits(_T_373, 4, 0) @[RiscvCompressedDecoder.scala 364:98]
node _T_376 = cat(UInt<3>("h03"), _T_375) @[Cat.scala 29:58]
node _T_377 = cat(_T_376, UInt<7>("h023")) @[Cat.scala 29:58]
node _T_378 = cat(_T_374, _T_264) @[Cat.scala 29:58]
node _T_379 = cat(_T_378, UInt<5>("h02")) @[Cat.scala 29:58]
node _T_380 = cat(_T_379, _T_377) @[Cat.scala 29:58]
_T_262 <= _T_380 @[RiscvCompressedDecoder.scala 364:23]
skip @[RiscvCompressedDecoder.scala 359:39]
else : @[RiscvCompressedDecoder.scala 366:17]
_T_262 <= UInt<32>("h013") @[RiscvCompressedDecoder.scala 369:23]
skip @[RiscvCompressedDecoder.scala 366:17]
fullInstruction <= _T_262 @[RiscvCompressedDecoder.scala 43:21]
skip @[RiscvCompressedDecoder.scala 41:37]
else : @[RiscvCompressedDecoder.scala 44:15]
fullInstruction <= io.instructionCompressed @[RiscvCompressedDecoder.scala 46:21]
skip @[RiscvCompressedDecoder.scala 44:15]
io.instructionDecompressed <= fullInstruction @[RiscvCompressedDecoder.scala 51:30]
module MokaExporter :
input clock : Clock
input reset : UInt<1>
output io : {flip coreStateVector : {isValidInstruction : UInt<1>, isCompressedInstruction : UInt<1>, instruction : UInt<32>, programCounter : UInt<64>, isWritebackEnabled : UInt<1>, writebackDestinationRegister : UInt<5>, writebackData : UInt<64>}[1], isReducedStateVectorReady : UInt<1>, reducedStateVector : {isValidInstruction : UInt<1>, instruction : UInt<32>, programCounter : UInt<64>, isWritebackEnabled : UInt<1>, writebackDestinationRegister : UInt<5>, writebackData : UInt<64>}[4]}
reg isReadyRegister : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[MokaExporter.scala 20:38]
wire _T : {isValidInstruction : UInt<1>, instruction : UInt<32>, programCounter : UInt<64>, isWritebackEnabled : UInt<1>, writebackDestinationRegister : UInt<5>, writebackData : UInt<64>}[4] @[MokaExporter.scala 21:91]
_T[0].writebackData <= UInt<64>("h00") @[MokaExporter.scala 21:91]
_T[0].writebackDestinationRegister <= UInt<5>("h00") @[MokaExporter.scala 21:91]
_T[0].isWritebackEnabled <= UInt<1>("h00") @[MokaExporter.scala 21:91]
_T[0].programCounter <= UInt<64>("h00") @[MokaExporter.scala 21:91]
_T[0].instruction <= UInt<32>("h00") @[MokaExporter.scala 21:91]
_T[0].isValidInstruction <= UInt<1>("h00") @[MokaExporter.scala 21:91]
_T[1].writebackData <= UInt<64>("h00") @[MokaExporter.scala 21:91]
_T[1].writebackDestinationRegister <= UInt<5>("h00") @[MokaExporter.scala 21:91]
_T[1].isWritebackEnabled <= UInt<1>("h00") @[MokaExporter.scala 21:91]
_T[1].programCounter <= UInt<64>("h00") @[MokaExporter.scala 21:91]
_T[1].instruction <= UInt<32>("h00") @[MokaExporter.scala 21:91]
_T[1].isValidInstruction <= UInt<1>("h00") @[MokaExporter.scala 21:91]
_T[2].writebackData <= UInt<64>("h00") @[MokaExporter.scala 21:91]
_T[2].writebackDestinationRegister <= UInt<5>("h00") @[MokaExporter.scala 21:91]
_T[2].isWritebackEnabled <= UInt<1>("h00") @[MokaExporter.scala 21:91]
_T[2].programCounter <= UInt<64>("h00") @[MokaExporter.scala 21:91]
_T[2].instruction <= UInt<32>("h00") @[MokaExporter.scala 21:91]
_T[2].isValidInstruction <= UInt<1>("h00") @[MokaExporter.scala 21:91]
_T[3].writebackData <= UInt<64>("h00") @[MokaExporter.scala 21:91]
_T[3].writebackDestinationRegister <= UInt<5>("h00") @[MokaExporter.scala 21:91]
_T[3].isWritebackEnabled <= UInt<1>("h00") @[MokaExporter.scala 21:91]
_T[3].programCounter <= UInt<64>("h00") @[MokaExporter.scala 21:91]
_T[3].instruction <= UInt<32>("h00") @[MokaExporter.scala 21:91]
_T[3].isValidInstruction <= UInt<1>("h00") @[MokaExporter.scala 21:91]
reg reducedStateVectorOutputRegisterA : {isValidInstruction : UInt<1>, instruction : UInt<32>, programCounter : UInt<64>, isWritebackEnabled : UInt<1>, writebackDestinationRegister : UInt<5>, writebackData : UInt<64>}[4], clock with : (reset => (reset, _T)) @[MokaExporter.scala 21:78]
wire _T_1 : {isValidInstruction : UInt<1>, instruction : UInt<32>, programCounter : UInt<64>, isWritebackEnabled : UInt<1>, writebackDestinationRegister : UInt<5>, writebackData : UInt<64>}[4] @[MokaExporter.scala 24:91]
_T_1[0].writebackData <= UInt<64>("h00") @[MokaExporter.scala 24:91]
_T_1[0].writebackDestinationRegister <= UInt<5>("h00") @[MokaExporter.scala 24:91]
_T_1[0].isWritebackEnabled <= UInt<1>("h00") @[MokaExporter.scala 24:91]
_T_1[0].programCounter <= UInt<64>("h00") @[MokaExporter.scala 24:91]
_T_1[0].instruction <= UInt<32>("h00") @[MokaExporter.scala 24:91]
_T_1[0].isValidInstruction <= UInt<1>("h00") @[MokaExporter.scala 24:91]
_T_1[1].writebackData <= UInt<64>("h00") @[MokaExporter.scala 24:91]
_T_1[1].writebackDestinationRegister <= UInt<5>("h00") @[MokaExporter.scala 24:91]
_T_1[1].isWritebackEnabled <= UInt<1>("h00") @[MokaExporter.scala 24:91]
_T_1[1].programCounter <= UInt<64>("h00") @[MokaExporter.scala 24:91]
_T_1[1].instruction <= UInt<32>("h00") @[MokaExporter.scala 24:91]
_T_1[1].isValidInstruction <= UInt<1>("h00") @[MokaExporter.scala 24:91]
_T_1[2].writebackData <= UInt<64>("h00") @[MokaExporter.scala 24:91]
_T_1[2].writebackDestinationRegister <= UInt<5>("h00") @[MokaExporter.scala 24:91]
_T_1[2].isWritebackEnabled <= UInt<1>("h00") @[MokaExporter.scala 24:91]
_T_1[2].programCounter <= UInt<64>("h00") @[MokaExporter.scala 24:91]
_T_1[2].instruction <= UInt<32>("h00") @[MokaExporter.scala 24:91]
_T_1[2].isValidInstruction <= UInt<1>("h00") @[MokaExporter.scala 24:91]
_T_1[3].writebackData <= UInt<64>("h00") @[MokaExporter.scala 24:91]
_T_1[3].writebackDestinationRegister <= UInt<5>("h00") @[MokaExporter.scala 24:91]
_T_1[3].isWritebackEnabled <= UInt<1>("h00") @[MokaExporter.scala 24:91]
_T_1[3].programCounter <= UInt<64>("h00") @[MokaExporter.scala 24:91]
_T_1[3].instruction <= UInt<32>("h00") @[MokaExporter.scala 24:91]
_T_1[3].isValidInstruction <= UInt<1>("h00") @[MokaExporter.scala 24:91]
reg reducedStateVectorOutputRegisterB : {isValidInstruction : UInt<1>, instruction : UInt<32>, programCounter : UInt<64>, isWritebackEnabled : UInt<1>, writebackDestinationRegister : UInt<5>, writebackData : UInt<64>}[4], clock with : (reset => (reset, _T_1)) @[MokaExporter.scala 24:78]
reg isSelectVectorA : UInt<1>, clock with : (reset => (reset, UInt<1>("h01"))) @[MokaExporter.scala 28:38]
reg indexElement : UInt<4>, clock with : (reset => (reset, UInt<4>("h00"))) @[MokaExporter.scala 30:35]
node _T_2 = add(indexElement, UInt<4>("h01")) @[MokaExporter.scala 34:32]
node _T_3 = tail(_T_2, 1) @[MokaExporter.scala 34:32]
indexElement <= _T_3 @[MokaExporter.scala 34:16]
node _T_4 = sub(UInt<4>("h04"), UInt<4>("h01")) @[MokaExporter.scala 36:70]
node _T_5 = tail(_T_4, 1) @[MokaExporter.scala 36:70]
node _T_6 = eq(indexElement, _T_5) @[MokaExporter.scala 36:21]
when _T_6 : @[MokaExporter.scala 36:117]
indexElement <= UInt<4>("h00") @[MokaExporter.scala 37:18]
isReadyRegister <= UInt<1>("h01") @[MokaExporter.scala 38:21]
node _T_7 = eq(isSelectVectorA, UInt<1>("h00")) @[MokaExporter.scala 39:24]
isSelectVectorA <= _T_7 @[MokaExporter.scala 39:21]
skip @[MokaExporter.scala 36:117]
else : @[MokaExporter.scala 40:15]
isReadyRegister <= UInt<1>("h00") @[MokaExporter.scala 41:21]
isSelectVectorA <= isSelectVectorA @[MokaExporter.scala 42:21]
skip @[MokaExporter.scala 40:15]
node _T_8 = add(indexElement, UInt<4>("h00")) @[MokaExporter.scala 47:36]
node _T_9 = tail(_T_8, 1) @[MokaExporter.scala 47:36]
inst RiscvCompressedDecoder of RiscvCompressedDecoder @[MokaExporter.scala 49:34]
RiscvCompressedDecoder.clock <= clock
RiscvCompressedDecoder.reset <= reset
RiscvCompressedDecoder.io.instructionCompressed <= io.coreStateVector[0].instruction @[MokaExporter.scala 50:47]
when isSelectVectorA : @[MokaExporter.scala 53:27]
node _T_10 = bits(_T_9, 1, 0)
reducedStateVectorOutputRegisterA[_T_10].isValidInstruction <= io.coreStateVector[0].isValidInstruction @[MokaExporter.scala 54:73]
node _T_11 = bits(_T_9, 1, 0)
node _T_12 = mux(io.coreStateVector[0].isCompressedInstruction, RiscvCompressedDecoder.io.instructionDecompressed, io.coreStateVector[0].instruction) @[MokaExporter.scala 55:72]
reducedStateVectorOutputRegisterA[_T_11].instruction <= _T_12 @[MokaExporter.scala 55:66]
node _T_13 = bits(_T_9, 1, 0)
reducedStateVectorOutputRegisterA[_T_13].programCounter <= io.coreStateVector[0].programCounter @[MokaExporter.scala 59:69]
node _T_14 = bits(_T_9, 1, 0)
reducedStateVectorOutputRegisterA[_T_14].writebackData <= io.coreStateVector[0].writebackData @[MokaExporter.scala 60:68]
node _T_15 = bits(_T_9, 1, 0)
reducedStateVectorOutputRegisterA[_T_15].writebackDestinationRegister <= io.coreStateVector[UInt<1>("h00")].writebackDestinationRegister @[MokaExporter.scala 61:83]
node _T_16 = bits(_T_9, 1, 0)
reducedStateVectorOutputRegisterA[_T_16].isWritebackEnabled <= io.coreStateVector[0].isWritebackEnabled @[MokaExporter.scala 62:73]
skip @[MokaExporter.scala 53:27]
else : @[MokaExporter.scala 63:17]
node _T_17 = bits(_T_9, 1, 0)
reducedStateVectorOutputRegisterB[_T_17].isValidInstruction <= io.coreStateVector[0].isValidInstruction @[MokaExporter.scala 64:73]
node _T_18 = bits(_T_9, 1, 0)
node _T_19 = mux(io.coreStateVector[0].isCompressedInstruction, RiscvCompressedDecoder.io.instructionDecompressed, io.coreStateVector[0].instruction) @[MokaExporter.scala 65:72]
reducedStateVectorOutputRegisterB[_T_18].instruction <= _T_19 @[MokaExporter.scala 65:66]
node _T_20 = bits(_T_9, 1, 0)
reducedStateVectorOutputRegisterB[_T_20].programCounter <= io.coreStateVector[0].programCounter @[MokaExporter.scala 69:69]
node _T_21 = bits(_T_9, 1, 0)
reducedStateVectorOutputRegisterB[_T_21].writebackData <= io.coreStateVector[0].writebackData @[MokaExporter.scala 70:68]
node _T_22 = bits(_T_9, 1, 0)
reducedStateVectorOutputRegisterB[_T_22].writebackDestinationRegister <= io.coreStateVector[UInt<1>("h00")].writebackDestinationRegister @[MokaExporter.scala 71:83]
node _T_23 = bits(_T_9, 1, 0)
reducedStateVectorOutputRegisterB[_T_23].isWritebackEnabled <= io.coreStateVector[0].isWritebackEnabled @[MokaExporter.scala 72:73]
skip @[MokaExporter.scala 63:17]
io.isReducedStateVectorReady <= isReadyRegister @[MokaExporter.scala 79:32]
node _T_24 = eq(isSelectVectorA, UInt<1>("h00")) @[MokaExporter.scala 80:32]
node _T_25 = mux(_T_24, reducedStateVectorOutputRegisterA, reducedStateVectorOutputRegisterB) @[MokaExporter.scala 80:31]
io.reducedStateVector[0].writebackData <= _T_25[0].writebackData @[MokaExporter.scala 80:25]
io.reducedStateVector[0].writebackDestinationRegister <= _T_25[0].writebackDestinationRegister @[MokaExporter.scala 80:25]
io.reducedStateVector[0].isWritebackEnabled <= _T_25[0].isWritebackEnabled @[MokaExporter.scala 80:25]
io.reducedStateVector[0].programCounter <= _T_25[0].programCounter @[MokaExporter.scala 80:25]
io.reducedStateVector[0].instruction <= _T_25[0].instruction @[MokaExporter.scala 80:25]
io.reducedStateVector[0].isValidInstruction <= _T_25[0].isValidInstruction @[MokaExporter.scala 80:25]
io.reducedStateVector[1].writebackData <= _T_25[1].writebackData @[MokaExporter.scala 80:25]
io.reducedStateVector[1].writebackDestinationRegister <= _T_25[1].writebackDestinationRegister @[MokaExporter.scala 80:25]
io.reducedStateVector[1].isWritebackEnabled <= _T_25[1].isWritebackEnabled @[MokaExporter.scala 80:25]
io.reducedStateVector[1].programCounter <= _T_25[1].programCounter @[MokaExporter.scala 80:25]
io.reducedStateVector[1].instruction <= _T_25[1].instruction @[MokaExporter.scala 80:25]
io.reducedStateVector[1].isValidInstruction <= _T_25[1].isValidInstruction @[MokaExporter.scala 80:25]
io.reducedStateVector[2].writebackData <= _T_25[2].writebackData @[MokaExporter.scala 80:25]
io.reducedStateVector[2].writebackDestinationRegister <= _T_25[2].writebackDestinationRegister @[MokaExporter.scala 80:25]
io.reducedStateVector[2].isWritebackEnabled <= _T_25[2].isWritebackEnabled @[MokaExporter.scala 80:25]
io.reducedStateVector[2].programCounter <= _T_25[2].programCounter @[MokaExporter.scala 80:25]
io.reducedStateVector[2].instruction <= _T_25[2].instruction @[MokaExporter.scala 80:25]
io.reducedStateVector[2].isValidInstruction <= _T_25[2].isValidInstruction @[MokaExporter.scala 80:25]
io.reducedStateVector[3].writebackData <= _T_25[3].writebackData @[MokaExporter.scala 80:25]
io.reducedStateVector[3].writebackDestinationRegister <= _T_25[3].writebackDestinationRegister @[MokaExporter.scala 80:25]
io.reducedStateVector[3].isWritebackEnabled <= _T_25[3].isWritebackEnabled @[MokaExporter.scala 80:25]
io.reducedStateVector[3].programCounter <= _T_25[3].programCounter @[MokaExporter.scala 80:25]
io.reducedStateVector[3].instruction <= _T_25[3].instruction @[MokaExporter.scala 80:25]
io.reducedStateVector[3].isValidInstruction <= _T_25[3].isValidInstruction @[MokaExporter.scala 80:25]