diff --git a/Core/MIPS/IR/IRInterpreter.cpp b/Core/MIPS/IR/IRInterpreter.cpp
index 045b69f469f5..396ee84fd238 100644
--- a/Core/MIPS/IR/IRInterpreter.cpp
+++ b/Core/MIPS/IR/IRInterpreter.cpp
@@ -618,45 +618,45 @@ u32 IRInterpret(MIPSState *mips, const IRInst *inst, int count) {
 		case IROp::Mult:
 		{
 			s64 result = (s64)(s32)mips->r[inst->src1] * (s64)(s32)mips->r[inst->src2];
-			memcpy(&mips->lo, &result, 8);
+			memcpy(&mips->loHi, &result, 8);
 			break;
 		}
 		case IROp::MultU:
 		{
 			u64 result = (u64)mips->r[inst->src1] * (u64)mips->r[inst->src2];
-			memcpy(&mips->lo, &result, 8);
+			memcpy(&mips->loHi, &result, 8);
 			break;
 		}
 		case IROp::Madd:
 		{
 			s64 result;
-			memcpy(&result, &mips->lo, 8);
+			memcpy(&result, &mips->loHi, 8);
 			result += (s64)(s32)mips->r[inst->src1] * (s64)(s32)mips->r[inst->src2];
-			memcpy(&mips->lo, &result, 8);
+			memcpy(&mips->loHi, &result, 8);
 			break;
 		}
 		case IROp::MaddU:
 		{
 			s64 result;
-			memcpy(&result, &mips->lo, 8);
+			memcpy(&result, &mips->loHi, 8);
 			result += (u64)mips->r[inst->src1] * (u64)mips->r[inst->src2];
-			memcpy(&mips->lo, &result, 8);
+			memcpy(&mips->loHi, &result, 8);
 			break;
 		}
 		case IROp::Msub:
 		{
 			s64 result;
-			memcpy(&result, &mips->lo, 8);
+			memcpy(&result, &mips->loHi, 8);
 			result -= (s64)(s32)mips->r[inst->src1] * (s64)(s32)mips->r[inst->src2];
-			memcpy(&mips->lo, &result, 8);
+			memcpy(&mips->loHi, &result, 8);
 			break;
 		}
 		case IROp::MsubU:
 		{
 			s64 result;
-			memcpy(&result, &mips->lo, 8);
+			memcpy(&result, &mips->loHi, 8);
 			result -= (u64)mips->r[inst->src1] * (u64)mips->r[inst->src2];
-			memcpy(&mips->lo, &result, 8);
+			memcpy(&mips->loHi, &result, 8);
 			break;
 		}
 
diff --git a/Core/MIPS/MIPS.h b/Core/MIPS/MIPS.h
index 7d2c40e8797d..ebede36dc742 100644
--- a/Core/MIPS/MIPS.h
+++ b/Core/MIPS/MIPS.h
@@ -210,8 +210,20 @@ class MIPSState
 		struct {
 			u32 pc;   //241
 
-			u32 lo;   //242
-			u32 hi;   //243
+			union {
+#ifdef COMMON_LITTLE_ENDIAN
+				struct {
+					u32 lo;   //242
+					u32 hi;   //243
+				};
+#else
+				struct {
+					u32 hi;   //242
+					u32 lo;   //243
+				};
+#endif
+				u64 loHi;    //242
+			};
 
 			u32 fcr31; //244 fpu control register
 			u32 fpcond;  //245 cache the cond flag of fcr31  (& 1 << 23)
diff --git a/Core/MemMap.h b/Core/MemMap.h
index 5c41f1e68381..374706f2c0f4 100644
--- a/Core/MemMap.h
+++ b/Core/MemMap.h
@@ -189,9 +189,9 @@ inline u32 ReadUnchecked_U32(const u32 address) {
 
 inline float ReadUnchecked_Float(const u32 address) {
 #ifdef MASKED_PSP_MEMORY
-	return *(float *)(base + (address & MEMVIEW32_MASK));
+	return *(float_le *)(base + (address & MEMVIEW32_MASK));
 #else
-	return *(float *)(base + address);
+	return *(float_le *)(base + address);
 #endif
 }
 
@@ -221,9 +221,9 @@ inline void WriteUnchecked_U32(u32 data, u32 address) {
 
 inline void WriteUnchecked_Float(float data, u32 address) {
 #ifdef MASKED_PSP_MEMORY
-	*(float *)(base + (address & MEMVIEW32_MASK)) = data;
+	*(float_le *)(base + (address & MEMVIEW32_MASK)) = data;
 #else
-	*(float *)(base + address) = data;
+	*(float_le *)(base + address) = data;
 #endif
 }