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gpu-sim.cc
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gpu-sim.cc
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// Copyright (c) 2009-2011, Tor M. Aamodt, Wilson W.L. Fung, George L. Yuan,
// Ali Bakhoda, Andrew Turner, Ivan Sham
// The University of British Columbia
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// Redistributions of source code must retain the above copyright notice, this
// list of conditions and the following disclaimer.
// Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution. Neither the name of
// The University of British Columbia nor the names of its contributors may be
// used to endorse or promote products derived from this software without
// specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
#include "gpu-sim.h"
#include <math.h>
#include <signal.h>
#include <stdio.h>
#include <stdlib.h>
#include "zlib.h"
#include "dram.h"
#include "mem_fetch.h"
#include "shader.h"
#include "shader_trace.h"
#include <time.h>
#include "addrdec.h"
#include "delayqueue.h"
#include "dram.h"
#include "gpu-cache.h"
#include "gpu-misc.h"
#include "icnt_wrapper.h"
#include "l2cache.h"
#include "shader.h"
#include "stat-tool.h"
#include "../../libcuda/gpgpu_context.h"
#include "../abstract_hardware_model.h"
#include "../cuda-sim/cuda-sim.h"
#include "../cuda-sim/cuda_device_runtime.h"
#include "../cuda-sim/ptx-stats.h"
#include "../cuda-sim/ptx_ir.h"
#include "../debug.h"
#include "../gpgpusim_entrypoint.h"
#include "../statwrapper.h"
#include "../trace.h"
#include "mem_latency_stat.h"
#include "power_stat.h"
#include "stats.h"
#include "visualizer.h"
#ifdef GPGPUSIM_POWER_MODEL
#include "power_interface.h"
#else
class gpgpu_sim_wrapper {};
#endif
#include <stdio.h>
#include <string.h>
#include <iostream>
#include <sstream>
#include <string>
#define MAX(a, b) (((a) > (b)) ? (a) : (b))
bool g_interactive_debugger_enabled = false;
tr1_hash_map<new_addr_type, unsigned> address_random_interleaving;
/* Clock Domains */
#define CORE 0x01
#define L2 0x02
#define DRAM 0x04
#define ICNT 0x08
#define MEM_LATENCY_STAT_IMPL
#include "mem_latency_stat.h"
void power_config::reg_options(class OptionParser *opp) {
option_parser_register(opp, "-gpuwattch_xml_file", OPT_CSTR,
&g_power_config_name, "GPUWattch XML file",
"gpuwattch.xml");
option_parser_register(opp, "-power_simulation_enabled", OPT_BOOL,
&g_power_simulation_enabled,
"Turn on power simulator (1=On, 0=Off)", "0");
option_parser_register(opp, "-power_per_cycle_dump", OPT_BOOL,
&g_power_per_cycle_dump,
"Dump detailed power output each cycle", "0");
// Output Data Formats
option_parser_register(
opp, "-power_trace_enabled", OPT_BOOL, &g_power_trace_enabled,
"produce a file for the power trace (1=On, 0=Off)", "0");
option_parser_register(
opp, "-power_trace_zlevel", OPT_INT32, &g_power_trace_zlevel,
"Compression level of the power trace output log (0=no comp, 9=highest)",
"6");
option_parser_register(
opp, "-steady_power_levels_enabled", OPT_BOOL,
&g_steady_power_levels_enabled,
"produce a file for the steady power levels (1=On, 0=Off)", "0");
option_parser_register(opp, "-steady_state_definition", OPT_CSTR,
&gpu_steady_state_definition,
"allowed deviation:number of samples", "8:4");
}
void memory_config::reg_options(class OptionParser *opp) {
option_parser_register(opp, "-gpgpu_perf_sim_memcpy", OPT_BOOL,
&m_perf_sim_memcpy, "Fill the L2 cache on memcpy",
"1");
option_parser_register(opp, "-gpgpu_simple_dram_model", OPT_BOOL,
&simple_dram_model,
"simple_dram_model with fixed latency and BW", "0");
option_parser_register(opp, "-gpgpu_dram_scheduler", OPT_INT32,
&scheduler_type, "0 = fifo, 1 = FR-FCFS (defaul)",
"1");
option_parser_register(opp, "-gpgpu_dram_partition_queues", OPT_CSTR,
&gpgpu_L2_queue_config, "i2$:$2d:d2$:$2i", "8:8:8:8");
option_parser_register(opp, "-l2_ideal", OPT_BOOL, &l2_ideal,
"Use a ideal L2 cache that always hit", "0");
option_parser_register(opp, "-gpgpu_cache:dl2", OPT_CSTR,
&m_L2_config.m_config_string,
"unified banked L2 data cache config "
" {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_"
"alloc>,<mshr>:<N>:<merge>,<mq>}",
"64:128:8,L:B:m:N,A:16:4,4");
option_parser_register(opp, "-gpgpu_cache:dl2_texture_only", OPT_BOOL,
&m_L2_texure_only, "L2 cache used for texture only",
"1");
option_parser_register(
opp, "-gpgpu_n_mem", OPT_UINT32, &m_n_mem,
"number of memory modules (e.g. memory controllers) in gpu", "8");
option_parser_register(opp, "-gpgpu_n_sub_partition_per_mchannel", OPT_UINT32,
&m_n_sub_partition_per_memory_channel,
"number of memory subpartition in each memory module",
"1");
option_parser_register(opp, "-gpgpu_n_mem_per_ctrlr", OPT_UINT32,
&gpu_n_mem_per_ctrlr,
"number of memory chips per memory controller", "1");
option_parser_register(opp, "-gpgpu_memlatency_stat", OPT_INT32,
&gpgpu_memlatency_stat,
"track and display latency statistics 0x2 enables MC, "
"0x4 enables queue logs",
"0");
option_parser_register(opp, "-gpgpu_frfcfs_dram_sched_queue_size", OPT_INT32,
&gpgpu_frfcfs_dram_sched_queue_size,
"0 = unlimited (default); # entries per chip", "0");
option_parser_register(opp, "-gpgpu_dram_return_queue_size", OPT_INT32,
&gpgpu_dram_return_queue_size,
"0 = unlimited (default); # entries per chip", "0");
option_parser_register(opp, "-gpgpu_dram_buswidth", OPT_UINT32, &busW,
"default = 4 bytes (8 bytes per cycle at DDR)", "4");
option_parser_register(
opp, "-gpgpu_dram_burst_length", OPT_UINT32, &BL,
"Burst length of each DRAM request (default = 4 data bus cycle)", "4");
option_parser_register(opp, "-dram_data_command_freq_ratio", OPT_UINT32,
&data_command_freq_ratio,
"Frequency ratio between DRAM data bus and command "
"bus (default = 2 times, i.e. DDR)",
"2");
option_parser_register(
opp, "-gpgpu_dram_timing_opt", OPT_CSTR, &gpgpu_dram_timing_opt,
"DRAM timing parameters = "
"{nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR:nbkgrp:tCCDL:tRTPL}",
"4:2:8:12:21:13:34:9:4:5:13:1:0:0");
option_parser_register(opp, "-gpgpu_l2_rop_latency", OPT_UINT32, &rop_latency,
"ROP queue latency (default 85)", "85");
option_parser_register(opp, "-dram_latency", OPT_UINT32, &dram_latency,
"DRAM latency (default 30)", "30");
option_parser_register(opp, "-dram_dual_bus_interface", OPT_UINT32,
&dual_bus_interface,
"dual_bus_interface (default = 0) ", "0");
option_parser_register(opp, "-dram_bnk_indexing_policy", OPT_UINT32,
&dram_bnk_indexing_policy,
"dram_bnk_indexing_policy (0 = normal indexing, 1 = "
"Xoring with the higher bits) (Default = 0)",
"0");
option_parser_register(opp, "-dram_bnkgrp_indexing_policy", OPT_UINT32,
&dram_bnkgrp_indexing_policy,
"dram_bnkgrp_indexing_policy (0 = take higher bits, 1 "
"= take lower bits) (Default = 0)",
"0");
option_parser_register(opp, "-dram_seperate_write_queue_enable", OPT_BOOL,
&seperate_write_queue_enabled,
"Seperate_Write_Queue_Enable", "0");
option_parser_register(opp, "-dram_write_queue_size", OPT_CSTR,
&write_queue_size_opt, "Write_Queue_Size", "32:28:16");
option_parser_register(
opp, "-dram_elimnate_rw_turnaround", OPT_BOOL, &elimnate_rw_turnaround,
"elimnate_rw_turnaround i.e set tWTR and tRTW = 0", "0");
option_parser_register(opp, "-icnt_flit_size", OPT_UINT32, &icnt_flit_size,
"icnt_flit_size", "32");
m_address_mapping.addrdec_setoption(opp);
}
void shader_core_config::reg_options(class OptionParser *opp) {
option_parser_register(opp, "-gpgpu_simd_model", OPT_INT32, &model,
"1 = post-dominator", "1");
option_parser_register(
opp, "-gpgpu_shader_core_pipeline", OPT_CSTR,
&gpgpu_shader_core_pipeline_opt,
"shader core pipeline config, i.e., {<nthread>:<warpsize>}", "1024:32");
option_parser_register(opp, "-gpgpu_tex_cache:l1", OPT_CSTR,
&m_L1T_config.m_config_string,
"per-shader L1 texture cache (READ-ONLY) config "
" {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_"
"alloc>,<mshr>:<N>:<merge>,<mq>:<rf>}",
"8:128:5,L:R:m:N,F:128:4,128:2");
option_parser_register(
opp, "-gpgpu_const_cache:l1", OPT_CSTR, &m_L1C_config.m_config_string,
"per-shader L1 constant memory cache (READ-ONLY) config "
" {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<"
"merge>,<mq>} ",
"64:64:2,L:R:f:N,A:2:32,4");
option_parser_register(opp, "-gpgpu_cache:il1", OPT_CSTR,
&m_L1I_config.m_config_string,
"shader L1 instruction cache config "
" {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_"
"alloc>,<mshr>:<N>:<merge>,<mq>} ",
"4:256:4,L:R:f:N,A:2:32,4");
option_parser_register(opp, "-gpgpu_cache:dl1", OPT_CSTR,
&m_L1D_config.m_config_string,
"per-shader L1 data cache config "
" {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_"
"alloc>,<mshr>:<N>:<merge>,<mq> | none}",
"none");
option_parser_register(opp, "-gpgpu_l1_banks", OPT_UINT32,
&m_L1D_config.l1_banks, "The number of L1 cache banks",
"1");
option_parser_register(opp, "-gpgpu_l1_banks_byte_interleaving", OPT_UINT32,
&m_L1D_config.l1_banks_byte_interleaving,
"l1 banks byte interleaving granularity", "32");
option_parser_register(opp, "-gpgpu_l1_banks_hashing_function", OPT_UINT32,
&m_L1D_config.l1_banks_hashing_function,
"l1 banks hashing function", "0");
option_parser_register(opp, "-gpgpu_l1_latency", OPT_UINT32,
&m_L1D_config.l1_latency, "L1 Hit Latency", "1");
option_parser_register(opp, "-gpgpu_smem_latency", OPT_UINT32, &smem_latency,
"smem Latency", "3");
option_parser_register(opp, "-gpgpu_cache:dl1PrefL1", OPT_CSTR,
&m_L1D_config.m_config_stringPrefL1,
"per-shader L1 data cache config "
" {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_"
"alloc>,<mshr>:<N>:<merge>,<mq> | none}",
"none");
option_parser_register(opp, "-gpgpu_cache:dl1PrefShared", OPT_CSTR,
&m_L1D_config.m_config_stringPrefShared,
"per-shader L1 data cache config "
" {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_"
"alloc>,<mshr>:<N>:<merge>,<mq> | none}",
"none");
option_parser_register(opp, "-gpgpu_gmem_skip_L1D", OPT_BOOL, &gmem_skip_L1D,
"global memory access skip L1D cache (implements "
"-Xptxas -dlcm=cg, default=no skip)",
"0");
option_parser_register(opp, "-gpgpu_perfect_mem", OPT_BOOL,
&gpgpu_perfect_mem,
"enable perfect memory mode (no cache miss)", "0");
option_parser_register(
opp, "-n_regfile_gating_group", OPT_UINT32, &n_regfile_gating_group,
"group of lanes that should be read/written together)", "4");
option_parser_register(
opp, "-gpgpu_clock_gated_reg_file", OPT_BOOL, &gpgpu_clock_gated_reg_file,
"enable clock gated reg file for power calculations", "0");
option_parser_register(
opp, "-gpgpu_clock_gated_lanes", OPT_BOOL, &gpgpu_clock_gated_lanes,
"enable clock gated lanes for power calculations", "0");
option_parser_register(opp, "-gpgpu_shader_registers", OPT_UINT32,
&gpgpu_shader_registers,
"Number of registers per shader core. Limits number "
"of concurrent CTAs. (default 8192)",
"8192");
option_parser_register(
opp, "-gpgpu_registers_per_block", OPT_UINT32, &gpgpu_registers_per_block,
"Maximum number of registers per CTA. (default 8192)", "8192");
option_parser_register(opp, "-gpgpu_ignore_resources_limitation", OPT_BOOL,
&gpgpu_ignore_resources_limitation,
"gpgpu_ignore_resources_limitation (default 0)", "0");
option_parser_register(
opp, "-gpgpu_shader_cta", OPT_UINT32, &max_cta_per_core,
"Maximum number of concurrent CTAs in shader (default 8)", "8");
option_parser_register(
opp, "-gpgpu_num_cta_barriers", OPT_UINT32, &max_barriers_per_cta,
"Maximum number of named barriers per CTA (default 16)", "16");
option_parser_register(opp, "-gpgpu_n_clusters", OPT_UINT32, &n_simt_clusters,
"number of processing clusters", "10");
option_parser_register(opp, "-gpgpu_n_cores_per_cluster", OPT_UINT32,
&n_simt_cores_per_cluster,
"number of simd cores per cluster", "3");
option_parser_register(opp, "-gpgpu_n_cluster_ejection_buffer_size",
OPT_UINT32, &n_simt_ejection_buffer_size,
"number of packets in ejection buffer", "8");
option_parser_register(
opp, "-gpgpu_n_ldst_response_buffer_size", OPT_UINT32,
&ldst_unit_response_queue_size,
"number of response packets in ld/st unit ejection buffer", "2");
option_parser_register(
opp, "-gpgpu_shmem_per_block", OPT_UINT32, &gpgpu_shmem_per_block,
"Size of shared memory per thread block or CTA (default 48kB)", "49152");
option_parser_register(
opp, "-gpgpu_shmem_size", OPT_UINT32, &gpgpu_shmem_size,
"Size of shared memory per shader core (default 16kB)", "16384");
option_parser_register(opp, "-gpgpu_adaptive_cache_config", OPT_UINT32,
&adaptive_cache_config, "adaptive_cache_config", "0");
option_parser_register(
opp, "-gpgpu_shmem_sizeDefault", OPT_UINT32, &gpgpu_shmem_sizeDefault,
"Size of shared memory per shader core (default 16kB)", "16384");
option_parser_register(
opp, "-gpgpu_shmem_size_PrefL1", OPT_UINT32, &gpgpu_shmem_sizePrefL1,
"Size of shared memory per shader core (default 16kB)", "16384");
option_parser_register(opp, "-gpgpu_shmem_size_PrefShared", OPT_UINT32,
&gpgpu_shmem_sizePrefShared,
"Size of shared memory per shader core (default 16kB)",
"16384");
option_parser_register(
opp, "-gpgpu_shmem_num_banks", OPT_UINT32, &num_shmem_bank,
"Number of banks in the shared memory in each shader core (default 16)",
"16");
option_parser_register(
opp, "-gpgpu_shmem_limited_broadcast", OPT_BOOL, &shmem_limited_broadcast,
"Limit shared memory to do one broadcast per cycle (default on)", "1");
option_parser_register(opp, "-gpgpu_shmem_warp_parts", OPT_INT32,
&mem_warp_parts,
"Number of portions a warp is divided into for shared "
"memory bank conflict check ",
"2");
option_parser_register(
opp, "-gpgpu_mem_unit_ports", OPT_INT32, &mem_unit_ports,
"The number of memory transactions allowed per core cycle", "1");
option_parser_register(opp, "-gpgpu_shmem_warp_parts", OPT_INT32,
&mem_warp_parts,
"Number of portions a warp is divided into for shared "
"memory bank conflict check ",
"2");
option_parser_register(
opp, "-gpgpu_warpdistro_shader", OPT_INT32, &gpgpu_warpdistro_shader,
"Specify which shader core to collect the warp size distribution from",
"-1");
option_parser_register(
opp, "-gpgpu_warp_issue_shader", OPT_INT32, &gpgpu_warp_issue_shader,
"Specify which shader core to collect the warp issue distribution from",
"0");
option_parser_register(opp, "-gpgpu_local_mem_map", OPT_BOOL,
&gpgpu_local_mem_map,
"Mapping from local memory space address to simulated "
"GPU physical address space (default = enabled)",
"1");
option_parser_register(opp, "-gpgpu_num_reg_banks", OPT_INT32,
&gpgpu_num_reg_banks,
"Number of register banks (default = 8)", "8");
option_parser_register(
opp, "-gpgpu_reg_bank_use_warp_id", OPT_BOOL, &gpgpu_reg_bank_use_warp_id,
"Use warp ID in mapping registers to banks (default = off)", "0");
option_parser_register(opp, "-gpgpu_sub_core_model", OPT_BOOL,
&sub_core_model,
"Sub Core Volta/Pascal model (default = off)", "0");
option_parser_register(opp, "-gpgpu_enable_specialized_operand_collector",
OPT_BOOL, &enable_specialized_operand_collector,
"enable_specialized_operand_collector", "1");
option_parser_register(opp, "-gpgpu_operand_collector_num_units_sp",
OPT_INT32, &gpgpu_operand_collector_num_units_sp,
"number of collector units (default = 4)", "4");
option_parser_register(opp, "-gpgpu_operand_collector_num_units_dp",
OPT_INT32, &gpgpu_operand_collector_num_units_dp,
"number of collector units (default = 0)", "0");
option_parser_register(opp, "-gpgpu_operand_collector_num_units_sfu",
OPT_INT32, &gpgpu_operand_collector_num_units_sfu,
"number of collector units (default = 4)", "4");
option_parser_register(opp, "-gpgpu_operand_collector_num_units_int",
OPT_INT32, &gpgpu_operand_collector_num_units_int,
"number of collector units (default = 0)", "0");
option_parser_register(opp, "-gpgpu_operand_collector_num_units_tensor_core",
OPT_INT32,
&gpgpu_operand_collector_num_units_tensor_core,
"number of collector units (default = 4)", "4");
option_parser_register(opp, "-gpgpu_operand_collector_num_units_mem",
OPT_INT32, &gpgpu_operand_collector_num_units_mem,
"number of collector units (default = 2)", "2");
option_parser_register(opp, "-gpgpu_operand_collector_num_units_gen",
OPT_INT32, &gpgpu_operand_collector_num_units_gen,
"number of collector units (default = 0)", "0");
option_parser_register(opp, "-gpgpu_operand_collector_num_in_ports_sp",
OPT_INT32, &gpgpu_operand_collector_num_in_ports_sp,
"number of collector unit in ports (default = 1)",
"1");
option_parser_register(opp, "-gpgpu_operand_collector_num_in_ports_dp",
OPT_INT32, &gpgpu_operand_collector_num_in_ports_dp,
"number of collector unit in ports (default = 0)",
"0");
option_parser_register(opp, "-gpgpu_operand_collector_num_in_ports_sfu",
OPT_INT32, &gpgpu_operand_collector_num_in_ports_sfu,
"number of collector unit in ports (default = 1)",
"1");
option_parser_register(opp, "-gpgpu_operand_collector_num_in_ports_int",
OPT_INT32, &gpgpu_operand_collector_num_in_ports_int,
"number of collector unit in ports (default = 0)",
"0");
option_parser_register(
opp, "-gpgpu_operand_collector_num_in_ports_tensor_core", OPT_INT32,
&gpgpu_operand_collector_num_in_ports_tensor_core,
"number of collector unit in ports (default = 1)", "1");
option_parser_register(opp, "-gpgpu_operand_collector_num_in_ports_mem",
OPT_INT32, &gpgpu_operand_collector_num_in_ports_mem,
"number of collector unit in ports (default = 1)",
"1");
option_parser_register(opp, "-gpgpu_operand_collector_num_in_ports_gen",
OPT_INT32, &gpgpu_operand_collector_num_in_ports_gen,
"number of collector unit in ports (default = 0)",
"0");
option_parser_register(opp, "-gpgpu_operand_collector_num_out_ports_sp",
OPT_INT32, &gpgpu_operand_collector_num_out_ports_sp,
"number of collector unit in ports (default = 1)",
"1");
option_parser_register(opp, "-gpgpu_operand_collector_num_out_ports_dp",
OPT_INT32, &gpgpu_operand_collector_num_out_ports_dp,
"number of collector unit in ports (default = 0)",
"0");
option_parser_register(opp, "-gpgpu_operand_collector_num_out_ports_sfu",
OPT_INT32, &gpgpu_operand_collector_num_out_ports_sfu,
"number of collector unit in ports (default = 1)",
"1");
option_parser_register(opp, "-gpgpu_operand_collector_num_out_ports_int",
OPT_INT32, &gpgpu_operand_collector_num_out_ports_int,
"number of collector unit in ports (default = 0)",
"0");
option_parser_register(
opp, "-gpgpu_operand_collector_num_out_ports_tensor_core", OPT_INT32,
&gpgpu_operand_collector_num_out_ports_tensor_core,
"number of collector unit in ports (default = 1)", "1");
option_parser_register(opp, "-gpgpu_operand_collector_num_out_ports_mem",
OPT_INT32, &gpgpu_operand_collector_num_out_ports_mem,
"number of collector unit in ports (default = 1)",
"1");
option_parser_register(opp, "-gpgpu_operand_collector_num_out_ports_gen",
OPT_INT32, &gpgpu_operand_collector_num_out_ports_gen,
"number of collector unit in ports (default = 0)",
"0");
option_parser_register(opp, "-gpgpu_coalesce_arch", OPT_INT32,
&gpgpu_coalesce_arch,
"Coalescing arch (GT200 = 13, Fermi = 20)", "13");
option_parser_register(opp, "-gpgpu_num_sched_per_core", OPT_INT32,
&gpgpu_num_sched_per_core,
"Number of warp schedulers per core", "1");
option_parser_register(opp, "-gpgpu_max_insn_issue_per_warp", OPT_INT32,
&gpgpu_max_insn_issue_per_warp,
"Max number of instructions that can be issued per "
"warp in one cycle by scheduler (either 1 or 2)",
"2");
option_parser_register(opp, "-gpgpu_dual_issue_diff_exec_units", OPT_BOOL,
&gpgpu_dual_issue_diff_exec_units,
"should dual issue use two different execution unit "
"resources (Default = 1)",
"1");
option_parser_register(opp, "-gpgpu_simt_core_sim_order", OPT_INT32,
&simt_core_sim_order,
"Select the simulation order of cores in a cluster "
"(0=Fix, 1=Round-Robin)",
"1");
option_parser_register(
opp, "-gpgpu_pipeline_widths", OPT_CSTR, &pipeline_widths_string,
"Pipeline widths "
"ID_OC_SP,ID_OC_DP,ID_OC_INT,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_"
"INT,OC_EX_SFU,OC_EX_MEM,EX_WB,ID_OC_TENSOR_CORE,OC_EX_TENSOR_CORE",
"1,1,1,1,1,1,1,1,1,1,1,1,1");
option_parser_register(opp, "-gpgpu_tensor_core_avail", OPT_INT32,
&gpgpu_tensor_core_avail,
"Tensor Core Available (default=0)", "0");
option_parser_register(opp, "-gpgpu_num_sp_units", OPT_INT32,
&gpgpu_num_sp_units, "Number of SP units (default=1)",
"1");
option_parser_register(opp, "-gpgpu_num_dp_units", OPT_INT32,
&gpgpu_num_dp_units, "Number of DP units (default=0)",
"0");
option_parser_register(opp, "-gpgpu_num_int_units", OPT_INT32,
&gpgpu_num_int_units,
"Number of INT units (default=0)", "0");
option_parser_register(opp, "-gpgpu_num_sfu_units", OPT_INT32,
&gpgpu_num_sfu_units, "Number of SF units (default=1)",
"1");
option_parser_register(opp, "-gpgpu_num_tensor_core_units", OPT_INT32,
&gpgpu_num_tensor_core_units,
"Number of tensor_core units (default=1)", "0");
option_parser_register(
opp, "-gpgpu_num_mem_units", OPT_INT32, &gpgpu_num_mem_units,
"Number if ldst units (default=1) WARNING: not hooked up to anything",
"1");
option_parser_register(
opp, "-gpgpu_scheduler", OPT_CSTR, &gpgpu_scheduler_string,
"Scheduler configuration: < lrr | gto | two_level_active > "
"If "
"two_level_active:<num_active_warps>:<inner_prioritization>:<outer_"
"prioritization>"
"For complete list of prioritization values see shader.h enum "
"scheduler_prioritization_type"
"Default: gto",
"gto");
option_parser_register(
opp, "-gpgpu_concurrent_kernel_sm", OPT_BOOL, &gpgpu_concurrent_kernel_sm,
"Support concurrent kernels on a SM (default = disabled)", "0");
option_parser_register(opp, "-gpgpu_perfect_inst_const_cache", OPT_BOOL,
&perfect_inst_const_cache,
"perfect inst and const cache mode, so all inst and "
"const hits in the cache(default = disabled)",
"0");
option_parser_register(
opp, "-gpgpu_inst_fetch_throughput", OPT_INT32, &inst_fetch_throughput,
"the number of fetched intruction per warp each cycle", "1");
option_parser_register(opp, "-gpgpu_reg_file_port_throughput", OPT_INT32,
®_file_port_throughput,
"the number ports of the register file", "1");
for (unsigned j = 0; j < SPECIALIZED_UNIT_NUM; ++j) {
std::stringstream ss;
ss << "-specialized_unit_" << j + 1;
option_parser_register(opp, ss.str().c_str(), OPT_CSTR,
&specialized_unit_string[j],
"specialized unit config"
" {<enabled>,<num_units>:<latency>:<initiation>,<ID_"
"OC_SPEC>:<OC_EX_SPEC>,<NAME>}",
"0,4,4,4,4,BRA");
}
}
void gpgpu_sim_config::reg_options(option_parser_t opp) {
gpgpu_functional_sim_config::reg_options(opp);
m_shader_config.reg_options(opp);
m_memory_config.reg_options(opp);
power_config::reg_options(opp);
option_parser_register(opp, "-gpgpu_max_cycle", OPT_INT64, &gpu_max_cycle_opt,
"terminates gpu simulation early (0 = no limit)", "0");
option_parser_register(opp, "-gpgpu_max_insn", OPT_INT64, &gpu_max_insn_opt,
"terminates gpu simulation early (0 = no limit)", "0");
option_parser_register(opp, "-gpgpu_max_cta", OPT_INT32, &gpu_max_cta_opt,
"terminates gpu simulation early (0 = no limit)", "0");
option_parser_register(opp, "-gpgpu_max_completed_cta", OPT_INT32,
&gpu_max_completed_cta_opt,
"terminates gpu simulation early (0 = no limit)", "0");
option_parser_register(
opp, "-gpgpu_runtime_stat", OPT_CSTR, &gpgpu_runtime_stat,
"display runtime statistics such as dram utilization {<freq>:<flag>}",
"10000:0");
option_parser_register(opp, "-liveness_message_freq", OPT_INT64,
&liveness_message_freq,
"Minimum number of seconds between simulation "
"liveness messages (0 = always print)",
"1");
option_parser_register(opp, "-gpgpu_compute_capability_major", OPT_UINT32,
&gpgpu_compute_capability_major,
"Major compute capability version number", "7");
option_parser_register(opp, "-gpgpu_compute_capability_minor", OPT_UINT32,
&gpgpu_compute_capability_minor,
"Minor compute capability version number", "0");
option_parser_register(opp, "-gpgpu_flush_l1_cache", OPT_BOOL,
&gpgpu_flush_l1_cache,
"Flush L1 cache at the end of each kernel call", "0");
option_parser_register(opp, "-gpgpu_flush_l2_cache", OPT_BOOL,
&gpgpu_flush_l2_cache,
"Flush L2 cache at the end of each kernel call", "0");
option_parser_register(
opp, "-gpgpu_deadlock_detect", OPT_BOOL, &gpu_deadlock_detect,
"Stop the simulation at deadlock (1=on (default), 0=off)", "1");
option_parser_register(
opp, "-gpgpu_ptx_instruction_classification", OPT_INT32,
&(gpgpu_ctx->func_sim->gpgpu_ptx_instruction_classification),
"if enabled will classify ptx instruction types per kernel (Max 255 "
"kernels now)",
"0");
option_parser_register(
opp, "-gpgpu_ptx_sim_mode", OPT_INT32,
&(gpgpu_ctx->func_sim->g_ptx_sim_mode),
"Select between Performance (default) or Functional simulation (1)", "0");
option_parser_register(opp, "-gpgpu_clock_domains", OPT_CSTR,
&gpgpu_clock_domains,
"Clock Domain Frequencies in MhZ {<Core Clock>:<ICNT "
"Clock>:<L2 Clock>:<DRAM Clock>}",
"500.0:2000.0:2000.0:2000.0");
option_parser_register(
opp, "-gpgpu_max_concurrent_kernel", OPT_INT32, &max_concurrent_kernel,
"maximum kernels that can run concurrently on GPU", "8");
option_parser_register(
opp, "-gpgpu_cflog_interval", OPT_INT32, &gpgpu_cflog_interval,
"Interval between each snapshot in control flow logger", "0");
option_parser_register(opp, "-visualizer_enabled", OPT_BOOL,
&g_visualizer_enabled,
"Turn on visualizer output (1=On, 0=Off)", "1");
option_parser_register(opp, "-visualizer_outputfile", OPT_CSTR,
&g_visualizer_filename,
"Specifies the output log file for visualizer", NULL);
option_parser_register(
opp, "-visualizer_zlevel", OPT_INT32, &g_visualizer_zlevel,
"Compression level of the visualizer output log (0=no comp, 9=highest)",
"6");
option_parser_register(opp, "-gpgpu_stack_size_limit", OPT_INT32,
&stack_size_limit, "GPU thread stack size", "1024");
option_parser_register(opp, "-gpgpu_heap_size_limit", OPT_INT32,
&heap_size_limit, "GPU malloc heap size ", "8388608");
option_parser_register(opp, "-gpgpu_runtime_sync_depth_limit", OPT_INT32,
&runtime_sync_depth_limit,
"GPU device runtime synchronize depth", "2");
option_parser_register(opp, "-gpgpu_runtime_pending_launch_count_limit",
OPT_INT32, &runtime_pending_launch_count_limit,
"GPU device runtime pending launch count", "2048");
option_parser_register(opp, "-trace_enabled", OPT_BOOL, &Trace::enabled,
"Turn on traces", "0");
option_parser_register(opp, "-trace_components", OPT_CSTR, &Trace::config_str,
"comma seperated list of traces to enable. "
"Complete list found in trace_streams.tup. "
"Default none",
"none");
option_parser_register(
opp, "-trace_sampling_core", OPT_INT32, &Trace::sampling_core,
"The core which is printed using CORE_DPRINTF. Default 0", "0");
option_parser_register(opp, "-trace_sampling_memory_partition", OPT_INT32,
&Trace::sampling_memory_partition,
"The memory partition which is printed using "
"MEMPART_DPRINTF. Default -1 (i.e. all)",
"-1");
gpgpu_ctx->stats->ptx_file_line_stats_options(opp);
// Jin: kernel launch latency
option_parser_register(opp, "-gpgpu_kernel_launch_latency", OPT_INT32,
&(gpgpu_ctx->device_runtime->g_kernel_launch_latency),
"Kernel launch latency in cycles. Default: 0", "0");
option_parser_register(opp, "-gpgpu_cdp_enabled", OPT_BOOL,
&(gpgpu_ctx->device_runtime->g_cdp_enabled),
"Turn on CDP", "0");
option_parser_register(opp, "-gpgpu_TB_launch_latency", OPT_INT32,
&(gpgpu_ctx->device_runtime->g_TB_launch_latency),
"thread block launch latency in cycles. Default: 0",
"0");
}
/////////////////////////////////////////////////////////////////////////////
void increment_x_then_y_then_z(dim3 &i, const dim3 &bound) {
i.x++;
if (i.x >= bound.x) {
i.x = 0;
i.y++;
if (i.y >= bound.y) {
i.y = 0;
if (i.z < bound.z) i.z++;
}
}
}
void gpgpu_sim::launch(kernel_info_t *kinfo) {
unsigned cta_size = kinfo->threads_per_cta();
if (cta_size > m_shader_config->n_thread_per_shader) {
printf(
"Execution error: Shader kernel CTA (block) size is too large for "
"microarch config.\n");
printf(" CTA size (x*y*z) = %u, max supported = %u\n",
cta_size, m_shader_config->n_thread_per_shader);
printf(
" => either change -gpgpu_shader argument in "
"gpgpusim.config file or\n");
printf(
" modify the CUDA source to decrease the kernel block "
"size.\n");
abort();
}
unsigned n = 0;
for (n = 0; n < m_running_kernels.size(); n++) {
if ((NULL == m_running_kernels[n]) || m_running_kernels[n]->done()) {
m_running_kernels[n] = kinfo;
break;
}
}
assert(n < m_running_kernels.size());
}
bool gpgpu_sim::can_start_kernel() {
for (unsigned n = 0; n < m_running_kernels.size(); n++) {
if ((NULL == m_running_kernels[n]) || m_running_kernels[n]->done())
return true;
}
return false;
}
bool gpgpu_sim::hit_max_cta_count() const {
if (m_config.gpu_max_cta_opt != 0) {
if ((gpu_tot_issued_cta + m_total_cta_launched) >= m_config.gpu_max_cta_opt)
return true;
}
return false;
}
bool gpgpu_sim::kernel_more_cta_left(kernel_info_t *kernel) const {
if (hit_max_cta_count()) return false;
if (kernel && !kernel->no_more_ctas_to_run()) return true;
return false;
}
bool gpgpu_sim::get_more_cta_left() const {
if (hit_max_cta_count()) return false;
for (unsigned n = 0; n < m_running_kernels.size(); n++) {
if (m_running_kernels[n] && !m_running_kernels[n]->no_more_ctas_to_run())
return true;
}
return false;
}
void gpgpu_sim::decrement_kernel_latency() {
for (unsigned n = 0; n < m_running_kernels.size(); n++) {
if (m_running_kernels[n] && m_running_kernels[n]->m_kernel_TB_latency)
m_running_kernels[n]->m_kernel_TB_latency--;
}
}
kernel_info_t *gpgpu_sim::select_kernel() {
if (m_running_kernels[m_last_issued_kernel] &&
!m_running_kernels[m_last_issued_kernel]->no_more_ctas_to_run() &&
!m_running_kernels[m_last_issued_kernel]->m_kernel_TB_latency) {
unsigned launch_uid = m_running_kernels[m_last_issued_kernel]->get_uid();
if (std::find(m_executed_kernel_uids.begin(), m_executed_kernel_uids.end(),
launch_uid) == m_executed_kernel_uids.end()) {
m_running_kernels[m_last_issued_kernel]->start_cycle =
gpu_sim_cycle + gpu_tot_sim_cycle;
m_executed_kernel_uids.push_back(launch_uid);
m_executed_kernel_names.push_back(
m_running_kernels[m_last_issued_kernel]->name());
}
return m_running_kernels[m_last_issued_kernel];
}
for (unsigned n = 0; n < m_running_kernels.size(); n++) {
unsigned idx =
(n + m_last_issued_kernel + 1) % m_config.max_concurrent_kernel;
if (kernel_more_cta_left(m_running_kernels[idx]) &&
!m_running_kernels[idx]->m_kernel_TB_latency) {
m_last_issued_kernel = idx;
m_running_kernels[idx]->start_cycle = gpu_sim_cycle + gpu_tot_sim_cycle;
// record this kernel for stat print if it is the first time this kernel
// is selected for execution
unsigned launch_uid = m_running_kernels[idx]->get_uid();
assert(std::find(m_executed_kernel_uids.begin(),
m_executed_kernel_uids.end(),
launch_uid) == m_executed_kernel_uids.end());
m_executed_kernel_uids.push_back(launch_uid);
m_executed_kernel_names.push_back(m_running_kernels[idx]->name());
return m_running_kernels[idx];
}
}
return NULL;
}
unsigned gpgpu_sim::finished_kernel() {
if (m_finished_kernel.empty()) return 0;
unsigned result = m_finished_kernel.front();
m_finished_kernel.pop_front();
return result;
}
void gpgpu_sim::set_kernel_done(kernel_info_t *kernel) {
unsigned uid = kernel->get_uid();
m_finished_kernel.push_back(uid);
std::vector<kernel_info_t *>::iterator k;
for (k = m_running_kernels.begin(); k != m_running_kernels.end(); k++) {
if (*k == kernel) {
kernel->end_cycle = gpu_sim_cycle + gpu_tot_sim_cycle;
*k = NULL;
break;
}
}
assert(k != m_running_kernels.end());
}
void gpgpu_sim::stop_all_running_kernels() {
std::vector<kernel_info_t *>::iterator k;
for (k = m_running_kernels.begin(); k != m_running_kernels.end(); ++k) {
if (*k != NULL) { // If a kernel is active
set_kernel_done(*k); // Stop the kernel
assert(*k == NULL);
}
}
}
void exec_gpgpu_sim::createSIMTCluster() {
m_cluster = new simt_core_cluster *[m_shader_config->n_simt_clusters];
for (unsigned i = 0; i < m_shader_config->n_simt_clusters; i++)
m_cluster[i] =
new exec_simt_core_cluster(this, i, m_shader_config, m_memory_config,
m_shader_stats, m_memory_stats);
}
gpgpu_sim::gpgpu_sim(const gpgpu_sim_config &config, gpgpu_context *ctx)
: gpgpu_t(config, ctx), m_config(config) {
gpgpu_ctx = ctx;
m_shader_config = &m_config.m_shader_config;
m_memory_config = &m_config.m_memory_config;
ctx->ptx_parser->set_ptx_warp_size(m_shader_config);
ptx_file_line_stats_create_exposed_latency_tracker(m_config.num_shader());
#ifdef GPGPUSIM_POWER_MODEL
m_gpgpusim_wrapper = new gpgpu_sim_wrapper(config.g_power_simulation_enabled,
config.g_power_config_name);
#endif
m_shader_stats = new shader_core_stats(m_shader_config);
m_memory_stats = new memory_stats_t(m_config.num_shader(), m_shader_config,
m_memory_config, this);
average_pipeline_duty_cycle = (float *)malloc(sizeof(float));
active_sms = (float *)malloc(sizeof(float));
m_power_stats =
new power_stat_t(m_shader_config, average_pipeline_duty_cycle, active_sms,
m_shader_stats, m_memory_config, m_memory_stats);
gpu_sim_insn = 0;
gpu_tot_sim_insn = 0;
gpu_tot_issued_cta = 0;
gpu_completed_cta = 0;
m_total_cta_launched = 0;
gpu_deadlock = false;
gpu_stall_dramfull = 0;
gpu_stall_icnt2sh = 0;
partiton_reqs_in_parallel = 0;
partiton_reqs_in_parallel_total = 0;
partiton_reqs_in_parallel_util = 0;
partiton_reqs_in_parallel_util_total = 0;
gpu_sim_cycle_parition_util = 0;
gpu_tot_sim_cycle_parition_util = 0;
partiton_replys_in_parallel = 0;
partiton_replys_in_parallel_total = 0;
m_memory_partition_unit =
new memory_partition_unit *[m_memory_config->m_n_mem];
m_memory_sub_partition =
new memory_sub_partition *[m_memory_config->m_n_mem_sub_partition];
for (unsigned i = 0; i < m_memory_config->m_n_mem; i++) {
m_memory_partition_unit[i] =
new memory_partition_unit(i, m_memory_config, m_memory_stats, this);
for (unsigned p = 0;
p < m_memory_config->m_n_sub_partition_per_memory_channel; p++) {
unsigned submpid =
i * m_memory_config->m_n_sub_partition_per_memory_channel + p;
m_memory_sub_partition[submpid] =
m_memory_partition_unit[i]->get_sub_partition(p);
}
}
icnt_wrapper_init();
icnt_create(m_shader_config->n_simt_clusters,
m_memory_config->m_n_mem_sub_partition);
time_vector_create(NUM_MEM_REQ_STAT);
fprintf(stdout,
"GPGPU-Sim uArch: performance model initialization complete.\n");
m_running_kernels.resize(config.max_concurrent_kernel, NULL);
m_last_issued_kernel = 0;
m_last_cluster_issue = m_shader_config->n_simt_clusters -
1; // this causes first launch to use simt cluster 0
*average_pipeline_duty_cycle = 0;
*active_sms = 0;
last_liveness_message_time = 0;
// Jin: functional simulation for CDP
m_functional_sim = false;
m_functional_sim_kernel = NULL;
}
int gpgpu_sim::shared_mem_size() const {
return m_shader_config->gpgpu_shmem_size;
}
int gpgpu_sim::shared_mem_per_block() const {
return m_shader_config->gpgpu_shmem_per_block;
}
int gpgpu_sim::num_registers_per_core() const {
return m_shader_config->gpgpu_shader_registers;
}
int gpgpu_sim::num_registers_per_block() const {
return m_shader_config->gpgpu_registers_per_block;
}
int gpgpu_sim::wrp_size() const { return m_shader_config->warp_size; }
int gpgpu_sim::shader_clock() const { return m_config.core_freq / 1000; }
int gpgpu_sim::max_cta_per_core() const {
return m_shader_config->max_cta_per_core;
}
int gpgpu_sim::get_max_cta(const kernel_info_t &k) const {
return m_shader_config->max_cta(k);
}
void gpgpu_sim::set_prop(cudaDeviceProp *prop) { m_cuda_properties = prop; }
int gpgpu_sim::compute_capability_major() const {
return m_config.gpgpu_compute_capability_major;
}
int gpgpu_sim::compute_capability_minor() const {
return m_config.gpgpu_compute_capability_minor;
}
const struct cudaDeviceProp *gpgpu_sim::get_prop() const {
return m_cuda_properties;
}
enum divergence_support_t gpgpu_sim::simd_model() const {
return m_shader_config->model;
}
void gpgpu_sim_config::init_clock_domains(void) {
sscanf(gpgpu_clock_domains, "%lf:%lf:%lf:%lf", &core_freq, &icnt_freq,
&l2_freq, &dram_freq);
core_freq = core_freq MhZ;
icnt_freq = icnt_freq MhZ;
l2_freq = l2_freq MhZ;
dram_freq = dram_freq MhZ;
core_period = 1 / core_freq;
icnt_period = 1 / icnt_freq;
dram_period = 1 / dram_freq;
l2_period = 1 / l2_freq;
printf("GPGPU-Sim uArch: clock freqs: %lf:%lf:%lf:%lf\n", core_freq,
icnt_freq, l2_freq, dram_freq);
printf("GPGPU-Sim uArch: clock periods: %.20lf:%.20lf:%.20lf:%.20lf\n",
core_period, icnt_period, l2_period, dram_period);
}
void gpgpu_sim::reinit_clock_domains(void) {
core_time = 0;
dram_time = 0;
icnt_time = 0;
l2_time = 0;
}
bool gpgpu_sim::active() {
if (m_config.gpu_max_cycle_opt &&
(gpu_tot_sim_cycle + gpu_sim_cycle) >= m_config.gpu_max_cycle_opt)
return false;
if (m_config.gpu_max_insn_opt &&
(gpu_tot_sim_insn + gpu_sim_insn) >= m_config.gpu_max_insn_opt)
return false;
if (m_config.gpu_max_cta_opt &&
(gpu_tot_issued_cta >= m_config.gpu_max_cta_opt))
return false;
if (m_config.gpu_max_completed_cta_opt &&
(gpu_completed_cta >= m_config.gpu_max_completed_cta_opt))
return false;
if (m_config.gpu_deadlock_detect && gpu_deadlock) return false;
for (unsigned i = 0; i < m_shader_config->n_simt_clusters; i++)
if (m_cluster[i]->get_not_completed() > 0) return true;
;
for (unsigned i = 0; i < m_memory_config->m_n_mem; i++)
if (m_memory_partition_unit[i]->busy() > 0) return true;
;
if (icnt_busy()) return true;
if (get_more_cta_left()) return true;
return false;
}
void gpgpu_sim::init() {
// run a CUDA grid on the GPU microarchitecture simulator
gpu_sim_cycle = 0;
gpu_sim_insn = 0;
last_gpu_sim_insn = 0;
m_total_cta_launched = 0;
gpu_completed_cta = 0;
partiton_reqs_in_parallel = 0;
partiton_replys_in_parallel = 0;