diff --git a/Documentation/backend_test_health.md b/Documentation/backend_test_health.md index 4fbde47c9b..72527ad1db 100644 --- a/Documentation/backend_test_health.md +++ b/Documentation/backend_test_health.md @@ -13,11 +13,22 @@ Tests skipped by each supported backend: * 4 not implemented * linux/386/pie skipped = 1 * 1 broken +* linux/ppc64le skipped = 1 + * 1 broken - cgo stacktraces +* linux/ppc64le/native skipped = 1 + * 1 broken in linux ppc64le +* linux/ppc64le/native/pie skipped = 11 + * 11 broken - pie mode * pie skipped = 2 * 2 upstream issue - https://github.com/golang/go/issues/29322 +* ppc64le skipped = 11 + * 6 broken + * 1 broken - global variable symbolication + * 4 not implemented * windows skipped = 4 * 1 broken * 3 see https://github.com/go-delve/delve/issues/2768 -* windows/arm64 skipped = 4 +* windows/arm64 skipped = 5 * 3 broken + * 1 broken - cgo stacktraces * 1 broken - step concurrent diff --git a/_fixtures/asmnilptr/main_ppc64le.s b/_fixtures/asmnilptr/main_ppc64le.s new file mode 100644 index 0000000000..fb57de19f6 --- /dev/null +++ b/_fixtures/asmnilptr/main_ppc64le.s @@ -0,0 +1,7 @@ +#include "textflag.h" + +TEXT ·asmFunc(SB),0,$0-16 + MOVD arg+0(FP), R5 + MOVD (R5), R5 + MOVD R5, ret+8(FP) + RET diff --git a/_fixtures/cgostacktest/hello.c b/_fixtures/cgostacktest/hello.c index edcef6b7e4..b779bf96aa 100644 --- a/_fixtures/cgostacktest/hello.c +++ b/_fixtures/cgostacktest/hello.c @@ -6,6 +6,8 @@ #define BREAKPOINT asm("int3;") #elif __i386__ #define BREAKPOINT asm("int3;") +#elif __PPC64__ +#define BREAKPOINT asm("tw 31,0,0;") #elif __aarch64__ #ifdef WIN32 #define BREAKPOINT asm("brk 0xF000;") diff --git a/_scripts/make.go b/_scripts/make.go index eef24266b1..ee75cff608 100644 --- a/_scripts/make.go +++ b/_scripts/make.go @@ -291,6 +291,9 @@ func tagFlags() string { if runtime.GOOS == "windows" && runtime.GOARCH == "arm64" { tags = append(tags, "exp.winarm64") } + if runtime.GOOS == "linux" && runtime.GOARCH == "ppc64le" { + tags = append(tags, "exp.linuxppc64le") + } if Tags != nil && len(*Tags) > 0 { tags = append(tags, *Tags...) } diff --git a/_scripts/test_linux.sh b/_scripts/test_linux.sh index 44ca5d7b44..a84d73abb3 100755 --- a/_scripts/test_linux.sh +++ b/_scripts/test_linux.sh @@ -76,3 +76,11 @@ else exit $x fi +export GOARCH=ppc64le +go run _scripts/make.go --tags exp.linuxppc64le +x=$? +if [ "$version" = "gotip" ]; then + exit 0 +else + exit $x +fi diff --git a/cmd/dlv/dlv_test.go b/cmd/dlv/dlv_test.go index 153cc962d1..1dc474a393 100644 --- a/cmd/dlv/dlv_test.go +++ b/cmd/dlv/dlv_test.go @@ -213,6 +213,9 @@ func getDlvBin(t *testing.T) string { if runtime.GOOS == "windows" && runtime.GOARCH == "arm64" { tags = "-tags=exp.winarm64" } + if runtime.GOOS == "linux" && runtime.GOARCH == "ppc64le" { + tags = "-tags=exp.linuxppc64le" + } return getDlvBinInternal(t, tags) } @@ -371,6 +374,10 @@ func TestGeneratedDoc(t *testing.T) { //TODO(qmuntal): investigate further when the Windows ARM64 backend is more stable. t.Skip("skipping test on Windows in CI") } + if runtime.GOOS == "linux" && runtime.GOARCH == "ppc64le" { + //TODO(alexsaezm): finish CI integration + t.Skip("skipping test on Linux/PPC64LE in CI") + } // Checks gen-cli-docs.go var generatedBuf bytes.Buffer commands := terminal.DebugCommands(nil) diff --git a/pkg/dwarf/regnum/ppc64le.go b/pkg/dwarf/regnum/ppc64le.go new file mode 100644 index 0000000000..412225a464 --- /dev/null +++ b/pkg/dwarf/regnum/ppc64le.go @@ -0,0 +1,115 @@ +package regnum + +import "fmt" + +// The mapping between hardware registers and DWARF registers is specified +// in the 64-Bit ELF V2 ABI Specification of the Power Architecture in section +// 2.4 DWARF Definition +// https://openpowerfoundation.org/specifications/64bitelfabi/ + +const ( + // General Purpose Registers: from R0 to R31 + PPC64LE_FIRST_GPR = 0 + PPC64LE_R0 = PPC64LE_FIRST_GPR + PPC64LE_LAST_GPR = 31 + // Floating point registers: from F0 to F31 + PPC64LE_FIRST_FPR = 32 + PPC64LE_F0 = PPC64LE_FIRST_FPR + PPC64LE_LAST_FPR = 63 + // Vector (Altivec/VMX) registers: from V0 to V31 + PPC64LE_FIRST_VMX = 64 + PPC64LE_V0 = PPC64LE_FIRST_VMX + PPC64LE_LAST_VMX = 95 + // Vector Scalar (VSX) registers: from VS0 to VS63 + PPC64LE_FIRST_VSX = 96 + PPC64LE_VS0 = PPC64LE_FIRST_VSX + PPC64LE_LAST_VSX = 160 + // Condition Registers: from CR0 to CR7 + PPC64LE_CR0 = 0 + // Special registers + PPC64LE_SP = 1 // Stack frame pointer: Gpr[1] + PPC64LE_PC = 12 // The documentation refers to this as the CIA (Current Instruction Address) + PPC64LE_LR = 65 // Link register +) + +func PPC64LEToName(num uint64) string { + switch { + case num == PPC64LE_SP: + return "SP" + case num == PPC64LE_PC: + return "PC" + case num == PPC64LE_LR: + return "LR" + case isGPR(num): + return fmt.Sprintf("r%d", int(num-PPC64LE_FIRST_GPR)) + case isFPR(num): + return fmt.Sprintf("f%d", int(num-PPC64LE_FIRST_FPR)) + case isVMX(num): + return fmt.Sprintf("v%d", int(num-PPC64LE_FIRST_VMX)) + case isVSX(num): + return fmt.Sprintf("vs%d", int(num-PPC64LE_FIRST_VSX)) + default: + return fmt.Sprintf("unknown%d", num) + } +} + +// PPC64LEMaxRegNum is 172 registers in total, across 4 categories: +// General Purpose Registers or GPR (32 GPR + 9 special registers) +// Floating Point Registers or FPR (32 FPR + 1 special register) +// Altivec/VMX Registers or VMX (32 VMX + 2 special registers) +// VSX Registers or VSX (64 VSX) +// Documentation: https://lldb.llvm.org/cpp_reference/RegisterContextPOSIX__ppc64le_8cpp_source.html +func PPC64LEMaxRegNum() uint64 { + return 172 +} + +func isGPR(num uint64) bool { + return num < PPC64LE_LAST_GPR +} + +func isFPR(num uint64) bool { + return num >= PPC64LE_FIRST_FPR && num <= PPC64LE_LAST_FPR +} + +func isVMX(num uint64) bool { + return num >= PPC64LE_FIRST_VMX && num <= PPC64LE_LAST_VMX +} + +func isVSX(num uint64) bool { + return num >= PPC64LE_FIRST_VSX && num <= PPC64LE_LAST_VSX +} + +var PPC64LENameToDwarf = func() map[string]int { + r := make(map[string]int) + + r["nip"] = PPC64LE_PC + r["sp"] = PPC64LE_SP + r["bp"] = PPC64LE_SP + r["link"] = PPC64LE_LR + + // General Purpose Registers: from R0 to R31 + for i := 0; i <= 31; i++ { + r[fmt.Sprintf("r%d", i)] = PPC64LE_R0 + i + } + + // Floating point registers: from F0 to F31 + for i := 0; i <= 31; i++ { + r[fmt.Sprintf("f%d", i)] = PPC64LE_F0 + i + } + + // Vector (Altivec/VMX) registers: from V0 to V31 + for i := 0; i <= 31; i++ { + r[fmt.Sprintf("v%d", i)] = PPC64LE_V0 + i + } + + // Vector Scalar (VSX) registers: from VS0 to VS63 + for i := 0; i <= 63; i++ { + r[fmt.Sprintf("vs%d", i)] = PPC64LE_VS0 + i + } + + // Condition Registers: from CR0 to CR7 + for i := 0; i <= 7; i++ { + r[fmt.Sprintf("cr%d", i)] = PPC64LE_CR0 + i + } + return r +}() diff --git a/pkg/proc/arch.go b/pkg/proc/arch.go index 22de6b1686..6c182ea263 100644 --- a/pkg/proc/arch.go +++ b/pkg/proc/arch.go @@ -151,5 +151,6 @@ func nameToDwarfFunc(n2d map[string]int) func(string) (int, bool) { const ( crosscall2SPOffsetBad = 0x8 crosscall2SPOffsetWindowsAMD64 = 0x118 + crosscall2SPOffsetLinuxPPC64LE = 0x158 crosscall2SPOffset = 0x58 ) diff --git a/pkg/proc/bininfo.go b/pkg/proc/bininfo.go index 0e61779b6b..2e08b32e59 100644 --- a/pkg/proc/bininfo.go +++ b/pkg/proc/bininfo.go @@ -129,6 +129,7 @@ var ( elf.EM_X86_64: true, elf.EM_AARCH64: true, elf.EM_386: true, + elf.EM_PPC64: true, } supportedWindowsArch = map[_PEMachine]bool{ @@ -687,6 +688,8 @@ func NewBinaryInfo(goos, goarch string) *BinaryInfo { r.Arch = AMD64Arch(goos) case "arm64": r.Arch = ARM64Arch(goos) + case "ppc64le": + r.Arch = PPC64LEArch(goos) } return r } @@ -1648,6 +1651,9 @@ func (bi *BinaryInfo) setGStructOffsetElf(image *Image, exe *elf.File, wg *sync. bi.gStructOffset = tlsg.Value + uint64(bi.Arch.PtrSize()*2) + ((tls.Vaddr - uint64(bi.Arch.PtrSize()*2)) & (tls.Align - 1)) + case elf.EM_PPC64: + _ = getSymbol(image, bi.logger, exe, "runtime.tls_g") + default: // we should never get here panic("architecture not supported") diff --git a/pkg/proc/dump.go b/pkg/proc/dump.go index bfa29cc9b5..ebda9d99d9 100644 --- a/pkg/proc/dump.go +++ b/pkg/proc/dump.go @@ -136,6 +136,8 @@ func (t *Target) Dump(out elfwriter.WriteCloserSeeker, flags DumpFlags, state *D fhdr.Machine = elf.EM_386 case "arm64": fhdr.Machine = elf.EM_AARCH64 + case "ppc64le": + fhdr.Machine = elf.EM_PPC64 default: panic("not implemented") } diff --git a/pkg/proc/linutil/regs_ppc64le_arch.go b/pkg/proc/linutil/regs_ppc64le_arch.go new file mode 100644 index 0000000000..56670ba59d --- /dev/null +++ b/pkg/proc/linutil/regs_ppc64le_arch.go @@ -0,0 +1,174 @@ +package linutil + +import ( + "fmt" + + "github.com/go-delve/delve/pkg/proc" +) + +// PPC64LERegisters implements the proc.Registers interface for the native/linux +// backend and core/linux backends, on PPC64LE. +type PPC64LERegisters struct { + Regs *PPC64LEPtraceRegs + Fpregs []proc.Register //Formatted floating point registers + Fpregset []byte //holding all floating point register values + loadFpRegs func(*PPC64LERegisters) error +} + +func NewPPC64LERegisters(regs *PPC64LEPtraceRegs, loadFpRegs func(*PPC64LERegisters) error) *PPC64LERegisters { + return &PPC64LERegisters{Regs: regs, loadFpRegs: loadFpRegs} +} + +// PPC64LEPtraceRegs is the struct used by the linux kernel to return the +// general purpose registers for PPC64LE CPUs. +// Copied from src/syscall/ztypes_linux_ppc64le.go#L518-L532 +type PPC64LEPtraceRegs struct { + Gpr [32]uint64 // 32 general-purpose registers, each 64 bits wide + Nip uint64 + Msr uint64 + Orig_gpr3 uint64 + Ctr uint64 + Link uint64 // Link register -- LLDB dwarf_lr_ppc64le = 65 + Xer uint64 // Fixed point exception register -- LLDB dwarf_xer_ppc64le = 76 + Ccr uint64 + Softe uint64 + Trap uint64 + Dar uint64 + Dsisr uint64 + Result uint64 +} + +// PC returns the value of the NIP register +// Also called the IAR/Instruction Address Register or NIP/Next Instruction Pointer +func (r *PPC64LERegisters) PC() uint64 { + return r.Regs.Nip +} + +// SP returns the value of Stack frame pointer stored in Gpr[1]. +func (r *PPC64LERegisters) SP() uint64 { + return r.Regs.Gpr[1] +} + +// LR The Link Register is a 64-bit register. It can be +// used to provide the branch target address for the +// Branch Conditional to Link Register instruction, and it +// holds the return address after Branch instructions for +// which LK=1 and after System Call Vectored instructions. +// Extracted from the 2.3.2 section of the PowerISA Book 3.1 +func (r *PPC64LERegisters) LR() uint64 { + return r.Regs.Link +} + +func (r *PPC64LERegisters) BP() uint64 { + return r.Regs.Gpr[1] +} + +// TLS returns the value of the thread pointer stored in Gpr[13] +func (r *PPC64LERegisters) TLS() uint64 { + return r.Regs.Gpr[13] +} + +// GAddr returns the address of the G variable +func (r *PPC64LERegisters) GAddr() (uint64, bool) { + return r.Regs.Gpr[30], true +} + +// Slice returns the registers as a list of (name, value) pairs. +func (r *PPC64LERegisters) Slice(floatingPoint bool) ([]proc.Register, error) { + var regs = []struct { + k string + v uint64 + }{ + {"R0", r.Regs.Gpr[0]}, + {"R1", r.Regs.Gpr[1]}, + {"R2", r.Regs.Gpr[2]}, + {"R3", r.Regs.Gpr[3]}, + {"R4", r.Regs.Gpr[4]}, + {"R5", r.Regs.Gpr[5]}, + {"R6", r.Regs.Gpr[6]}, + {"R7", r.Regs.Gpr[7]}, + {"R8", r.Regs.Gpr[8]}, + {"R9", r.Regs.Gpr[9]}, + {"R10", r.Regs.Gpr[10]}, + {"R11", r.Regs.Gpr[11]}, + {"R12", r.Regs.Gpr[12]}, + {"R13", r.Regs.Gpr[13]}, + {"R14", r.Regs.Gpr[14]}, + {"R15", r.Regs.Gpr[15]}, + {"R16", r.Regs.Gpr[16]}, + {"R17", r.Regs.Gpr[17]}, + {"R18", r.Regs.Gpr[18]}, + {"R19", r.Regs.Gpr[19]}, + {"R20", r.Regs.Gpr[20]}, + {"R21", r.Regs.Gpr[21]}, + {"R22", r.Regs.Gpr[22]}, + {"R23", r.Regs.Gpr[23]}, + {"R24", r.Regs.Gpr[24]}, + {"R25", r.Regs.Gpr[25]}, + {"R26", r.Regs.Gpr[26]}, + {"R27", r.Regs.Gpr[27]}, + {"R28", r.Regs.Gpr[28]}, + {"R29", r.Regs.Gpr[29]}, + {"R30", r.Regs.Gpr[30]}, + {"R31", r.Regs.Gpr[31]}, + {"Nip", r.Regs.Nip}, + {"MSr", r.Regs.Msr}, + {"Orig_gpr3", r.Regs.Orig_gpr3}, + {"Ctr", r.Regs.Ctr}, + {"Link", r.Regs.Link}, + {"Xer", r.Regs.Xer}, + {"Ccr", r.Regs.Ccr}, + {"Softe", r.Regs.Softe}, + {"Trap", r.Regs.Trap}, + {"Dar", r.Regs.Dar}, + {"Dsisr", r.Regs.Dsisr}, + {"Result", r.Regs.Result}, + } + out := make([]proc.Register, 0, len(regs)+len(r.Fpregs)) + for _, reg := range regs { + out = proc.AppendUint64Register(out, reg.k, reg.v) + } + var floatLoadError error + if floatingPoint { + if r.loadFpRegs != nil { + floatLoadError = r.loadFpRegs(r) + r.loadFpRegs = nil + } + out = append(out, r.Fpregs...) + } + return out, floatLoadError +} + +// Copy returns a copy of these registers that is guaranteed not to change. +func (r *PPC64LERegisters) Copy() (proc.Registers, error) { + if r.loadFpRegs != nil { + err := r.loadFpRegs(r) + r.loadFpRegs = nil + if err != nil { + return nil, err + } + } + var rr PPC64LERegisters + rr.Regs = &PPC64LEPtraceRegs{} + *(rr.Regs) = *(r.Regs) + if r.Fpregs != nil { + rr.Fpregs = make([]proc.Register, len(r.Fpregs)) + copy(rr.Fpregs, r.Fpregs) + } + if r.Fpregset != nil { + rr.Fpregset = make([]byte, len(r.Fpregset)) + copy(rr.Fpregset, r.Fpregset) + } + return &rr, nil +} + +type PPC64LEPtraceFpRegs struct { + Fp []byte +} + +func (fpregs *PPC64LEPtraceFpRegs) Decode() (regs []proc.Register) { + for i := 0; i < len(fpregs.Fp); i += 16 { + regs = proc.AppendBytesRegister(regs, fmt.Sprintf("V%d", i/16), fpregs.Fp[i:i+16]) + } + return +} diff --git a/pkg/proc/native/hwbreak_other.go b/pkg/proc/native/hwbreak_other.go index 261448303c..a728bca744 100644 --- a/pkg/proc/native/hwbreak_other.go +++ b/pkg/proc/native/hwbreak_other.go @@ -1,5 +1,5 @@ -//go:build (linux && 386) || (darwin && arm64) || (windows && arm64) -// +build linux,386 darwin,arm64 windows,arm64 +//go:build (linux && 386) || (darwin && arm64) || (windows && arm64) || (linux && ppc64le) +// +build linux,386 darwin,arm64 windows,arm64 linux,ppc64le package native diff --git a/pkg/proc/native/proc.go b/pkg/proc/native/proc.go index da5d88650e..cd84391f2d 100644 --- a/pkg/proc/native/proc.go +++ b/pkg/proc/native/proc.go @@ -321,7 +321,11 @@ func (dbp *nativeProcess) initialize(path string, debugInfoDirs []string) (*proc // look like the breakpoint was hit twice when it was "logically" only // executed once. // See: https://go-review.googlesource.com/c/go/+/208126 - DisableAsyncPreempt: runtime.GOOS == "windows" || (runtime.GOOS == "linux" && runtime.GOARCH == "arm64"), + // - on linux/ppc64le according to @laboger, they had issues in the past + // with gdb once AsyncPreempt was enabled. While implementing the port, + // few tests failed while it was enabled, but cannot be warrantied that + // disabling it fixed the issues. + DisableAsyncPreempt: runtime.GOOS == "windows" || (runtime.GOOS == "linux" && runtime.GOARCH == "arm64") || (runtime.GOOS == "linux" && runtime.GOARCH == "ppc64le"), StopReason: stopReason, CanDump: runtime.GOOS == "linux" || runtime.GOOS == "freebsd" || (runtime.GOOS == "windows" && runtime.GOARCH == "amd64"), @@ -331,7 +335,7 @@ func (dbp *nativeProcess) initialize(path string, debugInfoDirs []string) (*proc if err != nil { return nil, err } - if dbp.bi.Arch.Name == "arm64" { + if dbp.bi.Arch.Name == "arm64" || dbp.bi.Arch.Name == "ppc64le" { dbp.iscgo = tgt.IsCgo() } return grp, nil diff --git a/pkg/proc/native/ptrace_linux_64bit.go b/pkg/proc/native/ptrace_linux_64bit.go index 542645bdd4..ebc0b4c028 100644 --- a/pkg/proc/native/ptrace_linux_64bit.go +++ b/pkg/proc/native/ptrace_linux_64bit.go @@ -1,5 +1,5 @@ -//go:build (linux && amd64) || (linux && arm64) -// +build linux,amd64 linux,arm64 +//go:build (linux && amd64) || (linux && arm64) || (linux && ppc64le) +// +build linux,amd64 linux,arm64 linux,ppc64le package native diff --git a/pkg/proc/native/registers_linux_ppc64le.go b/pkg/proc/native/registers_linux_ppc64le.go new file mode 100644 index 0000000000..4cbdee638b --- /dev/null +++ b/pkg/proc/native/registers_linux_ppc64le.go @@ -0,0 +1,104 @@ +package native + +import ( + "debug/elf" + "syscall" + "unsafe" + + "github.com/go-delve/delve/pkg/dwarf/op" + "github.com/go-delve/delve/pkg/dwarf/regnum" + "github.com/go-delve/delve/pkg/proc" + "github.com/go-delve/delve/pkg/proc/linutil" + sys "golang.org/x/sys/unix" +) + +const ( + _PPC64LE_GPREGS_SIZE = 44 * 8 + _PPC64LE_FPREGS_SIZE = 33*8 + 8 +) + +func ptraceGetGRegs(pid int, regs *linutil.PPC64LEPtraceRegs) (err error) { + sys.PtraceGetRegs(pid, (*sys.PtraceRegs)(regs)) + if err == syscall.Errno(0) { + err = nil + } + return +} + +func ptraceSetGRegs(pid int, regs *linutil.PPC64LEPtraceRegs) (err error) { + sys.PtraceSetRegs(pid, (*sys.PtraceRegs)(regs)) + if err == syscall.Errno(0) { + err = nil + } + return +} + +func ptraceGetFpRegset(tid int) (fpregset []byte, err error) { + var ppc64leFpregs [_PPC64LE_FPREGS_SIZE]byte + iov := sys.Iovec{Base: &ppc64leFpregs[0], Len: _PPC64LE_FPREGS_SIZE} + _, _, err = syscall.Syscall6(syscall.SYS_PTRACE, sys.PTRACE_GETREGSET, uintptr(tid), uintptr(elf.NT_FPREGSET), uintptr(unsafe.Pointer(&iov)), 0, 0) + if err != syscall.Errno(0) { + if err == syscall.ENODEV { + err = nil + } + return + } else { + err = nil + } + + fpregset = ppc64leFpregs[:iov.Len-8] + return fpregset, err +} + +// SetPC sets PC to the value specified by 'pc'. +func (t *nativeThread) setPC(pc uint64) error { + ir, err := registers(t) + if err != nil { + return err + } + r := ir.(*linutil.PPC64LERegisters) + r.Regs.Nip = pc + t.dbp.execPtraceFunc(func() { err = ptraceSetGRegs(t.ID, r.Regs) }) + return err +} + +// SetReg changes the value of the specified register. +func (t *nativeThread) SetReg(regNum uint64, reg *op.DwarfRegister) error { + ir, err := registers(t) + if err != nil { + return err + } + r := ir.(*linutil.PPC64LERegisters) + + switch regNum { + case regnum.PPC64LE_PC: + r.Regs.Nip = reg.Uint64Val + case regnum.PPC64LE_SP: + r.Regs.Gpr[1] = reg.Uint64Val + case regnum.PPC64LE_LR: + r.Regs.Link = reg.Uint64Val + default: + panic("SetReg") + } + + t.dbp.execPtraceFunc(func() { err = ptraceSetGRegs(t.ID, r.Regs) }) + return err +} + +func registers(thread *nativeThread) (proc.Registers, error) { + var ( + regs linutil.PPC64LEPtraceRegs + err error + ) + + thread.dbp.execPtraceFunc(func() { err = ptraceGetGRegs(thread.ID, ®s) }) + if err != nil { + return nil, err + } + r := linutil.NewPPC64LERegisters(®s, func(r *linutil.PPC64LERegisters) error { + var floatLoadError error + r.Fpregs, r.Fpregset, floatLoadError = thread.fpRegisters() + return floatLoadError + }) + return r, nil +} diff --git a/pkg/proc/native/support_sentinel_linux.go b/pkg/proc/native/support_sentinel_linux.go index 1325f09cc4..b13e206e38 100644 --- a/pkg/proc/native/support_sentinel_linux.go +++ b/pkg/proc/native/support_sentinel_linux.go @@ -1,6 +1,10 @@ // This file is used to detect build on unsupported GOOS/GOARCH combinations. -//go:build linux && !amd64 && !arm64 && !386 -// +build linux,!amd64,!arm64,!386 +//go:build linux && !amd64 && !arm64 && !386 && !(ppc64le && exp.linuxppc64le) +// +build linux +// +build !amd64 +// +build !arm64 +// +build !386 +// +build !ppc64le !exp.linuxppc64le package your_linux_architecture_is_not_supported_by_delve diff --git a/pkg/proc/native/threads_linux_ppc64le.go b/pkg/proc/native/threads_linux_ppc64le.go new file mode 100644 index 0000000000..d9b53d1269 --- /dev/null +++ b/pkg/proc/native/threads_linux_ppc64le.go @@ -0,0 +1,25 @@ +package native + +import ( + "fmt" + + "github.com/go-delve/delve/pkg/proc" + "github.com/go-delve/delve/pkg/proc/linutil" +) + +func (t *nativeThread) fpRegisters() ([]proc.Register, []byte, error) { + var regs []proc.Register + var fpregs linutil.PPC64LEPtraceFpRegs + var err error + + t.dbp.execPtraceFunc(func() { fpregs.Fp, err = ptraceGetFpRegset(t.ID) }) + regs = fpregs.Decode() + if err != nil { + err = fmt.Errorf("could not get floating point registers: %v", err.Error()) + } + return regs, fpregs.Fp, err +} + +func (t *nativeThread) restoreRegisters(savedRegs proc.Registers) error { + panic("Unimplemented restoreRegisters method in threads_linux_ppc64le.go") +} diff --git a/pkg/proc/ppc64le_arch.go b/pkg/proc/ppc64le_arch.go new file mode 100644 index 0000000000..53c82125c2 --- /dev/null +++ b/pkg/proc/ppc64le_arch.go @@ -0,0 +1,234 @@ +package proc + +import ( + "encoding/binary" + "fmt" + "strings" + + "github.com/go-delve/delve/pkg/dwarf/frame" + + "github.com/go-delve/delve/pkg/dwarf/op" + "github.com/go-delve/delve/pkg/dwarf/regnum" +) + +// This is the unconditional trap, the same mnemonic that both clang and gcc use +// It's documented in Section C.6 Trap Mnemonics in the Power ISA Book 3 +var ppc64leBreakInstruction = []byte{0x08, 0x00, 0xe0, 0x7f} + +func PPC64LEArch(goos string) *Arch { + return &Arch{ + Name: "ppc64le", + ptrSize: 8, + maxInstructionLength: 4, + breakpointInstruction: ppc64leBreakInstruction, + breakInstrMovesPC: false, + derefTLS: false, // Chapter 3.7 of the ELF V2 ABI Specification + prologues: prologuesPPC64LE, + fixFrameUnwindContext: ppc64leFixFrameUnwindContext, + switchStack: ppc64leSwitchStack, + regSize: ppc64leRegSize, + RegistersToDwarfRegisters: ppc64leRegistersToDwarfRegisters, + addrAndStackRegsToDwarfRegisters: ppc64leAddrAndStackRegsToDwarfRegisters, + DwarfRegisterToString: ppc64leDwarfRegisterToString, + inhibitStepInto: func(*BinaryInfo, uint64) bool { return false }, + asmDecode: ppc64leAsmDecode, + usesLR: true, + PCRegNum: regnum.PPC64LE_PC, + SPRegNum: regnum.PPC64LE_SP, + LRRegNum: regnum.PPC64LE_LR, + asmRegisters: ppc64leAsmRegisters, + RegisterNameToDwarf: nameToDwarfFunc(regnum.PPC64LENameToDwarf), + } +} + +func ppc64leFixFrameUnwindContext(fctxt *frame.FrameContext, pc uint64, bi *BinaryInfo) *frame.FrameContext { + a := bi.Arch + if a.sigreturnfn == nil { + a.sigreturnfn = bi.lookupOneFunc("runtime.sigreturn") + } + if fctxt == nil || (a.sigreturnfn != nil && pc >= a.sigreturnfn.Entry && pc < a.sigreturnfn.End) { + return &frame.FrameContext{ + RetAddrReg: regnum.PPC64LE_LR, + Regs: map[uint64]frame.DWRule{ + regnum.PPC64LE_PC: { + Rule: frame.RuleOffset, + Offset: int64(-a.PtrSize()), + }, + regnum.PPC64LE_LR: { + Rule: frame.RuleOffset, + Offset: int64(-2 * a.PtrSize()), + }, + regnum.PPC64LE_SP: { + Rule: frame.RuleValOffset, + Offset: 0, + }, + }, + CFA: frame.DWRule{ + Rule: frame.RuleCFA, + Reg: regnum.PPC64LE_SP, + Offset: int64(2 * a.PtrSize()), + }, + } + } + if a.crosscall2fn == nil { + // This is used to fix issues with the c calling frames + a.crosscall2fn = bi.lookupOneFunc("crosscall2") + } + + // Checks if we marked the function as a crosscall and if we are currently in it + if a.crosscall2fn != nil && pc >= a.crosscall2fn.Entry && pc < a.crosscall2fn.End { + rule := fctxt.CFA + if rule.Offset == crosscall2SPOffsetBad { + // Linux support only + rule.Offset += crosscall2SPOffsetLinuxPPC64LE + } + fctxt.CFA = rule + } + if fctxt.Regs[regnum.PPC64LE_LR].Rule == frame.RuleUndefined { + fctxt.Regs[regnum.PPC64LE_LR] = frame.DWRule{ + Rule: frame.RuleFramePointer, + Reg: regnum.PPC64LE_LR, + Offset: 0, + } + } + return fctxt +} + +const ppc64cgocallSPOffsetSaveSlot = 32 +const ppc64prevG0schedSPOffsetSaveSlot = 40 + +func ppc64leSwitchStack(it *stackIterator, callFrameRegs *op.DwarfRegisters) bool { + if it.frame.Current.Fn == nil && it.systemstack && it.g != nil && it.top { + it.switchToGoroutineStack() + return true + } + if it.frame.Current.Fn != nil { + switch it.frame.Current.Fn.Name { + case "runtime.asmcgocall", "runtime.cgocallback_gofunc", "runtime.sigpanic", "runtime.cgocallback": + //do nothing + case "runtime.goexit", "runtime.rt0_go", "runtime.mcall": + // Look for "top of stack" functions. + it.atend = true + return true + case "crosscall2": + //The offsets get from runtime/cgo/asm_ppc64x.s:10 + newsp, _ := readUintRaw(it.mem, it.regs.SP()+8*24, int64(it.bi.Arch.PtrSize())) + newbp, _ := readUintRaw(it.mem, it.regs.SP()+8*14, int64(it.bi.Arch.PtrSize())) + newlr, _ := readUintRaw(it.mem, it.regs.SP()+16, int64(it.bi.Arch.PtrSize())) + if it.regs.Reg(it.regs.BPRegNum) != nil { + it.regs.Reg(it.regs.BPRegNum).Uint64Val = newbp + } else { + reg, _ := it.readRegisterAt(it.regs.BPRegNum, it.regs.SP()+8*14) + it.regs.AddReg(it.regs.BPRegNum, reg) + } + it.regs.Reg(it.regs.LRRegNum).Uint64Val = newlr + it.regs.Reg(it.regs.SPRegNum).Uint64Val = newsp + it.pc = newlr + return true + default: + if it.systemstack && it.top && it.g != nil && strings.HasPrefix(it.frame.Current.Fn.Name, "runtime.") && it.frame.Current.Fn.Name != "runtime.fatalthrow" { + // The runtime switches to the system stack in multiple places. + // This usually happens through a call to runtime.systemstack but there + // are functions that switch to the system stack manually (for example + // runtime.morestack). + // Since we are only interested in printing the system stack for cgo + // calls we switch directly to the goroutine stack if we detect that the + // function at the top of the stack is a runtime function. + it.switchToGoroutineStack() + return true + } + } + } + fn := it.bi.PCToFunc(it.frame.Ret) + if fn == nil { + return false + } + switch fn.Name { + case "runtime.asmcgocall": + if !it.systemstack { + return false + } + + // This function is called by a goroutine to execute a C function and + // switches from the goroutine stack to the system stack. + // Since we are unwinding the stack from callee to caller we have to switch + // from the system stack to the goroutine stack. + off, _ := readIntRaw(it.mem, + callFrameRegs.SP()+ppc64cgocallSPOffsetSaveSlot, + int64(it.bi.Arch.PtrSize())) + oldsp := callFrameRegs.SP() + newsp := uint64(int64(it.stackhi) - off) + + // runtime.asmcgocall can also be called from inside the system stack, + // in that case no stack switch actually happens + if newsp == oldsp { + return false + } + it.systemstack = false + callFrameRegs.Reg(callFrameRegs.SPRegNum).Uint64Val = uint64(int64(newsp)) + return false + + case "runtime.cgocallback_gofunc", "runtime.cgocallback": + // For a detailed description of how this works read the long comment at + // the start of $GOROOT/src/runtime/cgocall.go and the source code of + // runtime.cgocallback_gofunc in $GOROOT/src/runtime/asm_ppc64.s + // + // When a C functions calls back into go it will eventually call into + // runtime.cgocallback_gofunc which is the function that does the stack + // switch from the system stack back into the goroutine stack + // Since we are going backwards on the stack here we see the transition + // as goroutine stack -> system stack. + if it.systemstack { + return false + } + + it.loadG0SchedSP() + if it.g0_sched_sp <= 0 { + return false + } + // entering the system stack + callFrameRegs.Reg(callFrameRegs.SPRegNum).Uint64Val = it.g0_sched_sp + // reads the previous value of g0.sched.sp that runtime.cgocallback_gofunc saved on the stack + + // TODO: is this save slot correct? + it.g0_sched_sp, _ = readUintRaw(it.mem, callFrameRegs.SP()+ppc64prevG0schedSPOffsetSaveSlot, int64(it.bi.Arch.PtrSize())) + it.systemstack = true + return false + } + + return false +} + +// ppc64leRegSize returns the size (in bytes) of register regnum. +func ppc64leRegSize(regnum uint64) int { + return 8 // each register is a 64-bit register +} + +func ppc64leRegistersToDwarfRegisters(staticBase uint64, regs Registers) *op.DwarfRegisters { + dregs := initDwarfRegistersFromSlice(int(regnum.PPC64LEMaxRegNum()), regs, regnum.PPC64LENameToDwarf) + dr := op.NewDwarfRegisters(staticBase, dregs, binary.LittleEndian, regnum.PPC64LE_PC, regnum.PPC64LE_SP, regnum.PPC64LE_SP, regnum.PPC64LE_LR) + dr.SetLoadMoreCallback(loadMoreDwarfRegistersFromSliceFunc(dr, regs, regnum.PPC64LENameToDwarf)) + return dr +} + +func ppc64leAddrAndStackRegsToDwarfRegisters(staticBase, pc, sp, bp, lr uint64) op.DwarfRegisters { + dregs := make([]*op.DwarfRegister, regnum.PPC64LE_LR+1) + dregs[regnum.PPC64LE_PC] = op.DwarfRegisterFromUint64(pc) + dregs[regnum.PPC64LE_SP] = op.DwarfRegisterFromUint64(sp) + dregs[regnum.PPC64LE_LR] = op.DwarfRegisterFromUint64(lr) + + return *op.NewDwarfRegisters(staticBase, dregs, binary.LittleEndian, regnum.PPC64LE_PC, regnum.PPC64LE_SP, 0, regnum.PPC64LE_LR) +} + +func ppc64leDwarfRegisterToString(i int, reg *op.DwarfRegister) (name string, floatingPoint bool, repr string) { + name = regnum.PPC64LEToName(uint64(i)) + + if reg == nil { + return name, false, "" + } + + if reg.Bytes == nil || (reg.Bytes != nil && len(reg.Bytes) < 16) { + return name, false, fmt.Sprintf("%#016x", reg.Uint64Val) + } + return name, true, fmt.Sprintf("%#x", reg.Bytes) +} diff --git a/pkg/proc/ppc64le_disasm.go b/pkg/proc/ppc64le_disasm.go new file mode 100644 index 0000000000..c3f9a72e3a --- /dev/null +++ b/pkg/proc/ppc64le_disasm.go @@ -0,0 +1,161 @@ +package proc + +import ( + "encoding/binary" + + "github.com/go-delve/delve/pkg/dwarf/op" + "github.com/go-delve/delve/pkg/dwarf/regnum" + "golang.org/x/arch/ppc64/ppc64asm" +) + +// Possible stacksplit prologues are inserted by stacksplit in +// $GOROOT/src/cmd/internal/obj/ppc64/obj9.go. +var prologuesPPC64LE []opcodeSeq + +func init() { + // Note: these will be the gnu opcodes and not the Go opcodes. Verify the sequences are as expected. + var tinyStacksplit = opcodeSeq{uint64(ppc64asm.ADDI), uint64(ppc64asm.CMPLD), uint64(ppc64asm.BC)} + var smallStacksplit = opcodeSeq{uint64(ppc64asm.ADDI), uint64(ppc64asm.CMPLD), uint64(ppc64asm.BC)} + var bigStacksplit = opcodeSeq{uint64(ppc64asm.ADDI), uint64(ppc64asm.CMPLD), uint64(ppc64asm.BC), uint64(ppc64asm.STD), uint64(ppc64asm.STD), uint64(ppc64asm.MFSPR)} + + var unixGetG = opcodeSeq{uint64(ppc64asm.LD)} + prologuesPPC64LE = make([]opcodeSeq, 0, 3) + for _, getG := range []opcodeSeq{unixGetG} { + for _, stacksplit := range []opcodeSeq{tinyStacksplit, smallStacksplit, bigStacksplit} { + prologue := make(opcodeSeq, 0, len(getG)+len(stacksplit)) + prologue = append(prologue, getG...) + prologue = append(prologue, stacksplit...) + prologuesPPC64LE = append(prologuesPPC64LE, prologue) + } + } +} + +func ppc64leAsmDecode(asmInst *AsmInstruction, mem []byte, regs *op.DwarfRegisters, memrw MemoryReadWriter, bi *BinaryInfo) error { + asmInst.Size = 4 + asmInst.Bytes = mem[:asmInst.Size] + + inst, err := ppc64asm.Decode(mem, binary.LittleEndian) + if err != nil { + asmInst.Inst = (*ppc64ArchInst)(nil) + return err + } + asmInst.Inst = (*ppc64ArchInst)(&inst) + asmInst.Kind = OtherInstruction + + switch inst.Op { + case ppc64asm.BL, ppc64asm.BLA, ppc64asm.BCL, ppc64asm.BCLA, ppc64asm.BCLRL, ppc64asm.BCCTRL, ppc64asm.BCTARL: + // Pages 38-40 Book I v3.0 + asmInst.Kind = CallInstruction + case ppc64asm.RFEBB, ppc64asm.RFID, ppc64asm.HRFID, ppc64asm.RFI, ppc64asm.RFCI, ppc64asm.RFDI, ppc64asm.RFMCI, ppc64asm.RFGI, ppc64asm.BCLR: + asmInst.Kind = RetInstruction + case ppc64asm.B, ppc64asm.BA, ppc64asm.BC, ppc64asm.BCA, ppc64asm.BCCTR, ppc64asm.BCTAR: + // Pages 38-40 Book I v3.0 + asmInst.Kind = JmpInstruction + case ppc64asm.TD, ppc64asm.TDI, ppc64asm.TW, ppc64asm.TWI: + asmInst.Kind = HardBreakInstruction + } + + asmInst.DestLoc = resolveCallArgPPC64LE(&inst, asmInst.Loc.PC, asmInst.AtPC, regs, memrw, bi) + return nil +} + +func resolveCallArgPPC64LE(inst *ppc64asm.Inst, instAddr uint64, currentGoroutine bool, regs *op.DwarfRegisters, mem MemoryReadWriter, bininfo *BinaryInfo) *Location { + switch inst.Op { + case ppc64asm.BCLRL, ppc64asm.BCLR: + if regs != nil && regs.PC() == instAddr { + pc := regs.Reg(bininfo.Arch.LRRegNum).Uint64Val + file, line, fn := bininfo.PCToLine(pc) + if fn == nil { + return &Location{PC: pc} + } + return &Location{PC: pc, File: file, Line: line, Fn: fn} + } + return nil + case ppc64asm.B, ppc64asm.BL, ppc64asm.BLA, ppc64asm.BCL, ppc64asm.BCLA, ppc64asm.BCCTRL, ppc64asm.BCTARL: + // ok + default: + return nil + } + + var pc uint64 + var err error + + switch arg := inst.Args[0].(type) { + case ppc64asm.Imm: + pc = uint64(arg) + case ppc64asm.Reg: + if !currentGoroutine || regs == nil { + return nil + } + pc, err = bininfo.Arch.getAsmRegister(regs, int(arg)) + if err != nil { + return nil + } + case ppc64asm.PCRel: + pc = instAddr + uint64(arg) + default: + return nil + } + + file, line, fn := bininfo.PCToLine(pc) + if fn == nil { + return &Location{PC: pc} + } + return &Location{PC: pc, File: file, Line: line, Fn: fn} +} + +type ppc64ArchInst ppc64asm.Inst + +func (inst *ppc64ArchInst) Text(flavour AssemblyFlavour, pc uint64, symLookup func(uint64) (string, uint64)) string { + if inst == nil { + return "?" + } + + var text string + + switch flavour { + case GNUFlavour: + text = ppc64asm.GNUSyntax(ppc64asm.Inst(*inst), pc) + default: + text = ppc64asm.GoSyntax(ppc64asm.Inst(*inst), pc, symLookup) + } + + return text +} + +func (inst *ppc64ArchInst) OpcodeEquals(op uint64) bool { + if inst == nil { + return false + } + return uint64(inst.Op) == op +} + +var ppc64leAsmRegisters = func() map[int]asmRegister { + r := make(map[int]asmRegister) + + // General Purpose Registers: from R0 to R31 + for i := ppc64asm.R0; i <= ppc64asm.R31; i++ { + r[int(i)] = asmRegister{regnum.PPC64LE_R0 + uint64(i-ppc64asm.R0), 0, 0} + } + + // Floating point registers: from F0 to F31 + for i := ppc64asm.F0; i <= ppc64asm.F31; i++ { + r[int(i)] = asmRegister{regnum.PPC64LE_F0 + uint64(i-ppc64asm.F0), 0, 0} + } + + // Vector (Altivec/VMX) registers: from V0 to V31 + for i := ppc64asm.V0; i <= ppc64asm.V31; i++ { + r[int(i)] = asmRegister{regnum.PPC64LE_V0 + uint64(i-ppc64asm.V0), 0, 0} + } + + // Vector Scalar (VSX) registers: from VS0 to VS63 + for i := ppc64asm.VS0; i <= ppc64asm.VS63; i++ { + r[int(i)] = asmRegister{regnum.PPC64LE_VS0 + uint64(i-ppc64asm.VS0), 0, 0} + } + + // Condition Registers: from CR0 to CR7 + for i := ppc64asm.CR0; i <= ppc64asm.CR7; i++ { + r[int(i)] = asmRegister{regnum.PPC64LE_CR0 + uint64(i-ppc64asm.CR0), 0, 0} + } + return r +}() diff --git a/pkg/proc/proc_test.go b/pkg/proc/proc_test.go index f00a10a777..4e5d5ca987 100644 --- a/pkg/proc/proc_test.go +++ b/pkg/proc/proc_test.go @@ -809,6 +809,7 @@ func TestFindReturnAddress(t *testing.T) { } func TestFindReturnAddressTopOfStackFn(t *testing.T) { + skipOn(t, "broken in linux ppc64le", "linux", "ppc64le", "native") protest.AllowRecording(t) withTestProcess("testreturnaddress", t, func(p *proc.Target, grp *proc.TargetGroup, fixture protest.Fixture) { fnName := "runtime.rt0_go" @@ -903,6 +904,7 @@ func (l1 *loc) match(l2 proc.Stackframe) bool { } func TestStacktrace(t *testing.T) { + skipOn(t, "broken - pie mode", "linux", "ppc64le", "native", "pie") stacks := [][]loc{ {{4, "main.stacktraceme"}, {8, "main.func1"}, {16, "main.main"}}, {{4, "main.stacktraceme"}, {8, "main.func1"}, {12, "main.func2"}, {17, "main.main"}}, @@ -987,6 +989,7 @@ func stackMatch(stack []loc, locations []proc.Stackframe, skipRuntime bool) bool func TestStacktraceGoroutine(t *testing.T) { skipOn(t, "broken - cgo stacktraces", "darwin", "arm64") + skipOn(t, "broken - pie mode", "linux", "ppc64le", "native", "pie") mainStack := []loc{{14, "main.stacktraceme"}, {29, "main.main"}} if goversion.VersionAfterOrEqual(runtime.Version(), 1, 11) { @@ -1311,6 +1314,7 @@ func TestVariableEvaluation(t *testing.T) { } func TestFrameEvaluation(t *testing.T) { + skipOn(t, "broken - pie mode", "linux", "ppc64le", "native", "pie") protest.AllowRecording(t) lenient := false if runtime.GOOS == "windows" { @@ -2303,6 +2307,7 @@ func TestNextDeferReturnAndDirectCall(t *testing.T) { } func TestNextPanicAndDirectCall(t *testing.T) { + skipOn(t, "broken - pie mode", "linux", "ppc64le", "native", "pie") // Next should not step into a deferred function if it is called // directly, only if it is called through a panic or a deferreturn. // Here we test the case where the function is called by a panic @@ -2320,6 +2325,7 @@ func TestStepCall(t *testing.T) { } func TestStepCallPtr(t *testing.T) { + skipOn(t, "broken - pie mode", "linux", "ppc64le", "native", "pie") // Tests that Step works correctly when calling functions with a // function pointer. if goversion.VersionAfterOrEqual(runtime.Version(), 1, 11) && !protest.RegabiSupported() { @@ -2339,6 +2345,7 @@ func TestStepCallPtr(t *testing.T) { } func TestStepReturnAndPanic(t *testing.T) { + skipOn(t, "broken - pie mode", "linux", "ppc64le", "native", "pie") // Tests that Step works correctly when returning from functions // and when a deferred function is called when panic'ing. testseq("defercall", contStep, []nextTest{ @@ -2350,6 +2357,7 @@ func TestStepReturnAndPanic(t *testing.T) { } func TestStepDeferReturn(t *testing.T) { + skipOn(t, "broken - pie mode", "linux", "ppc64le", "native", "pie") // Tests that Step works correctly when a deferred function is // called during a return. testseq("defercall", contStep, []nextTest{ @@ -2364,6 +2372,7 @@ func TestStepDeferReturn(t *testing.T) { } func TestStepIgnorePrivateRuntime(t *testing.T) { + skipOn(t, "broken - pie mode", "linux", "ppc64le", "native", "pie") // Tests that Step will ignore calls to private runtime functions // (such as runtime.convT2E in this case) switch { @@ -2742,6 +2751,7 @@ func TestIssue594(t *testing.T) { } func TestStepOutPanicAndDirectCall(t *testing.T) { + skipOn(t, "broken - pie mode", "linux", "ppc64le", "native", "pie") // StepOut should not step into a deferred function if it is called // directly, only if it is called through a panic. // Here we test the case where the function is called by a panic @@ -3170,6 +3180,7 @@ func TestDebugStripped(t *testing.T) { // TODO(derekparker): Add support for Mach-O and PE. skipUnlessOn(t, "linux only", "linux") skipOn(t, "not working on linux/386 with PIE", "linux", "386", "pie") + skipOn(t, "not working on linux/ppc64le when -gcflags=-N -l is passed", "linux", "ppc64le") withTestProcessArgs("testnextprog", t, "", []string{}, protest.LinkStrip, func(p *proc.Target, grp *proc.TargetGroup, f protest.Fixture) { setFunctionBreakpoint(p, t, "main.main") assertNoError(grp.Continue(), t, "Continue") @@ -3308,6 +3319,8 @@ func TestCgoStacktrace(t *testing.T) { } } skipOn(t, "broken - cgo stacktraces", "386") + skipOn(t, "broken - cgo stacktraces", "windows", "arm64") + skipOn(t, "broken - cgo stacktraces", "linux", "ppc64le") if !goversion.VersionAfterOrEqual(runtime.Version(), 1, 21) { skipOn(t, "broken - cgo stacktraces", "windows", "arm64") } @@ -3437,6 +3450,7 @@ func TestCgoSources(t *testing.T) { } func TestSystemstackStacktrace(t *testing.T) { + skipOn(t, "broken", "ppc64le") // check that we can follow a stack switch initiated by runtime.systemstack() withTestProcess("panic", t, func(p *proc.Target, grp *proc.TargetGroup, fixture protest.Fixture) { setFunctionBreakpoint(p, t, "runtime.startpanic_m") @@ -3455,6 +3469,7 @@ func TestSystemstackStacktrace(t *testing.T) { } func TestSystemstackOnRuntimeNewstack(t *testing.T) { + skipOn(t, "broken", "ppc64le") // The bug being tested here manifests as follows: // - set a breakpoint somewhere or interrupt the program with Ctrl-C // - try to look at stacktraces of other goroutines @@ -3692,7 +3707,8 @@ func TestHaltKeepsSteppingBreakpoints(t *testing.T) { } func TestDisassembleGlobalVars(t *testing.T) { - skipOn(t, "broken - global variable symbolication", "arm64") // On ARM64 symLookup can't look up variables due to how they are loaded, see issue #1778 + skipOn(t, "broken - global variable symbolication", "arm64") // On ARM64 symLookup can't look up variables due to how they are loaded, see issue #1778 + skipOn(t, "broken - global variable symbolication", "ppc64le") // See comment on ARM64 above. // On 386 linux when pie, the generated code use __x86.get_pc_thunk to ensure position-independent. // Locate global variable by // `CALL __x86.get_pc_thunk.ax(SB) 0xb0f7f @@ -3878,6 +3894,7 @@ func TestInlinedStacktraceAndVariables(t *testing.T) { } func TestInlineStep(t *testing.T) { + skipOn(t, "broken", "ppc64le") if ver, _ := goversion.Parse(runtime.Version()); ver.Major >= 0 && !ver.AfterOrEqual(goversion.GoVersion{Major: 1, Minor: 10, Rev: -1}) { // Versions of go before 1.10 do not have DWARF information for inlined calls t.Skip("inlining not supported") @@ -4038,6 +4055,7 @@ func TestIssue951(t *testing.T) { } func TestDWZCompression(t *testing.T) { + skipOn(t, "broken", "ppc64le") // If dwz is not available in the system, skip this test if _, err := exec.LookPath("dwz"); err != nil { t.Skip("dwz not installed") @@ -4610,6 +4628,7 @@ func TestCgoStacktrace2(t *testing.T) { skipOn(t, "broken", "386") } skipOn(t, "broken - cgo stacktraces", "darwin", "arm64") + skipOn(t, "broken", "ppc64le") protest.MustHaveCgo(t) // If a panic happens during cgo execution the stacktrace should show the C // function that caused the problem. @@ -4718,6 +4737,7 @@ func TestIssue1795(t *testing.T) { if !goversion.VersionAfterOrEqual(runtime.Version(), 1, 13) { t.Skip("Test not relevant to Go < 1.13") } + skipOn(t, "broken", "ppc64le") withTestProcessArgs("issue1795", t, ".", []string{}, protest.EnableInlining|protest.EnableOptimization, func(p *proc.Target, grp *proc.TargetGroup, fixture protest.Fixture) { assertNoError(grp.Continue(), t, "Continue()") assertLineNumber(p, t, 12, "wrong line number after Continue,") @@ -5149,6 +5169,7 @@ func TestDump(t *testing.T) { if (runtime.GOOS == "darwin" && testBackend == "native") || (runtime.GOOS == "windows" && runtime.GOARCH != "amd64") { t.Skip("not supported") } + skipOn(t, "not implemented", "ppc64le") convertRegisters := func(arch *proc.Arch, dregs op.DwarfRegisters) string { dregs.Reg(^uint64(0)) @@ -5398,6 +5419,7 @@ func TestVariablesWithExternalLinking(t *testing.T) { func TestWatchpointsBasic(t *testing.T) { skipOn(t, "not implemented", "freebsd") skipOn(t, "not implemented", "386") + skipOn(t, "not implemented", "ppc64le") skipOn(t, "see https://github.com/go-delve/delve/issues/2768", "windows") protest.AllowRecording(t) @@ -5458,6 +5480,7 @@ func TestWatchpointCounts(t *testing.T) { skipOn(t, "not implemented", "freebsd") skipOn(t, "not implemented", "386") skipOn(t, "see https://github.com/go-delve/delve/issues/2768", "windows") + skipOn(t, "not implemented", "ppc64le") protest.AllowRecording(t) withTestProcess("databpcountstest", t, func(p *proc.Target, grp *proc.TargetGroup, fixture protest.Fixture) { @@ -5545,6 +5568,7 @@ func TestManualStopWhileStopped(t *testing.T) { } func TestDwrapStartLocation(t *testing.T) { + skipOn(t, "broken - pie mode", "linux", "ppc64le", "native", "pie") // Tests that the start location of a goroutine is unwrapped in Go 1.17 and later. withTestProcess("goroutinestackprog", t, func(p *proc.Target, grp *proc.TargetGroup, fixture protest.Fixture) { setFunctionBreakpoint(p, t, "main.stacktraceme") @@ -5572,6 +5596,7 @@ func TestDwrapStartLocation(t *testing.T) { func TestWatchpointStack(t *testing.T) { skipOn(t, "not implemented", "freebsd") skipOn(t, "not implemented", "386") + skipOn(t, "not implemented", "ppc64le") skipOn(t, "see https://github.com/go-delve/delve/issues/2768", "windows") protest.AllowRecording(t) @@ -5768,13 +5793,15 @@ func TestNilPtrDerefInBreakInstr(t *testing.T) { asmfile = "main_arm64.s" case "386": asmfile = "main_386.s" + case "ppc64le": + asmfile = "main_ppc64le.s" default: t.Fatalf("assembly file for %s not provided", runtime.GOARCH) } withTestProcess("asmnilptr/", t, func(p *proc.Target, grp *proc.TargetGroup, fixture protest.Fixture) { f := filepath.Join(fixture.BuildDir, asmfile) - f = strings.ReplaceAll(f, "\\", "/") + f = strings.Replace(f, "\\", "/", -1) setFileBreakpoint(p, t, f, 5) t.Logf("first continue") assertNoError(grp.Continue(), t, "Continue()") @@ -6042,6 +6069,7 @@ func TestEscapeCheckUnreadable(t *testing.T) { } func TestStepShadowConcurrentBreakpoint(t *testing.T) { + skipOn(t, "broken - pie mode", "linux", "ppc64le", "native", "pie") // Checks that a StepBreakpoint can not shadow a concurrently hit user breakpoint withTestProcess("stepshadow", t, func(p *proc.Target, grp *proc.TargetGroup, fixture protest.Fixture) { break2 := setFunctionBreakpoint(p, t, "main.stacktraceme2") diff --git a/pkg/proc/stack.go b/pkg/proc/stack.go index fb6260bcab..fc3feb007b 100644 --- a/pkg/proc/stack.go +++ b/pkg/proc/stack.go @@ -280,7 +280,7 @@ func (it *stackIterator) switchToGoroutineStack() { it.pc = it.g.PC it.regs.Reg(it.regs.SPRegNum).Uint64Val = it.g.SP it.regs.AddReg(it.regs.BPRegNum, op.DwarfRegisterFromUint64(it.g.BP)) - if it.bi.Arch.Name == "arm64" { + if it.bi.Arch.Name == "arm64" || it.bi.Arch.Name == "ppc64le" { it.regs.Reg(it.regs.LRRegNum).Uint64Val = it.g.LR } } @@ -475,7 +475,7 @@ func (it *stackIterator) advanceRegs() (callFrameRegs op.DwarfRegisters, ret uin // In the following line we copy GDB's behaviour by assuming this is // implicit. // See also the comment in dwarf2_frame_default_init in - // $GDB_SOURCE/dwarf2-frame.c + // $GDB_SOURCE/dwarf2/frame.c callFrameRegs.AddReg(callFrameRegs.SPRegNum, cfareg) for i, regRule := range framectx.Regs { @@ -504,7 +504,7 @@ func (it *stackIterator) advanceRegs() (callFrameRegs op.DwarfRegisters, ret uin } } - if it.bi.Arch.Name == "arm64" { + if it.bi.Arch.Name == "arm64" || it.bi.Arch.Name == "ppc64le" { if ret == 0 && it.regs.Reg(it.regs.LRRegNum) != nil { ret = it.regs.Reg(it.regs.LRRegNum).Uint64Val } diff --git a/pkg/proc/target_exec.go b/pkg/proc/target_exec.go index dae0afae04..630f83ab37 100644 --- a/pkg/proc/target_exec.go +++ b/pkg/proc/target_exec.go @@ -8,8 +8,11 @@ import ( "go/ast" "go/token" "path/filepath" + "runtime" "strings" + "golang.org/x/arch/ppc64/ppc64asm" + "github.com/go-delve/delve/pkg/astutil" "github.com/go-delve/delve/pkg/dwarf/reader" ) @@ -913,7 +916,16 @@ func setStepIntoBreakpoint(dbp *Target, curfn *Function, text []AsmInstruction, return nil } + pc := instr.DestLoc.PC fn := instr.DestLoc.Fn + if runtime.GOARCH == "ppc64le" && instr.Inst.OpcodeEquals(uint64(ppc64asm.BCLRL)) { + regs, err := dbp.CurrentThread().Registers() + if err != nil { + return err + } + lr := regs.LR() + fn = dbp.BinInfo().PCToFunc(lr) + } // Skip unexported runtime functions if !stepIntoUnexportedRuntime && fn != nil && fn.privateRuntime() { @@ -924,8 +936,6 @@ func setStepIntoBreakpoint(dbp *Target, curfn *Function, text []AsmInstruction, // or entire packages from being stepped into with 'step' // those extra checks should be done here. - pc := instr.DestLoc.PC - // Skip InhibitStepInto functions for different arch. if dbp.BinInfo().Arch.inhibitStepInto(dbp.BinInfo(), pc) { return nil diff --git a/pkg/proc/test/support.go b/pkg/proc/test/support.go index 2e882d99ba..7b87ced55c 100644 --- a/pkg/proc/test/support.go +++ b/pkg/proc/test/support.go @@ -310,7 +310,7 @@ func MustSupportFunctionCalls(t *testing.T, testBackend string) { if runtime.GOOS == "darwin" && os.Getenv("TRAVIS") == "true" && runtime.GOARCH == "amd64" { t.Skip("function call injection tests are failing on macOS on Travis-CI (see #1802)") } - if runtime.GOARCH == "386" { + if runtime.GOARCH == "386" || runtime.GOARCH == "ppc64le" { t.Skip(fmt.Errorf("%s does not support FunctionCall for now", runtime.GOARCH)) } if runtime.GOARCH == "arm64" { diff --git a/pkg/proc/variables_test.go b/pkg/proc/variables_test.go index fa317aa7ac..01435e2b78 100644 --- a/pkg/proc/variables_test.go +++ b/pkg/proc/variables_test.go @@ -1462,6 +1462,7 @@ func assertCurrentLocationFunction(p *proc.Target, t *testing.T, fnname string) } func TestPluginVariables(t *testing.T) { + skipOn(t, "broken", "ppc64le") pluginFixtures := protest.WithPlugins(t, protest.AllNonOptimized, "plugin1/", "plugin2/") withTestProcessArgs("plugintest2", t, ".", []string{pluginFixtures[0].Path, pluginFixtures[1].Path}, protest.AllNonOptimized, func(p *proc.Target, grp *proc.TargetGroup, fixture protest.Fixture) { @@ -1544,6 +1545,10 @@ func TestCgoEval(t *testing.T) { t.Skip("cgo doesn't work on darwin/arm64") } + if runtime.GOARCH == "ppc64le" { + t.Skip("skipped on ppc64le: broken") + } + protest.AllowRecording(t) withTestProcess("testvariablescgo/", t, func(p *proc.Target, grp *proc.TargetGroup, fixture protest.Fixture) { assertNoError(grp.Continue(), t, "Continue() returned an error") diff --git a/pkg/terminal/command_test.go b/pkg/terminal/command_test.go index 36ac44e84c..925568ac16 100644 --- a/pkg/terminal/command_test.go +++ b/pkg/terminal/command_test.go @@ -305,6 +305,9 @@ func TestExitStatus(t *testing.T) { } func TestScopePrefix(t *testing.T) { + if runtime.GOARCH == "ppc64le" && buildMode == "pie" { + t.Skip("pie mode broken on ppc64le") + } const goroutinesLinePrefix = " Goroutine " const goroutinesCurLinePrefix = "* Goroutine " test.AllowRecording(t) @@ -873,6 +876,9 @@ func TestIssue1090(t *testing.T) { } func TestPrintContextParkedGoroutine(t *testing.T) { + if runtime.GOARCH == "ppc64le" && buildMode == "pie" { + t.Skip("pie mode broken on ppc64le") + } withTestTerminal("goroutinestackprog", t, func(term *FakeTerminal) { term.MustExec("break stacktraceme") term.MustExec("continue") @@ -946,6 +952,9 @@ func TestOptimizationCheck(t *testing.T) { } func TestTruncateStacktrace(t *testing.T) { + if runtime.GOARCH == "ppc64le" && buildMode == "pie" { + t.Skip("pie mode broken on ppc64le") + } const stacktraceTruncatedMessage = "(truncated)" withTestTerminal("stacktraceprog", t, func(term *FakeTerminal) { term.MustExec("break main.stacktraceme") @@ -966,6 +975,9 @@ func TestTruncateStacktrace(t *testing.T) { func TestIssue1493(t *testing.T) { // The 'regs' command without the '-a' option should only return // general purpose registers. + if runtime.GOARCH == "ppc64le" { + t.Skip("skipping, some registers such as vector registers are currently not loaded") + } withTestTerminal("continuetestprog", t, func(term *FakeTerminal) { r := term.MustExec("regs") nr := len(strings.Split(r, "\n")) @@ -1381,6 +1393,9 @@ func TestTranscript(t *testing.T) { } func TestDisassPosCmd(t *testing.T) { + if runtime.GOARCH == "ppc64le" && buildMode == "pie" { + t.Skip("pie mode broken on ppc64le") + } withTestTerminal("testvariables2", t, func(term *FakeTerminal) { term.MustExec("continue") out := term.MustExec("step-instruction") diff --git a/service/dap/server_test.go b/service/dap/server_test.go index 3b142dca92..c2d8dfebfa 100644 --- a/service/dap/server_test.go +++ b/service/dap/server_test.go @@ -2458,6 +2458,9 @@ func TestGlobalScopeAndVariables(t *testing.T) { // got loaded. It then steps into a function in another package and tests that // the registers were updated by checking PC. func TestRegistersScopeAndVariables(t *testing.T) { + if runtime.GOARCH == "ppc64le" { + t.Skip("skipped on ppc64le: broken") + } runTest(t, "consts", func(client *daptest.Client, fixture protest.Fixture) { runDebugSessionWithBPs(t, client, "launch", // Launch diff --git a/service/debugger/debugger_test.go b/service/debugger/debugger_test.go index 9af7a75fed..3e78257b04 100644 --- a/service/debugger/debugger_test.go +++ b/service/debugger/debugger_test.go @@ -53,6 +53,9 @@ func TestDebugger_LaunchInvalidFormat(t *testing.T) { if runtime.GOARCH == "arm64" && runtime.GOOS == "linux" { os.Setenv("GOARCH", "amd64") } + if runtime.GOARCH == "ppc64le" && runtime.GOOS == "linux" { + os.Setenv("GOARCH", "amd64") + } os.Setenv("GOOS", switchOS[runtime.GOOS]) exepath := filepath.Join(buildtestdir, debugname) if err := gobuild.GoBuild(debugname, []string{buildtestdir}, fmt.Sprintf("-o %s", exepath)); err != nil { diff --git a/service/debugger/debugger_unix_test.go b/service/debugger/debugger_unix_test.go index 07f78833a0..d0bc009ac4 100644 --- a/service/debugger/debugger_unix_test.go +++ b/service/debugger/debugger_unix_test.go @@ -36,6 +36,9 @@ func TestDebugger_LaunchNoExecutablePerm(t *testing.T) { if runtime.GOARCH == "arm64" && runtime.GOOS == "linux" { os.Setenv("GOARCH", "amd64") } + if runtime.GOARCH == "ppc64le" && runtime.GOOS == "linux" { + os.Setenv("GOARCH", "amd64") + } os.Setenv("GOOS", switchOS[runtime.GOOS]) exepath := filepath.Join(buildtestdir, debugname) defer os.Remove(exepath) diff --git a/service/test/integration1_test.go b/service/test/integration1_test.go index 93f4df82c6..9e9dd3ce5a 100644 --- a/service/test/integration1_test.go +++ b/service/test/integration1_test.go @@ -564,6 +564,9 @@ func Test1ClientServer_traceContinue2(t *testing.T) { } func Test1ClientServer_FindLocations(t *testing.T) { + if buildMode == "pie" && runtime.GOARCH == "ppc64le" { + t.Skip("skipped on ppc64le: broken") + } withTestClient1("locationsprog", t, func(c *rpc1.RPCClient) { someFunctionCallAddr := findLocationHelper(t, c, "locationsprog.go:26", false, 1, 0)[0] someFunctionLine1 := findLocationHelper(t, c, "locationsprog.go:27", false, 1, 0)[0] @@ -719,6 +722,9 @@ func Test1ClientServer_FullStacktrace(t *testing.T) { if runtime.GOOS == "darwin" && runtime.GOARCH == "arm64" { t.Skip("cgo doesn't work on darwin/arm64") } + if runtime.GOARCH == "ppc64le" && buildMode == "pie" { + t.Skip("pie mode broken on ppc64le") + } lenient := false if runtime.GOOS == "windows" { @@ -858,6 +864,9 @@ func Test1Issue355(t *testing.T) { } func Test1Disasm(t *testing.T) { + if runtime.GOARCH == "ppc64le" { + t.Skip("skipped on ppc64le: broken") + } // Tests that disassembling by PC, range, and current PC all yield similar results // Tests that disassembly by current PC will return a disassembly containing the instruction at PC // Tests that stepping on a calculated CALL instruction will yield a disassembly that contains the diff --git a/service/test/integration2_test.go b/service/test/integration2_test.go index 6b03a852bd..50f2644949 100644 --- a/service/test/integration2_test.go +++ b/service/test/integration2_test.go @@ -946,6 +946,9 @@ func TestClientServer_traceContinue2(t *testing.T) { } func TestClientServer_FindLocations(t *testing.T) { + if runtime.GOARCH == "ppc64le" && buildMode == "pie" { + t.Skip("pie mode broken on ppc64le") + } withTestClient2("locationsprog", t, func(c service.Client) { someFunctionCallAddr := findLocationHelper(t, c, "locationsprog.go:26", false, 1, 0)[0] someFunctionLine1 := findLocationHelper(t, c, "locationsprog.go:27", false, 1, 0)[0] @@ -1210,6 +1213,9 @@ func TestClientServer_FullStacktrace(t *testing.T) { if runtime.GOOS == "darwin" && runtime.GOARCH == "arm64" { t.Skip("cgo doesn't work on darwin/arm64") } + if runtime.GOARCH == "ppc64le" && buildMode == "pie" { + t.Skip("pie mode broken on ppc64le") + } lenient := false if runtime.GOOS == "windows" { @@ -1362,6 +1368,9 @@ func TestIssue355(t *testing.T) { } func TestDisasm(t *testing.T) { + if runtime.GOARCH == "ppc64le" { + t.Skip("skipped on ppc64le: broken") + } // Tests that disassembling by PC, range, and current PC all yield similar results // Tests that disassembly by current PC will return a disassembly containing the instruction at PC // Tests that stepping on a calculated CALL instruction will yield a disassembly that contains the @@ -2858,6 +2867,9 @@ func assertLine(t *testing.T, state *api.DebuggerState, file string, lineno int) } func TestPluginSuspendedBreakpoint(t *testing.T) { + if runtime.GOARCH == "ppc64le" { + t.Skip("skipped on ppc64le: broken") + } // Tests that breakpoints created in a suspended state will be enabled automatically when a plugin is loaded. pluginFixtures := protest.WithPlugins(t, protest.AllNonOptimized, "plugin1/", "plugin2/") dir, err := filepath.Abs(protest.FindFixturesDir()) diff --git a/vendor/golang.org/x/arch/ppc64/ppc64asm/decode.go b/vendor/golang.org/x/arch/ppc64/ppc64asm/decode.go new file mode 100644 index 0000000000..5f04ff40e4 --- /dev/null +++ b/vendor/golang.org/x/arch/ppc64/ppc64asm/decode.go @@ -0,0 +1,179 @@ +// Copyright 2014 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package ppc64asm + +import ( + "encoding/binary" + "fmt" + "log" +) + +const debugDecode = false + +// instFormat is a decoding rule for one specific instruction form. +// a uint32 instruction ins matches the rule if ins&Mask == Value +// DontCare bits should be zero, but the machine might not reject +// ones in those bits, they are mainly reserved for future expansion +// of the instruction set. +// The Args are stored in the same order as the instruction manual. +type instFormat struct { + Op Op + Mask uint32 + Value uint32 + DontCare uint32 + Args [5]*argField +} + +// argField indicate how to decode an argument to an instruction. +// First parse the value from the BitFields, shift it left by Shift +// bits to get the actual numerical value. +type argField struct { + Type ArgType + Shift uint8 + BitFields +} + +// Parse parses the Arg out from the given binary instruction i. +func (a argField) Parse(i uint32) Arg { + switch a.Type { + default: + return nil + case TypeUnknown: + return nil + case TypeReg: + return R0 + Reg(a.BitFields.Parse(i)) + case TypeCondRegBit: + return Cond0LT + CondReg(a.BitFields.Parse(i)) + case TypeCondRegField: + return CR0 + CondReg(a.BitFields.Parse(i)) + case TypeFPReg: + return F0 + Reg(a.BitFields.Parse(i)) + case TypeVecReg: + return V0 + Reg(a.BitFields.Parse(i)) + case TypeVecSReg: + return VS0 + Reg(a.BitFields.Parse(i)) + case TypeSpReg: + return SpReg(a.BitFields.Parse(i)) + case TypeImmSigned: + return Imm(a.BitFields.ParseSigned(i) << a.Shift) + case TypeImmUnsigned: + return Imm(a.BitFields.Parse(i) << a.Shift) + case TypePCRel: + return PCRel(a.BitFields.ParseSigned(i) << a.Shift) + case TypeLabel: + return Label(a.BitFields.ParseSigned(i) << a.Shift) + case TypeOffset: + return Offset(a.BitFields.ParseSigned(i) << a.Shift) + } +} + +type ArgType int8 + +const ( + TypeUnknown ArgType = iota + TypePCRel // PC-relative address + TypeLabel // absolute address + TypeReg // integer register + TypeCondRegBit // conditional register bit (0-31) + TypeCondRegField // conditional register field (0-7) + TypeFPReg // floating point register + TypeVecReg // vector register + TypeVecSReg // VSX register + TypeSpReg // special register (depends on Op) + TypeImmSigned // signed immediate + TypeImmUnsigned // unsigned immediate/flag/mask, this is the catch-all type + TypeOffset // signed offset in load/store + TypeLast // must be the last one +) + +func (t ArgType) String() string { + switch t { + default: + return fmt.Sprintf("ArgType(%d)", int(t)) + case TypeUnknown: + return "Unknown" + case TypeReg: + return "Reg" + case TypeCondRegBit: + return "CondRegBit" + case TypeCondRegField: + return "CondRegField" + case TypeFPReg: + return "FPReg" + case TypeVecReg: + return "VecReg" + case TypeVecSReg: + return "VecSReg" + case TypeSpReg: + return "SpReg" + case TypeImmSigned: + return "ImmSigned" + case TypeImmUnsigned: + return "ImmUnsigned" + case TypePCRel: + return "PCRel" + case TypeLabel: + return "Label" + case TypeOffset: + return "Offset" + } +} + +func (t ArgType) GoString() string { + s := t.String() + if t > 0 && t < TypeLast { + return "Type" + s + } + return s +} + +var ( + // Errors + errShort = fmt.Errorf("truncated instruction") + errUnknown = fmt.Errorf("unknown instruction") +) + +var decoderCover []bool + +// Decode decodes the leading bytes in src as a single instruction using +// byte order ord. +func Decode(src []byte, ord binary.ByteOrder) (inst Inst, err error) { + if len(src) < 4 { + return inst, errShort + } + if decoderCover == nil { + decoderCover = make([]bool, len(instFormats)) + } + inst.Len = 4 // only 4-byte instructions are supported + ui := ord.Uint32(src[:inst.Len]) + inst.Enc = ui + for i, iform := range instFormats { + if ui&iform.Mask != iform.Value { + continue + } + if ui&iform.DontCare != 0 { + if debugDecode { + log.Printf("Decode(%#x): unused bit is 1 for Op %s", ui, iform.Op) + } + // to match GNU objdump (libopcodes), we ignore don't care bits + } + for i, argfield := range iform.Args { + if argfield == nil { + break + } + inst.Args[i] = argfield.Parse(ui) + } + inst.Op = iform.Op + if debugDecode { + log.Printf("%#x: search entry %d", ui, i) + continue + } + break + } + if inst.Op == 0 && inst.Enc != 0 { + return inst, errUnknown + } + return inst, nil +} diff --git a/vendor/golang.org/x/arch/ppc64/ppc64asm/doc.go b/vendor/golang.org/x/arch/ppc64/ppc64asm/doc.go new file mode 100644 index 0000000000..5f4ef7d10a --- /dev/null +++ b/vendor/golang.org/x/arch/ppc64/ppc64asm/doc.go @@ -0,0 +1,6 @@ +// Copyright 2014 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +// Package ppc64asm implements decoding of 64-bit PowerPC machine code. +package ppc64asm diff --git a/vendor/golang.org/x/arch/ppc64/ppc64asm/field.go b/vendor/golang.org/x/arch/ppc64/ppc64asm/field.go new file mode 100644 index 0000000000..26a4fdf1a0 --- /dev/null +++ b/vendor/golang.org/x/arch/ppc64/ppc64asm/field.go @@ -0,0 +1,84 @@ +// Copyright 2014 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package ppc64asm + +import ( + "fmt" + "strings" +) + +// A BitField is a bit-field in a 32-bit word. +// Bits are counted from 0 from the MSB to 31 as the LSB. +type BitField struct { + Offs uint8 // the offset of the left-most bit. + Bits uint8 // length in bits. +} + +func (b BitField) String() string { + if b.Bits > 1 { + return fmt.Sprintf("[%d:%d]", b.Offs, int(b.Offs+b.Bits)-1) + } else if b.Bits == 1 { + return fmt.Sprintf("[%d]", b.Offs) + } else { + return fmt.Sprintf("[%d, len=0]", b.Offs) + } +} + +// Parse extracts the bitfield b from i, and return it as an unsigned integer. +// Parse will panic if b is invalid. +func (b BitField) Parse(i uint32) uint32 { + if b.Bits > 32 || b.Bits == 0 || b.Offs > 31 || b.Offs+b.Bits > 32 { + panic(fmt.Sprintf("invalid bitfiled %v", b)) + } + return (i >> (32 - b.Offs - b.Bits)) & ((1 << b.Bits) - 1) +} + +// ParseSigned extracts the bitfield b from i, and return it as a signed integer. +// ParseSigned will panic if b is invalid. +func (b BitField) ParseSigned(i uint32) int32 { + u := int32(b.Parse(i)) + return u << (32 - b.Bits) >> (32 - b.Bits) +} + +// BitFields is a series of BitFields representing a single number. +type BitFields []BitField + +func (bs BitFields) String() string { + ss := make([]string, len(bs)) + for i, bf := range bs { + ss[i] = bf.String() + } + return fmt.Sprintf("<%s>", strings.Join(ss, "|")) +} + +func (bs *BitFields) Append(b BitField) { + *bs = append(*bs, b) +} + +// parse extracts the bitfields from i, concatenate them and return the result +// as an unsigned integer and the total length of all the bitfields. +// parse will panic if any bitfield in b is invalid, but it doesn't check if +// the sequence of bitfields is reasonable. +func (bs BitFields) parse(i uint32) (u uint32, Bits uint8) { + for _, b := range bs { + u = (u << b.Bits) | b.Parse(i) + Bits += b.Bits + } + return u, Bits +} + +// Parse extracts the bitfields from i, concatenate them and return the result +// as an unsigned integer. Parse will panic if any bitfield in b is invalid. +func (bs BitFields) Parse(i uint32) uint32 { + u, _ := bs.parse(i) + return u +} + +// Parse extracts the bitfields from i, concatenate them and return the result +// as a signed integer. Parse will panic if any bitfield in b is invalid. +func (bs BitFields) ParseSigned(i uint32) int32 { + u, l := bs.parse(i) + return int32(u) << (32 - l) >> (32 - l) +} diff --git a/vendor/golang.org/x/arch/ppc64/ppc64asm/gnu.go b/vendor/golang.org/x/arch/ppc64/ppc64asm/gnu.go new file mode 100644 index 0000000000..fc2916408c --- /dev/null +++ b/vendor/golang.org/x/arch/ppc64/ppc64asm/gnu.go @@ -0,0 +1,267 @@ +// Copyright 2014 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package ppc64asm + +import ( + "bytes" + "fmt" + "strings" +) + +var ( + condBit = [4]string{"lt", "gt", "eq", "so"} + condBitNeg = [4]string{"ge", "le", "ne", "so"} +) + +// GNUSyntax returns the GNU assembler syntax for the instruction, as defined by GNU binutils. +// This form typically matches the syntax defined in the Power ISA Reference Manual. +func GNUSyntax(inst Inst, pc uint64) string { + var buf bytes.Buffer + // When there are all 0s, identify them as the disassembler + // in binutils would. + if inst.Enc == 0 { + return ".long 0x0" + } else if inst.Op == 0 { + return "error: unknown instruction" + } + + PC := pc + // Special handling for some ops + startArg := 0 + sep := " " + switch inst.Op.String() { + case "bc": + bo := gnuArg(&inst, 0, inst.Args[0], PC) + bi := inst.Args[1] + switch bi := bi.(type) { + case CondReg: + if bi >= CR0 { + if bi == CR0 && bo == "16" { + buf.WriteString("bdnz") + } + buf.WriteString(fmt.Sprintf("bc cr%d", bi-CR0)) + } + cr := bi / 4 + switch bo { + case "4": + bit := condBitNeg[(bi-Cond0LT)%4] + if cr == 0 { + buf.WriteString(fmt.Sprintf("b%s", bit)) + } else { + buf.WriteString(fmt.Sprintf("b%s cr%d,", bit, cr)) + sep = "" + } + case "12": + bit := condBit[(bi-Cond0LT)%4] + if cr == 0 { + buf.WriteString(fmt.Sprintf("b%s", bit)) + } else { + buf.WriteString(fmt.Sprintf("b%s cr%d,", bit, cr)) + sep = "" + } + case "8": + bit := condBit[(bi-Cond0LT)%4] + sep = "" + if cr == 0 { + buf.WriteString(fmt.Sprintf("bdnzt %s,", bit)) + } else { + buf.WriteString(fmt.Sprintf("bdnzt cr%d,%s,", cr, bit)) + } + case "16": + if cr == 0 && bi == Cond0LT { + buf.WriteString("bdnz") + } else { + buf.WriteString(fmt.Sprintf("bdnz cr%d,", cr)) + sep = "" + } + } + startArg = 2 + default: + fmt.Printf("Unexpected bi: %d for bc with bo: %s\n", bi, bo) + } + startArg = 2 + case "mtspr": + opcode := inst.Op.String() + buf.WriteString(opcode[0:2]) + switch spr := inst.Args[0].(type) { + case SpReg: + switch spr { + case 1: + buf.WriteString("xer") + startArg = 1 + case 8: + buf.WriteString("lr") + startArg = 1 + case 9: + buf.WriteString("ctr") + startArg = 1 + default: + buf.WriteString("spr") + } + default: + buf.WriteString("spr") + } + + case "mfspr": + opcode := inst.Op.String() + buf.WriteString(opcode[0:2]) + arg := inst.Args[0] + switch spr := inst.Args[1].(type) { + case SpReg: + switch spr { + case 1: + buf.WriteString("xer ") + buf.WriteString(gnuArg(&inst, 0, arg, PC)) + startArg = 2 + case 8: + buf.WriteString("lr ") + buf.WriteString(gnuArg(&inst, 0, arg, PC)) + startArg = 2 + case 9: + buf.WriteString("ctr ") + buf.WriteString(gnuArg(&inst, 0, arg, PC)) + startArg = 2 + case 268: + buf.WriteString("tb ") + buf.WriteString(gnuArg(&inst, 0, arg, PC)) + startArg = 2 + default: + buf.WriteString("spr") + } + default: + buf.WriteString("spr") + } + + default: + buf.WriteString(inst.Op.String()) + } + for i, arg := range inst.Args[:] { + if arg == nil { + break + } + if i < startArg { + continue + } + text := gnuArg(&inst, i, arg, PC) + if text == "" { + continue + } + buf.WriteString(sep) + sep = "," + buf.WriteString(text) + } + return buf.String() +} + +// gnuArg formats arg (which is the argIndex's arg in inst) according to GNU rules. +// NOTE: because GNUSyntax is the only caller of this func, and it receives a copy +// of inst, it's ok to modify inst.Args here. +func gnuArg(inst *Inst, argIndex int, arg Arg, pc uint64) string { + // special cases for load/store instructions + if _, ok := arg.(Offset); ok { + if argIndex+1 == len(inst.Args) || inst.Args[argIndex+1] == nil { + panic(fmt.Errorf("wrong table: offset not followed by register")) + } + } + switch arg := arg.(type) { + case Reg: + if isLoadStoreOp(inst.Op) && argIndex == 1 && arg == R0 { + return "0" + } + return arg.String() + case CondReg: + // The CondReg can either be found in a CMP, where the + // condition register field is being set, or in an instruction + // like a branch or isel that is testing a bit in a condition + // register field. + if arg == CR0 && strings.HasPrefix(inst.Op.String(), "cmp") { + return "" // don't show cr0 for cmp instructions + } else if arg >= CR0 { + return fmt.Sprintf("cr%d", int(arg-CR0)) + } + bit := condBit[(arg-Cond0LT)%4] + if arg <= Cond0SO { + return bit + } + return fmt.Sprintf("%s cr%d", bit, int(arg-Cond0LT)/4) + case Imm: + return fmt.Sprintf("%d", arg) + case SpReg: + switch int(arg) { + case 1: + return "xer" + case 8: + return "lr" + case 9: + return "ctr" + case 268: + return "tb" + default: + return fmt.Sprintf("%d", int(arg)) + } + case PCRel: + // If the arg is 0, use the relative address format. + // Otherwise the pc is meaningful, use absolute address. + if int(arg) == 0 { + return fmt.Sprintf(".%+#x", int(arg)) + } + addr := pc + uint64(int64(arg)) + return fmt.Sprintf("%#x", addr) + case Label: + return fmt.Sprintf("%#x", uint32(arg)) + case Offset: + reg := inst.Args[argIndex+1].(Reg) + removeArg(inst, argIndex+1) + if reg == R0 { + return fmt.Sprintf("%d(0)", int(arg)) + } + return fmt.Sprintf("%d(r%d)", int(arg), reg-R0) + } + return fmt.Sprintf("???(%v)", arg) +} + +// removeArg removes the arg in inst.Args[index]. +func removeArg(inst *Inst, index int) { + for i := index; i < len(inst.Args); i++ { + if i+1 < len(inst.Args) { + inst.Args[i] = inst.Args[i+1] + } else { + inst.Args[i] = nil + } + } +} + +// isLoadStoreOp returns true if op is a load or store instruction +func isLoadStoreOp(op Op) bool { + switch op { + case LBZ, LBZU, LBZX, LBZUX: + return true + case LHZ, LHZU, LHZX, LHZUX: + return true + case LHA, LHAU, LHAX, LHAUX: + return true + case LWZ, LWZU, LWZX, LWZUX: + return true + case LWA, LWAX, LWAUX: + return true + case LD, LDU, LDX, LDUX: + return true + case LQ: + return true + case STB, STBU, STBX, STBUX: + return true + case STH, STHU, STHX, STHUX: + return true + case STW, STWU, STWX, STWUX: + return true + case STD, STDU, STDX, STDUX: + return true + case STQ: + return true + case LHBRX, LWBRX, STHBRX, STWBRX: + return true + } + return false +} diff --git a/vendor/golang.org/x/arch/ppc64/ppc64asm/inst.go b/vendor/golang.org/x/arch/ppc64/ppc64asm/inst.go new file mode 100644 index 0000000000..870522a10b --- /dev/null +++ b/vendor/golang.org/x/arch/ppc64/ppc64asm/inst.go @@ -0,0 +1,344 @@ +// Copyright 2014 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package ppc64asm + +import ( + "bytes" + "fmt" +) + +type Inst struct { + Op Op // Opcode mnemonic + Enc uint32 // Raw encoding bits + Len int // Length of encoding in bytes. + Args Args // Instruction arguments, in Power ISA manual order. +} + +func (i Inst) String() string { + var buf bytes.Buffer + buf.WriteString(i.Op.String()) + for j, arg := range i.Args { + if arg == nil { + break + } + if j == 0 { + buf.WriteString(" ") + } else { + buf.WriteString(", ") + } + buf.WriteString(arg.String()) + } + return buf.String() +} + +// An Op is an instruction operation. +type Op uint16 + +func (o Op) String() string { + if int(o) >= len(opstr) || opstr[o] == "" { + return fmt.Sprintf("Op(%d)", int(o)) + } + return opstr[o] +} + +// An Arg is a single instruction argument, one of these types: Reg, CondReg, SpReg, Imm, PCRel, Label, or Offset. +type Arg interface { + IsArg() + String() string +} + +// An Args holds the instruction arguments. +// If an instruction has fewer than 4 arguments, +// the final elements in the array are nil. +type Args [5]Arg + +// A Reg is a single register. The zero value means R0, not the absence of a register. +// It also includes special registers. +type Reg uint16 + +const ( + _ Reg = iota + R0 + R1 + R2 + R3 + R4 + R5 + R6 + R7 + R8 + R9 + R10 + R11 + R12 + R13 + R14 + R15 + R16 + R17 + R18 + R19 + R20 + R21 + R22 + R23 + R24 + R25 + R26 + R27 + R28 + R29 + R30 + R31 + F0 + F1 + F2 + F3 + F4 + F5 + F6 + F7 + F8 + F9 + F10 + F11 + F12 + F13 + F14 + F15 + F16 + F17 + F18 + F19 + F20 + F21 + F22 + F23 + F24 + F25 + F26 + F27 + F28 + F29 + F30 + F31 + V0 // VSX extension, F0 is V0[0:63]. + V1 + V2 + V3 + V4 + V5 + V6 + V7 + V8 + V9 + V10 + V11 + V12 + V13 + V14 + V15 + V16 + V17 + V18 + V19 + V20 + V21 + V22 + V23 + V24 + V25 + V26 + V27 + V28 + V29 + V30 + V31 + VS0 + VS1 + VS2 + VS3 + VS4 + VS5 + VS6 + VS7 + VS8 + VS9 + VS10 + VS11 + VS12 + VS13 + VS14 + VS15 + VS16 + VS17 + VS18 + VS19 + VS20 + VS21 + VS22 + VS23 + VS24 + VS25 + VS26 + VS27 + VS28 + VS29 + VS30 + VS31 + VS32 + VS33 + VS34 + VS35 + VS36 + VS37 + VS38 + VS39 + VS40 + VS41 + VS42 + VS43 + VS44 + VS45 + VS46 + VS47 + VS48 + VS49 + VS50 + VS51 + VS52 + VS53 + VS54 + VS55 + VS56 + VS57 + VS58 + VS59 + VS60 + VS61 + VS62 + VS63 +) + +func (Reg) IsArg() {} +func (r Reg) String() string { + switch { + case R0 <= r && r <= R31: + return fmt.Sprintf("r%d", int(r-R0)) + case F0 <= r && r <= F31: + return fmt.Sprintf("f%d", int(r-F0)) + case V0 <= r && r <= V31: + return fmt.Sprintf("v%d", int(r-V0)) + case VS0 <= r && r <= VS63: + return fmt.Sprintf("vs%d", int(r-VS0)) + default: + return fmt.Sprintf("Reg(%d)", int(r)) + } +} + +// CondReg is a bit or field in the condition register. +type CondReg int8 + +const ( + _ CondReg = iota + // Condition Regster bits + Cond0LT + Cond0GT + Cond0EQ + Cond0SO + Cond1LT + Cond1GT + Cond1EQ + Cond1SO + Cond2LT + Cond2GT + Cond2EQ + Cond2SO + Cond3LT + Cond3GT + Cond3EQ + Cond3SO + Cond4LT + Cond4GT + Cond4EQ + Cond4SO + Cond5LT + Cond5GT + Cond5EQ + Cond5SO + Cond6LT + Cond6GT + Cond6EQ + Cond6SO + Cond7LT + Cond7GT + Cond7EQ + Cond7SO + // Condition Register Fields + CR0 + CR1 + CR2 + CR3 + CR4 + CR5 + CR6 + CR7 +) + +func (CondReg) IsArg() {} +func (c CondReg) String() string { + switch { + default: + return fmt.Sprintf("CondReg(%d)", int(c)) + case c >= CR0: + return fmt.Sprintf("CR%d", int(c-CR0)) + case c >= Cond0LT && c < CR0: + return fmt.Sprintf("Cond%d%s", int((c-Cond0LT)/4), [4]string{"LT", "GT", "EQ", "SO"}[(c-Cond0LT)%4]) + } +} + +// SpReg is a special register, its meaning depends on Op. +type SpReg uint16 + +const ( + SpRegZero SpReg = 0 +) + +func (SpReg) IsArg() {} +func (s SpReg) String() string { + return fmt.Sprintf("SpReg(%d)", int(s)) +} + +// PCRel is a PC-relative offset, used only in branch instructions. +type PCRel int32 + +func (PCRel) IsArg() {} +func (r PCRel) String() string { + return fmt.Sprintf("PC%+#x", int32(r)) +} + +// A Label is a code (text) address, used only in absolute branch instructions. +type Label uint32 + +func (Label) IsArg() {} +func (l Label) String() string { + return fmt.Sprintf("%#x", uint32(l)) +} + +// Imm represents an immediate number. +type Imm int32 + +func (Imm) IsArg() {} +func (i Imm) String() string { + return fmt.Sprintf("%d", int32(i)) +} + +// Offset represents a memory offset immediate. +type Offset int32 + +func (Offset) IsArg() {} +func (o Offset) String() string { + return fmt.Sprintf("%+d", int32(o)) +} diff --git a/vendor/golang.org/x/arch/ppc64/ppc64asm/plan9.go b/vendor/golang.org/x/arch/ppc64/ppc64asm/plan9.go new file mode 100644 index 0000000000..d039d9d500 --- /dev/null +++ b/vendor/golang.org/x/arch/ppc64/ppc64asm/plan9.go @@ -0,0 +1,245 @@ +// Copyright 2015 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package ppc64asm + +import ( + "fmt" + "strings" +) + +// GoSyntax returns the Go assembler syntax for the instruction. +// The pc is the program counter of the first instruction, used for expanding +// PC-relative addresses into absolute ones. +// The symname function queries the symbol table for the program +// being disassembled. It returns the name and base address of the symbol +// containing the target, if any; otherwise it returns "", 0. +func GoSyntax(inst Inst, pc uint64, symname func(uint64) (string, uint64)) string { + if symname == nil { + symname = func(uint64) (string, uint64) { return "", 0 } + } + if inst.Op == 0 && inst.Enc == 0 { + return "WORD $0" + } else if inst.Op == 0 { + return "?" + } + var args []string + for i, a := range inst.Args[:] { + if a == nil { + break + } + if s := plan9Arg(&inst, i, pc, a, symname); s != "" { + // In the case for some BC instructions, a CondReg arg has + // both the CR and the branch condition encoded in its value. + // plan9Arg will return a string with the string representation + // of these values separated by a blank that will be treated + // as 2 args from this point on. + if strings.IndexByte(s, ' ') > 0 { + t := strings.Split(s, " ") + args = append(args, t[0]) + args = append(args, t[1]) + } else { + args = append(args, s) + } + } + } + var op string + op = plan9OpMap[inst.Op] + if op == "" { + op = strings.ToUpper(inst.Op.String()) + if op[len(op)-1] == '.' { + op = op[:len(op)-1] + "CC" + } + } + // laid out the instruction + switch inst.Op { + default: // dst, sA, sB, ... + if len(args) == 0 { + return op + } else if len(args) == 1 { + return fmt.Sprintf("%s %s", op, args[0]) + } + args = append(args, args[0]) + return op + " " + strings.Join(args[1:], ",") + case SYNC: + if args[0] == "$1" { + return "LWSYNC" + } + return "HWSYNC" + + case ISEL: + return "ISEL " + args[3] + "," + args[1] + "," + args[2] + "," + args[0] + + // store instructions always have the memory operand at the end, no need to reorder + // indexed stores handled separately + case STB, STBU, + STH, STHU, + STW, STWU, + STD, STDU, + STQ: + return op + " " + strings.Join(args, ",") + + case CMPD, CMPDI, CMPLD, CMPLDI, CMPW, CMPWI, CMPLW, CMPLWI: + if len(args) == 2 { + return op + " " + args[0] + "," + args[1] + } else if len(args) == 3 { + return op + " " + args[0] + "," + args[1] + "," + args[2] + } + return op + " " + args[0] + " ??" + + case LIS: + return "ADDIS $0," + args[1] + "," + args[0] + // store instructions with index registers + case STBX, STBUX, STHX, STHUX, STWX, STWUX, STDX, STDUX, + STHBRX, STWBRX, STDBRX, STSWX, STFSX, STFSUX, STFDX, STFDUX, STFIWX, STFDPX: + return "MOV" + op[2:len(op)-1] + " " + args[0] + ",(" + args[2] + ")(" + args[1] + ")" + + case STDCXCC, STWCXCC, STHCXCC, STBCXCC: + return op + " " + args[0] + ",(" + args[2] + ")(" + args[1] + ")" + + case STXVD2X, STXVW4X: + return op + " " + args[0] + ",(" + args[2] + ")(" + args[1] + ")" + + // load instructions with index registers + case LBZX, LBZUX, LHZX, LHZUX, LWZX, LWZUX, LDX, LDUX, + LHBRX, LWBRX, LDBRX, LSWX, LFSX, LFSUX, LFDX, LFDUX, LFIWAX, LFIWZX: + return "MOV" + op[1:len(op)-1] + " (" + args[2] + ")(" + args[1] + ")," + args[0] + + case LDARX, LWARX, LHARX, LBARX: + return op + " (" + args[2] + ")(" + args[1] + ")," + args[0] + + case LXVD2X, LXVW4X: + return op + " (" + args[2] + ")(" + args[1] + ")," + args[0] + + case DCBT, DCBTST, DCBZ, DCBST: + return op + " (" + args[1] + ")" + + // branch instructions needs additional handling + case BCLR: + if int(inst.Args[0].(Imm))&20 == 20 { // unconditional + return "RET" + } + return op + " " + strings.Join(args, ", ") + case BC: + if int(inst.Args[0].(Imm))&0x1c == 12 { // jump on cond bit set + if len(args) == 4 { + return fmt.Sprintf("B%s %s,%s", args[1], args[2], args[3]) + } + return fmt.Sprintf("B%s %s", args[1], args[2]) + } else if int(inst.Args[0].(Imm))&0x1c == 4 && revCondMap[args[1]] != "" { // jump on cond bit not set + if len(args) == 4 { + return fmt.Sprintf("B%s %s,%s", revCondMap[args[1]], args[2], args[3]) + } + return fmt.Sprintf("B%s %s", revCondMap[args[1]], args[2]) + } + return op + " " + strings.Join(args, ",") + case BCCTR: + if int(inst.Args[0].(Imm))&20 == 20 { // unconditional + return "BR (CTR)" + } + return op + " " + strings.Join(args, ", ") + case BCCTRL: + if int(inst.Args[0].(Imm))&20 == 20 { // unconditional + return "BL (CTR)" + } + return op + " " + strings.Join(args, ",") + case BCA, BCL, BCLA, BCLRL, BCTAR, BCTARL: + return op + " " + strings.Join(args, ",") + } +} + +// plan9Arg formats arg (which is the argIndex's arg in inst) according to Plan 9 rules. +// NOTE: because Plan9Syntax is the only caller of this func, and it receives a copy +// of inst, it's ok to modify inst.Args here. +func plan9Arg(inst *Inst, argIndex int, pc uint64, arg Arg, symname func(uint64) (string, uint64)) string { + // special cases for load/store instructions + if _, ok := arg.(Offset); ok { + if argIndex+1 == len(inst.Args) || inst.Args[argIndex+1] == nil { + panic(fmt.Errorf("wrong table: offset not followed by register")) + } + } + switch arg := arg.(type) { + case Reg: + if isLoadStoreOp(inst.Op) && argIndex == 1 && arg == R0 { + return "0" + } + if arg == R30 { + return "g" + } + return strings.ToUpper(arg.String()) + case CondReg: + // This op is left as its numerical value, not mapped onto CR + condition + if inst.Op == ISEL { + return fmt.Sprintf("$%d", (arg - Cond0LT)) + } + if arg == CR0 && strings.HasPrefix(inst.Op.String(), "cmp") { + return "" // don't show cr0 for cmp instructions + } else if arg >= CR0 { + return fmt.Sprintf("CR%d", int(arg-CR0)) + } + bit := [4]string{"LT", "GT", "EQ", "SO"}[(arg-Cond0LT)%4] + if arg <= Cond0SO { + return bit + } + return fmt.Sprintf("%s CR%d", bit, int(arg-Cond0LT)/4) + case Imm: + return fmt.Sprintf("$%d", arg) + case SpReg: + switch arg { + case 8: + return "LR" + case 9: + return "CTR" + } + return fmt.Sprintf("SPR(%d)", int(arg)) + case PCRel: + addr := pc + uint64(int64(arg)) + if s, base := symname(addr); s != "" && base == addr { + return fmt.Sprintf("%s(SB)", s) + } + return fmt.Sprintf("%#x", addr) + case Label: + return fmt.Sprintf("%#x", int(arg)) + case Offset: + reg := inst.Args[argIndex+1].(Reg) + removeArg(inst, argIndex+1) + if reg == R0 { + return fmt.Sprintf("%d(0)", int(arg)) + } + return fmt.Sprintf("%d(R%d)", int(arg), reg-R0) + } + return fmt.Sprintf("???(%v)", arg) +} + +// revCondMap maps a conditional register bit to its inverse, if possible. +var revCondMap = map[string]string{ + "LT": "GE", "GT": "LE", "EQ": "NE", +} + +// plan9OpMap maps an Op to its Plan 9 mnemonics, if different than its GNU mnemonics. +var plan9OpMap = map[Op]string{ + LWARX: "LWAR", + LDARX: "LDAR", + LHARX: "LHAR", + LBARX: "LBAR", + ADDI: "ADD", + SRADI: "SRAD", + SUBF: "SUB", + LI: "MOVD", + LBZ: "MOVBZ", STB: "MOVB", + LBZU: "MOVBZU", STBU: "MOVBU", + LHZ: "MOVHZ", LHA: "MOVH", STH: "MOVH", + LHZU: "MOVHZU", STHU: "MOVHU", + LWZ: "MOVWZ", LWA: "MOVW", STW: "MOVW", + LWZU: "MOVWZU", STWU: "MOVWU", + LD: "MOVD", STD: "MOVD", + LDU: "MOVDU", STDU: "MOVDU", + CMPD: "CMP", CMPDI: "CMP", + CMPW: "CMPW", CMPWI: "CMPW", + CMPLD: "CMPU", CMPLDI: "CMPU", + CMPLW: "CMPWU", CMPLWI: "CMPWU", + MTSPR: "MOVD", MFSPR: "MOVD", // the width is ambiguous for SPRs + B: "BR", + BL: "CALL", +} diff --git a/vendor/golang.org/x/arch/ppc64/ppc64asm/tables.go b/vendor/golang.org/x/arch/ppc64/ppc64asm/tables.go new file mode 100644 index 0000000000..f536926dbc --- /dev/null +++ b/vendor/golang.org/x/arch/ppc64/ppc64asm/tables.go @@ -0,0 +1,5494 @@ +// DO NOT EDIT +// generated by: ppc64map -fmt=decoder ../pp64.csv + +package ppc64asm + +const ( + _ Op = iota + CNTLZW + CNTLZWCC + B + BA + BL + BLA + BC + BCA + BCL + BCLA + BCLR + BCLRL + BCCTR + BCCTRL + BCTAR + BCTARL + CRAND + CROR + CRNAND + CRXOR + CRNOR + CRANDC + MCRF + CREQV + CRORC + SC + CLRBHRB + MFBHRBE + LBZ + LBZU + LBZX + LBZUX + LHZ + LHZU + LHZX + LHZUX + LHA + LHAU + LHAX + LHAUX + LWZ + LWZU + LWZX + LWZUX + LWA + LWAX + LWAUX + LD + LDU + LDX + LDUX + STB + STBU + STBX + STBUX + STH + STHU + STHX + STHUX + STW + STWU + STWX + STWUX + STD + STDU + STDX + STDUX + LQ + STQ + LHBRX + LWBRX + STHBRX + STWBRX + LDBRX + STDBRX + LMW + STMW + LSWI + LSWX + STSWI + STSWX + LI + ADDI + LIS + ADDIS + ADD + ADDCC + ADDO + ADDOCC + ADDIC + SUBF + SUBFCC + SUBFO + SUBFOCC + ADDICCC + SUBFIC + ADDC + ADDCCC + ADDCO + ADDCOCC + SUBFC + SUBFCCC + SUBFCO + SUBFCOCC + ADDE + ADDECC + ADDEO + ADDEOCC + ADDME + ADDMECC + ADDMEO + ADDMEOCC + SUBFE + SUBFECC + SUBFEO + SUBFEOCC + SUBFME + SUBFMECC + SUBFMEO + SUBFMEOCC + ADDZE + ADDZECC + ADDZEO + ADDZEOCC + SUBFZE + SUBFZECC + SUBFZEO + SUBFZEOCC + NEG + NEGCC + NEGO + NEGOCC + MULLI + MULLW + MULLWCC + MULLWO + MULLWOCC + MULHW + MULHWCC + MULHWU + MULHWUCC + DIVW + DIVWCC + DIVWO + DIVWOCC + DIVWU + DIVWUCC + DIVWUO + DIVWUOCC + DIVWE + DIVWECC + DIVWEO + DIVWEOCC + DIVWEU + DIVWEUCC + DIVWEUO + DIVWEUOCC + MULLD + MULLDCC + MULLDO + MULLDOCC + MULHDU + MULHDUCC + MULHD + MULHDCC + DIVD + DIVDCC + DIVDO + DIVDOCC + DIVDU + DIVDUCC + DIVDUO + DIVDUOCC + DIVDE + DIVDECC + DIVDEO + DIVDEOCC + DIVDEU + DIVDEUCC + DIVDEUO + DIVDEUOCC + CMPWI + CMPDI + CMPW + CMPD + CMPLWI + CMPLDI + CMPLW + CMPLD + TWI + TW + TDI + ISEL + TD + ANDICC + ANDISCC + ORI + ORIS + XORI + XORIS + AND + ANDCC + XOR + XORCC + NAND + NANDCC + OR + ORCC + NOR + NORCC + ANDC + ANDCCC + EXTSB + EXTSBCC + EQV + EQVCC + ORC + ORCCC + EXTSH + EXTSHCC + CMPB + POPCNTB + POPCNTW + PRTYD + PRTYW + EXTSW + EXTSWCC + CNTLZD + CNTLZDCC + POPCNTD + BPERMD + RLWINM + RLWINMCC + RLWNM + RLWNMCC + RLWIMI + RLWIMICC + RLDICL + RLDICLCC + RLDICR + RLDICRCC + RLDIC + RLDICCC + RLDCL + RLDCLCC + RLDCR + RLDCRCC + RLDIMI + RLDIMICC + SLW + SLWCC + SRW + SRWCC + SRAWI + SRAWICC + SRAW + SRAWCC + SLD + SLDCC + SRD + SRDCC + SRADI + SRADICC + SRAD + SRADCC + CDTBCD + CBCDTD + ADDG6S + MTSPR + MFSPR + MTCRF + MFCR + MTSLE + MFVSRD + MFVSRWZ + MTVSRD + MTVSRWA + MTVSRWZ + MTOCRF + MFOCRF + MCRXR + MTDCRUX + MFDCRUX + LFS + LFSU + LFSX + LFSUX + LFD + LFDU + LFDX + LFDUX + LFIWAX + LFIWZX + STFS + STFSU + STFSX + STFSUX + STFD + STFDU + STFDX + STFDUX + STFIWX + LFDP + LFDPX + STFDP + STFDPX + FMR + FMRCC + FABS + FABSCC + FNABS + FNABSCC + FNEG + FNEGCC + FCPSGN + FCPSGNCC + FMRGEW + FMRGOW + FADD + FADDCC + FADDS + FADDSCC + FSUB + FSUBCC + FSUBS + FSUBSCC + FMUL + FMULCC + FMULS + FMULSCC + FDIV + FDIVCC + FDIVS + FDIVSCC + FSQRT + FSQRTCC + FSQRTS + FSQRTSCC + FRE + FRECC + FRES + FRESCC + FRSQRTE + FRSQRTECC + FRSQRTES + FRSQRTESCC + FTDIV + FTSQRT + FMADD + FMADDCC + FMADDS + FMADDSCC + FMSUB + FMSUBCC + FMSUBS + FMSUBSCC + FNMADD + FNMADDCC + FNMADDS + FNMADDSCC + FNMSUB + FNMSUBCC + FNMSUBS + FNMSUBSCC + FRSP + FRSPCC + FCTID + FCTIDCC + FCTIDZ + FCTIDZCC + FCTIDU + FCTIDUCC + FCTIDUZ + FCTIDUZCC + FCTIW + FCTIWCC + FCTIWZ + FCTIWZCC + FCTIWU + FCTIWUCC + FCTIWUZ + FCTIWUZCC + FCFID + FCFIDCC + FCFIDU + FCFIDUCC + FCFIDS + FCFIDSCC + FCFIDUS + FCFIDUSCC + FRIN + FRINCC + FRIZ + FRIZCC + FRIP + FRIPCC + FRIM + FRIMCC + FCMPU + FCMPO + FSEL + FSELCC + MFFS + MFFSCC + MCRFS + MTFSFI + MTFSFICC + MTFSF + MTFSFCC + MTFSB0 + MTFSB0CC + MTFSB1 + MTFSB1CC + LVEBX + LVEHX + LVEWX + LVX + LVXL + STVEBX + STVEHX + STVEWX + STVX + STVXL + LVSL + LVSR + VPKPX + VPKSDSS + VPKSDUS + VPKSHSS + VPKSHUS + VPKSWSS + VPKSWUS + VPKUDUM + VPKUDUS + VPKUHUM + VPKUHUS + VPKUWUM + VPKUWUS + VUPKHPX + VUPKLPX + VUPKHSB + VUPKHSH + VUPKHSW + VUPKLSB + VUPKLSH + VUPKLSW + VMRGHB + VMRGHH + VMRGLB + VMRGLH + VMRGHW + VMRGLW + VMRGEW + VMRGOW + VSPLTB + VSPLTH + VSPLTW + VSPLTISB + VSPLTISH + VSPLTISW + VPERM + VSEL + VSL + VSLDOI + VSLO + VSR + VSRO + VADDCUW + VADDSBS + VADDSHS + VADDSWS + VADDUBM + VADDUDM + VADDUHM + VADDUWM + VADDUBS + VADDUHS + VADDUWS + VADDUQM + VADDEUQM + VADDCUQ + VADDECUQ + VSUBCUW + VSUBSBS + VSUBSHS + VSUBSWS + VSUBUBM + VSUBUDM + VSUBUHM + VSUBUWM + VSUBUBS + VSUBUHS + VSUBUWS + VSUBUQM + VSUBEUQM + VSUBCUQ + VSUBECUQ + VMULESB + VMULEUB + VMULOSB + VMULOUB + VMULESH + VMULEUH + VMULOSH + VMULOUH + VMULESW + VMULEUW + VMULOSW + VMULOUW + VMULUWM + VMHADDSHS + VMHRADDSHS + VMLADDUHM + VMSUMUBM + VMSUMMBM + VMSUMSHM + VMSUMSHS + VMSUMUHM + VMSUMUHS + VSUMSWS + VSUM2SWS + VSUM4SBS + VSUM4SHS + VSUM4UBS + VAVGSB + VAVGSH + VAVGSW + VAVGUB + VAVGUW + VAVGUH + VMAXSB + VMAXSD + VMAXUB + VMAXUD + VMAXSH + VMAXSW + VMAXUH + VMAXUW + VMINSB + VMINSD + VMINUB + VMINUD + VMINSH + VMINSW + VMINUH + VMINUW + VCMPEQUB + VCMPEQUBCC + VCMPEQUH + VCMPEQUHCC + VCMPEQUW + VCMPEQUWCC + VCMPEQUD + VCMPEQUDCC + VCMPGTSB + VCMPGTSBCC + VCMPGTSD + VCMPGTSDCC + VCMPGTSH + VCMPGTSHCC + VCMPGTSW + VCMPGTSWCC + VCMPGTUB + VCMPGTUBCC + VCMPGTUD + VCMPGTUDCC + VCMPGTUH + VCMPGTUHCC + VCMPGTUW + VCMPGTUWCC + VAND + VANDC + VEQV + VNAND + VORC + VNOR + VOR + VXOR + VRLB + VRLH + VRLW + VRLD + VSLB + VSLH + VSLW + VSLD + VSRB + VSRH + VSRW + VSRD + VSRAB + VSRAH + VSRAW + VSRAD + VADDFP + VSUBFP + VMADDFP + VNMSUBFP + VMAXFP + VMINFP + VCTSXS + VCTUXS + VCFSX + VCFUX + VRFIM + VRFIN + VRFIP + VRFIZ + VCMPBFP + VCMPBFPCC + VCMPEQFP + VCMPEQFPCC + VCMPGEFP + VCMPGEFPCC + VCMPGTFP + VCMPGTFPCC + VEXPTEFP + VLOGEFP + VREFP + VRSQRTEFP + VCIPHER + VCIPHERLAST + VNCIPHER + VNCIPHERLAST + VSBOX + VSHASIGMAD + VSHASIGMAW + VPMSUMB + VPMSUMD + VPMSUMH + VPMSUMW + VPERMXOR + VGBBD + VCLZB + VCLZH + VCLZW + VCLZD + VPOPCNTB + VPOPCNTD + VPOPCNTH + VPOPCNTW + VBPERMQ + BCDADDCC + BCDSUBCC + MTVSCR + MFVSCR + DADD + DADDCC + DSUB + DSUBCC + DMUL + DMULCC + DDIV + DDIVCC + DCMPU + DCMPO + DTSTDC + DTSTDG + DTSTEX + DTSTSF + DQUAI + DQUAICC + DQUA + DQUACC + DRRND + DRRNDCC + DRINTX + DRINTXCC + DRINTN + DRINTNCC + DCTDP + DCTDPCC + DCTQPQ + DCTQPQCC + DRSP + DRSPCC + DRDPQ + DRDPQCC + DCFFIX + DCFFIXCC + DCFFIXQ + DCFFIXQCC + DCTFIX + DCTFIXCC + DDEDPD + DDEDPDCC + DENBCD + DENBCDCC + DXEX + DXEXCC + DIEX + DIEXCC + DSCLI + DSCLICC + DSCRI + DSCRICC + LXSDX + LXSIWAX + LXSIWZX + LXSSPX + LXVD2X + LXVDSX + LXVW4X + STXSDX + STXSIWX + STXSSPX + STXVD2X + STXVW4X + XSABSDP + XSADDDP + XSADDSP + XSCMPODP + XSCMPUDP + XSCPSGNDP + XSCVDPSP + XSCVDPSPN + XSCVDPSXDS + XSCVDPSXWS + XSCVDPUXDS + XSCVDPUXWS + XSCVSPDP + XSCVSPDPN + XSCVSXDDP + XSCVSXDSP + XSCVUXDDP + XSCVUXDSP + XSDIVDP + XSDIVSP + XSMADDADP + XSMADDASP + XSMAXDP + XSMINDP + XSMSUBADP + XSMSUBASP + XSMULDP + XSMULSP + XSNABSDP + XSNEGDP + XSNMADDADP + XSNMADDASP + XSNMSUBADP + XSNMSUBASP + XSRDPI + XSRDPIC + XSRDPIM + XSRDPIP + XSRDPIZ + XSREDP + XSRESP + XSRSP + XSRSQRTEDP + XSRSQRTESP + XSSQRTDP + XSSQRTSP + XSSUBDP + XSSUBSP + XSTDIVDP + XSTSQRTDP + XVABSDP + XVABSSP + XVADDDP + XVADDSP + XVCMPEQDP + XVCMPEQDPCC + XVCMPEQSP + XVCMPEQSPCC + XVCMPGEDP + XVCMPGEDPCC + XVCMPGESP + XVCMPGESPCC + XVCMPGTDP + XVCMPGTDPCC + XVCMPGTSP + XVCMPGTSPCC + XVCPSGNDP + XVCPSGNSP + XVCVDPSP + XVCVDPSXDS + XVCVDPSXWS + XVCVDPUXDS + XVCVDPUXWS + XVCVSPDP + XVCVSPSXDS + XVCVSPSXWS + XVCVSPUXDS + XVCVSPUXWS + XVCVSXDDP + XVCVSXDSP + XVCVSXWDP + XVCVSXWSP + XVCVUXDDP + XVCVUXDSP + XVCVUXWDP + XVCVUXWSP + XVDIVDP + XVDIVSP + XVMADDADP + XVMADDASP + XVMAXDP + XVMAXSP + XVMINDP + XVMINSP + XVMSUBADP + XVMSUBASP + XVMULDP + XVMULSP + XVNABSDP + XVNABSSP + XVNEGDP + XVNEGSP + XVNMADDADP + XVNMADDASP + XVNMSUBADP + XVNMSUBASP + XVRDPI + XVRDPIC + XVRDPIM + XVRDPIP + XVRDPIZ + XVREDP + XVRESP + XVRSPI + XVRSPIC + XVRSPIM + XVRSPIP + XVRSPIZ + XVRSQRTEDP + XVRSQRTESP + XVSQRTDP + XVSQRTSP + XVSUBDP + XVSUBSP + XVTDIVDP + XVTDIVSP + XVTSQRTDP + XVTSQRTSP + XXLAND + XXLANDC + XXLEQV + XXLNAND + XXLORC + XXLNOR + XXLOR + XXLXOR + XXMRGHW + XXMRGLW + XXPERMDI + XXSEL + XXSLDWI + XXSPLTW + BRINC + EVABS + EVADDIW + EVADDSMIAAW + EVADDSSIAAW + EVADDUMIAAW + EVADDUSIAAW + EVADDW + EVAND + EVCMPEQ + EVANDC + EVCMPGTS + EVCMPGTU + EVCMPLTU + EVCMPLTS + EVCNTLSW + EVCNTLZW + EVDIVWS + EVDIVWU + EVEQV + EVEXTSB + EVEXTSH + EVLDD + EVLDH + EVLDDX + EVLDHX + EVLDW + EVLHHESPLAT + EVLDWX + EVLHHESPLATX + EVLHHOSSPLAT + EVLHHOUSPLAT + EVLHHOSSPLATX + EVLHHOUSPLATX + EVLWHE + EVLWHOS + EVLWHEX + EVLWHOSX + EVLWHOU + EVLWHSPLAT + EVLWHOUX + EVLWHSPLATX + EVLWWSPLAT + EVMERGEHI + EVLWWSPLATX + EVMERGELO + EVMERGEHILO + EVMHEGSMFAA + EVMERGELOHI + EVMHEGSMFAN + EVMHEGSMIAA + EVMHEGUMIAA + EVMHEGSMIAN + EVMHEGUMIAN + EVMHESMF + EVMHESMFAAW + EVMHESMFA + EVMHESMFANW + EVMHESMI + EVMHESMIAAW + EVMHESMIA + EVMHESMIANW + EVMHESSF + EVMHESSFA + EVMHESSFAAW + EVMHESSFANW + EVMHESSIAAW + EVMHESSIANW + EVMHEUMI + EVMHEUMIAAW + EVMHEUMIA + EVMHEUMIANW + EVMHEUSIAAW + EVMHEUSIANW + EVMHOGSMFAA + EVMHOGSMIAA + EVMHOGSMFAN + EVMHOGSMIAN + EVMHOGUMIAA + EVMHOSMF + EVMHOGUMIAN + EVMHOSMFA + EVMHOSMFAAW + EVMHOSMI + EVMHOSMFANW + EVMHOSMIA + EVMHOSMIAAW + EVMHOSMIANW + EVMHOSSF + EVMHOSSFA + EVMHOSSFAAW + EVMHOSSFANW + EVMHOSSIAAW + EVMHOUMI + EVMHOSSIANW + EVMHOUMIA + EVMHOUMIAAW + EVMHOUSIAAW + EVMHOUMIANW + EVMHOUSIANW + EVMRA + EVMWHSMF + EVMWHSMI + EVMWHSMFA + EVMWHSMIA + EVMWHSSF + EVMWHUMI + EVMWHSSFA + EVMWHUMIA + EVMWLSMIAAW + EVMWLSSIAAW + EVMWLSMIANW + EVMWLSSIANW + EVMWLUMI + EVMWLUMIAAW + EVMWLUMIA + EVMWLUMIANW + EVMWLUSIAAW + EVMWSMF + EVMWLUSIANW + EVMWSMFA + EVMWSMFAA + EVMWSMI + EVMWSMIAA + EVMWSMFAN + EVMWSMIA + EVMWSMIAN + EVMWSSF + EVMWSSFA + EVMWSSFAA + EVMWUMI + EVMWSSFAN + EVMWUMIA + EVMWUMIAA + EVNAND + EVMWUMIAN + EVNEG + EVNOR + EVORC + EVOR + EVRLW + EVRLWI + EVSEL + EVRNDW + EVSLW + EVSPLATFI + EVSRWIS + EVSLWI + EVSPLATI + EVSRWIU + EVSRWS + EVSTDD + EVSRWU + EVSTDDX + EVSTDH + EVSTDW + EVSTDHX + EVSTDWX + EVSTWHE + EVSTWHO + EVSTWWE + EVSTWHEX + EVSTWHOX + EVSTWWEX + EVSTWWO + EVSUBFSMIAAW + EVSTWWOX + EVSUBFSSIAAW + EVSUBFUMIAAW + EVSUBFUSIAAW + EVSUBFW + EVSUBIFW + EVXOR + EVFSABS + EVFSNABS + EVFSNEG + EVFSADD + EVFSMUL + EVFSSUB + EVFSDIV + EVFSCMPGT + EVFSCMPLT + EVFSCMPEQ + EVFSTSTGT + EVFSTSTLT + EVFSTSTEQ + EVFSCFSI + EVFSCFSF + EVFSCFUI + EVFSCFUF + EVFSCTSI + EVFSCTUI + EVFSCTSIZ + EVFSCTUIZ + EVFSCTSF + EVFSCTUF + EFSABS + EFSNEG + EFSNABS + EFSADD + EFSMUL + EFSSUB + EFSDIV + EFSCMPGT + EFSCMPLT + EFSCMPEQ + EFSTSTGT + EFSTSTLT + EFSTSTEQ + EFSCFSI + EFSCFSF + EFSCTSI + EFSCFUI + EFSCFUF + EFSCTUI + EFSCTSIZ + EFSCTSF + EFSCTUIZ + EFSCTUF + EFDABS + EFDNEG + EFDNABS + EFDADD + EFDMUL + EFDSUB + EFDDIV + EFDCMPGT + EFDCMPEQ + EFDCMPLT + EFDTSTGT + EFDTSTLT + EFDCFSI + EFDTSTEQ + EFDCFUI + EFDCFSID + EFDCFSF + EFDCFUF + EFDCFUID + EFDCTSI + EFDCTUI + EFDCTSIDZ + EFDCTUIDZ + EFDCTSIZ + EFDCTSF + EFDCTUF + EFDCTUIZ + EFDCFS + EFSCFD + DLMZB + DLMZBCC + MACCHW + MACCHWCC + MACCHWO + MACCHWOCC + MACCHWS + MACCHWSCC + MACCHWSO + MACCHWSOCC + MACCHWU + MACCHWUCC + MACCHWUO + MACCHWUOCC + MACCHWSU + MACCHWSUCC + MACCHWSUO + MACCHWSUOCC + MACHHW + MACHHWCC + MACHHWO + MACHHWOCC + MACHHWS + MACHHWSCC + MACHHWSO + MACHHWSOCC + MACHHWU + MACHHWUCC + MACHHWUO + MACHHWUOCC + MACHHWSU + MACHHWSUCC + MACHHWSUO + MACHHWSUOCC + MACLHW + MACLHWCC + MACLHWO + MACLHWOCC + MACLHWS + MACLHWSCC + MACLHWSO + MACLHWSOCC + MACLHWU + MACLHWUCC + MACLHWUO + MACLHWUOCC + MULCHW + MULCHWCC + MACLHWSU + MACLHWSUCC + MACLHWSUO + MACLHWSUOCC + MULCHWU + MULCHWUCC + MULHHW + MULHHWCC + MULLHW + MULLHWCC + MULHHWU + MULHHWUCC + MULLHWU + MULLHWUCC + NMACCHW + NMACCHWCC + NMACCHWO + NMACCHWOCC + NMACCHWS + NMACCHWSCC + NMACCHWSO + NMACCHWSOCC + NMACHHW + NMACHHWCC + NMACHHWO + NMACHHWOCC + NMACHHWS + NMACHHWSCC + NMACHHWSO + NMACHHWSOCC + NMACLHW + NMACLHWCC + NMACLHWO + NMACLHWOCC + NMACLHWS + NMACLHWSCC + NMACLHWSO + NMACLHWSOCC + ICBI + ICBT + DCBA + DCBT + DCBTST + DCBZ + DCBST + DCBF + ISYNC + LBARX + LHARX + LWARX + STBCXCC + STHCXCC + STWCXCC + LDARX + STDCXCC + LQARX + STQCXCC + SYNC + EIEIO + MBAR + WAIT + TBEGINCC + TENDCC + TABORTCC + TABORTWCCC + TABORTWCICC + TABORTDCCC + TABORTDCICC + TSRCC + TCHECK + MFTB + RFEBB + LBDX + LHDX + LWDX + LDDX + LFDDX + STBDX + STHDX + STWDX + STDDX + STFDDX + DSN + ECIWX + ECOWX + RFID + HRFID + DOZE + NAP + SLEEP + RVWINKLE + LBZCIX + LWZCIX + LHZCIX + LDCIX + STBCIX + STWCIX + STHCIX + STDCIX + TRECLAIMCC + TRECHKPTCC + MTMSR + MTMSRD + MFMSR + SLBIE + SLBIA + SLBMTE + SLBMFEV + SLBMFEE + SLBFEECC + MTSR + MTSRIN + MFSR + MFSRIN + TLBIE + TLBIEL + TLBIA + TLBSYNC + MSGSND + MSGCLR + MSGSNDP + MSGCLRP + MTTMR + RFI + RFCI + RFDI + RFMCI + RFGI + EHPRIV + MTDCR + MTDCRX + MFDCR + MFDCRX + WRTEE + WRTEEI + LBEPX + LHEPX + LWEPX + LDEPX + STBEPX + STHEPX + STWEPX + STDEPX + DCBSTEP + DCBTEP + DCBFEP + DCBTSTEP + ICBIEP + DCBZEP + LFDEPX + STFDEPX + EVLDDEPX + EVSTDDEPX + LVEPX + LVEPXL + STVEPX + STVEPXL + DCBI + DCBLQCC + ICBLQCC + DCBTLS + DCBTSTLS + ICBTLS + ICBLC + DCBLC + TLBIVAX + TLBILX + TLBSX + TLBSRXCC + TLBRE + TLBWE + DNH + DCI + ICI + DCREAD + ICREAD + MFPMR + MTPMR + ADDEX + DARN + MADDHD + MADDHDU + MADDLD + CMPRB + CMPEQB + EXTSWSLI + EXTSWSLICC + MFVSRLD + MTVSRDD + MTVSRWS + MCRXRX + COPY + PASTECC +) + +var opstr = [...]string{ + CNTLZW: "cntlzw", + CNTLZWCC: "cntlzw.", + B: "b", + BA: "ba", + BL: "bl", + BLA: "bla", + BC: "bc", + BCA: "bca", + BCL: "bcl", + BCLA: "bcla", + BCLR: "bclr", + BCLRL: "bclrl", + BCCTR: "bcctr", + BCCTRL: "bcctrl", + BCTAR: "bctar", + BCTARL: "bctarl", + CRAND: "crand", + CROR: "cror", + CRNAND: "crnand", + CRXOR: "crxor", + CRNOR: "crnor", + CRANDC: "crandc", + MCRF: "mcrf", + CREQV: "creqv", + CRORC: "crorc", + SC: "sc", + CLRBHRB: "clrbhrb", + MFBHRBE: "mfbhrbe", + LBZ: "lbz", + LBZU: "lbzu", + LBZX: "lbzx", + LBZUX: "lbzux", + LHZ: "lhz", + LHZU: "lhzu", + LHZX: "lhzx", + LHZUX: "lhzux", + LHA: "lha", + LHAU: "lhau", + LHAX: "lhax", + LHAUX: "lhaux", + LWZ: "lwz", + LWZU: "lwzu", + LWZX: "lwzx", + LWZUX: "lwzux", + LWA: "lwa", + LWAX: "lwax", + LWAUX: "lwaux", + LD: "ld", + LDU: "ldu", + LDX: "ldx", + LDUX: "ldux", + STB: "stb", + STBU: "stbu", + STBX: "stbx", + STBUX: "stbux", + STH: "sth", + STHU: "sthu", + STHX: "sthx", + STHUX: "sthux", + STW: "stw", + STWU: "stwu", + STWX: "stwx", + STWUX: "stwux", + STD: "std", + STDU: "stdu", + STDX: "stdx", + STDUX: "stdux", + LQ: "lq", + STQ: "stq", + LHBRX: "lhbrx", + LWBRX: "lwbrx", + STHBRX: "sthbrx", + STWBRX: "stwbrx", + LDBRX: "ldbrx", + STDBRX: "stdbrx", + LMW: "lmw", + STMW: "stmw", + LSWI: "lswi", + LSWX: "lswx", + STSWI: "stswi", + STSWX: "stswx", + LI: "li", + ADDI: "addi", + LIS: "lis", + ADDIS: "addis", + ADD: "add", + ADDCC: "add.", + ADDO: "addo", + ADDOCC: "addo.", + ADDIC: "addic", + SUBF: "subf", + SUBFCC: "subf.", + SUBFO: "subfo", + SUBFOCC: "subfo.", + ADDICCC: "addic.", + SUBFIC: "subfic", + ADDC: "addc", + ADDCCC: "addc.", + ADDCO: "addco", + ADDCOCC: "addco.", + SUBFC: "subfc", + SUBFCCC: "subfc.", + SUBFCO: "subfco", + SUBFCOCC: "subfco.", + ADDE: "adde", + ADDECC: "adde.", + ADDEO: "addeo", + ADDEOCC: "addeo.", + ADDME: "addme", + ADDMECC: "addme.", + ADDMEO: "addmeo", + ADDMEOCC: "addmeo.", + SUBFE: "subfe", + SUBFECC: "subfe.", + SUBFEO: "subfeo", + SUBFEOCC: "subfeo.", + SUBFME: "subfme", + SUBFMECC: "subfme.", + SUBFMEO: "subfmeo", + SUBFMEOCC: "subfmeo.", + ADDZE: "addze", + ADDZECC: "addze.", + ADDZEO: "addzeo", + ADDZEOCC: "addzeo.", + SUBFZE: "subfze", + SUBFZECC: "subfze.", + SUBFZEO: "subfzeo", + SUBFZEOCC: "subfzeo.", + NEG: "neg", + NEGCC: "neg.", + NEGO: "nego", + NEGOCC: "nego.", + MULLI: "mulli", + MULLW: "mullw", + MULLWCC: "mullw.", + MULLWO: "mullwo", + MULLWOCC: "mullwo.", + MULHW: "mulhw", + MULHWCC: "mulhw.", + MULHWU: "mulhwu", + MULHWUCC: "mulhwu.", + DIVW: "divw", + DIVWCC: "divw.", + DIVWO: "divwo", + DIVWOCC: "divwo.", + DIVWU: "divwu", + DIVWUCC: "divwu.", + DIVWUO: "divwuo", + DIVWUOCC: "divwuo.", + DIVWE: "divwe", + DIVWECC: "divwe.", + DIVWEO: "divweo", + DIVWEOCC: "divweo.", + DIVWEU: "divweu", + DIVWEUCC: "divweu.", + DIVWEUO: "divweuo", + DIVWEUOCC: "divweuo.", + MULLD: "mulld", + MULLDCC: "mulld.", + MULLDO: "mulldo", + MULLDOCC: "mulldo.", + MULHDU: "mulhdu", + MULHDUCC: "mulhdu.", + MULHD: "mulhd", + MULHDCC: "mulhd.", + DIVD: "divd", + DIVDCC: "divd.", + DIVDO: "divdo", + DIVDOCC: "divdo.", + DIVDU: "divdu", + DIVDUCC: "divdu.", + DIVDUO: "divduo", + DIVDUOCC: "divduo.", + DIVDE: "divde", + DIVDECC: "divde.", + DIVDEO: "divdeo", + DIVDEOCC: "divdeo.", + DIVDEU: "divdeu", + DIVDEUCC: "divdeu.", + DIVDEUO: "divdeuo", + DIVDEUOCC: "divdeuo.", + CMPWI: "cmpwi", + CMPDI: "cmpdi", + CMPW: "cmpw", + CMPD: "cmpd", + CMPLWI: "cmplwi", + CMPLDI: "cmpldi", + CMPLW: "cmplw", + CMPLD: "cmpld", + TWI: "twi", + TW: "tw", + TDI: "tdi", + ISEL: "isel", + TD: "td", + ANDICC: "andi.", + ANDISCC: "andis.", + ORI: "ori", + ORIS: "oris", + XORI: "xori", + XORIS: "xoris", + AND: "and", + ANDCC: "and.", + XOR: "xor", + XORCC: "xor.", + NAND: "nand", + NANDCC: "nand.", + OR: "or", + ORCC: "or.", + NOR: "nor", + NORCC: "nor.", + ANDC: "andc", + ANDCCC: "andc.", + EXTSB: "extsb", + EXTSBCC: "extsb.", + EQV: "eqv", + EQVCC: "eqv.", + ORC: "orc", + ORCCC: "orc.", + EXTSH: "extsh", + EXTSHCC: "extsh.", + CMPB: "cmpb", + POPCNTB: "popcntb", + POPCNTW: "popcntw", + PRTYD: "prtyd", + PRTYW: "prtyw", + EXTSW: "extsw", + EXTSWCC: "extsw.", + CNTLZD: "cntlzd", + CNTLZDCC: "cntlzd.", + POPCNTD: "popcntd", + BPERMD: "bpermd", + RLWINM: "rlwinm", + RLWINMCC: "rlwinm.", + RLWNM: "rlwnm", + RLWNMCC: "rlwnm.", + RLWIMI: "rlwimi", + RLWIMICC: "rlwimi.", + RLDICL: "rldicl", + RLDICLCC: "rldicl.", + RLDICR: "rldicr", + RLDICRCC: "rldicr.", + RLDIC: "rldic", + RLDICCC: "rldic.", + RLDCL: "rldcl", + RLDCLCC: "rldcl.", + RLDCR: "rldcr", + RLDCRCC: "rldcr.", + RLDIMI: "rldimi", + RLDIMICC: "rldimi.", + SLW: "slw", + SLWCC: "slw.", + SRW: "srw", + SRWCC: "srw.", + SRAWI: "srawi", + SRAWICC: "srawi.", + SRAW: "sraw", + SRAWCC: "sraw.", + SLD: "sld", + SLDCC: "sld.", + SRD: "srd", + SRDCC: "srd.", + SRADI: "sradi", + SRADICC: "sradi.", + SRAD: "srad", + SRADCC: "srad.", + CDTBCD: "cdtbcd", + CBCDTD: "cbcdtd", + ADDG6S: "addg6s", + MTSPR: "mtspr", + MFSPR: "mfspr", + MTCRF: "mtcrf", + MFCR: "mfcr", + MTSLE: "mtsle", + MFVSRD: "mfvsrd", + MFVSRWZ: "mfvsrwz", + MTVSRD: "mtvsrd", + MTVSRWA: "mtvsrwa", + MTVSRWZ: "mtvsrwz", + MTOCRF: "mtocrf", + MFOCRF: "mfocrf", + MCRXR: "mcrxr", + MTDCRUX: "mtdcrux", + MFDCRUX: "mfdcrux", + LFS: "lfs", + LFSU: "lfsu", + LFSX: "lfsx", + LFSUX: "lfsux", + LFD: "lfd", + LFDU: "lfdu", + LFDX: "lfdx", + LFDUX: "lfdux", + LFIWAX: "lfiwax", + LFIWZX: "lfiwzx", + STFS: "stfs", + STFSU: "stfsu", + STFSX: "stfsx", + STFSUX: "stfsux", + STFD: "stfd", + STFDU: "stfdu", + STFDX: "stfdx", + STFDUX: "stfdux", + STFIWX: "stfiwx", + LFDP: "lfdp", + LFDPX: "lfdpx", + STFDP: "stfdp", + STFDPX: "stfdpx", + FMR: "fmr", + FMRCC: "fmr.", + FABS: "fabs", + FABSCC: "fabs.", + FNABS: "fnabs", + FNABSCC: "fnabs.", + FNEG: "fneg", + FNEGCC: "fneg.", + FCPSGN: "fcpsgn", + FCPSGNCC: "fcpsgn.", + FMRGEW: "fmrgew", + FMRGOW: "fmrgow", + FADD: "fadd", + FADDCC: "fadd.", + FADDS: "fadds", + FADDSCC: "fadds.", + FSUB: "fsub", + FSUBCC: "fsub.", + FSUBS: "fsubs", + FSUBSCC: "fsubs.", + FMUL: "fmul", + FMULCC: "fmul.", + FMULS: "fmuls", + FMULSCC: "fmuls.", + FDIV: "fdiv", + FDIVCC: "fdiv.", + FDIVS: "fdivs", + FDIVSCC: "fdivs.", + FSQRT: "fsqrt", + FSQRTCC: "fsqrt.", + FSQRTS: "fsqrts", + FSQRTSCC: "fsqrts.", + FRE: "fre", + FRECC: "fre.", + FRES: "fres", + FRESCC: "fres.", + FRSQRTE: "frsqrte", + FRSQRTECC: "frsqrte.", + FRSQRTES: "frsqrtes", + FRSQRTESCC: "frsqrtes.", + FTDIV: "ftdiv", + FTSQRT: "ftsqrt", + FMADD: "fmadd", + FMADDCC: "fmadd.", + FMADDS: "fmadds", + FMADDSCC: "fmadds.", + FMSUB: "fmsub", + FMSUBCC: "fmsub.", + FMSUBS: "fmsubs", + FMSUBSCC: "fmsubs.", + FNMADD: "fnmadd", + FNMADDCC: "fnmadd.", + FNMADDS: "fnmadds", + FNMADDSCC: "fnmadds.", + FNMSUB: "fnmsub", + FNMSUBCC: "fnmsub.", + FNMSUBS: "fnmsubs", + FNMSUBSCC: "fnmsubs.", + FRSP: "frsp", + FRSPCC: "frsp.", + FCTID: "fctid", + FCTIDCC: "fctid.", + FCTIDZ: "fctidz", + FCTIDZCC: "fctidz.", + FCTIDU: "fctidu", + FCTIDUCC: "fctidu.", + FCTIDUZ: "fctiduz", + FCTIDUZCC: "fctiduz.", + FCTIW: "fctiw", + FCTIWCC: "fctiw.", + FCTIWZ: "fctiwz", + FCTIWZCC: "fctiwz.", + FCTIWU: "fctiwu", + FCTIWUCC: "fctiwu.", + FCTIWUZ: "fctiwuz", + FCTIWUZCC: "fctiwuz.", + FCFID: "fcfid", + FCFIDCC: "fcfid.", + FCFIDU: "fcfidu", + FCFIDUCC: "fcfidu.", + FCFIDS: "fcfids", + FCFIDSCC: "fcfids.", + FCFIDUS: "fcfidus", + FCFIDUSCC: "fcfidus.", + FRIN: "frin", + FRINCC: "frin.", + FRIZ: "friz", + FRIZCC: "friz.", + FRIP: "frip", + FRIPCC: "frip.", + FRIM: "frim", + FRIMCC: "frim.", + FCMPU: "fcmpu", + FCMPO: "fcmpo", + FSEL: "fsel", + FSELCC: "fsel.", + MFFS: "mffs", + MFFSCC: "mffs.", + MCRFS: "mcrfs", + MTFSFI: "mtfsfi", + MTFSFICC: "mtfsfi.", + MTFSF: "mtfsf", + MTFSFCC: "mtfsf.", + MTFSB0: "mtfsb0", + MTFSB0CC: "mtfsb0.", + MTFSB1: "mtfsb1", + MTFSB1CC: "mtfsb1.", + LVEBX: "lvebx", + LVEHX: "lvehx", + LVEWX: "lvewx", + LVX: "lvx", + LVXL: "lvxl", + STVEBX: "stvebx", + STVEHX: "stvehx", + STVEWX: "stvewx", + STVX: "stvx", + STVXL: "stvxl", + LVSL: "lvsl", + LVSR: "lvsr", + VPKPX: "vpkpx", + VPKSDSS: "vpksdss", + VPKSDUS: "vpksdus", + VPKSHSS: "vpkshss", + VPKSHUS: "vpkshus", + VPKSWSS: "vpkswss", + VPKSWUS: "vpkswus", + VPKUDUM: "vpkudum", + VPKUDUS: "vpkudus", + VPKUHUM: "vpkuhum", + VPKUHUS: "vpkuhus", + VPKUWUM: "vpkuwum", + VPKUWUS: "vpkuwus", + VUPKHPX: "vupkhpx", + VUPKLPX: "vupklpx", + VUPKHSB: "vupkhsb", + VUPKHSH: "vupkhsh", + VUPKHSW: "vupkhsw", + VUPKLSB: "vupklsb", + VUPKLSH: "vupklsh", + VUPKLSW: "vupklsw", + VMRGHB: "vmrghb", + VMRGHH: "vmrghh", + VMRGLB: "vmrglb", + VMRGLH: "vmrglh", + VMRGHW: "vmrghw", + VMRGLW: "vmrglw", + VMRGEW: "vmrgew", + VMRGOW: "vmrgow", + VSPLTB: "vspltb", + VSPLTH: "vsplth", + VSPLTW: "vspltw", + VSPLTISB: "vspltisb", + VSPLTISH: "vspltish", + VSPLTISW: "vspltisw", + VPERM: "vperm", + VSEL: "vsel", + VSL: "vsl", + VSLDOI: "vsldoi", + VSLO: "vslo", + VSR: "vsr", + VSRO: "vsro", + VADDCUW: "vaddcuw", + VADDSBS: "vaddsbs", + VADDSHS: "vaddshs", + VADDSWS: "vaddsws", + VADDUBM: "vaddubm", + VADDUDM: "vaddudm", + VADDUHM: "vadduhm", + VADDUWM: "vadduwm", + VADDUBS: "vaddubs", + VADDUHS: "vadduhs", + VADDUWS: "vadduws", + VADDUQM: "vadduqm", + VADDEUQM: "vaddeuqm", + VADDCUQ: "vaddcuq", + VADDECUQ: "vaddecuq", + VSUBCUW: "vsubcuw", + VSUBSBS: "vsubsbs", + VSUBSHS: "vsubshs", + VSUBSWS: "vsubsws", + VSUBUBM: "vsububm", + VSUBUDM: "vsubudm", + VSUBUHM: "vsubuhm", + VSUBUWM: "vsubuwm", + VSUBUBS: "vsububs", + VSUBUHS: "vsubuhs", + VSUBUWS: "vsubuws", + VSUBUQM: "vsubuqm", + VSUBEUQM: "vsubeuqm", + VSUBCUQ: "vsubcuq", + VSUBECUQ: "vsubecuq", + VMULESB: "vmulesb", + VMULEUB: "vmuleub", + VMULOSB: "vmulosb", + VMULOUB: "vmuloub", + VMULESH: "vmulesh", + VMULEUH: "vmuleuh", + VMULOSH: "vmulosh", + VMULOUH: "vmulouh", + VMULESW: "vmulesw", + VMULEUW: "vmuleuw", + VMULOSW: "vmulosw", + VMULOUW: "vmulouw", + VMULUWM: "vmuluwm", + VMHADDSHS: "vmhaddshs", + VMHRADDSHS: "vmhraddshs", + VMLADDUHM: "vmladduhm", + VMSUMUBM: "vmsumubm", + VMSUMMBM: "vmsummbm", + VMSUMSHM: "vmsumshm", + VMSUMSHS: "vmsumshs", + VMSUMUHM: "vmsumuhm", + VMSUMUHS: "vmsumuhs", + VSUMSWS: "vsumsws", + VSUM2SWS: "vsum2sws", + VSUM4SBS: "vsum4sbs", + VSUM4SHS: "vsum4shs", + VSUM4UBS: "vsum4ubs", + VAVGSB: "vavgsb", + VAVGSH: "vavgsh", + VAVGSW: "vavgsw", + VAVGUB: "vavgub", + VAVGUW: "vavguw", + VAVGUH: "vavguh", + VMAXSB: "vmaxsb", + VMAXSD: "vmaxsd", + VMAXUB: "vmaxub", + VMAXUD: "vmaxud", + VMAXSH: "vmaxsh", + VMAXSW: "vmaxsw", + VMAXUH: "vmaxuh", + VMAXUW: "vmaxuw", + VMINSB: "vminsb", + VMINSD: "vminsd", + VMINUB: "vminub", + VMINUD: "vminud", + VMINSH: "vminsh", + VMINSW: "vminsw", + VMINUH: "vminuh", + VMINUW: "vminuw", + VCMPEQUB: "vcmpequb", + VCMPEQUBCC: "vcmpequb.", + VCMPEQUH: "vcmpequh", + VCMPEQUHCC: "vcmpequh.", + VCMPEQUW: "vcmpequw", + VCMPEQUWCC: "vcmpequw.", + VCMPEQUD: "vcmpequd", + VCMPEQUDCC: "vcmpequd.", + VCMPGTSB: "vcmpgtsb", + VCMPGTSBCC: "vcmpgtsb.", + VCMPGTSD: "vcmpgtsd", + VCMPGTSDCC: "vcmpgtsd.", + VCMPGTSH: "vcmpgtsh", + VCMPGTSHCC: "vcmpgtsh.", + VCMPGTSW: "vcmpgtsw", + VCMPGTSWCC: "vcmpgtsw.", + VCMPGTUB: "vcmpgtub", + VCMPGTUBCC: "vcmpgtub.", + VCMPGTUD: "vcmpgtud", + VCMPGTUDCC: "vcmpgtud.", + VCMPGTUH: "vcmpgtuh", + VCMPGTUHCC: "vcmpgtuh.", + VCMPGTUW: "vcmpgtuw", + VCMPGTUWCC: "vcmpgtuw.", + VAND: "vand", + VANDC: "vandc", + VEQV: "veqv", + VNAND: "vnand", + VORC: "vorc", + VNOR: "vnor", + VOR: "vor", + VXOR: "vxor", + VRLB: "vrlb", + VRLH: "vrlh", + VRLW: "vrlw", + VRLD: "vrld", + VSLB: "vslb", + VSLH: "vslh", + VSLW: "vslw", + VSLD: "vsld", + VSRB: "vsrb", + VSRH: "vsrh", + VSRW: "vsrw", + VSRD: "vsrd", + VSRAB: "vsrab", + VSRAH: "vsrah", + VSRAW: "vsraw", + VSRAD: "vsrad", + VADDFP: "vaddfp", + VSUBFP: "vsubfp", + VMADDFP: "vmaddfp", + VNMSUBFP: "vnmsubfp", + VMAXFP: "vmaxfp", + VMINFP: "vminfp", + VCTSXS: "vctsxs", + VCTUXS: "vctuxs", + VCFSX: "vcfsx", + VCFUX: "vcfux", + VRFIM: "vrfim", + VRFIN: "vrfin", + VRFIP: "vrfip", + VRFIZ: "vrfiz", + VCMPBFP: "vcmpbfp", + VCMPBFPCC: "vcmpbfp.", + VCMPEQFP: "vcmpeqfp", + VCMPEQFPCC: "vcmpeqfp.", + VCMPGEFP: "vcmpgefp", + VCMPGEFPCC: "vcmpgefp.", + VCMPGTFP: "vcmpgtfp", + VCMPGTFPCC: "vcmpgtfp.", + VEXPTEFP: "vexptefp", + VLOGEFP: "vlogefp", + VREFP: "vrefp", + VRSQRTEFP: "vrsqrtefp", + VCIPHER: "vcipher", + VCIPHERLAST: "vcipherlast", + VNCIPHER: "vncipher", + VNCIPHERLAST: "vncipherlast", + VSBOX: "vsbox", + VSHASIGMAD: "vshasigmad", + VSHASIGMAW: "vshasigmaw", + VPMSUMB: "vpmsumb", + VPMSUMD: "vpmsumd", + VPMSUMH: "vpmsumh", + VPMSUMW: "vpmsumw", + VPERMXOR: "vpermxor", + VGBBD: "vgbbd", + VCLZB: "vclzb", + VCLZH: "vclzh", + VCLZW: "vclzw", + VCLZD: "vclzd", + VPOPCNTB: "vpopcntb", + VPOPCNTD: "vpopcntd", + VPOPCNTH: "vpopcnth", + VPOPCNTW: "vpopcntw", + VBPERMQ: "vbpermq", + BCDADDCC: "bcdadd.", + BCDSUBCC: "bcdsub.", + MTVSCR: "mtvscr", + MFVSCR: "mfvscr", + DADD: "dadd", + DADDCC: "dadd.", + DSUB: "dsub", + DSUBCC: "dsub.", + DMUL: "dmul", + DMULCC: "dmul.", + DDIV: "ddiv", + DDIVCC: "ddiv.", + DCMPU: "dcmpu", + DCMPO: "dcmpo", + DTSTDC: "dtstdc", + DTSTDG: "dtstdg", + DTSTEX: "dtstex", + DTSTSF: "dtstsf", + DQUAI: "dquai", + DQUAICC: "dquai.", + DQUA: "dqua", + DQUACC: "dqua.", + DRRND: "drrnd", + DRRNDCC: "drrnd.", + DRINTX: "drintx", + DRINTXCC: "drintx.", + DRINTN: "drintn", + DRINTNCC: "drintn.", + DCTDP: "dctdp", + DCTDPCC: "dctdp.", + DCTQPQ: "dctqpq", + DCTQPQCC: "dctqpq.", + DRSP: "drsp", + DRSPCC: "drsp.", + DRDPQ: "drdpq", + DRDPQCC: "drdpq.", + DCFFIX: "dcffix", + DCFFIXCC: "dcffix.", + DCFFIXQ: "dcffixq", + DCFFIXQCC: "dcffixq.", + DCTFIX: "dctfix", + DCTFIXCC: "dctfix.", + DDEDPD: "ddedpd", + DDEDPDCC: "ddedpd.", + DENBCD: "denbcd", + DENBCDCC: "denbcd.", + DXEX: "dxex", + DXEXCC: "dxex.", + DIEX: "diex", + DIEXCC: "diex.", + DSCLI: "dscli", + DSCLICC: "dscli.", + DSCRI: "dscri", + DSCRICC: "dscri.", + LXSDX: "lxsdx", + LXSIWAX: "lxsiwax", + LXSIWZX: "lxsiwzx", + LXSSPX: "lxsspx", + LXVD2X: "lxvd2x", + LXVDSX: "lxvdsx", + LXVW4X: "lxvw4x", + STXSDX: "stxsdx", + STXSIWX: "stxsiwx", + STXSSPX: "stxsspx", + STXVD2X: "stxvd2x", + STXVW4X: "stxvw4x", + XSABSDP: "xsabsdp", + XSADDDP: "xsadddp", + XSADDSP: "xsaddsp", + XSCMPODP: "xscmpodp", + XSCMPUDP: "xscmpudp", + XSCPSGNDP: "xscpsgndp", + XSCVDPSP: "xscvdpsp", + XSCVDPSPN: "xscvdpspn", + XSCVDPSXDS: "xscvdpsxds", + XSCVDPSXWS: "xscvdpsxws", + XSCVDPUXDS: "xscvdpuxds", + XSCVDPUXWS: "xscvdpuxws", + XSCVSPDP: "xscvspdp", + XSCVSPDPN: "xscvspdpn", + XSCVSXDDP: "xscvsxddp", + XSCVSXDSP: "xscvsxdsp", + XSCVUXDDP: "xscvuxddp", + XSCVUXDSP: "xscvuxdsp", + XSDIVDP: "xsdivdp", + XSDIVSP: "xsdivsp", + XSMADDADP: "xsmaddadp", + XSMADDASP: "xsmaddasp", + XSMAXDP: "xsmaxdp", + XSMINDP: "xsmindp", + XSMSUBADP: "xsmsubadp", + XSMSUBASP: "xsmsubasp", + XSMULDP: "xsmuldp", + XSMULSP: "xsmulsp", + XSNABSDP: "xsnabsdp", + XSNEGDP: "xsnegdp", + XSNMADDADP: "xsnmaddadp", + XSNMADDASP: "xsnmaddasp", + XSNMSUBADP: "xsnmsubadp", + XSNMSUBASP: "xsnmsubasp", + XSRDPI: "xsrdpi", + XSRDPIC: "xsrdpic", + XSRDPIM: "xsrdpim", + XSRDPIP: "xsrdpip", + XSRDPIZ: "xsrdpiz", + XSREDP: "xsredp", + XSRESP: "xsresp", + XSRSP: "xsrsp", + XSRSQRTEDP: "xsrsqrtedp", + XSRSQRTESP: "xsrsqrtesp", + XSSQRTDP: "xssqrtdp", + XSSQRTSP: "xssqrtsp", + XSSUBDP: "xssubdp", + XSSUBSP: "xssubsp", + XSTDIVDP: "xstdivdp", + XSTSQRTDP: "xstsqrtdp", + XVABSDP: "xvabsdp", + XVABSSP: "xvabssp", + XVADDDP: "xvadddp", + XVADDSP: "xvaddsp", + XVCMPEQDP: "xvcmpeqdp", + XVCMPEQDPCC: "xvcmpeqdp.", + XVCMPEQSP: "xvcmpeqsp", + XVCMPEQSPCC: "xvcmpeqsp.", + XVCMPGEDP: "xvcmpgedp", + XVCMPGEDPCC: "xvcmpgedp.", + XVCMPGESP: "xvcmpgesp", + XVCMPGESPCC: "xvcmpgesp.", + XVCMPGTDP: "xvcmpgtdp", + XVCMPGTDPCC: "xvcmpgtdp.", + XVCMPGTSP: "xvcmpgtsp", + XVCMPGTSPCC: "xvcmpgtsp.", + XVCPSGNDP: "xvcpsgndp", + XVCPSGNSP: "xvcpsgnsp", + XVCVDPSP: "xvcvdpsp", + XVCVDPSXDS: "xvcvdpsxds", + XVCVDPSXWS: "xvcvdpsxws", + XVCVDPUXDS: "xvcvdpuxds", + XVCVDPUXWS: "xvcvdpuxws", + XVCVSPDP: "xvcvspdp", + XVCVSPSXDS: "xvcvspsxds", + XVCVSPSXWS: "xvcvspsxws", + XVCVSPUXDS: "xvcvspuxds", + XVCVSPUXWS: "xvcvspuxws", + XVCVSXDDP: "xvcvsxddp", + XVCVSXDSP: "xvcvsxdsp", + XVCVSXWDP: "xvcvsxwdp", + XVCVSXWSP: "xvcvsxwsp", + XVCVUXDDP: "xvcvuxddp", + XVCVUXDSP: "xvcvuxdsp", + XVCVUXWDP: "xvcvuxwdp", + XVCVUXWSP: "xvcvuxwsp", + XVDIVDP: "xvdivdp", + XVDIVSP: "xvdivsp", + XVMADDADP: "xvmaddadp", + XVMADDASP: "xvmaddasp", + XVMAXDP: "xvmaxdp", + XVMAXSP: "xvmaxsp", + XVMINDP: "xvmindp", + XVMINSP: "xvminsp", + XVMSUBADP: "xvmsubadp", + XVMSUBASP: "xvmsubasp", + XVMULDP: "xvmuldp", + XVMULSP: "xvmulsp", + XVNABSDP: "xvnabsdp", + XVNABSSP: "xvnabssp", + XVNEGDP: "xvnegdp", + XVNEGSP: "xvnegsp", + XVNMADDADP: "xvnmaddadp", + XVNMADDASP: "xvnmaddasp", + XVNMSUBADP: "xvnmsubadp", + XVNMSUBASP: "xvnmsubasp", + XVRDPI: "xvrdpi", + XVRDPIC: "xvrdpic", + XVRDPIM: "xvrdpim", + XVRDPIP: "xvrdpip", + XVRDPIZ: "xvrdpiz", + XVREDP: "xvredp", + XVRESP: "xvresp", + XVRSPI: "xvrspi", + XVRSPIC: "xvrspic", + XVRSPIM: "xvrspim", + XVRSPIP: "xvrspip", + XVRSPIZ: "xvrspiz", + XVRSQRTEDP: "xvrsqrtedp", + XVRSQRTESP: "xvrsqrtesp", + XVSQRTDP: "xvsqrtdp", + XVSQRTSP: "xvsqrtsp", + XVSUBDP: "xvsubdp", + XVSUBSP: "xvsubsp", + XVTDIVDP: "xvtdivdp", + XVTDIVSP: "xvtdivsp", + XVTSQRTDP: "xvtsqrtdp", + XVTSQRTSP: "xvtsqrtsp", + XXLAND: "xxland", + XXLANDC: "xxlandc", + XXLEQV: "xxleqv", + XXLNAND: "xxlnand", + XXLORC: "xxlorc", + XXLNOR: "xxlnor", + XXLOR: "xxlor", + XXLXOR: "xxlxor", + XXMRGHW: "xxmrghw", + XXMRGLW: "xxmrglw", + XXPERMDI: "xxpermdi", + XXSEL: "xxsel", + XXSLDWI: "xxsldwi", + XXSPLTW: "xxspltw", + BRINC: "brinc", + EVABS: "evabs", + EVADDIW: "evaddiw", + EVADDSMIAAW: "evaddsmiaaw", + EVADDSSIAAW: "evaddssiaaw", + EVADDUMIAAW: "evaddumiaaw", + EVADDUSIAAW: "evaddusiaaw", + EVADDW: "evaddw", + EVAND: "evand", + EVCMPEQ: "evcmpeq", + EVANDC: "evandc", + EVCMPGTS: "evcmpgts", + EVCMPGTU: "evcmpgtu", + EVCMPLTU: "evcmpltu", + EVCMPLTS: "evcmplts", + EVCNTLSW: "evcntlsw", + EVCNTLZW: "evcntlzw", + EVDIVWS: "evdivws", + EVDIVWU: "evdivwu", + EVEQV: "eveqv", + EVEXTSB: "evextsb", + EVEXTSH: "evextsh", + EVLDD: "evldd", + EVLDH: "evldh", + EVLDDX: "evlddx", + EVLDHX: "evldhx", + EVLDW: "evldw", + EVLHHESPLAT: "evlhhesplat", + EVLDWX: "evldwx", + EVLHHESPLATX: "evlhhesplatx", + EVLHHOSSPLAT: "evlhhossplat", + EVLHHOUSPLAT: "evlhhousplat", + EVLHHOSSPLATX: "evlhhossplatx", + EVLHHOUSPLATX: "evlhhousplatx", + EVLWHE: "evlwhe", + EVLWHOS: "evlwhos", + EVLWHEX: "evlwhex", + EVLWHOSX: "evlwhosx", + EVLWHOU: "evlwhou", + EVLWHSPLAT: "evlwhsplat", + EVLWHOUX: "evlwhoux", + EVLWHSPLATX: "evlwhsplatx", + EVLWWSPLAT: "evlwwsplat", + EVMERGEHI: "evmergehi", + EVLWWSPLATX: "evlwwsplatx", + EVMERGELO: "evmergelo", + EVMERGEHILO: "evmergehilo", + EVMHEGSMFAA: "evmhegsmfaa", + EVMERGELOHI: "evmergelohi", + EVMHEGSMFAN: "evmhegsmfan", + EVMHEGSMIAA: "evmhegsmiaa", + EVMHEGUMIAA: "evmhegumiaa", + EVMHEGSMIAN: "evmhegsmian", + EVMHEGUMIAN: "evmhegumian", + EVMHESMF: "evmhesmf", + EVMHESMFAAW: "evmhesmfaaw", + EVMHESMFA: "evmhesmfa", + EVMHESMFANW: "evmhesmfanw", + EVMHESMI: "evmhesmi", + EVMHESMIAAW: "evmhesmiaaw", + EVMHESMIA: "evmhesmia", + EVMHESMIANW: "evmhesmianw", + EVMHESSF: "evmhessf", + EVMHESSFA: "evmhessfa", + EVMHESSFAAW: "evmhessfaaw", + EVMHESSFANW: "evmhessfanw", + EVMHESSIAAW: "evmhessiaaw", + EVMHESSIANW: "evmhessianw", + EVMHEUMI: "evmheumi", + EVMHEUMIAAW: "evmheumiaaw", + EVMHEUMIA: "evmheumia", + EVMHEUMIANW: "evmheumianw", + EVMHEUSIAAW: "evmheusiaaw", + EVMHEUSIANW: "evmheusianw", + EVMHOGSMFAA: "evmhogsmfaa", + EVMHOGSMIAA: "evmhogsmiaa", + EVMHOGSMFAN: "evmhogsmfan", + EVMHOGSMIAN: "evmhogsmian", + EVMHOGUMIAA: "evmhogumiaa", + EVMHOSMF: "evmhosmf", + EVMHOGUMIAN: "evmhogumian", + EVMHOSMFA: "evmhosmfa", + EVMHOSMFAAW: "evmhosmfaaw", + EVMHOSMI: "evmhosmi", + EVMHOSMFANW: "evmhosmfanw", + EVMHOSMIA: "evmhosmia", + EVMHOSMIAAW: "evmhosmiaaw", + EVMHOSMIANW: "evmhosmianw", + EVMHOSSF: "evmhossf", + EVMHOSSFA: "evmhossfa", + EVMHOSSFAAW: "evmhossfaaw", + EVMHOSSFANW: "evmhossfanw", + EVMHOSSIAAW: "evmhossiaaw", + EVMHOUMI: "evmhoumi", + EVMHOSSIANW: "evmhossianw", + EVMHOUMIA: "evmhoumia", + EVMHOUMIAAW: "evmhoumiaaw", + EVMHOUSIAAW: "evmhousiaaw", + EVMHOUMIANW: "evmhoumianw", + EVMHOUSIANW: "evmhousianw", + EVMRA: "evmra", + EVMWHSMF: "evmwhsmf", + EVMWHSMI: "evmwhsmi", + EVMWHSMFA: "evmwhsmfa", + EVMWHSMIA: "evmwhsmia", + EVMWHSSF: "evmwhssf", + EVMWHUMI: "evmwhumi", + EVMWHSSFA: "evmwhssfa", + EVMWHUMIA: "evmwhumia", + EVMWLSMIAAW: "evmwlsmiaaw", + EVMWLSSIAAW: "evmwlssiaaw", + EVMWLSMIANW: "evmwlsmianw", + EVMWLSSIANW: "evmwlssianw", + EVMWLUMI: "evmwlumi", + EVMWLUMIAAW: "evmwlumiaaw", + EVMWLUMIA: "evmwlumia", + EVMWLUMIANW: "evmwlumianw", + EVMWLUSIAAW: "evmwlusiaaw", + EVMWSMF: "evmwsmf", + EVMWLUSIANW: "evmwlusianw", + EVMWSMFA: "evmwsmfa", + EVMWSMFAA: "evmwsmfaa", + EVMWSMI: "evmwsmi", + EVMWSMIAA: "evmwsmiaa", + EVMWSMFAN: "evmwsmfan", + EVMWSMIA: "evmwsmia", + EVMWSMIAN: "evmwsmian", + EVMWSSF: "evmwssf", + EVMWSSFA: "evmwssfa", + EVMWSSFAA: "evmwssfaa", + EVMWUMI: "evmwumi", + EVMWSSFAN: "evmwssfan", + EVMWUMIA: "evmwumia", + EVMWUMIAA: "evmwumiaa", + EVNAND: "evnand", + EVMWUMIAN: "evmwumian", + EVNEG: "evneg", + EVNOR: "evnor", + EVORC: "evorc", + EVOR: "evor", + EVRLW: "evrlw", + EVRLWI: "evrlwi", + EVSEL: "evsel", + EVRNDW: "evrndw", + EVSLW: "evslw", + EVSPLATFI: "evsplatfi", + EVSRWIS: "evsrwis", + EVSLWI: "evslwi", + EVSPLATI: "evsplati", + EVSRWIU: "evsrwiu", + EVSRWS: "evsrws", + EVSTDD: "evstdd", + EVSRWU: "evsrwu", + EVSTDDX: "evstddx", + EVSTDH: "evstdh", + EVSTDW: "evstdw", + EVSTDHX: "evstdhx", + EVSTDWX: "evstdwx", + EVSTWHE: "evstwhe", + EVSTWHO: "evstwho", + EVSTWWE: "evstwwe", + EVSTWHEX: "evstwhex", + EVSTWHOX: "evstwhox", + EVSTWWEX: "evstwwex", + EVSTWWO: "evstwwo", + EVSUBFSMIAAW: "evsubfsmiaaw", + EVSTWWOX: "evstwwox", + EVSUBFSSIAAW: "evsubfssiaaw", + EVSUBFUMIAAW: "evsubfumiaaw", + EVSUBFUSIAAW: "evsubfusiaaw", + EVSUBFW: "evsubfw", + EVSUBIFW: "evsubifw", + EVXOR: "evxor", + EVFSABS: "evfsabs", + EVFSNABS: "evfsnabs", + EVFSNEG: "evfsneg", + EVFSADD: "evfsadd", + EVFSMUL: "evfsmul", + EVFSSUB: "evfssub", + EVFSDIV: "evfsdiv", + EVFSCMPGT: "evfscmpgt", + EVFSCMPLT: "evfscmplt", + EVFSCMPEQ: "evfscmpeq", + EVFSTSTGT: "evfststgt", + EVFSTSTLT: "evfststlt", + EVFSTSTEQ: "evfststeq", + EVFSCFSI: "evfscfsi", + EVFSCFSF: "evfscfsf", + EVFSCFUI: "evfscfui", + EVFSCFUF: "evfscfuf", + EVFSCTSI: "evfsctsi", + EVFSCTUI: "evfsctui", + EVFSCTSIZ: "evfsctsiz", + EVFSCTUIZ: "evfsctuiz", + EVFSCTSF: "evfsctsf", + EVFSCTUF: "evfsctuf", + EFSABS: "efsabs", + EFSNEG: "efsneg", + EFSNABS: "efsnabs", + EFSADD: "efsadd", + EFSMUL: "efsmul", + EFSSUB: "efssub", + EFSDIV: "efsdiv", + EFSCMPGT: "efscmpgt", + EFSCMPLT: "efscmplt", + EFSCMPEQ: "efscmpeq", + EFSTSTGT: "efststgt", + EFSTSTLT: "efststlt", + EFSTSTEQ: "efststeq", + EFSCFSI: "efscfsi", + EFSCFSF: "efscfsf", + EFSCTSI: "efsctsi", + EFSCFUI: "efscfui", + EFSCFUF: "efscfuf", + EFSCTUI: "efsctui", + EFSCTSIZ: "efsctsiz", + EFSCTSF: "efsctsf", + EFSCTUIZ: "efsctuiz", + EFSCTUF: "efsctuf", + EFDABS: "efdabs", + EFDNEG: "efdneg", + EFDNABS: "efdnabs", + EFDADD: "efdadd", + EFDMUL: "efdmul", + EFDSUB: "efdsub", + EFDDIV: "efddiv", + EFDCMPGT: "efdcmpgt", + EFDCMPEQ: "efdcmpeq", + EFDCMPLT: "efdcmplt", + EFDTSTGT: "efdtstgt", + EFDTSTLT: "efdtstlt", + EFDCFSI: "efdcfsi", + EFDTSTEQ: "efdtsteq", + EFDCFUI: "efdcfui", + EFDCFSID: "efdcfsid", + EFDCFSF: "efdcfsf", + EFDCFUF: "efdcfuf", + EFDCFUID: "efdcfuid", + EFDCTSI: "efdctsi", + EFDCTUI: "efdctui", + EFDCTSIDZ: "efdctsidz", + EFDCTUIDZ: "efdctuidz", + EFDCTSIZ: "efdctsiz", + EFDCTSF: "efdctsf", + EFDCTUF: "efdctuf", + EFDCTUIZ: "efdctuiz", + EFDCFS: "efdcfs", + EFSCFD: "efscfd", + DLMZB: "dlmzb", + DLMZBCC: "dlmzb.", + MACCHW: "macchw", + MACCHWCC: "macchw.", + MACCHWO: "macchwo", + MACCHWOCC: "macchwo.", + MACCHWS: "macchws", + MACCHWSCC: "macchws.", + MACCHWSO: "macchwso", + MACCHWSOCC: "macchwso.", + MACCHWU: "macchwu", + MACCHWUCC: "macchwu.", + MACCHWUO: "macchwuo", + MACCHWUOCC: "macchwuo.", + MACCHWSU: "macchwsu", + MACCHWSUCC: "macchwsu.", + MACCHWSUO: "macchwsuo", + MACCHWSUOCC: "macchwsuo.", + MACHHW: "machhw", + MACHHWCC: "machhw.", + MACHHWO: "machhwo", + MACHHWOCC: "machhwo.", + MACHHWS: "machhws", + MACHHWSCC: "machhws.", + MACHHWSO: "machhwso", + MACHHWSOCC: "machhwso.", + MACHHWU: "machhwu", + MACHHWUCC: "machhwu.", + MACHHWUO: "machhwuo", + MACHHWUOCC: "machhwuo.", + MACHHWSU: "machhwsu", + MACHHWSUCC: "machhwsu.", + MACHHWSUO: "machhwsuo", + MACHHWSUOCC: "machhwsuo.", + MACLHW: "maclhw", + MACLHWCC: "maclhw.", + MACLHWO: "maclhwo", + MACLHWOCC: "maclhwo.", + MACLHWS: "maclhws", + MACLHWSCC: "maclhws.", + MACLHWSO: "maclhwso", + MACLHWSOCC: "maclhwso.", + MACLHWU: "maclhwu", + MACLHWUCC: "maclhwu.", + MACLHWUO: "maclhwuo", + MACLHWUOCC: "maclhwuo.", + MULCHW: "mulchw", + MULCHWCC: "mulchw.", + MACLHWSU: "maclhwsu", + MACLHWSUCC: "maclhwsu.", + MACLHWSUO: "maclhwsuo", + MACLHWSUOCC: "maclhwsuo.", + MULCHWU: "mulchwu", + MULCHWUCC: "mulchwu.", + MULHHW: "mulhhw", + MULHHWCC: "mulhhw.", + MULLHW: "mullhw", + MULLHWCC: "mullhw.", + MULHHWU: "mulhhwu", + MULHHWUCC: "mulhhwu.", + MULLHWU: "mullhwu", + MULLHWUCC: "mullhwu.", + NMACCHW: "nmacchw", + NMACCHWCC: "nmacchw.", + NMACCHWO: "nmacchwo", + NMACCHWOCC: "nmacchwo.", + NMACCHWS: "nmacchws", + NMACCHWSCC: "nmacchws.", + NMACCHWSO: "nmacchwso", + NMACCHWSOCC: "nmacchwso.", + NMACHHW: "nmachhw", + NMACHHWCC: "nmachhw.", + NMACHHWO: "nmachhwo", + NMACHHWOCC: "nmachhwo.", + NMACHHWS: "nmachhws", + NMACHHWSCC: "nmachhws.", + NMACHHWSO: "nmachhwso", + NMACHHWSOCC: "nmachhwso.", + NMACLHW: "nmaclhw", + NMACLHWCC: "nmaclhw.", + NMACLHWO: "nmaclhwo", + NMACLHWOCC: "nmaclhwo.", + NMACLHWS: "nmaclhws", + NMACLHWSCC: "nmaclhws.", + NMACLHWSO: "nmaclhwso", + NMACLHWSOCC: "nmaclhwso.", + ICBI: "icbi", + ICBT: "icbt", + DCBA: "dcba", + DCBT: "dcbt", + DCBTST: "dcbtst", + DCBZ: "dcbz", + DCBST: "dcbst", + DCBF: "dcbf", + ISYNC: "isync", + LBARX: "lbarx", + LHARX: "lharx", + LWARX: "lwarx", + STBCXCC: "stbcx.", + STHCXCC: "sthcx.", + STWCXCC: "stwcx.", + LDARX: "ldarx", + STDCXCC: "stdcx.", + LQARX: "lqarx", + STQCXCC: "stqcx.", + SYNC: "sync", + EIEIO: "eieio", + MBAR: "mbar", + WAIT: "wait", + TBEGINCC: "tbegin.", + TENDCC: "tend.", + TABORTCC: "tabort.", + TABORTWCCC: "tabortwc.", + TABORTWCICC: "tabortwci.", + TABORTDCCC: "tabortdc.", + TABORTDCICC: "tabortdci.", + TSRCC: "tsr.", + TCHECK: "tcheck", + MFTB: "mftb", + RFEBB: "rfebb", + LBDX: "lbdx", + LHDX: "lhdx", + LWDX: "lwdx", + LDDX: "lddx", + LFDDX: "lfddx", + STBDX: "stbdx", + STHDX: "sthdx", + STWDX: "stwdx", + STDDX: "stddx", + STFDDX: "stfddx", + DSN: "dsn", + ECIWX: "eciwx", + ECOWX: "ecowx", + RFID: "rfid", + HRFID: "hrfid", + DOZE: "doze", + NAP: "nap", + SLEEP: "sleep", + RVWINKLE: "rvwinkle", + LBZCIX: "lbzcix", + LWZCIX: "lwzcix", + LHZCIX: "lhzcix", + LDCIX: "ldcix", + STBCIX: "stbcix", + STWCIX: "stwcix", + STHCIX: "sthcix", + STDCIX: "stdcix", + TRECLAIMCC: "treclaim.", + TRECHKPTCC: "trechkpt.", + MTMSR: "mtmsr", + MTMSRD: "mtmsrd", + MFMSR: "mfmsr", + SLBIE: "slbie", + SLBIA: "slbia", + SLBMTE: "slbmte", + SLBMFEV: "slbmfev", + SLBMFEE: "slbmfee", + SLBFEECC: "slbfee.", + MTSR: "mtsr", + MTSRIN: "mtsrin", + MFSR: "mfsr", + MFSRIN: "mfsrin", + TLBIE: "tlbie", + TLBIEL: "tlbiel", + TLBIA: "tlbia", + TLBSYNC: "tlbsync", + MSGSND: "msgsnd", + MSGCLR: "msgclr", + MSGSNDP: "msgsndp", + MSGCLRP: "msgclrp", + MTTMR: "mttmr", + RFI: "rfi", + RFCI: "rfci", + RFDI: "rfdi", + RFMCI: "rfmci", + RFGI: "rfgi", + EHPRIV: "ehpriv", + MTDCR: "mtdcr", + MTDCRX: "mtdcrx", + MFDCR: "mfdcr", + MFDCRX: "mfdcrx", + WRTEE: "wrtee", + WRTEEI: "wrteei", + LBEPX: "lbepx", + LHEPX: "lhepx", + LWEPX: "lwepx", + LDEPX: "ldepx", + STBEPX: "stbepx", + STHEPX: "sthepx", + STWEPX: "stwepx", + STDEPX: "stdepx", + DCBSTEP: "dcbstep", + DCBTEP: "dcbtep", + DCBFEP: "dcbfep", + DCBTSTEP: "dcbtstep", + ICBIEP: "icbiep", + DCBZEP: "dcbzep", + LFDEPX: "lfdepx", + STFDEPX: "stfdepx", + EVLDDEPX: "evlddepx", + EVSTDDEPX: "evstddepx", + LVEPX: "lvepx", + LVEPXL: "lvepxl", + STVEPX: "stvepx", + STVEPXL: "stvepxl", + DCBI: "dcbi", + DCBLQCC: "dcblq.", + ICBLQCC: "icblq.", + DCBTLS: "dcbtls", + DCBTSTLS: "dcbtstls", + ICBTLS: "icbtls", + ICBLC: "icblc", + DCBLC: "dcblc", + TLBIVAX: "tlbivax", + TLBILX: "tlbilx", + TLBSX: "tlbsx", + TLBSRXCC: "tlbsrx.", + TLBRE: "tlbre", + TLBWE: "tlbwe", + DNH: "dnh", + DCI: "dci", + ICI: "ici", + DCREAD: "dcread", + ICREAD: "icread", + MFPMR: "mfpmr", + MTPMR: "mtpmr", + ADDEX: "addex", + DARN: "darn", + MADDHD: "maddhd", + MADDHDU: "maddhdu", + MADDLD: "maddld", + CMPRB: "cmprb", + CMPEQB: "cmpeqb", + EXTSWSLI: "extswsli", + EXTSWSLICC: "extswsli.", + MFVSRLD: "mfvsrld", + MTVSRDD: "mtvsrdd", + MTVSRWS: "mtvsrws", + MCRXRX: "mcrxrx", + COPY: "copy", + PASTECC: "paste.", +} + +var ( + ap_Reg_11_15 = &argField{Type: TypeReg, Shift: 0, BitFields: BitFields{{11, 5}}} + ap_Reg_6_10 = &argField{Type: TypeReg, Shift: 0, BitFields: BitFields{{6, 5}}} + ap_PCRel_6_29_shift2 = &argField{Type: TypePCRel, Shift: 2, BitFields: BitFields{{6, 24}}} + ap_Label_6_29_shift2 = &argField{Type: TypeLabel, Shift: 2, BitFields: BitFields{{6, 24}}} + ap_ImmUnsigned_6_10 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{6, 5}}} + ap_CondRegBit_11_15 = &argField{Type: TypeCondRegBit, Shift: 0, BitFields: BitFields{{11, 5}}} + ap_PCRel_16_29_shift2 = &argField{Type: TypePCRel, Shift: 2, BitFields: BitFields{{16, 14}}} + ap_Label_16_29_shift2 = &argField{Type: TypeLabel, Shift: 2, BitFields: BitFields{{16, 14}}} + ap_ImmUnsigned_19_20 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{19, 2}}} + ap_CondRegBit_6_10 = &argField{Type: TypeCondRegBit, Shift: 0, BitFields: BitFields{{6, 5}}} + ap_CondRegBit_16_20 = &argField{Type: TypeCondRegBit, Shift: 0, BitFields: BitFields{{16, 5}}} + ap_CondRegField_6_8 = &argField{Type: TypeCondRegField, Shift: 0, BitFields: BitFields{{6, 3}}} + ap_CondRegField_11_13 = &argField{Type: TypeCondRegField, Shift: 0, BitFields: BitFields{{11, 3}}} + ap_ImmUnsigned_20_26 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{20, 7}}} + ap_SpReg_11_20 = &argField{Type: TypeSpReg, Shift: 0, BitFields: BitFields{{11, 10}}} + ap_Offset_16_31 = &argField{Type: TypeOffset, Shift: 0, BitFields: BitFields{{16, 16}}} + ap_Reg_16_20 = &argField{Type: TypeReg, Shift: 0, BitFields: BitFields{{16, 5}}} + ap_Offset_16_29_shift2 = &argField{Type: TypeOffset, Shift: 2, BitFields: BitFields{{16, 14}}} + ap_Offset_16_27_shift4 = &argField{Type: TypeOffset, Shift: 4, BitFields: BitFields{{16, 12}}} + ap_ImmUnsigned_16_20 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{16, 5}}} + ap_ImmSigned_16_31 = &argField{Type: TypeImmSigned, Shift: 0, BitFields: BitFields{{16, 16}}} + ap_ImmUnsigned_16_31 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{16, 16}}} + ap_CondRegBit_21_25 = &argField{Type: TypeCondRegBit, Shift: 0, BitFields: BitFields{{21, 5}}} + ap_ImmUnsigned_21_25 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{21, 5}}} + ap_ImmUnsigned_26_30 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{26, 5}}} + ap_ImmUnsigned_30_30_16_20 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{30, 1}, {16, 5}}} + ap_ImmUnsigned_26_26_21_25 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{26, 1}, {21, 5}}} + ap_SpReg_16_20_11_15 = &argField{Type: TypeSpReg, Shift: 0, BitFields: BitFields{{16, 5}, {11, 5}}} + ap_ImmUnsigned_12_19 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{12, 8}}} + ap_ImmUnsigned_10_10 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{10, 1}}} + ap_VecSReg_31_31_6_10 = &argField{Type: TypeVecSReg, Shift: 0, BitFields: BitFields{{31, 1}, {6, 5}}} + ap_FPReg_6_10 = &argField{Type: TypeFPReg, Shift: 0, BitFields: BitFields{{6, 5}}} + ap_FPReg_16_20 = &argField{Type: TypeFPReg, Shift: 0, BitFields: BitFields{{16, 5}}} + ap_FPReg_11_15 = &argField{Type: TypeFPReg, Shift: 0, BitFields: BitFields{{11, 5}}} + ap_FPReg_21_25 = &argField{Type: TypeFPReg, Shift: 0, BitFields: BitFields{{21, 5}}} + ap_ImmUnsigned_16_19 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{16, 4}}} + ap_ImmUnsigned_15_15 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{15, 1}}} + ap_ImmUnsigned_7_14 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{7, 8}}} + ap_ImmUnsigned_6_6 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{6, 1}}} + ap_VecReg_6_10 = &argField{Type: TypeVecReg, Shift: 0, BitFields: BitFields{{6, 5}}} + ap_VecReg_11_15 = &argField{Type: TypeVecReg, Shift: 0, BitFields: BitFields{{11, 5}}} + ap_VecReg_16_20 = &argField{Type: TypeVecReg, Shift: 0, BitFields: BitFields{{16, 5}}} + ap_ImmUnsigned_12_15 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{12, 4}}} + ap_ImmUnsigned_13_15 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{13, 3}}} + ap_ImmUnsigned_14_15 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{14, 2}}} + ap_ImmSigned_11_15 = &argField{Type: TypeImmSigned, Shift: 0, BitFields: BitFields{{11, 5}}} + ap_VecReg_21_25 = &argField{Type: TypeVecReg, Shift: 0, BitFields: BitFields{{21, 5}}} + ap_ImmUnsigned_22_25 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{22, 4}}} + ap_ImmUnsigned_11_15 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{11, 5}}} + ap_ImmUnsigned_16_16 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{16, 1}}} + ap_ImmUnsigned_17_20 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{17, 4}}} + ap_ImmUnsigned_22_22 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{22, 1}}} + ap_ImmUnsigned_16_21 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{16, 6}}} + ap_ImmUnsigned_21_22 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{21, 2}}} + ap_ImmUnsigned_11_12 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{11, 2}}} + ap_ImmUnsigned_11_11 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{11, 1}}} + ap_VecSReg_30_30_16_20 = &argField{Type: TypeVecSReg, Shift: 0, BitFields: BitFields{{30, 1}, {16, 5}}} + ap_VecSReg_29_29_11_15 = &argField{Type: TypeVecSReg, Shift: 0, BitFields: BitFields{{29, 1}, {11, 5}}} + ap_ImmUnsigned_22_23 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{22, 2}}} + ap_VecSReg_28_28_21_25 = &argField{Type: TypeVecSReg, Shift: 0, BitFields: BitFields{{28, 1}, {21, 5}}} + ap_CondRegField_29_31 = &argField{Type: TypeCondRegField, Shift: 0, BitFields: BitFields{{29, 3}}} + ap_ImmUnsigned_7_10 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{7, 4}}} + ap_ImmUnsigned_9_10 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{9, 2}}} + ap_ImmUnsigned_31_31 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{31, 1}}} + ap_ImmSigned_16_20 = &argField{Type: TypeImmSigned, Shift: 0, BitFields: BitFields{{16, 5}}} + ap_ImmUnsigned_20_20 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{20, 1}}} + ap_ImmUnsigned_8_10 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{8, 3}}} + ap_SpReg_12_15 = &argField{Type: TypeSpReg, Shift: 0, BitFields: BitFields{{12, 4}}} + ap_ImmUnsigned_6_20 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{6, 15}}} + ap_ImmUnsigned_11_20 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{11, 10}}} + ap_Reg_21_25 = &argField{Type: TypeReg, Shift: 0, BitFields: BitFields{{21, 5}}} +) + +var instFormats = [...]instFormat{ + {CNTLZW, 0xfc0007ff, 0x7c000034, 0xf800, // Count Leading Zeros Word X-form (cntlzw RA, RS) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10}}, + {CNTLZWCC, 0xfc0007ff, 0x7c000035, 0xf800, // Count Leading Zeros Word X-form (cntlzw. RA, RS) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10}}, + {B, 0xfc000003, 0x48000000, 0x0, // Branch I-form (b target_addr) + [5]*argField{ap_PCRel_6_29_shift2}}, + {BA, 0xfc000003, 0x48000002, 0x0, // Branch I-form (ba target_addr) + [5]*argField{ap_Label_6_29_shift2}}, + {BL, 0xfc000003, 0x48000001, 0x0, // Branch I-form (bl target_addr) + [5]*argField{ap_PCRel_6_29_shift2}}, + {BLA, 0xfc000003, 0x48000003, 0x0, // Branch I-form (bla target_addr) + [5]*argField{ap_Label_6_29_shift2}}, + {BC, 0xfc000003, 0x40000000, 0x0, // Branch Conditional B-form (bc BO,BI,target_addr) + [5]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_PCRel_16_29_shift2}}, + {BCA, 0xfc000003, 0x40000002, 0x0, // Branch Conditional B-form (bca BO,BI,target_addr) + [5]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_Label_16_29_shift2}}, + {BCL, 0xfc000003, 0x40000001, 0x0, // Branch Conditional B-form (bcl BO,BI,target_addr) + [5]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_PCRel_16_29_shift2}}, + {BCLA, 0xfc000003, 0x40000003, 0x0, // Branch Conditional B-form (bcla BO,BI,target_addr) + [5]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_Label_16_29_shift2}}, + {BCLR, 0xfc0007ff, 0x4c000020, 0xe000, // Branch Conditional to Link Register XL-form (bclr BO,BI,BH) + [5]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_ImmUnsigned_19_20}}, + {BCLRL, 0xfc0007ff, 0x4c000021, 0xe000, // Branch Conditional to Link Register XL-form (bclrl BO,BI,BH) + [5]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_ImmUnsigned_19_20}}, + {BCCTR, 0xfc0007ff, 0x4c000420, 0xe000, // Branch Conditional to Count Register XL-form (bcctr BO,BI,BH) + [5]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_ImmUnsigned_19_20}}, + {BCCTRL, 0xfc0007ff, 0x4c000421, 0xe000, // Branch Conditional to Count Register XL-form (bcctrl BO,BI,BH) + [5]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_ImmUnsigned_19_20}}, + {BCTAR, 0xfc0007ff, 0x4c000460, 0xe000, // Branch Conditional to Branch Target Address Register XL-form (bctar BO,BI,BH) + [5]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_ImmUnsigned_19_20}}, + {BCTARL, 0xfc0007ff, 0x4c000461, 0xe000, // Branch Conditional to Branch Target Address Register XL-form (bctarl BO,BI,BH) + [5]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_ImmUnsigned_19_20}}, + {CRAND, 0xfc0007fe, 0x4c000202, 0x1, // Condition Register AND XL-form (crand BT,BA,BB) + [5]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}}, + {CROR, 0xfc0007fe, 0x4c000382, 0x1, // Condition Register OR XL-form (cror BT,BA,BB) + [5]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}}, + {CRNAND, 0xfc0007fe, 0x4c0001c2, 0x1, // Condition Register NAND XL-form (crnand BT,BA,BB) + [5]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}}, + {CRXOR, 0xfc0007fe, 0x4c000182, 0x1, // Condition Register XOR XL-form (crxor BT,BA,BB) + [5]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}}, + {CRNOR, 0xfc0007fe, 0x4c000042, 0x1, // Condition Register NOR XL-form (crnor BT,BA,BB) + [5]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}}, + {CRANDC, 0xfc0007fe, 0x4c000102, 0x1, // Condition Register AND with Complement XL-form (crandc BT,BA,BB) + [5]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}}, + {MCRF, 0xfc0007fe, 0x4c000000, 0x63f801, // Move Condition Register Field XL-form (mcrf BF,BFA) + [5]*argField{ap_CondRegField_6_8, ap_CondRegField_11_13}}, + {CREQV, 0xfc0007fe, 0x4c000242, 0x1, // Condition Register Equivalent XL-form (creqv BT,BA,BB) + [5]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}}, + {CRORC, 0xfc0007fe, 0x4c000342, 0x1, // Condition Register OR with Complement XL-form (crorc BT,BA,BB) + [5]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}}, + {SC, 0xfc000002, 0x44000002, 0x3fff01d, // System Call SC-form (sc LEV) + [5]*argField{ap_ImmUnsigned_20_26}}, + {CLRBHRB, 0xfc0007fe, 0x7c00035c, 0x3fff801, // Clear BHRB X-form (clrbhrb) + [5]*argField{}}, + {MFBHRBE, 0xfc0007fe, 0x7c00025c, 0x1, // Move From Branch History Rolling Buffer XFX-form (mfbhrbe RT,BHRBE) + [5]*argField{ap_Reg_6_10, ap_SpReg_11_20}}, + {LBZ, 0xfc000000, 0x88000000, 0x0, // Load Byte and Zero D-form (lbz RT,D(RA)) + [5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, + {LBZU, 0xfc000000, 0x8c000000, 0x0, // Load Byte and Zero with Update D-form (lbzu RT,D(RA)) + [5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, + {LBZX, 0xfc0007fe, 0x7c0000ae, 0x1, // Load Byte and Zero Indexed X-form (lbzx RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LBZUX, 0xfc0007fe, 0x7c0000ee, 0x1, // Load Byte and Zero with Update Indexed X-form (lbzux RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LHZ, 0xfc000000, 0xa0000000, 0x0, // Load Halfword and Zero D-form (lhz RT,D(RA)) + [5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, + {LHZU, 0xfc000000, 0xa4000000, 0x0, // Load Halfword and Zero with Update D-form (lhzu RT,D(RA)) + [5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, + {LHZX, 0xfc0007fe, 0x7c00022e, 0x1, // Load Halfword and Zero Indexed X-form (lhzx RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LHZUX, 0xfc0007fe, 0x7c00026e, 0x1, // Load Halfword and Zero with Update Indexed X-form (lhzux RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LHA, 0xfc000000, 0xa8000000, 0x0, // Load Halfword Algebraic D-form (lha RT,D(RA)) + [5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, + {LHAU, 0xfc000000, 0xac000000, 0x0, // Load Halfword Algebraic with Update D-form (lhau RT,D(RA)) + [5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, + {LHAX, 0xfc0007fe, 0x7c0002ae, 0x1, // Load Halfword Algebraic Indexed X-form (lhax RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LHAUX, 0xfc0007fe, 0x7c0002ee, 0x1, // Load Halfword Algebraic with Update Indexed X-form (lhaux RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LWZ, 0xfc000000, 0x80000000, 0x0, // Load Word and Zero D-form (lwz RT,D(RA)) + [5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, + {LWZU, 0xfc000000, 0x84000000, 0x0, // Load Word and Zero with Update D-form (lwzu RT,D(RA)) + [5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, + {LWZX, 0xfc0007fe, 0x7c00002e, 0x1, // Load Word and Zero Indexed X-form (lwzx RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LWZUX, 0xfc0007fe, 0x7c00006e, 0x1, // Load Word and Zero with Update Indexed X-form (lwzux RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LWA, 0xfc000003, 0xe8000002, 0x0, // Load Word Algebraic DS-form (lwa RT,DS(RA)) + [5]*argField{ap_Reg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}}, + {LWAX, 0xfc0007fe, 0x7c0002aa, 0x1, // Load Word Algebraic Indexed X-form (lwax RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LWAUX, 0xfc0007fe, 0x7c0002ea, 0x1, // Load Word Algebraic with Update Indexed X-form (lwaux RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LD, 0xfc000003, 0xe8000000, 0x0, // Load Doubleword DS-form (ld RT,DS(RA)) + [5]*argField{ap_Reg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}}, + {LDU, 0xfc000003, 0xe8000001, 0x0, // Load Doubleword with Update DS-form (ldu RT,DS(RA)) + [5]*argField{ap_Reg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}}, + {LDX, 0xfc0007fe, 0x7c00002a, 0x1, // Load Doubleword Indexed X-form (ldx RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LDUX, 0xfc0007fe, 0x7c00006a, 0x1, // Load Doubleword with Update Indexed X-form (ldux RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STB, 0xfc000000, 0x98000000, 0x0, // Store Byte D-form (stb RS,D(RA)) + [5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, + {STBU, 0xfc000000, 0x9c000000, 0x0, // Store Byte with Update D-form (stbu RS,D(RA)) + [5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, + {STBX, 0xfc0007fe, 0x7c0001ae, 0x1, // Store Byte Indexed X-form (stbx RS,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STBUX, 0xfc0007fe, 0x7c0001ee, 0x1, // Store Byte with Update Indexed X-form (stbux RS,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STH, 0xfc000000, 0xb0000000, 0x0, // Store Halfword D-form (sth RS,D(RA)) + [5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, + {STHU, 0xfc000000, 0xb4000000, 0x0, // Store Halfword with Update D-form (sthu RS,D(RA)) + [5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, + {STHX, 0xfc0007fe, 0x7c00032e, 0x1, // Store Halfword Indexed X-form (sthx RS,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STHUX, 0xfc0007fe, 0x7c00036e, 0x1, // Store Halfword with Update Indexed X-form (sthux RS,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STW, 0xfc000000, 0x90000000, 0x0, // Store Word D-form (stw RS,D(RA)) + [5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, + {STWU, 0xfc000000, 0x94000000, 0x0, // Store Word with Update D-form (stwu RS,D(RA)) + [5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, + {STWX, 0xfc0007fe, 0x7c00012e, 0x1, // Store Word Indexed X-form (stwx RS,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STWUX, 0xfc0007fe, 0x7c00016e, 0x1, // Store Word with Update Indexed X-form (stwux RS,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STD, 0xfc000003, 0xf8000000, 0x0, // Store Doubleword DS-form (std RS,DS(RA)) + [5]*argField{ap_Reg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}}, + {STDU, 0xfc000003, 0xf8000001, 0x0, // Store Doubleword with Update DS-form (stdu RS,DS(RA)) + [5]*argField{ap_Reg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}}, + {STDX, 0xfc0007fe, 0x7c00012a, 0x1, // Store Doubleword Indexed X-form (stdx RS,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STDUX, 0xfc0007fe, 0x7c00016a, 0x1, // Store Doubleword with Update Indexed X-form (stdux RS,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LQ, 0xfc000000, 0xe0000000, 0xf, // Load Quadword DQ-form (lq RTp,DQ(RA)) + [5]*argField{ap_Reg_6_10, ap_Offset_16_27_shift4, ap_Reg_11_15}}, + {STQ, 0xfc000003, 0xf8000002, 0x0, // Store Quadword DS-form (stq RSp,DS(RA)) + [5]*argField{ap_Reg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}}, + {LHBRX, 0xfc0007fe, 0x7c00062c, 0x1, // Load Halfword Byte-Reverse Indexed X-form (lhbrx RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LWBRX, 0xfc0007fe, 0x7c00042c, 0x1, // Load Word Byte-Reverse Indexed X-form (lwbrx RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STHBRX, 0xfc0007fe, 0x7c00072c, 0x1, // Store Halfword Byte-Reverse Indexed X-form (sthbrx RS,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STWBRX, 0xfc0007fe, 0x7c00052c, 0x1, // Store Word Byte-Reverse Indexed X-form (stwbrx RS,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LDBRX, 0xfc0007fe, 0x7c000428, 0x1, // Load Doubleword Byte-Reverse Indexed X-form (ldbrx RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STDBRX, 0xfc0007fe, 0x7c000528, 0x1, // Store Doubleword Byte-Reverse Indexed X-form (stdbrx RS,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LMW, 0xfc000000, 0xb8000000, 0x0, // Load Multiple Word D-form (lmw RT,D(RA)) + [5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, + {STMW, 0xfc000000, 0xbc000000, 0x0, // Store Multiple Word D-form (stmw RS,D(RA)) + [5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, + {LSWI, 0xfc0007fe, 0x7c0004aa, 0x1, // Load String Word Immediate X-form (lswi RT,RA,NB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmUnsigned_16_20}}, + {LSWX, 0xfc0007fe, 0x7c00042a, 0x1, // Load String Word Indexed X-form (lswx RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STSWI, 0xfc0007fe, 0x7c0005aa, 0x1, // Store String Word Immediate X-form (stswi RS,RA,NB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmUnsigned_16_20}}, + {STSWX, 0xfc0007fe, 0x7c00052a, 0x1, // Store String Word Indexed X-form (stswx RS,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LI, 0xfc1f0000, 0x38000000, 0x0, // Add Immediate D-form (li RT,SI) + [5]*argField{ap_Reg_6_10, ap_ImmSigned_16_31}}, + {ADDI, 0xfc000000, 0x38000000, 0x0, // Add Immediate D-form (addi RT,RA,SI) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}}, + {LIS, 0xfc1f0000, 0x3c000000, 0x0, // Add Immediate Shifted D-form (lis RT, SI) + [5]*argField{ap_Reg_6_10, ap_ImmSigned_16_31}}, + {ADDIS, 0xfc000000, 0x3c000000, 0x0, // Add Immediate Shifted D-form (addis RT,RA,SI) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}}, + {ADD, 0xfc0007ff, 0x7c000214, 0x0, // Add XO-form (add RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {ADDCC, 0xfc0007ff, 0x7c000215, 0x0, // Add XO-form (add. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {ADDO, 0xfc0007ff, 0x7c000614, 0x0, // Add XO-form (addo RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {ADDOCC, 0xfc0007ff, 0x7c000615, 0x0, // Add XO-form (addo. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {ADDIC, 0xfc000000, 0x30000000, 0x0, // Add Immediate Carrying D-form (addic RT,RA,SI) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}}, + {SUBF, 0xfc0007ff, 0x7c000050, 0x0, // Subtract From XO-form (subf RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {SUBFCC, 0xfc0007ff, 0x7c000051, 0x0, // Subtract From XO-form (subf. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {SUBFO, 0xfc0007ff, 0x7c000450, 0x0, // Subtract From XO-form (subfo RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {SUBFOCC, 0xfc0007ff, 0x7c000451, 0x0, // Subtract From XO-form (subfo. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {ADDICCC, 0xfc000000, 0x34000000, 0x0, // Add Immediate Carrying and Record D-form (addic. RT,RA,SI) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}}, + {SUBFIC, 0xfc000000, 0x20000000, 0x0, // Subtract From Immediate Carrying D-form (subfic RT,RA,SI) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}}, + {ADDC, 0xfc0007ff, 0x7c000014, 0x0, // Add Carrying XO-form (addc RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {ADDCCC, 0xfc0007ff, 0x7c000015, 0x0, // Add Carrying XO-form (addc. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {ADDCO, 0xfc0007ff, 0x7c000414, 0x0, // Add Carrying XO-form (addco RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {ADDCOCC, 0xfc0007ff, 0x7c000415, 0x0, // Add Carrying XO-form (addco. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {SUBFC, 0xfc0007ff, 0x7c000010, 0x0, // Subtract From Carrying XO-form (subfc RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {SUBFCCC, 0xfc0007ff, 0x7c000011, 0x0, // Subtract From Carrying XO-form (subfc. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {SUBFCO, 0xfc0007ff, 0x7c000410, 0x0, // Subtract From Carrying XO-form (subfco RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {SUBFCOCC, 0xfc0007ff, 0x7c000411, 0x0, // Subtract From Carrying XO-form (subfco. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {ADDE, 0xfc0007ff, 0x7c000114, 0x0, // Add Extended XO-form (adde RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {ADDECC, 0xfc0007ff, 0x7c000115, 0x0, // Add Extended XO-form (adde. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {ADDEO, 0xfc0007ff, 0x7c000514, 0x0, // Add Extended XO-form (addeo RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {ADDEOCC, 0xfc0007ff, 0x7c000515, 0x0, // Add Extended XO-form (addeo. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {ADDME, 0xfc0007ff, 0x7c0001d4, 0xf800, // Add to Minus One Extended XO-form (addme RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {ADDMECC, 0xfc0007ff, 0x7c0001d5, 0xf800, // Add to Minus One Extended XO-form (addme. RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {ADDMEO, 0xfc0007ff, 0x7c0005d4, 0xf800, // Add to Minus One Extended XO-form (addmeo RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {ADDMEOCC, 0xfc0007ff, 0x7c0005d5, 0xf800, // Add to Minus One Extended XO-form (addmeo. RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {SUBFE, 0xfc0007ff, 0x7c000110, 0x0, // Subtract From Extended XO-form (subfe RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {SUBFECC, 0xfc0007ff, 0x7c000111, 0x0, // Subtract From Extended XO-form (subfe. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {SUBFEO, 0xfc0007ff, 0x7c000510, 0x0, // Subtract From Extended XO-form (subfeo RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {SUBFEOCC, 0xfc0007ff, 0x7c000511, 0x0, // Subtract From Extended XO-form (subfeo. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {SUBFME, 0xfc0007ff, 0x7c0001d0, 0xf800, // Subtract From Minus One Extended XO-form (subfme RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {SUBFMECC, 0xfc0007ff, 0x7c0001d1, 0xf800, // Subtract From Minus One Extended XO-form (subfme. RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {SUBFMEO, 0xfc0007ff, 0x7c0005d0, 0xf800, // Subtract From Minus One Extended XO-form (subfmeo RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {SUBFMEOCC, 0xfc0007ff, 0x7c0005d1, 0xf800, // Subtract From Minus One Extended XO-form (subfmeo. RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {ADDZE, 0xfc0007ff, 0x7c000194, 0xf800, // Add to Zero Extended XO-form (addze RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {ADDZECC, 0xfc0007ff, 0x7c000195, 0xf800, // Add to Zero Extended XO-form (addze. RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {ADDZEO, 0xfc0007ff, 0x7c000594, 0xf800, // Add to Zero Extended XO-form (addzeo RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {ADDZEOCC, 0xfc0007ff, 0x7c000595, 0xf800, // Add to Zero Extended XO-form (addzeo. RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {SUBFZE, 0xfc0007ff, 0x7c000190, 0xf800, // Subtract From Zero Extended XO-form (subfze RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {SUBFZECC, 0xfc0007ff, 0x7c000191, 0xf800, // Subtract From Zero Extended XO-form (subfze. RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {SUBFZEO, 0xfc0007ff, 0x7c000590, 0xf800, // Subtract From Zero Extended XO-form (subfzeo RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {SUBFZEOCC, 0xfc0007ff, 0x7c000591, 0xf800, // Subtract From Zero Extended XO-form (subfzeo. RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {NEG, 0xfc0007ff, 0x7c0000d0, 0xf800, // Negate XO-form (neg RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {NEGCC, 0xfc0007ff, 0x7c0000d1, 0xf800, // Negate XO-form (neg. RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {NEGO, 0xfc0007ff, 0x7c0004d0, 0xf800, // Negate XO-form (nego RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {NEGOCC, 0xfc0007ff, 0x7c0004d1, 0xf800, // Negate XO-form (nego. RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {MULLI, 0xfc000000, 0x1c000000, 0x0, // Multiply Low Immediate D-form (mulli RT,RA,SI) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}}, + {MULLW, 0xfc0007ff, 0x7c0001d6, 0x0, // Multiply Low Word XO-form (mullw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MULLWCC, 0xfc0007ff, 0x7c0001d7, 0x0, // Multiply Low Word XO-form (mullw. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MULLWO, 0xfc0007ff, 0x7c0005d6, 0x0, // Multiply Low Word XO-form (mullwo RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MULLWOCC, 0xfc0007ff, 0x7c0005d7, 0x0, // Multiply Low Word XO-form (mullwo. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MULHW, 0xfc0003ff, 0x7c000096, 0x400, // Multiply High Word XO-form (mulhw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MULHWCC, 0xfc0003ff, 0x7c000097, 0x400, // Multiply High Word XO-form (mulhw. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MULHWU, 0xfc0003ff, 0x7c000016, 0x400, // Multiply High Word Unsigned XO-form (mulhwu RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MULHWUCC, 0xfc0003ff, 0x7c000017, 0x400, // Multiply High Word Unsigned XO-form (mulhwu. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DIVW, 0xfc0007ff, 0x7c0003d6, 0x0, // Divide Word XO-form (divw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DIVWCC, 0xfc0007ff, 0x7c0003d7, 0x0, // Divide Word XO-form (divw. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DIVWO, 0xfc0007ff, 0x7c0007d6, 0x0, // Divide Word XO-form (divwo RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DIVWOCC, 0xfc0007ff, 0x7c0007d7, 0x0, // Divide Word XO-form (divwo. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DIVWU, 0xfc0007ff, 0x7c000396, 0x0, // Divide Word Unsigned XO-form (divwu RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DIVWUCC, 0xfc0007ff, 0x7c000397, 0x0, // Divide Word Unsigned XO-form (divwu. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DIVWUO, 0xfc0007ff, 0x7c000796, 0x0, // Divide Word Unsigned XO-form (divwuo RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DIVWUOCC, 0xfc0007ff, 0x7c000797, 0x0, // Divide Word Unsigned XO-form (divwuo. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DIVWE, 0xfc0007ff, 0x7c000356, 0x0, // Divide Word Extended XO-form (divwe RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DIVWECC, 0xfc0007ff, 0x7c000357, 0x0, // Divide Word Extended XO-form (divwe. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DIVWEO, 0xfc0007ff, 0x7c000756, 0x0, // Divide Word Extended XO-form (divweo RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DIVWEOCC, 0xfc0007ff, 0x7c000757, 0x0, // Divide Word Extended XO-form (divweo. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DIVWEU, 0xfc0007ff, 0x7c000316, 0x0, // Divide Word Extended Unsigned XO-form (divweu RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DIVWEUCC, 0xfc0007ff, 0x7c000317, 0x0, // Divide Word Extended Unsigned XO-form (divweu. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DIVWEUO, 0xfc0007ff, 0x7c000716, 0x0, // Divide Word Extended Unsigned XO-form (divweuo RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DIVWEUOCC, 0xfc0007ff, 0x7c000717, 0x0, // Divide Word Extended Unsigned XO-form (divweuo. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MULLD, 0xfc0007ff, 0x7c0001d2, 0x0, // Multiply Low Doubleword XO-form (mulld RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MULLDCC, 0xfc0007ff, 0x7c0001d3, 0x0, // Multiply Low Doubleword XO-form (mulld. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MULLDO, 0xfc0007ff, 0x7c0005d2, 0x0, // Multiply Low Doubleword XO-form (mulldo RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MULLDOCC, 0xfc0007ff, 0x7c0005d3, 0x0, // Multiply Low Doubleword XO-form (mulldo. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MULHDU, 0xfc0003ff, 0x7c000012, 0x400, // Multiply High Doubleword Unsigned XO-form (mulhdu RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MULHDUCC, 0xfc0003ff, 0x7c000013, 0x400, // Multiply High Doubleword Unsigned XO-form (mulhdu. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MULHD, 0xfc0003ff, 0x7c000092, 0x400, // Multiply High Doubleword XO-form (mulhd RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MULHDCC, 0xfc0003ff, 0x7c000093, 0x400, // Multiply High Doubleword XO-form (mulhd. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DIVD, 0xfc0007ff, 0x7c0003d2, 0x0, // Divide Doubleword XO-form (divd RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DIVDCC, 0xfc0007ff, 0x7c0003d3, 0x0, // Divide Doubleword XO-form (divd. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DIVDO, 0xfc0007ff, 0x7c0007d2, 0x0, // Divide Doubleword XO-form (divdo RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DIVDOCC, 0xfc0007ff, 0x7c0007d3, 0x0, // Divide Doubleword XO-form (divdo. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DIVDU, 0xfc0007ff, 0x7c000392, 0x0, // Divide Doubleword Unsigned XO-form (divdu RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DIVDUCC, 0xfc0007ff, 0x7c000393, 0x0, // Divide Doubleword Unsigned XO-form (divdu. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DIVDUO, 0xfc0007ff, 0x7c000792, 0x0, // Divide Doubleword Unsigned XO-form (divduo RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DIVDUOCC, 0xfc0007ff, 0x7c000793, 0x0, // Divide Doubleword Unsigned XO-form (divduo. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DIVDE, 0xfc0007ff, 0x7c000352, 0x0, // Divide Doubleword Extended XO-form (divde RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DIVDECC, 0xfc0007ff, 0x7c000353, 0x0, // Divide Doubleword Extended XO-form (divde. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DIVDEO, 0xfc0007ff, 0x7c000752, 0x0, // Divide Doubleword Extended XO-form (divdeo RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DIVDEOCC, 0xfc0007ff, 0x7c000753, 0x0, // Divide Doubleword Extended XO-form (divdeo. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DIVDEU, 0xfc0007ff, 0x7c000312, 0x0, // Divide Doubleword Extended Unsigned XO-form (divdeu RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DIVDEUCC, 0xfc0007ff, 0x7c000313, 0x0, // Divide Doubleword Extended Unsigned XO-form (divdeu. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DIVDEUO, 0xfc0007ff, 0x7c000712, 0x0, // Divide Doubleword Extended Unsigned XO-form (divdeuo RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DIVDEUOCC, 0xfc0007ff, 0x7c000713, 0x0, // Divide Doubleword Extended Unsigned XO-form (divdeuo. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {CMPWI, 0xfc200000, 0x2c000000, 0x400000, // Compare Immediate D-form (cmpwi BF,RA,SI) + [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_ImmSigned_16_31}}, + {CMPDI, 0xfc200000, 0x2c200000, 0x400000, // Compare Immediate D-form (cmpdi BF,RA,SI) + [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_ImmSigned_16_31}}, + {CMPW, 0xfc2007fe, 0x7c000000, 0x400001, // Compare X-form (cmpw BF,RA,RB) + [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, + {CMPD, 0xfc2007fe, 0x7c200000, 0x400001, // Compare X-form (cmpd BF,RA,RB) + [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, + {CMPLWI, 0xfc200000, 0x28000000, 0x400000, // Compare Logical Immediate D-form (cmplwi BF,RA,UI) + [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_ImmUnsigned_16_31}}, + {CMPLDI, 0xfc200000, 0x28200000, 0x400000, // Compare Logical Immediate D-form (cmpldi BF,RA,UI) + [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_ImmUnsigned_16_31}}, + {CMPLW, 0xfc2007fe, 0x7c000040, 0x400001, // Compare Logical X-form (cmplw BF,RA,RB) + [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, + {CMPLD, 0xfc2007fe, 0x7c200040, 0x400001, // Compare Logical X-form (cmpld BF,RA,RB) + [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, + {TWI, 0xfc000000, 0xc000000, 0x0, // Trap Word Immediate D-form (twi TO,RA,SI) + [5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}}, + {TW, 0xfc0007fe, 0x7c000008, 0x1, // Trap Word X-form (tw TO,RA,RB) + [5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {TDI, 0xfc000000, 0x8000000, 0x0, // Trap Doubleword Immediate D-form (tdi TO,RA,SI) + [5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}}, + {ISEL, 0xfc00003e, 0x7c00001e, 0x1, // Integer Select A-form (isel RT,RA,RB,BC) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_CondRegBit_21_25}}, + {TD, 0xfc0007fe, 0x7c000088, 0x1, // Trap Doubleword X-form (td TO,RA,RB) + [5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {ANDICC, 0xfc000000, 0x70000000, 0x0, // AND Immediate D-form (andi. RA,RS,UI) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_31}}, + {ANDISCC, 0xfc000000, 0x74000000, 0x0, // AND Immediate Shifted D-form (andis. RA,RS,UI) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_31}}, + {ORI, 0xfc000000, 0x60000000, 0x0, // OR Immediate D-form (ori RA,RS,UI) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_31}}, + {ORIS, 0xfc000000, 0x64000000, 0x0, // OR Immediate Shifted D-form (oris RA,RS,UI) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_31}}, + {XORI, 0xfc000000, 0x68000000, 0x0, // XOR Immediate D-form (xori RA,RS,UI) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_31}}, + {XORIS, 0xfc000000, 0x6c000000, 0x0, // XOR Immediate Shifted D-form (xoris RA,RS,UI) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_31}}, + {AND, 0xfc0007ff, 0x7c000038, 0x0, // AND X-form (and RA,RS,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, + {ANDCC, 0xfc0007ff, 0x7c000039, 0x0, // AND X-form (and. RA,RS,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, + {XOR, 0xfc0007ff, 0x7c000278, 0x0, // XOR X-form (xor RA,RS,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, + {XORCC, 0xfc0007ff, 0x7c000279, 0x0, // XOR X-form (xor. RA,RS,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, + {NAND, 0xfc0007ff, 0x7c0003b8, 0x0, // NAND X-form (nand RA,RS,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, + {NANDCC, 0xfc0007ff, 0x7c0003b9, 0x0, // NAND X-form (nand. RA,RS,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, + {OR, 0xfc0007ff, 0x7c000378, 0x0, // OR X-form (or RA,RS,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, + {ORCC, 0xfc0007ff, 0x7c000379, 0x0, // OR X-form (or. RA,RS,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, + {NOR, 0xfc0007ff, 0x7c0000f8, 0x0, // NOR X-form (nor RA,RS,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, + {NORCC, 0xfc0007ff, 0x7c0000f9, 0x0, // NOR X-form (nor. RA,RS,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, + {ANDC, 0xfc0007ff, 0x7c000078, 0x0, // AND with Complement X-form (andc RA,RS,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, + {ANDCCC, 0xfc0007ff, 0x7c000079, 0x0, // AND with Complement X-form (andc. RA,RS,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, + {EXTSB, 0xfc0007ff, 0x7c000774, 0xf800, // Extend Sign Byte X-form (extsb RA,RS) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10}}, + {EXTSBCC, 0xfc0007ff, 0x7c000775, 0xf800, // Extend Sign Byte X-form (extsb. RA,RS) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10}}, + {EQV, 0xfc0007ff, 0x7c000238, 0x0, // Equivalent X-form (eqv RA,RS,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, + {EQVCC, 0xfc0007ff, 0x7c000239, 0x0, // Equivalent X-form (eqv. RA,RS,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, + {ORC, 0xfc0007ff, 0x7c000338, 0x0, // OR with Complement X-form (orc RA,RS,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, + {ORCCC, 0xfc0007ff, 0x7c000339, 0x0, // OR with Complement X-form (orc. RA,RS,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, + {EXTSH, 0xfc0007ff, 0x7c000734, 0xf800, // Extend Sign Halfword X-form (extsh RA,RS) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10}}, + {EXTSHCC, 0xfc0007ff, 0x7c000735, 0xf800, // Extend Sign Halfword X-form (extsh. RA,RS) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10}}, + {CMPB, 0xfc0007fe, 0x7c0003f8, 0x1, // Compare Bytes X-form (cmpb RA,RS,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, + {POPCNTB, 0xfc0007fe, 0x7c0000f4, 0xf801, // Population Count Bytes X-form (popcntb RA, RS) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10}}, + {POPCNTW, 0xfc0007fe, 0x7c0002f4, 0xf801, // Population Count Words X-form (popcntw RA, RS) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10}}, + {PRTYD, 0xfc0007fe, 0x7c000174, 0xf801, // Parity Doubleword X-form (prtyd RA,RS) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10}}, + {PRTYW, 0xfc0007fe, 0x7c000134, 0xf801, // Parity Word X-form (prtyw RA,RS) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10}}, + {EXTSW, 0xfc0007ff, 0x7c0007b4, 0xf800, // Extend Sign Word X-form (extsw RA,RS) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10}}, + {EXTSWCC, 0xfc0007ff, 0x7c0007b5, 0xf800, // Extend Sign Word X-form (extsw. RA,RS) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10}}, + {CNTLZD, 0xfc0007ff, 0x7c000074, 0xf800, // Count Leading Zeros Doubleword X-form (cntlzd RA,RS) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10}}, + {CNTLZDCC, 0xfc0007ff, 0x7c000075, 0xf800, // Count Leading Zeros Doubleword X-form (cntlzd. RA,RS) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10}}, + {POPCNTD, 0xfc0007fe, 0x7c0003f4, 0xf801, // Population Count Doubleword X-form (popcntd RA, RS) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10}}, + {BPERMD, 0xfc0007fe, 0x7c0001f8, 0x1, // Bit Permute Doubleword X-form (bpermd RA,RS,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, + {RLWINM, 0xfc000001, 0x54000000, 0x0, // Rotate Left Word Immediate then AND with Mask M-form (rlwinm RA,RS,SH,MB,ME) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_ImmUnsigned_21_25, ap_ImmUnsigned_26_30}}, + {RLWINMCC, 0xfc000001, 0x54000001, 0x0, // Rotate Left Word Immediate then AND with Mask M-form (rlwinm. RA,RS,SH,MB,ME) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_ImmUnsigned_21_25, ap_ImmUnsigned_26_30}}, + {RLWNM, 0xfc000001, 0x5c000000, 0x0, // Rotate Left Word then AND with Mask M-form (rlwnm RA,RS,RB,MB,ME) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20, ap_ImmUnsigned_21_25, ap_ImmUnsigned_26_30}}, + {RLWNMCC, 0xfc000001, 0x5c000001, 0x0, // Rotate Left Word then AND with Mask M-form (rlwnm. RA,RS,RB,MB,ME) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20, ap_ImmUnsigned_21_25, ap_ImmUnsigned_26_30}}, + {RLWIMI, 0xfc000001, 0x50000000, 0x0, // Rotate Left Word Immediate then Mask Insert M-form (rlwimi RA,RS,SH,MB,ME) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_ImmUnsigned_21_25, ap_ImmUnsigned_26_30}}, + {RLWIMICC, 0xfc000001, 0x50000001, 0x0, // Rotate Left Word Immediate then Mask Insert M-form (rlwimi. RA,RS,SH,MB,ME) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_ImmUnsigned_21_25, ap_ImmUnsigned_26_30}}, + {RLDICL, 0xfc00001d, 0x78000000, 0x0, // Rotate Left Doubleword Immediate then Clear Left MD-form (rldicl RA,RS,SH,MB) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}}, + {RLDICLCC, 0xfc00001d, 0x78000001, 0x0, // Rotate Left Doubleword Immediate then Clear Left MD-form (rldicl. RA,RS,SH,MB) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}}, + {RLDICR, 0xfc00001d, 0x78000004, 0x0, // Rotate Left Doubleword Immediate then Clear Right MD-form (rldicr RA,RS,SH,ME) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}}, + {RLDICRCC, 0xfc00001d, 0x78000005, 0x0, // Rotate Left Doubleword Immediate then Clear Right MD-form (rldicr. RA,RS,SH,ME) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}}, + {RLDIC, 0xfc00001d, 0x78000008, 0x0, // Rotate Left Doubleword Immediate then Clear MD-form (rldic RA,RS,SH,MB) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}}, + {RLDICCC, 0xfc00001d, 0x78000009, 0x0, // Rotate Left Doubleword Immediate then Clear MD-form (rldic. RA,RS,SH,MB) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}}, + {RLDCL, 0xfc00001f, 0x78000010, 0x0, // Rotate Left Doubleword then Clear Left MDS-form (rldcl RA,RS,RB,MB) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20, ap_ImmUnsigned_26_26_21_25}}, + {RLDCLCC, 0xfc00001f, 0x78000011, 0x0, // Rotate Left Doubleword then Clear Left MDS-form (rldcl. RA,RS,RB,MB) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20, ap_ImmUnsigned_26_26_21_25}}, + {RLDCR, 0xfc00001f, 0x78000012, 0x0, // Rotate Left Doubleword then Clear Right MDS-form (rldcr RA,RS,RB,ME) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20, ap_ImmUnsigned_26_26_21_25}}, + {RLDCRCC, 0xfc00001f, 0x78000013, 0x0, // Rotate Left Doubleword then Clear Right MDS-form (rldcr. RA,RS,RB,ME) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20, ap_ImmUnsigned_26_26_21_25}}, + {RLDIMI, 0xfc00001d, 0x7800000c, 0x0, // Rotate Left Doubleword Immediate then Mask Insert MD-form (rldimi RA,RS,SH,MB) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}}, + {RLDIMICC, 0xfc00001d, 0x7800000d, 0x0, // Rotate Left Doubleword Immediate then Mask Insert MD-form (rldimi. RA,RS,SH,MB) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}}, + {SLW, 0xfc0007ff, 0x7c000030, 0x0, // Shift Left Word X-form (slw RA,RS,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, + {SLWCC, 0xfc0007ff, 0x7c000031, 0x0, // Shift Left Word X-form (slw. RA,RS,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, + {SRW, 0xfc0007ff, 0x7c000430, 0x0, // Shift Right Word X-form (srw RA,RS,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, + {SRWCC, 0xfc0007ff, 0x7c000431, 0x0, // Shift Right Word X-form (srw. RA,RS,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, + {SRAWI, 0xfc0007ff, 0x7c000670, 0x0, // Shift Right Algebraic Word Immediate X-form (srawi RA,RS,SH) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_20}}, + {SRAWICC, 0xfc0007ff, 0x7c000671, 0x0, // Shift Right Algebraic Word Immediate X-form (srawi. RA,RS,SH) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_20}}, + {SRAW, 0xfc0007ff, 0x7c000630, 0x0, // Shift Right Algebraic Word X-form (sraw RA,RS,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, + {SRAWCC, 0xfc0007ff, 0x7c000631, 0x0, // Shift Right Algebraic Word X-form (sraw. RA,RS,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, + {SLD, 0xfc0007ff, 0x7c000036, 0x0, // Shift Left Doubleword X-form (sld RA,RS,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, + {SLDCC, 0xfc0007ff, 0x7c000037, 0x0, // Shift Left Doubleword X-form (sld. RA,RS,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, + {SRD, 0xfc0007ff, 0x7c000436, 0x0, // Shift Right Doubleword X-form (srd RA,RS,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, + {SRDCC, 0xfc0007ff, 0x7c000437, 0x0, // Shift Right Doubleword X-form (srd. RA,RS,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, + {SRADI, 0xfc0007fd, 0x7c000674, 0x0, // Shift Right Algebraic Doubleword Immediate XS-form (sradi RA,RS,SH) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20}}, + {SRADICC, 0xfc0007fd, 0x7c000675, 0x0, // Shift Right Algebraic Doubleword Immediate XS-form (sradi. RA,RS,SH) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20}}, + {SRAD, 0xfc0007ff, 0x7c000634, 0x0, // Shift Right Algebraic Doubleword X-form (srad RA,RS,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, + {SRADCC, 0xfc0007ff, 0x7c000635, 0x0, // Shift Right Algebraic Doubleword X-form (srad. RA,RS,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, + {CDTBCD, 0xfc0007fe, 0x7c000234, 0xf801, // Convert Declets To Binary Coded Decimal X-form (cdtbcd RA, RS) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10}}, + {CBCDTD, 0xfc0007fe, 0x7c000274, 0xf801, // Convert Binary Coded Decimal To Declets X-form (cbcdtd RA, RS) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10}}, + {ADDG6S, 0xfc0003fe, 0x7c000094, 0x401, // Add and Generate Sixes XO-form (addg6s RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MTSPR, 0xfc0007fe, 0x7c0003a6, 0x1, // Move To Special Purpose Register XFX-form (mtspr SPR,RS) + [5]*argField{ap_SpReg_16_20_11_15, ap_Reg_6_10}}, + {MFSPR, 0xfc0007fe, 0x7c0002a6, 0x1, // Move From Special Purpose Register XFX-form (mfspr RT,SPR) + [5]*argField{ap_Reg_6_10, ap_SpReg_16_20_11_15}}, + {MTCRF, 0xfc1007fe, 0x7c000120, 0x801, // Move To Condition Register Fields XFX-form (mtcrf FXM,RS) + [5]*argField{ap_ImmUnsigned_12_19, ap_Reg_6_10}}, + {MFCR, 0xfc1007fe, 0x7c000026, 0xff801, // Move From Condition Register XFX-form (mfcr RT) + [5]*argField{ap_Reg_6_10}}, + {MTSLE, 0xfc0007fe, 0x7c000126, 0x3dff801, // Move To Split Little Endian X-form (mtsle L) + [5]*argField{ap_ImmUnsigned_10_10}}, + {MFVSRD, 0xfc0007fe, 0x7c000066, 0xf800, // Move From VSR Doubleword XX1-form (mfvsrd RA,XS) + [5]*argField{ap_Reg_11_15, ap_VecSReg_31_31_6_10}}, + {MFVSRWZ, 0xfc0007fe, 0x7c0000e6, 0xf800, // Move From VSR Word and Zero XX1-form (mfvsrwz RA,XS) + [5]*argField{ap_Reg_11_15, ap_VecSReg_31_31_6_10}}, + {MTVSRD, 0xfc0007fe, 0x7c000166, 0xf800, // Move To VSR Doubleword XX1-form (mtvsrd XT,RA) + [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15}}, + {MTVSRWA, 0xfc0007fe, 0x7c0001a6, 0xf800, // Move To VSR Word Algebraic XX1-form (mtvsrwa XT,RA) + [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15}}, + {MTVSRWZ, 0xfc0007fe, 0x7c0001e6, 0xf800, // Move To VSR Word and Zero XX1-form (mtvsrwz XT,RA) + [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15}}, + {MTOCRF, 0xfc1007fe, 0x7c100120, 0x801, // Move To One Condition Register Field XFX-form (mtocrf FXM,RS) + [5]*argField{ap_ImmUnsigned_12_19, ap_Reg_6_10}}, + {MFOCRF, 0xfc1007fe, 0x7c100026, 0x801, // Move From One Condition Register Field XFX-form (mfocrf RT,FXM) + [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_12_19}}, + {MCRXR, 0xfc0007fe, 0x7c000400, 0x7ff801, // Move to Condition Register from XER X-form (mcrxr BF) + [5]*argField{ap_CondRegField_6_8}}, + {MTDCRUX, 0xfc0007fe, 0x7c000346, 0xf801, // Move To Device Control Register User-mode Indexed X-form (mtdcrux RS,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {MFDCRUX, 0xfc0007fe, 0x7c000246, 0xf801, // Move From Device Control Register User-mode Indexed X-form (mfdcrux RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {LFS, 0xfc000000, 0xc0000000, 0x0, // Load Floating-Point Single D-form (lfs FRT,D(RA)) + [5]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, + {LFSU, 0xfc000000, 0xc4000000, 0x0, // Load Floating-Point Single with Update D-form (lfsu FRT,D(RA)) + [5]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, + {LFSX, 0xfc0007fe, 0x7c00042e, 0x1, // Load Floating-Point Single Indexed X-form (lfsx FRT,RA,RB) + [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LFSUX, 0xfc0007fe, 0x7c00046e, 0x1, // Load Floating-Point Single with Update Indexed X-form (lfsux FRT,RA,RB) + [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LFD, 0xfc000000, 0xc8000000, 0x0, // Load Floating-Point Double D-form (lfd FRT,D(RA)) + [5]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, + {LFDU, 0xfc000000, 0xcc000000, 0x0, // Load Floating-Point Double with Update D-form (lfdu FRT,D(RA)) + [5]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, + {LFDX, 0xfc0007fe, 0x7c0004ae, 0x1, // Load Floating-Point Double Indexed X-form (lfdx FRT,RA,RB) + [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LFDUX, 0xfc0007fe, 0x7c0004ee, 0x1, // Load Floating-Point Double with Update Indexed X-form (lfdux FRT,RA,RB) + [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LFIWAX, 0xfc0007fe, 0x7c0006ae, 0x1, // Load Floating-Point as Integer Word Algebraic Indexed X-form (lfiwax FRT,RA,RB) + [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LFIWZX, 0xfc0007fe, 0x7c0006ee, 0x1, // Load Floating-Point as Integer Word and Zero Indexed X-form (lfiwzx FRT,RA,RB) + [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STFS, 0xfc000000, 0xd0000000, 0x0, // Store Floating-Point Single D-form (stfs FRS,D(RA)) + [5]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, + {STFSU, 0xfc000000, 0xd4000000, 0x0, // Store Floating-Point Single with Update D-form (stfsu FRS,D(RA)) + [5]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, + {STFSX, 0xfc0007fe, 0x7c00052e, 0x1, // Store Floating-Point Single Indexed X-form (stfsx FRS,RA,RB) + [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STFSUX, 0xfc0007fe, 0x7c00056e, 0x1, // Store Floating-Point Single with Update Indexed X-form (stfsux FRS,RA,RB) + [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STFD, 0xfc000000, 0xd8000000, 0x0, // Store Floating-Point Double D-form (stfd FRS,D(RA)) + [5]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, + {STFDU, 0xfc000000, 0xdc000000, 0x0, // Store Floating-Point Double with Update D-form (stfdu FRS,D(RA)) + [5]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, + {STFDX, 0xfc0007fe, 0x7c0005ae, 0x1, // Store Floating-Point Double Indexed X-form (stfdx FRS,RA,RB) + [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STFDUX, 0xfc0007fe, 0x7c0005ee, 0x1, // Store Floating-Point Double with Update Indexed X-form (stfdux FRS,RA,RB) + [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STFIWX, 0xfc0007fe, 0x7c0007ae, 0x1, // Store Floating-Point as Integer Word Indexed X-form (stfiwx FRS,RA,RB) + [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LFDP, 0xfc000003, 0xe4000000, 0x0, // Load Floating-Point Double Pair DS-form (lfdp FRTp,DS(RA)) + [5]*argField{ap_FPReg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}}, + {LFDPX, 0xfc0007fe, 0x7c00062e, 0x1, // Load Floating-Point Double Pair Indexed X-form (lfdpx FRTp,RA,RB) + [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STFDP, 0xfc000003, 0xf4000000, 0x0, // Store Floating-Point Double Pair DS-form (stfdp FRSp,DS(RA)) + [5]*argField{ap_FPReg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}}, + {STFDPX, 0xfc0007fe, 0x7c00072e, 0x1, // Store Floating-Point Double Pair Indexed X-form (stfdpx FRSp,RA,RB) + [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {FMR, 0xfc0007ff, 0xfc000090, 0x1f0000, // Floating Move Register X-form (fmr FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FMRCC, 0xfc0007ff, 0xfc000091, 0x1f0000, // Floating Move Register X-form (fmr. FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FABS, 0xfc0007ff, 0xfc000210, 0x1f0000, // Floating Absolute Value X-form (fabs FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FABSCC, 0xfc0007ff, 0xfc000211, 0x1f0000, // Floating Absolute Value X-form (fabs. FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FNABS, 0xfc0007ff, 0xfc000110, 0x1f0000, // Floating Negative Absolute Value X-form (fnabs FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FNABSCC, 0xfc0007ff, 0xfc000111, 0x1f0000, // Floating Negative Absolute Value X-form (fnabs. FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FNEG, 0xfc0007ff, 0xfc000050, 0x1f0000, // Floating Negate X-form (fneg FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FNEGCC, 0xfc0007ff, 0xfc000051, 0x1f0000, // Floating Negate X-form (fneg. FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FCPSGN, 0xfc0007ff, 0xfc000010, 0x0, // Floating Copy Sign X-form (fcpsgn FRT, FRA, FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, + {FCPSGNCC, 0xfc0007ff, 0xfc000011, 0x0, // Floating Copy Sign X-form (fcpsgn. FRT, FRA, FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, + {FMRGEW, 0xfc0007fe, 0xfc00078c, 0x1, // Floating Merge Even Word X-form (fmrgew FRT,FRA,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, + {FMRGOW, 0xfc0007fe, 0xfc00068c, 0x1, // Floating Merge Odd Word X-form (fmrgow FRT,FRA,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, + {FADD, 0xfc00003f, 0xfc00002a, 0x7c0, // Floating Add [Single] A-form (fadd FRT,FRA,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, + {FADDCC, 0xfc00003f, 0xfc00002b, 0x7c0, // Floating Add [Single] A-form (fadd. FRT,FRA,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, + {FADDS, 0xfc00003f, 0xec00002a, 0x7c0, // Floating Add [Single] A-form (fadds FRT,FRA,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, + {FADDSCC, 0xfc00003f, 0xec00002b, 0x7c0, // Floating Add [Single] A-form (fadds. FRT,FRA,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, + {FSUB, 0xfc00003f, 0xfc000028, 0x7c0, // Floating Subtract [Single] A-form (fsub FRT,FRA,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, + {FSUBCC, 0xfc00003f, 0xfc000029, 0x7c0, // Floating Subtract [Single] A-form (fsub. FRT,FRA,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, + {FSUBS, 0xfc00003f, 0xec000028, 0x7c0, // Floating Subtract [Single] A-form (fsubs FRT,FRA,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, + {FSUBSCC, 0xfc00003f, 0xec000029, 0x7c0, // Floating Subtract [Single] A-form (fsubs. FRT,FRA,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, + {FMUL, 0xfc00003f, 0xfc000032, 0xf800, // Floating Multiply [Single] A-form (fmul FRT,FRA,FRC) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25}}, + {FMULCC, 0xfc00003f, 0xfc000033, 0xf800, // Floating Multiply [Single] A-form (fmul. FRT,FRA,FRC) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25}}, + {FMULS, 0xfc00003f, 0xec000032, 0xf800, // Floating Multiply [Single] A-form (fmuls FRT,FRA,FRC) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25}}, + {FMULSCC, 0xfc00003f, 0xec000033, 0xf800, // Floating Multiply [Single] A-form (fmuls. FRT,FRA,FRC) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25}}, + {FDIV, 0xfc00003f, 0xfc000024, 0x7c0, // Floating Divide [Single] A-form (fdiv FRT,FRA,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, + {FDIVCC, 0xfc00003f, 0xfc000025, 0x7c0, // Floating Divide [Single] A-form (fdiv. FRT,FRA,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, + {FDIVS, 0xfc00003f, 0xec000024, 0x7c0, // Floating Divide [Single] A-form (fdivs FRT,FRA,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, + {FDIVSCC, 0xfc00003f, 0xec000025, 0x7c0, // Floating Divide [Single] A-form (fdivs. FRT,FRA,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, + {FSQRT, 0xfc00003f, 0xfc00002c, 0x1f07c0, // Floating Square Root [Single] A-form (fsqrt FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FSQRTCC, 0xfc00003f, 0xfc00002d, 0x1f07c0, // Floating Square Root [Single] A-form (fsqrt. FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FSQRTS, 0xfc00003f, 0xec00002c, 0x1f07c0, // Floating Square Root [Single] A-form (fsqrts FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FSQRTSCC, 0xfc00003f, 0xec00002d, 0x1f07c0, // Floating Square Root [Single] A-form (fsqrts. FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FRE, 0xfc00003f, 0xfc000030, 0x1f07c0, // Floating Reciprocal Estimate [Single] A-form (fre FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FRECC, 0xfc00003f, 0xfc000031, 0x1f07c0, // Floating Reciprocal Estimate [Single] A-form (fre. FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FRES, 0xfc00003f, 0xec000030, 0x1f07c0, // Floating Reciprocal Estimate [Single] A-form (fres FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FRESCC, 0xfc00003f, 0xec000031, 0x1f07c0, // Floating Reciprocal Estimate [Single] A-form (fres. FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FRSQRTE, 0xfc00003f, 0xfc000034, 0x1f07c0, // Floating Reciprocal Square Root Estimate [Single] A-form (frsqrte FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FRSQRTECC, 0xfc00003f, 0xfc000035, 0x1f07c0, // Floating Reciprocal Square Root Estimate [Single] A-form (frsqrte. FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FRSQRTES, 0xfc00003f, 0xec000034, 0x1f07c0, // Floating Reciprocal Square Root Estimate [Single] A-form (frsqrtes FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FRSQRTESCC, 0xfc00003f, 0xec000035, 0x1f07c0, // Floating Reciprocal Square Root Estimate [Single] A-form (frsqrtes. FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FTDIV, 0xfc0007fe, 0xfc000100, 0x600001, // Floating Test for software Divide X-form (ftdiv BF,FRA,FRB) + [5]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}}, + {FTSQRT, 0xfc0007fe, 0xfc000140, 0x7f0001, // Floating Test for software Square Root X-form (ftsqrt BF,FRB) + [5]*argField{ap_CondRegField_6_8, ap_FPReg_16_20}}, + {FMADD, 0xfc00003f, 0xfc00003a, 0x0, // Floating Multiply-Add [Single] A-form (fmadd FRT,FRA,FRC,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}}, + {FMADDCC, 0xfc00003f, 0xfc00003b, 0x0, // Floating Multiply-Add [Single] A-form (fmadd. FRT,FRA,FRC,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}}, + {FMADDS, 0xfc00003f, 0xec00003a, 0x0, // Floating Multiply-Add [Single] A-form (fmadds FRT,FRA,FRC,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}}, + {FMADDSCC, 0xfc00003f, 0xec00003b, 0x0, // Floating Multiply-Add [Single] A-form (fmadds. FRT,FRA,FRC,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}}, + {FMSUB, 0xfc00003f, 0xfc000038, 0x0, // Floating Multiply-Subtract [Single] A-form (fmsub FRT,FRA,FRC,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}}, + {FMSUBCC, 0xfc00003f, 0xfc000039, 0x0, // Floating Multiply-Subtract [Single] A-form (fmsub. FRT,FRA,FRC,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}}, + {FMSUBS, 0xfc00003f, 0xec000038, 0x0, // Floating Multiply-Subtract [Single] A-form (fmsubs FRT,FRA,FRC,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}}, + {FMSUBSCC, 0xfc00003f, 0xec000039, 0x0, // Floating Multiply-Subtract [Single] A-form (fmsubs. FRT,FRA,FRC,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}}, + {FNMADD, 0xfc00003f, 0xfc00003e, 0x0, // Floating Negative Multiply-Add [Single] A-form (fnmadd FRT,FRA,FRC,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}}, + {FNMADDCC, 0xfc00003f, 0xfc00003f, 0x0, // Floating Negative Multiply-Add [Single] A-form (fnmadd. FRT,FRA,FRC,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}}, + {FNMADDS, 0xfc00003f, 0xec00003e, 0x0, // Floating Negative Multiply-Add [Single] A-form (fnmadds FRT,FRA,FRC,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}}, + {FNMADDSCC, 0xfc00003f, 0xec00003f, 0x0, // Floating Negative Multiply-Add [Single] A-form (fnmadds. FRT,FRA,FRC,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}}, + {FNMSUB, 0xfc00003f, 0xfc00003c, 0x0, // Floating Negative Multiply-Subtract [Single] A-form (fnmsub FRT,FRA,FRC,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}}, + {FNMSUBCC, 0xfc00003f, 0xfc00003d, 0x0, // Floating Negative Multiply-Subtract [Single] A-form (fnmsub. FRT,FRA,FRC,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}}, + {FNMSUBS, 0xfc00003f, 0xec00003c, 0x0, // Floating Negative Multiply-Subtract [Single] A-form (fnmsubs FRT,FRA,FRC,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}}, + {FNMSUBSCC, 0xfc00003f, 0xec00003d, 0x0, // Floating Negative Multiply-Subtract [Single] A-form (fnmsubs. FRT,FRA,FRC,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}}, + {FRSP, 0xfc0007ff, 0xfc000018, 0x1f0000, // Floating Round to Single-Precision X-form (frsp FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FRSPCC, 0xfc0007ff, 0xfc000019, 0x1f0000, // Floating Round to Single-Precision X-form (frsp. FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FCTID, 0xfc0007ff, 0xfc00065c, 0x1f0000, // Floating Convert To Integer Doubleword X-form (fctid FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FCTIDCC, 0xfc0007ff, 0xfc00065d, 0x1f0000, // Floating Convert To Integer Doubleword X-form (fctid. FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FCTIDZ, 0xfc0007ff, 0xfc00065e, 0x1f0000, // Floating Convert To Integer Doubleword with round toward Zero X-form (fctidz FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FCTIDZCC, 0xfc0007ff, 0xfc00065f, 0x1f0000, // Floating Convert To Integer Doubleword with round toward Zero X-form (fctidz. FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FCTIDU, 0xfc0007ff, 0xfc00075c, 0x1f0000, // Floating Convert To Integer Doubleword Unsigned X-form (fctidu FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FCTIDUCC, 0xfc0007ff, 0xfc00075d, 0x1f0000, // Floating Convert To Integer Doubleword Unsigned X-form (fctidu. FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FCTIDUZ, 0xfc0007ff, 0xfc00075e, 0x1f0000, // Floating Convert To Integer Doubleword Unsigned with round toward Zero X-form (fctiduz FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FCTIDUZCC, 0xfc0007ff, 0xfc00075f, 0x1f0000, // Floating Convert To Integer Doubleword Unsigned with round toward Zero X-form (fctiduz. FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FCTIW, 0xfc0007ff, 0xfc00001c, 0x1f0000, // Floating Convert To Integer Word X-form (fctiw FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FCTIWCC, 0xfc0007ff, 0xfc00001d, 0x1f0000, // Floating Convert To Integer Word X-form (fctiw. FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FCTIWZ, 0xfc0007ff, 0xfc00001e, 0x1f0000, // Floating Convert To Integer Word with round toward Zero X-form (fctiwz FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FCTIWZCC, 0xfc0007ff, 0xfc00001f, 0x1f0000, // Floating Convert To Integer Word with round toward Zero X-form (fctiwz. FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FCTIWU, 0xfc0007ff, 0xfc00011c, 0x1f0000, // Floating Convert To Integer Word Unsigned X-form (fctiwu FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FCTIWUCC, 0xfc0007ff, 0xfc00011d, 0x1f0000, // Floating Convert To Integer Word Unsigned X-form (fctiwu. FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FCTIWUZ, 0xfc0007ff, 0xfc00011e, 0x1f0000, // Floating Convert To Integer Word Unsigned with round toward Zero X-form (fctiwuz FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FCTIWUZCC, 0xfc0007ff, 0xfc00011f, 0x1f0000, // Floating Convert To Integer Word Unsigned with round toward Zero X-form (fctiwuz. FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FCFID, 0xfc0007ff, 0xfc00069c, 0x1f0000, // Floating Convert From Integer Doubleword X-form (fcfid FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FCFIDCC, 0xfc0007ff, 0xfc00069d, 0x1f0000, // Floating Convert From Integer Doubleword X-form (fcfid. FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FCFIDU, 0xfc0007ff, 0xfc00079c, 0x1f0000, // Floating Convert From Integer Doubleword Unsigned X-form (fcfidu FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FCFIDUCC, 0xfc0007ff, 0xfc00079d, 0x1f0000, // Floating Convert From Integer Doubleword Unsigned X-form (fcfidu. FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FCFIDS, 0xfc0007ff, 0xec00069c, 0x1f0000, // Floating Convert From Integer Doubleword Single X-form (fcfids FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FCFIDSCC, 0xfc0007ff, 0xec00069d, 0x1f0000, // Floating Convert From Integer Doubleword Single X-form (fcfids. FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FCFIDUS, 0xfc0007ff, 0xec00079c, 0x1f0000, // Floating Convert From Integer Doubleword Unsigned Single X-form (fcfidus FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FCFIDUSCC, 0xfc0007ff, 0xec00079d, 0x1f0000, // Floating Convert From Integer Doubleword Unsigned Single X-form (fcfidus. FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FRIN, 0xfc0007ff, 0xfc000310, 0x1f0000, // Floating Round to Integer Nearest X-form (frin FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FRINCC, 0xfc0007ff, 0xfc000311, 0x1f0000, // Floating Round to Integer Nearest X-form (frin. FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FRIZ, 0xfc0007ff, 0xfc000350, 0x1f0000, // Floating Round to Integer Toward Zero X-form (friz FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FRIZCC, 0xfc0007ff, 0xfc000351, 0x1f0000, // Floating Round to Integer Toward Zero X-form (friz. FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FRIP, 0xfc0007ff, 0xfc000390, 0x1f0000, // Floating Round to Integer Plus X-form (frip FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FRIPCC, 0xfc0007ff, 0xfc000391, 0x1f0000, // Floating Round to Integer Plus X-form (frip. FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FRIM, 0xfc0007ff, 0xfc0003d0, 0x1f0000, // Floating Round to Integer Minus X-form (frim FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FRIMCC, 0xfc0007ff, 0xfc0003d1, 0x1f0000, // Floating Round to Integer Minus X-form (frim. FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FCMPU, 0xfc0007fe, 0xfc000000, 0x600001, // Floating Compare Unordered X-form (fcmpu BF,FRA,FRB) + [5]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}}, + {FCMPO, 0xfc0007fe, 0xfc000040, 0x600001, // Floating Compare Ordered X-form (fcmpo BF,FRA,FRB) + [5]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}}, + {FSEL, 0xfc00003f, 0xfc00002e, 0x0, // Floating Select A-form (fsel FRT,FRA,FRC,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}}, + {FSELCC, 0xfc00003f, 0xfc00002f, 0x0, // Floating Select A-form (fsel. FRT,FRA,FRC,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}}, + {MFFS, 0xfc0007ff, 0xfc00048e, 0x1ff800, // Move From FPSCR X-form (mffs FRT) + [5]*argField{ap_FPReg_6_10}}, + {MFFSCC, 0xfc0007ff, 0xfc00048f, 0x1ff800, // Move From FPSCR X-form (mffs. FRT) + [5]*argField{ap_FPReg_6_10}}, + {MCRFS, 0xfc0007fe, 0xfc000080, 0x63f801, // Move to Condition Register from FPSCR X-form (mcrfs BF,BFA) + [5]*argField{ap_CondRegField_6_8, ap_CondRegField_11_13}}, + {MTFSFI, 0xfc0007ff, 0xfc00010c, 0x7e0800, // Move To FPSCR Field Immediate X-form (mtfsfi BF,U,W) + [5]*argField{ap_CondRegField_6_8, ap_ImmUnsigned_16_19, ap_ImmUnsigned_15_15}}, + {MTFSFICC, 0xfc0007ff, 0xfc00010d, 0x7e0800, // Move To FPSCR Field Immediate X-form (mtfsfi. BF,U,W) + [5]*argField{ap_CondRegField_6_8, ap_ImmUnsigned_16_19, ap_ImmUnsigned_15_15}}, + {MTFSF, 0xfc0007ff, 0xfc00058e, 0x0, // Move To FPSCR Fields XFL-form (mtfsf FLM,FRB,L,W) + [5]*argField{ap_ImmUnsigned_7_14, ap_FPReg_16_20, ap_ImmUnsigned_6_6, ap_ImmUnsigned_15_15}}, + {MTFSFCC, 0xfc0007ff, 0xfc00058f, 0x0, // Move To FPSCR Fields XFL-form (mtfsf. FLM,FRB,L,W) + [5]*argField{ap_ImmUnsigned_7_14, ap_FPReg_16_20, ap_ImmUnsigned_6_6, ap_ImmUnsigned_15_15}}, + {MTFSB0, 0xfc0007ff, 0xfc00008c, 0x1ff800, // Move To FPSCR Bit 0 X-form (mtfsb0 BT) + [5]*argField{ap_CondRegBit_6_10}}, + {MTFSB0CC, 0xfc0007ff, 0xfc00008d, 0x1ff800, // Move To FPSCR Bit 0 X-form (mtfsb0. BT) + [5]*argField{ap_CondRegBit_6_10}}, + {MTFSB1, 0xfc0007ff, 0xfc00004c, 0x1ff800, // Move To FPSCR Bit 1 X-form (mtfsb1 BT) + [5]*argField{ap_CondRegBit_6_10}}, + {MTFSB1CC, 0xfc0007ff, 0xfc00004d, 0x1ff800, // Move To FPSCR Bit 1 X-form (mtfsb1. BT) + [5]*argField{ap_CondRegBit_6_10}}, + {LVEBX, 0xfc0007fe, 0x7c00000e, 0x1, // Load Vector Element Byte Indexed X-form (lvebx VRT,RA,RB) + [5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LVEHX, 0xfc0007fe, 0x7c00004e, 0x1, // Load Vector Element Halfword Indexed X-form (lvehx VRT,RA,RB) + [5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LVEWX, 0xfc0007fe, 0x7c00008e, 0x1, // Load Vector Element Word Indexed X-form (lvewx VRT,RA,RB) + [5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LVX, 0xfc0007fe, 0x7c0000ce, 0x1, // Load Vector Indexed X-form (lvx VRT,RA,RB) + [5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LVXL, 0xfc0007fe, 0x7c0002ce, 0x1, // Load Vector Indexed LRU X-form (lvxl VRT,RA,RB) + [5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STVEBX, 0xfc0007fe, 0x7c00010e, 0x1, // Store Vector Element Byte Indexed X-form (stvebx VRS,RA,RB) + [5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STVEHX, 0xfc0007fe, 0x7c00014e, 0x1, // Store Vector Element Halfword Indexed X-form (stvehx VRS,RA,RB) + [5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STVEWX, 0xfc0007fe, 0x7c00018e, 0x1, // Store Vector Element Word Indexed X-form (stvewx VRS,RA,RB) + [5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STVX, 0xfc0007fe, 0x7c0001ce, 0x1, // Store Vector Indexed X-form (stvx VRS,RA,RB) + [5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STVXL, 0xfc0007fe, 0x7c0003ce, 0x1, // Store Vector Indexed LRU X-form (stvxl VRS,RA,RB) + [5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LVSL, 0xfc0007fe, 0x7c00000c, 0x1, // Load Vector for Shift Left Indexed X-form (lvsl VRT,RA,RB) + [5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LVSR, 0xfc0007fe, 0x7c00004c, 0x1, // Load Vector for Shift Right Indexed X-form (lvsr VRT,RA,RB) + [5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {VPKPX, 0xfc0007ff, 0x1000030e, 0x0, // Vector Pack Pixel VX-form (vpkpx VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VPKSDSS, 0xfc0007ff, 0x100005ce, 0x0, // Vector Pack Signed Doubleword Signed Saturate VX-form (vpksdss VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VPKSDUS, 0xfc0007ff, 0x1000054e, 0x0, // Vector Pack Signed Doubleword Unsigned Saturate VX-form (vpksdus VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VPKSHSS, 0xfc0007ff, 0x1000018e, 0x0, // Vector Pack Signed Halfword Signed Saturate VX-form (vpkshss VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VPKSHUS, 0xfc0007ff, 0x1000010e, 0x0, // Vector Pack Signed Halfword Unsigned Saturate VX-form (vpkshus VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VPKSWSS, 0xfc0007ff, 0x100001ce, 0x0, // Vector Pack Signed Word Signed Saturate VX-form (vpkswss VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VPKSWUS, 0xfc0007ff, 0x1000014e, 0x0, // Vector Pack Signed Word Unsigned Saturate VX-form (vpkswus VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VPKUDUM, 0xfc0007ff, 0x1000044e, 0x0, // Vector Pack Unsigned Doubleword Unsigned Modulo VX-form (vpkudum VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VPKUDUS, 0xfc0007ff, 0x100004ce, 0x0, // Vector Pack Unsigned Doubleword Unsigned Saturate VX-form (vpkudus VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VPKUHUM, 0xfc0007ff, 0x1000000e, 0x0, // Vector Pack Unsigned Halfword Unsigned Modulo VX-form (vpkuhum VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VPKUHUS, 0xfc0007ff, 0x1000008e, 0x0, // Vector Pack Unsigned Halfword Unsigned Saturate VX-form (vpkuhus VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VPKUWUM, 0xfc0007ff, 0x1000004e, 0x0, // Vector Pack Unsigned Word Unsigned Modulo VX-form (vpkuwum VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VPKUWUS, 0xfc0007ff, 0x100000ce, 0x0, // Vector Pack Unsigned Word Unsigned Saturate VX-form (vpkuwus VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VUPKHPX, 0xfc0007ff, 0x1000034e, 0x1f0000, // Vector Unpack High Pixel VX-form (vupkhpx VRT,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, + {VUPKLPX, 0xfc0007ff, 0x100003ce, 0x1f0000, // Vector Unpack Low Pixel VX-form (vupklpx VRT,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, + {VUPKHSB, 0xfc0007ff, 0x1000020e, 0x1f0000, // Vector Unpack High Signed Byte VX-form (vupkhsb VRT,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, + {VUPKHSH, 0xfc0007ff, 0x1000024e, 0x1f0000, // Vector Unpack High Signed Halfword VX-form (vupkhsh VRT,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, + {VUPKHSW, 0xfc0007ff, 0x1000064e, 0x1f0000, // Vector Unpack High Signed Word VX-form (vupkhsw VRT,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, + {VUPKLSB, 0xfc0007ff, 0x1000028e, 0x1f0000, // Vector Unpack Low Signed Byte VX-form (vupklsb VRT,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, + {VUPKLSH, 0xfc0007ff, 0x100002ce, 0x1f0000, // Vector Unpack Low Signed Halfword VX-form (vupklsh VRT,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, + {VUPKLSW, 0xfc0007ff, 0x100006ce, 0x1f0000, // Vector Unpack Low Signed Word VX-form (vupklsw VRT,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, + {VMRGHB, 0xfc0007ff, 0x1000000c, 0x0, // Vector Merge High Byte VX-form (vmrghb VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VMRGHH, 0xfc0007ff, 0x1000004c, 0x0, // Vector Merge High Halfword VX-form (vmrghh VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VMRGLB, 0xfc0007ff, 0x1000010c, 0x0, // Vector Merge Low Byte VX-form (vmrglb VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VMRGLH, 0xfc0007ff, 0x1000014c, 0x0, // Vector Merge Low Halfword VX-form (vmrglh VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VMRGHW, 0xfc0007ff, 0x1000008c, 0x0, // Vector Merge High Word VX-form (vmrghw VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VMRGLW, 0xfc0007ff, 0x1000018c, 0x0, // Vector Merge Low Word VX-form (vmrglw VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VMRGEW, 0xfc0007ff, 0x1000078c, 0x0, // Vector Merge Even Word VX-form (vmrgew VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VMRGOW, 0xfc0007ff, 0x1000068c, 0x0, // Vector Merge Odd Word VX-form (vmrgow VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VSPLTB, 0xfc0007ff, 0x1000020c, 0x100000, // Vector Splat Byte VX-form (vspltb VRT,VRB,UIM) + [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_12_15}}, + {VSPLTH, 0xfc0007ff, 0x1000024c, 0x180000, // Vector Splat Halfword VX-form (vsplth VRT,VRB,UIM) + [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_13_15}}, + {VSPLTW, 0xfc0007ff, 0x1000028c, 0x1c0000, // Vector Splat Word VX-form (vspltw VRT,VRB,UIM) + [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_14_15}}, + {VSPLTISB, 0xfc0007ff, 0x1000030c, 0xf800, // Vector Splat Immediate Signed Byte VX-form (vspltisb VRT,SIM) + [5]*argField{ap_VecReg_6_10, ap_ImmSigned_11_15}}, + {VSPLTISH, 0xfc0007ff, 0x1000034c, 0xf800, // Vector Splat Immediate Signed Halfword VX-form (vspltish VRT,SIM) + [5]*argField{ap_VecReg_6_10, ap_ImmSigned_11_15}}, + {VSPLTISW, 0xfc0007ff, 0x1000038c, 0xf800, // Vector Splat Immediate Signed Word VX-form (vspltisw VRT,SIM) + [5]*argField{ap_VecReg_6_10, ap_ImmSigned_11_15}}, + {VPERM, 0xfc00003f, 0x1000002b, 0x0, // Vector Permute VA-form (vperm VRT,VRA,VRB,VRC) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}}, + {VSEL, 0xfc00003f, 0x1000002a, 0x0, // Vector Select VA-form (vsel VRT,VRA,VRB,VRC) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}}, + {VSL, 0xfc0007ff, 0x100001c4, 0x0, // Vector Shift Left VX-form (vsl VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VSLDOI, 0xfc00003f, 0x1000002c, 0x400, // Vector Shift Left Double by Octet Immediate VA-form (vsldoi VRT,VRA,VRB,SHB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_ImmUnsigned_22_25}}, + {VSLO, 0xfc0007ff, 0x1000040c, 0x0, // Vector Shift Left by Octet VX-form (vslo VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VSR, 0xfc0007ff, 0x100002c4, 0x0, // Vector Shift Right VX-form (vsr VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VSRO, 0xfc0007ff, 0x1000044c, 0x0, // Vector Shift Right by Octet VX-form (vsro VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VADDCUW, 0xfc0007ff, 0x10000180, 0x0, // Vector Add and Write Carry-Out Unsigned Word VX-form (vaddcuw VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VADDSBS, 0xfc0007ff, 0x10000300, 0x0, // Vector Add Signed Byte Saturate VX-form (vaddsbs VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VADDSHS, 0xfc0007ff, 0x10000340, 0x0, // Vector Add Signed Halfword Saturate VX-form (vaddshs VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VADDSWS, 0xfc0007ff, 0x10000380, 0x0, // Vector Add Signed Word Saturate VX-form (vaddsws VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VADDUBM, 0xfc0007ff, 0x10000000, 0x0, // Vector Add Unsigned Byte Modulo VX-form (vaddubm VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VADDUDM, 0xfc0007ff, 0x100000c0, 0x0, // Vector Add Unsigned Doubleword Modulo VX-form (vaddudm VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VADDUHM, 0xfc0007ff, 0x10000040, 0x0, // Vector Add Unsigned Halfword Modulo VX-form (vadduhm VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VADDUWM, 0xfc0007ff, 0x10000080, 0x0, // Vector Add Unsigned Word Modulo VX-form (vadduwm VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VADDUBS, 0xfc0007ff, 0x10000200, 0x0, // Vector Add Unsigned Byte Saturate VX-form (vaddubs VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VADDUHS, 0xfc0007ff, 0x10000240, 0x0, // Vector Add Unsigned Halfword Saturate VX-form (vadduhs VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VADDUWS, 0xfc0007ff, 0x10000280, 0x0, // Vector Add Unsigned Word Saturate VX-form (vadduws VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VADDUQM, 0xfc0007ff, 0x10000100, 0x0, // Vector Add Unsigned Quadword Modulo VX-form (vadduqm VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VADDEUQM, 0xfc00003f, 0x1000003c, 0x0, // Vector Add Extended Unsigned Quadword Modulo VA-form (vaddeuqm VRT,VRA,VRB,VRC) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}}, + {VADDCUQ, 0xfc0007ff, 0x10000140, 0x0, // Vector Add & write Carry Unsigned Quadword VX-form (vaddcuq VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VADDECUQ, 0xfc00003f, 0x1000003d, 0x0, // Vector Add Extended & write Carry Unsigned Quadword VA-form (vaddecuq VRT,VRA,VRB,VRC) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}}, + {VSUBCUW, 0xfc0007ff, 0x10000580, 0x0, // Vector Subtract and Write Carry-Out Unsigned Word VX-form (vsubcuw VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VSUBSBS, 0xfc0007ff, 0x10000700, 0x0, // Vector Subtract Signed Byte Saturate VX-form (vsubsbs VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VSUBSHS, 0xfc0007ff, 0x10000740, 0x0, // Vector Subtract Signed Halfword Saturate VX-form (vsubshs VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VSUBSWS, 0xfc0007ff, 0x10000780, 0x0, // Vector Subtract Signed Word Saturate VX-form (vsubsws VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VSUBUBM, 0xfc0007ff, 0x10000400, 0x0, // Vector Subtract Unsigned Byte Modulo VX-form (vsububm VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VSUBUDM, 0xfc0007ff, 0x100004c0, 0x0, // Vector Subtract Unsigned Doubleword Modulo VX-form (vsubudm VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VSUBUHM, 0xfc0007ff, 0x10000440, 0x0, // Vector Subtract Unsigned Halfword Modulo VX-form (vsubuhm VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VSUBUWM, 0xfc0007ff, 0x10000480, 0x0, // Vector Subtract Unsigned Word Modulo VX-form (vsubuwm VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VSUBUBS, 0xfc0007ff, 0x10000600, 0x0, // Vector Subtract Unsigned Byte Saturate VX-form (vsububs VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VSUBUHS, 0xfc0007ff, 0x10000640, 0x0, // Vector Subtract Unsigned Halfword Saturate VX-form (vsubuhs VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VSUBUWS, 0xfc0007ff, 0x10000680, 0x0, // Vector Subtract Unsigned Word Saturate VX-form (vsubuws VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VSUBUQM, 0xfc0007ff, 0x10000500, 0x0, // Vector Subtract Unsigned Quadword Modulo VX-form (vsubuqm VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VSUBEUQM, 0xfc00003f, 0x1000003e, 0x0, // Vector Subtract Extended Unsigned Quadword Modulo VA-form (vsubeuqm VRT,VRA,VRB,VRC) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}}, + {VSUBCUQ, 0xfc0007ff, 0x10000540, 0x0, // Vector Subtract & write Carry Unsigned Quadword VX-form (vsubcuq VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VSUBECUQ, 0xfc00003f, 0x1000003f, 0x0, // Vector Subtract Extended & write Carry Unsigned Quadword VA-form (vsubecuq VRT,VRA,VRB,VRC) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}}, + {VMULESB, 0xfc0007ff, 0x10000308, 0x0, // Vector Multiply Even Signed Byte VX-form (vmulesb VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VMULEUB, 0xfc0007ff, 0x10000208, 0x0, // Vector Multiply Even Unsigned Byte VX-form (vmuleub VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VMULOSB, 0xfc0007ff, 0x10000108, 0x0, // Vector Multiply Odd Signed Byte VX-form (vmulosb VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VMULOUB, 0xfc0007ff, 0x10000008, 0x0, // Vector Multiply Odd Unsigned Byte VX-form (vmuloub VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VMULESH, 0xfc0007ff, 0x10000348, 0x0, // Vector Multiply Even Signed Halfword VX-form (vmulesh VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VMULEUH, 0xfc0007ff, 0x10000248, 0x0, // Vector Multiply Even Unsigned Halfword VX-form (vmuleuh VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VMULOSH, 0xfc0007ff, 0x10000148, 0x0, // Vector Multiply Odd Signed Halfword VX-form (vmulosh VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VMULOUH, 0xfc0007ff, 0x10000048, 0x0, // Vector Multiply Odd Unsigned Halfword VX-form (vmulouh VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VMULESW, 0xfc0007ff, 0x10000388, 0x0, // Vector Multiply Even Signed Word VX-form (vmulesw VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VMULEUW, 0xfc0007ff, 0x10000288, 0x0, // Vector Multiply Even Unsigned Word VX-form (vmuleuw VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VMULOSW, 0xfc0007ff, 0x10000188, 0x0, // Vector Multiply Odd Signed Word VX-form (vmulosw VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VMULOUW, 0xfc0007ff, 0x10000088, 0x0, // Vector Multiply Odd Unsigned Word VX-form (vmulouw VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VMULUWM, 0xfc0007ff, 0x10000089, 0x0, // Vector Multiply Unsigned Word Modulo VX-form (vmuluwm VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VMHADDSHS, 0xfc00003f, 0x10000020, 0x0, // Vector Multiply-High-Add Signed Halfword Saturate VA-form (vmhaddshs VRT,VRA,VRB,VRC) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}}, + {VMHRADDSHS, 0xfc00003f, 0x10000021, 0x0, // Vector Multiply-High-Round-Add Signed Halfword Saturate VA-form (vmhraddshs VRT,VRA,VRB,VRC) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}}, + {VMLADDUHM, 0xfc00003f, 0x10000022, 0x0, // Vector Multiply-Low-Add Unsigned Halfword Modulo VA-form (vmladduhm VRT,VRA,VRB,VRC) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}}, + {VMSUMUBM, 0xfc00003f, 0x10000024, 0x0, // Vector Multiply-Sum Unsigned Byte Modulo VA-form (vmsumubm VRT,VRA,VRB,VRC) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}}, + {VMSUMMBM, 0xfc00003f, 0x10000025, 0x0, // Vector Multiply-Sum Mixed Byte Modulo VA-form (vmsummbm VRT,VRA,VRB,VRC) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}}, + {VMSUMSHM, 0xfc00003f, 0x10000028, 0x0, // Vector Multiply-Sum Signed Halfword Modulo VA-form (vmsumshm VRT,VRA,VRB,VRC) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}}, + {VMSUMSHS, 0xfc00003f, 0x10000029, 0x0, // Vector Multiply-Sum Signed Halfword Saturate VA-form (vmsumshs VRT,VRA,VRB,VRC) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}}, + {VMSUMUHM, 0xfc00003f, 0x10000026, 0x0, // Vector Multiply-Sum Unsigned Halfword Modulo VA-form (vmsumuhm VRT,VRA,VRB,VRC) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}}, + {VMSUMUHS, 0xfc00003f, 0x10000027, 0x0, // Vector Multiply-Sum Unsigned Halfword Saturate VA-form (vmsumuhs VRT,VRA,VRB,VRC) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}}, + {VSUMSWS, 0xfc0007ff, 0x10000788, 0x0, // Vector Sum across Signed Word Saturate VX-form (vsumsws VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VSUM2SWS, 0xfc0007ff, 0x10000688, 0x0, // Vector Sum across Half Signed Word Saturate VX-form (vsum2sws VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VSUM4SBS, 0xfc0007ff, 0x10000708, 0x0, // Vector Sum across Quarter Signed Byte Saturate VX-form (vsum4sbs VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VSUM4SHS, 0xfc0007ff, 0x10000648, 0x0, // Vector Sum across Quarter Signed Halfword Saturate VX-form (vsum4shs VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VSUM4UBS, 0xfc0007ff, 0x10000608, 0x0, // Vector Sum across Quarter Unsigned Byte Saturate VX-form (vsum4ubs VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VAVGSB, 0xfc0007ff, 0x10000502, 0x0, // Vector Average Signed Byte VX-form (vavgsb VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VAVGSH, 0xfc0007ff, 0x10000542, 0x0, // Vector Average Signed Halfword VX-form (vavgsh VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VAVGSW, 0xfc0007ff, 0x10000582, 0x0, // Vector Average Signed Word VX-form (vavgsw VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VAVGUB, 0xfc0007ff, 0x10000402, 0x0, // Vector Average Unsigned Byte VX-form (vavgub VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VAVGUW, 0xfc0007ff, 0x10000482, 0x0, // Vector Average Unsigned Word VX-form (vavguw VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VAVGUH, 0xfc0007ff, 0x10000442, 0x0, // Vector Average Unsigned Halfword VX-form (vavguh VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VMAXSB, 0xfc0007ff, 0x10000102, 0x0, // Vector Maximum Signed Byte VX-form (vmaxsb VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VMAXSD, 0xfc0007ff, 0x100001c2, 0x0, // Vector Maximum Signed Doubleword VX-form (vmaxsd VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VMAXUB, 0xfc0007ff, 0x10000002, 0x0, // Vector Maximum Unsigned Byte VX-form (vmaxub VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VMAXUD, 0xfc0007ff, 0x100000c2, 0x0, // Vector Maximum Unsigned Doubleword VX-form (vmaxud VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VMAXSH, 0xfc0007ff, 0x10000142, 0x0, // Vector Maximum Signed Halfword VX-form (vmaxsh VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VMAXSW, 0xfc0007ff, 0x10000182, 0x0, // Vector Maximum Signed Word VX-form (vmaxsw VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VMAXUH, 0xfc0007ff, 0x10000042, 0x0, // Vector Maximum Unsigned Halfword VX-form (vmaxuh VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VMAXUW, 0xfc0007ff, 0x10000082, 0x0, // Vector Maximum Unsigned Word VX-form (vmaxuw VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VMINSB, 0xfc0007ff, 0x10000302, 0x0, // Vector Minimum Signed Byte VX-form (vminsb VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VMINSD, 0xfc0007ff, 0x100003c2, 0x0, // Vector Minimum Signed Doubleword VX-form (vminsd VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VMINUB, 0xfc0007ff, 0x10000202, 0x0, // Vector Minimum Unsigned Byte VX-form (vminub VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VMINUD, 0xfc0007ff, 0x100002c2, 0x0, // Vector Minimum Unsigned Doubleword VX-form (vminud VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VMINSH, 0xfc0007ff, 0x10000342, 0x0, // Vector Minimum Signed Halfword VX-form (vminsh VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VMINSW, 0xfc0007ff, 0x10000382, 0x0, // Vector Minimum Signed Word VX-form (vminsw VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VMINUH, 0xfc0007ff, 0x10000242, 0x0, // Vector Minimum Unsigned Halfword VX-form (vminuh VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VMINUW, 0xfc0007ff, 0x10000282, 0x0, // Vector Minimum Unsigned Word VX-form (vminuw VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VCMPEQUB, 0xfc0007ff, 0x10000006, 0x0, // Vector Compare Equal To Unsigned Byte VC-form (vcmpequb VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VCMPEQUBCC, 0xfc0007ff, 0x10000406, 0x0, // Vector Compare Equal To Unsigned Byte VC-form (vcmpequb. VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VCMPEQUH, 0xfc0007ff, 0x10000046, 0x0, // Vector Compare Equal To Unsigned Halfword VC-form (vcmpequh VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VCMPEQUHCC, 0xfc0007ff, 0x10000446, 0x0, // Vector Compare Equal To Unsigned Halfword VC-form (vcmpequh. VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VCMPEQUW, 0xfc0007ff, 0x10000086, 0x0, // Vector Compare Equal To Unsigned Word VC-form (vcmpequw VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VCMPEQUWCC, 0xfc0007ff, 0x10000486, 0x0, // Vector Compare Equal To Unsigned Word VC-form (vcmpequw. VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VCMPEQUD, 0xfc0007ff, 0x100000c7, 0x0, // Vector Compare Equal To Unsigned Doubleword VX-form (vcmpequd VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VCMPEQUDCC, 0xfc0007ff, 0x100004c7, 0x0, // Vector Compare Equal To Unsigned Doubleword VX-form (vcmpequd. VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VCMPGTSB, 0xfc0007ff, 0x10000306, 0x0, // Vector Compare Greater Than Signed Byte VC-form (vcmpgtsb VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VCMPGTSBCC, 0xfc0007ff, 0x10000706, 0x0, // Vector Compare Greater Than Signed Byte VC-form (vcmpgtsb. VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VCMPGTSD, 0xfc0007ff, 0x100003c7, 0x0, // Vector Compare Greater Than Signed Doubleword VX-form (vcmpgtsd VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VCMPGTSDCC, 0xfc0007ff, 0x100007c7, 0x0, // Vector Compare Greater Than Signed Doubleword VX-form (vcmpgtsd. VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VCMPGTSH, 0xfc0007ff, 0x10000346, 0x0, // Vector Compare Greater Than Signed Halfword VC-form (vcmpgtsh VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VCMPGTSHCC, 0xfc0007ff, 0x10000746, 0x0, // Vector Compare Greater Than Signed Halfword VC-form (vcmpgtsh. VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VCMPGTSW, 0xfc0007ff, 0x10000386, 0x0, // Vector Compare Greater Than Signed Word VC-form (vcmpgtsw VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VCMPGTSWCC, 0xfc0007ff, 0x10000786, 0x0, // Vector Compare Greater Than Signed Word VC-form (vcmpgtsw. VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VCMPGTUB, 0xfc0007ff, 0x10000206, 0x0, // Vector Compare Greater Than Unsigned Byte VC-form (vcmpgtub VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VCMPGTUBCC, 0xfc0007ff, 0x10000606, 0x0, // Vector Compare Greater Than Unsigned Byte VC-form (vcmpgtub. VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VCMPGTUD, 0xfc0007ff, 0x100002c7, 0x0, // Vector Compare Greater Than Unsigned Doubleword VX-form (vcmpgtud VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VCMPGTUDCC, 0xfc0007ff, 0x100006c7, 0x0, // Vector Compare Greater Than Unsigned Doubleword VX-form (vcmpgtud. VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VCMPGTUH, 0xfc0007ff, 0x10000246, 0x0, // Vector Compare Greater Than Unsigned Halfword VC-form (vcmpgtuh VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VCMPGTUHCC, 0xfc0007ff, 0x10000646, 0x0, // Vector Compare Greater Than Unsigned Halfword VC-form (vcmpgtuh. VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VCMPGTUW, 0xfc0007ff, 0x10000286, 0x0, // Vector Compare Greater Than Unsigned Word VC-form (vcmpgtuw VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VCMPGTUWCC, 0xfc0007ff, 0x10000686, 0x0, // Vector Compare Greater Than Unsigned Word VC-form (vcmpgtuw. VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VAND, 0xfc0007ff, 0x10000404, 0x0, // Vector Logical AND VX-form (vand VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VANDC, 0xfc0007ff, 0x10000444, 0x0, // Vector Logical AND with Complement VX-form (vandc VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VEQV, 0xfc0007ff, 0x10000684, 0x0, // Vector Logical Equivalent VX-form (veqv VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VNAND, 0xfc0007ff, 0x10000584, 0x0, // Vector Logical NAND VX-form (vnand VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VORC, 0xfc0007ff, 0x10000544, 0x0, // Vector Logical OR with Complement VX-form (vorc VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VNOR, 0xfc0007ff, 0x10000504, 0x0, // Vector Logical NOR VX-form (vnor VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VOR, 0xfc0007ff, 0x10000484, 0x0, // Vector Logical OR VX-form (vor VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VXOR, 0xfc0007ff, 0x100004c4, 0x0, // Vector Logical XOR VX-form (vxor VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VRLB, 0xfc0007ff, 0x10000004, 0x0, // Vector Rotate Left Byte VX-form (vrlb VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VRLH, 0xfc0007ff, 0x10000044, 0x0, // Vector Rotate Left Halfword VX-form (vrlh VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VRLW, 0xfc0007ff, 0x10000084, 0x0, // Vector Rotate Left Word VX-form (vrlw VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VRLD, 0xfc0007ff, 0x100000c4, 0x0, // Vector Rotate Left Doubleword VX-form (vrld VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VSLB, 0xfc0007ff, 0x10000104, 0x0, // Vector Shift Left Byte VX-form (vslb VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VSLH, 0xfc0007ff, 0x10000144, 0x0, // Vector Shift Left Halfword VX-form (vslh VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VSLW, 0xfc0007ff, 0x10000184, 0x0, // Vector Shift Left Word VX-form (vslw VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VSLD, 0xfc0007ff, 0x100005c4, 0x0, // Vector Shift Left Doubleword VX-form (vsld VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VSRB, 0xfc0007ff, 0x10000204, 0x0, // Vector Shift Right Byte VX-form (vsrb VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VSRH, 0xfc0007ff, 0x10000244, 0x0, // Vector Shift Right Halfword VX-form (vsrh VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VSRW, 0xfc0007ff, 0x10000284, 0x0, // Vector Shift Right Word VX-form (vsrw VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VSRD, 0xfc0007ff, 0x100006c4, 0x0, // Vector Shift Right Doubleword VX-form (vsrd VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VSRAB, 0xfc0007ff, 0x10000304, 0x0, // Vector Shift Right Algebraic Byte VX-form (vsrab VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VSRAH, 0xfc0007ff, 0x10000344, 0x0, // Vector Shift Right Algebraic Halfword VX-form (vsrah VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VSRAW, 0xfc0007ff, 0x10000384, 0x0, // Vector Shift Right Algebraic Word VX-form (vsraw VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VSRAD, 0xfc0007ff, 0x100003c4, 0x0, // Vector Shift Right Algebraic Doubleword VX-form (vsrad VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VADDFP, 0xfc0007ff, 0x1000000a, 0x0, // Vector Add Single-Precision VX-form (vaddfp VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VSUBFP, 0xfc0007ff, 0x1000004a, 0x0, // Vector Subtract Single-Precision VX-form (vsubfp VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VMADDFP, 0xfc00003f, 0x1000002e, 0x0, // Vector Multiply-Add Single-Precision VA-form (vmaddfp VRT,VRA,VRC,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_21_25, ap_VecReg_16_20}}, + {VNMSUBFP, 0xfc00003f, 0x1000002f, 0x0, // Vector Negative Multiply-Subtract Single-Precision VA-form (vnmsubfp VRT,VRA,VRC,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_21_25, ap_VecReg_16_20}}, + {VMAXFP, 0xfc0007ff, 0x1000040a, 0x0, // Vector Maximum Single-Precision VX-form (vmaxfp VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VMINFP, 0xfc0007ff, 0x1000044a, 0x0, // Vector Minimum Single-Precision VX-form (vminfp VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VCTSXS, 0xfc0007ff, 0x100003ca, 0x0, // Vector Convert To Signed Fixed-Point Word Saturate VX-form (vctsxs VRT,VRB,UIM) + [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_11_15}}, + {VCTUXS, 0xfc0007ff, 0x1000038a, 0x0, // Vector Convert To Unsigned Fixed-Point Word Saturate VX-form (vctuxs VRT,VRB,UIM) + [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_11_15}}, + {VCFSX, 0xfc0007ff, 0x1000034a, 0x0, // Vector Convert From Signed Fixed-Point Word VX-form (vcfsx VRT,VRB,UIM) + [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_11_15}}, + {VCFUX, 0xfc0007ff, 0x1000030a, 0x0, // Vector Convert From Unsigned Fixed-Point Word VX-form (vcfux VRT,VRB,UIM) + [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_11_15}}, + {VRFIM, 0xfc0007ff, 0x100002ca, 0x1f0000, // Vector Round to Single-Precision Integer toward -Infinity VX-form (vrfim VRT,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, + {VRFIN, 0xfc0007ff, 0x1000020a, 0x1f0000, // Vector Round to Single-Precision Integer Nearest VX-form (vrfin VRT,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, + {VRFIP, 0xfc0007ff, 0x1000028a, 0x1f0000, // Vector Round to Single-Precision Integer toward +Infinity VX-form (vrfip VRT,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, + {VRFIZ, 0xfc0007ff, 0x1000024a, 0x1f0000, // Vector Round to Single-Precision Integer toward Zero VX-form (vrfiz VRT,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, + {VCMPBFP, 0xfc0007ff, 0x100003c6, 0x0, // Vector Compare Bounds Single-Precision VC-form (vcmpbfp VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VCMPBFPCC, 0xfc0007ff, 0x100007c6, 0x0, // Vector Compare Bounds Single-Precision VC-form (vcmpbfp. VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VCMPEQFP, 0xfc0007ff, 0x100000c6, 0x0, // Vector Compare Equal To Single-Precision VC-form (vcmpeqfp VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VCMPEQFPCC, 0xfc0007ff, 0x100004c6, 0x0, // Vector Compare Equal To Single-Precision VC-form (vcmpeqfp. VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VCMPGEFP, 0xfc0007ff, 0x100001c6, 0x0, // Vector Compare Greater Than or Equal To Single-Precision VC-form (vcmpgefp VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VCMPGEFPCC, 0xfc0007ff, 0x100005c6, 0x0, // Vector Compare Greater Than or Equal To Single-Precision VC-form (vcmpgefp. VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VCMPGTFP, 0xfc0007ff, 0x100002c6, 0x0, // Vector Compare Greater Than Single-Precision VC-form (vcmpgtfp VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VCMPGTFPCC, 0xfc0007ff, 0x100006c6, 0x0, // Vector Compare Greater Than Single-Precision VC-form (vcmpgtfp. VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VEXPTEFP, 0xfc0007ff, 0x1000018a, 0x1f0000, // Vector 2 Raised to the Exponent Estimate Floating-Point VX-form (vexptefp VRT,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, + {VLOGEFP, 0xfc0007ff, 0x100001ca, 0x1f0000, // Vector Log Base 2 Estimate Floating-Point VX-form (vlogefp VRT,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, + {VREFP, 0xfc0007ff, 0x1000010a, 0x1f0000, // Vector Reciprocal Estimate Single-Precision VX-form (vrefp VRT,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, + {VRSQRTEFP, 0xfc0007ff, 0x1000014a, 0x1f0000, // Vector Reciprocal Square Root Estimate Single-Precision VX-form (vrsqrtefp VRT,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, + {VCIPHER, 0xfc0007ff, 0x10000508, 0x0, // Vector AES Cipher VX-form (vcipher VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VCIPHERLAST, 0xfc0007ff, 0x10000509, 0x0, // Vector AES Cipher Last VX-form (vcipherlast VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VNCIPHER, 0xfc0007ff, 0x10000548, 0x0, // Vector AES Inverse Cipher VX-form (vncipher VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VNCIPHERLAST, 0xfc0007ff, 0x10000549, 0x0, // Vector AES Inverse Cipher Last VX-form (vncipherlast VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VSBOX, 0xfc0007ff, 0x100005c8, 0xf800, // Vector AES SubBytes VX-form (vsbox VRT,VRA) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15}}, + {VSHASIGMAD, 0xfc0007ff, 0x100006c2, 0x0, // Vector SHA-512 Sigma Doubleword VX-form (vshasigmad VRT,VRA,ST,SIX) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_ImmUnsigned_16_16, ap_ImmUnsigned_17_20}}, + {VSHASIGMAW, 0xfc0007ff, 0x10000682, 0x0, // Vector SHA-256 Sigma Word VX-form (vshasigmaw VRT,VRA,ST,SIX) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_ImmUnsigned_16_16, ap_ImmUnsigned_17_20}}, + {VPMSUMB, 0xfc0007ff, 0x10000408, 0x0, // Vector Polynomial Multiply-Sum Byte VX-form (vpmsumb VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VPMSUMD, 0xfc0007ff, 0x100004c8, 0x0, // Vector Polynomial Multiply-Sum Doubleword VX-form (vpmsumd VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VPMSUMH, 0xfc0007ff, 0x10000448, 0x0, // Vector Polynomial Multiply-Sum Halfword VX-form (vpmsumh VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VPMSUMW, 0xfc0007ff, 0x10000488, 0x0, // Vector Polynomial Multiply-Sum Word VX-form (vpmsumw VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VPERMXOR, 0xfc00003f, 0x1000002d, 0x0, // Vector Permute and Exclusive-OR VA-form (vpermxor VRT,VRA,VRB,VRC) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}}, + {VGBBD, 0xfc0007ff, 0x1000050c, 0x1f0000, // Vector Gather Bits by Bytes by Doubleword VX-form (vgbbd VRT,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, + {VCLZB, 0xfc0007ff, 0x10000702, 0x1f0000, // Vector Count Leading Zeros Byte VX-form (vclzb VRT,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, + {VCLZH, 0xfc0007ff, 0x10000742, 0x1f0000, // Vector Count Leading Zeros Halfword VX-form (vclzh VRT,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, + {VCLZW, 0xfc0007ff, 0x10000782, 0x1f0000, // Vector Count Leading Zeros Word VX-form (vclzw VRT,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, + {VCLZD, 0xfc0007ff, 0x100007c2, 0x1f0000, // Vector Count Leading Zeros Doubleword (vclzd VRT,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, + {VPOPCNTB, 0xfc0007ff, 0x10000703, 0x1f0000, // Vector Population Count Byte (vpopcntb VRT,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, + {VPOPCNTD, 0xfc0007ff, 0x100007c3, 0x1f0000, // Vector Population Count Doubleword (vpopcntd VRT,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, + {VPOPCNTH, 0xfc0007ff, 0x10000743, 0x1f0000, // Vector Population Count Halfword (vpopcnth VRT,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, + {VPOPCNTW, 0xfc0007ff, 0x10000783, 0x1f0000, // Vector Population Count Word (vpopcntw VRT,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, + {VBPERMQ, 0xfc0007ff, 0x1000054c, 0x0, // Vector Bit Permute Quadword VX-form (vbpermq VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {BCDADDCC, 0xfc0005ff, 0x10000401, 0x0, // Decimal Add Modulo VX-form (bcdadd. VRT,VRA,VRB,PS) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_ImmUnsigned_22_22}}, + {BCDSUBCC, 0xfc0005ff, 0x10000441, 0x0, // Decimal Subtract Modulo VX-form (bcdsub. VRT,VRA,VRB,PS) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_ImmUnsigned_22_22}}, + {MTVSCR, 0xfc0007ff, 0x10000644, 0x3ff0000, // Move To Vector Status and Control Register VX-form (mtvscr VRB) + [5]*argField{ap_VecReg_16_20}}, + {MFVSCR, 0xfc0007ff, 0x10000604, 0x1ff800, // Move From Vector Status and Control Register VX-form (mfvscr VRT) + [5]*argField{ap_VecReg_6_10}}, + {DADD, 0xfc0007ff, 0xec000004, 0x0, // DFP Add [Quad] X-form (dadd FRT,FRA,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, + {DADDCC, 0xfc0007ff, 0xec000005, 0x0, // DFP Add [Quad] X-form (dadd. FRT,FRA,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, + {DSUB, 0xfc0007ff, 0xec000404, 0x0, // DFP Subtract [Quad] X-form (dsub FRT,FRA,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, + {DSUBCC, 0xfc0007ff, 0xec000405, 0x0, // DFP Subtract [Quad] X-form (dsub. FRT,FRA,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, + {DMUL, 0xfc0007ff, 0xec000044, 0x0, // DFP Multiply [Quad] X-form (dmul FRT,FRA,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, + {DMULCC, 0xfc0007ff, 0xec000045, 0x0, // DFP Multiply [Quad] X-form (dmul. FRT,FRA,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, + {DDIV, 0xfc0007ff, 0xec000444, 0x0, // DFP Divide [Quad] X-form (ddiv FRT,FRA,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, + {DDIVCC, 0xfc0007ff, 0xec000445, 0x0, // DFP Divide [Quad] X-form (ddiv. FRT,FRA,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, + {DCMPU, 0xfc0007fe, 0xec000504, 0x600001, // DFP Compare Unordered [Quad] X-form (dcmpu BF,FRA,FRB) + [5]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}}, + {DCMPO, 0xfc0007fe, 0xec000104, 0x600001, // DFP Compare Ordered [Quad] X-form (dcmpo BF,FRA,FRB) + [5]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}}, + {DTSTDC, 0xfc0003fe, 0xec000184, 0x600001, // DFP Test Data Class [Quad] Z22-form (dtstdc BF,FRA,DCM) + [5]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_ImmUnsigned_16_21}}, + {DTSTDG, 0xfc0003fe, 0xec0001c4, 0x600001, // DFP Test Data Group [Quad] Z22-form (dtstdg BF,FRA,DGM) + [5]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_ImmUnsigned_16_21}}, + {DTSTEX, 0xfc0007fe, 0xec000144, 0x600001, // DFP Test Exponent [Quad] X-form (dtstex BF,FRA,FRB) + [5]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}}, + {DTSTSF, 0xfc0007fe, 0xec000544, 0x600001, // DFP Test Significance [Quad] X-form (dtstsf BF,FRA,FRB) + [5]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}}, + {DQUAI, 0xfc0001ff, 0xec000086, 0x0, // DFP Quantize Immediate [Quad] Z23-form (dquai TE,FRT,FRB,RMC) + [5]*argField{ap_ImmSigned_11_15, ap_FPReg_6_10, ap_FPReg_16_20, ap_ImmUnsigned_21_22}}, + {DQUAICC, 0xfc0001ff, 0xec000087, 0x0, // DFP Quantize Immediate [Quad] Z23-form (dquai. TE,FRT,FRB,RMC) + [5]*argField{ap_ImmSigned_11_15, ap_FPReg_6_10, ap_FPReg_16_20, ap_ImmUnsigned_21_22}}, + {DQUA, 0xfc0001ff, 0xec000006, 0x0, // DFP Quantize [Quad] Z23-form (dqua FRT,FRA,FRB,RMC) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20, ap_ImmUnsigned_21_22}}, + {DQUACC, 0xfc0001ff, 0xec000007, 0x0, // DFP Quantize [Quad] Z23-form (dqua. FRT,FRA,FRB,RMC) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20, ap_ImmUnsigned_21_22}}, + {DRRND, 0xfc0001ff, 0xec000046, 0x0, // DFP Reround [Quad] Z23-form (drrnd FRT,FRA,FRB,RMC) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20, ap_ImmUnsigned_21_22}}, + {DRRNDCC, 0xfc0001ff, 0xec000047, 0x0, // DFP Reround [Quad] Z23-form (drrnd. FRT,FRA,FRB,RMC) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20, ap_ImmUnsigned_21_22}}, + {DRINTX, 0xfc0001ff, 0xec0000c6, 0x1e0000, // DFP Round To FP Integer With Inexact [Quad] Z23-form (drintx R,FRT,FRB,RMC) + [5]*argField{ap_ImmUnsigned_15_15, ap_FPReg_6_10, ap_FPReg_16_20, ap_ImmUnsigned_21_22}}, + {DRINTXCC, 0xfc0001ff, 0xec0000c7, 0x1e0000, // DFP Round To FP Integer With Inexact [Quad] Z23-form (drintx. R,FRT,FRB,RMC) + [5]*argField{ap_ImmUnsigned_15_15, ap_FPReg_6_10, ap_FPReg_16_20, ap_ImmUnsigned_21_22}}, + {DRINTN, 0xfc0001ff, 0xec0001c6, 0x1e0000, // DFP Round To FP Integer Without Inexact [Quad] Z23-form (drintn R,FRT,FRB,RMC) + [5]*argField{ap_ImmUnsigned_15_15, ap_FPReg_6_10, ap_FPReg_16_20, ap_ImmUnsigned_21_22}}, + {DRINTNCC, 0xfc0001ff, 0xec0001c7, 0x1e0000, // DFP Round To FP Integer Without Inexact [Quad] Z23-form (drintn. R,FRT,FRB,RMC) + [5]*argField{ap_ImmUnsigned_15_15, ap_FPReg_6_10, ap_FPReg_16_20, ap_ImmUnsigned_21_22}}, + {DCTDP, 0xfc0007ff, 0xec000204, 0x1f0000, // DFP Convert To DFP Long X-form (dctdp FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {DCTDPCC, 0xfc0007ff, 0xec000205, 0x1f0000, // DFP Convert To DFP Long X-form (dctdp. FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {DCTQPQ, 0xfc0007ff, 0xfc000204, 0x1f0000, // DFP Convert To DFP Extended X-form (dctqpq FRTp,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {DCTQPQCC, 0xfc0007ff, 0xfc000205, 0x1f0000, // DFP Convert To DFP Extended X-form (dctqpq. FRTp,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {DRSP, 0xfc0007ff, 0xec000604, 0x1f0000, // DFP Round To DFP Short X-form (drsp FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {DRSPCC, 0xfc0007ff, 0xec000605, 0x1f0000, // DFP Round To DFP Short X-form (drsp. FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {DRDPQ, 0xfc0007ff, 0xfc000604, 0x1f0000, // DFP Round To DFP Long X-form (drdpq FRTp,FRBp) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {DRDPQCC, 0xfc0007ff, 0xfc000605, 0x1f0000, // DFP Round To DFP Long X-form (drdpq. FRTp,FRBp) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {DCFFIX, 0xfc0007ff, 0xec000644, 0x1f0000, // DFP Convert From Fixed X-form (dcffix FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {DCFFIXCC, 0xfc0007ff, 0xec000645, 0x1f0000, // DFP Convert From Fixed X-form (dcffix. FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {DCFFIXQ, 0xfc0007ff, 0xfc000644, 0x1f0000, // DFP Convert From Fixed Quad X-form (dcffixq FRTp,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {DCFFIXQCC, 0xfc0007ff, 0xfc000645, 0x1f0000, // DFP Convert From Fixed Quad X-form (dcffixq. FRTp,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {DCTFIX, 0xfc0007ff, 0xec000244, 0x1f0000, // DFP Convert To Fixed [Quad] X-form (dctfix FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {DCTFIXCC, 0xfc0007ff, 0xec000245, 0x1f0000, // DFP Convert To Fixed [Quad] X-form (dctfix. FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {DDEDPD, 0xfc0007ff, 0xec000284, 0x70000, // DFP Decode DPD To BCD [Quad] X-form (ddedpd SP,FRT,FRB) + [5]*argField{ap_ImmUnsigned_11_12, ap_FPReg_6_10, ap_FPReg_16_20}}, + {DDEDPDCC, 0xfc0007ff, 0xec000285, 0x70000, // DFP Decode DPD To BCD [Quad] X-form (ddedpd. SP,FRT,FRB) + [5]*argField{ap_ImmUnsigned_11_12, ap_FPReg_6_10, ap_FPReg_16_20}}, + {DENBCD, 0xfc0007ff, 0xec000684, 0xf0000, // DFP Encode BCD To DPD [Quad] X-form (denbcd S,FRT,FRB) + [5]*argField{ap_ImmUnsigned_11_11, ap_FPReg_6_10, ap_FPReg_16_20}}, + {DENBCDCC, 0xfc0007ff, 0xec000685, 0xf0000, // DFP Encode BCD To DPD [Quad] X-form (denbcd. S,FRT,FRB) + [5]*argField{ap_ImmUnsigned_11_11, ap_FPReg_6_10, ap_FPReg_16_20}}, + {DXEX, 0xfc0007ff, 0xec0002c4, 0x1f0000, // DFP Extract Biased Exponent [Quad] X-form (dxex FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {DXEXCC, 0xfc0007ff, 0xec0002c5, 0x1f0000, // DFP Extract Biased Exponent [Quad] X-form (dxex. FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {DIEX, 0xfc0007ff, 0xec0006c4, 0x0, // DFP Insert Biased Exponent [Quad] X-form (diex FRT,FRA,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, + {DIEXCC, 0xfc0007ff, 0xec0006c5, 0x0, // DFP Insert Biased Exponent [Quad] X-form (diex. FRT,FRA,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, + {DSCLI, 0xfc0003ff, 0xec000084, 0x0, // DFP Shift Significand Left Immediate [Quad] Z22-form (dscli FRT,FRA,SH) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_ImmUnsigned_16_21}}, + {DSCLICC, 0xfc0003ff, 0xec000085, 0x0, // DFP Shift Significand Left Immediate [Quad] Z22-form (dscli. FRT,FRA,SH) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_ImmUnsigned_16_21}}, + {DSCRI, 0xfc0003ff, 0xec0000c4, 0x0, // DFP Shift Significand Right Immediate [Quad] Z22-form (dscri FRT,FRA,SH) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_ImmUnsigned_16_21}}, + {DSCRICC, 0xfc0003ff, 0xec0000c5, 0x0, // DFP Shift Significand Right Immediate [Quad] Z22-form (dscri. FRT,FRA,SH) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_ImmUnsigned_16_21}}, + {LXSDX, 0xfc0007fe, 0x7c000498, 0x0, // Load VSX Scalar Doubleword Indexed XX1-form (lxsdx XT,RA,RB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LXSIWAX, 0xfc0007fe, 0x7c000098, 0x0, // Load VSX Scalar as Integer Word Algebraic Indexed XX1-form (lxsiwax XT,RA,RB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LXSIWZX, 0xfc0007fe, 0x7c000018, 0x0, // Load VSX Scalar as Integer Word and Zero Indexed XX1-form (lxsiwzx XT,RA,RB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LXSSPX, 0xfc0007fe, 0x7c000418, 0x0, // Load VSX Scalar Single-Precision Indexed XX1-form (lxsspx XT,RA,RB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LXVD2X, 0xfc0007fe, 0x7c000698, 0x0, // Load VSX Vector Doubleword*2 Indexed XX1-form (lxvd2x XT,RA,RB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LXVDSX, 0xfc0007fe, 0x7c000298, 0x0, // Load VSX Vector Doubleword & Splat Indexed XX1-form (lxvdsx XT,RA,RB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LXVW4X, 0xfc0007fe, 0x7c000618, 0x0, // Load VSX Vector Word*4 Indexed XX1-form (lxvw4x XT,RA,RB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STXSDX, 0xfc0007fe, 0x7c000598, 0x0, // Store VSX Scalar Doubleword Indexed XX1-form (stxsdx XS,RA,RB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STXSIWX, 0xfc0007fe, 0x7c000118, 0x0, // Store VSX Scalar as Integer Word Indexed XX1-form (stxsiwx XS,RA,RB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STXSSPX, 0xfc0007fe, 0x7c000518, 0x0, // Store VSX Scalar Single-Precision Indexed XX1-form (stxsspx XS,RA,RB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STXVD2X, 0xfc0007fe, 0x7c000798, 0x0, // Store VSX Vector Doubleword*2 Indexed XX1-form (stxvd2x XS,RA,RB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STXVW4X, 0xfc0007fe, 0x7c000718, 0x0, // Store VSX Vector Word*4 Indexed XX1-form (stxvw4x XS,RA,RB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {XSABSDP, 0xfc0007fc, 0xf0000564, 0x1f0000, // VSX Scalar Absolute Value Double-Precision XX2-form (xsabsdp XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XSADDDP, 0xfc0007f8, 0xf0000100, 0x0, // VSX Scalar Add Double-Precision XX3-form (xsadddp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XSADDSP, 0xfc0007f8, 0xf0000000, 0x0, // VSX Scalar Add Single-Precision XX3-form (xsaddsp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XSCMPODP, 0xfc0007f8, 0xf0000158, 0x600001, // VSX Scalar Compare Ordered Double-Precision XX3-form (xscmpodp BF,XA,XB) + [5]*argField{ap_CondRegField_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XSCMPUDP, 0xfc0007f8, 0xf0000118, 0x600001, // VSX Scalar Compare Unordered Double-Precision XX3-form (xscmpudp BF,XA,XB) + [5]*argField{ap_CondRegField_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XSCPSGNDP, 0xfc0007f8, 0xf0000580, 0x0, // VSX Scalar Copy Sign Double-Precision XX3-form (xscpsgndp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XSCVDPSP, 0xfc0007fc, 0xf0000424, 0x1f0000, // VSX Scalar round Double-Precision to single-precision and Convert to Single-Precision format XX2-form (xscvdpsp XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XSCVDPSPN, 0xfc0007fc, 0xf000042c, 0x1f0000, // VSX Scalar Convert Scalar Single-Precision to Vector Single-Precision format Non-signalling XX2-form (xscvdpspn XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XSCVDPSXDS, 0xfc0007fc, 0xf0000560, 0x1f0000, // VSX Scalar truncate Double-Precision to integer and Convert to Signed Integer Doubleword format with Saturate XX2-form (xscvdpsxds XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XSCVDPSXWS, 0xfc0007fc, 0xf0000160, 0x1f0000, // VSX Scalar truncate Double-Precision to integer and Convert to Signed Integer Word format with Saturate XX2-form (xscvdpsxws XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XSCVDPUXDS, 0xfc0007fc, 0xf0000520, 0x1f0000, // VSX Scalar truncate Double-Precision integer and Convert to Unsigned Integer Doubleword format with Saturate XX2-form (xscvdpuxds XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XSCVDPUXWS, 0xfc0007fc, 0xf0000120, 0x1f0000, // VSX Scalar truncate Double-Precision to integer and Convert to Unsigned Integer Word format with Saturate XX2-form (xscvdpuxws XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XSCVSPDP, 0xfc0007fc, 0xf0000524, 0x1f0000, // VSX Scalar Convert Single-Precision to Double-Precision format XX2-form (xscvspdp XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XSCVSPDPN, 0xfc0007fc, 0xf000052c, 0x1f0000, // VSX Scalar Convert Single-Precision to Double-Precision format Non-signalling XX2-form (xscvspdpn XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XSCVSXDDP, 0xfc0007fc, 0xf00005e0, 0x1f0000, // VSX Scalar Convert Signed Integer Doubleword to floating-point format and round to Double-Precision format XX2-form (xscvsxddp XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XSCVSXDSP, 0xfc0007fc, 0xf00004e0, 0x1f0000, // VSX Scalar Convert Signed Integer Doubleword to floating-point format and round to Single-Precision XX2-form (xscvsxdsp XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XSCVUXDDP, 0xfc0007fc, 0xf00005a0, 0x1f0000, // VSX Scalar Convert Unsigned Integer Doubleword to floating-point format and round to Double-Precision format XX2-form (xscvuxddp XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XSCVUXDSP, 0xfc0007fc, 0xf00004a0, 0x1f0000, // VSX Scalar Convert Unsigned Integer Doubleword to floating-point format and round to Single-Precision XX2-form (xscvuxdsp XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XSDIVDP, 0xfc0007f8, 0xf00001c0, 0x0, // VSX Scalar Divide Double-Precision XX3-form (xsdivdp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XSDIVSP, 0xfc0007f8, 0xf00000c0, 0x0, // VSX Scalar Divide Single-Precision XX3-form (xsdivsp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XSMADDADP, 0xfc0007f8, 0xf0000108, 0x0, // VSX Scalar Multiply-Add Double-Precision XX3-form (xsmaddadp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XSMADDASP, 0xfc0007f8, 0xf0000008, 0x0, // VSX Scalar Multiply-Add Single-Precision XX3-form (xsmaddasp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XSMAXDP, 0xfc0007f8, 0xf0000500, 0x0, // VSX Scalar Maximum Double-Precision XX3-form (xsmaxdp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XSMINDP, 0xfc0007f8, 0xf0000540, 0x0, // VSX Scalar Minimum Double-Precision XX3-form (xsmindp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XSMSUBADP, 0xfc0007f8, 0xf0000188, 0x0, // VSX Scalar Multiply-Subtract Double-Precision XX3-form (xsmsubadp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XSMSUBASP, 0xfc0007f8, 0xf0000088, 0x0, // VSX Scalar Multiply-Subtract Single-Precision XX3-form (xsmsubasp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XSMULDP, 0xfc0007f8, 0xf0000180, 0x0, // VSX Scalar Multiply Double-Precision XX3-form (xsmuldp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XSMULSP, 0xfc0007f8, 0xf0000080, 0x0, // VSX Scalar Multiply Single-Precision XX3-form (xsmulsp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XSNABSDP, 0xfc0007fc, 0xf00005a4, 0x1f0000, // VSX Scalar Negative Absolute Value Double-Precision XX2-form (xsnabsdp XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XSNEGDP, 0xfc0007fc, 0xf00005e4, 0x1f0000, // VSX Scalar Negate Double-Precision XX2-form (xsnegdp XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XSNMADDADP, 0xfc0007f8, 0xf0000508, 0x0, // VSX Scalar Negative Multiply-Add Double-Precision XX3-form (xsnmaddadp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XSNMADDASP, 0xfc0007f8, 0xf0000408, 0x0, // VSX Scalar Negative Multiply-Add Single-Precision XX3-form (xsnmaddasp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XSNMSUBADP, 0xfc0007f8, 0xf0000588, 0x0, // VSX Scalar Negative Multiply-Subtract Double-Precision XX3-form (xsnmsubadp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XSNMSUBASP, 0xfc0007f8, 0xf0000488, 0x0, // VSX Scalar Negative Multiply-Subtract Single-Precision XX3-form (xsnmsubasp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XSRDPI, 0xfc0007fc, 0xf0000124, 0x1f0000, // VSX Scalar Round to Double-Precision Integer using round to Nearest Away XX2-form (xsrdpi XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XSRDPIC, 0xfc0007fc, 0xf00001ac, 0x1f0000, // VSX Scalar Round to Double-Precision Integer exact using Current rounding mode XX2-form (xsrdpic XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XSRDPIM, 0xfc0007fc, 0xf00001e4, 0x1f0000, // VSX Scalar Round to Double-Precision Integer using round toward -Infinity XX2-form (xsrdpim XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XSRDPIP, 0xfc0007fc, 0xf00001a4, 0x1f0000, // VSX Scalar Round to Double-Precision Integer using round toward +Infinity XX2-form (xsrdpip XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XSRDPIZ, 0xfc0007fc, 0xf0000164, 0x1f0000, // VSX Scalar Round to Double-Precision Integer using round toward Zero XX2-form (xsrdpiz XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XSREDP, 0xfc0007fc, 0xf0000168, 0x1f0000, // VSX Scalar Reciprocal Estimate Double-Precision XX2-form (xsredp XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XSRESP, 0xfc0007fc, 0xf0000068, 0x1f0000, // VSX Scalar Reciprocal Estimate Single-Precision XX2-form (xsresp XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XSRSP, 0xfc0007fc, 0xf0000464, 0x1f0000, // VSX Scalar Round to Single-Precision XX2-form (xsrsp XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XSRSQRTEDP, 0xfc0007fc, 0xf0000128, 0x1f0000, // VSX Scalar Reciprocal Square Root Estimate Double-Precision XX2-form (xsrsqrtedp XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XSRSQRTESP, 0xfc0007fc, 0xf0000028, 0x1f0000, // VSX Scalar Reciprocal Square Root Estimate Single-Precision XX2-form (xsrsqrtesp XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XSSQRTDP, 0xfc0007fc, 0xf000012c, 0x1f0000, // VSX Scalar Square Root Double-Precision XX2-form (xssqrtdp XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XSSQRTSP, 0xfc0007fc, 0xf000002c, 0x1f0000, // VSX Scalar Square Root Single-Precision XX-form (xssqrtsp XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XSSUBDP, 0xfc0007f8, 0xf0000140, 0x0, // VSX Scalar Subtract Double-Precision XX3-form (xssubdp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XSSUBSP, 0xfc0007f8, 0xf0000040, 0x0, // VSX Scalar Subtract Single-Precision XX3-form (xssubsp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XSTDIVDP, 0xfc0007f8, 0xf00001e8, 0x600001, // VSX Scalar Test for software Divide Double-Precision XX3-form (xstdivdp BF,XA,XB) + [5]*argField{ap_CondRegField_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XSTSQRTDP, 0xfc0007fc, 0xf00001a8, 0x7f0001, // VSX Scalar Test for software Square Root Double-Precision XX2-form (xstsqrtdp BF,XB) + [5]*argField{ap_CondRegField_6_8, ap_VecSReg_30_30_16_20}}, + {XVABSDP, 0xfc0007fc, 0xf0000764, 0x1f0000, // VSX Vector Absolute Value Double-Precision XX2-form (xvabsdp XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XVABSSP, 0xfc0007fc, 0xf0000664, 0x1f0000, // VSX Vector Absolute Value Single-Precision XX2-form (xvabssp XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XVADDDP, 0xfc0007f8, 0xf0000300, 0x0, // VSX Vector Add Double-Precision XX3-form (xvadddp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XVADDSP, 0xfc0007f8, 0xf0000200, 0x0, // VSX Vector Add Single-Precision XX3-form (xvaddsp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XVCMPEQDP, 0xfc0007f8, 0xf0000318, 0x0, // VSX Vector Compare Equal To Double-Precision [ & Record ] XX3-form (xvcmpeqdp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XVCMPEQDPCC, 0xfc0007f8, 0xf0000718, 0x0, // VSX Vector Compare Equal To Double-Precision [ & Record ] XX3-form (xvcmpeqdp. XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XVCMPEQSP, 0xfc0007f8, 0xf0000218, 0x0, // VSX Vector Compare Equal To Single-Precision [ & Record ] XX3-form (xvcmpeqsp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XVCMPEQSPCC, 0xfc0007f8, 0xf0000618, 0x0, // VSX Vector Compare Equal To Single-Precision [ & Record ] XX3-form (xvcmpeqsp. XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XVCMPGEDP, 0xfc0007f8, 0xf0000398, 0x0, // VSX Vector Compare Greater Than or Equal To Double-Precision [ & Record ] XX3-form (xvcmpgedp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XVCMPGEDPCC, 0xfc0007f8, 0xf0000798, 0x0, // VSX Vector Compare Greater Than or Equal To Double-Precision [ & Record ] XX3-form (xvcmpgedp. XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XVCMPGESP, 0xfc0007f8, 0xf0000298, 0x0, // VSX Vector Compare Greater Than or Equal To Single-Precision [ & record CR6 ] XX3-form (xvcmpgesp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XVCMPGESPCC, 0xfc0007f8, 0xf0000698, 0x0, // VSX Vector Compare Greater Than or Equal To Single-Precision [ & record CR6 ] XX3-form (xvcmpgesp. XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XVCMPGTDP, 0xfc0007f8, 0xf0000358, 0x0, // VSX Vector Compare Greater Than Double-Precision [ & record CR6 ] XX3-form (xvcmpgtdp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XVCMPGTDPCC, 0xfc0007f8, 0xf0000758, 0x0, // VSX Vector Compare Greater Than Double-Precision [ & record CR6 ] XX3-form (xvcmpgtdp. XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XVCMPGTSP, 0xfc0007f8, 0xf0000258, 0x0, // VSX Vector Compare Greater Than Single-Precision [ & record CR6 ] XX3-form (xvcmpgtsp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XVCMPGTSPCC, 0xfc0007f8, 0xf0000658, 0x0, // VSX Vector Compare Greater Than Single-Precision [ & record CR6 ] XX3-form (xvcmpgtsp. XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XVCPSGNDP, 0xfc0007f8, 0xf0000780, 0x0, // VSX Vector Copy Sign Double-Precision XX3-form (xvcpsgndp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XVCPSGNSP, 0xfc0007f8, 0xf0000680, 0x0, // VSX Vector Copy Sign Single-Precision XX3-form (xvcpsgnsp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XVCVDPSP, 0xfc0007fc, 0xf0000624, 0x1f0000, // VSX Vector round Double-Precision to single-precision and Convert to Single-Precision format XX2-form (xvcvdpsp XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XVCVDPSXDS, 0xfc0007fc, 0xf0000760, 0x1f0000, // VSX Vector truncate Double-Precision to integer and Convert to Signed Integer Doubleword format with Saturate XX2-form (xvcvdpsxds XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XVCVDPSXWS, 0xfc0007fc, 0xf0000360, 0x1f0000, // VSX Vector truncate Double-Precision to integer and Convert to Signed Integer Word format with Saturate XX2-form (xvcvdpsxws XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XVCVDPUXDS, 0xfc0007fc, 0xf0000720, 0x1f0000, // VSX Vector truncate Double-Precision to integer and Convert to Unsigned Integer Doubleword format with Saturate XX2-form (xvcvdpuxds XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XVCVDPUXWS, 0xfc0007fc, 0xf0000320, 0x1f0000, // VSX Vector truncate Double-Precision to integer and Convert to Unsigned Integer Word format with Saturate XX2-form (xvcvdpuxws XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XVCVSPDP, 0xfc0007fc, 0xf0000724, 0x1f0000, // VSX Vector Convert Single-Precision to Double-Precision format XX2-form (xvcvspdp XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XVCVSPSXDS, 0xfc0007fc, 0xf0000660, 0x1f0000, // VSX Vector truncate Single-Precision to integer and Convert to Signed Integer Doubleword format with Saturate XX2-form (xvcvspsxds XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XVCVSPSXWS, 0xfc0007fc, 0xf0000260, 0x1f0000, // VSX Vector truncate Single-Precision to integer and Convert to Signed Integer Word format with Saturate XX2-form (xvcvspsxws XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XVCVSPUXDS, 0xfc0007fc, 0xf0000620, 0x1f0000, // VSX Vector truncate Single-Precision to integer and Convert to Unsigned Integer Doubleword format with Saturate XX2-form (xvcvspuxds XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XVCVSPUXWS, 0xfc0007fc, 0xf0000220, 0x1f0000, // VSX Vector truncate Single-Precision to integer and Convert to Unsigned Integer Word format with Saturate XX2-form (xvcvspuxws XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XVCVSXDDP, 0xfc0007fc, 0xf00007e0, 0x1f0000, // VSX Vector Convert and round Signed Integer Doubleword to Double-Precision format XX2-form (xvcvsxddp XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XVCVSXDSP, 0xfc0007fc, 0xf00006e0, 0x1f0000, // VSX Vector Convert and round Signed Integer Doubleword to Single-Precision format XX2-form (xvcvsxdsp XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XVCVSXWDP, 0xfc0007fc, 0xf00003e0, 0x1f0000, // VSX Vector Convert Signed Integer Word to Double-Precision format XX2-form (xvcvsxwdp XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XVCVSXWSP, 0xfc0007fc, 0xf00002e0, 0x1f0000, // VSX Vector Convert and round Signed Integer Word to Single-Precision format XX2-form (xvcvsxwsp XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XVCVUXDDP, 0xfc0007fc, 0xf00007a0, 0x1f0000, // VSX Vector Convert and round Unsigned Integer Doubleword to Double-Precision format XX2-form (xvcvuxddp XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XVCVUXDSP, 0xfc0007fc, 0xf00006a0, 0x1f0000, // VSX Vector Convert and round Unsigned Integer Doubleword to Single-Precision format XX2-form (xvcvuxdsp XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XVCVUXWDP, 0xfc0007fc, 0xf00003a0, 0x1f0000, // VSX Vector Convert and round Unsigned Integer Word to Double-Precision format XX2-form (xvcvuxwdp XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XVCVUXWSP, 0xfc0007fc, 0xf00002a0, 0x1f0000, // VSX Vector Convert and round Unsigned Integer Word to Single-Precision format XX2-form (xvcvuxwsp XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XVDIVDP, 0xfc0007f8, 0xf00003c0, 0x0, // VSX Vector Divide Double-Precision XX3-form (xvdivdp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XVDIVSP, 0xfc0007f8, 0xf00002c0, 0x0, // VSX Vector Divide Single-Precision XX3-form (xvdivsp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XVMADDADP, 0xfc0007f8, 0xf0000308, 0x0, // VSX Vector Multiply-Add Double-Precision XX3-form (xvmaddadp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XVMADDASP, 0xfc0007f8, 0xf0000208, 0x0, // VSX Vector Multiply-Add Single-Precision XX3-form (xvmaddasp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XVMAXDP, 0xfc0007f8, 0xf0000700, 0x0, // VSX Vector Maximum Double-Precision XX3-form (xvmaxdp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XVMAXSP, 0xfc0007f8, 0xf0000600, 0x0, // VSX Vector Maximum Single-Precision XX3-form (xvmaxsp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XVMINDP, 0xfc0007f8, 0xf0000740, 0x0, // VSX Vector Minimum Double-Precision XX3-form (xvmindp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XVMINSP, 0xfc0007f8, 0xf0000640, 0x0, // VSX Vector Minimum Single-Precision XX3-form (xvminsp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XVMSUBADP, 0xfc0007f8, 0xf0000388, 0x0, // VSX Vector Multiply-Subtract Double-Precision XX3-form (xvmsubadp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XVMSUBASP, 0xfc0007f8, 0xf0000288, 0x0, // VSX Vector Multiply-Subtract Single-Precision XX3-form (xvmsubasp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XVMULDP, 0xfc0007f8, 0xf0000380, 0x0, // VSX Vector Multiply Double-Precision XX3-form (xvmuldp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XVMULSP, 0xfc0007f8, 0xf0000280, 0x0, // VSX Vector Multiply Single-Precision XX3-form (xvmulsp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XVNABSDP, 0xfc0007fc, 0xf00007a4, 0x1f0000, // VSX Vector Negative Absolute Value Double-Precision XX2-form (xvnabsdp XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XVNABSSP, 0xfc0007fc, 0xf00006a4, 0x1f0000, // VSX Vector Negative Absolute Value Single-Precision XX2-form (xvnabssp XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XVNEGDP, 0xfc0007fc, 0xf00007e4, 0x1f0000, // VSX Vector Negate Double-Precision XX2-form (xvnegdp XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XVNEGSP, 0xfc0007fc, 0xf00006e4, 0x1f0000, // VSX Vector Negate Single-Precision XX2-form (xvnegsp XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XVNMADDADP, 0xfc0007f8, 0xf0000708, 0x0, // VSX Vector Negative Multiply-Add Double-Precision XX3-form (xvnmaddadp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XVNMADDASP, 0xfc0007f8, 0xf0000608, 0x0, // VSX Vector Negative Multiply-Add Single-Precision XX3-form (xvnmaddasp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XVNMSUBADP, 0xfc0007f8, 0xf0000788, 0x0, // VSX Vector Negative Multiply-Subtract Double-Precision XX3-form (xvnmsubadp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XVNMSUBASP, 0xfc0007f8, 0xf0000688, 0x0, // VSX Vector Negative Multiply-Subtract Single-Precision XX3-form (xvnmsubasp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XVRDPI, 0xfc0007fc, 0xf0000324, 0x1f0000, // VSX Vector Round to Double-Precision Integer using round to Nearest Away XX2-form (xvrdpi XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XVRDPIC, 0xfc0007fc, 0xf00003ac, 0x1f0000, // VSX Vector Round to Double-Precision Integer Exact using Current rounding mode XX2-form (xvrdpic XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XVRDPIM, 0xfc0007fc, 0xf00003e4, 0x1f0000, // VSX Vector Round to Double-Precision Integer using round toward -Infinity XX2-form (xvrdpim XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XVRDPIP, 0xfc0007fc, 0xf00003a4, 0x1f0000, // VSX Vector Round to Double-Precision Integer using round toward +Infinity XX2-form (xvrdpip XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XVRDPIZ, 0xfc0007fc, 0xf0000364, 0x1f0000, // VSX Vector Round to Double-Precision Integer using round toward Zero XX2-form (xvrdpiz XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XVREDP, 0xfc0007fc, 0xf0000368, 0x1f0000, // VSX Vector Reciprocal Estimate Double-Precision XX2-form (xvredp XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XVRESP, 0xfc0007fc, 0xf0000268, 0x1f0000, // VSX Vector Reciprocal Estimate Single-Precision XX2-form (xvresp XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XVRSPI, 0xfc0007fc, 0xf0000224, 0x1f0000, // VSX Vector Round to Single-Precision Integer using round to Nearest Away XX2-form (xvrspi XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XVRSPIC, 0xfc0007fc, 0xf00002ac, 0x1f0000, // VSX Vector Round to Single-Precision Integer Exact using Current rounding mode XX2-form (xvrspic XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XVRSPIM, 0xfc0007fc, 0xf00002e4, 0x1f0000, // VSX Vector Round to Single-Precision Integer using round toward -Infinity XX2-form (xvrspim XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XVRSPIP, 0xfc0007fc, 0xf00002a4, 0x1f0000, // VSX Vector Round to Single-Precision Integer using round toward +Infinity XX2-form (xvrspip XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XVRSPIZ, 0xfc0007fc, 0xf0000264, 0x1f0000, // VSX Vector Round to Single-Precision Integer using round toward Zero XX2-form (xvrspiz XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XVRSQRTEDP, 0xfc0007fc, 0xf0000328, 0x1f0000, // VSX Vector Reciprocal Square Root Estimate Double-Precision XX2-form (xvrsqrtedp XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XVRSQRTESP, 0xfc0007fc, 0xf0000228, 0x1f0000, // VSX Vector Reciprocal Square Root Estimate Single-Precision XX2-form (xvrsqrtesp XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XVSQRTDP, 0xfc0007fc, 0xf000032c, 0x1f0000, // VSX Vector Square Root Double-Precision XX2-form (xvsqrtdp XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XVSQRTSP, 0xfc0007fc, 0xf000022c, 0x1f0000, // VSX Vector Square Root Single-Precision XX2-form (xvsqrtsp XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XVSUBDP, 0xfc0007f8, 0xf0000340, 0x0, // VSX Vector Subtract Double-Precision XX3-form (xvsubdp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XVSUBSP, 0xfc0007f8, 0xf0000240, 0x0, // VSX Vector Subtract Single-Precision XX3-form (xvsubsp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XVTDIVDP, 0xfc0007f8, 0xf00003e8, 0x600001, // VSX Vector Test for software Divide Double-Precision XX3-form (xvtdivdp BF,XA,XB) + [5]*argField{ap_CondRegField_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XVTDIVSP, 0xfc0007f8, 0xf00002e8, 0x600001, // VSX Vector Test for software Divide Single-Precision XX3-form (xvtdivsp BF,XA,XB) + [5]*argField{ap_CondRegField_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XVTSQRTDP, 0xfc0007fc, 0xf00003a8, 0x7f0001, // VSX Vector Test for software Square Root Double-Precision XX2-form (xvtsqrtdp BF,XB) + [5]*argField{ap_CondRegField_6_8, ap_VecSReg_30_30_16_20}}, + {XVTSQRTSP, 0xfc0007fc, 0xf00002a8, 0x7f0001, // VSX Vector Test for software Square Root Single-Precision XX2-form (xvtsqrtsp BF,XB) + [5]*argField{ap_CondRegField_6_8, ap_VecSReg_30_30_16_20}}, + {XXLAND, 0xfc0007f8, 0xf0000410, 0x0, // VSX Logical AND XX3-form (xxland XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XXLANDC, 0xfc0007f8, 0xf0000450, 0x0, // VSX Logical AND with Complement XX3-form (xxlandc XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XXLEQV, 0xfc0007f8, 0xf00005d0, 0x0, // VSX Logical Equivalence XX3-form (xxleqv XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XXLNAND, 0xfc0007f8, 0xf0000590, 0x0, // VSX Logical NAND XX3-form (xxlnand XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XXLORC, 0xfc0007f8, 0xf0000550, 0x0, // VSX Logical OR with Complement XX3-form (xxlorc XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XXLNOR, 0xfc0007f8, 0xf0000510, 0x0, // VSX Logical NOR XX3-form (xxlnor XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XXLOR, 0xfc0007f8, 0xf0000490, 0x0, // VSX Logical OR XX3-form (xxlor XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XXLXOR, 0xfc0007f8, 0xf00004d0, 0x0, // VSX Logical XOR XX3-form (xxlxor XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XXMRGHW, 0xfc0007f8, 0xf0000090, 0x0, // VSX Merge High Word XX3-form (xxmrghw XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XXMRGLW, 0xfc0007f8, 0xf0000190, 0x0, // VSX Merge Low Word XX3-form (xxmrglw XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XXPERMDI, 0xfc0004f8, 0xf0000050, 0x0, // VSX Permute Doubleword Immediate XX3-form (xxpermdi XT,XA,XB,DM) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20, ap_ImmUnsigned_22_23}}, + {XXSEL, 0xfc000030, 0xf0000030, 0x0, // VSX Select XX4-form (xxsel XT,XA,XB,XC) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20, ap_VecSReg_28_28_21_25}}, + {XXSLDWI, 0xfc0004f8, 0xf0000010, 0x0, // VSX Shift Left Double by Word Immediate XX3-form (xxsldwi XT,XA,XB,SHW) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20, ap_ImmUnsigned_22_23}}, + {XXSPLTW, 0xfc0007fc, 0xf0000290, 0x1c0000, // VSX Splat Word XX2-form (xxspltw XT,XB,UIM) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20, ap_ImmUnsigned_14_15}}, + {BRINC, 0xfc0007ff, 0x1000020f, 0x0, // Bit Reversed Increment EVX-form (brinc RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVABS, 0xfc0007ff, 0x10000208, 0xf800, // Vector Absolute Value EVX-form (evabs RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {EVADDIW, 0xfc0007ff, 0x10000202, 0x0, // Vector Add Immediate Word EVX-form (evaddiw RT,RB,UI) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20, ap_ImmUnsigned_11_15}}, + {EVADDSMIAAW, 0xfc0007ff, 0x100004c9, 0xf800, // Vector Add Signed, Modulo, Integer to Accumulator Word EVX-form (evaddsmiaaw RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {EVADDSSIAAW, 0xfc0007ff, 0x100004c1, 0xf800, // Vector Add Signed, Saturate, Integer to Accumulator Word EVX-form (evaddssiaaw RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {EVADDUMIAAW, 0xfc0007ff, 0x100004c8, 0xf800, // Vector Add Unsigned, Modulo, Integer to Accumulator Word EVX-form (evaddumiaaw RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {EVADDUSIAAW, 0xfc0007ff, 0x100004c0, 0xf800, // Vector Add Unsigned, Saturate, Integer to Accumulator Word EVX-form (evaddusiaaw RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {EVADDW, 0xfc0007ff, 0x10000200, 0x0, // Vector Add Word EVX-form (evaddw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVAND, 0xfc0007ff, 0x10000211, 0x0, // Vector AND EVX-form (evand RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVCMPEQ, 0xfc0007ff, 0x10000234, 0x600000, // Vector Compare Equal EVX-form (evcmpeq BF,RA,RB) + [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, + {EVANDC, 0xfc0007ff, 0x10000212, 0x0, // Vector AND with Complement EVX-form (evandc RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVCMPGTS, 0xfc0007ff, 0x10000231, 0x600000, // Vector Compare Greater Than Signed EVX-form (evcmpgts BF,RA,RB) + [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, + {EVCMPGTU, 0xfc0007ff, 0x10000230, 0x600000, // Vector Compare Greater Than Unsigned EVX-form (evcmpgtu BF,RA,RB) + [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, + {EVCMPLTU, 0xfc0007ff, 0x10000232, 0x600000, // Vector Compare Less Than Unsigned EVX-form (evcmpltu BF,RA,RB) + [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, + {EVCMPLTS, 0xfc0007ff, 0x10000233, 0x600000, // Vector Compare Less Than Signed EVX-form (evcmplts BF,RA,RB) + [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, + {EVCNTLSW, 0xfc0007ff, 0x1000020e, 0xf800, // Vector Count Leading Signed Bits Word EVX-form (evcntlsw RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {EVCNTLZW, 0xfc0007ff, 0x1000020d, 0xf800, // Vector Count Leading Zeros Word EVX-form (evcntlzw RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {EVDIVWS, 0xfc0007ff, 0x100004c6, 0x0, // Vector Divide Word Signed EVX-form (evdivws RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVDIVWU, 0xfc0007ff, 0x100004c7, 0x0, // Vector Divide Word Unsigned EVX-form (evdivwu RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVEQV, 0xfc0007ff, 0x10000219, 0x0, // Vector Equivalent EVX-form (eveqv RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVEXTSB, 0xfc0007ff, 0x1000020a, 0xf800, // Vector Extend Sign Byte EVX-form (evextsb RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {EVEXTSH, 0xfc0007ff, 0x1000020b, 0xf800, // Vector Extend Sign Halfword EVX-form (evextsh RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {EVLDD, 0xfc0007ff, 0x10000301, 0x0, // Vector Load Double Word into Double Word EVX-form (evldd RT,D(RA)) + [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}}, + {EVLDH, 0xfc0007ff, 0x10000305, 0x0, // Vector Load Double into Four Halfwords EVX-form (evldh RT,D(RA)) + [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}}, + {EVLDDX, 0xfc0007ff, 0x10000300, 0x0, // Vector Load Double Word into Double Word Indexed EVX-form (evlddx RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVLDHX, 0xfc0007ff, 0x10000304, 0x0, // Vector Load Double into Four Halfwords Indexed EVX-form (evldhx RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVLDW, 0xfc0007ff, 0x10000303, 0x0, // Vector Load Double into Two Words EVX-form (evldw RT,D(RA)) + [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}}, + {EVLHHESPLAT, 0xfc0007ff, 0x10000309, 0x0, // Vector Load Halfword into Halfwords Even and Splat EVX-form (evlhhesplat RT,D(RA)) + [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}}, + {EVLDWX, 0xfc0007ff, 0x10000302, 0x0, // Vector Load Double into Two Words Indexed EVX-form (evldwx RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVLHHESPLATX, 0xfc0007ff, 0x10000308, 0x0, // Vector Load Halfword into Halfwords Even and Splat Indexed EVX-form (evlhhesplatx RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVLHHOSSPLAT, 0xfc0007ff, 0x1000030f, 0x0, // Vector Load Halfword into Halfword Odd Signed and Splat EVX-form (evlhhossplat RT,D(RA)) + [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}}, + {EVLHHOUSPLAT, 0xfc0007ff, 0x1000030d, 0x0, // Vector Load Halfword into Halfword Odd Unsigned and Splat EVX-form (evlhhousplat RT,D(RA)) + [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}}, + {EVLHHOSSPLATX, 0xfc0007ff, 0x1000030e, 0x0, // Vector Load Halfword into Halfword Odd Signed and Splat Indexed EVX-form (evlhhossplatx RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVLHHOUSPLATX, 0xfc0007ff, 0x1000030c, 0x0, // Vector Load Halfword into Halfword Odd Unsigned and Splat Indexed EVX-form (evlhhousplatx RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVLWHE, 0xfc0007ff, 0x10000311, 0x0, // Vector Load Word into Two Halfwords Even EVX-form (evlwhe RT,D(RA)) + [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}}, + {EVLWHOS, 0xfc0007ff, 0x10000317, 0x0, // Vector Load Word into Two Halfwords Odd Signed (with sign extension) EVX-form (evlwhos RT,D(RA)) + [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}}, + {EVLWHEX, 0xfc0007ff, 0x10000310, 0x0, // Vector Load Word into Two Halfwords Even Indexed EVX-form (evlwhex RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVLWHOSX, 0xfc0007ff, 0x10000316, 0x0, // Vector Load Word into Two Halfwords Odd Signed Indexed (with sign extension) EVX-form (evlwhosx RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVLWHOU, 0xfc0007ff, 0x10000315, 0x0, // Vector Load Word into Two Halfwords Odd Unsigned (zero-extended) EVX-form (evlwhou RT,D(RA)) + [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}}, + {EVLWHSPLAT, 0xfc0007ff, 0x1000031d, 0x0, // Vector Load Word into Two Halfwords and Splat EVX-form (evlwhsplat RT,D(RA)) + [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}}, + {EVLWHOUX, 0xfc0007ff, 0x10000314, 0x0, // Vector Load Word into Two Halfwords Odd Unsigned Indexed (zero-extended) EVX-form (evlwhoux RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVLWHSPLATX, 0xfc0007ff, 0x1000031c, 0x0, // Vector Load Word into Two Halfwords and Splat Indexed EVX-form (evlwhsplatx RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVLWWSPLAT, 0xfc0007ff, 0x10000319, 0x0, // Vector Load Word into Word and Splat EVX-form (evlwwsplat RT,D(RA)) + [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}}, + {EVMERGEHI, 0xfc0007ff, 0x1000022c, 0x0, // Vector Merge High EVX-form (evmergehi RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVLWWSPLATX, 0xfc0007ff, 0x10000318, 0x0, // Vector Load Word into Word and Splat Indexed EVX-form (evlwwsplatx RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMERGELO, 0xfc0007ff, 0x1000022d, 0x0, // Vector Merge Low EVX-form (evmergelo RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMERGEHILO, 0xfc0007ff, 0x1000022e, 0x0, // Vector Merge High/Low EVX-form (evmergehilo RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHEGSMFAA, 0xfc0007ff, 0x1000052b, 0x0, // Vector Multiply Halfwords, Even, Guarded, Signed, Modulo, Fractional and Accumulate EVX-form (evmhegsmfaa RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMERGELOHI, 0xfc0007ff, 0x1000022f, 0x0, // Vector Merge Low/High EVX-form (evmergelohi RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHEGSMFAN, 0xfc0007ff, 0x100005ab, 0x0, // Vector Multiply Halfwords, Even, Guarded, Signed, Modulo, Fractional and Accumulate Negative EVX-form (evmhegsmfan RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHEGSMIAA, 0xfc0007ff, 0x10000529, 0x0, // Vector Multiply Halfwords, Even, Guarded, Signed, Modulo, Integer and Accumulate EVX-form (evmhegsmiaa RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHEGUMIAA, 0xfc0007ff, 0x10000528, 0x0, // Vector Multiply Halfwords, Even, Guarded, Unsigned, Modulo, Integer and Accumulate EVX-form (evmhegumiaa RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHEGSMIAN, 0xfc0007ff, 0x100005a9, 0x0, // Vector Multiply Halfwords, Even, Guarded, Signed, Modulo, Integer and Accumulate Negative EVX-form (evmhegsmian RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHEGUMIAN, 0xfc0007ff, 0x100005a8, 0x0, // Vector Multiply Halfwords, Even, Guarded, Unsigned, Modulo, Integer and Accumulate Negative EVX-form (evmhegumian RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHESMF, 0xfc0007ff, 0x1000040b, 0x0, // Vector Multiply Halfwords, Even, Signed, Modulo, Fractional EVX-form (evmhesmf RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHESMFAAW, 0xfc0007ff, 0x1000050b, 0x0, // Vector Multiply Halfwords, Even, Signed, Modulo, Fractional and Accumulate into Words EVX-form (evmhesmfaaw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHESMFA, 0xfc0007ff, 0x1000042b, 0x0, // Vector Multiply Halfwords, Even, Signed, Modulo, Fractional to Accumulator EVX-form (evmhesmfa RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHESMFANW, 0xfc0007ff, 0x1000058b, 0x0, // Vector Multiply Halfwords, Even, Signed, Modulo, Fractional and Accumulate Negative into Words EVX-form (evmhesmfanw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHESMI, 0xfc0007ff, 0x10000409, 0x0, // Vector Multiply Halfwords, Even, Signed, Modulo, Integer EVX-form (evmhesmi RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHESMIAAW, 0xfc0007ff, 0x10000509, 0x0, // Vector Multiply Halfwords, Even, Signed, Modulo, Integer and Accumulate into Words EVX-form (evmhesmiaaw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHESMIA, 0xfc0007ff, 0x10000429, 0x0, // Vector Multiply Halfwords, Even, Signed, Modulo, Integer to Accumulator EVX-form (evmhesmia RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHESMIANW, 0xfc0007ff, 0x10000589, 0x0, // Vector Multiply Halfwords, Even, Signed, Modulo, Integer and Accumulate Negative into Words EVX-form (evmhesmianw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHESSF, 0xfc0007ff, 0x10000403, 0x0, // Vector Multiply Halfwords, Even, Signed, Saturate, Fractional EVX-form (evmhessf RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHESSFA, 0xfc0007ff, 0x10000423, 0x0, // Vector Multiply Halfwords, Even, Signed, Saturate, Fractional to Accumulator EVX-form (evmhessfa RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHESSFAAW, 0xfc0007ff, 0x10000503, 0x0, // Vector Multiply Halfwords, Even, Signed, Saturate, Fractional and Accumulate into Words EVX-form (evmhessfaaw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHESSFANW, 0xfc0007ff, 0x10000583, 0x0, // Vector Multiply Halfwords, Even, Signed, Saturate, Fractional and Accumulate Negative into Words EVX-form (evmhessfanw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHESSIAAW, 0xfc0007ff, 0x10000501, 0x0, // Vector Multiply Halfwords, Even, Signed, Saturate, Integer and Accumulate into Words EVX-form (evmhessiaaw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHESSIANW, 0xfc0007ff, 0x10000581, 0x0, // Vector Multiply Halfwords, Even, Signed, Saturate, Integer and Accumulate Negative into Words EVX-form (evmhessianw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHEUMI, 0xfc0007ff, 0x10000408, 0x0, // Vector Multiply Halfwords, Even, Unsigned, Modulo, Integer EVX-form (evmheumi RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHEUMIAAW, 0xfc0007ff, 0x10000508, 0x0, // Vector Multiply Halfwords, Even, Unsigned, Modulo, Integer and Accumulate into Words EVX-form (evmheumiaaw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHEUMIA, 0xfc0007ff, 0x10000428, 0x0, // Vector Multiply Halfwords, Even, Unsigned, Modulo, Integer to Accumulator EVX-form (evmheumia RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHEUMIANW, 0xfc0007ff, 0x10000588, 0x0, // Vector Multiply Halfwords, Even, Unsigned, Modulo, Integer and Accumulate Negative into Words EVX-form (evmheumianw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHEUSIAAW, 0xfc0007ff, 0x10000500, 0x0, // Vector Multiply Halfwords, Even, Unsigned, Saturate, Integer and Accumulate into Words EVX-form (evmheusiaaw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHEUSIANW, 0xfc0007ff, 0x10000580, 0x0, // Vector Multiply Halfwords, Even, Unsigned, Saturate, Integer and Accumulate Negative into Words EVX-form (evmheusianw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHOGSMFAA, 0xfc0007ff, 0x1000052f, 0x0, // Vector Multiply Halfwords, Odd, Guarded, Signed, Modulo, Fractional and Accumulate EVX-form (evmhogsmfaa RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHOGSMIAA, 0xfc0007ff, 0x1000052d, 0x0, // Vector Multiply Halfwords, Odd, Guarded, Signed, Modulo, Integer and Accumulate EVX-form (evmhogsmiaa RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHOGSMFAN, 0xfc0007ff, 0x100005af, 0x0, // Vector Multiply Halfwords, Odd, Guarded, Signed, Modulo, Fractional and Accumulate Negative EVX-form (evmhogsmfan RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHOGSMIAN, 0xfc0007ff, 0x100005ad, 0x0, // Vector Multiply Halfwords, Odd, Guarded, Signed, Modulo, Integer and Accumulate Negative EVX-form (evmhogsmian RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHOGUMIAA, 0xfc0007ff, 0x1000052c, 0x0, // Vector Multiply Halfwords, Odd, Guarded, Unsigned, Modulo, Integer and Accumulate EVX-form (evmhogumiaa RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHOSMF, 0xfc0007ff, 0x1000040f, 0x0, // Vector Multiply Halfwords, Odd, Signed, Modulo, Fractional EVX-form (evmhosmf RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHOGUMIAN, 0xfc0007ff, 0x100005ac, 0x0, // Vector Multiply Halfwords, Odd, Guarded, Unsigned, Modulo, Integer and Accumulate Negative EVX-form (evmhogumian RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHOSMFA, 0xfc0007ff, 0x1000042f, 0x0, // Vector Multiply Halfwords, Odd, Signed, Modulo, Fractional to Accumulator EVX-form (evmhosmfa RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHOSMFAAW, 0xfc0007ff, 0x1000050f, 0x0, // Vector Multiply Halfwords, Odd, Signed, Modulo, Fractional and Accumulate into Words EVX-form (evmhosmfaaw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHOSMI, 0xfc0007ff, 0x1000040d, 0x0, // Vector Multiply Halfwords, Odd, Signed, Modulo, Integer EVX-form (evmhosmi RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHOSMFANW, 0xfc0007ff, 0x1000058f, 0x0, // Vector Multiply Halfwords, Odd, Signed, Modulo, Fractional and Accumulate Negative into Words EVX-form (evmhosmfanw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHOSMIA, 0xfc0007ff, 0x1000042d, 0x0, // Vector Multiply Halfwords, Odd, Signed, Modulo, Integer to Accumulator EVX-form (evmhosmia RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHOSMIAAW, 0xfc0007ff, 0x1000050d, 0x0, // Vector Multiply Halfwords, Odd, Signed, Modulo, Integer and Accumulate into Words EVX-form (evmhosmiaaw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHOSMIANW, 0xfc0007ff, 0x1000058d, 0x0, // Vector Multiply Halfwords, Odd, Signed, Modulo, Integer and Accumulate Negative into Words EVX-form (evmhosmianw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHOSSF, 0xfc0007ff, 0x10000407, 0x0, // Vector Multiply Halfwords, Odd, Signed, Saturate, Fractional EVX-form (evmhossf RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHOSSFA, 0xfc0007ff, 0x10000427, 0x0, // Vector Multiply Halfwords, Odd, Signed, Saturate, Fractional to Accumulator EVX-form (evmhossfa RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHOSSFAAW, 0xfc0007ff, 0x10000507, 0x0, // Vector Multiply Halfwords, Odd, Signed, Saturate, Fractional and Accumulate into Words EVX-form (evmhossfaaw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHOSSFANW, 0xfc0007ff, 0x10000587, 0x0, // Vector Multiply Halfwords, Odd, Signed, Saturate, Fractional and Accumulate Negative into Words EVX-form (evmhossfanw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHOSSIAAW, 0xfc0007ff, 0x10000505, 0x0, // Vector Multiply Halfwords, Odd, Signed, Saturate, Integer and Accumulate into Words EVX-form (evmhossiaaw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHOUMI, 0xfc0007ff, 0x1000040c, 0x0, // Vector Multiply Halfwords, Odd, Unsigned, Modulo, Integer EVX-form (evmhoumi RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHOSSIANW, 0xfc0007ff, 0x10000585, 0x0, // Vector Multiply Halfwords, Odd, Signed, Saturate, Integer and Accumulate Negative into Words EVX-form (evmhossianw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHOUMIA, 0xfc0007ff, 0x1000042c, 0x0, // Vector Multiply Halfwords, Odd, Unsigned, Modulo, Integer to Accumulator EVX-form (evmhoumia RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHOUMIAAW, 0xfc0007ff, 0x1000050c, 0x0, // Vector Multiply Halfwords, Odd, Unsigned, Modulo, Integer and Accumulate into Words EVX-form (evmhoumiaaw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHOUSIAAW, 0xfc0007ff, 0x10000504, 0x0, // Vector Multiply Halfwords, Odd, Unsigned, Saturate, Integer and Accumulate into Words EVX-form (evmhousiaaw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHOUMIANW, 0xfc0007ff, 0x1000058c, 0x0, // Vector Multiply Halfwords, Odd, Unsigned, Modulo, Integer and Accumulate Negative into Words EVX-form (evmhoumianw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHOUSIANW, 0xfc0007ff, 0x10000584, 0x0, // Vector Multiply Halfwords, Odd, Unsigned, Saturate, Integer and Accumulate Negative into Words EVX-form (evmhousianw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMRA, 0xfc0007ff, 0x100004c4, 0xf800, // Initialize Accumulator EVX-form (evmra RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {EVMWHSMF, 0xfc0007ff, 0x1000044f, 0x0, // Vector Multiply Word High Signed, Modulo, Fractional EVX-form (evmwhsmf RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMWHSMI, 0xfc0007ff, 0x1000044d, 0x0, // Vector Multiply Word High Signed, Modulo, Integer EVX-form (evmwhsmi RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMWHSMFA, 0xfc0007ff, 0x1000046f, 0x0, // Vector Multiply Word High Signed, Modulo, Fractional to Accumulator EVX-form (evmwhsmfa RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMWHSMIA, 0xfc0007ff, 0x1000046d, 0x0, // Vector Multiply Word High Signed, Modulo, Integer to Accumulator EVX-form (evmwhsmia RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMWHSSF, 0xfc0007ff, 0x10000447, 0x0, // Vector Multiply Word High Signed, Saturate, Fractional EVX-form (evmwhssf RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMWHUMI, 0xfc0007ff, 0x1000044c, 0x0, // Vector Multiply Word High Unsigned, Modulo, Integer EVX-form (evmwhumi RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMWHSSFA, 0xfc0007ff, 0x10000467, 0x0, // Vector Multiply Word High Signed, Saturate, Fractional to Accumulator EVX-form (evmwhssfa RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMWHUMIA, 0xfc0007ff, 0x1000046c, 0x0, // Vector Multiply Word High Unsigned, Modulo, Integer to Accumulator EVX-form (evmwhumia RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMWLSMIAAW, 0xfc0007ff, 0x10000549, 0x0, // Vector Multiply Word Low Signed, Modulo, Integer and Accumulate into Words EVX-form (evmwlsmiaaw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMWLSSIAAW, 0xfc0007ff, 0x10000541, 0x0, // Vector Multiply Word Low Signed, Saturate, Integer and Accumulate into Words EVX-form (evmwlssiaaw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMWLSMIANW, 0xfc0007ff, 0x100005c9, 0x0, // Vector Multiply Word Low Signed, Modulo, Integer and Accumulate Negative in Words EVX-form (evmwlsmianw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMWLSSIANW, 0xfc0007ff, 0x100005c1, 0x0, // Vector Multiply Word Low Signed, Saturate, Integer and Accumulate Negative in Words EVX-form (evmwlssianw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMWLUMI, 0xfc0007ff, 0x10000448, 0x0, // Vector Multiply Word Low Unsigned, Modulo, Integer EVX-form (evmwlumi RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMWLUMIAAW, 0xfc0007ff, 0x10000548, 0x0, // Vector Multiply Word Low Unsigned, Modulo, Integer and Accumulate into Words EVX-form (evmwlumiaaw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMWLUMIA, 0xfc0007ff, 0x10000468, 0x0, // Vector Multiply Word Low Unsigned, Modulo, Integer to Accumulator EVX-form (evmwlumia RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMWLUMIANW, 0xfc0007ff, 0x100005c8, 0x0, // Vector Multiply Word Low Unsigned, Modulo, Integer and Accumulate Negative in Words EVX-form (evmwlumianw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMWLUSIAAW, 0xfc0007ff, 0x10000540, 0x0, // Vector Multiply Word Low Unsigned, Saturate, Integer and Accumulate into Words EVX-form (evmwlusiaaw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMWSMF, 0xfc0007ff, 0x1000045b, 0x0, // Vector Multiply Word Signed, Modulo, Fractional EVX-form (evmwsmf RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMWLUSIANW, 0xfc0007ff, 0x100005c0, 0x0, // Vector Multiply Word Low Unsigned, Saturate, Integer and Accumulate Negative in Words EVX-form (evmwlusianw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMWSMFA, 0xfc0007ff, 0x1000047b, 0x0, // Vector Multiply Word Signed, Modulo, Fractional to Accumulator EVX-form (evmwsmfa RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMWSMFAA, 0xfc0007ff, 0x1000055b, 0x0, // Vector Multiply Word Signed, Modulo, Fractional and Accumulate EVX-form (evmwsmfaa RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMWSMI, 0xfc0007ff, 0x10000459, 0x0, // Vector Multiply Word Signed, Modulo, Integer EVX-form (evmwsmi RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMWSMIAA, 0xfc0007ff, 0x10000559, 0x0, // Vector Multiply Word Signed, Modulo, Integer and Accumulate EVX-form (evmwsmiaa RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMWSMFAN, 0xfc0007ff, 0x100005db, 0x0, // Vector Multiply Word Signed, Modulo, Fractional and Accumulate Negative EVX-form (evmwsmfan RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMWSMIA, 0xfc0007ff, 0x10000479, 0x0, // Vector Multiply Word Signed, Modulo, Integer to Accumulator EVX-form (evmwsmia RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMWSMIAN, 0xfc0007ff, 0x100005d9, 0x0, // Vector Multiply Word Signed, Modulo, Integer and Accumulate Negative EVX-form (evmwsmian RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMWSSF, 0xfc0007ff, 0x10000453, 0x0, // Vector Multiply Word Signed, Saturate, Fractional EVX-form (evmwssf RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMWSSFA, 0xfc0007ff, 0x10000473, 0x0, // Vector Multiply Word Signed, Saturate, Fractional to Accumulator EVX-form (evmwssfa RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMWSSFAA, 0xfc0007ff, 0x10000553, 0x0, // Vector Multiply Word Signed, Saturate, Fractional and Accumulate EVX-form (evmwssfaa RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMWUMI, 0xfc0007ff, 0x10000458, 0x0, // Vector Multiply Word Unsigned, Modulo, Integer EVX-form (evmwumi RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMWSSFAN, 0xfc0007ff, 0x100005d3, 0x0, // Vector Multiply Word Signed, Saturate, Fractional and Accumulate Negative EVX-form (evmwssfan RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMWUMIA, 0xfc0007ff, 0x10000478, 0x0, // Vector Multiply Word Unsigned, Modulo, Integer to Accumulator EVX-form (evmwumia RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMWUMIAA, 0xfc0007ff, 0x10000558, 0x0, // Vector Multiply Word Unsigned, Modulo, Integer and Accumulate EVX-form (evmwumiaa RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVNAND, 0xfc0007ff, 0x1000021e, 0x0, // Vector NAND EVX-form (evnand RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMWUMIAN, 0xfc0007ff, 0x100005d8, 0x0, // Vector Multiply Word Unsigned, Modulo, Integer and Accumulate Negative EVX-form (evmwumian RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVNEG, 0xfc0007ff, 0x10000209, 0xf800, // Vector Negate EVX-form (evneg RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {EVNOR, 0xfc0007ff, 0x10000218, 0x0, // Vector NOR EVX-form (evnor RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVORC, 0xfc0007ff, 0x1000021b, 0x0, // Vector OR with Complement EVX-form (evorc RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVOR, 0xfc0007ff, 0x10000217, 0x0, // Vector OR EVX-form (evor RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVRLW, 0xfc0007ff, 0x10000228, 0x0, // Vector Rotate Left Word EVX-form (evrlw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVRLWI, 0xfc0007ff, 0x1000022a, 0x0, // Vector Rotate Left Word Immediate EVX-form (evrlwi RT,RA,UI) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmUnsigned_16_20}}, + {EVSEL, 0xfc0007f8, 0x10000278, 0x0, // Vector Select EVS-form (evsel RT,RA,RB,BFA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_CondRegField_29_31}}, + {EVRNDW, 0xfc0007ff, 0x1000020c, 0xf800, // Vector Round Word EVX-form (evrndw RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {EVSLW, 0xfc0007ff, 0x10000224, 0x0, // Vector Shift Left Word EVX-form (evslw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVSPLATFI, 0xfc0007ff, 0x1000022b, 0xf800, // Vector Splat Fractional Immediate EVX-form (evsplatfi RT,SI) + [5]*argField{ap_Reg_6_10, ap_ImmSigned_11_15}}, + {EVSRWIS, 0xfc0007ff, 0x10000223, 0x0, // Vector Shift Right Word Immediate Signed EVX-form (evsrwis RT,RA,UI) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmUnsigned_16_20}}, + {EVSLWI, 0xfc0007ff, 0x10000226, 0x0, // Vector Shift Left Word Immediate EVX-form (evslwi RT,RA,UI) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmUnsigned_16_20}}, + {EVSPLATI, 0xfc0007ff, 0x10000229, 0xf800, // Vector Splat Immediate EVX-form (evsplati RT,SI) + [5]*argField{ap_Reg_6_10, ap_ImmSigned_11_15}}, + {EVSRWIU, 0xfc0007ff, 0x10000222, 0x0, // Vector Shift Right Word Immediate Unsigned EVX-form (evsrwiu RT,RA,UI) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmUnsigned_16_20}}, + {EVSRWS, 0xfc0007ff, 0x10000221, 0x0, // Vector Shift Right Word Signed EVX-form (evsrws RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVSTDD, 0xfc0007ff, 0x10000321, 0x0, // Vector Store Double of Double EVX-form (evstdd RS,D(RA)) + [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}}, + {EVSRWU, 0xfc0007ff, 0x10000220, 0x0, // Vector Shift Right Word Unsigned EVX-form (evsrwu RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVSTDDX, 0xfc0007ff, 0x10000320, 0x0, // Vector Store Double of Double Indexed EVX-form (evstddx RS,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVSTDH, 0xfc0007ff, 0x10000325, 0x0, // Vector Store Double of Four Halfwords EVX-form (evstdh RS,D(RA)) + [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}}, + {EVSTDW, 0xfc0007ff, 0x10000323, 0x0, // Vector Store Double of Two Words EVX-form (evstdw RS,D(RA)) + [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}}, + {EVSTDHX, 0xfc0007ff, 0x10000324, 0x0, // Vector Store Double of Four Halfwords Indexed EVX-form (evstdhx RS,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVSTDWX, 0xfc0007ff, 0x10000322, 0x0, // Vector Store Double of Two Words Indexed EVX-form (evstdwx RS,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVSTWHE, 0xfc0007ff, 0x10000331, 0x0, // Vector Store Word of Two Halfwords from Even EVX-form (evstwhe RS,D(RA)) + [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}}, + {EVSTWHO, 0xfc0007ff, 0x10000335, 0x0, // Vector Store Word of Two Halfwords from Odd EVX-form (evstwho RS,D(RA)) + [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}}, + {EVSTWWE, 0xfc0007ff, 0x10000339, 0x0, // Vector Store Word of Word from Even EVX-form (evstwwe RS,D(RA)) + [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}}, + {EVSTWHEX, 0xfc0007ff, 0x10000330, 0x0, // Vector Store Word of Two Halfwords from Even Indexed EVX-form (evstwhex RS,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVSTWHOX, 0xfc0007ff, 0x10000334, 0x0, // Vector Store Word of Two Halfwords from Odd Indexed EVX-form (evstwhox RS,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVSTWWEX, 0xfc0007ff, 0x10000338, 0x0, // Vector Store Word of Word from Even Indexed EVX-form (evstwwex RS,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVSTWWO, 0xfc0007ff, 0x1000033d, 0x0, // Vector Store Word of Word from Odd EVX-form (evstwwo RS,D(RA)) + [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}}, + {EVSUBFSMIAAW, 0xfc0007ff, 0x100004cb, 0xf800, // Vector Subtract Signed, Modulo, Integer to Accumulator Word EVX-form (evsubfsmiaaw RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {EVSTWWOX, 0xfc0007ff, 0x1000033c, 0x0, // Vector Store Word of Word from Odd Indexed EVX-form (evstwwox RS,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVSUBFSSIAAW, 0xfc0007ff, 0x100004c3, 0xf800, // Vector Subtract Signed, Saturate, Integer to Accumulator Word EVX-form (evsubfssiaaw RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {EVSUBFUMIAAW, 0xfc0007ff, 0x100004ca, 0xf800, // Vector Subtract Unsigned, Modulo, Integer to Accumulator Word EVX-form (evsubfumiaaw RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {EVSUBFUSIAAW, 0xfc0007ff, 0x100004c2, 0xf800, // Vector Subtract Unsigned, Saturate, Integer to Accumulator Word EVX-form (evsubfusiaaw RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {EVSUBFW, 0xfc0007ff, 0x10000204, 0x0, // Vector Subtract from Word EVX-form (evsubfw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVSUBIFW, 0xfc0007ff, 0x10000206, 0x0, // Vector Subtract Immediate from Word EVX-form (evsubifw RT,UI,RB) + [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_11_15, ap_Reg_16_20}}, + {EVXOR, 0xfc0007ff, 0x10000216, 0x0, // Vector XOR EVX-form (evxor RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVFSABS, 0xfc0007ff, 0x10000284, 0xf800, // Vector Floating-Point Single-Precision Absolute Value EVX-form (evfsabs RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {EVFSNABS, 0xfc0007ff, 0x10000285, 0xf800, // Vector Floating-Point Single-Precision Negative Absolute Value EVX-form (evfsnabs RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {EVFSNEG, 0xfc0007ff, 0x10000286, 0xf800, // Vector Floating-Point Single-Precision Negate EVX-form (evfsneg RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {EVFSADD, 0xfc0007ff, 0x10000280, 0x0, // Vector Floating-Point Single-Precision Add EVX-form (evfsadd RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVFSMUL, 0xfc0007ff, 0x10000288, 0x0, // Vector Floating-Point Single-Precision Multiply EVX-form (evfsmul RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVFSSUB, 0xfc0007ff, 0x10000281, 0x0, // Vector Floating-Point Single-Precision Subtract EVX-form (evfssub RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVFSDIV, 0xfc0007ff, 0x10000289, 0x0, // Vector Floating-Point Single-Precision Divide EVX-form (evfsdiv RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVFSCMPGT, 0xfc0007ff, 0x1000028c, 0x600000, // Vector Floating-Point Single-Precision Compare Greater Than EVX-form (evfscmpgt BF,RA,RB) + [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, + {EVFSCMPLT, 0xfc0007ff, 0x1000028d, 0x600000, // Vector Floating-Point Single-Precision Compare Less Than EVX-form (evfscmplt BF,RA,RB) + [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, + {EVFSCMPEQ, 0xfc0007ff, 0x1000028e, 0x600000, // Vector Floating-Point Single-Precision Compare Equal EVX-form (evfscmpeq BF,RA,RB) + [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, + {EVFSTSTGT, 0xfc0007ff, 0x1000029c, 0x600000, // Vector Floating-Point Single-Precision Test Greater Than EVX-form (evfststgt BF,RA,RB) + [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, + {EVFSTSTLT, 0xfc0007ff, 0x1000029d, 0x600000, // Vector Floating-Point Single-Precision Test Less Than EVX-form (evfststlt BF,RA,RB) + [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, + {EVFSTSTEQ, 0xfc0007ff, 0x1000029e, 0x600000, // Vector Floating-Point Single-Precision Test Equal EVX-form (evfststeq BF,RA,RB) + [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, + {EVFSCFSI, 0xfc0007ff, 0x10000291, 0x1f0000, // Vector Convert Floating-Point Single-Precision from Signed Integer EVX-form (evfscfsi RT,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {EVFSCFSF, 0xfc0007ff, 0x10000293, 0x1f0000, // Vector Convert Floating-Point Single-Precision from Signed Fraction EVX-form (evfscfsf RT,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {EVFSCFUI, 0xfc0007ff, 0x10000290, 0x1f0000, // Vector Convert Floating-Point Single-Precision from Unsigned Integer EVX-form (evfscfui RT,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {EVFSCFUF, 0xfc0007ff, 0x10000292, 0x1f0000, // Vector Convert Floating-Point Single-Precision from Unsigned Fraction EVX-form (evfscfuf RT,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {EVFSCTSI, 0xfc0007ff, 0x10000295, 0x1f0000, // Vector Convert Floating-Point Single-Precision to Signed Integer EVX-form (evfsctsi RT,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {EVFSCTUI, 0xfc0007ff, 0x10000294, 0x1f0000, // Vector Convert Floating-Point Single-Precision to Unsigned Integer EVX-form (evfsctui RT,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {EVFSCTSIZ, 0xfc0007ff, 0x1000029a, 0x1f0000, // Vector Convert Floating-Point Single-Precision to Signed Integer with Round toward Zero EVX-form (evfsctsiz RT,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {EVFSCTUIZ, 0xfc0007ff, 0x10000298, 0x1f0000, // Vector Convert Floating-Point Single-Precision to Unsigned Integer with Round toward Zero EVX-form (evfsctuiz RT,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {EVFSCTSF, 0xfc0007ff, 0x10000297, 0x1f0000, // Vector Convert Floating-Point Single-Precision to Signed Fraction EVX-form (evfsctsf RT,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {EVFSCTUF, 0xfc0007ff, 0x10000296, 0x1f0000, // Vector Convert Floating-Point Single-Precision to Unsigned Fraction EVX-form (evfsctuf RT,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {EFSABS, 0xfc0007ff, 0x100002c4, 0xf800, // Floating-Point Single-Precision Absolute Value EVX-form (efsabs RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {EFSNEG, 0xfc0007ff, 0x100002c6, 0xf800, // Floating-Point Single-Precision Negate EVX-form (efsneg RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {EFSNABS, 0xfc0007ff, 0x100002c5, 0xf800, // Floating-Point Single-Precision Negative Absolute Value EVX-form (efsnabs RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {EFSADD, 0xfc0007ff, 0x100002c0, 0x0, // Floating-Point Single-Precision Add EVX-form (efsadd RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EFSMUL, 0xfc0007ff, 0x100002c8, 0x0, // Floating-Point Single-Precision Multiply EVX-form (efsmul RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EFSSUB, 0xfc0007ff, 0x100002c1, 0x0, // Floating-Point Single-Precision Subtract EVX-form (efssub RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EFSDIV, 0xfc0007ff, 0x100002c9, 0x0, // Floating-Point Single-Precision Divide EVX-form (efsdiv RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EFSCMPGT, 0xfc0007ff, 0x100002cc, 0x600000, // Floating-Point Single-Precision Compare Greater Than EVX-form (efscmpgt BF,RA,RB) + [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, + {EFSCMPLT, 0xfc0007ff, 0x100002cd, 0x600000, // Floating-Point Single-Precision Compare Less Than EVX-form (efscmplt BF,RA,RB) + [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, + {EFSCMPEQ, 0xfc0007ff, 0x100002ce, 0x600000, // Floating-Point Single-Precision Compare Equal EVX-form (efscmpeq BF,RA,RB) + [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, + {EFSTSTGT, 0xfc0007ff, 0x100002dc, 0x600000, // Floating-Point Single-Precision Test Greater Than EVX-form (efststgt BF,RA,RB) + [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, + {EFSTSTLT, 0xfc0007ff, 0x100002dd, 0x600000, // Floating-Point Single-Precision Test Less Than EVX-form (efststlt BF,RA,RB) + [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, + {EFSTSTEQ, 0xfc0007ff, 0x100002de, 0x600000, // Floating-Point Single-Precision Test Equal EVX-form (efststeq BF,RA,RB) + [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, + {EFSCFSI, 0xfc0007ff, 0x100002d1, 0x1f0000, // Convert Floating-Point Single-Precision from Signed Integer EVX-form (efscfsi RT,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {EFSCFSF, 0xfc0007ff, 0x100002d3, 0x1f0000, // Convert Floating-Point Single-Precision from Signed Fraction EVX-form (efscfsf RT,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {EFSCTSI, 0xfc0007ff, 0x100002d5, 0x1f0000, // Convert Floating-Point Single-Precision to Signed Integer EVX-form (efsctsi RT,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {EFSCFUI, 0xfc0007ff, 0x100002d0, 0x1f0000, // Convert Floating-Point Single-Precision from Unsigned Integer EVX-form (efscfui RT,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {EFSCFUF, 0xfc0007ff, 0x100002d2, 0x1f0000, // Convert Floating-Point Single-Precision from Unsigned Fraction EVX-form (efscfuf RT,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {EFSCTUI, 0xfc0007ff, 0x100002d4, 0x1f0000, // Convert Floating-Point Single-Precision to Unsigned Integer EVX-form (efsctui RT,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {EFSCTSIZ, 0xfc0007ff, 0x100002da, 0x1f0000, // Convert Floating-Point Single-Precision to Signed Integer with Round toward Zero EVX-form (efsctsiz RT,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {EFSCTSF, 0xfc0007ff, 0x100002d7, 0x1f0000, // Convert Floating-Point Single-Precision to Signed Fraction EVX-form (efsctsf RT,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {EFSCTUIZ, 0xfc0007ff, 0x100002d8, 0x1f0000, // Convert Floating-Point Single-Precision to Unsigned Integer with Round toward Zero EVX-form (efsctuiz RT,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {EFSCTUF, 0xfc0007ff, 0x100002d6, 0x1f0000, // Convert Floating-Point Single-Precision to Unsigned Fraction EVX-form (efsctuf RT,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {EFDABS, 0xfc0007ff, 0x100002e4, 0xf800, // Floating-Point Double-Precision Absolute Value EVX-form (efdabs RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {EFDNEG, 0xfc0007ff, 0x100002e6, 0xf800, // Floating-Point Double-Precision Negate EVX-form (efdneg RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {EFDNABS, 0xfc0007ff, 0x100002e5, 0xf800, // Floating-Point Double-Precision Negative Absolute Value EVX-form (efdnabs RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {EFDADD, 0xfc0007ff, 0x100002e0, 0x0, // Floating-Point Double-Precision Add EVX-form (efdadd RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EFDMUL, 0xfc0007ff, 0x100002e8, 0x0, // Floating-Point Double-Precision Multiply EVX-form (efdmul RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EFDSUB, 0xfc0007ff, 0x100002e1, 0x0, // Floating-Point Double-Precision Subtract EVX-form (efdsub RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EFDDIV, 0xfc0007ff, 0x100002e9, 0x0, // Floating-Point Double-Precision Divide EVX-form (efddiv RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EFDCMPGT, 0xfc0007ff, 0x100002ec, 0x600000, // Floating-Point Double-Precision Compare Greater Than EVX-form (efdcmpgt BF,RA,RB) + [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, + {EFDCMPEQ, 0xfc0007ff, 0x100002ee, 0x600000, // Floating-Point Double-Precision Compare Equal EVX-form (efdcmpeq BF,RA,RB) + [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, + {EFDCMPLT, 0xfc0007ff, 0x100002ed, 0x600000, // Floating-Point Double-Precision Compare Less Than EVX-form (efdcmplt BF,RA,RB) + [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, + {EFDTSTGT, 0xfc0007ff, 0x100002fc, 0x600000, // Floating-Point Double-Precision Test Greater Than EVX-form (efdtstgt BF,RA,RB) + [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, + {EFDTSTLT, 0xfc0007ff, 0x100002fd, 0x600000, // Floating-Point Double-Precision Test Less Than EVX-form (efdtstlt BF,RA,RB) + [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, + {EFDCFSI, 0xfc0007ff, 0x100002f1, 0x1f0000, // Convert Floating-Point Double-Precision from Signed Integer EVX-form (efdcfsi RT,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {EFDTSTEQ, 0xfc0007ff, 0x100002fe, 0x600000, // Floating-Point Double-Precision Test Equal EVX-form (efdtsteq BF,RA,RB) + [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, + {EFDCFUI, 0xfc0007ff, 0x100002f0, 0x1f0000, // Convert Floating-Point Double-Precision from Unsigned Integer EVX-form (efdcfui RT,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {EFDCFSID, 0xfc0007ff, 0x100002e3, 0x1f0000, // Convert Floating-Point Double-Precision from Signed Integer Doubleword EVX-form (efdcfsid RT,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {EFDCFSF, 0xfc0007ff, 0x100002f3, 0x1f0000, // Convert Floating-Point Double-Precision from Signed Fraction EVX-form (efdcfsf RT,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {EFDCFUF, 0xfc0007ff, 0x100002f2, 0x1f0000, // Convert Floating-Point Double-Precision from Unsigned Fraction EVX-form (efdcfuf RT,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {EFDCFUID, 0xfc0007ff, 0x100002e2, 0x1f0000, // Convert Floating-Point Double-Precision from Unsigned Integer Doubleword EVX-form (efdcfuid RT,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {EFDCTSI, 0xfc0007ff, 0x100002f5, 0x1f0000, // Convert Floating-Point Double-Precision to Signed Integer EVX-form (efdctsi RT,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {EFDCTUI, 0xfc0007ff, 0x100002f4, 0x1f0000, // Convert Floating-Point Double-Precision to Unsigned Integer EVX-form (efdctui RT,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {EFDCTSIDZ, 0xfc0007ff, 0x100002eb, 0x1f0000, // Convert Floating-Point Double-Precision to Signed Integer Doubleword with Round toward Zero EVX-form (efdctsidz RT,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {EFDCTUIDZ, 0xfc0007ff, 0x100002ea, 0x1f0000, // Convert Floating-Point Double-Precision to Unsigned Integer Doubleword with Round toward Zero EVX-form (efdctuidz RT,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {EFDCTSIZ, 0xfc0007ff, 0x100002fa, 0x1f0000, // Convert Floating-Point Double-Precision to Signed Integer with Round toward Zero EVX-form (efdctsiz RT,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {EFDCTSF, 0xfc0007ff, 0x100002f7, 0x1f0000, // Convert Floating-Point Double-Precision to Signed Fraction EVX-form (efdctsf RT,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {EFDCTUF, 0xfc0007ff, 0x100002f6, 0x1f0000, // Convert Floating-Point Double-Precision to Unsigned Fraction EVX-form (efdctuf RT,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {EFDCTUIZ, 0xfc0007ff, 0x100002f8, 0x1f0000, // Convert Floating-Point Double-Precision to Unsigned Integer with Round toward Zero EVX-form (efdctuiz RT,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {EFDCFS, 0xfc0007ff, 0x100002ef, 0x1f0000, // Floating-Point Double-Precision Convert from Single-Precision EVX-form (efdcfs RT,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {EFSCFD, 0xfc0007ff, 0x100002cf, 0x1f0000, // Floating-Point Single-Precision Convert from Double-Precision EVX-form (efscfd RT,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {DLMZB, 0xfc0007ff, 0x7c00009c, 0x0, // Determine Leftmost Zero Byte X-form (dlmzb RA,RS,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, + {DLMZBCC, 0xfc0007ff, 0x7c00009d, 0x0, // Determine Leftmost Zero Byte X-form (dlmzb. RA,RS,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, + {MACCHW, 0xfc0007ff, 0x10000158, 0x0, // Multiply Accumulate Cross Halfword to Word Modulo Signed XO-form (macchw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACCHWCC, 0xfc0007ff, 0x10000159, 0x0, // Multiply Accumulate Cross Halfword to Word Modulo Signed XO-form (macchw. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACCHWO, 0xfc0007ff, 0x10000558, 0x0, // Multiply Accumulate Cross Halfword to Word Modulo Signed XO-form (macchwo RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACCHWOCC, 0xfc0007ff, 0x10000559, 0x0, // Multiply Accumulate Cross Halfword to Word Modulo Signed XO-form (macchwo. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACCHWS, 0xfc0007ff, 0x100001d8, 0x0, // Multiply Accumulate Cross Halfword to Word Saturate Signed XO-form (macchws RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACCHWSCC, 0xfc0007ff, 0x100001d9, 0x0, // Multiply Accumulate Cross Halfword to Word Saturate Signed XO-form (macchws. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACCHWSO, 0xfc0007ff, 0x100005d8, 0x0, // Multiply Accumulate Cross Halfword to Word Saturate Signed XO-form (macchwso RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACCHWSOCC, 0xfc0007ff, 0x100005d9, 0x0, // Multiply Accumulate Cross Halfword to Word Saturate Signed XO-form (macchwso. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACCHWU, 0xfc0007ff, 0x10000118, 0x0, // Multiply Accumulate Cross Halfword to Word Modulo Unsigned XO-form (macchwu RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACCHWUCC, 0xfc0007ff, 0x10000119, 0x0, // Multiply Accumulate Cross Halfword to Word Modulo Unsigned XO-form (macchwu. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACCHWUO, 0xfc0007ff, 0x10000518, 0x0, // Multiply Accumulate Cross Halfword to Word Modulo Unsigned XO-form (macchwuo RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACCHWUOCC, 0xfc0007ff, 0x10000519, 0x0, // Multiply Accumulate Cross Halfword to Word Modulo Unsigned XO-form (macchwuo. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACCHWSU, 0xfc0007ff, 0x10000198, 0x0, // Multiply Accumulate Cross Halfword to Word Saturate Unsigned XO-form (macchwsu RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACCHWSUCC, 0xfc0007ff, 0x10000199, 0x0, // Multiply Accumulate Cross Halfword to Word Saturate Unsigned XO-form (macchwsu. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACCHWSUO, 0xfc0007ff, 0x10000598, 0x0, // Multiply Accumulate Cross Halfword to Word Saturate Unsigned XO-form (macchwsuo RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACCHWSUOCC, 0xfc0007ff, 0x10000599, 0x0, // Multiply Accumulate Cross Halfword to Word Saturate Unsigned XO-form (macchwsuo. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACHHW, 0xfc0007ff, 0x10000058, 0x0, // Multiply Accumulate High Halfword to Word Modulo Signed XO-form (machhw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACHHWCC, 0xfc0007ff, 0x10000059, 0x0, // Multiply Accumulate High Halfword to Word Modulo Signed XO-form (machhw. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACHHWO, 0xfc0007ff, 0x10000458, 0x0, // Multiply Accumulate High Halfword to Word Modulo Signed XO-form (machhwo RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACHHWOCC, 0xfc0007ff, 0x10000459, 0x0, // Multiply Accumulate High Halfword to Word Modulo Signed XO-form (machhwo. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACHHWS, 0xfc0007ff, 0x100000d8, 0x0, // Multiply Accumulate High Halfword to Word Saturate Signed XO-form (machhws RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACHHWSCC, 0xfc0007ff, 0x100000d9, 0x0, // Multiply Accumulate High Halfword to Word Saturate Signed XO-form (machhws. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACHHWSO, 0xfc0007ff, 0x100004d8, 0x0, // Multiply Accumulate High Halfword to Word Saturate Signed XO-form (machhwso RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACHHWSOCC, 0xfc0007ff, 0x100004d9, 0x0, // Multiply Accumulate High Halfword to Word Saturate Signed XO-form (machhwso. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACHHWU, 0xfc0007ff, 0x10000018, 0x0, // Multiply Accumulate High Halfword to Word Modulo Unsigned XO-form (machhwu RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACHHWUCC, 0xfc0007ff, 0x10000019, 0x0, // Multiply Accumulate High Halfword to Word Modulo Unsigned XO-form (machhwu. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACHHWUO, 0xfc0007ff, 0x10000418, 0x0, // Multiply Accumulate High Halfword to Word Modulo Unsigned XO-form (machhwuo RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACHHWUOCC, 0xfc0007ff, 0x10000419, 0x0, // Multiply Accumulate High Halfword to Word Modulo Unsigned XO-form (machhwuo. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACHHWSU, 0xfc0007ff, 0x10000098, 0x0, // Multiply Accumulate High Halfword to Word Saturate Unsigned XO-form (machhwsu RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACHHWSUCC, 0xfc0007ff, 0x10000099, 0x0, // Multiply Accumulate High Halfword to Word Saturate Unsigned XO-form (machhwsu. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACHHWSUO, 0xfc0007ff, 0x10000498, 0x0, // Multiply Accumulate High Halfword to Word Saturate Unsigned XO-form (machhwsuo RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACHHWSUOCC, 0xfc0007ff, 0x10000499, 0x0, // Multiply Accumulate High Halfword to Word Saturate Unsigned XO-form (machhwsuo. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACLHW, 0xfc0007ff, 0x10000358, 0x0, // Multiply Accumulate Low Halfword to Word Modulo Signed XO-form (maclhw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACLHWCC, 0xfc0007ff, 0x10000359, 0x0, // Multiply Accumulate Low Halfword to Word Modulo Signed XO-form (maclhw. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACLHWO, 0xfc0007ff, 0x10000758, 0x0, // Multiply Accumulate Low Halfword to Word Modulo Signed XO-form (maclhwo RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACLHWOCC, 0xfc0007ff, 0x10000759, 0x0, // Multiply Accumulate Low Halfword to Word Modulo Signed XO-form (maclhwo. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACLHWS, 0xfc0007ff, 0x100003d8, 0x0, // Multiply Accumulate Low Halfword to Word Saturate Signed XO-form (maclhws RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACLHWSCC, 0xfc0007ff, 0x100003d9, 0x0, // Multiply Accumulate Low Halfword to Word Saturate Signed XO-form (maclhws. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACLHWSO, 0xfc0007ff, 0x100007d8, 0x0, // Multiply Accumulate Low Halfword to Word Saturate Signed XO-form (maclhwso RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACLHWSOCC, 0xfc0007ff, 0x100007d9, 0x0, // Multiply Accumulate Low Halfword to Word Saturate Signed XO-form (maclhwso. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACLHWU, 0xfc0007ff, 0x10000318, 0x0, // Multiply Accumulate Low Halfword to Word Modulo Unsigned XO-form (maclhwu RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACLHWUCC, 0xfc0007ff, 0x10000319, 0x0, // Multiply Accumulate Low Halfword to Word Modulo Unsigned XO-form (maclhwu. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACLHWUO, 0xfc0007ff, 0x10000718, 0x0, // Multiply Accumulate Low Halfword to Word Modulo Unsigned XO-form (maclhwuo RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACLHWUOCC, 0xfc0007ff, 0x10000719, 0x0, // Multiply Accumulate Low Halfword to Word Modulo Unsigned XO-form (maclhwuo. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MULCHW, 0xfc0007ff, 0x10000150, 0x0, // Multiply Cross Halfword to Word Signed X-form (mulchw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MULCHWCC, 0xfc0007ff, 0x10000151, 0x0, // Multiply Cross Halfword to Word Signed X-form (mulchw. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACLHWSU, 0xfc0007ff, 0x10000398, 0x0, // Multiply Accumulate Low Halfword to Word Saturate Unsigned XO-form (maclhwsu RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACLHWSUCC, 0xfc0007ff, 0x10000399, 0x0, // Multiply Accumulate Low Halfword to Word Saturate Unsigned XO-form (maclhwsu. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACLHWSUO, 0xfc0007ff, 0x10000798, 0x0, // Multiply Accumulate Low Halfword to Word Saturate Unsigned XO-form (maclhwsuo RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACLHWSUOCC, 0xfc0007ff, 0x10000799, 0x0, // Multiply Accumulate Low Halfword to Word Saturate Unsigned XO-form (maclhwsuo. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MULCHWU, 0xfc0007ff, 0x10000110, 0x0, // Multiply Cross Halfword to Word Unsigned X-form (mulchwu RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MULCHWUCC, 0xfc0007ff, 0x10000111, 0x0, // Multiply Cross Halfword to Word Unsigned X-form (mulchwu. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MULHHW, 0xfc0007ff, 0x10000050, 0x0, // Multiply High Halfword to Word Signed X-form (mulhhw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MULHHWCC, 0xfc0007ff, 0x10000051, 0x0, // Multiply High Halfword to Word Signed X-form (mulhhw. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MULLHW, 0xfc0007ff, 0x10000350, 0x0, // Multiply Low Halfword to Word Signed X-form (mullhw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MULLHWCC, 0xfc0007ff, 0x10000351, 0x0, // Multiply Low Halfword to Word Signed X-form (mullhw. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MULHHWU, 0xfc0007ff, 0x10000010, 0x0, // Multiply High Halfword to Word Unsigned X-form (mulhhwu RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MULHHWUCC, 0xfc0007ff, 0x10000011, 0x0, // Multiply High Halfword to Word Unsigned X-form (mulhhwu. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MULLHWU, 0xfc0007ff, 0x10000310, 0x0, // Multiply Low Halfword to Word Unsigned X-form (mullhwu RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MULLHWUCC, 0xfc0007ff, 0x10000311, 0x0, // Multiply Low Halfword to Word Unsigned X-form (mullhwu. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {NMACCHW, 0xfc0007ff, 0x1000015c, 0x0, // Negative Multiply Accumulate Cross Halfword to Word Modulo Signed XO-form (nmacchw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {NMACCHWCC, 0xfc0007ff, 0x1000015d, 0x0, // Negative Multiply Accumulate Cross Halfword to Word Modulo Signed XO-form (nmacchw. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {NMACCHWO, 0xfc0007ff, 0x1000055c, 0x0, // Negative Multiply Accumulate Cross Halfword to Word Modulo Signed XO-form (nmacchwo RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {NMACCHWOCC, 0xfc0007ff, 0x1000055d, 0x0, // Negative Multiply Accumulate Cross Halfword to Word Modulo Signed XO-form (nmacchwo. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {NMACCHWS, 0xfc0007ff, 0x100001dc, 0x0, // Negative Multiply Accumulate Cross Halfword to Word Saturate Signed XO-form (nmacchws RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {NMACCHWSCC, 0xfc0007ff, 0x100001dd, 0x0, // Negative Multiply Accumulate Cross Halfword to Word Saturate Signed XO-form (nmacchws. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {NMACCHWSO, 0xfc0007ff, 0x100005dc, 0x0, // Negative Multiply Accumulate Cross Halfword to Word Saturate Signed XO-form (nmacchwso RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {NMACCHWSOCC, 0xfc0007ff, 0x100005dd, 0x0, // Negative Multiply Accumulate Cross Halfword to Word Saturate Signed XO-form (nmacchwso. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {NMACHHW, 0xfc0007ff, 0x1000005c, 0x0, // Negative Multiply Accumulate High Halfword to Word Modulo Signed XO-form (nmachhw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {NMACHHWCC, 0xfc0007ff, 0x1000005d, 0x0, // Negative Multiply Accumulate High Halfword to Word Modulo Signed XO-form (nmachhw. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {NMACHHWO, 0xfc0007ff, 0x1000045c, 0x0, // Negative Multiply Accumulate High Halfword to Word Modulo Signed XO-form (nmachhwo RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {NMACHHWOCC, 0xfc0007ff, 0x1000045d, 0x0, // Negative Multiply Accumulate High Halfword to Word Modulo Signed XO-form (nmachhwo. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {NMACHHWS, 0xfc0007ff, 0x100000dc, 0x0, // Negative Multiply Accumulate High Halfword to Word Saturate Signed XO-form (nmachhws RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {NMACHHWSCC, 0xfc0007ff, 0x100000dd, 0x0, // Negative Multiply Accumulate High Halfword to Word Saturate Signed XO-form (nmachhws. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {NMACHHWSO, 0xfc0007ff, 0x100004dc, 0x0, // Negative Multiply Accumulate High Halfword to Word Saturate Signed XO-form (nmachhwso RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {NMACHHWSOCC, 0xfc0007ff, 0x100004dd, 0x0, // Negative Multiply Accumulate High Halfword to Word Saturate Signed XO-form (nmachhwso. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {NMACLHW, 0xfc0007ff, 0x1000035c, 0x0, // Negative Multiply Accumulate Low Halfword to Word Modulo Signed XO-form (nmaclhw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {NMACLHWCC, 0xfc0007ff, 0x1000035d, 0x0, // Negative Multiply Accumulate Low Halfword to Word Modulo Signed XO-form (nmaclhw. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {NMACLHWO, 0xfc0007ff, 0x1000075c, 0x0, // Negative Multiply Accumulate Low Halfword to Word Modulo Signed XO-form (nmaclhwo RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {NMACLHWOCC, 0xfc0007ff, 0x1000075d, 0x0, // Negative Multiply Accumulate Low Halfword to Word Modulo Signed XO-form (nmaclhwo. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {NMACLHWS, 0xfc0007ff, 0x100003dc, 0x0, // Negative Multiply Accumulate Low Halfword to Word Saturate Signed XO-form (nmaclhws RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {NMACLHWSCC, 0xfc0007ff, 0x100003dd, 0x0, // Negative Multiply Accumulate Low Halfword to Word Saturate Signed XO-form (nmaclhws. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {NMACLHWSO, 0xfc0007ff, 0x100007dc, 0x0, // Negative Multiply Accumulate Low Halfword to Word Saturate Signed XO-form (nmaclhwso RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {NMACLHWSOCC, 0xfc0007ff, 0x100007dd, 0x0, // Negative Multiply Accumulate Low Halfword to Word Saturate Signed XO-form (nmaclhwso. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {ICBI, 0xfc0007fe, 0x7c0007ac, 0x3e00001, // Instruction Cache Block Invalidate X-form (icbi RA,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_16_20}}, + {ICBT, 0xfc0007fe, 0x7c00002c, 0x2000001, // Instruction Cache Block Touch X-form (icbt CT, RA, RB) + [5]*argField{ap_ImmUnsigned_7_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DCBA, 0xfc0007fe, 0x7c0005ec, 0x3e00001, // Data Cache Block Allocate X-form (dcba RA,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_16_20}}, + {DCBT, 0xfc0007fe, 0x7c00022c, 0x1, // Data Cache Block Touch X-form (dcbt RA,RB,TH) + [5]*argField{ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_6_10}}, + {DCBT, 0xfc0007fe, 0x7c00022c, 0x1, // Data Cache Block Touch X-form (dcbt TH,RA,RB) + [5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DCBTST, 0xfc0007fe, 0x7c0001ec, 0x1, // Data Cache Block Touch for Store X-form (dcbtst RA,RB,TH) + [5]*argField{ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_6_10}}, + {DCBTST, 0xfc0007fe, 0x7c0001ec, 0x1, // Data Cache Block Touch for Store X-form (dcbtst TH,RA,RB) + [5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DCBZ, 0xfc0007fe, 0x7c0007ec, 0x3e00001, // Data Cache Block set to Zero X-form (dcbz RA,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_16_20}}, + {DCBST, 0xfc0007fe, 0x7c00006c, 0x3e00001, // Data Cache Block Store X-form (dcbst RA,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_16_20}}, + {DCBF, 0xfc0007fe, 0x7c0000ac, 0x3800001, // Data Cache Block Flush X-form (dcbf RA,RB,L) + [5]*argField{ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_9_10}}, + {ISYNC, 0xfc0007fe, 0x4c00012c, 0x3fff801, // Instruction Synchronize XL-form (isync) + [5]*argField{}}, + {LBARX, 0xfc0007ff, 0x7c000068, 0x0, // Load Byte And Reserve Indexed X-form [Category: Phased-In] (lbarx RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LBARX, 0xfc0007fe, 0x7c000068, 0x0, // Load Byte And Reserve Indexed X-form [Category: Phased-In] (lbarx RT,RA,RB,EH) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_31_31}}, + {LHARX, 0xfc0007ff, 0x7c0000e8, 0x0, // Load Halfword And Reserve Indexed X-form [Category: Phased-In] (lharx RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LHARX, 0xfc0007fe, 0x7c0000e8, 0x0, // Load Halfword And Reserve Indexed X-form [Category: Phased-In] (lharx RT,RA,RB,EH) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_31_31}}, + {LWARX, 0xfc0007ff, 0x7c000028, 0x0, // Load Word And Reserve Indexed X-form (lwarx RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LWARX, 0xfc0007ff, 0x7c000028, 0x0, // Load Word And Reserve Indexed X-form (lwarx RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LWARX, 0xfc0007fe, 0x7c000028, 0x0, // Load Word And Reserve Indexed X-form (lwarx RT,RA,RB,EH) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_31_31}}, + {STBCXCC, 0xfc0007ff, 0x7c00056d, 0x0, // Store Byte Conditional Indexed X-form [Category: Phased-In] (stbcx. RS,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STHCXCC, 0xfc0007ff, 0x7c0005ad, 0x0, // Store Halfword Conditional Indexed X-form [Category: Phased-In] (sthcx. RS,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STWCXCC, 0xfc0007ff, 0x7c00012d, 0x0, // Store Word Conditional Indexed X-form (stwcx. RS,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LDARX, 0xfc0007ff, 0x7c0000a8, 0x0, // Load Doubleword And Reserve Indexed X-form (ldarx RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LDARX, 0xfc0007fe, 0x7c0000a8, 0x0, // Load Doubleword And Reserve Indexed X-form (ldarx RT,RA,RB,EH) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_31_31}}, + {STDCXCC, 0xfc0007ff, 0x7c0001ad, 0x0, // Store Doubleword Conditional Indexed X-form (stdcx. RS,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LQARX, 0xfc0007ff, 0x7c000228, 0x0, // Load Quadword And Reserve Indexed X-form (lqarx RTp,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LQARX, 0xfc0007fe, 0x7c000228, 0x0, // Load Quadword And Reserve Indexed X-form (lqarx RTp,RA,RB,EH) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_31_31}}, + {STQCXCC, 0xfc0007ff, 0x7c00016d, 0x0, // Store Quadword Conditional Indexed X-form (stqcx. RSp,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {SYNC, 0xfc0007fe, 0x7c0004ac, 0x390f801, // Synchronize X-form (sync L, E) + [5]*argField{ap_ImmUnsigned_9_10, ap_ImmUnsigned_12_15}}, + {EIEIO, 0xfc0007fe, 0x7c0006ac, 0x3fff801, // Enforce In-order Execution of I/O X-form (eieio) + [5]*argField{}}, + {MBAR, 0xfc0007fe, 0x7c0006ac, 0x1ff801, // Memory Barrier X-form (mbar MO) + [5]*argField{ap_ImmUnsigned_6_10}}, + {WAIT, 0xfc0007fe, 0x7c00007c, 0x39ff801, // Wait X-form (wait WC) + [5]*argField{ap_ImmUnsigned_9_10}}, + {TBEGINCC, 0xfc0007ff, 0x7c00051d, 0x1dff800, // Transaction Begin X-form (tbegin. R) + [5]*argField{ap_ImmUnsigned_10_10}}, + {TENDCC, 0xfc0007ff, 0x7c00055d, 0x1fff800, // Transaction End X-form (tend. A) + [5]*argField{ap_ImmUnsigned_6_6}}, + {TABORTCC, 0xfc0007ff, 0x7c00071d, 0x3e0f800, // Transaction Abort X-form (tabort. RA) + [5]*argField{ap_Reg_11_15}}, + {TABORTWCCC, 0xfc0007ff, 0x7c00061d, 0x0, // Transaction Abort Word Conditional X-form (tabortwc. TO,RA,RB) + [5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {TABORTWCICC, 0xfc0007ff, 0x7c00069d, 0x0, // Transaction Abort Word Conditional Immediate X-form (tabortwci. TO,RA,SI) + [5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_ImmSigned_16_20}}, + {TABORTDCCC, 0xfc0007ff, 0x7c00065d, 0x0, // Transaction Abort Doubleword Conditional X-form (tabortdc. TO,RA,RB) + [5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {TABORTDCICC, 0xfc0007ff, 0x7c0006dd, 0x0, // Transaction Abort Doubleword Conditional Immediate X-form (tabortdci. TO,RA, SI) + [5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_ImmSigned_16_20}}, + {TSRCC, 0xfc0007ff, 0x7c0005dd, 0x3dff800, // Transaction Suspend or Resume X-form (tsr. L) + [5]*argField{ap_ImmUnsigned_10_10}}, + {TCHECK, 0xfc0007fe, 0x7c00059c, 0x7ff801, // Transaction Check X-form (tcheck BF) + [5]*argField{ap_CondRegField_6_8}}, + {MFTB, 0xfc0007fe, 0x7c0002e6, 0x1, // Move From Time Base XFX-form (mftb RT,TBR) + [5]*argField{ap_Reg_6_10, ap_SpReg_16_20_11_15}}, + {RFEBB, 0xfc0007fe, 0x4c000124, 0x3fff001, // Return from Event-Based Branch XL-form (rfebb S) + [5]*argField{ap_ImmUnsigned_20_20}}, + {LBDX, 0xfc0007fe, 0x7c000406, 0x1, // Load Byte with Decoration Indexed X-form (lbdx RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LHDX, 0xfc0007fe, 0x7c000446, 0x1, // Load Halfword with Decoration Indexed X-form (lhdx RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LWDX, 0xfc0007fe, 0x7c000486, 0x1, // Load Word with Decoration Indexed X-form (lwdx RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LDDX, 0xfc0007fe, 0x7c0004c6, 0x1, // Load Doubleword with Decoration Indexed X-form (lddx RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LFDDX, 0xfc0007fe, 0x7c000646, 0x1, // Load Floating Doubleword with Decoration Indexed X-form (lfddx FRT,RA,RB) + [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STBDX, 0xfc0007fe, 0x7c000506, 0x1, // Store Byte with Decoration Indexed X-form (stbdx RS,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STHDX, 0xfc0007fe, 0x7c000546, 0x1, // Store Halfword with Decoration Indexed X-form (sthdx RS,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STWDX, 0xfc0007fe, 0x7c000586, 0x1, // Store Word with Decoration Indexed X-form (stwdx RS,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STDDX, 0xfc0007fe, 0x7c0005c6, 0x1, // Store Doubleword with Decoration Indexed X-form (stddx RS,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STFDDX, 0xfc0007fe, 0x7c000746, 0x1, // Store Floating Doubleword with Decoration Indexed X-form (stfddx FRS,RA,RB) + [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DSN, 0xfc0007fe, 0x7c0003c6, 0x3e00001, // Decorated Storage Notify X-form (dsn RA,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_16_20}}, + {ECIWX, 0xfc0007fe, 0x7c00026c, 0x1, // External Control In Word Indexed X-form (eciwx RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {ECOWX, 0xfc0007fe, 0x7c00036c, 0x1, // External Control Out Word Indexed X-form (ecowx RS,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {SC, 0xfc000002, 0x44000002, 0x3fff01d, // System Call SC-form (sc LEV) + [5]*argField{ap_ImmUnsigned_20_26}}, + {RFID, 0xfc0007fe, 0x4c000024, 0x3fff801, // Return From Interrupt Doubleword XL-form (rfid) + [5]*argField{}}, + {HRFID, 0xfc0007fe, 0x4c000224, 0x3fff801, // Hypervisor Return From Interrupt Doubleword XL-form (hrfid) + [5]*argField{}}, + {DOZE, 0xfc0007fe, 0x4c000324, 0x3fff801, // Doze XL-form (doze) + [5]*argField{}}, + {NAP, 0xfc0007fe, 0x4c000364, 0x3fff801, // Nap XL-form (nap) + [5]*argField{}}, + {SLEEP, 0xfc0007fe, 0x4c0003a4, 0x3fff801, // Sleep XL-form (sleep) + [5]*argField{}}, + {RVWINKLE, 0xfc0007fe, 0x4c0003e4, 0x3fff801, // Rip Van Winkle XL-form (rvwinkle) + [5]*argField{}}, + {LBZCIX, 0xfc0007fe, 0x7c0006aa, 0x1, // Load Byte and Zero Caching Inhibited Indexed X-form (lbzcix RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LWZCIX, 0xfc0007fe, 0x7c00062a, 0x1, // Load Word and Zero Caching Inhibited Indexed X-form (lwzcix RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LHZCIX, 0xfc0007fe, 0x7c00066a, 0x1, // Load Halfword and Zero Caching Inhibited Indexed X-form (lhzcix RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LDCIX, 0xfc0007fe, 0x7c0006ea, 0x1, // Load Doubleword Caching Inhibited Indexed X-form (ldcix RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STBCIX, 0xfc0007fe, 0x7c0007aa, 0x1, // Store Byte Caching Inhibited Indexed X-form (stbcix RS,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STWCIX, 0xfc0007fe, 0x7c00072a, 0x1, // Store Word Caching Inhibited Indexed X-form (stwcix RS,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STHCIX, 0xfc0007fe, 0x7c00076a, 0x1, // Store Halfword Caching Inhibited Indexed X-form (sthcix RS,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STDCIX, 0xfc0007fe, 0x7c0007ea, 0x1, // Store Doubleword Caching Inhibited Indexed X-form (stdcix RS,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {TRECLAIMCC, 0xfc0007ff, 0x7c00075d, 0x3e0f800, // Transaction Reclaim X-form (treclaim. RA) + [5]*argField{ap_Reg_11_15}}, + {TRECHKPTCC, 0xfc0007ff, 0x7c0007dd, 0x3fff800, // Transaction Recheckpoint X-form (trechkpt.) + [5]*argField{}}, + {MTSPR, 0xfc0007fe, 0x7c0003a6, 0x1, // Move To Special Purpose Register XFX-form (mtspr SPR,RS) + [5]*argField{ap_SpReg_16_20_11_15, ap_Reg_6_10}}, + {MFSPR, 0xfc0007fe, 0x7c0002a6, 0x1, // Move From Special Purpose Register XFX-form (mfspr RT,SPR) + [5]*argField{ap_Reg_6_10, ap_SpReg_16_20_11_15}}, + {MTMSR, 0xfc0007fe, 0x7c000124, 0x1ef801, // Move To Machine State Register X-form (mtmsr RS,L) + [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_15_15}}, + {MTMSRD, 0xfc0007fe, 0x7c000164, 0x1ef801, // Move To Machine State Register Doubleword X-form (mtmsrd RS,L) + [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_15_15}}, + {MFMSR, 0xfc0007fe, 0x7c0000a6, 0x1ff801, // Move From Machine State Register X-form (mfmsr RT) + [5]*argField{ap_Reg_6_10}}, + {SLBIE, 0xfc0007fe, 0x7c000364, 0x3ff0001, // SLB Invalidate Entry X-form (slbie RB) + [5]*argField{ap_Reg_16_20}}, + {SLBIA, 0xfc0007fe, 0x7c0003e4, 0x31ff801, // SLB Invalidate All X-form (slbia IH) + [5]*argField{ap_ImmUnsigned_8_10}}, + {SLBMTE, 0xfc0007fe, 0x7c000324, 0x1f0001, // SLB Move To Entry X-form (slbmte RS,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {SLBMFEV, 0xfc0007fe, 0x7c0006a6, 0x1f0001, // SLB Move From Entry VSID X-form (slbmfev RT,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {SLBMFEE, 0xfc0007fe, 0x7c000726, 0x1f0001, // SLB Move From Entry ESID X-form (slbmfee RT,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {SLBFEECC, 0xfc0007ff, 0x7c0007a7, 0x1f0000, // SLB Find Entry ESID X-form (slbfee. RT,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {MTSR, 0xfc0007fe, 0x7c0001a4, 0x10f801, // Move To Segment Register X-form (mtsr SR,RS) + [5]*argField{ap_SpReg_12_15, ap_Reg_6_10}}, + {MTSRIN, 0xfc0007fe, 0x7c0001e4, 0x1f0001, // Move To Segment Register Indirect X-form (mtsrin RS,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {MFSR, 0xfc0007fe, 0x7c0004a6, 0x10f801, // Move From Segment Register X-form (mfsr RT,SR) + [5]*argField{ap_Reg_6_10, ap_SpReg_12_15}}, + {MFSRIN, 0xfc0007fe, 0x7c000526, 0x1f0001, // Move From Segment Register Indirect X-form (mfsrin RT,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {TLBIE, 0xfc0007fe, 0x7c000264, 0x1f0001, // TLB Invalidate Entry X-form (tlbie RB,RS) + [5]*argField{ap_Reg_16_20, ap_Reg_6_10}}, + {TLBIEL, 0xfc0007fe, 0x7c000224, 0x3ff0001, // TLB Invalidate Entry Local X-form (tlbiel RB) + [5]*argField{ap_Reg_16_20}}, + {TLBIA, 0xfc0007fe, 0x7c0002e4, 0x3fff801, // TLB Invalidate All X-form (tlbia) + [5]*argField{}}, + {TLBSYNC, 0xfc0007fe, 0x7c00046c, 0x3fff801, // TLB Synchronize X-form (tlbsync) + [5]*argField{}}, + {MSGSND, 0xfc0007fe, 0x7c00019c, 0x3ff0001, // Message Send X-form (msgsnd RB) + [5]*argField{ap_Reg_16_20}}, + {MSGCLR, 0xfc0007fe, 0x7c0001dc, 0x3ff0001, // Message Clear X-form (msgclr RB) + [5]*argField{ap_Reg_16_20}}, + {MSGSNDP, 0xfc0007fe, 0x7c00011c, 0x3ff0001, // Message Send Privileged X-form (msgsndp RB) + [5]*argField{ap_Reg_16_20}}, + {MSGCLRP, 0xfc0007fe, 0x7c00015c, 0x3ff0001, // Message Clear Privileged X-form (msgclrp RB) + [5]*argField{ap_Reg_16_20}}, + {MTTMR, 0xfc0007fe, 0x7c0003dc, 0x1, // Move To Thread Management Register XFX-form (mttmr TMR,RS) + [5]*argField{ap_SpReg_16_20_11_15, ap_Reg_6_10}}, + {SC, 0xfc000002, 0x44000002, 0x3fffffd, // System Call SC-form (sc) + [5]*argField{}}, + {RFI, 0xfc0007fe, 0x4c000064, 0x3fff801, // Return From Interrupt XL-form (rfi) + [5]*argField{}}, + {RFCI, 0xfc0007fe, 0x4c000066, 0x3fff801, // Return From Critical Interrupt XL-form (rfci) + [5]*argField{}}, + {RFDI, 0xfc0007fe, 0x4c00004e, 0x3fff801, // Return From Debug Interrupt X-form (rfdi) + [5]*argField{}}, + {RFMCI, 0xfc0007fe, 0x4c00004c, 0x3fff801, // Return From Machine Check Interrupt XL-form (rfmci) + [5]*argField{}}, + {RFGI, 0xfc0007fe, 0x4c0000cc, 0x3fff801, // Return From Guest Interrupt XL-form (rfgi) + [5]*argField{}}, + {EHPRIV, 0xfc0007fe, 0x7c00021c, 0x1, // Embedded Hypervisor Privilege XL-form (ehpriv OC) + [5]*argField{ap_ImmUnsigned_6_20}}, + {MTSPR, 0xfc0007fe, 0x7c0003a6, 0x1, // Move To Special Purpose Register XFX-form (mtspr SPR,RS) + [5]*argField{ap_SpReg_16_20_11_15, ap_Reg_6_10}}, + {MFSPR, 0xfc0007fe, 0x7c0002a6, 0x1, // Move From Special Purpose Register XFX-form (mfspr RT,SPR) + [5]*argField{ap_Reg_6_10, ap_SpReg_16_20_11_15}}, + {MTDCR, 0xfc0007fe, 0x7c000386, 0x1, // Move To Device Control Register XFX-form (mtdcr DCRN,RS) + [5]*argField{ap_SpReg_16_20_11_15, ap_Reg_6_10}}, + {MTDCRX, 0xfc0007fe, 0x7c000306, 0xf801, // Move To Device Control Register Indexed X-form (mtdcrx RA,RS) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10}}, + {MFDCR, 0xfc0007fe, 0x7c000286, 0x1, // Move From Device Control Register XFX-form (mfdcr RT,DCRN) + [5]*argField{ap_Reg_6_10, ap_SpReg_16_20_11_15}}, + {MFDCRX, 0xfc0007fe, 0x7c000206, 0xf801, // Move From Device Control Register Indexed X-form (mfdcrx RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {MTMSR, 0xfc0007fe, 0x7c000124, 0x1ff801, // Move To Machine State Register X-form (mtmsr RS) + [5]*argField{ap_Reg_6_10}}, + {MFMSR, 0xfc0007fe, 0x7c0000a6, 0x1ff801, // Move From Machine State Register X-form (mfmsr RT) + [5]*argField{ap_Reg_6_10}}, + {WRTEE, 0xfc0007fe, 0x7c000106, 0x1ff801, // Write MSR External Enable X-form (wrtee RS) + [5]*argField{ap_Reg_6_10}}, + {WRTEEI, 0xfc0007fe, 0x7c000146, 0x3ff7801, // Write MSR External Enable Immediate X-form (wrteei E) + [5]*argField{ap_ImmUnsigned_16_16}}, + {LBEPX, 0xfc0007fe, 0x7c0000be, 0x1, // Load Byte by External Process ID Indexed X-form (lbepx RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LHEPX, 0xfc0007fe, 0x7c00023e, 0x1, // Load Halfword by External Process ID Indexed X-form (lhepx RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LWEPX, 0xfc0007fe, 0x7c00003e, 0x1, // Load Word by External Process ID Indexed X-form (lwepx RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LDEPX, 0xfc0007fe, 0x7c00003a, 0x1, // Load Doubleword by External Process ID Indexed X-form (ldepx RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STBEPX, 0xfc0007fe, 0x7c0001be, 0x1, // Store Byte by External Process ID Indexed X-form (stbepx RS,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STHEPX, 0xfc0007fe, 0x7c00033e, 0x1, // Store Halfword by External Process ID Indexed X-form (sthepx RS,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STWEPX, 0xfc0007fe, 0x7c00013e, 0x1, // Store Word by External Process ID Indexed X-form (stwepx RS,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STDEPX, 0xfc0007fe, 0x7c00013a, 0x1, // Store Doubleword by External Process ID Indexed X-form (stdepx RS,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DCBSTEP, 0xfc0007fe, 0x7c00007e, 0x3e00001, // Data Cache Block Store by External PID X-form (dcbstep RA,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_16_20}}, + {DCBTEP, 0xfc0007fe, 0x7c00027e, 0x1, // Data Cache Block Touch by External PID X-form (dcbtep TH,RA,RB) + [5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DCBFEP, 0xfc0007fe, 0x7c0000fe, 0x3800001, // Data Cache Block Flush by External PID X-form (dcbfep RA,RB,L) + [5]*argField{ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_9_10}}, + {DCBTSTEP, 0xfc0007fe, 0x7c0001fe, 0x1, // Data Cache Block Touch for Store by External PID X-form (dcbtstep TH,RA,RB) + [5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {ICBIEP, 0xfc0007fe, 0x7c0007be, 0x3e00001, // Instruction Cache Block Invalidate by External PID X-form (icbiep RA,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_16_20}}, + {DCBZEP, 0xfc0007fe, 0x7c0007fe, 0x3e00001, // Data Cache Block set to Zero by External PID X-form (dcbzep RA,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_16_20}}, + {LFDEPX, 0xfc0007fe, 0x7c0004be, 0x1, // Load Floating-Point Double by External Process ID Indexed X-form (lfdepx FRT,RA,RB) + [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STFDEPX, 0xfc0007fe, 0x7c0005be, 0x1, // Store Floating-Point Double by External Process ID Indexed X-form (stfdepx FRS,RA,RB) + [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVLDDEPX, 0xfc0007fe, 0x7c00063e, 0x1, // Vector Load Doubleword into Doubleword by External Process ID Indexed EVX-form (evlddepx RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVSTDDEPX, 0xfc0007fe, 0x7c00073e, 0x1, // Vector Store Doubleword into Doubleword by External Process ID Indexed EVX-form (evstddepx RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LVEPX, 0xfc0007fe, 0x7c00024e, 0x1, // Load Vector by External Process ID Indexed X-form (lvepx VRT,RA,RB) + [5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LVEPXL, 0xfc0007fe, 0x7c00020e, 0x1, // Load Vector by External Process ID Indexed LRU X-form (lvepxl VRT,RA,RB) + [5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STVEPX, 0xfc0007fe, 0x7c00064e, 0x1, // Store Vector by External Process ID Indexed X-form (stvepx VRS,RA,RB) + [5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STVEPXL, 0xfc0007fe, 0x7c00060e, 0x1, // Store Vector by External Process ID Indexed LRU X-form (stvepxl VRS,RA,RB) + [5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DCBI, 0xfc0007fe, 0x7c0003ac, 0x3e00001, // Data Cache Block Invalidate X-form (dcbi RA,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_16_20}}, + {DCBLQCC, 0xfc0007ff, 0x7c00034d, 0x2000000, // Data Cache Block Lock Query X-form (dcblq. CT,RA,RB) + [5]*argField{ap_ImmUnsigned_7_10, ap_Reg_11_15, ap_Reg_16_20}}, + {ICBLQCC, 0xfc0007ff, 0x7c00018d, 0x2000000, // Instruction Cache Block Lock Query X-form (icblq. CT,RA,RB) + [5]*argField{ap_ImmUnsigned_7_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DCBTLS, 0xfc0007fe, 0x7c00014c, 0x2000001, // Data Cache Block Touch and Lock Set X-form (dcbtls CT,RA,RB) + [5]*argField{ap_ImmUnsigned_7_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DCBTSTLS, 0xfc0007fe, 0x7c00010c, 0x2000001, // Data Cache Block Touch for Store and Lock Set X-form (dcbtstls CT,RA,RB) + [5]*argField{ap_ImmUnsigned_7_10, ap_Reg_11_15, ap_Reg_16_20}}, + {ICBTLS, 0xfc0007fe, 0x7c0003cc, 0x2000001, // Instruction Cache Block Touch and Lock Set X-form (icbtls CT,RA,RB) + [5]*argField{ap_ImmUnsigned_7_10, ap_Reg_11_15, ap_Reg_16_20}}, + {ICBLC, 0xfc0007fe, 0x7c0001cc, 0x2000001, // Instruction Cache Block Lock Clear X-form (icblc CT,RA,RB) + [5]*argField{ap_ImmUnsigned_7_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DCBLC, 0xfc0007fe, 0x7c00030c, 0x2000001, // Data Cache Block Lock Clear X-form (dcblc CT,RA,RB) + [5]*argField{ap_ImmUnsigned_7_10, ap_Reg_11_15, ap_Reg_16_20}}, + {TLBIVAX, 0xfc0007fe, 0x7c000624, 0x3e00001, // TLB Invalidate Virtual Address Indexed X-form (tlbivax RA,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_16_20}}, + {TLBILX, 0xfc0007fe, 0x7c000024, 0x3800001, // TLB Invalidate Local Indexed X-form (tlbilx RA,RB]) + [5]*argField{ap_Reg_11_15, ap_Reg_16_20}}, + {TLBSX, 0xfc0007fe, 0x7c000724, 0x3e00001, // TLB Search Indexed X-form (tlbsx RA,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_16_20}}, + {TLBSRXCC, 0xfc0007ff, 0x7c0006a5, 0x3e00000, // TLB Search and Reserve Indexed X-form (tlbsrx. RA,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_16_20}}, + {TLBRE, 0xfc0007fe, 0x7c000764, 0x3fff801, // TLB Read Entry X-form (tlbre) + [5]*argField{}}, + {TLBSYNC, 0xfc0007fe, 0x7c00046c, 0x3fff801, // TLB Synchronize X-form (tlbsync) + [5]*argField{}}, + {TLBWE, 0xfc0007fe, 0x7c0007a4, 0x3fff801, // TLB Write Entry X-form (tlbwe) + [5]*argField{}}, + {DNH, 0xfc0007fe, 0x4c00018c, 0x1, // Debugger Notify Halt XFX-form (dnh DUI,DUIS) + [5]*argField{ap_ImmUnsigned_6_10, ap_ImmUnsigned_11_20}}, + {MSGSND, 0xfc0007fe, 0x7c00019c, 0x3ff0001, // Message Send X-form (msgsnd RB) + [5]*argField{ap_Reg_16_20}}, + {MSGCLR, 0xfc0007fe, 0x7c0001dc, 0x3ff0001, // Message Clear X-form (msgclr RB) + [5]*argField{ap_Reg_16_20}}, + {DCI, 0xfc0007fe, 0x7c00038c, 0x21ff801, // Data Cache Invalidate X-form (dci CT) + [5]*argField{ap_ImmUnsigned_7_10}}, + {ICI, 0xfc0007fe, 0x7c00078c, 0x21ff801, // Instruction Cache Invalidate X-form (ici CT) + [5]*argField{ap_ImmUnsigned_7_10}}, + {DCREAD, 0xfc0007fe, 0x7c0003cc, 0x1, // Data Cache Read X-form (dcread RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {ICREAD, 0xfc0007fe, 0x7c0007cc, 0x3e00001, // Instruction Cache Read X-form (icread RA,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_16_20}}, + {MFPMR, 0xfc0007fe, 0x7c00029c, 0x1, // Move From Performance Monitor Register XFX-form (mfpmr RT,PMRN) + [5]*argField{ap_Reg_6_10, ap_SpReg_11_20}}, + {MTPMR, 0xfc0007fe, 0x7c00039c, 0x1, // Move To Performance Monitor Register XFX-form (mtpmr PMRN,RS) + [5]*argField{ap_SpReg_11_20, ap_Reg_6_10}}, + {ADDEX, 0xfc0001fe, 0x7c000154, 0x1, // Add Extended using alternate carry bit Z23-form (addex RT,RA,RB,CY) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_21_22}}, + {DARN, 0xfc0007fe, 0x7c0005e6, 0x1cf801, // Deliver A Random Number X-form (darn RT,L) + [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_14_15}}, + {MADDHD, 0xfc00003f, 0x10000030, 0x0, // Multiply-Add High Doubleword VA-form (maddhd RT,RA,RB,RC) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_Reg_21_25}}, + {MADDHDU, 0xfc00003f, 0x10000031, 0x0, // Multiply-Add High Doubleword Unsigned VA-form (maddhdu RT,RA,RB,RC) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_Reg_21_25}}, + {MADDLD, 0xfc00003f, 0x10000033, 0x0, // Multiply-Add Low Doubleword VA-form (maddld RT,RA,RB,RC) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_Reg_21_25}}, + {CMPRB, 0xfc0007fe, 0x7c000180, 0x400001, // Compare Ranged Byte X-form (cmprb BF,L,RA,RB) + [5]*argField{ap_CondRegField_6_8, ap_ImmUnsigned_10_10, ap_Reg_11_15, ap_Reg_16_20}}, + {CMPEQB, 0xfc0007fe, 0x7c0001c0, 0x600001, // Compare Equal Byte X-form (cmpeqb BF,RA,RB) + [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, + {BPERMD, 0xfc0007fe, 0x7c0001f8, 0x1, // Bit Permute Doubleword X-form (bpermd RA,RS,RB]) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, + {EXTSWSLI, 0xfc0007fd, 0x7c0006f4, 0x0, // Extend-Sign Word and Shift Left Immediate XS-form (extswsli RA,RS,SH) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20}}, + {EXTSWSLICC, 0xfc0007fd, 0x7c0006f5, 0x0, // Extend-Sign Word and Shift Left Immediate XS-form (extswsli. RA,RS,SH) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20}}, + {MFVSRD, 0xfc0007fe, 0x7c000066, 0xf800, // Move From VSR Doubleword X-form (mfvsrd RA,XS) + [5]*argField{ap_Reg_11_15, ap_VecSReg_31_31_6_10}}, + {MFVSRLD, 0xfc0007fe, 0x7c000266, 0xf800, // Move From VSR Lower Doubleword X-form (mfvsrld RA,XS) + [5]*argField{ap_Reg_11_15, ap_VecSReg_31_31_6_10}}, + {MFVSRWZ, 0xfc0007fe, 0x7c0000e6, 0xf800, // Move From VSR Word and Zero X-form (mfvsrwz RA,XS) + [5]*argField{ap_Reg_11_15, ap_VecSReg_31_31_6_10}}, + {MTVSRD, 0xfc0007fe, 0x7c000166, 0xf800, // Move To VSR Doubleword X-form (mtvsrd XT,RA) + [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15}}, + {MTVSRWA, 0xfc0007fe, 0x7c0001a6, 0xf800, // Move To VSR Word Algebraic X-form (mtvsrwa XT,RA) + [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15}}, + {MTVSRWZ, 0xfc0007fe, 0x7c0001e6, 0xf800, // Move To VSR Word and Zero X-form (mtvsrwz XT,RA) + [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15}}, + {MTVSRDD, 0xfc0007fe, 0x7c000366, 0x0, // Move To VSR Double Doubleword X-form (mtvsrdd XT,RA,RB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MTVSRWS, 0xfc0007fe, 0x7c000326, 0xf800, // Move To VSR Word & Splat X-form (mtvsrws XT,RA) + [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15}}, + {MCRXRX, 0xfc0007fe, 0x7c000480, 0x7ff801, // Move to CR from XER Extended X-form (mcrxrx BF) + [5]*argField{ap_CondRegField_6_8}}, + {COPY, 0xfc2007fe, 0x7c20060c, 0x3c00001, // Copy X-form (copy RA,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_16_20}}, + {PASTECC, 0xfc2007ff, 0x7c20070d, 0x3c00000, // Paste X-form (paste. RA,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_16_20}}, +} diff --git a/vendor/modules.txt b/vendor/modules.txt index 783546ca5a..e2812d1f92 100644 --- a/vendor/modules.txt +++ b/vendor/modules.txt @@ -70,6 +70,7 @@ go.starlark.net/syntax # golang.org/x/arch v0.0.0-20190927153633-4e8777c89be4 ## explicit golang.org/x/arch/arm64/arm64asm +golang.org/x/arch/ppc64/ppc64asm golang.org/x/arch/x86/x86asm # golang.org/x/mod v0.6.0-dev.0.20220419223038-86c51ed26bb4 golang.org/x/mod/semver