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This is part of being able to handle bursts of data. Supporting sob and eob for starting and stopping transactions on the HDL buses would be really valuable. Some consideration of how clocking would work when samples are not passing is needed I think.
The text was updated successfully, but these errors were encountered:
Originally requested by @gs-jgj at B0WEN-HU/gr-verilog#4
This is part of being able to handle bursts of data. Supporting
sob
andeob
for starting and stopping transactions on the HDL buses would be really valuable. Some consideration of how clocking would work when samples are not passing is needed I think.The text was updated successfully, but these errors were encountered: