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D-PHY spec operates in two modes, HS and low power which use different IO standards such as differential and single ended. How can we support this in an FPGA?
Any issue you see in trying to use RocketIO primitives available in virtex-2 pro devices?
Thanks
The text was updated successfully, but these errors were encountered:
Hello
I have two questions.
Thanks
The text was updated successfully, but these errors were encountered: