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dvt_build.log
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dvt_build.log
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*** Start analyzing build configuration ***
*** List of included argument files ***
Build configuration file: /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/.dvt/default.build
-F /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/socv/rtl/socv.irunargs
included by /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/.dvt/default.build at line 51
-F /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/padframe/rtl/padframe.irunargs
included by /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/socv/rtl/socv.irunargs at line 19
-F /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/socv/rtl/cdn_busmatrix.irunargs
included by /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/socv/rtl/socv.irunargs at line 22
-F /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/rom_subsystem/rtl/rom_subsystem.irunargs
included by /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/socv/rtl/socv.irunargs at line 25
-F /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/sram_subsystem/rtl/sram_subsystem.irunargs
included by /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/socv/rtl/socv.irunargs at line 28
-F /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/apb_subsystem/rtl/apb_subsystem.irunargs
included by /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/socv/rtl/socv.irunargs at line 31
-F /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/ahb2apb/rtl/ahb2apb.irunargs
included by /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/apb_subsystem/rtl/apb_subsystem.irunargs at line 14
-F /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/alut/rtl/alut.irunargs
included by /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/apb_subsystem/rtl/apb_subsystem.irunargs at line 17
-F /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/oc_spi.irunargs
included by /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/apb_subsystem/rtl/apb_subsystem.irunargs at line 20
-F /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/oc_uart.irunargs
included by /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/apb_subsystem/rtl/apb_subsystem.irunargs at line 23
-F /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/gpio/rtl/gpio_lite.irunargs
included by /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/apb_subsystem/rtl/apb_subsystem.irunargs at line 26
-F /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/ttc/rtl/ttc_lite.irunargs
included by /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/apb_subsystem/rtl/apb_subsystem.irunargs at line 29
-F /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/smc/rtl/smc_lite.irunargs
included by /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/apb_subsystem/rtl/apb_subsystem.irunargs at line 32
-F /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/power_ctrl/rtl/power_ctrl.irunargs
included by /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/apb_subsystem/rtl/apb_subsystem.irunargs at line 35
-F /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/dma/rtl/dma.irunargs
included by /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/socv/rtl/socv.irunargs at line 34
-F /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/mac.irunargs
included by /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/socv/rtl/socv.irunargs at line 37
*** List of invocations ***
Invocation #1 +dvt_init+ius.irun in /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/.dvt/default.build at line 4
*** Done analyzing build configuration [316 ms] ***
*** Start SystemVerilog build ***
*** Loading top files ***
Loading (1) /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/uvm_pkg.sv ...
Loading (2) /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/uvm_macros.svh ...
Loading (3) /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/macros/uvm_version_defines.svh ...
Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/macros/uvm_version_defines.svh [97 ms, 51 lines, SystemVerilog_2012] ...
Loading (4) /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/macros/uvm_message_defines.svh ...
Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/macros/uvm_message_defines.svh [0 ms, 220 lines, SystemVerilog_2012] ...
Loading (5) /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/macros/uvm_phase_defines.svh ...
Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/macros/uvm_phase_defines.svh [0 ms, 130 lines, SystemVerilog_2012] ...
Loading (6) /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/macros/uvm_object_defines.svh ...
Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/macros/uvm_object_defines.svh [51 ms, 3640 lines, SystemVerilog_2012] ...
Loading (7) /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/macros/uvm_printer_defines.svh ...
Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/macros/uvm_printer_defines.svh [0 ms, 420 lines, SystemVerilog_2012] ...
Loading (8) /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/macros/uvm_tlm_defines.svh ...
Loading (9) /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/tlm1/uvm_tlm_imps.svh ...
Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/tlm1/uvm_tlm_imps.svh [0 ms, 229 lines, SystemVerilog_2012] ...
Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/macros/uvm_tlm_defines.svh [0 ms, 615 lines, SystemVerilog_2012] ...
Loading (10) /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/macros/uvm_sequence_defines.svh ...
Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/macros/uvm_sequence_defines.svh [0 ms, 456 lines, SystemVerilog_2012] ...
Loading (11) /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/macros/uvm_callback_defines.svh ...
Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/macros/uvm_callback_defines.svh [50 ms, 292 lines, SystemVerilog_2012] ...
Loading (12) /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/macros/uvm_reg_defines.svh ...
Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/macros/uvm_reg_defines.svh [0 ms, 69 lines, SystemVerilog_2012] ...
Loading (13) /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/macros/uvm_deprecated_defines.svh ...
Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/macros/uvm_deprecated_defines.svh [0 ms, 251 lines, SystemVerilog_2012] ...
Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/uvm_macros.svh [0 ms, 99 lines, SystemVerilog_2012] ...
Loading (14) /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/dpi/uvm_dpi.svh ...
Loading (15) /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/dpi/uvm_hdl.svh ...
Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/dpi/uvm_hdl.svh [16 ms, 164 lines, SystemVerilog_2012] ...
Loading (16) /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/dpi/uvm_svcmd_dpi.svh ...
Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/dpi/uvm_svcmd_dpi.svh [2 ms, 61 lines, SystemVerilog_2012] ...
Loading (17) /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/dpi/uvm_regex.svh ...
Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/dpi/uvm_regex.svh [1 ms, 89 lines, SystemVerilog_2012] ...
Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/dpi/uvm_dpi.svh [0 ms, 44 lines, SystemVerilog_2012] ...
Loading (18) /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/base/uvm_base.svh ...
Loading (19) /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/base/uvm_version.svh ...
Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/base/uvm_version.svh [1 ms, 37 lines, SystemVerilog_2012] ...
Loading (20) /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/base/uvm_object_globals.svh ...
Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/base/uvm_object_globals.svh [25 ms, 672 lines, SystemVerilog_2012] ...
Loading (21) /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/base/uvm_misc.svh ...
Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/base/uvm_misc.svh [94 ms, 702 lines, SystemVerilog_2012] ...
Loading (22) /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/deprecated/uvm_type_utils.svh ...
Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/deprecated/uvm_type_utils.svh [2 ms, 42 lines, SystemVerilog_2012] ...
Loading (23) /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/base/uvm_object.svh ...
Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/base/uvm_object.svh [78 ms, 1329 lines, SystemVerilog_2012] ...
Loading (24) /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/base/uvm_pool.svh ...
Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/base/uvm_pool.svh [23 ms, 348 lines, SystemVerilog_2012] ...
Loading (25) /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/base/uvm_queue.svh ...
Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/base/uvm_queue.svh [14 ms, 214 lines, SystemVerilog_2012] ...
Loading (26) /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/base/uvm_factory.svh ...
Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/base/uvm_factory.svh [111 ms, 1633 lines, SystemVerilog_2012] ...
Loading (27) /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/base/uvm_registry.svh ...
Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/base/uvm_registry.svh [18 ms, 366 lines, SystemVerilog_2012] ...
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Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/uvm_macros.svh [1 ms, 99 lines, SystemVerilog_2012] ...
Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/base/uvm_callback.svh [61 ms, 1192 lines, SystemVerilog_2012] ...
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Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/base/uvm_bottomup_phase.svh [5 ms, 113 lines, SystemVerilog_2012] ...
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Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/base/uvm_common_phases.svh [14 ms, 413 lines, SystemVerilog_2012] ...
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Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/base/uvm_root.svh [61 ms, 903 lines, SystemVerilog_2012] ...
Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/base/uvm_component.svh [92 ms, 3414 lines, SystemVerilog_2012] ...
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Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/base/uvm_base.svh [0 ms, 101 lines, SystemVerilog_2012] ...
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Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/tlm1/uvm_tlm_ifs.svh [6 ms, 219 lines, SystemVerilog_2012] ...
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Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/base/uvm_port_base.svh [29 ms, 792 lines, SystemVerilog_2012] ...
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Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/tlm1/uvm_imps.svh [38 ms, 317 lines, SystemVerilog_2012] ...
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Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/tlm1/uvm_ports.svh [27 ms, 262 lines, SystemVerilog_2012] ...
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Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/tlm1/uvm_exports.svh [26 ms, 260 lines, SystemVerilog_2012] ...
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Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/tlm1/uvm_analysis_port.svh [6 ms, 156 lines, SystemVerilog_2012] ...
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Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/tlm1/uvm_tlm_fifo_base.svh [11 ms, 253 lines, SystemVerilog_2012] ...
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Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/tlm1/uvm_tlm_fifos.svh [7 ms, 239 lines, SystemVerilog_2012] ...
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Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/tlm1/uvm_tlm_req_rsp.svh [11 ms, 349 lines, SystemVerilog_2012] ...
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Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/tlm1/uvm_sqr_connections.svh [8 ms, 96 lines, SystemVerilog_2012] ...
Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/tlm1/uvm_tlm.svh [0 ms, 40 lines, SystemVerilog_2012] ...
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Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/comps/uvm_pair.svh [12 ms, 177 lines, SystemVerilog_2012] ...
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Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/comps/uvm_policies.svh [2 ms, 150 lines, SystemVerilog_2012] ...
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Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/comps/uvm_in_order_comparator.svh [11 ms, 260 lines, SystemVerilog_2012] ...
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Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/comps/uvm_algorithmic_comparator.svh [4 ms, 135 lines, SystemVerilog_2012] ...
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Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/comps/uvm_random_stimulus.svh [4 ms, 132 lines, SystemVerilog_2012] ...
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Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/comps/uvm_subscriber.svh [2 ms, 68 lines, SystemVerilog_2012] ...
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Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/comps/uvm_monitor.svh [1 ms, 54 lines, SystemVerilog_2012] ...
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Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/comps/uvm_driver.svh [2 ms, 89 lines, SystemVerilog_2012] ...
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Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/comps/uvm_push_driver.svh [4 ms, 97 lines, SystemVerilog_2012] ...
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Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/comps/uvm_scoreboard.svh [1 ms, 56 lines, SystemVerilog_2012] ...
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Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/comps/uvm_agent.svh [2 ms, 83 lines, SystemVerilog_2012] ...
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Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/comps/uvm_env.svh [1 ms, 54 lines, SystemVerilog_2012] ...
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Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/comps/uvm_test.svh [2 ms, 82 lines, SystemVerilog_2012] ...
Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/comps/uvm_comps.svh [0 ms, 37 lines, SystemVerilog_2012] ...
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Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/seq/uvm_sequence_item.svh [18 ms, 494 lines, SystemVerilog_2012] ...
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Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/seq/uvm_sequencer_base.svh [64 ms, 1653 lines, SystemVerilog_2012] ...
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Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/seq/uvm_sequence.svh [6 ms, 165 lines, SystemVerilog_2012] ...
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Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/seq/uvm_seq.svh [0 ms, 40 lines, SystemVerilog_2012] ...
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Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/tlm2/uvm_tlm2_defines.svh [0 ms, 45 lines, SystemVerilog_2012] ...
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Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/tlm2/uvm_tlm2_time.svh [4 ms, 333 lines, SystemVerilog_2012] ...
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Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/tlm2/uvm_tlm2_generic_payload.svh [43 ms, 1053 lines, SystemVerilog_2012] ...
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Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/tlm2/uvm_tlm2_imps.svh [4 ms, 203 lines, SystemVerilog_2012] ...
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Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/tlm2/uvm_tlm2_ports.svh [4 ms, 75 lines, SystemVerilog_2012] ...
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Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/tlm2/uvm_tlm2_sockets_base.svh [10 ms, 195 lines, SystemVerilog_2012] ...
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Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/tlm2/uvm_tlm2.svh [0 ms, 30 lines, SystemVerilog_2012] ...
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Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/reg/uvm_vreg_field.svh [27 ms, 1005 lines, SystemVerilog_2012] ...
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Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/reg/uvm_reg_fifo.svh [8 ms, 311 lines, SystemVerilog_2012] ...
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Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/reg/uvm_vreg.svh [55 ms, 1550 lines, SystemVerilog_2012] ...
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Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/reg/uvm_mem.svh [65 ms, 2409 lines, SystemVerilog_2012] ...
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Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/reg/uvm_reg_map.svh [79 ms, 2163 lines, SystemVerilog_2012] ...
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Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/reg/uvm_reg_block.svh [56 ms, 2272 lines, SystemVerilog_2012] ...
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Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/reg/sequences/uvm_reg_hw_reset_seq.svh [6 ms, 146 lines, SystemVerilog_2012] ...
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Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/reg/sequences/uvm_reg_bit_bash_seq.svh [19 ms, 301 lines, SystemVerilog_2012] ...
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Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/reg/sequences/uvm_mem_walk_seq.svh [17 ms, 300 lines, SystemVerilog_2012] ...
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Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/reg/sequences/uvm_mem_access_seq.svh [20 ms, 308 lines, SystemVerilog_2012] ...
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Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/reg/sequences/uvm_reg_access_seq.svh [23 ms, 361 lines, SystemVerilog_2012] ...
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Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/reg/sequences/uvm_reg_mem_shared_access_seq.svh [32 ms, 486 lines, SystemVerilog_2012] ...
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Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/reg/sequences/uvm_reg_mem_built_in_seq.svh [11 ms, 139 lines, SystemVerilog_2012] ...
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Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/reg/sequences/uvm_reg_mem_hdl_paths_seq.svh [25 ms, 175 lines, SystemVerilog_2012] ...
Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/reg/uvm_reg_model.svh [0 ms, 445 lines, SystemVerilog_2012] ...
Done /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/uvm_pkg.sv [0 ms, 41 lines, SystemVerilog_2012] ...
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Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/uart16550/rtl/uart_defines.v [0 ms, 248 lines, Verilog_2001] ...
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Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/spi/rtl/spi_defines.v [0 ms, 160 lines, Verilog_2001] ...
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Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/apb_subsystem/sv/gpio_defines.svh [0 ms, 45 lines, SystemVerilog_2012] ...
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Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/apb_subsystem/sv/spi_defines.svh [0 ms, 43 lines, SystemVerilog_2012] ...
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Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/uart_ctrl/sv/uart_ctrl_defines.svh [0 ms, 47 lines, SystemVerilog_2012] ...
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Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/apb_subsystem/sv/apb_subsystem_defines.svh [0 ms, 41 lines, SystemVerilog_2012] ...
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Skip (optimized) /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/uvm_macros.svh ...
Loading (142) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/ahb/sv/ahb_defines.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/ahb/sv/ahb_defines.sv [0 ms, 12 lines, SystemVerilog_2012] ...
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Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/ahb/sv/ahb_transfer.sv [34 ms, 118 lines, SystemVerilog_2012] ...
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Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/ahb/sv/ahb_master_monitor.sv [20 ms, 179 lines, SystemVerilog_2012] ...
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Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/ahb/sv/ahb_master_sequencer.sv [2 ms, 59 lines, SystemVerilog_2012] ...
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Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/ahb/sv/ahb_master_driver.sv [6 ms, 140 lines, SystemVerilog_2012] ...
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Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/ahb/sv/ahb_master_agent.sv [9 ms, 90 lines, SystemVerilog_2012] ...
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Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/ahb/sv/ahb_slave_monitor.sv [20 ms, 167 lines, SystemVerilog_2012] ...
Loading (149) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/ahb/sv/ahb_slave_sequencer.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/ahb/sv/ahb_slave_sequencer.sv [2 ms, 56 lines, SystemVerilog_2012] ...
Loading (150) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/ahb/sv/ahb_slave_driver.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/ahb/sv/ahb_slave_driver.sv [4 ms, 132 lines, SystemVerilog_2012] ...
Loading (151) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/ahb/sv/ahb_slave_agent.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/ahb/sv/ahb_slave_agent.sv [7 ms, 90 lines, SystemVerilog_2012] ...
Loading (152) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/ahb/sv/ahb_env.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/ahb/sv/ahb_env.sv [12 ms, 104 lines, SystemVerilog_2012] ...
Loading (153) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/ahb/sv/reg_to_ahb_adapter.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/ahb/sv/reg_to_ahb_adapter.sv [4 ms, 60 lines, SystemVerilog_2012] ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/ahb/sv/ahb_pkg.sv [0 ms, 58 lines, SystemVerilog_2012] ...
Loading (154) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/apb/sv/apb_pkg.sv ...
Skip (optimized) /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/uvm_macros.svh ...
Loading (155) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/apb/sv/apb_config.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/apb/sv/apb_config.sv [66 ms, 161 lines, SystemVerilog_2012] ...
Loading (156) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/apb/sv/apb_types.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/apb/sv/apb_types.sv [0 ms, 32 lines, SystemVerilog_2012] ...
Loading (157) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/apb/sv/apb_transfer.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/apb/sv/apb_transfer.sv [21 ms, 59 lines, SystemVerilog_2012] ...
Loading (158) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/apb/sv/apb_monitor.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/apb/sv/apb_monitor.sv [25 ms, 169 lines, SystemVerilog_2012] ...
Loading (159) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/apb/sv/apb_collector.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/apb/sv/apb_collector.sv [25 ms, 158 lines, SystemVerilog_2012] ...
Loading (160) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/apb/sv/apb_master_driver.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/apb/sv/apb_master_driver.sv [16 ms, 165 lines, SystemVerilog_2012] ...
Loading (161) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/apb/sv/apb_master_sequencer.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/apb/sv/apb_master_sequencer.sv [10 ms, 58 lines, SystemVerilog_2012] ...
Loading (162) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/apb/sv/apb_master_agent.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/apb/sv/apb_master_agent.sv [25 ms, 99 lines, SystemVerilog_2012] ...
Loading (163) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/apb/sv/apb_slave_driver.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/apb/sv/apb_slave_driver.sv [4 ms, 104 lines, SystemVerilog_2012] ...
Loading (164) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/apb/sv/apb_slave_sequencer.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/apb/sv/apb_slave_sequencer.sv [8 ms, 58 lines, SystemVerilog_2012] ...
Loading (165) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/apb/sv/apb_slave_agent.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/apb/sv/apb_slave_agent.sv [22 ms, 108 lines, SystemVerilog_2012] ...
Loading (166) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/apb/sv/apb_master_seq_lib.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/apb/sv/apb_master_seq_lib.sv [39 ms, 227 lines, SystemVerilog_2012] ...
Loading (167) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/apb/sv/apb_slave_seq_lib.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/apb/sv/apb_slave_seq_lib.sv [17 ms, 110 lines, SystemVerilog_2012] ...
Loading (168) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/apb/sv/apb_env.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/apb/sv/apb_env.sv [28 ms, 154 lines, SystemVerilog_2012] ...
Loading (169) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/apb/sv/reg_to_apb_adapter.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/apb/sv/reg_to_apb_adapter.sv [6 ms, 61 lines, SystemVerilog_2012] ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/apb/sv/apb_pkg.sv [0 ms, 61 lines, SystemVerilog_2012] ...
Loading (170) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/uart/sv/uart_pkg.sv ...
Skip (optimized) /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/uvm_macros.svh ...
Loading (171) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/uart/sv/uart_config.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/uart/sv/uart_config.sv [46 ms, 112 lines, SystemVerilog_2012] ...
Loading (172) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/uart/sv/uart_frame.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/uart/sv/uart_frame.sv [42 ms, 104 lines, SystemVerilog_2012] ...
Loading (173) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/uart/sv/uart_monitor.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/uart/sv/uart_monitor.sv [40 ms, 248 lines, SystemVerilog_2012] ...
Loading (174) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/uart/sv/uart_rx_monitor.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/uart/sv/uart_rx_monitor.sv [12 ms, 105 lines, SystemVerilog_2012] ...
Loading (175) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/uart/sv/uart_tx_monitor.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/uart/sv/uart_tx_monitor.sv [12 ms, 104 lines, SystemVerilog_2012] ...
Loading (176) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/uart/sv/uart_sequencer.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/uart/sv/uart_sequencer.sv [9 ms, 56 lines, SystemVerilog_2012] ...
Loading (177) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/uart/sv/uart_tx_driver.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/uart/sv/uart_tx_driver.sv [44 ms, 234 lines, SystemVerilog_2012] ...
Loading (178) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/uart/sv/uart_rx_driver.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/uart/sv/uart_rx_driver.sv [29 ms, 231 lines, SystemVerilog_2012] ...
Loading (179) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/uart/sv/uart_tx_agent.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/uart/sv/uart_tx_agent.sv [15 ms, 97 lines, SystemVerilog_2012] ...
Loading (180) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/uart/sv/uart_rx_agent.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/uart/sv/uart_rx_agent.sv [15 ms, 98 lines, SystemVerilog_2012] ...
Loading (181) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/uart/sv/uart_env.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/uart/sv/uart_env.sv [24 ms, 132 lines, SystemVerilog_2012] ...
Loading (182) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/uart/sv/uart_seq_lib.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/uart/sv/uart_seq_lib.sv [29 ms, 172 lines, SystemVerilog_2012] ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/uart/sv/uart_pkg.sv [0 ms, 53 lines, SystemVerilog_2012] ...
Loading (183) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/gpio/sv/gpio_pkg.sv ...
Skip (optimized) /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/uvm_macros.svh ...
Loading (184) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/gpio/sv/gpio_csr.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/gpio/sv/gpio_csr.sv [50 ms, 114 lines, SystemVerilog_2012] ...
Loading (185) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/gpio/sv/gpio_transfer.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/gpio/sv/gpio_transfer.sv [22 ms, 63 lines, SystemVerilog_2012] ...
Loading (186) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/gpio/sv/gpio_config.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/gpio/sv/gpio_config.sv [5 ms, 47 lines, SystemVerilog_2012] ...
Loading (187) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/gpio/sv/gpio_monitor.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/gpio/sv/gpio_monitor.sv [19 ms, 130 lines, SystemVerilog_2012] ...
Loading (188) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/gpio/sv/gpio_sequencer.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/gpio/sv/gpio_sequencer.sv [2 ms, 44 lines, SystemVerilog_2012] ...
Loading (189) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/gpio/sv/gpio_driver.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/gpio/sv/gpio_driver.sv [5 ms, 104 lines, SystemVerilog_2012] ...
Loading (190) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/gpio/sv/gpio_agent.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/gpio/sv/gpio_agent.sv [14 ms, 77 lines, SystemVerilog_2012] ...
Loading (191) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/gpio/sv/gpio_env.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/gpio/sv/gpio_env.sv [23 ms, 118 lines, SystemVerilog_2012] ...
Loading (192) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/gpio/sv/gpio_seq_lib.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/gpio/sv/gpio_seq_lib.sv [11 ms, 76 lines, SystemVerilog_2012] ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/gpio/sv/gpio_pkg.sv [0 ms, 69 lines, SystemVerilog_2012] ...
Loading (193) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/spi/sv/spi_pkg.sv ...
Skip (optimized) /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/uvm_macros.svh ...
Loading (194) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/spi/sv/spi_csr.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/spi/sv/spi_csr.sv [55 ms, 148 lines, SystemVerilog_2012] ...
Loading (195) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/spi/sv/spi_transfer.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/spi/sv/spi_transfer.sv [23 ms, 61 lines, SystemVerilog_2012] ...
Loading (196) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/spi/sv/spi_config.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/spi/sv/spi_config.sv [8 ms, 47 lines, SystemVerilog_2012] ...
Loading (197) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/spi/sv/spi_monitor.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/spi/sv/spi_monitor.sv [18 ms, 154 lines, SystemVerilog_2012] ...
Loading (198) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/spi/sv/spi_sequencer.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/spi/sv/spi_sequencer.sv [1 ms, 44 lines, SystemVerilog_2012] ...
Loading (199) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/spi/sv/spi_driver.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/spi/sv/spi_driver.sv [8 ms, 114 lines, SystemVerilog_2012] ...
Loading (200) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/spi/sv/spi_agent.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/spi/sv/spi_agent.sv [10 ms, 81 lines, SystemVerilog_2012] ...
Loading (201) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/spi/sv/spi_env.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/spi/sv/spi_env.sv [14 ms, 118 lines, SystemVerilog_2012] ...
Loading (202) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/spi/sv/spi_seq_lib.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/spi/sv/spi_seq_lib.sv [8 ms, 74 lines, SystemVerilog_2012] ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/spi/sv/spi_pkg.sv [0 ms, 68 lines, SystemVerilog_2012] ...
Loading (203) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/uart_ctrl/sv/uart_ctrl_pkg.sv ...
Skip (optimized) /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/uvm_macros.svh ...
Loading (204) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/uart_ctrl/sv/uart_ctrl_config.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/uart_ctrl/sv/uart_ctrl_config.sv [15 ms, 71 lines, SystemVerilog_2012] ...
Loading (205) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/uart_ctrl/sv/uart_ctrl_reg_model.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/uart_ctrl/sv/uart_ctrl_reg_model.sv [50 ms, 399 lines, SystemVerilog_2012] ...
Loading (206) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/uart_ctrl/sv/uart_ctrl_scoreboard.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/uart_ctrl/sv/uart_ctrl_scoreboard.sv [29 ms, 247 lines, SystemVerilog_2012] ...
Loading (207) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/uart_ctrl/sv/coverage/uart_ctrl_cover.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/uart_ctrl/sv/coverage/uart_ctrl_cover.sv [4 ms, 96 lines, SystemVerilog_2012] ...
Loading (208) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/uart_ctrl/sv/uart_ctrl_monitor.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/uart_ctrl/sv/uart_ctrl_monitor.sv [24 ms, 182 lines, SystemVerilog_2012] ...
Loading (209) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/uart_ctrl/sv/uart_ctrl_reg_sequencer.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/uart_ctrl/sv/uart_ctrl_reg_sequencer.sv [9 ms, 27 lines, SystemVerilog_2012] ...
Loading (210) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/uart_ctrl/sv/uart_ctrl_virtual_sequencer.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/uart_ctrl/sv/uart_ctrl_virtual_sequencer.sv [15 ms, 50 lines, SystemVerilog_2012] ...
Loading (211) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/uart_ctrl/sv/uart_ctrl_env.sv ...
Loading (212) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/uart_ctrl/sv/uart_ctrl_defines.svh ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/uart_ctrl/sv/uart_ctrl_defines.svh [0 ms, 47 lines, SystemVerilog_2012] ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/uart_ctrl/sv/uart_ctrl_env.sv [33 ms, 189 lines, SystemVerilog_2012] ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/uart_ctrl/sv/uart_ctrl_pkg.sv [0 ms, 53 lines, SystemVerilog_2012] ...
Loading (213) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/apb_subsystem/sv/apb_subsystem_pkg.sv ...
Skip (optimized) /home/irina.tica/git/dvt.main/ro.amiq.dvt.predefined_projects/libs/uvm-1.1b/src/uvm_macros.svh ...
Loading (214) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/apb_subsystem/sv/apb_subsystem_config.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/apb_subsystem/sv/apb_subsystem_config.sv [30 ms, 87 lines, SystemVerilog_2012] ...
Loading (215) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/apb_subsystem/sv/apb_subsystem_scoreboard.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/apb_subsystem/sv/apb_subsystem_scoreboard.sv [13 ms, 128 lines, SystemVerilog_2012] ...
Loading (216) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/apb_subsystem/sv/apb_subsystem_monitor.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/apb_subsystem/sv/apb_subsystem_monitor.sv [4 ms, 64 lines, SystemVerilog_2012] ...
Loading (217) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/apb_subsystem/sv/apb_subsystem_env.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/apb_subsystem/sv/apb_subsystem_env.sv [22 ms, 158 lines, SystemVerilog_2012] ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/apb_subsystem/sv/apb_subsystem_pkg.sv [0 ms, 53 lines, SystemVerilog_2012] ...
Loading (218) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/apb_subsystem/tb/sv/apb_subsystem_top.sv ...
Loading (219) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/ahb/sv/ahb_if.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/ahb/sv/ahb_if.sv [3 ms, 95 lines, SystemVerilog_2012] ...
Loading (220) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/apb/sv/apb_if.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/apb/sv/apb_if.sv [0 ms, 111 lines, SystemVerilog_2012] ...
Loading (221) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/apb/sv/apb_master_if.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/apb/sv/apb_master_if.sv [1 ms, 96 lines, SystemVerilog_2012] ...
Loading (222) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/apb/sv/apb_slave_if.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/apb/sv/apb_slave_if.sv [1 ms, 87 lines, SystemVerilog_2012] ...
Loading (223) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/uart/sv/uart_if.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/uart/sv/uart_if.sv [1 ms, 60 lines, SystemVerilog_2012] ...
Loading (224) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/spi/sv/spi_if.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/spi/sv/spi_if.sv [0 ms, 80 lines, SystemVerilog_2012] ...
Loading (225) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/gpio/sv/gpio_if.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/interface_uvc_lib/gpio/sv/gpio_if.sv [1 ms, 63 lines, SystemVerilog_2012] ...
Loading (226) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/uart_ctrl/sv/coverage/uart_ctrl_internal_if.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/uart_ctrl/sv/coverage/uart_ctrl_internal_if.sv [0 ms, 18 lines, SystemVerilog_2012] ...
Loading (227) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/apb_subsystem/sv/spi_reg_model.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/apb_subsystem/sv/spi_reg_model.sv [30 ms, 207 lines, SystemVerilog_2012] ...
Loading (228) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/apb_subsystem/sv/gpio_reg_model.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/apb_subsystem/sv/gpio_reg_model.sv [35 ms, 253 lines, SystemVerilog_2012] ...
Loading (229) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/apb_subsystem/sv/apb_subsystem_reg_rdb.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/apb_subsystem/sv/apb_subsystem_reg_rdb.sv [7 ms, 92 lines, SystemVerilog_2012] ...
Loading (230) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/uart_ctrl/sv/sequence_lib/uart_ctrl_reg_seq_lib.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/uart_ctrl/sv/sequence_lib/uart_ctrl_reg_seq_lib.sv [20 ms, 166 lines, SystemVerilog_2012] ...
Loading (231) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/apb_subsystem/sv/sequence_lib/spi_reg_seq_lib.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/apb_subsystem/sv/sequence_lib/spi_reg_seq_lib.sv [5 ms, 79 lines, SystemVerilog_2012] ...
Loading (232) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/apb_subsystem/sv/sequence_lib/gpio_reg_seq_lib.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/apb_subsystem/sv/sequence_lib/gpio_reg_seq_lib.sv [3 ms, 54 lines, SystemVerilog_2012] ...
Loading (233) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/apb_subsystem/sv/ahb_user_monitor.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/apb_subsystem/sv/ahb_user_monitor.sv [3 ms, 69 lines, SystemVerilog_2012] ...
Loading (234) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/apb_subsystem/sv/sequence_lib/apb_subsystem_seq_lib.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/apb_subsystem/sv/sequence_lib/apb_subsystem_seq_lib.sv [45 ms, 257 lines, SystemVerilog_2012] ...
Loading (235) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/apb_subsystem/sv/apb_subsystem_vir_sequencer.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/apb_subsystem/sv/apb_subsystem_vir_sequencer.sv [7 ms, 46 lines, SystemVerilog_2012] ...
Loading (236) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/apb_subsystem/sv/sequence_lib/apb_subsystem_vir_seq_lib.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/apb_subsystem/sv/sequence_lib/apb_subsystem_vir_seq_lib.sv [96 ms, 489 lines, SystemVerilog_2012] ...
Loading (237) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/apb_subsystem/tb/sv/apb_subsystem_tb.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/apb_subsystem/tb/sv/apb_subsystem_tb.sv [51 ms, 223 lines, SystemVerilog_2012] ...
Loading (238) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/apb_subsystem/tb/tests/test_lib.sv ...
Loading (239) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/apb_subsystem/tb/tests/apb_uart_simple_test.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/apb_subsystem/tb/tests/apb_uart_simple_test.sv [4 ms, 49 lines, SystemVerilog_2012] ...
Loading (240) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/apb_subsystem/tb/tests/apb_spi_simple_test.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/apb_subsystem/tb/tests/apb_spi_simple_test.sv [3 ms, 48 lines, SystemVerilog_2012] ...
Loading (241) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/apb_subsystem/tb/tests/apb_gpio_simple_test.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/apb_subsystem/tb/tests/apb_gpio_simple_test.sv [3 ms, 49 lines, SystemVerilog_2012] ...
Loading (242) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/apb_subsystem/tb/tests/apb_subsystem_test.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/apb_subsystem/tb/tests/apb_subsystem_test.sv [3 ms, 49 lines, SystemVerilog_2012] ...
Loading (243) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/apb_subsystem/tb/tests/apb_subsystem_lp_test.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/apb_subsystem/tb/tests/apb_subsystem_lp_test.sv [3 ms, 48 lines, SystemVerilog_2012] ...
Loading (244) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/apb_subsystem/tb/tests/lp_shutdown_urt1.sv ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/apb_subsystem/tb/tests/lp_shutdown_urt1.sv [3 ms, 48 lines, SystemVerilog_2012] ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/apb_subsystem/tb/tests/test_lib.sv [0 ms, 34 lines, SystemVerilog_2012] ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/soc_verification_lib/sv_cb_ex_lib/apb_subsystem/tb/sv/apb_subsystem_top.sv [10 ms, 293 lines, SystemVerilog_2012] ...
Loading (245) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/misc/rtl/generic_sram_bit.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/misc/rtl/generic_sram_bit.v [4 ms, 116 lines, Verilog_2001] ...
Loading (246) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/wb_to_ahb/rtl/wb2ahb.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/wb_to_ahb/rtl/wb2ahb.v [11 ms, 242 lines, Verilog_2001] ...
Loading (247) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/socv/rtl/socv.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/socv/rtl/socv.v [28 ms, 2089 lines, Verilog_2001] ...
Loading (248) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/padframe/rtl/pad_models.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/padframe/rtl/pad_models.v [3 ms, 80 lines, Verilog_2001] ...
Loading (249) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/padframe/rtl/dummy_analog_pad.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/padframe/rtl/dummy_analog_pad.v [0 ms, 31 lines, Verilog_2001] ...
Loading (250) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/padframe/rtl/padframe.v ...
Skip (optimized) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/spi/rtl/spi_defines.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/padframe/rtl/padframe.v [24 ms, 797 lines, Verilog_2001] ...
Loading (251) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/padframe/rtl/lvds_beh.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/padframe/rtl/lvds_beh.v [5 ms, 128 lines, Verilog_2001] ...
Loading (252) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/cdn_busmatrix/arbiter.v ...
Loading (253) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/socv/rtl/bm_defs.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/socv/rtl/bm_defs.v [0 ms, 94 lines, Verilog_2001] ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/cdn_busmatrix/arbiter.v [3 ms, 103 lines, Verilog_2001] ...
Loading (254) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/cdn_busmatrix/busmatrix.v ...
Skip (optimized) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/socv/rtl/bm_defs.v ...
Loading (255) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/socv/rtl/bm_params.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/socv/rtl/bm_params.v [6 ms, 68 lines, Verilog_2001] ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/cdn_busmatrix/busmatrix.v [50 ms, 3458 lines, Verilog_2001] ...
Loading (256) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/cdn_busmatrix/master_if.v ...
Skip (optimized) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/socv/rtl/bm_defs.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/cdn_busmatrix/master_if.v [16 ms, 515 lines, Verilog_2001] ...
Loading (257) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/cdn_busmatrix/multiplexer.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/cdn_busmatrix/multiplexer.v [11 ms, 169 lines, Verilog_2001] ...
Loading (258) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/cdn_busmatrix/req_register.v ...
Skip (optimized) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/socv/rtl/bm_defs.v ...
Loading (259) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/socv/rtl/bm_params.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/socv/rtl/bm_params.v [5 ms, 68 lines, Verilog_2001] ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/cdn_busmatrix/req_register.v [14 ms, 350 lines, Verilog_2001] ...
Loading (260) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/cdn_busmatrix/slave_if.v ...
Skip (optimized) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/socv/rtl/bm_defs.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/cdn_busmatrix/slave_if.v [12 ms, 407 lines, Verilog_2001] ...
Loading (261) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/rom_subsystem/rtl/rom_response_gen.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/rom_subsystem/rtl/rom_response_gen.v [4 ms, 117 lines, Verilog_2001] ...
Loading (262) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/rom_subsystem/rtl/rom_subsystem.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/rom_subsystem/rtl/rom_subsystem.v [2 ms, 154 lines, Verilog_2001] ...
Loading (263) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/mem_wrap/rtl/ROM_SP_512x32_wrap.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/mem_wrap/rtl/ROM_SP_512x32_wrap.v [2 ms, 58 lines, Verilog_2001] ...
Loading (264) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/misc/rtl/generic_sram.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/misc/rtl/generic_sram.v [3 ms, 113 lines, Verilog_2001] ...
Loading (265) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/sram_subsystem/rtl/sram_subsystem.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/sram_subsystem/rtl/sram_subsystem.v [13 ms, 387 lines, Verilog_2001] ...
Loading (266) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/sram_subsystem/rtl/insn_sram_subsystem.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/sram_subsystem/rtl/insn_sram_subsystem.v [6 ms, 272 lines, Verilog_2001] ...
Loading (267) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/sram_subsystem/rtl/en_gen.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/sram_subsystem/rtl/en_gen.v [3 ms, 103 lines, Verilog_2001] ...
Loading (268) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/sram_subsystem/rtl/sram_response_gen.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/sram_subsystem/rtl/sram_response_gen.v [3 ms, 141 lines, Verilog_2001] ...
Loading (269) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/sram_subsystem/rtl/generic_sram_128k_wrapper.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/sram_subsystem/rtl/generic_sram_128k_wrapper.v [2 ms, 62 lines, Verilog_2001] ...
Loading (270) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/sram_subsystem/rtl/generic_sram_32k_wrapper.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/sram_subsystem/rtl/generic_sram_32k_wrapper.v [2 ms, 79 lines, Verilog_2001] ...
Loading (271) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/apb_subsystem/rtl/apb_subsystem_0.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/apb_subsystem/rtl/apb_subsystem_0.v [26 ms, 1228 lines, Verilog_2001] ...
Loading (272) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/apb_subsystem/rtl/apb_subsystem_1.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/apb_subsystem/rtl/apb_subsystem_1.v [5 ms, 307 lines, Verilog_2001] ...
Loading (273) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/apb_subsystem/rtl/alut_veneer.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/apb_subsystem/rtl/alut_veneer.v [1 ms, 93 lines, Verilog_2001] ...
Loading (274) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/apb_subsystem/rtl/gpio_veneer.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/apb_subsystem/rtl/gpio_veneer.v [2 ms, 179 lines, Verilog_2001] ...
Loading (275) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/apb_subsystem/rtl/ttc_veneer.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/apb_subsystem/rtl/ttc_veneer.v [2 ms, 112 lines, Verilog_2001] ...
Loading (276) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/apb_subsystem/rtl/smc_veneer.v ...
Loading (277) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/smc/rtl/smc_defs_lite.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/smc/rtl/smc_defs_lite.v [0 ms, 67 lines, Verilog_2001] ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/apb_subsystem/rtl/smc_veneer.v [3 ms, 252 lines, Verilog_2001] ...
Loading (278) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/apb_subsystem/rtl/power_ctrl_veneer.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/apb_subsystem/rtl/power_ctrl_veneer.v [6 ms, 460 lines, Verilog_2001] ...
Loading (279) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/ahb2apb/rtl/ahb2apb.v ...
Loading (280) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/ahb2apb/rtl/ahb2apb_defines.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/ahb2apb/rtl/ahb2apb_defines.v [0 ms, 35 lines, Verilog_2001] ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/ahb2apb/rtl/ahb2apb.v [17 ms, 709 lines, Verilog_2001] ...
Loading (281) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/alut/rtl/alut_reg_bank.v ...
Loading (282) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/alut/rtl/alut_defines.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/alut/rtl/alut_defines.v [0 ms, 42 lines, Verilog_2001] ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/alut/rtl/alut_reg_bank.v [13 ms, 386 lines, Verilog_2001] ...
Loading (283) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/alut/rtl/alut_addr_checker.v ...
Skip (optimized) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/alut/rtl/alut_defines.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/alut/rtl/alut_addr_checker.v [10 ms, 369 lines, Verilog_2001] ...
Loading (284) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/alut/rtl/alut_mem.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/alut/rtl/alut_mem.v [2 ms, 84 lines, Verilog_2001] ...
Loading (285) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/alut/rtl/alut_age_checker.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/alut/rtl/alut_age_checker.v [10 ms, 331 lines, Verilog_2001] ...
Loading (286) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/alut/rtl/alut.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/alut/rtl/alut.v [3 ms, 224 lines, Verilog_2001] ...
Loading (287) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/spi/rtl/spi_clgen.v ...
Skip (optimized) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/spi/rtl/spi_defines.v ...
Loading (288) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/spi/rtl/timescale.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/spi/rtl/timescale.v [0 ms, 3 lines, Verilog_2001] ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/spi/rtl/spi_clgen.v [3 ms, 109 lines, Verilog_2001] ...
Loading (289) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/spi/rtl/spi_shift.v ...
Skip (optimized) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/spi/rtl/spi_defines.v ...
Skip (optimized) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/spi/rtl/timescale.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/spi/rtl/spi_shift.v [11 ms, 239 lines, Verilog_2001] ...
Loading (290) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/spi/rtl/spi_top.v ...
Skip (optimized) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/spi/rtl/spi_defines.v ...
Skip (optimized) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/spi/rtl/timescale.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/spi/rtl/spi_top.v [11 ms, 315 lines, Verilog_2001] ...
Loading (291) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/uart16550/rtl/uart_top.v ...
Skip (optimized) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/spi/rtl/timescale.v ...
Skip (optimized) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/uart16550/rtl/uart_defines.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/uart16550/rtl/uart_top.v [5 ms, 341 lines, Verilog_2001] ...
Loading (292) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/uart16550/rtl/uart_wb.v ...
Skip (optimized) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/spi/rtl/timescale.v ...
Skip (optimized) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/uart16550/rtl/uart_defines.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/uart16550/rtl/uart_wb.v [8 ms, 318 lines, Verilog_2001] ...
Loading (293) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/uart16550/rtl/uart_transmitter.v ...
Skip (optimized) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/spi/rtl/timescale.v ...
Skip (optimized) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/uart16550/rtl/uart_defines.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/uart16550/rtl/uart_transmitter.v [9 ms, 352 lines, Verilog_2001] ...
Loading (294) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/uart16550/rtl/uart_receiver.v ...
Skip (optimized) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/spi/rtl/timescale.v ...
Skip (optimized) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/uart16550/rtl/uart_defines.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/uart16550/rtl/uart_receiver.v [12 ms, 483 lines, Verilog_2001] ...
Loading (295) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/uart16550/rtl/uart_tfifo.v ...
Skip (optimized) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/spi/rtl/timescale.v ...
Skip (optimized) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/uart16550/rtl/uart_defines.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/uart16550/rtl/uart_tfifo.v [3 ms, 244 lines, Verilog_2001] ...
Loading (296) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/uart16550/rtl/uart_rfifo.v ...
Skip (optimized) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/spi/rtl/timescale.v ...
Skip (optimized) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/uart16550/rtl/uart_defines.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/uart16550/rtl/uart_rfifo.v [6 ms, 321 lines, Verilog_2001] ...
Loading (297) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/uart16550/rtl/uart_regs.v ...
Skip (optimized) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/spi/rtl/timescale.v ...
Skip (optimized) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/uart16550/rtl/uart_defines.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/uart16550/rtl/uart_regs.v [36 ms, 894 lines, Verilog_2001] ...
Loading (298) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/uart16550/rtl/uart_debug_if.v ...
Skip (optimized) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/spi/rtl/timescale.v ...
Skip (optimized) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/uart16550/rtl/uart_defines.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/uart16550/rtl/uart_debug_if.v [3 ms, 127 lines, Verilog_2001] ...
Loading (299) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/uart16550/rtl/raminfr.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/uart16550/rtl/raminfr.v [3 ms, 112 lines, Verilog_2001] ...
Loading (300) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/uart16550/rtl/uart_sync_flops.v ...
Skip (optimized) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/spi/rtl/timescale.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/uart16550/rtl/uart_sync_flops.v [3 ms, 123 lines, Verilog_2001] ...
Loading (301) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/gpio/rtl/gpio_lite_subunit.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/gpio/rtl/gpio_lite_subunit.v [7 ms, 360 lines, Verilog_2001] ...
Loading (302) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/gpio/rtl/gpio_lite.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/gpio/rtl/gpio_lite.v [4 ms, 193 lines, Verilog_2001] ...
Loading (303) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/ttc/rtl/ttc_counter_lite.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/ttc/rtl/ttc_counter_lite.v [7 ms, 262 lines, Verilog_2001] ...
Loading (304) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/ttc/rtl/ttc_interface_lite.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/ttc/rtl/ttc_interface_lite.v [19 ms, 319 lines, Verilog_2001] ...
Loading (305) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/ttc/rtl/ttc_interrupt_lite.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/ttc/rtl/ttc_interrupt_lite.v [4 ms, 162 lines, Verilog_2001] ...
Loading (306) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/ttc/rtl/ttc_count_rst_lite.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/ttc/rtl/ttc_count_rst_lite.v [3 ms, 145 lines, Verilog_2001] ...
Loading (307) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/ttc/rtl/ttc_timer_counter_lite.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/ttc/rtl/ttc_timer_counter_lite.v [4 ms, 170 lines, Verilog_2001] ...
Loading (308) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/ttc/rtl/ttc_lite.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/ttc/rtl/ttc_lite.v [6 ms, 287 lines, Verilog_2001] ...
Loading (309) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/smc/rtl/smc_addr_lite.v ...
Skip (optimized) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/smc/rtl/smc_defs_lite.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/smc/rtl/smc_addr_lite.v [20 ms, 410 lines, Verilog_2001] ...
Loading (310) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/smc/rtl/smc_cfreg_lite.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/smc/rtl/smc_cfreg_lite.v [1 ms, 54 lines, Verilog_2001] ...
Loading (311) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/smc/rtl/smc_apb_lite_if.v ...
Skip (optimized) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/smc/rtl/smc_defs_lite.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/smc/rtl/smc_apb_lite_if.v [2 ms, 114 lines, Verilog_2001] ...
Loading (312) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/smc/rtl/smc_ahb_lite_if.v ...
Skip (optimized) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/smc/rtl/smc_defs_lite.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/smc/rtl/smc_ahb_lite_if.v [6 ms, 380 lines, Verilog_2001] ...
Loading (313) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/smc/rtl/smc_counter_lite.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/smc/rtl/smc_counter_lite.v [7 ms, 468 lines, Verilog_2001] ...
Loading (314) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/smc/rtl/smc_mac_lite.v ...
Skip (optimized) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/smc/rtl/smc_defs_lite.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/smc/rtl/smc_mac_lite.v [35 ms, 614 lines, Verilog_2001] ...
Loading (315) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/smc/rtl/smc_state_lite.v ...
Skip (optimized) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/smc/rtl/smc_defs_lite.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/smc/rtl/smc_state_lite.v [12 ms, 507 lines, Verilog_2001] ...
Loading (316) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/smc/rtl/smc_strobe_lite.v ...
Skip (optimized) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/smc/rtl/smc_defs_lite.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/smc/rtl/smc_strobe_lite.v [14 ms, 714 lines, Verilog_2001] ...
Loading (317) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/smc/rtl/smc_wr_enable_lite.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/smc/rtl/smc_wr_enable_lite.v [2 ms, 95 lines, Verilog_2001] ...
Loading (318) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/smc/rtl/smc_lite.v ...
Skip (optimized) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/smc/rtl/smc_defs_lite.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/smc/rtl/smc_lite.v [4 ms, 467 lines, Verilog_2001] ...
Loading (319) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/power_ctrl/rtl/power_ctrl_sm.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/power_ctrl/rtl/power_ctrl_sm.v [7 ms, 333 lines, Verilog_2001] ...
Loading (320) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/power_ctrl/rtl/power_ctrl.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/power_ctrl/rtl/power_ctrl.v [53 ms, 1558 lines, Verilog_2001] ...
Loading (321) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/dma/rtl/dma.v ...
Loading (322) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/dma/rtl/dma_defs.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/dma/rtl/dma_defs.v [0 ms, 175 lines, Verilog_2001] ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/dma/rtl/dma.v [12 ms, 1117 lines, Verilog_2001] ...
Loading (323) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/dma/rtl/dma_ahb_config.v ...
Skip (optimized) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/dma/rtl/dma_defs.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/dma/rtl/dma_ahb_config.v [25 ms, 873 lines, Verilog_2001] ...
Loading (324) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/dma/rtl/dma_int_control.v ...
Skip (optimized) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/dma/rtl/dma_defs.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/dma/rtl/dma_int_control.v [5 ms, 384 lines, Verilog_2001] ...
Loading (325) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/dma/rtl/dma_ahb_master.v ...
Skip (optimized) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/dma/rtl/dma_defs.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/dma/rtl/dma_ahb_master.v [4 ms, 166 lines, Verilog_2001] ...
Loading (326) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/dma/rtl/dma_ahb_mux.v ...
Skip (optimized) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/dma/rtl/dma_defs.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/dma/rtl/dma_ahb_mux.v [8 ms, 430 lines, Verilog_2001] ...
Loading (327) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/dma/rtl/dma_apb_mux.v ...
Skip (optimized) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/dma/rtl/dma_defs.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/dma/rtl/dma_apb_mux.v [7 ms, 389 lines, Verilog_2001] ...
Loading (328) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/dma/rtl/dma_arbiter.v ...
Skip (optimized) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/dma/rtl/dma_defs.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/dma/rtl/dma_arbiter.v [11 ms, 662 lines, Verilog_2001] ...
Loading (329) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/dma/rtl/dma_channel.v ...
Skip (optimized) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/dma/rtl/dma_defs.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/dma/rtl/dma_channel.v [51 ms, 1507 lines, Verilog_2001] ...
Loading (330) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/dma/rtl/dma_flow_mux.v ...
Skip (optimized) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/dma/rtl/dma_defs.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/dma/rtl/dma_flow_mux.v [11 ms, 467 lines, Verilog_2001] ...
Loading (331) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/dma/rtl/dma_rx_sm.v ...
Skip (optimized) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/dma/rtl/dma_defs.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/dma/rtl/dma_rx_sm.v [5 ms, 302 lines, Verilog_2001] ...
Loading (332) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/dma/rtl/dma_tx_sm.v ...
Skip (optimized) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/dma/rtl/dma_defs.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/dma/rtl/dma_tx_sm.v [5 ms, 290 lines, Verilog_2001] ...
Loading (333) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/mac_veneer.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/mac_veneer.v [7 ms, 332 lines, Verilog_2001] ...
Loading (334) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/mac_pcm.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/mac_pcm.v [3 ms, 127 lines, Verilog_2001] ...
Loading (335) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/ethmac/rtl/eth_crc.v ...
Skip (optimized) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/spi/rtl/timescale.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/ethmac/rtl/eth_crc.v [4 ms, 146 lines, Verilog_2001] ...
Loading (336) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/ethmac/rtl/eth_maccontrol.v ...
Skip (optimized) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/spi/rtl/timescale.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/ethmac/rtl/eth_maccontrol.v [5 ms, 272 lines, Verilog_2001] ...
Loading (337) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/ethmac/rtl/eth_macstatus.v ...
Skip (optimized) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/spi/rtl/timescale.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/ethmac/rtl/eth_macstatus.v [10 ms, 426 lines, Verilog_2001] ...
Loading (338) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/ethmac/rtl/eth_miim.v ...
Skip (optimized) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/spi/rtl/timescale.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/ethmac/rtl/eth_miim.v [12 ms, 449 lines, Verilog_2001] ...
Loading (339) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/ethmac/rtl/eth_outputcontrol.v ...
Skip (optimized) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/spi/rtl/timescale.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/ethmac/rtl/eth_outputcontrol.v [2 ms, 148 lines, Verilog_2001] ...
Loading (340) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/ethmac/rtl/eth_random.v ...
Skip (optimized) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/spi/rtl/timescale.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/ethmac/rtl/eth_random.v [2 ms, 142 lines, Verilog_2001] ...
Loading (341) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/ethmac/rtl/eth_receivecontrol.v ...
Skip (optimized) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/spi/rtl/timescale.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/ethmac/rtl/eth_receivecontrol.v [16 ms, 439 lines, Verilog_2001] ...
Loading (342) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/ethmac/rtl/eth_register.v ...
Skip (optimized) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/spi/rtl/timescale.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/ethmac/rtl/eth_register.v [1 ms, 110 lines, Verilog_2001] ...
Loading (343) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/ethmac/rtl/eth_registers.v ...
Loading (344) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/ethmac/rtl/eth_defines.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/ethmac/rtl/eth_defines.v [0 ms, 346 lines, Verilog_2001] ...
Skip (optimized) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/spi/rtl/timescale.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/ethmac/rtl/eth_registers.v [70 ms, 1182 lines, Verilog_2001] ...
Loading (345) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/ethmac/rtl/eth_rxcounters.v ...
Skip (optimized) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/spi/rtl/timescale.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/ethmac/rtl/eth_rxcounters.v [12 ms, 219 lines, Verilog_2001] ...
Loading (346) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/ethmac/rtl/eth_rxethmac.v ...
Skip (optimized) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/spi/rtl/timescale.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/ethmac/rtl/eth_rxethmac.v [17 ms, 378 lines, Verilog_2001] ...
Loading (347) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/ethmac/rtl/eth_rxstatem.v ...
Skip (optimized) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/spi/rtl/timescale.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/ethmac/rtl/eth_rxstatem.v [6 ms, 197 lines, Verilog_2001] ...
Loading (348) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/ethmac/rtl/eth_shiftreg.v ...
Skip (optimized) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/spi/rtl/timescale.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/ethmac/rtl/eth_shiftreg.v [7 ms, 152 lines, Verilog_2001] ...
Loading (349) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/ethmac/rtl/eth_top.v ...
Skip (optimized) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/ethmac/rtl/eth_defines.v ...
Skip (optimized) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/spi/rtl/timescale.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/ethmac/rtl/eth_top.v [25 ms, 969 lines, Verilog_2001] ...
Loading (350) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/ethmac/rtl/eth_transmitcontrol.v ...
Skip (optimized) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/spi/rtl/timescale.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/ethmac/rtl/eth_transmitcontrol.v [19 ms, 327 lines, Verilog_2001] ...
Loading (351) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/ethmac/rtl/eth_txcounters.v ...
Skip (optimized) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/spi/rtl/timescale.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/ethmac/rtl/eth_txcounters.v [8 ms, 222 lines, Verilog_2001] ...
Loading (352) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/ethmac/rtl/eth_txethmac.v ...
Skip (optimized) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/spi/rtl/timescale.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/ethmac/rtl/eth_txethmac.v [23 ms, 493 lines, Verilog_2001] ...
Loading (353) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/ethmac/rtl/eth_txstatem.v ...
Skip (optimized) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/spi/rtl/timescale.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/ethmac/rtl/eth_txstatem.v [10 ms, 285 lines, Verilog_2001] ...
Loading (354) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/ethmac/rtl/eth_clockgen.v ...
Skip (optimized) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/spi/rtl/timescale.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/ethmac/rtl/eth_clockgen.v [4 ms, 132 lines, Verilog_2001] ...
Loading (355) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/ethmac/rtl/eth_spram_256x32.v ...
Skip (optimized) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/ethmac/rtl/eth_defines.v ...
Skip (optimized) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/spi/rtl/timescale.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/ethmac/rtl/eth_spram_256x32.v [5 ms, 310 lines, Verilog_2001] ...
Loading (356) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/ethmac/rtl/eth_wishbone.v ...
Skip (optimized) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/ethmac/rtl/eth_defines.v ...
Skip (optimized) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/spi/rtl/timescale.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/ethmac/rtl/eth_wishbone.v [94 ms, 2557 lines, Verilog_2001] ...
Loading (357) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/ethmac/rtl/eth_fifo.v ...
Skip (optimized) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/ethmac/rtl/eth_defines.v ...
Skip (optimized) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/spi/rtl/timescale.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/ethmac/rtl/eth_fifo.v [5 ms, 187 lines, Verilog_2001] ...
Loading (358) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/ethmac/rtl/eth_rxaddrcheck.v ...
Skip (optimized) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/spi/rtl/timescale.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/opencores/ethmac/rtl/eth_rxaddrcheck.v [9 ms, 208 lines, Verilog_2001] ...
Loading (359) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/cdn_chip/rtl/ahb2ocp.v ...
Loading (360) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/cdn_chip/rtl/ahb2ocp_defs.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/cdn_chip/rtl/ahb2ocp_defs.v [0 ms, 36 lines, Verilog_2001] ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/cdn_chip/rtl/ahb2ocp.v [17 ms, 550 lines, Verilog_2001] ...
Loading (361) /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/cdn_chip/rtl/ahb2ocp_ram.v ...
Done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/designs/socv/rtl/rtl_lpw/cdn_chip/rtl/ahb2ocp_ram.v [3 ms, 94 lines, Verilog_2001] ...
*** Done parsing [LT 2622.0 ms, PT 5512.0 ms, SGT 13%, UGT 36%] ***
*** Total number of lines [125 097] ***
Performing post full build actions ...
Performing post full build step 1 (SRI) [6 ms] ...
Performing post full build step 2 (RI) [9 ms] ...
Performing post full build step 3 (RCP) [43 ms] ...
*** Done SystemVerilog build [5s.723ms] ***
*** Start mixed mode extension build ***
Performing mixed post full build step 1 (Verilog - RI) [8 ms] ...
Performing mixed post full build step 2 (Verilog - RC) [0 ms] ...
Elaborate top design elements:
work:apb_subsystem_top (-top work.apb_subsystem_top)
Performing mixed post full build step 3 (Verilog - RPC) [167 ms] ...
Performing mixed post full build step 4 (Verilog - RD) [28 ms] ...
Performing mixed post full build step 5 (Verilog - FSC) [771 ms] ...
Performing mixed post full build step 6 (Verilog - EV) [519 ms] ...
Performing mixed post full build step 7 (Verilog - US) [152 ms] ...
*** Start Power Format build ***
[DVTTclInterp] Defined build config var 'UVM_REF_HOME=/home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1'
[DVTTclInterp] Defined build config var 'DVT_PROJECT_LOC=/home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1'
[DVTTclInterp] Defined build config var 'DVT_COMPILATION_ROOT=/home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1'
TCL done /home/irina.tica/.dvt/settings/dvt_pre_interpret.tcl [1 ms]
TCL load_upf /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/upf/testbench.upf @ 5 : sourcing /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/./upf/apb_subsystem.upf
TCL done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/./upf/apb_subsystem.upf [15 ms]
TCL done /home/irina.tica/dvt_predefined_projects_target/uvm_ref_flow_1.1/upf/testbench.upf [12 ms]
*** Done Power Format build [257 ms] ***
*** Done mixed mode extension build [2s.004ms] ***
*** Start adding/validating the DVT Auto-Linked resources ***
*** Done adding/validating the DVT Auto-Linked resources [42 ms] ***
*** Total build time [8s.078ms] ***