From d4774c6ca435ab61c3dfe51eea9c283f79c73d63 Mon Sep 17 00:00:00 2001 From: Jiuyang liu Date: Fri, 15 Jan 2021 17:51:28 +0000 Subject: [PATCH] remove chisel.Driver and other deprecated usages. --- .../scala/chisel3/iotesters/ChiselMain.scala | 20 +- .../scala/chisel3/iotesters/ChiselSpec.scala | 2 +- src/main/scala/chisel3/iotesters/Driver.scala | 7 +- .../iotesters/DriverCompatibility.scala | 288 ++++++++++++++++++ .../chisel3/iotesters/FirrtlTerpBackend.scala | 5 +- .../scala/chisel3/iotesters/IOAccessor.scala | 1 - .../scala/chisel3/iotesters/IVLBackend.scala | 5 +- .../iotesters/PeekPokeTesterUtils.scala | 1 - .../scala/chisel3/iotesters/Pokeable.scala | 5 +- .../chisel3/iotesters/SteppedHWIOTester.scala | 2 +- .../scala/chisel3/iotesters/TestErrors.scala | 2 - .../scala/chisel3/iotesters/VCSBackend.scala | 5 +- .../scala/chisel3/iotesters/VSIMBackend.scala | 5 +- .../chisel3/iotesters/VerilatorBackend.scala | 8 +- .../chisel3/iotesters/compatibility.scala | 3 +- .../BlackBoxVerilogDeliverySpec.scala | 4 +- .../scala/examples/DynamicMemorySearch.scala | 2 +- src/test/scala/examples/GCDUnitTest.scala | 2 +- src/test/scala/verilator/Verilator.scala | 3 +- 19 files changed, 330 insertions(+), 40 deletions(-) create mode 100644 src/main/scala/chisel3/iotesters/DriverCompatibility.scala diff --git a/src/main/scala/chisel3/iotesters/ChiselMain.scala b/src/main/scala/chisel3/iotesters/ChiselMain.scala index 63028c56..2401e4ee 100644 --- a/src/main/scala/chisel3/iotesters/ChiselMain.scala +++ b/src/main/scala/chisel3/iotesters/ChiselMain.scala @@ -82,13 +82,13 @@ object chiselMain { // Copy API files copyVerilatorHeaderFiles(context.targetDir.toString) // Generate Verilator - assert(chisel3.Driver.verilogToCpp( + assert(firrtl.util.BackendCompilationUtilities.verilogToCpp( dutName, dir, Seq(), new File(dir, s"$dutName-harness.cpp")).! == 0) // Compile Verilator - assert(chisel3.Driver.cppToExe(dutName, dir).! == 0) + assert(firrtl.util.BackendCompilationUtilities.cppToExe(dutName, dir).! == 0) case "vcs" | "glsim" => // Copy API files copyVpiFiles(context.targetDir.toString) @@ -107,25 +107,25 @@ object chiselMain { case x: IOException => System.err.format("createFile error: %s%n", x) } - val circuit = chisel3.Driver.elaborate(dutGen) - val dut = getTopModule(circuit).asInstanceOf[T] - val nodes = getChiselNodes(circuit) + val cir = chisel3.stage.ChiselStage.elaborate(dutGen()) + val dut = getTopModule(cir).asInstanceOf[T] + val nodes = getChiselNodes(cir) val dir = context.targetDir - val name = circuit.name + val name = cir.name - val chirrtl = firrtl.Parser.parse(chisel3.Driver.emit(circuit)) + val fir = chisel3.stage.ChiselStage.convert(dutGen()) val chirrtlFile = new File(dir, s"$name.ir") val verilogFile = new File(dir, s"$name.v") context.backendType match { case "firrtl" => val writer = new FileWriter(chirrtlFile) - (new firrtl.LowFirrtlEmitter).emit(firrtl.CircuitState(chirrtl, firrtl.ChirrtlForm), writer) + (new firrtl.LowFirrtlEmitter).emit(firrtl.CircuitState(fir, firrtl.ChirrtlForm), writer) writer.close() case _ if context.isGenVerilog => val annotations = Seq(firrtl.passes.memlib.InferReadWriteAnnotation) val writer = new FileWriter(verilogFile) val compileResult = (new firrtl.VerilogCompiler).compileAndEmit( - firrtl.CircuitState(chirrtl, firrtl.ChirrtlForm, annotations), + firrtl.CircuitState(fir, firrtl.ChirrtlForm, annotations), List(new firrtl.passes.memlib.InferReadWrite) ) writer.write(compileResult.getEmittedCircuit.value) @@ -133,7 +133,7 @@ object chiselMain { case _ => } - if (context.isGenHarness) genHarness(dut, nodes, chirrtl) + if (context.isGenHarness) genHarness(dut, nodes, fir) if (context.isCompiling) compile(name) diff --git a/src/main/scala/chisel3/iotesters/ChiselSpec.scala b/src/main/scala/chisel3/iotesters/ChiselSpec.scala index 691358c0..4a7843f6 100644 --- a/src/main/scala/chisel3/iotesters/ChiselSpec.scala +++ b/src/main/scala/chisel3/iotesters/ChiselSpec.scala @@ -23,7 +23,7 @@ trait ChiselRunners extends Assertions { def assertTesterPasses(t: => BasicTester, additionalVResources: Seq[String] = Seq()): Unit = { assert(runTester(t, additionalVResources)) } - def elaborate(t: => Module): Unit = chisel3.Driver.elaborate(() => t) + def elaborate(t: => Module): Unit = chisel3.stage.ChiselStage.elaborate(t) } /** Spec base class for BDD-style testers. */ diff --git a/src/main/scala/chisel3/iotesters/Driver.scala b/src/main/scala/chisel3/iotesters/Driver.scala index 03b84a22..14bf72c5 100644 --- a/src/main/scala/chisel3/iotesters/Driver.scala +++ b/src/main/scala/chisel3/iotesters/Driver.scala @@ -2,9 +2,10 @@ package chisel3.iotesters -import chisel3._ +import chisel3.{ChiselExecutionFailure => _, ChiselExecutionResult => _, ChiselExecutionSuccess => _, _} import java.io.File +import chisel3.iotesters.DriverCompatibility._ import firrtl.annotations.Annotation import firrtl_interpreter._ import logger.Logger @@ -142,7 +143,7 @@ object Driver { optionsManager.firrtlOptions = optionsManager.firrtlOptions.copy(compilerName = "low") Logger.makeScope(optionsManager) { - val chiselResult: ChiselExecutionResult = chisel3.Driver.execute(optionsManager, dutGenerator) + val chiselResult: ChiselExecutionResult = DriverCompatibility.execute(optionsManager, dutGenerator) chiselResult match { case ChiselExecutionSuccess(_, emitted, _) => optionsManager.replConfig = optionsManager.replConfig.copy(firrtlSource = emitted) @@ -245,7 +246,7 @@ object Driver { */ def run[T <: MultiIOModule](dutGen: () => T, cmd: Seq[String]) (testerGen: T => PeekPokeTester[T]): Boolean = { - val circuit = chisel3.Driver.elaborate(dutGen) + val circuit = chisel3.stage.ChiselStage.elaborate(dutGen()) val dut = getTopModule(circuit).asInstanceOf[T] backendVar.withValue(Some(new VerilatorBackend(dut, cmd))) { try { diff --git a/src/main/scala/chisel3/iotesters/DriverCompatibility.scala b/src/main/scala/chisel3/iotesters/DriverCompatibility.scala new file mode 100644 index 00000000..1e899cee --- /dev/null +++ b/src/main/scala/chisel3/iotesters/DriverCompatibility.scala @@ -0,0 +1,288 @@ +package chisel3.iotesters + +import chisel3.internal.firrtl.Circuit +import chisel3.stage.CircuitSerializationAnnotation.FirrtlFileFormat +import chisel3.stage.phases.MaybeFirrtlStage +import chisel3.stage.{ChiselCircuitAnnotation, ChiselGeneratorAnnotation, ChiselOutputFileAnnotation, ChiselStage, CircuitSerializationAnnotation, NoRunFirrtlCompilerAnnotation} +import chisel3.{HasChiselExecutionOptions, RawModule} +import firrtl.annotations.NoTargetAnnotation +import firrtl.options.Viewer.view +import firrtl.options.phases.DeletedWrapper +import firrtl.options.{Dependency, OptionsException, OptionsView, OutputAnnotationFileAnnotation, Phase, PhaseManager, StageError, Unserializable} +import firrtl.stage.phases.DriverCompatibility.TopNameAnnotation +import firrtl.stage.{FirrtlCircuitAnnotation, RunFirrtlTransformAnnotation} +import firrtl.{AnnotationSeq, ExecutionOptionsManager, FirrtlExecutionResult, HasFirrtlOptions} + +/** This provides components of a compatibility wrapper around Chisel's removed `chisel3.Driver`. + * + * Primarily, this object includes [[firrtl.options.Phase Phase]]s that generate [[firrtl.annotations.Annotation]]s + * derived from the deprecated [[firrtl.stage.phases.DriverCompatibility.TopNameAnnotation]]. + */ +object DriverCompatibility { + + private[chisel3] implicit object ChiselExecutionResultView extends OptionsView[ChiselExecutionResult] { + + def view(options: AnnotationSeq): ChiselExecutionResult = { + var chiselCircuit: Option[chisel3.internal.firrtl.Circuit] = None + var chirrtlCircuit: Option[String] = None + + options.foreach { + case a@ChiselCircuitAnnotation(b) => + chiselCircuit = Some(b) + chirrtlCircuit = { + val anno = CircuitSerializationAnnotation(a.circuit, "", FirrtlFileFormat) + Some(anno.getBytes.map(_.toChar).mkString) + } + case _ => + } + + val fResult = firrtl.stage.phases.DriverCompatibility.firrtlResultView(options) + + (chiselCircuit, chirrtlCircuit) match { + case (None, _) => ChiselExecutionFailure("Failed to elaborate Chisel circuit") + case (Some(_), None) => ChiselExecutionFailure("Failed to convert Chisel circuit to FIRRTL") + case (Some(a), Some(b)) => ChiselExecutionSuccess(Some(a), b, Some(fResult)) + } + + } + + } + + def execute(optionsManager: ExecutionOptionsManager with HasChiselExecutionOptions with HasFirrtlOptions, + dut: () => RawModule): ChiselExecutionResult = { + + val annos: AnnotationSeq = + Seq(DriverCompatibility.OptionsManagerAnnotation(optionsManager), ChiselGeneratorAnnotation(dut)) ++ + optionsManager.chiselOptions.toAnnotations ++ + optionsManager.firrtlOptions.toAnnotations ++ + optionsManager.commonOptions.toAnnotations + + val targets = + Seq(Dependency[DriverCompatibility.AddImplicitOutputFile], + Dependency[DriverCompatibility.AddImplicitOutputAnnotationFile], + Dependency[DriverCompatibility.DisableFirrtlStage], + Dependency[ChiselStage], + Dependency[DriverCompatibility.MutateOptionsManager], + Dependency[DriverCompatibility.ReEnableFirrtlStage], + Dependency[DriverCompatibility.FirrtlPreprocessing], + Dependency[chisel3.stage.phases.MaybeFirrtlStage]) + val currentState = + Seq(Dependency[firrtl.stage.phases.DriverCompatibility.AddImplicitFirrtlFile], + Dependency[chisel3.stage.phases.Convert]) + + val phases: Seq[Phase] = new PhaseManager(targets, currentState) { + override val wrappers = Seq(DeletedWrapper(_: Phase)) + }.transformOrder + + val annosx = try { + phases.foldLeft(annos)((a, p) => p.transform(a)) + } catch { + /* ChiselStage and FirrtlStage can throw StageError. Since Driver is not a StageMain, it cannot catch these. While + * Driver is deprecated and removed in 3.2.1+, the Driver catches all errors. + */ + case e: StageError => annos + } + + view[ChiselExecutionResult](annosx) + } + + /** + * This family provides return values from the chisel3 and possibly firrtl compile steps + */ + trait ChiselExecutionResult + + /** + * + * @param circuitOption Optional circuit, has information like circuit name + * @param emitted The emitted Chirrrl text + * @param firrtlResultOption Optional Firrtl result, @see freechipsproject/firrtl for details + */ + case class ChiselExecutionSuccess( + circuitOption: Option[Circuit], + emitted: String, + firrtlResultOption: Option[FirrtlExecutionResult] + ) extends ChiselExecutionResult + + /** + * Getting one of these indicates failure of some sort. + * + * @param message A clue might be provided here. + */ + case class ChiselExecutionFailure(message: String) extends ChiselExecutionResult + + + /** Adds a [[ChiselOutputFileAnnotation]] derived from a [[TopNameAnnotation]] if no [[ChiselOutputFileAnnotation]] + * already exists. If no [[TopNameAnnotation]] exists, then no [[firrtl.stage.OutputFileAnnotation]] is added. ''This is not a + * replacement for [[chisel3.stage.phases.AddImplicitOutputFile AddImplicitOutputFile]] as this only adds an output + * file based on a discovered top name and not on a discovered elaborated circuit.'' Consequently, this will provide + * the correct behavior before a circuit has been elaborated. + * + * @note the output suffix is unspecified and will be set by the underlying [[firrtl.EmittedComponent]] + */ + private[iotesters] class AddImplicitOutputFile extends Phase { + + override def prerequisites = Seq.empty + + override def optionalPrerequisites = Seq.empty + + override def optionalPrerequisiteOf = Seq(Dependency[chisel3.stage.ChiselStage]) + + override def invalidates(a: Phase) = false + + def transform(annotations: AnnotationSeq): AnnotationSeq = { + val hasOutputFile = annotations + .collectFirst { case a: ChiselOutputFileAnnotation => a } + .isDefined + lazy val top = annotations.collectFirst { case TopNameAnnotation(a) => a } + + if (!hasOutputFile && top.isDefined) { + ChiselOutputFileAnnotation(top.get) +: annotations + } else { + annotations + } + } + } + + /** If a [[firrtl.options.OutputAnnotationFileAnnotation]] does not exist, this adds one derived from a + * [[TopNameAnnotation]]. ''This is not a replacement for [[chisel3.stage.phases.AddImplicitOutputAnnotationFile]] as + * this only adds an output annotation file based on a discovered top name.'' Consequently, this will provide the + * correct behavior before a circuit has been elaborated. + * + * @note the output suffix is unspecified and will be set by [[firrtl.options.phases.WriteOutputAnnotations]] + */ + private[iotesters] class AddImplicitOutputAnnotationFile extends Phase { + + override def prerequisites = Seq.empty + + override def optionalPrerequisites = Seq.empty + + override def optionalPrerequisiteOf = Seq(Dependency[chisel3.stage.ChiselStage]) + + override def invalidates(a: Phase) = false + + def transform(annotations: AnnotationSeq): AnnotationSeq = + annotations + .collectFirst { case _: OutputAnnotationFileAnnotation => annotations } + .getOrElse { + val top = annotations.collectFirst { case TopNameAnnotation(a) => a } + if (top.isDefined) { + OutputAnnotationFileAnnotation(top.get) +: annotations + } else { + annotations + } + } + } + + private[iotesters] case object RunFirrtlCompilerAnnotation extends NoTargetAnnotation + + /** Disables the execution of [[firrtl.stage.FirrtlStage]]. This can be used to call [[chisel3.stage.ChiselStage]] and + * guarantee that the FIRRTL compiler will not run. This is necessary for certain `chisel3.Driver` compatibility + * situations where you need to do something between Chisel compilation and FIRRTL compilations, e.g., update a + * mutable data structure. + */ + private[iotesters] class DisableFirrtlStage extends Phase { + + override def prerequisites = Seq.empty + + override def optionalPrerequisites = Seq.empty + + override def optionalPrerequisiteOf = Seq(Dependency[ChiselStage]) + + override def invalidates(a: Phase) = false + + def transform(annotations: AnnotationSeq): AnnotationSeq = annotations + .collectFirst { case NoRunFirrtlCompilerAnnotation => annotations } + .getOrElse { + Seq(RunFirrtlCompilerAnnotation, NoRunFirrtlCompilerAnnotation) ++ annotations + } + } + + private[iotesters] class ReEnableFirrtlStage extends Phase { + + override def prerequisites = Seq(Dependency[DisableFirrtlStage], Dependency[ChiselStage]) + + override def optionalPrerequisites = Seq.empty + + override def optionalPrerequisiteOf = Seq.empty + + override def invalidates(a: Phase) = false + + def transform(annotations: AnnotationSeq): AnnotationSeq = annotations + .collectFirst { case RunFirrtlCompilerAnnotation => + val a: AnnotationSeq = annotations.filter { + case NoRunFirrtlCompilerAnnotation | RunFirrtlCompilerAnnotation => false + case _ => true + } + a + } + .getOrElse { + annotations + } + + } + + private[iotesters] case class OptionsManagerAnnotation( + manager: ExecutionOptionsManager with HasChiselExecutionOptions with HasFirrtlOptions) + extends NoTargetAnnotation with Unserializable + + /** Mutate an input [[firrtl.ExecutionOptionsManager]] based on information encoded in an [[firrtl.AnnotationSeq]]. + * This is intended to be run between [[chisel3.stage.ChiselStage ChiselStage]] and [[firrtl.stage.FirrtlStage]] if + * you want to have backwards compatibility with an [[firrtl.ExecutionOptionsManager]]. + */ + private[iotesters] class MutateOptionsManager extends Phase { + + override def prerequisites = Seq(Dependency[chisel3.stage.ChiselStage]) + + override def optionalPrerequisites = Seq.empty + + override def optionalPrerequisiteOf = Seq(Dependency[ReEnableFirrtlStage]) + + override def invalidates(a: Phase) = false + + def transform(annotations: AnnotationSeq): AnnotationSeq = { + + val optionsManager = annotations + .collectFirst { case OptionsManagerAnnotation(a) => a } + .getOrElse { + throw new OptionsException( + "An OptionsManagerException must exist for Chisel Driver compatibility mode") + } + + val firrtlCircuit = annotations.collectFirst { case FirrtlCircuitAnnotation(a) => a } + optionsManager.firrtlOptions = optionsManager.firrtlOptions.copy( + firrtlCircuit = firrtlCircuit, + annotations = optionsManager.firrtlOptions.annotations ++ annotations, + customTransforms = optionsManager.firrtlOptions.customTransforms ++ + annotations.collect { case RunFirrtlTransformAnnotation(a) => a }) + + annotations + + } + + } + + /** A [[Phase]] that lets us run + * + * @todo a better solution than the current state hack below may be needed + */ + private[iotesters] class FirrtlPreprocessing extends Phase { + + override def prerequisites = Seq(Dependency[ChiselStage], Dependency[MutateOptionsManager], Dependency[ReEnableFirrtlStage]) + + override def optionalPrerequisites = Seq.empty + + override def optionalPrerequisiteOf = Seq(Dependency[MaybeFirrtlStage]) + + override def invalidates(a: Phase) = false + + private val phases = + Seq(new firrtl.stage.phases.DriverCompatibility.AddImplicitOutputFile, + new firrtl.stage.phases.DriverCompatibility.AddImplicitEmitter) + + override def transform(annotations: AnnotationSeq): AnnotationSeq = + phases + .foldLeft(annotations)((a, p) => p.transform(a)) + + } + +} diff --git a/src/main/scala/chisel3/iotesters/FirrtlTerpBackend.scala b/src/main/scala/chisel3/iotesters/FirrtlTerpBackend.scala index 96ee4627..11960d22 100644 --- a/src/main/scala/chisel3/iotesters/FirrtlTerpBackend.scala +++ b/src/main/scala/chisel3/iotesters/FirrtlTerpBackend.scala @@ -1,8 +1,9 @@ // SPDX-License-Identifier: Apache-2.0 package chisel3.iotesters -import chisel3._ +import chisel3.{ChiselExecutionFailure => _, ChiselExecutionResult => _, ChiselExecutionSuccess => _, _} import chisel3.internal.InstanceId +import chisel3.iotesters.DriverCompatibility._ import firrtl.{FirrtlExecutionFailure, FirrtlExecutionSuccess} import firrtl_interpreter._ @@ -134,7 +135,7 @@ private[iotesters] object setupFirrtlTerpBackend { val annos = Driver.filterAnnotations(firrtl.Driver.getAnnotations(optionsManager)) optionsManager.firrtlOptions = optionsManager.firrtlOptions.copy(annotations = annos.toList) - chisel3.Driver.execute(optionsManager, dutGen) match { + DriverCompatibility.execute(optionsManager, dutGen) match { case ChiselExecutionSuccess(Some(circuit), _, Some(firrtlExecutionResult)) => val dut = getTopModule(circuit).asInstanceOf[T] firrtlExecutionResult match { diff --git a/src/main/scala/chisel3/iotesters/IOAccessor.scala b/src/main/scala/chisel3/iotesters/IOAccessor.scala index 1433d1fb..36bdd546 100644 --- a/src/main/scala/chisel3/iotesters/IOAccessor.scala +++ b/src/main/scala/chisel3/iotesters/IOAccessor.scala @@ -3,7 +3,6 @@ package chisel3.iotesters import chisel3._ -import chisel3.core.ActualDirection import chisel3.util._ import chisel3.experimental._ diff --git a/src/main/scala/chisel3/iotesters/IVLBackend.scala b/src/main/scala/chisel3/iotesters/IVLBackend.scala index d7f2b39e..2b71e163 100644 --- a/src/main/scala/chisel3/iotesters/IVLBackend.scala +++ b/src/main/scala/chisel3/iotesters/IVLBackend.scala @@ -5,7 +5,8 @@ import java.io.{File, FileWriter, IOException, Writer} import java.nio.file.{FileAlreadyExistsException, Files, Paths} import java.nio.file.StandardCopyOption.REPLACE_EXISTING -import chisel3.{ChiselExecutionFailure, ChiselExecutionSuccess, Element, MultiIOModule} +import chisel3.{Element, MultiIOModule} +import chisel3.iotesters.DriverCompatibility._ import firrtl.{ChirrtlForm, CircuitState} import firrtl.transforms.BlackBoxTargetDirAnno @@ -127,7 +128,7 @@ private[iotesters] object setupIVLBackend { val dir = new File(optionsManager.targetDirName) // Generate CHIRRTL - chisel3.Driver.execute(optionsManager, dutGen) match { + DriverCompatibility.execute(optionsManager, dutGen) match { case ChiselExecutionSuccess(Some(circuit), emitted, _) => val chirrtl = firrtl.Parser.parse(emitted) diff --git a/src/main/scala/chisel3/iotesters/PeekPokeTesterUtils.scala b/src/main/scala/chisel3/iotesters/PeekPokeTesterUtils.scala index fabd0c5d..bd0bb2f3 100644 --- a/src/main/scala/chisel3/iotesters/PeekPokeTesterUtils.scala +++ b/src/main/scala/chisel3/iotesters/PeekPokeTesterUtils.scala @@ -5,7 +5,6 @@ package chisel3.iotesters import java.io.File import chisel3._ -import chisel3.core.ActualDirection import chisel3.experimental._ import chisel3.internal.InstanceId import chisel3.internal.firrtl.Circuit diff --git a/src/main/scala/chisel3/iotesters/Pokeable.scala b/src/main/scala/chisel3/iotesters/Pokeable.scala index ce2cc725..5e73ffdd 100644 --- a/src/main/scala/chisel3/iotesters/Pokeable.scala +++ b/src/main/scala/chisel3/iotesters/Pokeable.scala @@ -2,8 +2,9 @@ package chisel3.iotesters -import chisel3.Bits -import chisel3.core.{Element, EnumType} +import chisel3.{Bits, Element} +import chisel3.experimental.EnumType + import scala.annotation.implicitNotFound // A typeclass that defines the types we can poke, peek, or expect from diff --git a/src/main/scala/chisel3/iotesters/SteppedHWIOTester.scala b/src/main/scala/chisel3/iotesters/SteppedHWIOTester.scala index 83ad7b45..a2bba3d3 100644 --- a/src/main/scala/chisel3/iotesters/SteppedHWIOTester.scala +++ b/src/main/scala/chisel3/iotesters/SteppedHWIOTester.scala @@ -3,7 +3,7 @@ package chisel3.iotesters import chisel3._ -import chisel3.core.{ActualDirection, DataMirror} +import chisel3.experimental.DataMirror import chisel3.util._ import scala.collection.mutable diff --git a/src/main/scala/chisel3/iotesters/TestErrors.scala b/src/main/scala/chisel3/iotesters/TestErrors.scala index 45843d15..5300599a 100644 --- a/src/main/scala/chisel3/iotesters/TestErrors.scala +++ b/src/main/scala/chisel3/iotesters/TestErrors.scala @@ -4,8 +4,6 @@ package chisel3.iotesters import scala.collection.mutable.ArrayBuffer -import chisel3.core._ - /** Records and reports runtime errors and warnings. */ private[iotesters] class TestErrorLog { def hasErrors: Boolean = errors.exists(_.isFatal) diff --git a/src/main/scala/chisel3/iotesters/VCSBackend.scala b/src/main/scala/chisel3/iotesters/VCSBackend.scala index d2c5277f..067a2ebb 100644 --- a/src/main/scala/chisel3/iotesters/VCSBackend.scala +++ b/src/main/scala/chisel3/iotesters/VCSBackend.scala @@ -5,7 +5,8 @@ import java.io.{File, FileWriter, IOException, Writer} import java.nio.file.{FileAlreadyExistsException, Files, Paths} import java.nio.file.StandardCopyOption.REPLACE_EXISTING -import chisel3.{ChiselExecutionFailure, ChiselExecutionSuccess, Element, MultiIOModule} +import chisel3.{Element, MultiIOModule} +import chisel3.iotesters.DriverCompatibility._ import firrtl.{ChirrtlForm, CircuitState} import firrtl.transforms.BlackBoxTargetDirAnno @@ -141,7 +142,7 @@ private[iotesters] object setupVCSBackend { val dir = new File(optionsManager.targetDirName) // Generate CHIRRTL - chisel3.Driver.execute(optionsManager, dutGen) match { + DriverCompatibility.execute(optionsManager, dutGen) match { case ChiselExecutionSuccess(Some(circuit), emitted, _) => val chirrtl = firrtl.Parser.parse(emitted) diff --git a/src/main/scala/chisel3/iotesters/VSIMBackend.scala b/src/main/scala/chisel3/iotesters/VSIMBackend.scala index ac789af9..df83a24f 100644 --- a/src/main/scala/chisel3/iotesters/VSIMBackend.scala +++ b/src/main/scala/chisel3/iotesters/VSIMBackend.scala @@ -5,7 +5,8 @@ import java.io.{File, FileWriter, IOException, Writer} import java.nio.file.{FileAlreadyExistsException, Files, Paths} import java.nio.file.StandardCopyOption.REPLACE_EXISTING -import chisel3.{ChiselExecutionFailure, ChiselExecutionSuccess, Element, MultiIOModule} +import chisel3.{Element, MultiIOModule} +import chisel3.iotesters.DriverCompatibility._ import firrtl.{ChirrtlForm, CircuitState} import firrtl.transforms.BlackBoxTargetDirAnno @@ -125,7 +126,7 @@ private[iotesters] object setupVSIMBackend { val dir = new File(optionsManager.targetDirName) // Generate CHIRRTL - chisel3.Driver.execute(optionsManager, dutGen) match { + DriverCompatibility.execute(optionsManager, dutGen) match { case ChiselExecutionSuccess(Some(circuit), emitted, _) => val chirrtl = firrtl.Parser.parse(emitted) diff --git a/src/main/scala/chisel3/iotesters/VerilatorBackend.scala b/src/main/scala/chisel3/iotesters/VerilatorBackend.scala index 1dbb83ee..46ad3c57 100644 --- a/src/main/scala/chisel3/iotesters/VerilatorBackend.scala +++ b/src/main/scala/chisel3/iotesters/VerilatorBackend.scala @@ -5,11 +5,11 @@ import java.io._ import java.nio.file.StandardCopyOption.REPLACE_EXISTING import java.nio.file.{FileAlreadyExistsException, Files, Paths} -import chisel3._ import chisel3.experimental.{FixedPoint, Interval} import chisel3.internal.InstanceId +import chisel3.iotesters.DriverCompatibility._ +import chisel3.{ChiselExecutionFailure => _, ChiselExecutionResult => _, ChiselExecutionSuccess => _, _} import firrtl._ -import firrtl.annotations.CircuitName import firrtl.transforms._ /** @@ -219,7 +219,7 @@ private[iotesters] object setupVerilatorBackend { val dir = new File(optionsManager.targetDirName) // Generate CHIRRTL - chisel3.Driver.execute(optionsManager, dutGen) match { + DriverCompatibility.execute(optionsManager, dutGen) match { case ChiselExecutionSuccess(Some(circuit), emitted, _) => val chirrtlSource = firrtlSourceOverride.getOrElse(emitted) @@ -275,7 +275,7 @@ private[iotesters] object setupVerilatorBackend { editCommands = optionsManager.testerOptions.vcsCommandEdits ).! == 0 ) - assert(chisel3.Driver.cppToExe(circuit.name, dir).! == 0) + assert(firrtl.util.BackendCompilationUtilities.cppToExe(circuit.name, dir).! == 0) val command = if(optionsManager.testerOptions.testCmd.nonEmpty) { optionsManager.testerOptions.testCmd diff --git a/src/main/scala/chisel3/iotesters/compatibility.scala b/src/main/scala/chisel3/iotesters/compatibility.scala index d7a88086..b7f89d1b 100644 --- a/src/main/scala/chisel3/iotesters/compatibility.scala +++ b/src/main/scala/chisel3/iotesters/compatibility.scala @@ -2,9 +2,10 @@ package Chisel -import chisel3.{ iotesters => ciot } import java.io.File +import chisel3.{iotesters => ciot} + /** * Provide "Chisel" interface to specific chisel3 internals. */ diff --git a/src/test/scala/chisel3/iotesters/BlackBoxVerilogDeliverySpec.scala b/src/test/scala/chisel3/iotesters/BlackBoxVerilogDeliverySpec.scala index 0d6b3625..66d37eb4 100644 --- a/src/test/scala/chisel3/iotesters/BlackBoxVerilogDeliverySpec.scala +++ b/src/test/scala/chisel3/iotesters/BlackBoxVerilogDeliverySpec.scala @@ -30,7 +30,7 @@ class BBAddTwo extends HasBlackBoxResource { val in = Input(UInt(16.W)) val out = Output(UInt(16.W)) }) - setResource("/AddTwoAddThree.v") + addResource("/AddTwoAddThree.v") } class BBAddThree extends HasBlackBoxResource { @@ -38,7 +38,7 @@ class BBAddThree extends HasBlackBoxResource { val in = Input(UInt(16.W)) val out = Output(UInt(16.W)) }) - setResource("/AddTwoAddThree.v") + addResource("/AddTwoAddThree.v") } class UsesBBAddOne extends Module { diff --git a/src/test/scala/examples/DynamicMemorySearch.scala b/src/test/scala/examples/DynamicMemorySearch.scala index 58ed47ce..98eee9a9 100644 --- a/src/test/scala/examples/DynamicMemorySearch.scala +++ b/src/test/scala/examples/DynamicMemorySearch.scala @@ -20,7 +20,7 @@ class DynamicMemorySearch(val n: Int, val w: Int) extends Module { val memVal = list(index) val over = !io.en && ((memVal === io.data) || (index === (n-1).asUInt)) - when(reset.toBool) { + when(reset.asBool()) { for(i <- 0 until n) { list(i) := 0.U } diff --git a/src/test/scala/examples/GCDUnitTest.scala b/src/test/scala/examples/GCDUnitTest.scala index 5e670664..5df31066 100644 --- a/src/test/scala/examples/GCDUnitTest.scala +++ b/src/test/scala/examples/GCDUnitTest.scala @@ -18,7 +18,7 @@ class GCD extends Module { val x = Reg(UInt(int_width.W)) val y = Reg(UInt(int_width.W)) when (x > y) { x := x - y } - unless (x > y) { y := y - x } + .elsewhen (x <= y) { y := y - x } when (io.e) { x := io.a; y := io.b } io.z := x io.v := y === 0.U diff --git a/src/test/scala/verilator/Verilator.scala b/src/test/scala/verilator/Verilator.scala index 87904379..eafe03ce 100644 --- a/src/test/scala/verilator/Verilator.scala +++ b/src/test/scala/verilator/Verilator.scala @@ -3,7 +3,6 @@ package verilator -import chisel3.Driver.createTestDirectory import chisel3.iotesters.chiselMain import org.scalatest.flatspec.AnyFlatSpec import org.scalatest.matchers.should.Matchers @@ -12,7 +11,7 @@ class VerilatorTest extends AnyFlatSpec with Matchers { // Ensure we run this test in a clean directory to avoid stale files such as black_box_verilog_files.f // See issue #132 - https://github.com/ucb-bar/chisel-testers/issues/132 // and issue #504 - https://github.com/ucb-bar/firrtl/issues/504 - val targetDir = createTestDirectory("ChiselMainVerilatorTest") + val targetDir = firrtl.util.BackendCompilationUtilities.createTestDirectory("ChiselMainVerilatorTest") "The Verilator backend" should "be able to compile the cpp code" in { val args = Array[String]("--v", "--backend",