forked from kstenerud/Musashi
-
Notifications
You must be signed in to change notification settings - Fork 0
/
Copy pathm68k_in.c
10657 lines (8450 loc) · 234 KB
/
m68k_in.c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/*
must fix:
callm
chk
*/
/* ======================================================================== */
/* ========================= LICENSING & COPYRIGHT ======================== */
/* ======================================================================== */
/*
* MUSASHI
* Version 3.32
*
* A portable Motorola M680x0 processor emulation engine.
* Copyright Karl Stenerud. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
/* Special thanks to Bart Trzynadlowski for his insight into the
* undocumented features of this chip:
*
* http://dynarec.com/~bart/files/68knotes.txt
*/
/* Input file for m68kmake
* -----------------------
*
* All sections begin with 80 X's in a row followed by an end-of-line
* sequence.
* After this, m68kmake will expect to find one of the following section
* identifiers:
* M68KMAKE_PROTOTYPE_HEADER - header for opcode handler prototypes
* M68KMAKE_PROTOTYPE_FOOTER - footer for opcode handler prototypes
* M68KMAKE_TABLE_HEADER - header for opcode handler jumptable
* M68KMAKE_TABLE_FOOTER - footer for opcode handler jumptable
* M68KMAKE_TABLE_BODY - the table itself
* M68KMAKE_OPCODE_HANDLER_HEADER - header for opcode handler implementation
* M68KMAKE_OPCODE_HANDLER_FOOTER - footer for opcode handler implementation
* M68KMAKE_OPCODE_HANDLER_BODY - body section for opcode handler implementation
*
* NOTE: M68KMAKE_OPCODE_HANDLER_BODY must be last in the file and
* M68KMAKE_TABLE_BODY must be second last in the file.
*
* The M68KMAKE_OPHANDLER_BODY section contains the opcode handler
* primitives themselves. Each opcode handler begins with:
* M68KMAKE_OP(A, B, C, D)
*
* where A is the opcode handler name, B is the size of the operation,
* C denotes any special processing mode, and D denotes a specific
* addressing mode.
* For C and D where nothing is specified, use "."
*
* Example:
* M68KMAKE_OP(abcd, 8, rr, .) abcd, size 8, register to register, default EA
* M68KMAKE_OP(abcd, 8, mm, ax7) abcd, size 8, memory to memory, register X is A7
* M68KMAKE_OP(tst, 16, ., pcix) tst, size 16, PCIX addressing
*
* All opcode handler primitives end with a closing curly brace "}" at column 1
*
* NOTE: Do not place a M68KMAKE_OP() directive inside the opcode handler,
* and do not put a closing curly brace at column 1 unless it is
* marking the end of the handler!
*
* Inside the handler, m68kmake will recognize M68KMAKE_GET_OPER_xx_xx,
* M68KMAKE_GET_EA_xx_xx, and M68KMAKE_CC directives, and create multiple
* opcode handlers to handle variations in the opcode handler.
* Note: M68KMAKE_CC will only be interpreted in condition code opcodes.
* As well, M68KMAKE_GET_EA_xx_xx and M68KMAKE_GET_OPER_xx_xx will only
* be interpreted on instructions where the corresponding table entry
* specifies multiple effective addressing modes.
* Example:
* clr 32 . . 0100001010...... A+-DXWL... U U U 12 6 4
*
* This table entry says that the clr.l opcde has 7 variations (A+-DXWL).
* It is run in user or supervisor mode for all CPUs, and uses 12 cycles for
* 68000, 6 cycles for 68010, and 4 cycles for 68020.
*/
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
M68KMAKE_PROTOTYPE_HEADER
#ifndef M68KOPS__HEADER
#define M68KOPS__HEADER
/* ======================================================================== */
/* ============================ OPCODE HANDLERS =========================== */
/* ======================================================================== */
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
M68KMAKE_PROTOTYPE_FOOTER
/* Build the opcode handler table */
void m68ki_build_opcode_table(void);
extern void (*m68ki_instruction_jump_table[0x10000])(void); /* opcode handler jump table */
extern unsigned char m68ki_cycles[][0x10000];
/* ======================================================================== */
/* ============================== END OF FILE ============================= */
/* ======================================================================== */
#endif /* M68KOPS__HEADER */
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
M68KMAKE_TABLE_HEADER
/* ======================================================================== */
/* ========================= OPCODE TABLE BUILDER ========================= */
/* ======================================================================== */
#include <stdio.h>
#include "m68kops.h"
#define NUM_CPU_TYPES 5
void (*m68ki_instruction_jump_table[0x10000])(void); /* opcode handler jump table */
unsigned char m68ki_cycles[NUM_CPU_TYPES][0x10000]; /* Cycles used by CPU type */
/* This is used to generate the opcode handler jump table */
typedef struct
{
void (*opcode_handler)(void); /* handler function */
unsigned int mask; /* mask on opcode */
unsigned int match; /* what to match after masking */
unsigned char cycles[NUM_CPU_TYPES]; /* cycles each cpu type takes */
} opcode_handler_struct;
/* Opcode handler table */
static const opcode_handler_struct m68k_opcode_handler_table[] =
{
/* function mask match 000 010 020 040 */
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
M68KMAKE_TABLE_FOOTER
{0, 0, 0, {0, 0, 0, 0, 0}}
};
/* Build the opcode handler jump table */
void m68ki_build_opcode_table(void)
{
const opcode_handler_struct *ostruct;
int cycle_cost;
int instr;
int i;
int j;
int k;
for(i = 0; i < 0x10000; i++)
{
/* default to illegal */
m68ki_instruction_jump_table[i] = m68k_op_illegal;
for(k=0;k<NUM_CPU_TYPES;k++)
m68ki_cycles[k][i] = 0;
}
ostruct = m68k_opcode_handler_table;
while(ostruct->mask != 0xff00)
{
for(i = 0;i < 0x10000;i++)
{
if((i & ostruct->mask) == ostruct->match)
{
m68ki_instruction_jump_table[i] = ostruct->opcode_handler;
for(k=0;k<NUM_CPU_TYPES;k++)
m68ki_cycles[k][i] = ostruct->cycles[k];
}
}
ostruct++;
}
while(ostruct->mask == 0xff00)
{
for(i = 0;i <= 0xff;i++)
{
m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler;
for(k=0;k<NUM_CPU_TYPES;k++)
m68ki_cycles[k][ostruct->match | i] = ostruct->cycles[k];
}
ostruct++;
}
while(ostruct->mask == 0xf1f8)
{
for(i = 0;i < 8;i++)
{
for(j = 0;j < 8;j++)
{
instr = ostruct->match | (i << 9) | j;
m68ki_instruction_jump_table[instr] = ostruct->opcode_handler;
for(k=0;k<NUM_CPU_TYPES;k++)
m68ki_cycles[k][instr] = ostruct->cycles[k];
// For all shift operations with known shift distance (encoded in instruction word)
if((instr & 0xf000) == 0xe000 && (!(instr & 0x20)))
{
// On the 68000 and 68010 shift distance affect execution time.
// Add the cycle cost of shifting; 2 times the shift distance
cycle_cost = ((((i-1)&7)+1)<<1);
m68ki_cycles[0][instr] += cycle_cost;
m68ki_cycles[1][instr] += cycle_cost;
// On the 68020 shift distance does not affect execution time
m68ki_cycles[2][instr] += 0;
}
}
}
ostruct++;
}
while(ostruct->mask == 0xfff0)
{
for(i = 0;i <= 0x0f;i++)
{
m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler;
for(k=0;k<NUM_CPU_TYPES;k++)
m68ki_cycles[k][ostruct->match | i] = ostruct->cycles[k];
}
ostruct++;
}
while(ostruct->mask == 0xf1ff)
{
for(i = 0;i <= 0x07;i++)
{
m68ki_instruction_jump_table[ostruct->match | (i << 9)] = ostruct->opcode_handler;
for(k=0;k<NUM_CPU_TYPES;k++)
m68ki_cycles[k][ostruct->match | (i << 9)] = ostruct->cycles[k];
}
ostruct++;
}
while(ostruct->mask == 0xfff8)
{
for(i = 0;i <= 0x07;i++)
{
m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler;
for(k=0;k<NUM_CPU_TYPES;k++)
m68ki_cycles[k][ostruct->match | i] = ostruct->cycles[k];
}
ostruct++;
}
while(ostruct->mask == 0xffff)
{
m68ki_instruction_jump_table[ostruct->match] = ostruct->opcode_handler;
for(k=0;k<NUM_CPU_TYPES;k++)
m68ki_cycles[k][ostruct->match] = ostruct->cycles[k];
ostruct++;
}
}
/* ======================================================================== */
/* ============================== END OF FILE ============================= */
/* ======================================================================== */
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
M68KMAKE_OPCODE_HANDLER_HEADER
#include <stdio.h>
#include "m68kcpu.h"
extern void m68040_fpu_op0(void);
extern void m68040_fpu_op1(void);
extern void m68881_mmu_ops(void);
/* ======================================================================== */
/* ========================= INSTRUCTION HANDLERS ========================= */
/* ======================================================================== */
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
M68KMAKE_OPCODE_HANDLER_FOOTER
/* ======================================================================== */
/* ============================== END OF FILE ============================= */
/* ======================================================================== */
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
M68KMAKE_TABLE_BODY
The following table is arranged as follows:
name: Opcode mnemonic
size: Operation size
spec proc: Special processing mode:
.: normal
s: static operand
r: register operand
rr: register to register
mm: memory to memory
er: effective address to register
re: register to effective address
dd: data register to data register
da: data register to address register
aa: address register to address register
cr: control register to register
rc: register to control register
toc: to condition code register
tos: to status register
tou: to user stack pointer
frc: from condition code register
frs: from status register
fru: from user stack pointer
* for move.x, the special processing mode is a specific
destination effective addressing mode.
spec ea: Specific effective addressing mode:
.: normal
i: immediate
d: data register
a: address register
ai: address register indirect
pi: address register indirect with postincrement
pd: address register indirect with predecrement
di: address register indirect with displacement
ix: address register indirect with index
aw: absolute word address
al: absolute long address
pcdi: program counter relative with displacement
pcix: program counter relative with index
a7: register specified in instruction is A7
ax7: register field X of instruction is A7
ay7: register field Y of instruction is A7
axy7: register fields X and Y of instruction are A7
bit pattern: Pattern to recognize this opcode. "." means don't care.
allowed ea: List of allowed addressing modes:
.: not present
A: address register indirect
+: ARI (address register indirect) with postincrement
-: ARI with predecrement
D: ARI with displacement
X: ARI with index
W: absolute word address
L: absolute long address
d: program counter indirect with displacement
x: program counter indirect with index
I: immediate
mode: CPU operating mode for each cpu type. U = user or supervisor,
S = supervisor only, "." = opcode not present.
cpu cycles: Base number of cycles required to execute this opcode on the
specified CPU type.
Use "." if CPU does not have this opcode.
spec spec allowed ea mode cpu cycles
name size proc ea bit pattern A+-DXWLdxI 0 1 2 3 4 000 010 020 030 040 comments
====== ==== ==== ==== ================ ========== = = = = = === === === === === =============
M68KMAKE_TABLE_START
1010 0 . . 1010............ .......... U U U U U 4 4 4 4 4
1111 0 . . 1111............ .......... U U U U U 4 4 4 4 4
040fpu0 32 . . 11110010........ .......... . . . . U . . . . 0
040fpu1 32 . . 11110011........ .......... . . . . U . . . . 0
abcd 8 rr . 1100...100000... .......... U U U U U 6 6 4 4 4
abcd 8 mm ax7 1100111100001... .......... U U U U U 18 18 16 16 16
abcd 8 mm ay7 1100...100001111 .......... U U U U U 18 18 16 16 16
abcd 8 mm axy7 1100111100001111 .......... U U U U U 18 18 16 16 16
abcd 8 mm . 1100...100001... .......... U U U U U 18 18 16 16 16
add 8 er d 1101...000000... .......... U U U U U 4 4 2 2 2
add 8 er . 1101...000...... A+-DXWLdxI U U U U U 4 4 2 2 2
add 16 er d 1101...001000... .......... U U U U U 4 4 2 2 2
add 16 er a 1101...001001... .......... U U U U U 4 4 2 2 2
add 16 er . 1101...001...... A+-DXWLdxI U U U U U 4 4 2 2 2
add 32 er d 1101...010000... .......... U U U U U 6 6 2 2 2
add 32 er a 1101...010001... .......... U U U U U 6 6 2 2 2
add 32 er . 1101...010...... A+-DXWLdxI U U U U U 6 6 2 2 2
add 8 re . 1101...100...... A+-DXWL... U U U U U 8 8 4 4 4
add 16 re . 1101...101...... A+-DXWL... U U U U U 8 8 4 4 4
add 32 re . 1101...110...... A+-DXWL... U U U U U 12 12 4 4 4
adda 16 . d 1101...011000... .......... U U U U U 8 8 2 2 2
adda 16 . a 1101...011001... .......... U U U U U 8 8 2 2 2
adda 16 . . 1101...011...... A+-DXWLdxI U U U U U 8 8 2 2 2
adda 32 . d 1101...111000... .......... U U U U U 6 6 2 2 2
adda 32 . a 1101...111001... .......... U U U U U 6 6 2 2 2
adda 32 . . 1101...111...... A+-DXWLdxI U U U U U 6 6 2 2 2
addi 8 . d 0000011000000... .......... U U U U U 8 8 2 2 2
addi 8 . . 0000011000...... A+-DXWL... U U U U U 12 12 4 4 4
addi 16 . d 0000011001000... .......... U U U U U 8 8 2 2 2
addi 16 . . 0000011001...... A+-DXWL... U U U U U 12 12 4 4 4
addi 32 . d 0000011010000... .......... U U U U U 16 14 2 2 2
addi 32 . . 0000011010...... A+-DXWL... U U U U U 20 20 4 4 4
addq 8 . d 0101...000000... .......... U U U U U 4 4 2 2 2
addq 8 . . 0101...000...... A+-DXWL... U U U U U 8 8 4 4 4
addq 16 . d 0101...001000... .......... U U U U U 4 4 2 2 2
addq 16 . a 0101...001001... .......... U U U U U 4 4 2 2 2
addq 16 . . 0101...001...... A+-DXWL... U U U U U 8 8 4 4 4
addq 32 . d 0101...010000... .......... U U U U U 8 8 2 2 2
addq 32 . a 0101...010001... .......... U U U U U 8 8 2 2 2
addq 32 . . 0101...010...... A+-DXWL... U U U U U 12 12 4 4 4
addx 8 rr . 1101...100000... .......... U U U U U 4 4 2 2 2
addx 16 rr . 1101...101000... .......... U U U U U 4 4 2 2 2
addx 32 rr . 1101...110000... .......... U U U U U 8 6 2 2 2
addx 8 mm ax7 1101111100001... .......... U U U U U 18 18 12 12 12
addx 8 mm ay7 1101...100001111 .......... U U U U U 18 18 12 12 12
addx 8 mm axy7 1101111100001111 .......... U U U U U 18 18 12 12 12
addx 8 mm . 1101...100001... .......... U U U U U 18 18 12 12 12
addx 16 mm . 1101...101001... .......... U U U U U 18 18 12 12 12
addx 32 mm . 1101...110001... .......... U U U U U 30 30 12 12 12
and 8 er d 1100...000000... .......... U U U U U 4 4 2 2 2
and 8 er . 1100...000...... A+-DXWLdxI U U U U U 4 4 2 2 2
and 16 er d 1100...001000... .......... U U U U U 4 4 2 2 2
and 16 er . 1100...001...... A+-DXWLdxI U U U U U 4 4 2 2 2
and 32 er d 1100...010000... .......... U U U U U 6 6 2 2 2
and 32 er . 1100...010...... A+-DXWLdxI U U U U U 6 6 2 2 2
and 8 re . 1100...100...... A+-DXWL... U U U U U 8 8 4 4 4
and 16 re . 1100...101...... A+-DXWL... U U U U U 8 8 4 4 4
and 32 re . 1100...110...... A+-DXWL... U U U U U 12 12 4 4 4
andi 16 toc . 0000001000111100 .......... U U U U U 20 16 12 12 12
andi 16 tos . 0000001001111100 .......... S S S S S 20 16 12 12 12
andi 8 . d 0000001000000... .......... U U U U U 8 8 2 2 2
andi 8 . . 0000001000...... A+-DXWL... U U U U U 12 12 4 4 4
andi 16 . d 0000001001000... .......... U U U U U 8 8 2 2 2
andi 16 . . 0000001001...... A+-DXWL... U U U U U 12 12 4 4 4
andi 32 . d 0000001010000... .......... U U U U U 14 14 2 2 2
andi 32 . . 0000001010...... A+-DXWL... U U U U U 20 20 4 4 4
asr 8 s . 1110...000000... .......... U U U U U 6 6 6 6 6
asr 16 s . 1110...001000... .......... U U U U U 6 6 6 6 6
asr 32 s . 1110...010000... .......... U U U U U 8 8 6 6 6
asr 8 r . 1110...000100... .......... U U U U U 6 6 6 6 6
asr 16 r . 1110...001100... .......... U U U U U 6 6 6 6 6
asr 32 r . 1110...010100... .......... U U U U U 8 8 6 6 6
asr 16 . . 1110000011...... A+-DXWL... U U U U U 8 8 5 5 5
asl 8 s . 1110...100000... .......... U U U U U 6 6 8 8 8
asl 16 s . 1110...101000... .......... U U U U U 6 6 8 8 8
asl 32 s . 1110...110000... .......... U U U U U 8 8 8 8 8
asl 8 r . 1110...100100... .......... U U U U U 6 6 8 8 8
asl 16 r . 1110...101100... .......... U U U U U 6 6 8 8 8
asl 32 r . 1110...110100... .......... U U U U U 8 8 8 8 8
asl 16 . . 1110000111...... A+-DXWL... U U U U U 8 8 6 6 6
bcc 8 . . 0110............ .......... U U U U U 10 10 6 6 6
bcc 16 . . 0110....00000000 .......... U U U U U 10 10 6 6 6
bcc 32 . . 0110....11111111 .......... U U U U U 10 10 6 6 6
bchg 8 r . 0000...101...... A+-DXWL... U U U U U 8 8 4 4 4
bchg 32 r d 0000...101000... .......... U U U U U 8 8 4 4 4
bchg 8 s . 0000100001...... A+-DXWL... U U U U U 12 12 4 4 4
bchg 32 s d 0000100001000... .......... U U U U U 12 12 4 4 4
bclr 8 r . 0000...110...... A+-DXWL... U U U U U 8 10 4 4 4
bclr 32 r d 0000...110000... .......... U U U U U 10 10 4 4 4
bclr 8 s . 0000100010...... A+-DXWL... U U U U U 12 12 4 4 4
bclr 32 s d 0000100010000... .......... U U U U U 14 14 4 4 4
bfchg 32 . d 1110101011000... .......... . . U U U . . 12 12 12 timing not quite correct
bfchg 32 . . 1110101011...... A..DXWL... . . U U U . . 20 20 20
bfclr 32 . d 1110110011000... .......... . . U U U . . 12 12 12
bfclr 32 . . 1110110011...... A..DXWL... . . U U U . . 20 20 20
bfexts 32 . d 1110101111000... .......... . . U U U . . 8 8 8
bfexts 32 . . 1110101111...... A..DXWLdx. . . U U U . . 15 15 15
bfextu 32 . d 1110100111000... .......... . . U U U . . 8 8 8
bfextu 32 . . 1110100111...... A..DXWLdx. . . U U U . . 15 15 15
bfffo 32 . d 1110110111000... .......... . . U U U . . 18 18 18
bfffo 32 . . 1110110111...... A..DXWLdx. . . U U U . . 28 28 28
bfins 32 . d 1110111111000... .......... . . U U U . . 10 10 10
bfins 32 . . 1110111111...... A..DXWL... . . U U U . . 17 17 17
bfset 32 . d 1110111011000... .......... . . U U U . . 12 12 12
bfset 32 . . 1110111011...... A..DXWL... . . U U U . . 20 20 20
bftst 32 . d 1110100011000... .......... . . U U U . . 6 6 6
bftst 32 . . 1110100011...... A..DXWLdx. . . U U U . . 13 13 13
bkpt 0 . . 0100100001001... .......... . U U U U . 10 10 10 10
bra 8 . . 01100000........ .......... U U U U U 10 10 10 10 10
bra 16 . . 0110000000000000 .......... U U U U U 10 10 10 10 10
bra 32 . . 0110000011111111 .......... U U U U U 10 10 10 10 10
bset 32 r d 0000...111000... .......... U U U U U 8 8 4 4 4
bset 8 r . 0000...111...... A+-DXWL... U U U U U 8 8 4 4 4
bset 8 s . 0000100011...... A+-DXWL... U U U U U 12 12 4 4 4
bset 32 s d 0000100011000... .......... U U U U U 12 12 4 4 4
bsr 8 . . 01100001........ .......... U U U U U 18 18 7 7 7
bsr 16 . . 0110000100000000 .......... U U U U U 18 18 7 7 7
bsr 32 . . 0110000111111111 .......... U U U U U 18 18 7 7 7
btst 8 r . 0000...100...... A+-DXWLdxI U U U U U 4 4 4 4 4
btst 32 r d 0000...100000... .......... U U U U U 6 6 4 4 4
btst 8 s . 0000100000...... A+-DXWLdx. U U U U U 8 8 4 4 4
btst 32 s d 0000100000000... .......... U U U U U 10 10 4 4 4
callm 32 . . 0000011011...... A..DXWLdx. . . U U U . . 60 60 60 not properly emulated
cas 8 . . 0000101011...... A+-DXWL... . . U U U . . 12 12 12
cas 16 . . 0000110011...... A+-DXWL... . . U U U . . 12 12 12
cas 32 . . 0000111011...... A+-DXWL... . . U U U . . 12 12 12
cas2 16 . . 0000110011111100 .......... . . U U U . . 12 12 12
cas2 32 . . 0000111011111100 .......... . . U U U . . 12 12 12
chk 16 . d 0100...110000... .......... U U U U U 10 8 8 8 8
chk 16 . . 0100...110...... A+-DXWLdxI U U U U U 10 8 8 8 8
chk 32 . d 0100...100000... .......... . . U U U . . 8 8 8
chk 32 . . 0100...100...... A+-DXWLdxI . . U U U . . 8 8 8
chk2cmp2 8 . pcdi 0000000011111010 .......... . . U U U . . 23 23 23
chk2cmp2 8 . pcix 0000000011111011 .......... . . U U U . . 23 23 23
chk2cmp2 8 . . 0000000011...... A..DXWL... . . U U U . . 18 18 18
chk2cmp2 16 . pcdi 0000001011111010 .......... . . U U U . . 23 23 23
chk2cmp2 16 . pcix 0000001011111011 .......... . . U U U . . 23 23 23
chk2cmp2 16 . . 0000001011...... A..DXWL... . . U U U . . 18 18 18
chk2cmp2 32 . pcdi 0000010011111010 .......... . . U U U . . 23 23 23
chk2cmp2 32 . pcix 0000010011111011 .......... . . U U U . . 23 23 23
chk2cmp2 32 . . 0000010011...... A..DXWL... . . U U U . . 18 18 18
clr 8 . d 0100001000000... .......... U U U U U 4 4 2 2 2
clr 8 . . 0100001000...... A+-DXWL... U U U U U 8 4 4 4 4
clr 16 . d 0100001001000... .......... U U U U U 4 4 2 2 2
clr 16 . . 0100001001...... A+-DXWL... U U U U U 8 4 4 4 4
clr 32 . d 0100001010000... .......... U U U U U 6 6 2 2 2
clr 32 . . 0100001010...... A+-DXWL... U U U U U 12 6 4 4 4
cmp 8 . d 1011...000000... .......... U U U U U 4 4 2 2 2
cmp 8 . . 1011...000...... A+-DXWLdxI U U U U U 4 4 2 2 2
cmp 16 . d 1011...001000... .......... U U U U U 4 4 2 2 2
cmp 16 . a 1011...001001... .......... U U U U U 4 4 2 2 2
cmp 16 . . 1011...001...... A+-DXWLdxI U U U U U 4 4 2 2 2
cmp 32 . d 1011...010000... .......... U U U U U 6 6 2 2 2
cmp 32 . a 1011...010001... .......... U U U U U 6 6 2 2 2
cmp 32 . . 1011...010...... A+-DXWLdxI U U U U U 6 6 2 2 2
cmpa 16 . d 1011...011000... .......... U U U U U 6 6 4 4 4
cmpa 16 . a 1011...011001... .......... U U U U U 6 6 4 4 4
cmpa 16 . . 1011...011...... A+-DXWLdxI U U U U U 6 6 4 4 4
cmpa 32 . d 1011...111000... .......... U U U U U 6 6 4 4 4
cmpa 32 . a 1011...111001... .......... U U U U U 6 6 4 4 4
cmpa 32 . . 1011...111...... A+-DXWLdxI U U U U U 6 6 4 4 4
cmpi 8 . d 0000110000000... .......... U U U U U 8 8 2 2 2
cmpi 8 . . 0000110000...... A+-DXWL... U U U U U 8 8 2 2 2
cmpi 8 . pcdi 0000110000111010 .......... . . U U U . . 7 7 7
cmpi 8 . pcix 0000110000111011 .......... . . U U U . . 9 9 9
cmpi 16 . d 0000110001000... .......... U U U U U 8 8 2 2 2
cmpi 16 . . 0000110001...... A+-DXWL... U U U U U 8 8 2 2 2
cmpi 16 . pcdi 0000110001111010 .......... . . U U U . . 7 7 7
cmpi 16 . pcix 0000110001111011 .......... . . U U U . . 9 9 9
cmpi 32 . d 0000110010000... .......... U U U U U 14 12 2 2 2
cmpi 32 . . 0000110010...... A+-DXWL... U U U U U 12 12 2 2 2
cmpi 32 . pcdi 0000110010111010 .......... . . U U U . . 7 7 7
cmpi 32 . pcix 0000110010111011 .......... . . U U U . . 9 9 9
cmpm 8 . ax7 1011111100001... .......... U U U U U 12 12 9 9 9
cmpm 8 . ay7 1011...100001111 .......... U U U U U 12 12 9 9 9
cmpm 8 . axy7 1011111100001111 .......... U U U U U 12 12 9 9 9
cmpm 8 . . 1011...100001... .......... U U U U U 12 12 9 9 9
cmpm 16 . . 1011...101001... .......... U U U U U 12 12 9 9 9
cmpm 32 . . 1011...110001... .......... U U U U U 20 20 9 9 9
cpbcc 32 . . 1111...01....... .......... . . U U . . . 4 4 . unemulated
cpdbcc 32 . . 1111...001001... .......... . . U U . . . 4 4 . unemulated
cpgen 32 . . 1111...000...... .......... . . U U . . . 4 4 . unemulated
cpscc 32 . . 1111...001...... .......... . . U U . . . 4 4 . unemulated
cptrapcc 32 . . 1111...001111... .......... . . U U . . . 4 4 . unemulated
dbt 16 . . 0101000011001... .......... U U U U U 12 12 6 6 6
dbf 16 . . 0101000111001... .......... U U U U U 12 12 6 6 6
dbcc 16 . . 0101....11001... .......... U U U U U 12 12 6 6 6
divs 16 . d 1000...111000... .......... U U U U U 158 122 56 56 56
divs 16 . . 1000...111...... A+-DXWLdxI U U U U U 158 122 56 56 56
divu 16 . d 1000...011000... .......... U U U U U 140 108 44 44 44
divu 16 . . 1000...011...... A+-DXWLdxI U U U U U 140 108 44 44 44
divl 32 . d 0100110001000... .......... . . U U U . . 84 84 84
divl 32 . . 0100110001...... A+-DXWLdxI . . U U U . . 84 84 84
eor 8 . d 1011...100000... .......... U U U U U 4 4 2 2 2
eor 8 . . 1011...100...... A+-DXWL... U U U U U 8 8 4 4 4
eor 16 . d 1011...101000... .......... U U U U U 4 4 2 2 2
eor 16 . . 1011...101...... A+-DXWL... U U U U U 8 8 4 4 4
eor 32 . d 1011...110000... .......... U U U U U 8 6 2 2 2
eor 32 . . 1011...110...... A+-DXWL... U U U U U 12 12 4 4 4
eori 16 toc . 0000101000111100 .......... U U U U U 20 16 12 12 12
eori 16 tos . 0000101001111100 .......... S S S S S 20 16 12 12 12
eori 8 . d 0000101000000... .......... U U U U U 8 8 2 2 2
eori 8 . . 0000101000...... A+-DXWL... U U U U U 12 12 4 4 4
eori 16 . d 0000101001000... .......... U U U U U 8 8 2 2 2
eori 16 . . 0000101001...... A+-DXWL... U U U U U 12 12 4 4 4
eori 32 . d 0000101010000... .......... U U U U U 16 14 2 2 2
eori 32 . . 0000101010...... A+-DXWL... U U U U U 20 20 4 4 4
exg 32 dd . 1100...101000... .......... U U U U U 6 6 2 2 2
exg 32 aa . 1100...101001... .......... U U U U U 6 6 2 2 2
exg 32 da . 1100...110001... .......... U U U U U 6 6 2 2 2
ext 16 . . 0100100010000... .......... U U U U U 4 4 4 4 4
ext 32 . . 0100100011000... .......... U U U U U 4 4 4 4 4
extb 32 . . 0100100111000... .......... . . U U U . . 4 4 4
illegal 0 . . 0100101011111100 .......... U U U U U 4 4 4 4 4
jmp 32 . . 0100111011...... A..DXWLdx. U U U U U 4 4 0 0 0
jsr 32 . . 0100111010...... A..DXWLdx. U U U U U 12 12 0 0 0
lea 32 . . 0100...111...... A..DXWLdx. U U U U U 0 0 2 2 2
link 16 . a7 0100111001010111 .......... U U U U U 16 16 5 5 5
link 16 . . 0100111001010... .......... U U U U U 16 16 5 5 5
link 32 . a7 0100100000001111 .......... . . U U U . . 6 6 6
link 32 . . 0100100000001... .......... . . U U U . . 6 6 6
lsr 8 s . 1110...000001... .......... U U U U U 6 6 4 4 4
lsr 16 s . 1110...001001... .......... U U U U U 6 6 4 4 4
lsr 32 s . 1110...010001... .......... U U U U U 8 8 4 4 4
lsr 8 r . 1110...000101... .......... U U U U U 6 6 6 6 6
lsr 16 r . 1110...001101... .......... U U U U U 6 6 6 6 6
lsr 32 r . 1110...010101... .......... U U U U U 8 8 6 6 6
lsr 16 . . 1110001011...... A+-DXWL... U U U U U 8 8 5 5 5
lsl 8 s . 1110...100001... .......... U U U U U 6 6 4 4 4
lsl 16 s . 1110...101001... .......... U U U U U 6 6 4 4 4
lsl 32 s . 1110...110001... .......... U U U U U 8 8 4 4 4
lsl 8 r . 1110...100101... .......... U U U U U 6 6 6 6 6
lsl 16 r . 1110...101101... .......... U U U U U 6 6 6 6 6
lsl 32 r . 1110...110101... .......... U U U U U 8 8 6 6 6
lsl 16 . . 1110001111...... A+-DXWL... U U U U U 8 8 5 5 5
move 8 d d 0001...000000... .......... U U U U U 4 4 2 2 2
move 8 d . 0001...000...... A+-DXWLdxI U U U U U 4 4 2 2 2
move 8 ai d 0001...010000... .......... U U U U U 8 8 4 4 4
move 8 ai . 0001...010...... A+-DXWLdxI U U U U U 8 8 4 4 4
move 8 pi d 0001...011000... .......... U U U U U 8 8 4 4 4
move 8 pi . 0001...011...... A+-DXWLdxI U U U U U 8 8 4 4 4
move 8 pi7 d 0001111011000... .......... U U U U U 8 8 4 4 4
move 8 pi7 . 0001111011...... A+-DXWLdxI U U U U U 8 8 4 4 4
move 8 pd d 0001...100000... .......... U U U U U 8 8 5 5 5
move 8 pd . 0001...100...... A+-DXWLdxI U U U U U 8 8 5 5 5
move 8 pd7 d 0001111100000... .......... U U U U U 8 8 5 5 5
move 8 pd7 . 0001111100...... A+-DXWLdxI U U U U U 8 8 5 5 5
move 8 di d 0001...101000... .......... U U U U U 12 12 5 5 5
move 8 di . 0001...101...... A+-DXWLdxI U U U U U 12 12 5 5 5
move 8 ix d 0001...110000... .......... U U U U U 14 14 7 7 7
move 8 ix . 0001...110...... A+-DXWLdxI U U U U U 14 14 7 7 7
move 8 aw d 0001000111000... .......... U U U U U 12 12 4 4 4
move 8 aw . 0001000111...... A+-DXWLdxI U U U U U 12 12 4 4 4
move 8 al d 0001001111000... .......... U U U U U 16 16 6 6 6
move 8 al . 0001001111...... A+-DXWLdxI U U U U U 16 16 6 6 6
move 16 d d 0011...000000... .......... U U U U U 4 4 2 2 2
move 16 d a 0011...000001... .......... U U U U U 4 4 2 2 2
move 16 d . 0011...000...... A+-DXWLdxI U U U U U 4 4 2 2 2
move 16 ai d 0011...010000... .......... U U U U U 8 8 4 4 4
move 16 ai a 0011...010001... .......... U U U U U 8 8 4 4 4
move 16 ai . 0011...010...... A+-DXWLdxI U U U U U 8 8 4 4 4
move 16 pi d 0011...011000... .......... U U U U U 8 8 4 4 4
move 16 pi a 0011...011001... .......... U U U U U 8 8 4 4 4
move 16 pi . 0011...011...... A+-DXWLdxI U U U U U 8 8 4 4 4
move 16 pd d 0011...100000... .......... U U U U U 8 8 5 5 5
move 16 pd a 0011...100001... .......... U U U U U 8 8 5 5 5
move 16 pd . 0011...100...... A+-DXWLdxI U U U U U 8 8 5 5 5
move 16 di d 0011...101000... .......... U U U U U 12 12 5 5 5
move 16 di a 0011...101001... .......... U U U U U 12 12 5 5 5
move 16 di . 0011...101...... A+-DXWLdxI U U U U U 12 12 5 5 5
move 16 ix d 0011...110000... .......... U U U U U 14 14 7 7 7
move 16 ix a 0011...110001... .......... U U U U U 14 14 7 7 7
move 16 ix . 0011...110...... A+-DXWLdxI U U U U U 14 14 7 7 7
move 16 aw d 0011000111000... .......... U U U U U 12 12 4 4 4
move 16 aw a 0011000111001... .......... U U U U U 12 12 4 4 4
move 16 aw . 0011000111...... A+-DXWLdxI U U U U U 12 12 4 4 4
move 16 al d 0011001111000... .......... U U U U U 16 16 6 6 6
move 16 al a 0011001111001... .......... U U U U U 16 16 6 6 6
move 16 al . 0011001111...... A+-DXWLdxI U U U U U 16 16 6 6 6
move 32 d d 0010...000000... .......... U U U U U 4 4 2 2 2
move 32 d a 0010...000001... .......... U U U U U 4 4 2 2 2
move 32 d . 0010...000...... A+-DXWLdxI U U U U U 4 4 2 2 2
move 32 ai d 0010...010000... .......... U U U U U 12 12 4 4 4
move 32 ai a 0010...010001... .......... U U U U U 12 12 4 4 4
move 32 ai . 0010...010...... A+-DXWLdxI U U U U U 12 12 4 4 4
move 32 pi d 0010...011000... .......... U U U U U 12 12 4 4 4
move 32 pi a 0010...011001... .......... U U U U U 12 12 4 4 4
move 32 pi . 0010...011...... A+-DXWLdxI U U U U U 12 12 4 4 4
move 32 pd d 0010...100000... .......... U U U U U 12 14 5 5 5
move 32 pd a 0010...100001... .......... U U U U U 12 14 5 5 5
move 32 pd . 0010...100...... A+-DXWLdxI U U U U U 12 14 5 5 5
move 32 di d 0010...101000... .......... U U U U U 16 16 5 5 5
move 32 di a 0010...101001... .......... U U U U U 16 16 5 5 5
move 32 di . 0010...101...... A+-DXWLdxI U U U U U 16 16 5 5 5
move 32 ix d 0010...110000... .......... U U U U U 18 18 7 7 7
move 32 ix a 0010...110001... .......... U U U U U 18 18 7 7 7
move 32 ix . 0010...110...... A+-DXWLdxI U U U U U 18 18 7 7 7
move 32 aw d 0010000111000... .......... U U U U U 16 16 4 4 4
move 32 aw a 0010000111001... .......... U U U U U 16 16 4 4 4
move 32 aw . 0010000111...... A+-DXWLdxI U U U U U 16 16 4 4 4
move 32 al d 0010001111000... .......... U U U U U 20 20 6 6 6
move 32 al a 0010001111001... .......... U U U U U 20 20 6 6 6
move 32 al . 0010001111...... A+-DXWLdxI U U U U U 20 20 6 6 6
movea 16 . d 0011...001000... .......... U U U U U 4 4 2 2 2
movea 16 . a 0011...001001... .......... U U U U U 4 4 2 2 2
movea 16 . . 0011...001...... A+-DXWLdxI U U U U U 4 4 2 2 2
movea 32 . d 0010...001000... .......... U U U U U 4 4 2 2 2
movea 32 . a 0010...001001... .......... U U U U U 4 4 2 2 2
movea 32 . . 0010...001...... A+-DXWLdxI U U U U U 4 4 2 2 2
move 16 frc d 0100001011000... .......... . U U U U . 4 4 4 4
move 16 frc . 0100001011...... A+-DXWL... . U U U U . 8 4 4 4
move 16 toc d 0100010011000... .......... U U U U U 12 12 4 4 4
move 16 toc . 0100010011...... A+-DXWLdxI U U U U U 12 12 4 4 4
move 16 frs d 0100000011000... .......... U S S S S 6 4 8 8 8 U only for 000
move 16 frs . 0100000011...... A+-DXWL... U S S S S 8 8 8 8 8 U only for 000
move 16 tos d 0100011011000... .......... S S S S S 12 12 8 8 8
move 16 tos . 0100011011...... A+-DXWLdxI S S S S S 12 12 8 8 8
move 32 fru . 0100111001101... .......... S S S S S 4 6 2 2 2
move 32 tou . 0100111001100... .......... S S S S S 4 6 2 2 2
movec 32 cr . 0100111001111010 .......... . S S S S . 12 6 6 6
movec 32 rc . 0100111001111011 .......... . S S S S . 10 12 12 12
movem 16 re pd 0100100010100... .......... U U U U U 8 8 4 4 4
movem 16 re . 0100100010...... A..DXWL... U U U U U 8 8 4 4 4
movem 32 re pd 0100100011100... .......... U U U U U 8 8 4 4 4
movem 32 re . 0100100011...... A..DXWL... U U U U U 8 8 4 4 4
movem 16 er pi 0100110010011... .......... U U U U U 12 12 8 8 8
movem 16 er pcdi 0100110010111010 .......... U U U U U 16 16 9 9 9
movem 16 er pcix 0100110010111011 .......... U U U U U 18 18 11 11 11
movem 16 er . 0100110010...... A..DXWL... U U U U U 12 12 8 8 8
movem 32 er pi 0100110011011... .......... U U U U U 12 12 8 8 8
movem 32 er pcdi 0100110011111010 .......... U U U U U 16 16 9 9 9
movem 32 er pcix 0100110011111011 .......... U U U U U 18 18 11 11 11
movem 32 er . 0100110011...... A..DXWL... U U U U U 12 12 8 8 8
movep 16 er . 0000...100001... .......... U U U U U 16 16 12 12 12
movep 32 er . 0000...101001... .......... U U U U U 24 24 18 18 18
movep 16 re . 0000...110001... .......... U U U U U 16 16 11 11 11
movep 32 re . 0000...111001... .......... U U U U U 24 24 17 17 17
moveq 32 . . 0111...0........ .......... U U U U U 4 4 2 2 2
moves 8 . . 0000111000...... A+-DXWL... . S S S S . 14 5 5 5
moves 16 . . 0000111001...... A+-DXWL... . S S S S . 14 5 5 5
moves 32 . . 0000111010...... A+-DXWL... . S S S S . 16 5 5 5
move16 32 . . 1111011000100... .......... . . . . U . . . . 4 TODO: correct timing
muls 16 . d 1100...111000... .......... U U U U U 54 32 27 27 27
muls 16 . . 1100...111...... A+-DXWLdxI U U U U U 54 32 27 27 27
mulu 16 . d 1100...011000... .......... U U U U U 54 30 27 27 27
mulu 16 . . 1100...011...... A+-DXWLdxI U U U U U 54 30 27 27 27
mull 32 . d 0100110000000... .......... . . U U U . . 43 43 43
mull 32 . . 0100110000...... A+-DXWLdxI . . U U U . . 43 43 43
nbcd 8 . d 0100100000000... .......... U U U U U 6 6 6 6 6
nbcd 8 . . 0100100000...... A+-DXWL... U U U U U 8 8 6 6 6
neg 8 . d 0100010000000... .......... U U U U U 4 4 2 2 2
neg 8 . . 0100010000...... A+-DXWL... U U U U U 8 8 4 4 4
neg 16 . d 0100010001000... .......... U U U U U 4 4 2 2 2
neg 16 . . 0100010001...... A+-DXWL... U U U U U 8 8 4 4 4
neg 32 . d 0100010010000... .......... U U U U U 6 6 2 2 2
neg 32 . . 0100010010...... A+-DXWL... U U U U U 12 12 4 4 4
negx 8 . d 0100000000000... .......... U U U U U 4 4 2 2 2
negx 8 . . 0100000000...... A+-DXWL... U U U U U 8 8 4 4 4
negx 16 . d 0100000001000... .......... U U U U U 4 4 2 2 2
negx 16 . . 0100000001...... A+-DXWL... U U U U U 8 8 4 4 4
negx 32 . d 0100000010000... .......... U U U U U 6 6 2 2 2
negx 32 . . 0100000010...... A+-DXWL... U U U U U 12 12 4 4 4
nop 0 . . 0100111001110001 .......... U U U U U 4 4 2 2 2
not 8 . d 0100011000000... .......... U U U U U 4 4 2 2 2
not 8 . . 0100011000...... A+-DXWL... U U U U U 8 8 4 4 4
not 16 . d 0100011001000... .......... U U U U U 4 4 2 2 2
not 16 . . 0100011001...... A+-DXWL... U U U U U 8 8 4 4 4
not 32 . d 0100011010000... .......... U U U U U 6 6 2 2 2
not 32 . . 0100011010...... A+-DXWL... U U U U U 12 12 4 4 4
or 8 er d 1000...000000... .......... U U U U U 4 4 2 2 2
or 8 er . 1000...000...... A+-DXWLdxI U U U U U 4 4 2 2 2
or 16 er d 1000...001000... .......... U U U U U 4 4 2 2 2
or 16 er . 1000...001...... A+-DXWLdxI U U U U U 4 4 2 2 2
or 32 er d 1000...010000... .......... U U U U U 6 6 2 2 2
or 32 er . 1000...010...... A+-DXWLdxI U U U U U 6 6 2 2 2
or 8 re . 1000...100...... A+-DXWL... U U U U U 8 8 4 4 4
or 16 re . 1000...101...... A+-DXWL... U U U U U 8 8 4 4 4
or 32 re . 1000...110...... A+-DXWL... U U U U U 12 12 4 4 4
ori 16 toc . 0000000000111100 .......... U U U U U 20 16 12 12 12
ori 16 tos . 0000000001111100 .......... S S S S S 20 16 12 12 12
ori 8 . d 0000000000000... .......... U U U U U 8 8 2 2 2
ori 8 . . 0000000000...... A+-DXWL... U U U U U 12 12 4 4 4
ori 16 . d 0000000001000... .......... U U U U U 8 8 2 2 2
ori 16 . . 0000000001...... A+-DXWL... U U U U U 12 12 4 4 4
ori 32 . d 0000000010000... .......... U U U U U 16 14 2 2 2
ori 32 . . 0000000010...... A+-DXWL... U U U U U 20 20 4 4 4
pack 16 rr . 1000...101000... .......... . . U U U . . 6 6 6
pack 16 mm ax7 1000111101001... .......... . . U U U . . 13 13 13
pack 16 mm ay7 1000...101001111 .......... . . U U U . . 13 13 13
pack 16 mm axy7 1000111101001111 .......... . . U U U . . 13 13 13
pack 16 mm . 1000...101001... .......... . . U U U . . 13 13 13
pea 32 . . 0100100001...... A..DXWLdx. U U U U U 6 6 5 5 5
pflush 32 . . 1111010100011000 .......... . . . . S . . . . 4 TODO: correct timing
pmmu 32 . . 1111000......... .......... . . S S S . . 8 8 8
reset 0 . . 0100111001110000 .......... S S S S S 0 0 0 0 0
ror 8 s . 1110...000011... .......... U U U U U 6 6 8 8 8
ror 16 s . 1110...001011... .......... U U U U U 6 6 8 8 8
ror 32 s . 1110...010011... .......... U U U U U 8 8 8 8 8
ror 8 r . 1110...000111... .......... U U U U U 6 6 8 8 8
ror 16 r . 1110...001111... .......... U U U U U 6 6 8 8 8
ror 32 r . 1110...010111... .......... U U U U U 8 8 8 8 8
ror 16 . . 1110011011...... A+-DXWL... U U U U U 8 8 7 7 7
rol 8 s . 1110...100011... .......... U U U U U 6 6 8 8 8
rol 16 s . 1110...101011... .......... U U U U U 6 6 8 8 8
rol 32 s . 1110...110011... .......... U U U U U 8 8 8 8 8
rol 8 r . 1110...100111... .......... U U U U U 6 6 8 8 8
rol 16 r . 1110...101111... .......... U U U U U 6 6 8 8 8
rol 32 r . 1110...110111... .......... U U U U U 8 8 8 8 8
rol 16 . . 1110011111...... A+-DXWL... U U U U U 8 8 7 7 7
roxr 8 s . 1110...000010... .......... U U U U U 6 6 12 12 12
roxr 16 s . 1110...001010... .......... U U U U U 6 6 12 12 12
roxr 32 s . 1110...010010... .......... U U U U U 8 8 12 12 12
roxr 8 r . 1110...000110... .......... U U U U U 6 6 12 12 12
roxr 16 r . 1110...001110... .......... U U U U U 6 6 12 12 12
roxr 32 r . 1110...010110... .......... U U U U U 8 8 12 12 12
roxr 16 . . 1110010011...... A+-DXWL... U U U U U 8 8 5 5 5
roxl 8 s . 1110...100010... .......... U U U U U 6 6 12 12 12
roxl 16 s . 1110...101010... .......... U U U U U 6 6 12 12 12
roxl 32 s . 1110...110010... .......... U U U U U 8 8 12 12 12
roxl 8 r . 1110...100110... .......... U U U U U 6 6 12 12 12
roxl 16 r . 1110...101110... .......... U U U U U 6 6 12 12 12
roxl 32 r . 1110...110110... .......... U U U U U 8 8 12 12 12
roxl 16 . . 1110010111...... A+-DXWL... U U U U U 8 8 5 5 5
rtd 32 . . 0100111001110100 .......... . U U U U . 16 10 10 10
rte 32 . . 0100111001110011 .......... S S S S S 20 24 20 20 20 bus fault not emulated
rtm 32 . . 000001101100.... .......... . . U U U . . 19 19 19 not properly emulated
rtr 32 . . 0100111001110111 .......... U U U U U 20 20 14 14 14
rts 32 . . 0100111001110101 .......... U U U U U 16 16 10 10 10
sbcd 8 rr . 1000...100000... .......... U U U U U 6 6 4 4 4
sbcd 8 mm ax7 1000111100001... .......... U U U U U 18 18 16 16 16
sbcd 8 mm ay7 1000...100001111 .......... U U U U U 18 18 16 16 16
sbcd 8 mm axy7 1000111100001111 .......... U U U U U 18 18 16 16 16
sbcd 8 mm . 1000...100001... .......... U U U U U 18 18 16 16 16
st 8 . d 0101000011000... .......... U U U U U 6 4 4 4 4
st 8 . . 0101000011...... A+-DXWL... U U U U U 8 8 6 6 6
sf 8 . d 0101000111000... .......... U U U U U 4 4 4 4 4
sf 8 . . 0101000111...... A+-DXWL... U U U U U 8 8 6 6 6
scc 8 . d 0101....11000... .......... U U U U U 4 4 4 4 4
scc 8 . . 0101....11...... A+-DXWL... U U U U U 8 8 6 6 6
stop 0 . . 0100111001110010 .......... S S S S S 4 4 8 8 8
sub 8 er d 1001...000000... .......... U U U U U 4 4 2 2 2
sub 8 er . 1001...000...... A+-DXWLdxI U U U U U 4 4 2 2 2
sub 16 er d 1001...001000... .......... U U U U U 4 4 2 2 2
sub 16 er a 1001...001001... .......... U U U U U 4 4 2 2 2
sub 16 er . 1001...001...... A+-DXWLdxI U U U U U 4 4 2 2 2
sub 32 er d 1001...010000... .......... U U U U U 6 6 2 2 2
sub 32 er a 1001...010001... .......... U U U U U 6 6 2 2 2
sub 32 er . 1001...010...... A+-DXWLdxI U U U U U 6 6 2 2 2
sub 8 re . 1001...100...... A+-DXWL... U U U U U 8 8 4 4 4
sub 16 re . 1001...101...... A+-DXWL... U U U U U 8 8 4 4 4
sub 32 re . 1001...110...... A+-DXWL... U U U U U 12 12 4 4 4
suba 16 . d 1001...011000... .......... U U U U U 8 8 2 2 2
suba 16 . a 1001...011001... .......... U U U U U 8 8 2 2 2
suba 16 . . 1001...011...... A+-DXWLdxI U U U U U 8 8 2 2 2
suba 32 . d 1001...111000... .......... U U U U U 6 6 2 2 2
suba 32 . a 1001...111001... .......... U U U U U 6 6 2 2 2
suba 32 . . 1001...111...... A+-DXWLdxI U U U U U 6 6 2 2 2
subi 8 . d 0000010000000... .......... U U U U U 8 8 2 2 2
subi 8 . . 0000010000...... A+-DXWL... U U U U U 12 12 4 4 4
subi 16 . d 0000010001000... .......... U U U U U 8 8 2 2 2
subi 16 . . 0000010001...... A+-DXWL... U U U U U 12 12 4 4 4
subi 32 . d 0000010010000... .......... U U U U U 16 14 2 2 2
subi 32 . . 0000010010...... A+-DXWL... U U U U U 20 20 4 4 4
subq 8 . d 0101...100000... .......... U U U U U 4 4 2 2 2
subq 8 . . 0101...100...... A+-DXWL... U U U U U 8 8 4 4 4
subq 16 . d 0101...101000... .......... U U U U U 4 4 2 2 2
subq 16 . a 0101...101001... .......... U U U U U 8 4 2 2 2
subq 16 . . 0101...101...... A+-DXWL... U U U U U 8 8 4 4 4
subq 32 . d 0101...110000... .......... U U U U U 8 8 2 2 2
subq 32 . a 0101...110001... .......... U U U U U 8 8 2 2 2
subq 32 . . 0101...110...... A+-DXWL... U U U U U 12 12 4 4 4
subx 8 rr . 1001...100000... .......... U U U U U 4 4 2 2 2
subx 16 rr . 1001...101000... .......... U U U U U 4 4 2 2 2
subx 32 rr . 1001...110000... .......... U U U U U 8 6 2 2 2
subx 8 mm ax7 1001111100001... .......... U U U U U 18 18 12 12 12
subx 8 mm ay7 1001...100001111 .......... U U U U U 18 18 12 12 12
subx 8 mm axy7 1001111100001111 .......... U U U U U 18 18 12 12 12
subx 8 mm . 1001...100001... .......... U U U U U 18 18 12 12 12
subx 16 mm . 1001...101001... .......... U U U U U 18 18 12 12 12
subx 32 mm . 1001...110001... .......... U U U U U 30 30 12 12 12
swap 32 . . 0100100001000... .......... U U U U U 4 4 4 4 4
tas 8 . d 0100101011000... .......... U U U U U 4 4 4 4 4
tas 8 . . 0100101011...... A+-DXWL... U U U U U 14 14 12 12 12
trap 0 . . 010011100100.... .......... U U U U U 4 4 4 4 4
trapt 0 . . 0101000011111100 .......... . . U U U . . 4 4 4
trapt 16 . . 0101000011111010 .......... . . U U U . . 6 6 6
trapt 32 . . 0101000011111011 .......... . . U U U . . 8 8 8
trapf 0 . . 0101000111111100 .......... . . U U U . . 4 4 4
trapf 16 . . 0101000111111010 .......... . . U U U . . 6 6 6
trapf 32 . . 0101000111111011 .......... . . U U U . . 8 8 8
trapcc 0 . . 0101....11111100 .......... . . U U U . . 4 4 4
trapcc 16 . . 0101....11111010 .......... . . U U U . . 6 6 6
trapcc 32 . . 0101....11111011 .......... . . U U U . . 8 8 8
trapv 0 . . 0100111001110110 .......... U U U U U 4 4 4 4 4
tst 8 . d 0100101000000... .......... U U U U U 4 4 2 2 2
tst 8 . . 0100101000...... A+-DXWL... U U U U U 4 4 2 2 2
tst 8 . pcdi 0100101000111010 .......... . . U U U . . 7 7 7
tst 8 . pcix 0100101000111011 .......... . . U U U . . 9 9 9
tst 8 . i 0100101000111100 .......... . . U U U . . 6 6 6
tst 16 . d 0100101001000... .......... U U U U U 4 4 2 2 2
tst 16 . a 0100101001001... .......... . . U U U . . 2 2 2
tst 16 . . 0100101001...... A+-DXWL... U U U U U 4 4 2 2 2
tst 16 . pcdi 0100101001111010 .......... . . U U U . . 7 7 7
tst 16 . pcix 0100101001111011 .......... . . U U U . . 9 9 9
tst 16 . i 0100101001111100 .......... . . U U U . . 6 6 6
tst 32 . d 0100101010000... .......... U U U U U 4 4 2 2 2
tst 32 . a 0100101010001... .......... . . U U U . . 2 2 2
tst 32 . . 0100101010...... A+-DXWL... U U U U U 4 4 2 2 2
tst 32 . pcdi 0100101010111010 .......... . . U U U . . 7 7 7
tst 32 . pcix 0100101010111011 .......... . . U U U . . 9 9 9
tst 32 . i 0100101010111100 .......... . . U U U . . 6 6 6
unlk 32 . a7 0100111001011111 .......... U U U U U 12 12 6 6 6
unlk 32 . . 0100111001011... .......... U U U U U 12 12 6 6 6
unpk 16 rr . 1000...110000... .......... . . U U U . . 8 8 8
unpk 16 mm ax7 1000111110001... .......... . . U U U . . 13 13 13
unpk 16 mm ay7 1000...110001111 .......... . . U U U . . 13 13 13
unpk 16 mm axy7 1000111110001111 .......... . . U U U . . 13 13 13
unpk 16 mm . 1000...110001... .......... . . U U U . . 13 13 13
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
M68KMAKE_OPCODE_HANDLER_BODY
M68KMAKE_OP(1010, 0, ., .)
{
m68ki_exception_1010();
}
M68KMAKE_OP(1111, 0, ., .)
{
m68ki_exception_1111();
}
M68KMAKE_OP(040fpu0, 32, ., .)
{
if(CPU_TYPE_IS_030_PLUS(CPU_TYPE))
{
m68040_fpu_op0();
return;
}
m68ki_exception_1111();
}
M68KMAKE_OP(040fpu1, 32, ., .)
{
if(CPU_TYPE_IS_030_PLUS(CPU_TYPE))
{
m68040_fpu_op1();
return;
}
m68ki_exception_1111();
}
M68KMAKE_OP(abcd, 8, rr, .)
{
uint* r_dst = &DX;
uint src = DY;
uint dst = *r_dst;
uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
FLAG_V = ~res; /* Undefined V behavior */
if(res > 9)
res += 6;
res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
FLAG_X = FLAG_C = (res > 0x99) << 8;
if(FLAG_C)
res -= 0xa0;
FLAG_V &= res; /* Undefined V behavior part II */
FLAG_N = NFLAG_8(res); /* Undefined N behavior */
res = MASK_OUT_ABOVE_8(res);
FLAG_Z |= res;
*r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
}
M68KMAKE_OP(abcd, 8, mm, ax7)
{
uint src = OPER_AY_PD_8();
uint ea = EA_A7_PD_8();
uint dst = m68ki_read_8(ea);
uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
FLAG_V = ~res; /* Undefined V behavior */
if(res > 9)
res += 6;
res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
FLAG_X = FLAG_C = (res > 0x99) << 8;
if(FLAG_C)
res -= 0xa0;
FLAG_V &= res; /* Undefined V behavior part II */
FLAG_N = NFLAG_8(res); /* Undefined N behavior */
res = MASK_OUT_ABOVE_8(res);
FLAG_Z |= res;
m68ki_write_8(ea, res);
}
M68KMAKE_OP(abcd, 8, mm, ay7)
{
uint src = OPER_A7_PD_8();
uint ea = EA_AX_PD_8();
uint dst = m68ki_read_8(ea);
uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
FLAG_V = ~res; /* Undefined V behavior */
if(res > 9)