Accessing Block from Vitis

[Cheatz04]

Hey peers,

I am having a problem to find the right approach to access my synthesized network from vitis. Most of my project runs in vitis, it's a network and supposed to calculate one output out of six inputs.

I synthesized the IP block and generated a Vivado block design from it using the design.tcl script.
My board is the digilentinc.com:zybo-z7-20:part0:1.0.

Until now, I have tried to export the hardware, build a platform project and write my application on top of the hardware accelerator, but all attempts to access the Axi interfaced NN-Block have failed. Any suggestions on how to access the block?

Thank you all in advance.

[jmitrevs]

Note that there is experimental Vitis support now. You can synthesize things with the Vitis backend. However, there is no equivalent of VivadoAccelerator just yet. If you do use the Vitis backend, try to use the "Latency" strategy instead of "Resource" if you can since Resource winds up being much slower (and maybe even bigger). We are trying to follow up on those issues.

[Cheatz04]

Hey Jovan, thank you for the reply. If I am using the 'vitis' backend insted of 'VivadoAccelerator' how is the synthesized IP block accesed? Can you maybe link me the example workflow for accessing the block in Vitis?

I am a bit new in this and don't get intuitively at what point of the workflow i can use the core. Because in the end it is also an IP-Block. So intuitively i would proceed just as with the other one and embed it into a block design.

[thesps]

Hi @Cheatz04 , can you give some more detail about how you have tried to access the AXI interfaced block? Have you been using the axi_stream_driver.py from Python for example?
https://github.com/fastmachinelearning/hls4ml/blob/main/hls4ml/templates/vivado_accelerator/pynq-z2/python_drivers/axi_stream_driver.py

[Cheatz04]

Hi @thesps , happily so. I went a step backwards and simulated the IP block. And it turns out the the valid in signal never goes to 0. I guess the axistream interface doesn't work as I expect. Could this be connected to using the zybo-z7 and not the pinq board?

I dont know about the axi_stream_driver.py. But I intend to access the Block from vitis over DMA with the XAxiDma_SimpleTransfer() function.

I am using vitis 2020.1 and a Zybo Z7-20 board.

[thesps]

The axi_stream_driver.py module is our Python driver for communicating with the NN via DMA using Xilinx's pynq Python framework. But maybe it won't be so easy to set that up on the Zybo... http://www.pynq.io/board.html

I don't really have experience with using the C Driver for the DMA, sorry!