Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Implement assignment expressions #172

Closed
3 tasks done
fabianschuiki opened this issue May 22, 2020 · 0 comments
Closed
3 tasks done

Implement assignment expressions #172

fabianschuiki opened this issue May 22, 2020 · 0 comments
Labels
A-hir Area: High-level Intermediate Representation. A-mir Area: Mid-level Intermediate Representation. A-typeck Area: Type checking, inference, and computation. C-enhancement Category: Adding or improving on features. L-vlog Language: Verilog and SystemVerilog.
Milestone

Comments

@fabianschuiki
Copy link
Owner

fabianschuiki commented May 22, 2020

Implement HIR lowering, typeck, and codegen of assignment expressions such as the following:

for (int i = 0; i < N; i += 1) begin
//                     ^^^^^^ this here
end

Todo

  • Lower expression to HIR
  • Implement the various typeck queries
  • Implement lowering to MIR (Assignment rvalue)
@fabianschuiki fabianschuiki added L-vlog Language: Verilog and SystemVerilog. C-enhancement Category: Adding or improving on features. A-typeck Area: Type checking, inference, and computation. A-mir Area: Mid-level Intermediate Representation. A-hir Area: High-level Intermediate Representation. labels May 22, 2020
@fabianschuiki fabianschuiki added this to the v0.11 milestone Jun 16, 2020
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
A-hir Area: High-level Intermediate Representation. A-mir Area: Mid-level Intermediate Representation. A-typeck Area: Type checking, inference, and computation. C-enhancement Category: Adding or improving on features. L-vlog Language: Verilog and SystemVerilog.
Projects
None yet
Development

No branches or pull requests

1 participant