philip@philip-ThinkBook-15-G2-ITL:~/eclipse-workspace/nodemcu/components/base_nodemcu/ld$ /usr/local/bin/openocd  -s /usr/local/share/openocd/scripts/ -f interface/jlink.cfg -f board/esp32c3-builtin.cfg 
Open On-Chip Debugger  v0.10.0-esp32-20201202-14-gde9e630c (2021-02-14-18:40)
Licensed under GNU GPL v2
For bug reports, read
	http://openocd.org/doc/doxygen/bugs.html
Warn : Interface already configured, ignoring
force hard breakpoints
Info : Listening on port 6666 for tcl connections
Info : Listening on port 4444 for telnet connections
Info : J-Link ARM V8 compiled Nov 14 2012 22:34:52
Info : Hardware version: 8.00
Info : VTarget = 3.287 V
Info : Reduced speed from 40000 kHz to 12000 kHz (maximum).
Info : Reduced speed from 40000 kHz to 12000 kHz (maximum).
Info : clock speed 40000 kHz
Info : JTAG tap: esp32c3.cpu tap/device found: 0x00005c25 (mfg: 0x612 (Espressif Systems), part: 0x0005, ver: 0x0)
Info : datacount=2 progbufsize=16
Info : Examined RISC-V core; found 1 harts
Info :  hart 0: XLEN=32, misa=0x40101104
Info : Listening on port 3333 for gdb connections
Info : accepting 'gdb' connection on tcp/3333
Warn : No symbols for FreeRTOS!
Info : JTAG tap: esp32c3.cpu tap/device found: 0x00005c25 (mfg: 0x612 (Espressif Systems), part: 0x0005, ver: 0x0)
Info : [0] Found 8 triggers
Error: FreeRTOS uxTaskNumber seems to be corrupted!
Error: FreeRTOS uxTaskNumber seems to be corrupted!
Error: FreeRTOS uxTaskNumber seems to be corrupted!
Error: FreeRTOS uxTaskNumber seems to be corrupted!
Error: FreeRTOS uxTaskNumber seems to be corrupted!
User : 59501 149693 gdb_server.c:719 gdb_output(): debug_level: 3
Debug: 59502 149693 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$O64656275675f6c6576656c3a20330a#62'
User : 59503 149693 gdb_server.c:719 gdb_output(): 
Debug: 59504 149693 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$O0a#e0'
Debug: 59523 149694 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$OK#9a'
Debug: 60082 152852 gdb_server.c:3358 gdb_input_inner(): received packet: 'm420cea40,40'
Debug: 60083 152853 gdb_server.c:1451 gdb_read_memory_packet(): addr: 0x00000000420cea40, len: 0x00000040
Debug: 60084 152853 target.c:2299 target_read_buffer(): reading buffer of 64 byte at 0x420cea40
Debug: 60139 152855 riscv-013.c:2072 log_memory_access(): M[0x420cea40] reads 0x3cc12083
Debug: 60158 152855 riscv-013.c:2072 log_memory_access(): M[0x420cea44] reads 0x3c812403
Debug: 60177 152856 riscv-013.c:2072 log_memory_access(): M[0x420cea48] reads 0x3c412483
Debug: 60196 152857 riscv-013.c:2072 log_memory_access(): M[0x420cea4c] reads 0x3d010113
Debug: 60215 152857 riscv-013.c:2072 log_memory_access(): M[0x420cea50] reads 0x00008067
Debug: 60234 152858 riscv-013.c:2072 log_memory_access(): M[0x420cea54] reads 0x00072023
Debug: 60253 152858 riscv-013.c:2072 log_memory_access(): M[0x420cea58] reads 0xfadff06f
Debug: 60272 152859 riscv-013.c:2072 log_memory_access(): M[0x420cea5c] reads 0x00000413
Debug: 60291 152860 riscv-013.c:2072 log_memory_access(): M[0x420cea60] reads 0xfddff06f
Debug: 60310 152860 riscv-013.c:2072 log_memory_access(): M[0x420cea64] reads 0x00008067
Debug: 60329 152861 riscv-013.c:2072 log_memory_access(): M[0x420cea68] reads 0xa7010113
Debug: 60348 152862 riscv-013.c:2072 log_memory_access(): M[0x420cea6c] reads 0x58812423
Debug: 60367 152862 riscv-013.c:2072 log_memory_access(): M[0x420cea70] reads 0x58a12023
Debug: 60386 152863 riscv-013.c:2072 log_memory_access(): M[0x420cea74] reads 0x56b12e23
Debug: 60405 152863 riscv-013.c:2072 log_memory_access(): M[0x420cea78] reads 0x56c12c23
Debug: 60460 152865 riscv-013.c:2072 log_memory_access(): M[0x420cea7c] reads 0x59010593
Debug: 60479 152866 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$8320c13c0324813c8324413c1301013d67800000232007006ff0dffa130400006ff0dffd67800000130101a7232481582320a158232eb156232cc15693050159#c9'
Debug: 60480 152866 gdb_server.c:3358 gdb_input_inner(): received packet: 'Z0,420cea64,4'
Debug: 60481 152866 gdb_server.c:1650 gdb_breakpoint_watchpoint_packet(): [esp32c3]
Debug: 60482 152866 riscv.c:703 riscv_add_breakpoint(): [0] @0x420cea64
Debug: 60483 152866 riscv-013.c:3416 riscv013_get_register(): [0] reading register tselect on hart 0
Debug: 60484 152866 riscv-013.c:765 execute_abstract_command(): command=0x2207a0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a0
Debug: 60530 152868 riscv-013.c:1415 register_read_direct(): {0} tselect = 0x0
Debug: 60531 152868 riscv.c:2795 riscv_get_register_on_hart(): {0} tselect: 0
Debug: 60532 152868 riscv.c:2756 riscv_set_register_on_hart(): {0} tselect <- 0
Debug: 60533 152868 riscv-013.c:3440 riscv013_set_register(): [0] writing 0x0 to register tselect on hart 0
Debug: 60534 152868 riscv-013.c:1227 register_write_direct(): {0} tselect <- 0x0
Debug: 60553 152868 riscv-013.c:765 execute_abstract_command(): command=0x2307a0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a0
Debug: 60581 152869 riscv-013.c:3416 riscv013_get_register(): [0] reading register tdata1 on hart 0
Debug: 60582 152869 riscv-013.c:765 execute_abstract_command(): command=0x2207a1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a1
Debug: 60628 152871 riscv-013.c:1415 register_read_direct(): {0} tdata1 = 0x23e00000
Debug: 60629 152871 riscv.c:2795 riscv_get_register_on_hart(): {0} tdata1: 23e00000
Debug: 60630 152871 riscv.c:2756 riscv_set_register_on_hart(): {0} tdata1 <- 2be0104c
Debug: 60631 152871 riscv-013.c:3440 riscv013_set_register(): [0] writing 0x2be0104c to register tdata1 on hart 0
Debug: 60632 152871 riscv-013.c:1227 register_write_direct(): {0} tdata1 <- 0x2be0104c
Debug: 60651 152872 riscv-013.c:765 execute_abstract_command(): command=0x2307a1; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a1
Debug: 60679 152872 riscv-013.c:3416 riscv013_get_register(): [0] reading register tdata1 on hart 0
Debug: 60680 152872 riscv-013.c:765 execute_abstract_command(): command=0x2207a1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a1
Debug: 60726 152874 riscv-013.c:1415 register_read_direct(): {0} tdata1 = 0x2be0104c
Debug: 60727 152874 riscv.c:2795 riscv_get_register_on_hart(): {0} tdata1: 2be0104c
Debug: 60728 152874 riscv.c:597 maybe_add_trigger_t2(): tdata1=0x2be0104c
Debug: 60729 152874 riscv.c:2756 riscv_set_register_on_hart(): {0} tdata2 <- 420cea64
Debug: 60730 152874 riscv-013.c:3440 riscv013_set_register(): [0] writing 0x420cea64 to register tdata2 on hart 0
Debug: 60731 152874 riscv-013.c:1227 register_write_direct(): {0} tdata2 <- 0x420cea64
Debug: 60750 152875 riscv-013.c:765 execute_abstract_command(): command=0x2307a2; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a2
Debug: 60778 152876 riscv.c:680 add_trigger(): [0] Using trigger 0 (type 2) for bp 2
Debug: 60779 152876 riscv.c:2756 riscv_set_register_on_hart(): {0} tselect <- 0
Debug: 60780 152876 riscv-013.c:3440 riscv013_set_register(): [0] writing 0x0 to register tselect on hart 0
Debug: 60781 152876 riscv-013.c:1227 register_write_direct(): {0} tselect <- 0x0
Debug: 60800 152876 riscv-013.c:765 execute_abstract_command(): command=0x2307a0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a0
Debug: 60828 152877 breakpoints.c:101 breakpoint_add_internal(): [0] added hardware breakpoint at 0x420cea64 of length 0x00000004, (BPID: 2)
Debug: 60829 152877 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$OK#9a'
Debug: 60830 152877 gdb_server.c:3358 gdb_input_inner(): received packet: 'vCont;s:3fc9ed78;c'
Debug: 60831 152877 FreeRTOS.c:405 FreeRTOS_find_target_from_threadid(): Find target for thr 0x3fc9ed78
Debug: 60832 152877 FreeRTOS.c:433 FreeRTOS_target_for_threadid(): target found : esp32c3
Debug: 60833 152877 gdb_server.c:2912 gdb_handle_vcont_packet(): target esp32c3 single-step thread 3fc9ed78
Debug: 60834 152877 target.c:1634 target_call_event_callbacks(): target event 5 (gdb-start) for core esp32c3
Debug: 60835 152877 riscv.c:965 old_or_new_riscv_step(): handle_breakpoints=0
Debug: 60836 152877 riscv.c:1845 riscv_openocd_step(): stepping rtos hart
Debug: 60837 152877 riscv.c:2624 riscv_step_rtos_hart(): stepping hart 0
Debug: 60856 152878 riscv.c:2699 riscv_invalidate_register_cache(): [0]
Debug: 60857 152878 program.c:33 riscv_program_write(): debug_buffer[00] = DASM(0x0000100f)
Debug: 60858 152878 riscv-013.c:3695 riscv013_write_debug_buffer(): cache hit for 0x100f @0
Debug: 60859 152878 program.c:33 riscv_program_write(): debug_buffer[01] = DASM(0x0000000f)
Debug: 60860 152878 riscv-013.c:3695 riscv013_write_debug_buffer(): cache hit for 0xf @1
Debug: 60861 152878 program.c:33 riscv_program_write(): debug_buffer[02] = DASM(0x00100073)
Debug: 60862 152878 riscv-013.c:3695 riscv013_write_debug_buffer(): cache hit for 0x100073 @2
Debug: 60863 152878 riscv-013.c:765 execute_abstract_command(): command=0x241000; access register, size=32, postexec=1, transfer=0, write=0, regno=0x1000
Debug: 60891 152879 program.c:33 riscv_program_write(): debug_buffer[00] = DASM(0x0000100f)
Debug: 60892 152879 riscv-013.c:3695 riscv013_write_debug_buffer(): cache hit for 0x100f @0
Debug: 60893 152879 program.c:33 riscv_program_write(): debug_buffer[01] = DASM(0x0000000f)
Debug: 60894 152879 riscv-013.c:3695 riscv013_write_debug_buffer(): cache hit for 0xf @1
Debug: 60895 152879 program.c:33 riscv_program_write(): debug_buffer[02] = DASM(0x00100073)
Debug: 60896 152879 riscv-013.c:3695 riscv013_write_debug_buffer(): cache hit for 0x100073 @2
Debug: 60897 152879 riscv-013.c:765 execute_abstract_command(): command=0x241000; access register, size=32, postexec=1, transfer=0, write=0, regno=0x1000
Debug: 60925 152880 riscv-013.c:765 execute_abstract_command(): command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0
Debug: 60971 152881 riscv-013.c:1415 register_read_direct(): {0} dcsr = 0x4000b107
Debug: 60972 152881 riscv.c:2756 riscv_set_register_on_hart(): {0} dcsr <- 4000b107
Debug: 60973 152881 riscv-013.c:3440 riscv013_set_register(): [0] writing 0x4000b107 to register dcsr on hart 0
Debug: 60974 152881 riscv-013.c:1227 register_write_direct(): {0} dcsr <- 0x4000b107
Debug: 60993 152882 riscv-013.c:765 execute_abstract_command(): command=0x2307b0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b0
Debug: 61021 152883 riscv-013.c:4130 riscv013_step_or_resume_current_hart(): resuming hart 0 (for step?=1)
Debug: 61094 152886 riscv.c:2699 riscv_invalidate_register_cache(): [0]
Debug: 61113 152886 target.c:1634 target_call_event_callbacks(): target event 2 (resumed) for core esp32c3
Debug: 61114 152886 target.c:1634 target_call_event_callbacks(): target event 0 (gdb-halt) for core esp32c3
Debug: 61115 152886 target.c:1634 target_call_event_callbacks(): target event 1 (halted) for core esp32c3
Debug: 61116 152886 target.c:4631 target_handle_event(): target(0): esp32c3 (riscv) event: 1 (halted) action:  esp32c3_wdt_disable 
Debug: 61117 152886 command.c:143 script_debug(): command - command command mode
Debug: 61118 152886 command.c:143 script_debug(): command - mww mww 0x6001f064 0x50D83AA1
Debug: 61138 152887 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$O#4f'
Debug: 61175 152888 riscv-013.c:3076 write_memory_bus_v1(): transferring burst starting at address 0x6001f064
Debug: 61176 152888 riscv-013.c:2072 log_memory_access(): M[0x6001f064] writes 0x50d83aa1
Debug: 61186 152889 batch.c:164 dump_field(): 41b 5i w 50d83aa1 @3c -> + 00000000 @39
Debug: 61187 152889 batch.c:164 dump_field(): 41b 5i - 00000000 @00 -> + 50d83aa1 @3c
Debug: 61197 152889 command.c:143 script_debug(): command - mww mww 0x6001F048 0
Debug: 61217 152890 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$O#4f'
Debug: 61254 152891 riscv-013.c:3076 write_memory_bus_v1(): transferring burst starting at address 0x6001f048
Debug: 61255 152891 riscv-013.c:2072 log_memory_access(): M[0x6001f048] writes 0x00000000
Debug: 61265 152891 batch.c:164 dump_field(): 41b 5i w 00000000 @3c -> + 00000000 @39
Debug: 61266 152891 batch.c:164 dump_field(): 41b 5i - 00000000 @00 -> + 00000000 @3c
Debug: 61276 152892 command.c:143 script_debug(): command - mww mww 0x60020064 0x50D83AA1
Debug: 61296 152892 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$O#4f'
Debug: 61333 152894 riscv-013.c:3076 write_memory_bus_v1(): transferring burst starting at address 0x60020064
Debug: 61334 152894 riscv-013.c:2072 log_memory_access(): M[0x60020064] writes 0x50d83aa1
Debug: 61344 152894 batch.c:164 dump_field(): 41b 5i w 50d83aa1 @3c -> + 00000000 @39
Debug: 61345 152894 batch.c:164 dump_field(): 41b 5i - 00000000 @00 -> + 50d83aa1 @3c
Debug: 61355 152894 command.c:143 script_debug(): command - mww mww 0x60020048 0
Debug: 61375 152895 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$O#4f'
Debug: 61412 152896 riscv-013.c:3076 write_memory_bus_v1(): transferring burst starting at address 0x60020048
Debug: 61413 152896 riscv-013.c:2072 log_memory_access(): M[0x60020048] writes 0x00000000
Debug: 61423 152897 batch.c:164 dump_field(): 41b 5i w 00000000 @3c -> + 00000000 @39
Debug: 61424 152897 batch.c:164 dump_field(): 41b 5i - 00000000 @00 -> + 00000000 @3c
Debug: 61434 152897 command.c:143 script_debug(): command - mww mww 0x600080a8 0x50D83AA1
Debug: 61454 152898 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$O#4f'
Debug: 61491 152899 riscv-013.c:3076 write_memory_bus_v1(): transferring burst starting at address 0x600080a8
Debug: 61492 152899 riscv-013.c:2072 log_memory_access(): M[0x600080a8] writes 0x50d83aa1
Debug: 61502 152899 batch.c:164 dump_field(): 41b 5i w 50d83aa1 @3c -> + 00000000 @39
Debug: 61503 152899 batch.c:164 dump_field(): 41b 5i - 00000000 @00 -> + 50d83aa1 @3c
Debug: 61513 152900 command.c:143 script_debug(): command - mww mww 0x60008090 0
Debug: 61533 152900 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$O#4f'
Debug: 61570 152902 riscv-013.c:3076 write_memory_bus_v1(): transferring burst starting at address 0x60008090
Debug: 61571 152902 riscv-013.c:2072 log_memory_access(): M[0x60008090] writes 0x00000000
Debug: 61581 152902 batch.c:164 dump_field(): 41b 5i w 00000000 @3c -> + 00000000 @39
Debug: 61582 152902 batch.c:164 dump_field(): 41b 5i - 00000000 @00 -> + 00000000 @3c
Debug: 61592 152902 target.c:1634 target_call_event_callbacks(): target event 6 (gdb-end) for core esp32c3
Debug: 61611 152903 FreeRTOS.c:694 FreeRTOS_update_threads(): FreeRTOS_update_threads
Debug: 61666 152905 riscv-013.c:2072 log_memory_access(): M[0x3fc97e8c] reads 0x00000004
Debug: 61685 152906 target.c:2447 target_read_u32(): address: 0x3fc97e8c, value: 0x00000004
Debug: 61686 152906 FreeRTOS.c:745 FreeRTOS_update_threads(): Read uxCurrentNumberOfTasks at 0x3fc97e8c, value 4
Debug: 61741 152908 riscv-013.c:2072 log_memory_access(): M[0x3fc97e98] reads 0x00000004
Debug: 61760 152908 target.c:2447 target_read_u32(): address: 0x3fc97e98, value: 0x00000004
Debug: 61761 152908 FreeRTOS.c:766 FreeRTOS_update_threads(): Read uxTaskNumber at 0x3fc97e98, value 4
Error: 61762 152908 FreeRTOS.c:771 FreeRTOS_update_threads(): FreeRTOS uxTaskNumber seems to be corrupted!
Debug: 61763 152908 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$O4672656552544f532075785461736b4e756d626572207365656d7320746f20626520636f72727570746564210a#38'
Debug: 61764 152908 FreeRTOS.c:405 FreeRTOS_find_target_from_threadid(): Find target for thr 0x3fc9ed78
Debug: 61765 152908 FreeRTOS.c:433 FreeRTOS_target_for_threadid(): target found : esp32c3
Debug: 61766 152908 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$T05thread:3fc9ed78;#13'
Debug: 61767 152909 gdb_server.c:3358 gdb_input_inner(): received packet: 'g'
Debug: 61768 152909 riscv.c:1357 riscv_get_gdb_reg_list_internal(): rtos_hartid=0, current_hartid=0, reg_class=1, read=1
Debug: 61769 152909 riscv-013.c:3416 riscv013_get_register(): [0] reading register zero on hart 0
Debug: 61770 152909 riscv.c:2795 riscv_get_register_on_hart(): {0} zero: 0
Debug: 61771 152909 riscv.c:3071 register_get(): [0]{0} read 0x0 from zero (valid=1)
Debug: 61772 152909 riscv-013.c:3416 riscv013_get_register(): [0] reading register ra on hart 0
Debug: 61773 152909 riscv-013.c:765 execute_abstract_command(): command=0x221001; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1001
Debug: 61819 152910 riscv-013.c:1415 register_read_direct(): {0} ra = 0x420082c8
Debug: 61820 152910 riscv.c:2795 riscv_get_register_on_hart(): {0} ra: 420082c8
Debug: 61821 152910 riscv.c:3071 register_get(): [0]{0} read 0x420082c8 from ra (valid=1)
Debug: 61822 152910 riscv-013.c:3416 riscv013_get_register(): [0] reading register sp on hart 0
Debug: 61823 152910 riscv-013.c:765 execute_abstract_command(): command=0x221002; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1002
Debug: 61869 152911 riscv-013.c:1415 register_read_direct(): {0} sp = 0x3fc9e0e0
Debug: 61870 152911 riscv.c:2795 riscv_get_register_on_hart(): {0} sp: 3fc9e0e0
Debug: 61871 152911 riscv.c:3071 register_get(): [0]{0} read 0x3fc9e0e0 from sp (valid=1)
Debug: 61872 152911 riscv-013.c:3416 riscv013_get_register(): [0] reading register gp on hart 0
Debug: 61873 152911 riscv-013.c:765 execute_abstract_command(): command=0x221003; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1003
Debug: 61919 152913 riscv-013.c:1415 register_read_direct(): {0} gp = 0x3fc8fc00
Debug: 61920 152913 riscv.c:2795 riscv_get_register_on_hart(): {0} gp: 3fc8fc00
Debug: 61921 152913 riscv.c:3071 register_get(): [0]{0} read 0x3fc8fc00 from gp (valid=1)
Debug: 61922 152913 riscv-013.c:3416 riscv013_get_register(): [0] reading register tp on hart 0
Debug: 61923 152913 riscv-013.c:765 execute_abstract_command(): command=0x221004; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1004
Debug: 61969 152915 riscv-013.c:1415 register_read_direct(): {0} tp = 0x3fc78f28
Debug: 61970 152915 riscv.c:2795 riscv_get_register_on_hart(): {0} tp: 3fc78f28
Debug: 61971 152915 riscv.c:3071 register_get(): [0]{0} read 0x3fc78f28 from tp (valid=1)
Debug: 61972 152915 riscv-013.c:3416 riscv013_get_register(): [0] reading register t0 on hart 0
Debug: 61973 152915 riscv-013.c:765 execute_abstract_command(): command=0x221005; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1005
Debug: 62019 152916 riscv-013.c:1415 register_read_direct(): {0} t0 = 0x40057fa6
Debug: 62020 152916 riscv.c:2795 riscv_get_register_on_hart(): {0} t0: 40057fa6
Debug: 62021 152916 riscv.c:3071 register_get(): [0]{0} read 0x40057fa6 from t0 (valid=1)
Debug: 62022 152916 riscv-013.c:3416 riscv013_get_register(): [0] reading register t1 on hart 0
Debug: 62023 152916 riscv-013.c:765 execute_abstract_command(): command=0x221006; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1006
Debug: 62069 152918 riscv-013.c:1415 register_read_direct(): {0} t1 = 0xf
Debug: 62070 152918 riscv.c:2795 riscv_get_register_on_hart(): {0} t1: f
Debug: 62071 152918 riscv.c:3071 register_get(): [0]{0} read 0xf from t1 (valid=1)
Debug: 62072 152918 riscv-013.c:3416 riscv013_get_register(): [0] reading register t2 on hart 0
Debug: 62073 152918 riscv-013.c:765 execute_abstract_command(): command=0x221007; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1007
Debug: 62119 152919 riscv-013.c:1415 register_read_direct(): {0} t2 = 0x0
Debug: 62120 152919 riscv.c:2795 riscv_get_register_on_hart(): {0} t2: 0
Debug: 62121 152919 riscv.c:3071 register_get(): [0]{0} read 0x0 from t2 (valid=1)
Debug: 62122 152919 riscv-013.c:3416 riscv013_get_register(): [0] reading register s0 on hart 0
Debug: 62123 152919 riscv-013.c:765 execute_abstract_command(): command=0x221008; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1008
Debug: 62169 152921 riscv-013.c:1415 register_read_direct(): {0} s0 = 0x0
Debug: 62170 152921 riscv.c:2795 riscv_get_register_on_hart(): {0} s0: 0
Debug: 62171 152921 riscv.c:3071 register_get(): [0]{0} read 0x0 from fp (valid=1)
Debug: 62172 152921 riscv-013.c:3416 riscv013_get_register(): [0] reading register s1 on hart 0
Debug: 62173 152921 riscv-013.c:765 execute_abstract_command(): command=0x221009; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1009
Debug: 62219 152922 riscv-013.c:1415 register_read_direct(): {0} s1 = 0x0
Debug: 62220 152922 riscv.c:2795 riscv_get_register_on_hart(): {0} s1: 0
Debug: 62221 152922 riscv.c:3071 register_get(): [0]{0} read 0x0 from s1 (valid=1)
Debug: 62222 152922 riscv-013.c:3416 riscv013_get_register(): [0] reading register a0 on hart 0
Debug: 62223 152922 riscv-013.c:765 execute_abstract_command(): command=0x22100a; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100a
Debug: 62269 152924 riscv-013.c:1415 register_read_direct(): {0} a0 = 0x0
Debug: 62270 152924 riscv.c:2795 riscv_get_register_on_hart(): {0} a0: 0
Debug: 62271 152924 riscv.c:3071 register_get(): [0]{0} read 0x0 from a0 (valid=1)
Debug: 62272 152924 riscv-013.c:3416 riscv013_get_register(): [0] reading register a1 on hart 0
Debug: 62273 152924 riscv-013.c:765 execute_abstract_command(): command=0x22100b; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100b
Debug: 62319 152925 riscv-013.c:1415 register_read_direct(): {0} a1 = 0x3fc94968
Debug: 62320 152925 riscv.c:2795 riscv_get_register_on_hart(): {0} a1: 3fc94968
Debug: 62321 152925 riscv.c:3071 register_get(): [0]{0} read 0x3fc94968 from a1 (valid=1)
Debug: 62322 152925 riscv-013.c:3416 riscv013_get_register(): [0] reading register a2 on hart 0
Debug: 62323 152925 riscv-013.c:765 execute_abstract_command(): command=0x22100c; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100c
Debug: 62369 152927 riscv-013.c:1415 register_read_direct(): {0} a2 = 0x8
Debug: 62370 152927 riscv.c:2795 riscv_get_register_on_hart(): {0} a2: 8
Debug: 62371 152927 riscv.c:3071 register_get(): [0]{0} read 0x8 from a2 (valid=1)
Debug: 62372 152927 riscv-013.c:3416 riscv013_get_register(): [0] reading register a3 on hart 0
Debug: 62373 152927 riscv-013.c:765 execute_abstract_command(): command=0x22100d; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100d
Debug: 62419 152929 riscv-013.c:1415 register_read_direct(): {0} a3 = 0x0
Debug: 62420 152929 riscv.c:2795 riscv_get_register_on_hart(): {0} a3: 0
Debug: 62421 152929 riscv.c:3071 register_get(): [0]{0} read 0x0 from a3 (valid=1)
Debug: 62422 152929 riscv-013.c:3416 riscv013_get_register(): [0] reading register a4 on hart 0
Debug: 62423 152929 riscv-013.c:765 execute_abstract_command(): command=0x22100e; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100e
Debug: 62469 152930 riscv-013.c:1415 register_read_direct(): {0} a4 = 0x1
Debug: 62470 152930 riscv.c:2795 riscv_get_register_on_hart(): {0} a4: 1
Debug: 62471 152930 riscv.c:3071 register_get(): [0]{0} read 0x1 from a4 (valid=1)
Debug: 62472 152930 riscv-013.c:3416 riscv013_get_register(): [0] reading register a5 on hart 0
Debug: 62473 152930 riscv-013.c:765 execute_abstract_command(): command=0x22100f; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100f
Debug: 62519 152932 riscv-013.c:1415 register_read_direct(): {0} a5 = 0x600c2000
Debug: 62520 152932 riscv.c:2795 riscv_get_register_on_hart(): {0} a5: 600c2000
Debug: 62521 152932 riscv.c:3071 register_get(): [0]{0} read 0x600c2000 from a5 (valid=1)
Debug: 62522 152932 riscv-013.c:3416 riscv013_get_register(): [0] reading register a6 on hart 0
Debug: 62523 152932 riscv-013.c:765 execute_abstract_command(): command=0x221010; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1010
Debug: 62569 152933 riscv-013.c:1415 register_read_direct(): {0} a6 = 0x1
Debug: 62570 152933 riscv.c:2795 riscv_get_register_on_hart(): {0} a6: 1
Debug: 62571 152933 riscv.c:3071 register_get(): [0]{0} read 0x1 from a6 (valid=1)
Debug: 62572 152933 riscv-013.c:3416 riscv013_get_register(): [0] reading register a7 on hart 0
Debug: 62573 152933 riscv-013.c:765 execute_abstract_command(): command=0x221011; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1011
Debug: 62619 152935 riscv-013.c:1415 register_read_direct(): {0} a7 = 0x3fc9f82c
Debug: 62620 152935 riscv.c:2795 riscv_get_register_on_hart(): {0} a7: 3fc9f82c
Debug: 62621 152935 riscv.c:3071 register_get(): [0]{0} read 0x3fc9f82c from a7 (valid=1)
Debug: 62622 152935 riscv-013.c:3416 riscv013_get_register(): [0] reading register s2 on hart 0
Debug: 62623 152935 riscv-013.c:765 execute_abstract_command(): command=0x221012; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1012
Debug: 62669 152937 riscv-013.c:1415 register_read_direct(): {0} s2 = 0x0
Debug: 62670 152937 riscv.c:2795 riscv_get_register_on_hart(): {0} s2: 0
Debug: 62671 152937 riscv.c:3071 register_get(): [0]{0} read 0x0 from s2 (valid=1)
Debug: 62672 152937 riscv-013.c:3416 riscv013_get_register(): [0] reading register s3 on hart 0
Debug: 62673 152937 riscv-013.c:765 execute_abstract_command(): command=0x221013; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1013
Debug: 62719 152938 riscv-013.c:1415 register_read_direct(): {0} s3 = 0x0
Debug: 62720 152938 riscv.c:2795 riscv_get_register_on_hart(): {0} s3: 0
Debug: 62721 152938 riscv.c:3071 register_get(): [0]{0} read 0x0 from s3 (valid=1)
Debug: 62722 152938 riscv-013.c:3416 riscv013_get_register(): [0] reading register s4 on hart 0
Debug: 62723 152938 riscv-013.c:765 execute_abstract_command(): command=0x221014; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1014
Debug: 62769 152940 riscv-013.c:1415 register_read_direct(): {0} s4 = 0x0
Debug: 62770 152940 riscv.c:2795 riscv_get_register_on_hart(): {0} s4: 0
Debug: 62771 152940 riscv.c:3071 register_get(): [0]{0} read 0x0 from s4 (valid=1)
Debug: 62772 152940 riscv-013.c:3416 riscv013_get_register(): [0] reading register s5 on hart 0
Debug: 62773 152940 riscv-013.c:765 execute_abstract_command(): command=0x221015; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1015
Debug: 62819 152941 riscv-013.c:1415 register_read_direct(): {0} s5 = 0x0
Debug: 62820 152941 riscv.c:2795 riscv_get_register_on_hart(): {0} s5: 0
Debug: 62821 152941 riscv.c:3071 register_get(): [0]{0} read 0x0 from s5 (valid=1)
Debug: 62822 152941 riscv-013.c:3416 riscv013_get_register(): [0] reading register s6 on hart 0
Debug: 62823 152941 riscv-013.c:765 execute_abstract_command(): command=0x221016; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1016
Debug: 62869 152943 riscv-013.c:1415 register_read_direct(): {0} s6 = 0x0
Debug: 62870 152943 riscv.c:2795 riscv_get_register_on_hart(): {0} s6: 0
Debug: 62871 152943 riscv.c:3071 register_get(): [0]{0} read 0x0 from s6 (valid=1)
Debug: 62872 152943 riscv-013.c:3416 riscv013_get_register(): [0] reading register s7 on hart 0
Debug: 62873 152943 riscv-013.c:765 execute_abstract_command(): command=0x221017; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1017
Debug: 62919 152944 riscv-013.c:1415 register_read_direct(): {0} s7 = 0x0
Debug: 62920 152945 riscv.c:2795 riscv_get_register_on_hart(): {0} s7: 0
Debug: 62921 152945 riscv.c:3071 register_get(): [0]{0} read 0x0 from s7 (valid=1)
Debug: 62922 152945 riscv-013.c:3416 riscv013_get_register(): [0] reading register s8 on hart 0
Debug: 62923 152945 riscv-013.c:765 execute_abstract_command(): command=0x221018; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1018
Debug: 62969 152946 riscv-013.c:1415 register_read_direct(): {0} s8 = 0x0
Debug: 62970 152946 riscv.c:2795 riscv_get_register_on_hart(): {0} s8: 0
Debug: 62971 152946 riscv.c:3071 register_get(): [0]{0} read 0x0 from s8 (valid=1)
Debug: 62972 152946 riscv-013.c:3416 riscv013_get_register(): [0] reading register s9 on hart 0
Debug: 62973 152946 riscv-013.c:765 execute_abstract_command(): command=0x221019; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1019
Debug: 63019 152948 riscv-013.c:1415 register_read_direct(): {0} s9 = 0x0
Debug: 63020 152948 riscv.c:2795 riscv_get_register_on_hart(): {0} s9: 0
Debug: 63021 152948 riscv.c:3071 register_get(): [0]{0} read 0x0 from s9 (valid=1)
Debug: 63022 152948 riscv-013.c:3416 riscv013_get_register(): [0] reading register s10 on hart 0
Debug: 63023 152948 riscv-013.c:765 execute_abstract_command(): command=0x22101a; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101a
Debug: 63069 152949 riscv-013.c:1415 register_read_direct(): {0} s10 = 0x0
Debug: 63070 152949 riscv.c:2795 riscv_get_register_on_hart(): {0} s10: 0
Debug: 63071 152949 riscv.c:3071 register_get(): [0]{0} read 0x0 from s10 (valid=1)
Debug: 63072 152949 riscv-013.c:3416 riscv013_get_register(): [0] reading register s11 on hart 0
Debug: 63073 152949 riscv-013.c:765 execute_abstract_command(): command=0x22101b; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101b
Debug: 63119 152951 riscv-013.c:1415 register_read_direct(): {0} s11 = 0x0
Debug: 63120 152951 riscv.c:2795 riscv_get_register_on_hart(): {0} s11: 0
Debug: 63121 152951 riscv.c:3071 register_get(): [0]{0} read 0x0 from s11 (valid=1)
Debug: 63122 152951 riscv-013.c:3416 riscv013_get_register(): [0] reading register t3 on hart 0
Debug: 63123 152951 riscv-013.c:765 execute_abstract_command(): command=0x22101c; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101c
Debug: 63169 152952 riscv-013.c:1415 register_read_direct(): {0} t3 = 0x0
Debug: 63170 152953 riscv.c:2795 riscv_get_register_on_hart(): {0} t3: 0
Debug: 63171 152953 riscv.c:3071 register_get(): [0]{0} read 0x0 from t3 (valid=1)
Debug: 63172 152953 riscv-013.c:3416 riscv013_get_register(): [0] reading register t4 on hart 0
Debug: 63173 152953 riscv-013.c:765 execute_abstract_command(): command=0x22101d; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101d
Debug: 63219 152954 riscv-013.c:1415 register_read_direct(): {0} t4 = 0x0
Debug: 63220 152954 riscv.c:2795 riscv_get_register_on_hart(): {0} t4: 0
Debug: 63221 152954 riscv.c:3071 register_get(): [0]{0} read 0x0 from t4 (valid=1)
Debug: 63222 152954 riscv-013.c:3416 riscv013_get_register(): [0] reading register t5 on hart 0
Debug: 63223 152954 riscv-013.c:765 execute_abstract_command(): command=0x22101e; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101e
Debug: 63269 152956 riscv-013.c:1415 register_read_direct(): {0} t5 = 0x0
Debug: 63270 152956 riscv.c:2795 riscv_get_register_on_hart(): {0} t5: 0
Debug: 63271 152956 riscv.c:3071 register_get(): [0]{0} read 0x0 from t5 (valid=1)
Debug: 63272 152956 riscv-013.c:3416 riscv013_get_register(): [0] reading register t6 on hart 0
Debug: 63273 152956 riscv-013.c:765 execute_abstract_command(): command=0x22101f; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101f
Debug: 63319 152957 riscv-013.c:1415 register_read_direct(): {0} t6 = 0x0
Debug: 63320 152957 riscv.c:2795 riscv_get_register_on_hart(): {0} t6: 0
Debug: 63321 152957 riscv.c:3071 register_get(): [0]{0} read 0x0 from t6 (valid=1)
Debug: 63322 152957 riscv-013.c:3416 riscv013_get_register(): [0] reading register pc on hart 0
Debug: 63323 152957 riscv-013.c:765 execute_abstract_command(): command=0x2207b1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b1
Debug: 63369 152959 riscv-013.c:1415 register_read_direct(): {0} dpc = 0x4202a00c
Debug: 63370 152959 riscv-013.c:3424 riscv013_get_register(): [0] read PC from DPC: 0x4202a00c
Debug: 63371 152959 riscv.c:2795 riscv_get_register_on_hart(): {0} pc: 4202a00c
Debug: 63372 152959 riscv.c:3071 register_get(): [0]{0} read 0x4202a00c from pc (valid=1)
Debug: 63373 152959 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$00000000c8820042e0e0c93f00fcc83f288fc73fa67f05400f000000000000000000000000000000000000006849c93f08000000000000000100000000200c60010000002cf8c93f00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ca00242#1e'
Debug: 63374 152959 gdb_server.c:3358 gdb_input_inner(): received packet: 'vCont;s:3fc9ed78;c'
Debug: 63375 152959 FreeRTOS.c:405 FreeRTOS_find_target_from_threadid(): Find target for thr 0x3fc9ed78
Debug: 63376 152959 FreeRTOS.c:433 FreeRTOS_target_for_threadid(): target found : esp32c3
Debug: 63377 152959 gdb_server.c:2912 gdb_handle_vcont_packet(): target esp32c3 single-step thread 3fc9ed78
Debug: 63378 152959 target.c:1634 target_call_event_callbacks(): target event 5 (gdb-start) for core esp32c3
Debug: 63379 152959 riscv.c:965 old_or_new_riscv_step(): handle_breakpoints=0
Debug: 63380 152959 riscv.c:1845 riscv_openocd_step(): stepping rtos hart
Debug: 63381 152959 riscv.c:2624 riscv_step_rtos_hart(): stepping hart 0
Debug: 63400 152960 riscv.c:2699 riscv_invalidate_register_cache(): [0]
Debug: 63401 152960 program.c:33 riscv_program_write(): debug_buffer[00] = DASM(0x0000100f)
Debug: 63402 152960 riscv-013.c:3695 riscv013_write_debug_buffer(): cache hit for 0x100f @0
Debug: 63403 152960 program.c:33 riscv_program_write(): debug_buffer[01] = DASM(0x0000000f)
Debug: 63404 152960 riscv-013.c:3695 riscv013_write_debug_buffer(): cache hit for 0xf @1
Debug: 63405 152960 program.c:33 riscv_program_write(): debug_buffer[02] = DASM(0x00100073)
Debug: 63406 152960 riscv-013.c:3695 riscv013_write_debug_buffer(): cache hit for 0x100073 @2
Debug: 63407 152960 riscv-013.c:765 execute_abstract_command(): command=0x241000; access register, size=32, postexec=1, transfer=0, write=0, regno=0x1000
Debug: 63435 152961 program.c:33 riscv_program_write(): debug_buffer[00] = DASM(0x0000100f)
Debug: 63436 152961 riscv-013.c:3695 riscv013_write_debug_buffer(): cache hit for 0x100f @0
Debug: 63437 152961 program.c:33 riscv_program_write(): debug_buffer[01] = DASM(0x0000000f)
Debug: 63438 152961 riscv-013.c:3695 riscv013_write_debug_buffer(): cache hit for 0xf @1
Debug: 63439 152961 program.c:33 riscv_program_write(): debug_buffer[02] = DASM(0x00100073)
Debug: 63440 152961 riscv-013.c:3695 riscv013_write_debug_buffer(): cache hit for 0x100073 @2
Debug: 63441 152961 riscv-013.c:765 execute_abstract_command(): command=0x241000; access register, size=32, postexec=1, transfer=0, write=0, regno=0x1000
Debug: 63469 152962 riscv-013.c:765 execute_abstract_command(): command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0
Debug: 63515 152963 riscv-013.c:1415 register_read_direct(): {0} dcsr = 0x4000b107
Debug: 63516 152963 riscv.c:2756 riscv_set_register_on_hart(): {0} dcsr <- 4000b107
Debug: 63517 152963 riscv-013.c:3440 riscv013_set_register(): [0] writing 0x4000b107 to register dcsr on hart 0
Debug: 63518 152963 riscv-013.c:1227 register_write_direct(): {0} dcsr <- 0x4000b107
Debug: 63537 152964 riscv-013.c:765 execute_abstract_command(): command=0x2307b0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b0
Debug: 63565 152965 riscv-013.c:4130 riscv013_step_or_resume_current_hart(): resuming hart 0 (for step?=1)
Debug: 63638 152968 riscv.c:2699 riscv_invalidate_register_cache(): [0]
Debug: 63657 152968 target.c:1634 target_call_event_callbacks(): target event 2 (resumed) for core esp32c3
Debug: 63658 152968 target.c:1634 target_call_event_callbacks(): target event 0 (gdb-halt) for core esp32c3
Debug: 63659 152968 target.c:1634 target_call_event_callbacks(): target event 1 (halted) for core esp32c3
Debug: 63660 152968 target.c:4631 target_handle_event(): target(0): esp32c3 (riscv) event: 1 (halted) action:  esp32c3_wdt_disable 
Debug: 63661 152968 command.c:143 script_debug(): command - command command mode
Debug: 63662 152968 command.c:143 script_debug(): command - mww mww 0x6001f064 0x50D83AA1
Debug: 63682 152969 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$O#4f'
Debug: 63719 152970 riscv-013.c:3076 write_memory_bus_v1(): transferring burst starting at address 0x6001f064
Debug: 63720 152970 riscv-013.c:2072 log_memory_access(): M[0x6001f064] writes 0x50d83aa1
Debug: 63730 152971 batch.c:164 dump_field(): 41b 5i w 50d83aa1 @3c -> + 00000000 @39
Debug: 63731 152971 batch.c:164 dump_field(): 41b 5i - 00000000 @00 -> + 50d83aa1 @3c
Debug: 63741 152971 command.c:143 script_debug(): command - mww mww 0x6001F048 0
Debug: 63761 152972 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$O#4f'
Debug: 63798 152973 riscv-013.c:3076 write_memory_bus_v1(): transferring burst starting at address 0x6001f048
Debug: 63799 152973 riscv-013.c:2072 log_memory_access(): M[0x6001f048] writes 0x00000000
Debug: 63809 152973 batch.c:164 dump_field(): 41b 5i w 00000000 @3c -> + 00000000 @39
Debug: 63810 152973 batch.c:164 dump_field(): 41b 5i - 00000000 @00 -> + 00000000 @3c
Debug: 63820 152974 command.c:143 script_debug(): command - mww mww 0x60020064 0x50D83AA1
Debug: 63840 152974 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$O#4f'
Debug: 63877 152976 riscv-013.c:3076 write_memory_bus_v1(): transferring burst starting at address 0x60020064
Debug: 63878 152976 riscv-013.c:2072 log_memory_access(): M[0x60020064] writes 0x50d83aa1
Debug: 63888 152976 batch.c:164 dump_field(): 41b 5i w 50d83aa1 @3c -> + 00000000 @39
Debug: 63889 152976 batch.c:164 dump_field(): 41b 5i - 00000000 @00 -> + 50d83aa1 @3c
Debug: 63899 152976 command.c:143 script_debug(): command - mww mww 0x60020048 0
Debug: 63919 152977 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$O#4f'
Debug: 63956 152978 riscv-013.c:3076 write_memory_bus_v1(): transferring burst starting at address 0x60020048
Debug: 63957 152978 riscv-013.c:2072 log_memory_access(): M[0x60020048] writes 0x00000000
Debug: 63967 152979 batch.c:164 dump_field(): 41b 5i w 00000000 @3c -> + 00000000 @39
Debug: 63968 152979 batch.c:164 dump_field(): 41b 5i - 00000000 @00 -> + 00000000 @3c
Debug: 63978 152979 command.c:143 script_debug(): command - mww mww 0x600080a8 0x50D83AA1
Debug: 63998 152979 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$O#4f'
Debug: 64035 152981 riscv-013.c:3076 write_memory_bus_v1(): transferring burst starting at address 0x600080a8
Debug: 64036 152981 riscv-013.c:2072 log_memory_access(): M[0x600080a8] writes 0x50d83aa1
Debug: 64046 152981 batch.c:164 dump_field(): 41b 5i w 50d83aa1 @3c -> + 00000000 @39
Debug: 64047 152981 batch.c:164 dump_field(): 41b 5i - 00000000 @00 -> + 50d83aa1 @3c
Debug: 64057 152982 command.c:143 script_debug(): command - mww mww 0x60008090 0
Debug: 64077 152982 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$O#4f'
Debug: 64114 152983 riscv-013.c:3076 write_memory_bus_v1(): transferring burst starting at address 0x60008090
Debug: 64115 152983 riscv-013.c:2072 log_memory_access(): M[0x60008090] writes 0x00000000
Debug: 64125 152984 batch.c:164 dump_field(): 41b 5i w 00000000 @3c -> + 00000000 @39
Debug: 64126 152984 batch.c:164 dump_field(): 41b 5i - 00000000 @00 -> + 00000000 @3c
Debug: 64136 152984 target.c:1634 target_call_event_callbacks(): target event 6 (gdb-end) for core esp32c3
Debug: 64155 152985 FreeRTOS.c:694 FreeRTOS_update_threads(): FreeRTOS_update_threads
Debug: 64210 152986 riscv-013.c:2072 log_memory_access(): M[0x3fc97e8c] reads 0x00000004
Debug: 64229 152987 target.c:2447 target_read_u32(): address: 0x3fc97e8c, value: 0x00000004
Debug: 64230 152987 FreeRTOS.c:745 FreeRTOS_update_threads(): Read uxCurrentNumberOfTasks at 0x3fc97e8c, value 4
Debug: 64285 152989 riscv-013.c:2072 log_memory_access(): M[0x3fc97e98] reads 0x00000004
Debug: 64304 152990 target.c:2447 target_read_u32(): address: 0x3fc97e98, value: 0x00000004
Debug: 64305 152990 FreeRTOS.c:766 FreeRTOS_update_threads(): Read uxTaskNumber at 0x3fc97e98, value 4
Error: 64306 152990 FreeRTOS.c:771 FreeRTOS_update_threads(): FreeRTOS uxTaskNumber seems to be corrupted!
Debug: 64307 152990 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$O4672656552544f532075785461736b4e756d626572207365656d7320746f20626520636f72727570746564210a#38'
Debug: 64308 152990 FreeRTOS.c:405 FreeRTOS_find_target_from_threadid(): Find target for thr 0x3fc9ed78
Debug: 64309 152990 FreeRTOS.c:433 FreeRTOS_target_for_threadid(): target found : esp32c3
Debug: 64310 152990 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$T05thread:3fc9ed78;#13'
Debug: 64311 152990 gdb_server.c:3358 gdb_input_inner(): received packet: 'g'
Debug: 64312 152990 riscv.c:1357 riscv_get_gdb_reg_list_internal(): rtos_hartid=0, current_hartid=0, reg_class=1, read=1
Debug: 64313 152990 riscv-013.c:3416 riscv013_get_register(): [0] reading register zero on hart 0
Debug: 64314 152990 riscv.c:2795 riscv_get_register_on_hart(): {0} zero: 0
Debug: 64315 152990 riscv.c:3071 register_get(): [0]{0} read 0x0 from zero (valid=1)
Debug: 64316 152990 riscv-013.c:3416 riscv013_get_register(): [0] reading register ra on hart 0
Debug: 64317 152990 riscv-013.c:765 execute_abstract_command(): command=0x221001; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1001
Debug: 64363 152991 riscv-013.c:1415 register_read_direct(): {0} ra = 0x420082c8
Debug: 64364 152991 riscv.c:2795 riscv_get_register_on_hart(): {0} ra: 420082c8
Debug: 64365 152991 riscv.c:3071 register_get(): [0]{0} read 0x420082c8 from ra (valid=1)
Debug: 64366 152991 riscv-013.c:3416 riscv013_get_register(): [0] reading register sp on hart 0
Debug: 64367 152991 riscv-013.c:765 execute_abstract_command(): command=0x221002; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1002
Debug: 64413 152993 riscv-013.c:1415 register_read_direct(): {0} sp = 0x3fc9e0e0
Debug: 64414 152993 riscv.c:2795 riscv_get_register_on_hart(): {0} sp: 3fc9e0e0
Debug: 64415 152993 riscv.c:3071 register_get(): [0]{0} read 0x3fc9e0e0 from sp (valid=1)
Debug: 64416 152993 riscv-013.c:3416 riscv013_get_register(): [0] reading register gp on hart 0
Debug: 64417 152993 riscv-013.c:765 execute_abstract_command(): command=0x221003; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1003
Debug: 64463 152994 riscv-013.c:1415 register_read_direct(): {0} gp = 0x3fc8fc00
Debug: 64464 152994 riscv.c:2795 riscv_get_register_on_hart(): {0} gp: 3fc8fc00
Debug: 64465 152995 riscv.c:3071 register_get(): [0]{0} read 0x3fc8fc00 from gp (valid=1)
Debug: 64466 152995 riscv-013.c:3416 riscv013_get_register(): [0] reading register tp on hart 0
Debug: 64467 152995 riscv-013.c:765 execute_abstract_command(): command=0x221004; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1004
Debug: 64513 152996 riscv-013.c:1415 register_read_direct(): {0} tp = 0x3fc78f28
Debug: 64514 152996 riscv.c:2795 riscv_get_register_on_hart(): {0} tp: 3fc78f28
Debug: 64515 152996 riscv.c:3071 register_get(): [0]{0} read 0x3fc78f28 from tp (valid=1)
Debug: 64516 152996 riscv-013.c:3416 riscv013_get_register(): [0] reading register t0 on hart 0
Debug: 64517 152996 riscv-013.c:765 execute_abstract_command(): command=0x221005; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1005
Debug: 64563 152998 riscv-013.c:1415 register_read_direct(): {0} t0 = 0x40057fa6
Debug: 64564 152998 riscv.c:2795 riscv_get_register_on_hart(): {0} t0: 40057fa6
Debug: 64565 152998 riscv.c:3071 register_get(): [0]{0} read 0x40057fa6 from t0 (valid=1)
Debug: 64566 152998 riscv-013.c:3416 riscv013_get_register(): [0] reading register t1 on hart 0
Debug: 64567 152998 riscv-013.c:765 execute_abstract_command(): command=0x221006; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1006
Debug: 64613 152999 riscv-013.c:1415 register_read_direct(): {0} t1 = 0xf
Debug: 64614 152999 riscv.c:2795 riscv_get_register_on_hart(): {0} t1: f
Debug: 64615 152999 riscv.c:3071 register_get(): [0]{0} read 0xf from t1 (valid=1)
Debug: 64616 152999 riscv-013.c:3416 riscv013_get_register(): [0] reading register t2 on hart 0
Debug: 64617 152999 riscv-013.c:765 execute_abstract_command(): command=0x221007; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1007
Debug: 64663 153001 riscv-013.c:1415 register_read_direct(): {0} t2 = 0x0
Debug: 64664 153001 riscv.c:2795 riscv_get_register_on_hart(): {0} t2: 0
Debug: 64665 153001 riscv.c:3071 register_get(): [0]{0} read 0x0 from t2 (valid=1)
Debug: 64666 153001 riscv-013.c:3416 riscv013_get_register(): [0] reading register s0 on hart 0
Debug: 64667 153001 riscv-013.c:765 execute_abstract_command(): command=0x221008; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1008
Debug: 64713 153003 riscv-013.c:1415 register_read_direct(): {0} s0 = 0x0
Debug: 64714 153003 riscv.c:2795 riscv_get_register_on_hart(): {0} s0: 0
Debug: 64715 153003 riscv.c:3071 register_get(): [0]{0} read 0x0 from fp (valid=1)
Debug: 64716 153003 riscv-013.c:3416 riscv013_get_register(): [0] reading register s1 on hart 0
Debug: 64717 153003 riscv-013.c:765 execute_abstract_command(): command=0x221009; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1009
Debug: 64763 153004 riscv-013.c:1415 register_read_direct(): {0} s1 = 0x0
Debug: 64764 153004 riscv.c:2795 riscv_get_register_on_hart(): {0} s1: 0
Debug: 64765 153004 riscv.c:3071 register_get(): [0]{0} read 0x0 from s1 (valid=1)
Debug: 64766 153004 riscv-013.c:3416 riscv013_get_register(): [0] reading register a0 on hart 0
Debug: 64767 153004 riscv-013.c:765 execute_abstract_command(): command=0x22100a; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100a
Debug: 64813 153006 riscv-013.c:1415 register_read_direct(): {0} a0 = 0x0
Debug: 64814 153006 riscv.c:2795 riscv_get_register_on_hart(): {0} a0: 0
Debug: 64815 153006 riscv.c:3071 register_get(): [0]{0} read 0x0 from a0 (valid=1)
Debug: 64816 153006 riscv-013.c:3416 riscv013_get_register(): [0] reading register a1 on hart 0
Debug: 64817 153006 riscv-013.c:765 execute_abstract_command(): command=0x22100b; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100b
Debug: 64863 153007 riscv-013.c:1415 register_read_direct(): {0} a1 = 0x3fc94968
Debug: 64864 153007 riscv.c:2795 riscv_get_register_on_hart(): {0} a1: 3fc94968
Debug: 64865 153007 riscv.c:3071 register_get(): [0]{0} read 0x3fc94968 from a1 (valid=1)
Debug: 64866 153007 riscv-013.c:3416 riscv013_get_register(): [0] reading register a2 on hart 0
Debug: 64867 153007 riscv-013.c:765 execute_abstract_command(): command=0x22100c; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100c
Debug: 64913 153009 riscv-013.c:1415 register_read_direct(): {0} a2 = 0x3
Debug: 64914 153009 riscv.c:2795 riscv_get_register_on_hart(): {0} a2: 3
Debug: 64915 153009 riscv.c:3071 register_get(): [0]{0} read 0x3 from a2 (valid=1)
Debug: 64916 153009 riscv-013.c:3416 riscv013_get_register(): [0] reading register a3 on hart 0
Debug: 64917 153009 riscv-013.c:765 execute_abstract_command(): command=0x22100d; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100d
Debug: 64963 153010 riscv-013.c:1415 register_read_direct(): {0} a3 = 0x0
Debug: 64964 153010 riscv.c:2795 riscv_get_register_on_hart(): {0} a3: 0
Debug: 64965 153010 riscv.c:3071 register_get(): [0]{0} read 0x0 from a3 (valid=1)
Debug: 64966 153010 riscv-013.c:3416 riscv013_get_register(): [0] reading register a4 on hart 0
Debug: 64967 153010 riscv-013.c:765 execute_abstract_command(): command=0x22100e; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100e
Debug: 65013 153012 riscv-013.c:1415 register_read_direct(): {0} a4 = 0x1
Debug: 65014 153012 riscv.c:2795 riscv_get_register_on_hart(): {0} a4: 1
Debug: 65015 153012 riscv.c:3071 register_get(): [0]{0} read 0x1 from a4 (valid=1)
Debug: 65016 153012 riscv-013.c:3416 riscv013_get_register(): [0] reading register a5 on hart 0
Debug: 65017 153012 riscv-013.c:765 execute_abstract_command(): command=0x22100f; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100f
Debug: 65063 153014 riscv-013.c:1415 register_read_direct(): {0} a5 = 0x600c2000
Debug: 65064 153014 riscv.c:2795 riscv_get_register_on_hart(): {0} a5: 600c2000
Debug: 65065 153014 riscv.c:3071 register_get(): [0]{0} read 0x600c2000 from a5 (valid=1)
Debug: 65066 153014 riscv-013.c:3416 riscv013_get_register(): [0] reading register a6 on hart 0
Debug: 65067 153014 riscv-013.c:765 execute_abstract_command(): command=0x221010; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1010
Debug: 65113 153015 riscv-013.c:1415 register_read_direct(): {0} a6 = 0x1
Debug: 65114 153015 riscv.c:2795 riscv_get_register_on_hart(): {0} a6: 1
Debug: 65115 153015 riscv.c:3071 register_get(): [0]{0} read 0x1 from a6 (valid=1)
Debug: 65116 153015 riscv-013.c:3416 riscv013_get_register(): [0] reading register a7 on hart 0
Debug: 65117 153015 riscv-013.c:765 execute_abstract_command(): command=0x221011; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1011
Debug: 65163 153017 riscv-013.c:1415 register_read_direct(): {0} a7 = 0x3fc9f82c
Debug: 65164 153017 riscv.c:2795 riscv_get_register_on_hart(): {0} a7: 3fc9f82c
Debug: 65165 153017 riscv.c:3071 register_get(): [0]{0} read 0x3fc9f82c from a7 (valid=1)
Debug: 65166 153017 riscv-013.c:3416 riscv013_get_register(): [0] reading register s2 on hart 0
Debug: 65167 153017 riscv-013.c:765 execute_abstract_command(): command=0x221012; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1012
Debug: 65213 153018 riscv-013.c:1415 register_read_direct(): {0} s2 = 0x0
Debug: 65214 153018 riscv.c:2795 riscv_get_register_on_hart(): {0} s2: 0
Debug: 65215 153018 riscv.c:3071 register_get(): [0]{0} read 0x0 from s2 (valid=1)
Debug: 65216 153018 riscv-013.c:3416 riscv013_get_register(): [0] reading register s3 on hart 0
Debug: 65217 153018 riscv-013.c:765 execute_abstract_command(): command=0x221013; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1013
Debug: 65263 153020 riscv-013.c:1415 register_read_direct(): {0} s3 = 0x0
Debug: 65264 153020 riscv.c:2795 riscv_get_register_on_hart(): {0} s3: 0
Debug: 65265 153020 riscv.c:3071 register_get(): [0]{0} read 0x0 from s3 (valid=1)
Debug: 65266 153020 riscv-013.c:3416 riscv013_get_register(): [0] reading register s4 on hart 0
Debug: 65267 153020 riscv-013.c:765 execute_abstract_command(): command=0x221014; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1014
Debug: 65313 153022 riscv-013.c:1415 register_read_direct(): {0} s4 = 0x0
Debug: 65314 153022 riscv.c:2795 riscv_get_register_on_hart(): {0} s4: 0
Debug: 65315 153022 riscv.c:3071 register_get(): [0]{0} read 0x0 from s4 (valid=1)
Debug: 65316 153022 riscv-013.c:3416 riscv013_get_register(): [0] reading register s5 on hart 0
Debug: 65317 153022 riscv-013.c:765 execute_abstract_command(): command=0x221015; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1015
Debug: 65363 153023 riscv-013.c:1415 register_read_direct(): {0} s5 = 0x0
Debug: 65364 153023 riscv.c:2795 riscv_get_register_on_hart(): {0} s5: 0
Debug: 65365 153023 riscv.c:3071 register_get(): [0]{0} read 0x0 from s5 (valid=1)
Debug: 65366 153023 riscv-013.c:3416 riscv013_get_register(): [0] reading register s6 on hart 0
Debug: 65367 153023 riscv-013.c:765 execute_abstract_command(): command=0x221016; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1016
Debug: 65413 153025 riscv-013.c:1415 register_read_direct(): {0} s6 = 0x0
Debug: 65414 153025 riscv.c:2795 riscv_get_register_on_hart(): {0} s6: 0
Debug: 65415 153025 riscv.c:3071 register_get(): [0]{0} read 0x0 from s6 (valid=1)
Debug: 65416 153025 riscv-013.c:3416 riscv013_get_register(): [0] reading register s7 on hart 0
Debug: 65417 153025 riscv-013.c:765 execute_abstract_command(): command=0x221017; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1017
Debug: 65463 153026 riscv-013.c:1415 register_read_direct(): {0} s7 = 0x0
Debug: 65464 153026 riscv.c:2795 riscv_get_register_on_hart(): {0} s7: 0
Debug: 65465 153026 riscv.c:3071 register_get(): [0]{0} read 0x0 from s7 (valid=1)
Debug: 65466 153026 riscv-013.c:3416 riscv013_get_register(): [0] reading register s8 on hart 0
Debug: 65467 153026 riscv-013.c:765 execute_abstract_command(): command=0x221018; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1018
Debug: 65513 153028 riscv-013.c:1415 register_read_direct(): {0} s8 = 0x0
Debug: 65514 153028 riscv.c:2795 riscv_get_register_on_hart(): {0} s8: 0
Debug: 65515 153028 riscv.c:3071 register_get(): [0]{0} read 0x0 from s8 (valid=1)
Debug: 65516 153028 riscv-013.c:3416 riscv013_get_register(): [0] reading register s9 on hart 0
Debug: 65517 153028 riscv-013.c:765 execute_abstract_command(): command=0x221019; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1019
Debug: 65563 153030 riscv-013.c:1415 register_read_direct(): {0} s9 = 0x0
Debug: 65564 153030 riscv.c:2795 riscv_get_register_on_hart(): {0} s9: 0
Debug: 65565 153030 riscv.c:3071 register_get(): [0]{0} read 0x0 from s9 (valid=1)
Debug: 65566 153030 riscv-013.c:3416 riscv013_get_register(): [0] reading register s10 on hart 0
Debug: 65567 153030 riscv-013.c:765 execute_abstract_command(): command=0x22101a; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101a
Debug: 65613 153031 riscv-013.c:1415 register_read_direct(): {0} s10 = 0x0
Debug: 65614 153031 riscv.c:2795 riscv_get_register_on_hart(): {0} s10: 0
Debug: 65615 153031 riscv.c:3071 register_get(): [0]{0} read 0x0 from s10 (valid=1)
Debug: 65616 153031 riscv-013.c:3416 riscv013_get_register(): [0] reading register s11 on hart 0
Debug: 65617 153031 riscv-013.c:765 execute_abstract_command(): command=0x22101b; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101b
Debug: 65663 153033 riscv-013.c:1415 register_read_direct(): {0} s11 = 0x0
Debug: 65664 153033 riscv.c:2795 riscv_get_register_on_hart(): {0} s11: 0
Debug: 65665 153033 riscv.c:3071 register_get(): [0]{0} read 0x0 from s11 (valid=1)
Debug: 65666 153033 riscv-013.c:3416 riscv013_get_register(): [0] reading register t3 on hart 0
Debug: 65667 153033 riscv-013.c:765 execute_abstract_command(): command=0x22101c; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101c
Debug: 65713 153034 riscv-013.c:1415 register_read_direct(): {0} t3 = 0x0
Debug: 65714 153034 riscv.c:2795 riscv_get_register_on_hart(): {0} t3: 0
Debug: 65715 153034 riscv.c:3071 register_get(): [0]{0} read 0x0 from t3 (valid=1)
Debug: 65716 153034 riscv-013.c:3416 riscv013_get_register(): [0] reading register t4 on hart 0
Debug: 65717 153034 riscv-013.c:765 execute_abstract_command(): command=0x22101d; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101d
Debug: 65763 153036 riscv-013.c:1415 register_read_direct(): {0} t4 = 0x0
Debug: 65764 153036 riscv.c:2795 riscv_get_register_on_hart(): {0} t4: 0
Debug: 65765 153036 riscv.c:3071 register_get(): [0]{0} read 0x0 from t4 (valid=1)
Debug: 65766 153036 riscv-013.c:3416 riscv013_get_register(): [0] reading register t5 on hart 0
Debug: 65767 153036 riscv-013.c:765 execute_abstract_command(): command=0x22101e; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101e
Debug: 65813 153037 riscv-013.c:1415 register_read_direct(): {0} t5 = 0x0
Debug: 65814 153037 riscv.c:2795 riscv_get_register_on_hart(): {0} t5: 0
Debug: 65815 153037 riscv.c:3071 register_get(): [0]{0} read 0x0 from t5 (valid=1)
Debug: 65816 153037 riscv-013.c:3416 riscv013_get_register(): [0] reading register t6 on hart 0
Debug: 65817 153037 riscv-013.c:765 execute_abstract_command(): command=0x22101f; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101f
Debug: 65863 153039 riscv-013.c:1415 register_read_direct(): {0} t6 = 0x0
Debug: 65864 153039 riscv.c:2795 riscv_get_register_on_hart(): {0} t6: 0
Debug: 65865 153039 riscv.c:3071 register_get(): [0]{0} read 0x0 from t6 (valid=1)
Debug: 65866 153039 riscv-013.c:3416 riscv013_get_register(): [0] reading register pc on hart 0
Debug: 65867 153039 riscv-013.c:765 execute_abstract_command(): command=0x2207b1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b1
Debug: 65913 153040 riscv-013.c:1415 register_read_direct(): {0} dpc = 0x4202a00e
Debug: 65914 153041 riscv-013.c:3424 riscv013_get_register(): [0] read PC from DPC: 0x4202a00e
Debug: 65915 153041 riscv.c:2795 riscv_get_register_on_hart(): {0} pc: 4202a00e
Debug: 65916 153041 riscv.c:3071 register_get(): [0]{0} read 0x4202a00e from pc (valid=1)
Debug: 65917 153041 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$00000000c8820042e0e0c93f00fcc83f288fc73fa67f05400f000000000000000000000000000000000000006849c93f03000000000000000100000000200c60010000002cf8c93f00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ea00242#1b'
Debug: 65918 153041 gdb_server.c:3358 gdb_input_inner(): received packet: 'vCont;s:3fc9ed78;c'
Debug: 65919 153041 FreeRTOS.c:405 FreeRTOS_find_target_from_threadid(): Find target for thr 0x3fc9ed78
Debug: 65920 153041 FreeRTOS.c:433 FreeRTOS_target_for_threadid(): target found : esp32c3
Debug: 65921 153041 gdb_server.c:2912 gdb_handle_vcont_packet(): target esp32c3 single-step thread 3fc9ed78
Debug: 65922 153041 target.c:1634 target_call_event_callbacks(): target event 5 (gdb-start) for core esp32c3
Debug: 65923 153041 riscv.c:965 old_or_new_riscv_step(): handle_breakpoints=0
Debug: 65924 153041 riscv.c:1845 riscv_openocd_step(): stepping rtos hart
Debug: 65925 153041 riscv.c:2624 riscv_step_rtos_hart(): stepping hart 0
Debug: 65944 153041 riscv.c:2699 riscv_invalidate_register_cache(): [0]
Debug: 65945 153041 program.c:33 riscv_program_write(): debug_buffer[00] = DASM(0x0000100f)
Debug: 65946 153041 riscv-013.c:3695 riscv013_write_debug_buffer(): cache hit for 0x100f @0
Debug: 65947 153041 program.c:33 riscv_program_write(): debug_buffer[01] = DASM(0x0000000f)
Debug: 65948 153041 riscv-013.c:3695 riscv013_write_debug_buffer(): cache hit for 0xf @1
Debug: 65949 153041 program.c:33 riscv_program_write(): debug_buffer[02] = DASM(0x00100073)
Debug: 65950 153041 riscv-013.c:3695 riscv013_write_debug_buffer(): cache hit for 0x100073 @2
Debug: 65951 153041 riscv-013.c:765 execute_abstract_command(): command=0x241000; access register, size=32, postexec=1, transfer=0, write=0, regno=0x1000
Debug: 65979 153042 program.c:33 riscv_program_write(): debug_buffer[00] = DASM(0x0000100f)
Debug: 65980 153042 riscv-013.c:3695 riscv013_write_debug_buffer(): cache hit for 0x100f @0
Debug: 65981 153042 program.c:33 riscv_program_write(): debug_buffer[01] = DASM(0x0000000f)
Debug: 65982 153042 riscv-013.c:3695 riscv013_write_debug_buffer(): cache hit for 0xf @1
Debug: 65983 153042 program.c:33 riscv_program_write(): debug_buffer[02] = DASM(0x00100073)
Debug: 65984 153042 riscv-013.c:3695 riscv013_write_debug_buffer(): cache hit for 0x100073 @2
Debug: 65985 153042 riscv-013.c:765 execute_abstract_command(): command=0x241000; access register, size=32, postexec=1, transfer=0, write=0, regno=0x1000
Debug: 66013 153043 riscv-013.c:765 execute_abstract_command(): command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0
Debug: 66059 153045 riscv-013.c:1415 register_read_direct(): {0} dcsr = 0x4000b107
Debug: 66060 153045 riscv.c:2756 riscv_set_register_on_hart(): {0} dcsr <- 4000b107
Debug: 66061 153045 riscv-013.c:3440 riscv013_set_register(): [0] writing 0x4000b107 to register dcsr on hart 0
Debug: 66062 153045 riscv-013.c:1227 register_write_direct(): {0} dcsr <- 0x4000b107
Debug: 66081 153046 riscv-013.c:765 execute_abstract_command(): command=0x2307b0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b0
Debug: 66109 153046 riscv-013.c:4130 riscv013_step_or_resume_current_hart(): resuming hart 0 (for step?=1)
Debug: 66182 153049 riscv.c:2699 riscv_invalidate_register_cache(): [0]
Debug: 66201 153049 target.c:1634 target_call_event_callbacks(): target event 2 (resumed) for core esp32c3
Debug: 66202 153049 target.c:1634 target_call_event_callbacks(): target event 0 (gdb-halt) for core esp32c3
Debug: 66203 153049 target.c:1634 target_call_event_callbacks(): target event 1 (halted) for core esp32c3
Debug: 66204 153049 target.c:4631 target_handle_event(): target(0): esp32c3 (riscv) event: 1 (halted) action:  esp32c3_wdt_disable 
Debug: 66205 153049 command.c:143 script_debug(): command - command command mode
Debug: 66206 153049 command.c:143 script_debug(): command - mww mww 0x6001f064 0x50D83AA1
Debug: 66226 153050 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$O#4f'
Debug: 66263 153051 riscv-013.c:3076 write_memory_bus_v1(): transferring burst starting at address 0x6001f064
Debug: 66264 153051 riscv-013.c:2072 log_memory_access(): M[0x6001f064] writes 0x50d83aa1
Debug: 66274 153051 batch.c:164 dump_field(): 41b 5i w 50d83aa1 @3c -> + 00000000 @39
Debug: 66275 153051 batch.c:164 dump_field(): 41b 5i - 00000000 @00 -> + 50d83aa1 @3c
Debug: 66285 153052 command.c:143 script_debug(): command - mww mww 0x6001F048 0
Debug: 66305 153052 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$O#4f'
Debug: 66342 153053 riscv-013.c:3076 write_memory_bus_v1(): transferring burst starting at address 0x6001f048
Debug: 66343 153053 riscv-013.c:2072 log_memory_access(): M[0x6001f048] writes 0x00000000
Debug: 66353 153054 batch.c:164 dump_field(): 41b 5i w 00000000 @3c -> + 00000000 @39
Debug: 66354 153054 batch.c:164 dump_field(): 41b 5i - 00000000 @00 -> + 00000000 @3c
Debug: 66364 153054 command.c:143 script_debug(): command - mww mww 0x60020064 0x50D83AA1
Debug: 66384 153054 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$O#4f'
Debug: 66421 153056 riscv-013.c:3076 write_memory_bus_v1(): transferring burst starting at address 0x60020064
Debug: 66422 153056 riscv-013.c:2072 log_memory_access(): M[0x60020064] writes 0x50d83aa1
Debug: 66432 153056 batch.c:164 dump_field(): 41b 5i w 50d83aa1 @3c -> + 00000000 @39
Debug: 66433 153056 batch.c:164 dump_field(): 41b 5i - 00000000 @00 -> + 50d83aa1 @3c
Debug: 66443 153056 command.c:143 script_debug(): command - mww mww 0x60020048 0
Debug: 66463 153057 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$O#4f'
Debug: 66500 153058 riscv-013.c:3076 write_memory_bus_v1(): transferring burst starting at address 0x60020048
Debug: 66501 153058 riscv-013.c:2072 log_memory_access(): M[0x60020048] writes 0x00000000
Debug: 66511 153058 batch.c:164 dump_field(): 41b 5i w 00000000 @3c -> + 00000000 @39
Debug: 66512 153058 batch.c:164 dump_field(): 41b 5i - 00000000 @00 -> + 00000000 @3c
Debug: 66522 153058 command.c:143 script_debug(): command - mww mww 0x600080a8 0x50D83AA1
Debug: 66542 153059 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$O#4f'
Debug: 66579 153060 riscv-013.c:3076 write_memory_bus_v1(): transferring burst starting at address 0x600080a8
Debug: 66580 153060 riscv-013.c:2072 log_memory_access(): M[0x600080a8] writes 0x50d83aa1
Debug: 66590 153061 batch.c:164 dump_field(): 41b 5i w 50d83aa1 @3c -> + 00000000 @39
Debug: 66591 153061 batch.c:164 dump_field(): 41b 5i - 00000000 @00 -> + 50d83aa1 @3c
Debug: 66601 153061 command.c:143 script_debug(): command - mww mww 0x60008090 0
Debug: 66621 153061 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$O#4f'
Debug: 66658 153063 riscv-013.c:3076 write_memory_bus_v1(): transferring burst starting at address 0x60008090
Debug: 66659 153063 riscv-013.c:2072 log_memory_access(): M[0x60008090] writes 0x00000000
Debug: 66669 153063 batch.c:164 dump_field(): 41b 5i w 00000000 @3c -> + 00000000 @39
Debug: 66670 153063 batch.c:164 dump_field(): 41b 5i - 00000000 @00 -> + 00000000 @3c
Debug: 66680 153063 target.c:1634 target_call_event_callbacks(): target event 6 (gdb-end) for core esp32c3
Debug: 66699 153064 FreeRTOS.c:694 FreeRTOS_update_threads(): FreeRTOS_update_threads
Debug: 66754 153066 riscv-013.c:2072 log_memory_access(): M[0x3fc97e8c] reads 0x00000004
Debug: 66773 153066 target.c:2447 target_read_u32(): address: 0x3fc97e8c, value: 0x00000004
Debug: 66774 153066 FreeRTOS.c:745 FreeRTOS_update_threads(): Read uxCurrentNumberOfTasks at 0x3fc97e8c, value 4
Debug: 66829 153068 riscv-013.c:2072 log_memory_access(): M[0x3fc97e98] reads 0x00000004
Debug: 66848 153069 target.c:2447 target_read_u32(): address: 0x3fc97e98, value: 0x00000004
Debug: 66849 153069 FreeRTOS.c:766 FreeRTOS_update_threads(): Read uxTaskNumber at 0x3fc97e98, value 4
Error: 66850 153069 FreeRTOS.c:771 FreeRTOS_update_threads(): FreeRTOS uxTaskNumber seems to be corrupted!
Debug: 66851 153069 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$O4672656552544f532075785461736b4e756d626572207365656d7320746f20626520636f72727570746564210a#38'
Debug: 66852 153069 FreeRTOS.c:405 FreeRTOS_find_target_from_threadid(): Find target for thr 0x3fc9ed78
Debug: 66853 153069 FreeRTOS.c:433 FreeRTOS_target_for_threadid(): target found : esp32c3
Debug: 66854 153069 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$T05thread:3fc9ed78;#13'
Debug: 66855 153069 gdb_server.c:3358 gdb_input_inner(): received packet: 'g'
Debug: 66856 153069 riscv.c:1357 riscv_get_gdb_reg_list_internal(): rtos_hartid=0, current_hartid=0, reg_class=1, read=1
Debug: 66857 153069 riscv-013.c:3416 riscv013_get_register(): [0] reading register zero on hart 0
Debug: 66858 153069 riscv.c:2795 riscv_get_register_on_hart(): {0} zero: 0
Debug: 66859 153069 riscv.c:3071 register_get(): [0]{0} read 0x0 from zero (valid=1)
Debug: 66860 153069 riscv-013.c:3416 riscv013_get_register(): [0] reading register ra on hart 0
Debug: 66861 153069 riscv-013.c:765 execute_abstract_command(): command=0x221001; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1001
Debug: 66907 153070 riscv-013.c:1415 register_read_direct(): {0} ra = 0x420082c8
Debug: 66908 153070 riscv.c:2795 riscv_get_register_on_hart(): {0} ra: 420082c8
Debug: 66909 153070 riscv.c:3071 register_get(): [0]{0} read 0x420082c8 from ra (valid=1)
Debug: 66910 153070 riscv-013.c:3416 riscv013_get_register(): [0] reading register sp on hart 0
Debug: 66911 153070 riscv-013.c:765 execute_abstract_command(): command=0x221002; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1002
Debug: 66957 153072 riscv-013.c:1415 register_read_direct(): {0} sp = 0x3fc9e0e0
Debug: 66958 153072 riscv.c:2795 riscv_get_register_on_hart(): {0} sp: 3fc9e0e0
Debug: 66959 153072 riscv.c:3071 register_get(): [0]{0} read 0x3fc9e0e0 from sp (valid=1)
Debug: 66960 153072 riscv-013.c:3416 riscv013_get_register(): [0] reading register gp on hart 0
Debug: 66961 153072 riscv-013.c:765 execute_abstract_command(): command=0x221003; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1003
Debug: 67007 153074 riscv-013.c:1415 register_read_direct(): {0} gp = 0x3fc8fc00
Debug: 67008 153074 riscv.c:2795 riscv_get_register_on_hart(): {0} gp: 3fc8fc00
Debug: 67009 153074 riscv.c:3071 register_get(): [0]{0} read 0x3fc8fc00 from gp (valid=1)
Debug: 67010 153074 riscv-013.c:3416 riscv013_get_register(): [0] reading register tp on hart 0
Debug: 67011 153074 riscv-013.c:765 execute_abstract_command(): command=0x221004; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1004
Debug: 67057 153075 riscv-013.c:1415 register_read_direct(): {0} tp = 0x3fc78f28
Debug: 67058 153075 riscv.c:2795 riscv_get_register_on_hart(): {0} tp: 3fc78f28
Debug: 67059 153075 riscv.c:3071 register_get(): [0]{0} read 0x3fc78f28 from tp (valid=1)
Debug: 67060 153075 riscv-013.c:3416 riscv013_get_register(): [0] reading register t0 on hart 0
Debug: 67061 153075 riscv-013.c:765 execute_abstract_command(): command=0x221005; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1005
Debug: 67107 153077 riscv-013.c:1415 register_read_direct(): {0} t0 = 0x40057fa6
Debug: 67108 153077 riscv.c:2795 riscv_get_register_on_hart(): {0} t0: 40057fa6
Debug: 67109 153077 riscv.c:3071 register_get(): [0]{0} read 0x40057fa6 from t0 (valid=1)
Debug: 67110 153077 riscv-013.c:3416 riscv013_get_register(): [0] reading register t1 on hart 0
Debug: 67111 153077 riscv-013.c:765 execute_abstract_command(): command=0x221006; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1006
Debug: 67157 153078 riscv-013.c:1415 register_read_direct(): {0} t1 = 0xf
Debug: 67158 153078 riscv.c:2795 riscv_get_register_on_hart(): {0} t1: f
Debug: 67159 153078 riscv.c:3071 register_get(): [0]{0} read 0xf from t1 (valid=1)
Debug: 67160 153078 riscv-013.c:3416 riscv013_get_register(): [0] reading register t2 on hart 0
Debug: 67161 153078 riscv-013.c:765 execute_abstract_command(): command=0x221007; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1007
Debug: 67207 153080 riscv-013.c:1415 register_read_direct(): {0} t2 = 0x0
Debug: 67208 153080 riscv.c:2795 riscv_get_register_on_hart(): {0} t2: 0
Debug: 67209 153080 riscv.c:3071 register_get(): [0]{0} read 0x0 from t2 (valid=1)
Debug: 67210 153080 riscv-013.c:3416 riscv013_get_register(): [0] reading register s0 on hart 0
Debug: 67211 153080 riscv-013.c:765 execute_abstract_command(): command=0x221008; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1008
Debug: 67257 153082 riscv-013.c:1415 register_read_direct(): {0} s0 = 0x0
Debug: 67258 153082 riscv.c:2795 riscv_get_register_on_hart(): {0} s0: 0
Debug: 67259 153082 riscv.c:3071 register_get(): [0]{0} read 0x0 from fp (valid=1)
Debug: 67260 153082 riscv-013.c:3416 riscv013_get_register(): [0] reading register s1 on hart 0
Debug: 67261 153082 riscv-013.c:765 execute_abstract_command(): command=0x221009; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1009
Debug: 67307 153083 riscv-013.c:1415 register_read_direct(): {0} s1 = 0x0
Debug: 67308 153083 riscv.c:2795 riscv_get_register_on_hart(): {0} s1: 0
Debug: 67309 153083 riscv.c:3071 register_get(): [0]{0} read 0x0 from s1 (valid=1)
Debug: 67310 153083 riscv-013.c:3416 riscv013_get_register(): [0] reading register a0 on hart 0
Debug: 67311 153083 riscv-013.c:765 execute_abstract_command(): command=0x22100a; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100a
Debug: 67357 153085 riscv-013.c:1415 register_read_direct(): {0} a0 = 0x0
Debug: 67358 153085 riscv.c:2795 riscv_get_register_on_hart(): {0} a0: 0
Debug: 67359 153085 riscv.c:3071 register_get(): [0]{0} read 0x0 from a0 (valid=1)
Debug: 67360 153085 riscv-013.c:3416 riscv013_get_register(): [0] reading register a1 on hart 0
Debug: 67361 153085 riscv-013.c:765 execute_abstract_command(): command=0x22100b; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100b
Debug: 67407 153086 riscv-013.c:1415 register_read_direct(): {0} a1 = 0x0
Debug: 67408 153086 riscv.c:2795 riscv_get_register_on_hart(): {0} a1: 0
Debug: 67409 153086 riscv.c:3071 register_get(): [0]{0} read 0x0 from a1 (valid=1)
Debug: 67410 153086 riscv-013.c:3416 riscv013_get_register(): [0] reading register a2 on hart 0
Debug: 67411 153086 riscv-013.c:765 execute_abstract_command(): command=0x22100c; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100c
Debug: 67457 153088 riscv-013.c:1415 register_read_direct(): {0} a2 = 0x3
Debug: 67458 153088 riscv.c:2795 riscv_get_register_on_hart(): {0} a2: 3
Debug: 67459 153088 riscv.c:3071 register_get(): [0]{0} read 0x3 from a2 (valid=1)
Debug: 67460 153088 riscv-013.c:3416 riscv013_get_register(): [0] reading register a3 on hart 0
Debug: 67461 153088 riscv-013.c:765 execute_abstract_command(): command=0x22100d; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100d
Debug: 67507 153089 riscv-013.c:1415 register_read_direct(): {0} a3 = 0x0
Debug: 67508 153089 riscv.c:2795 riscv_get_register_on_hart(): {0} a3: 0
Debug: 67509 153089 riscv.c:3071 register_get(): [0]{0} read 0x0 from a3 (valid=1)
Debug: 67510 153089 riscv-013.c:3416 riscv013_get_register(): [0] reading register a4 on hart 0
Debug: 67511 153089 riscv-013.c:765 execute_abstract_command(): command=0x22100e; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100e
Debug: 67557 153091 riscv-013.c:1415 register_read_direct(): {0} a4 = 0x1
Debug: 67558 153091 riscv.c:2795 riscv_get_register_on_hart(): {0} a4: 1
Debug: 67559 153091 riscv.c:3071 register_get(): [0]{0} read 0x1 from a4 (valid=1)
Debug: 67560 153091 riscv-013.c:3416 riscv013_get_register(): [0] reading register a5 on hart 0
Debug: 67561 153091 riscv-013.c:765 execute_abstract_command(): command=0x22100f; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100f
Debug: 67607 153093 riscv-013.c:1415 register_read_direct(): {0} a5 = 0x600c2000
Debug: 67608 153093 riscv.c:2795 riscv_get_register_on_hart(): {0} a5: 600c2000
Debug: 67609 153093 riscv.c:3071 register_get(): [0]{0} read 0x600c2000 from a5 (valid=1)
Debug: 67610 153093 riscv-013.c:3416 riscv013_get_register(): [0] reading register a6 on hart 0
Debug: 67611 153093 riscv-013.c:765 execute_abstract_command(): command=0x221010; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1010
Debug: 67657 153094 riscv-013.c:1415 register_read_direct(): {0} a6 = 0x1
Debug: 67658 153094 riscv.c:2795 riscv_get_register_on_hart(): {0} a6: 1
Debug: 67659 153094 riscv.c:3071 register_get(): [0]{0} read 0x1 from a6 (valid=1)
Debug: 67660 153094 riscv-013.c:3416 riscv013_get_register(): [0] reading register a7 on hart 0
Debug: 67661 153094 riscv-013.c:765 execute_abstract_command(): command=0x221011; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1011
Debug: 67707 153096 riscv-013.c:1415 register_read_direct(): {0} a7 = 0x3fc9f82c
Debug: 67708 153096 riscv.c:2795 riscv_get_register_on_hart(): {0} a7: 3fc9f82c
Debug: 67709 153096 riscv.c:3071 register_get(): [0]{0} read 0x3fc9f82c from a7 (valid=1)
Debug: 67710 153096 riscv-013.c:3416 riscv013_get_register(): [0] reading register s2 on hart 0
Debug: 67711 153096 riscv-013.c:765 execute_abstract_command(): command=0x221012; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1012
Debug: 67757 153097 riscv-013.c:1415 register_read_direct(): {0} s2 = 0x0
Debug: 67758 153097 riscv.c:2795 riscv_get_register_on_hart(): {0} s2: 0
Debug: 67759 153097 riscv.c:3071 register_get(): [0]{0} read 0x0 from s2 (valid=1)
Debug: 67760 153097 riscv-013.c:3416 riscv013_get_register(): [0] reading register s3 on hart 0
Debug: 67761 153097 riscv-013.c:765 execute_abstract_command(): command=0x221013; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1013
Debug: 67807 153099 riscv-013.c:1415 register_read_direct(): {0} s3 = 0x0
Debug: 67808 153099 riscv.c:2795 riscv_get_register_on_hart(): {0} s3: 0
Debug: 67809 153099 riscv.c:3071 register_get(): [0]{0} read 0x0 from s3 (valid=1)
Debug: 67810 153099 riscv-013.c:3416 riscv013_get_register(): [0] reading register s4 on hart 0
Debug: 67811 153099 riscv-013.c:765 execute_abstract_command(): command=0x221014; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1014
Debug: 67857 153100 riscv-013.c:1415 register_read_direct(): {0} s4 = 0x0
Debug: 67858 153100 riscv.c:2795 riscv_get_register_on_hart(): {0} s4: 0
Debug: 67859 153100 riscv.c:3071 register_get(): [0]{0} read 0x0 from s4 (valid=1)
Debug: 67860 153100 riscv-013.c:3416 riscv013_get_register(): [0] reading register s5 on hart 0
Debug: 67861 153100 riscv-013.c:765 execute_abstract_command(): command=0x221015; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1015
Debug: 67907 153102 riscv-013.c:1415 register_read_direct(): {0} s5 = 0x0
Debug: 67908 153102 riscv.c:2795 riscv_get_register_on_hart(): {0} s5: 0
Debug: 67909 153102 riscv.c:3071 register_get(): [0]{0} read 0x0 from s5 (valid=1)
Debug: 67910 153102 riscv-013.c:3416 riscv013_get_register(): [0] reading register s6 on hart 0
Debug: 67911 153102 riscv-013.c:765 execute_abstract_command(): command=0x221016; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1016
Debug: 67957 153103 riscv-013.c:1415 register_read_direct(): {0} s6 = 0x0
Debug: 67958 153103 riscv.c:2795 riscv_get_register_on_hart(): {0} s6: 0
Debug: 67959 153103 riscv.c:3071 register_get(): [0]{0} read 0x0 from s6 (valid=1)
Debug: 67960 153103 riscv-013.c:3416 riscv013_get_register(): [0] reading register s7 on hart 0
Debug: 67961 153103 riscv-013.c:765 execute_abstract_command(): command=0x221017; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1017
Debug: 68007 153105 riscv-013.c:1415 register_read_direct(): {0} s7 = 0x0
Debug: 68008 153105 riscv.c:2795 riscv_get_register_on_hart(): {0} s7: 0
Debug: 68009 153105 riscv.c:3071 register_get(): [0]{0} read 0x0 from s7 (valid=1)
Debug: 68010 153105 riscv-013.c:3416 riscv013_get_register(): [0] reading register s8 on hart 0
Debug: 68011 153105 riscv-013.c:765 execute_abstract_command(): command=0x221018; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1018
Debug: 68057 153106 riscv-013.c:1415 register_read_direct(): {0} s8 = 0x0
Debug: 68058 153106 riscv.c:2795 riscv_get_register_on_hart(): {0} s8: 0
Debug: 68059 153106 riscv.c:3071 register_get(): [0]{0} read 0x0 from s8 (valid=1)
Debug: 68060 153106 riscv-013.c:3416 riscv013_get_register(): [0] reading register s9 on hart 0
Debug: 68061 153107 riscv-013.c:765 execute_abstract_command(): command=0x221019; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1019
Debug: 68107 153108 riscv-013.c:1415 register_read_direct(): {0} s9 = 0x0
Debug: 68108 153108 riscv.c:2795 riscv_get_register_on_hart(): {0} s9: 0
Debug: 68109 153108 riscv.c:3071 register_get(): [0]{0} read 0x0 from s9 (valid=1)
Debug: 68110 153108 riscv-013.c:3416 riscv013_get_register(): [0] reading register s10 on hart 0
Debug: 68111 153108 riscv-013.c:765 execute_abstract_command(): command=0x22101a; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101a
Debug: 68157 153110 riscv-013.c:1415 register_read_direct(): {0} s10 = 0x0
Debug: 68158 153110 riscv.c:2795 riscv_get_register_on_hart(): {0} s10: 0
Debug: 68159 153110 riscv.c:3071 register_get(): [0]{0} read 0x0 from s10 (valid=1)
Debug: 68160 153110 riscv-013.c:3416 riscv013_get_register(): [0] reading register s11 on hart 0
Debug: 68161 153110 riscv-013.c:765 execute_abstract_command(): command=0x22101b; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101b
Debug: 68207 153111 riscv-013.c:1415 register_read_direct(): {0} s11 = 0x0
Debug: 68208 153111 riscv.c:2795 riscv_get_register_on_hart(): {0} s11: 0
Debug: 68209 153111 riscv.c:3071 register_get(): [0]{0} read 0x0 from s11 (valid=1)
Debug: 68210 153111 riscv-013.c:3416 riscv013_get_register(): [0] reading register t3 on hart 0
Debug: 68211 153111 riscv-013.c:765 execute_abstract_command(): command=0x22101c; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101c
Debug: 68257 153113 riscv-013.c:1415 register_read_direct(): {0} t3 = 0x0
Debug: 68258 153113 riscv.c:2795 riscv_get_register_on_hart(): {0} t3: 0
Debug: 68259 153113 riscv.c:3071 register_get(): [0]{0} read 0x0 from t3 (valid=1)
Debug: 68260 153113 riscv-013.c:3416 riscv013_get_register(): [0] reading register t4 on hart 0
Debug: 68261 153113 riscv-013.c:765 execute_abstract_command(): command=0x22101d; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101d
Debug: 68307 153114 riscv-013.c:1415 register_read_direct(): {0} t4 = 0x0
Debug: 68308 153114 riscv.c:2795 riscv_get_register_on_hart(): {0} t4: 0
Debug: 68309 153114 riscv.c:3071 register_get(): [0]{0} read 0x0 from t4 (valid=1)
Debug: 68310 153114 riscv-013.c:3416 riscv013_get_register(): [0] reading register t5 on hart 0
Debug: 68311 153114 riscv-013.c:765 execute_abstract_command(): command=0x22101e; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101e
Debug: 68357 153116 riscv-013.c:1415 register_read_direct(): {0} t5 = 0x0
Debug: 68358 153116 riscv.c:2795 riscv_get_register_on_hart(): {0} t5: 0
Debug: 68359 153116 riscv.c:3071 register_get(): [0]{0} read 0x0 from t5 (valid=1)
Debug: 68360 153116 riscv-013.c:3416 riscv013_get_register(): [0] reading register t6 on hart 0
Debug: 68361 153116 riscv-013.c:765 execute_abstract_command(): command=0x22101f; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101f
Debug: 68407 153117 riscv-013.c:1415 register_read_direct(): {0} t6 = 0x0
Debug: 68408 153117 riscv.c:2795 riscv_get_register_on_hart(): {0} t6: 0
Debug: 68409 153117 riscv.c:3071 register_get(): [0]{0} read 0x0 from t6 (valid=1)
Debug: 68410 153117 riscv-013.c:3416 riscv013_get_register(): [0] reading register pc on hart 0
Debug: 68411 153117 riscv-013.c:765 execute_abstract_command(): command=0x2207b1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b1
Debug: 68457 153119 riscv-013.c:1415 register_read_direct(): {0} dpc = 0x4202a010
Debug: 68458 153119 riscv-013.c:3424 riscv013_get_register(): [0] read PC from DPC: 0x4202a010
Debug: 68459 153119 riscv.c:2795 riscv_get_register_on_hart(): {0} pc: 4202a010
Debug: 68460 153119 riscv.c:3071 register_get(): [0]{0} read 0x4202a010 from pc (valid=1)
Debug: 68461 153119 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$00000000c8820042e0e0c93f00fcc83f288fc73fa67f05400f000000000000000000000000000000000000000000000003000000000000000100000000200c60010000002cf8c93f000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010a00242#57'
Debug: 68462 153119 gdb_server.c:3358 gdb_input_inner(): received packet: 'vCont;s:3fc9ed78;c'
Debug: 68463 153119 FreeRTOS.c:405 FreeRTOS_find_target_from_threadid(): Find target for thr 0x3fc9ed78
Debug: 68464 153119 FreeRTOS.c:433 FreeRTOS_target_for_threadid(): target found : esp32c3
Debug: 68465 153119 gdb_server.c:2912 gdb_handle_vcont_packet(): target esp32c3 single-step thread 3fc9ed78
Debug: 68466 153119 target.c:1634 target_call_event_callbacks(): target event 5 (gdb-start) for core esp32c3
Debug: 68467 153119 riscv.c:965 old_or_new_riscv_step(): handle_breakpoints=0
Debug: 68468 153119 riscv.c:1845 riscv_openocd_step(): stepping rtos hart
Debug: 68469 153119 riscv.c:2624 riscv_step_rtos_hart(): stepping hart 0
Debug: 68488 153119 riscv.c:2699 riscv_invalidate_register_cache(): [0]
Debug: 68489 153119 program.c:33 riscv_program_write(): debug_buffer[00] = DASM(0x0000100f)
Debug: 68490 153119 riscv-013.c:3695 riscv013_write_debug_buffer(): cache hit for 0x100f @0
Debug: 68491 153119 program.c:33 riscv_program_write(): debug_buffer[01] = DASM(0x0000000f)
Debug: 68492 153119 riscv-013.c:3695 riscv013_write_debug_buffer(): cache hit for 0xf @1
Debug: 68493 153119 program.c:33 riscv_program_write(): debug_buffer[02] = DASM(0x00100073)
Debug: 68494 153119 riscv-013.c:3695 riscv013_write_debug_buffer(): cache hit for 0x100073 @2
Debug: 68495 153119 riscv-013.c:765 execute_abstract_command(): command=0x241000; access register, size=32, postexec=1, transfer=0, write=0, regno=0x1000
Debug: 68523 153120 program.c:33 riscv_program_write(): debug_buffer[00] = DASM(0x0000100f)
Debug: 68524 153120 riscv-013.c:3695 riscv013_write_debug_buffer(): cache hit for 0x100f @0
Debug: 68525 153120 program.c:33 riscv_program_write(): debug_buffer[01] = DASM(0x0000000f)
Debug: 68526 153120 riscv-013.c:3695 riscv013_write_debug_buffer(): cache hit for 0xf @1
Debug: 68527 153120 program.c:33 riscv_program_write(): debug_buffer[02] = DASM(0x00100073)
Debug: 68528 153120 riscv-013.c:3695 riscv013_write_debug_buffer(): cache hit for 0x100073 @2
Debug: 68529 153120 riscv-013.c:765 execute_abstract_command(): command=0x241000; access register, size=32, postexec=1, transfer=0, write=0, regno=0x1000
Debug: 68557 153121 riscv-013.c:765 execute_abstract_command(): command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0
Debug: 68603 153122 riscv-013.c:1415 register_read_direct(): {0} dcsr = 0x4000b107
Debug: 68604 153122 riscv.c:2756 riscv_set_register_on_hart(): {0} dcsr <- 4000b107
Debug: 68605 153122 riscv-013.c:3440 riscv013_set_register(): [0] writing 0x4000b107 to register dcsr on hart 0
Debug: 68606 153122 riscv-013.c:1227 register_write_direct(): {0} dcsr <- 0x4000b107
Debug: 68625 153123 riscv-013.c:765 execute_abstract_command(): command=0x2307b0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b0
Debug: 68653 153124 riscv-013.c:4130 riscv013_step_or_resume_current_hart(): resuming hart 0 (for step?=1)
Debug: 68726 153126 riscv.c:2699 riscv_invalidate_register_cache(): [0]
Debug: 68745 153127 target.c:1634 target_call_event_callbacks(): target event 2 (resumed) for core esp32c3
Debug: 68746 153127 target.c:1634 target_call_event_callbacks(): target event 0 (gdb-halt) for core esp32c3
Debug: 68747 153127 target.c:1634 target_call_event_callbacks(): target event 1 (halted) for core esp32c3
Debug: 68748 153127 target.c:4631 target_handle_event(): target(0): esp32c3 (riscv) event: 1 (halted) action:  esp32c3_wdt_disable 
Debug: 68749 153127 command.c:143 script_debug(): command - command command mode
Debug: 68750 153127 command.c:143 script_debug(): command - mww mww 0x6001f064 0x50D83AA1
Debug: 68770 153127 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$O#4f'
Debug: 68807 153128 riscv-013.c:3076 write_memory_bus_v1(): transferring burst starting at address 0x6001f064
Debug: 68808 153128 riscv-013.c:2072 log_memory_access(): M[0x6001f064] writes 0x50d83aa1
Debug: 68818 153129 batch.c:164 dump_field(): 41b 5i w 50d83aa1 @3c -> + 00000000 @39
Debug: 68819 153129 batch.c:164 dump_field(): 41b 5i - 00000000 @00 -> + 50d83aa1 @3c
Debug: 68829 153129 command.c:143 script_debug(): command - mww mww 0x6001F048 0
Debug: 68849 153129 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$O#4f'
Debug: 68886 153131 riscv-013.c:3076 write_memory_bus_v1(): transferring burst starting at address 0x6001f048
Debug: 68887 153131 riscv-013.c:2072 log_memory_access(): M[0x6001f048] writes 0x00000000
Debug: 68897 153131 batch.c:164 dump_field(): 41b 5i w 00000000 @3c -> + 00000000 @39
Debug: 68898 153131 batch.c:164 dump_field(): 41b 5i - 00000000 @00 -> + 00000000 @3c
Debug: 68908 153131 command.c:143 script_debug(): command - mww mww 0x60020064 0x50D83AA1
Debug: 68928 153132 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$O#4f'
Debug: 68965 153133 riscv-013.c:3076 write_memory_bus_v1(): transferring burst starting at address 0x60020064
Debug: 68966 153133 riscv-013.c:2072 log_memory_access(): M[0x60020064] writes 0x50d83aa1
Debug: 68976 153134 batch.c:164 dump_field(): 41b 5i w 50d83aa1 @3c -> + 00000000 @39
Debug: 68977 153134 batch.c:164 dump_field(): 41b 5i - 00000000 @00 -> + 50d83aa1 @3c
Debug: 68987 153134 command.c:143 script_debug(): command - mww mww 0x60020048 0
Debug: 69007 153135 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$O#4f'
Debug: 69044 153136 riscv-013.c:3076 write_memory_bus_v1(): transferring burst starting at address 0x60020048
Debug: 69045 153136 riscv-013.c:2072 log_memory_access(): M[0x60020048] writes 0x00000000
Debug: 69055 153136 batch.c:164 dump_field(): 41b 5i w 00000000 @3c -> + 00000000 @39
Debug: 69056 153136 batch.c:164 dump_field(): 41b 5i - 00000000 @00 -> + 00000000 @3c
Debug: 69066 153136 command.c:143 script_debug(): command - mww mww 0x600080a8 0x50D83AA1
Debug: 69086 153137 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$O#4f'
Debug: 69123 153138 riscv-013.c:3076 write_memory_bus_v1(): transferring burst starting at address 0x600080a8
Debug: 69124 153138 riscv-013.c:2072 log_memory_access(): M[0x600080a8] writes 0x50d83aa1
Debug: 69134 153139 batch.c:164 dump_field(): 41b 5i w 50d83aa1 @3c -> + 00000000 @39
Debug: 69135 153139 batch.c:164 dump_field(): 41b 5i - 00000000 @00 -> + 50d83aa1 @3c
Debug: 69145 153139 command.c:143 script_debug(): command - mww mww 0x60008090 0
Debug: 69165 153140 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$O#4f'
Debug: 69202 153141 riscv-013.c:3076 write_memory_bus_v1(): transferring burst starting at address 0x60008090
Debug: 69203 153141 riscv-013.c:2072 log_memory_access(): M[0x60008090] writes 0x00000000
Debug: 69213 153141 batch.c:164 dump_field(): 41b 5i w 00000000 @3c -> + 00000000 @39
Debug: 69214 153141 batch.c:164 dump_field(): 41b 5i - 00000000 @00 -> + 00000000 @3c
Debug: 69224 153142 target.c:1634 target_call_event_callbacks(): target event 6 (gdb-end) for core esp32c3
Debug: 69243 153142 FreeRTOS.c:694 FreeRTOS_update_threads(): FreeRTOS_update_threads
Debug: 69298 153144 riscv-013.c:2072 log_memory_access(): M[0x3fc97e8c] reads 0x00000004
Debug: 69317 153145 target.c:2447 target_read_u32(): address: 0x3fc97e8c, value: 0x00000004
Debug: 69318 153145 FreeRTOS.c:745 FreeRTOS_update_threads(): Read uxCurrentNumberOfTasks at 0x3fc97e8c, value 4
Debug: 69373 153147 riscv-013.c:2072 log_memory_access(): M[0x3fc97e98] reads 0x00000004
Debug: 69392 153147 target.c:2447 target_read_u32(): address: 0x3fc97e98, value: 0x00000004
Debug: 69393 153147 FreeRTOS.c:766 FreeRTOS_update_threads(): Read uxTaskNumber at 0x3fc97e98, value 4
Error: 69394 153147 FreeRTOS.c:771 FreeRTOS_update_threads(): FreeRTOS uxTaskNumber seems to be corrupted!
Debug: 69395 153147 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$O4672656552544f532075785461736b4e756d626572207365656d7320746f20626520636f72727570746564210a#38'
Debug: 69396 153147 FreeRTOS.c:405 FreeRTOS_find_target_from_threadid(): Find target for thr 0x3fc9ed78
Debug: 69397 153147 FreeRTOS.c:433 FreeRTOS_target_for_threadid(): target found : esp32c3
Debug: 69398 153147 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$T05thread:3fc9ed78;#13'
Debug: 69399 153148 gdb_server.c:3358 gdb_input_inner(): received packet: 'g'
Debug: 69400 153148 riscv.c:1357 riscv_get_gdb_reg_list_internal(): rtos_hartid=0, current_hartid=0, reg_class=1, read=1
Debug: 69401 153148 riscv-013.c:3416 riscv013_get_register(): [0] reading register zero on hart 0
Debug: 69402 153148 riscv.c:2795 riscv_get_register_on_hart(): {0} zero: 0
Debug: 69403 153148 riscv.c:3071 register_get(): [0]{0} read 0x0 from zero (valid=1)
Debug: 69404 153148 riscv-013.c:3416 riscv013_get_register(): [0] reading register ra on hart 0
Debug: 69405 153148 riscv-013.c:765 execute_abstract_command(): command=0x221001; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1001
Debug: 69451 153149 riscv-013.c:1415 register_read_direct(): {0} ra = 0x420082c8
Debug: 69452 153149 riscv.c:2795 riscv_get_register_on_hart(): {0} ra: 420082c8
Debug: 69453 153149 riscv.c:3071 register_get(): [0]{0} read 0x420082c8 from ra (valid=1)
Debug: 69454 153149 riscv-013.c:3416 riscv013_get_register(): [0] reading register sp on hart 0
Debug: 69455 153149 riscv-013.c:765 execute_abstract_command(): command=0x221002; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1002
Debug: 69501 153151 riscv-013.c:1415 register_read_direct(): {0} sp = 0x3fc9e0e0
Debug: 69502 153151 riscv.c:2795 riscv_get_register_on_hart(): {0} sp: 3fc9e0e0
Debug: 69503 153151 riscv.c:3071 register_get(): [0]{0} read 0x3fc9e0e0 from sp (valid=1)
Debug: 69504 153151 riscv-013.c:3416 riscv013_get_register(): [0] reading register gp on hart 0
Debug: 69505 153151 riscv-013.c:765 execute_abstract_command(): command=0x221003; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1003
Debug: 69551 153152 riscv-013.c:1415 register_read_direct(): {0} gp = 0x3fc8fc00
Debug: 69552 153152 riscv.c:2795 riscv_get_register_on_hart(): {0} gp: 3fc8fc00
Debug: 69553 153152 riscv.c:3071 register_get(): [0]{0} read 0x3fc8fc00 from gp (valid=1)
Debug: 69554 153152 riscv-013.c:3416 riscv013_get_register(): [0] reading register tp on hart 0
Debug: 69555 153152 riscv-013.c:765 execute_abstract_command(): command=0x221004; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1004
Debug: 69601 153154 riscv-013.c:1415 register_read_direct(): {0} tp = 0x3fc78f28
Debug: 69602 153154 riscv.c:2795 riscv_get_register_on_hart(): {0} tp: 3fc78f28
Debug: 69603 153154 riscv.c:3071 register_get(): [0]{0} read 0x3fc78f28 from tp (valid=1)
Debug: 69604 153154 riscv-013.c:3416 riscv013_get_register(): [0] reading register t0 on hart 0
Debug: 69605 153154 riscv-013.c:765 execute_abstract_command(): command=0x221005; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1005
Debug: 69651 153156 riscv-013.c:1415 register_read_direct(): {0} t0 = 0x40057fa6
Debug: 69652 153156 riscv.c:2795 riscv_get_register_on_hart(): {0} t0: 40057fa6
Debug: 69653 153156 riscv.c:3071 register_get(): [0]{0} read 0x40057fa6 from t0 (valid=1)
Debug: 69654 153156 riscv-013.c:3416 riscv013_get_register(): [0] reading register t1 on hart 0
Debug: 69655 153156 riscv-013.c:765 execute_abstract_command(): command=0x221006; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1006
Debug: 69701 153157 riscv-013.c:1415 register_read_direct(): {0} t1 = 0xf
Debug: 69702 153157 riscv.c:2795 riscv_get_register_on_hart(): {0} t1: f
Debug: 69703 153157 riscv.c:3071 register_get(): [0]{0} read 0xf from t1 (valid=1)
Debug: 69704 153157 riscv-013.c:3416 riscv013_get_register(): [0] reading register t2 on hart 0
Debug: 69705 153157 riscv-013.c:765 execute_abstract_command(): command=0x221007; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1007
Debug: 69751 153159 riscv-013.c:1415 register_read_direct(): {0} t2 = 0x0
Debug: 69752 153159 riscv.c:2795 riscv_get_register_on_hart(): {0} t2: 0
Debug: 69753 153159 riscv.c:3071 register_get(): [0]{0} read 0x0 from t2 (valid=1)
Debug: 69754 153159 riscv-013.c:3416 riscv013_get_register(): [0] reading register s0 on hart 0
Debug: 69755 153159 riscv-013.c:765 execute_abstract_command(): command=0x221008; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1008
Debug: 69801 153160 riscv-013.c:1415 register_read_direct(): {0} s0 = 0x0
Debug: 69802 153160 riscv.c:2795 riscv_get_register_on_hart(): {0} s0: 0
Debug: 69803 153160 riscv.c:3071 register_get(): [0]{0} read 0x0 from fp (valid=1)
Debug: 69804 153160 riscv-013.c:3416 riscv013_get_register(): [0] reading register s1 on hart 0
Debug: 69805 153160 riscv-013.c:765 execute_abstract_command(): command=0x221009; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1009
Debug: 69851 153162 riscv-013.c:1415 register_read_direct(): {0} s1 = 0x0
Debug: 69852 153162 riscv.c:2795 riscv_get_register_on_hart(): {0} s1: 0
Debug: 69853 153162 riscv.c:3071 register_get(): [0]{0} read 0x0 from s1 (valid=1)
Debug: 69854 153162 riscv-013.c:3416 riscv013_get_register(): [0] reading register a0 on hart 0
Debug: 69855 153162 riscv-013.c:765 execute_abstract_command(): command=0x22100a; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100a
Debug: 69901 153163 riscv-013.c:1415 register_read_direct(): {0} a0 = 0x1
Debug: 69902 153164 riscv.c:2795 riscv_get_register_on_hart(): {0} a0: 1
Debug: 69903 153164 riscv.c:3071 register_get(): [0]{0} read 0x1 from a0 (valid=1)
Debug: 69904 153164 riscv-013.c:3416 riscv013_get_register(): [0] reading register a1 on hart 0
Debug: 69905 153164 riscv-013.c:765 execute_abstract_command(): command=0x22100b; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100b
Debug: 69951 153165 riscv-013.c:1415 register_read_direct(): {0} a1 = 0x0
Debug: 69952 153165 riscv.c:2795 riscv_get_register_on_hart(): {0} a1: 0
Debug: 69953 153165 riscv.c:3071 register_get(): [0]{0} read 0x0 from a1 (valid=1)
Debug: 69954 153165 riscv-013.c:3416 riscv013_get_register(): [0] reading register a2 on hart 0
Debug: 69955 153165 riscv-013.c:765 execute_abstract_command(): command=0x22100c; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100c
Debug: 70001 153167 riscv-013.c:1415 register_read_direct(): {0} a2 = 0x3
Debug: 70002 153167 riscv.c:2795 riscv_get_register_on_hart(): {0} a2: 3
Debug: 70003 153167 riscv.c:3071 register_get(): [0]{0} read 0x3 from a2 (valid=1)
Debug: 70004 153167 riscv-013.c:3416 riscv013_get_register(): [0] reading register a3 on hart 0
Debug: 70005 153167 riscv-013.c:765 execute_abstract_command(): command=0x22100d; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100d
Debug: 70051 153168 riscv-013.c:1415 register_read_direct(): {0} a3 = 0x0
Debug: 70052 153168 riscv.c:2795 riscv_get_register_on_hart(): {0} a3: 0
Debug: 70053 153168 riscv.c:3071 register_get(): [0]{0} read 0x0 from a3 (valid=1)
Debug: 70054 153168 riscv-013.c:3416 riscv013_get_register(): [0] reading register a4 on hart 0
Debug: 70055 153168 riscv-013.c:765 execute_abstract_command(): command=0x22100e; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100e
Debug: 70101 153170 riscv-013.c:1415 register_read_direct(): {0} a4 = 0x1
Debug: 70102 153170 riscv.c:2795 riscv_get_register_on_hart(): {0} a4: 1
Debug: 70103 153170 riscv.c:3071 register_get(): [0]{0} read 0x1 from a4 (valid=1)
Debug: 70104 153170 riscv-013.c:3416 riscv013_get_register(): [0] reading register a5 on hart 0
Debug: 70105 153170 riscv-013.c:765 execute_abstract_command(): command=0x22100f; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100f
Debug: 70151 153171 riscv-013.c:1415 register_read_direct(): {0} a5 = 0x600c2000
Debug: 70152 153171 riscv.c:2795 riscv_get_register_on_hart(): {0} a5: 600c2000
Debug: 70153 153171 riscv.c:3071 register_get(): [0]{0} read 0x600c2000 from a5 (valid=1)
Debug: 70154 153171 riscv-013.c:3416 riscv013_get_register(): [0] reading register a6 on hart 0
Debug: 70155 153171 riscv-013.c:765 execute_abstract_command(): command=0x221010; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1010
Debug: 70201 153172 riscv-013.c:1415 register_read_direct(): {0} a6 = 0x1
Debug: 70202 153172 riscv.c:2795 riscv_get_register_on_hart(): {0} a6: 1
Debug: 70203 153172 riscv.c:3071 register_get(): [0]{0} read 0x1 from a6 (valid=1)
Debug: 70204 153172 riscv-013.c:3416 riscv013_get_register(): [0] reading register a7 on hart 0
Debug: 70205 153172 riscv-013.c:765 execute_abstract_command(): command=0x221011; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1011
Debug: 70251 153174 riscv-013.c:1415 register_read_direct(): {0} a7 = 0x3fc9f82c
Debug: 70252 153174 riscv.c:2795 riscv_get_register_on_hart(): {0} a7: 3fc9f82c
Debug: 70253 153174 riscv.c:3071 register_get(): [0]{0} read 0x3fc9f82c from a7 (valid=1)
Debug: 70254 153174 riscv-013.c:3416 riscv013_get_register(): [0] reading register s2 on hart 0
Debug: 70255 153174 riscv-013.c:765 execute_abstract_command(): command=0x221012; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1012
Debug: 70301 153175 riscv-013.c:1415 register_read_direct(): {0} s2 = 0x0
Debug: 70302 153175 riscv.c:2795 riscv_get_register_on_hart(): {0} s2: 0
Debug: 70303 153175 riscv.c:3071 register_get(): [0]{0} read 0x0 from s2 (valid=1)
Debug: 70304 153175 riscv-013.c:3416 riscv013_get_register(): [0] reading register s3 on hart 0
Debug: 70305 153175 riscv-013.c:765 execute_abstract_command(): command=0x221013; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1013
Debug: 70351 153176 riscv-013.c:1415 register_read_direct(): {0} s3 = 0x0
Debug: 70352 153176 riscv.c:2795 riscv_get_register_on_hart(): {0} s3: 0
Debug: 70353 153177 riscv.c:3071 register_get(): [0]{0} read 0x0 from s3 (valid=1)
Debug: 70354 153177 riscv-013.c:3416 riscv013_get_register(): [0] reading register s4 on hart 0
Debug: 70355 153177 riscv-013.c:765 execute_abstract_command(): command=0x221014; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1014
Debug: 70401 153178 riscv-013.c:1415 register_read_direct(): {0} s4 = 0x0
Debug: 70402 153178 riscv.c:2795 riscv_get_register_on_hart(): {0} s4: 0
Debug: 70403 153178 riscv.c:3071 register_get(): [0]{0} read 0x0 from s4 (valid=1)
Debug: 70404 153178 riscv-013.c:3416 riscv013_get_register(): [0] reading register s5 on hart 0
Debug: 70405 153178 riscv-013.c:765 execute_abstract_command(): command=0x221015; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1015
Debug: 70451 153179 riscv-013.c:1415 register_read_direct(): {0} s5 = 0x0
Debug: 70452 153179 riscv.c:2795 riscv_get_register_on_hart(): {0} s5: 0
Debug: 70453 153179 riscv.c:3071 register_get(): [0]{0} read 0x0 from s5 (valid=1)
Debug: 70454 153179 riscv-013.c:3416 riscv013_get_register(): [0] reading register s6 on hart 0
Debug: 70455 153179 riscv-013.c:765 execute_abstract_command(): command=0x221016; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1016
Debug: 70501 153181 riscv-013.c:1415 register_read_direct(): {0} s6 = 0x0
Debug: 70502 153181 riscv.c:2795 riscv_get_register_on_hart(): {0} s6: 0
Debug: 70503 153181 riscv.c:3071 register_get(): [0]{0} read 0x0 from s6 (valid=1)
Debug: 70504 153181 riscv-013.c:3416 riscv013_get_register(): [0] reading register s7 on hart 0
Debug: 70505 153181 riscv-013.c:765 execute_abstract_command(): command=0x221017; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1017
Debug: 70551 153182 riscv-013.c:1415 register_read_direct(): {0} s7 = 0x0
Debug: 70552 153182 riscv.c:2795 riscv_get_register_on_hart(): {0} s7: 0
Debug: 70553 153182 riscv.c:3071 register_get(): [0]{0} read 0x0 from s7 (valid=1)
Debug: 70554 153182 riscv-013.c:3416 riscv013_get_register(): [0] reading register s8 on hart 0
Debug: 70555 153182 riscv-013.c:765 execute_abstract_command(): command=0x221018; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1018
Debug: 70601 153183 riscv-013.c:1415 register_read_direct(): {0} s8 = 0x0
Debug: 70602 153183 riscv.c:2795 riscv_get_register_on_hart(): {0} s8: 0
Debug: 70603 153183 riscv.c:3071 register_get(): [0]{0} read 0x0 from s8 (valid=1)
Debug: 70604 153183 riscv-013.c:3416 riscv013_get_register(): [0] reading register s9 on hart 0
Debug: 70605 153183 riscv-013.c:765 execute_abstract_command(): command=0x221019; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1019
Debug: 70651 153185 riscv-013.c:1415 register_read_direct(): {0} s9 = 0x0
Debug: 70652 153185 riscv.c:2795 riscv_get_register_on_hart(): {0} s9: 0
Debug: 70653 153185 riscv.c:3071 register_get(): [0]{0} read 0x0 from s9 (valid=1)
Debug: 70654 153185 riscv-013.c:3416 riscv013_get_register(): [0] reading register s10 on hart 0
Debug: 70655 153185 riscv-013.c:765 execute_abstract_command(): command=0x22101a; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101a
Debug: 70701 153186 riscv-013.c:1415 register_read_direct(): {0} s10 = 0x0
Debug: 70702 153186 riscv.c:2795 riscv_get_register_on_hart(): {0} s10: 0
Debug: 70703 153186 riscv.c:3071 register_get(): [0]{0} read 0x0 from s10 (valid=1)
Debug: 70704 153186 riscv-013.c:3416 riscv013_get_register(): [0] reading register s11 on hart 0
Debug: 70705 153186 riscv-013.c:765 execute_abstract_command(): command=0x22101b; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101b
Debug: 70751 153188 riscv-013.c:1415 register_read_direct(): {0} s11 = 0x0
Debug: 70752 153188 riscv.c:2795 riscv_get_register_on_hart(): {0} s11: 0
Debug: 70753 153188 riscv.c:3071 register_get(): [0]{0} read 0x0 from s11 (valid=1)
Debug: 70754 153188 riscv-013.c:3416 riscv013_get_register(): [0] reading register t3 on hart 0
Debug: 70755 153188 riscv-013.c:765 execute_abstract_command(): command=0x22101c; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101c
Debug: 70801 153189 riscv-013.c:1415 register_read_direct(): {0} t3 = 0x0
Debug: 70802 153189 riscv.c:2795 riscv_get_register_on_hart(): {0} t3: 0
Debug: 70803 153189 riscv.c:3071 register_get(): [0]{0} read 0x0 from t3 (valid=1)
Debug: 70804 153189 riscv-013.c:3416 riscv013_get_register(): [0] reading register t4 on hart 0
Debug: 70805 153189 riscv-013.c:765 execute_abstract_command(): command=0x22101d; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101d
Debug: 70851 153190 riscv-013.c:1415 register_read_direct(): {0} t4 = 0x0
Debug: 70852 153190 riscv.c:2795 riscv_get_register_on_hart(): {0} t4: 0
Debug: 70853 153190 riscv.c:3071 register_get(): [0]{0} read 0x0 from t4 (valid=1)
Debug: 70854 153190 riscv-013.c:3416 riscv013_get_register(): [0] reading register t5 on hart 0
Debug: 70855 153190 riscv-013.c:765 execute_abstract_command(): command=0x22101e; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101e
Debug: 70901 153192 riscv-013.c:1415 register_read_direct(): {0} t5 = 0x0
Debug: 70902 153192 riscv.c:2795 riscv_get_register_on_hart(): {0} t5: 0
Debug: 70903 153192 riscv.c:3071 register_get(): [0]{0} read 0x0 from t5 (valid=1)
Debug: 70904 153192 riscv-013.c:3416 riscv013_get_register(): [0] reading register t6 on hart 0
Debug: 70905 153192 riscv-013.c:765 execute_abstract_command(): command=0x22101f; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101f
Debug: 70951 153193 riscv-013.c:1415 register_read_direct(): {0} t6 = 0x0
Debug: 70952 153193 riscv.c:2795 riscv_get_register_on_hart(): {0} t6: 0
Debug: 70953 153193 riscv.c:3071 register_get(): [0]{0} read 0x0 from t6 (valid=1)
Debug: 70954 153193 riscv-013.c:3416 riscv013_get_register(): [0] reading register pc on hart 0
Debug: 70955 153193 riscv-013.c:765 execute_abstract_command(): command=0x2207b1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b1
Debug: 71001 153195 riscv-013.c:1415 register_read_direct(): {0} dpc = 0x4202a012
Debug: 71002 153195 riscv-013.c:3424 riscv013_get_register(): [0] read PC from DPC: 0x4202a012
Debug: 71003 153195 riscv.c:2795 riscv_get_register_on_hart(): {0} pc: 4202a012
Debug: 71004 153195 riscv.c:3071 register_get(): [0]{0} read 0x4202a012 from pc (valid=1)
Debug: 71005 153195 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$00000000c8820042e0e0c93f00fcc83f288fc73fa67f05400f000000000000000000000000000000010000000000000003000000000000000100000000200c60010000002cf8c93f000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000012a00242#5a'
Debug: 71006 153195 gdb_server.c:3358 gdb_input_inner(): received packet: 'vCont;s:3fc9ed78;c'
Debug: 71007 153195 FreeRTOS.c:405 FreeRTOS_find_target_from_threadid(): Find target for thr 0x3fc9ed78
Debug: 71008 153195 FreeRTOS.c:433 FreeRTOS_target_for_threadid(): target found : esp32c3
Debug: 71009 153195 gdb_server.c:2912 gdb_handle_vcont_packet(): target esp32c3 single-step thread 3fc9ed78
Debug: 71010 153195 target.c:1634 target_call_event_callbacks(): target event 5 (gdb-start) for core esp32c3
Debug: 71011 153195 riscv.c:965 old_or_new_riscv_step(): handle_breakpoints=0
Debug: 71012 153195 riscv.c:1845 riscv_openocd_step(): stepping rtos hart
Debug: 71013 153195 riscv.c:2624 riscv_step_rtos_hart(): stepping hart 0
Debug: 71032 153195 riscv.c:2699 riscv_invalidate_register_cache(): [0]
Debug: 71033 153195 program.c:33 riscv_program_write(): debug_buffer[00] = DASM(0x0000100f)
Debug: 71034 153195 riscv-013.c:3695 riscv013_write_debug_buffer(): cache hit for 0x100f @0
Debug: 71035 153195 program.c:33 riscv_program_write(): debug_buffer[01] = DASM(0x0000000f)
Debug: 71036 153195 riscv-013.c:3695 riscv013_write_debug_buffer(): cache hit for 0xf @1
Debug: 71037 153195 program.c:33 riscv_program_write(): debug_buffer[02] = DASM(0x00100073)
Debug: 71038 153195 riscv-013.c:3695 riscv013_write_debug_buffer(): cache hit for 0x100073 @2
Debug: 71039 153195 riscv-013.c:765 execute_abstract_command(): command=0x241000; access register, size=32, postexec=1, transfer=0, write=0, regno=0x1000
Debug: 71067 153196 program.c:33 riscv_program_write(): debug_buffer[00] = DASM(0x0000100f)
Debug: 71068 153196 riscv-013.c:3695 riscv013_write_debug_buffer(): cache hit for 0x100f @0
Debug: 71069 153196 program.c:33 riscv_program_write(): debug_buffer[01] = DASM(0x0000000f)
Debug: 71070 153196 riscv-013.c:3695 riscv013_write_debug_buffer(): cache hit for 0xf @1
Debug: 71071 153196 program.c:33 riscv_program_write(): debug_buffer[02] = DASM(0x00100073)
Debug: 71072 153196 riscv-013.c:3695 riscv013_write_debug_buffer(): cache hit for 0x100073 @2
Debug: 71073 153196 riscv-013.c:765 execute_abstract_command(): command=0x241000; access register, size=32, postexec=1, transfer=0, write=0, regno=0x1000
Debug: 71101 153197 riscv-013.c:765 execute_abstract_command(): command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0
Debug: 71147 153199 riscv-013.c:1415 register_read_direct(): {0} dcsr = 0x4000b107
Debug: 71148 153199 riscv.c:2756 riscv_set_register_on_hart(): {0} dcsr <- 4000b107
Debug: 71149 153199 riscv-013.c:3440 riscv013_set_register(): [0] writing 0x4000b107 to register dcsr on hart 0
Debug: 71150 153199 riscv-013.c:1227 register_write_direct(): {0} dcsr <- 0x4000b107
Debug: 71169 153200 riscv-013.c:765 execute_abstract_command(): command=0x2307b0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b0
Debug: 71197 153201 riscv-013.c:4130 riscv013_step_or_resume_current_hart(): resuming hart 0 (for step?=1)
Debug: 71270 153203 riscv.c:2699 riscv_invalidate_register_cache(): [0]
Debug: 71289 153204 target.c:1634 target_call_event_callbacks(): target event 2 (resumed) for core esp32c3
Debug: 71290 153204 target.c:1634 target_call_event_callbacks(): target event 0 (gdb-halt) for core esp32c3
Debug: 71291 153204 target.c:1634 target_call_event_callbacks(): target event 1 (halted) for core esp32c3
Debug: 71292 153204 target.c:4631 target_handle_event(): target(0): esp32c3 (riscv) event: 1 (halted) action:  esp32c3_wdt_disable 
Debug: 71293 153204 command.c:143 script_debug(): command - command command mode
Debug: 71294 153204 command.c:143 script_debug(): command - mww mww 0x6001f064 0x50D83AA1
Debug: 71314 153204 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$O#4f'
Debug: 71351 153206 riscv-013.c:3076 write_memory_bus_v1(): transferring burst starting at address 0x6001f064
Debug: 71352 153206 riscv-013.c:2072 log_memory_access(): M[0x6001f064] writes 0x50d83aa1
Debug: 71362 153206 batch.c:164 dump_field(): 41b 5i w 50d83aa1 @3c -> + 00000000 @39
Debug: 71363 153206 batch.c:164 dump_field(): 41b 5i - 00000000 @00 -> + 50d83aa1 @3c
Debug: 71373 153206 command.c:143 script_debug(): command - mww mww 0x6001F048 0
Debug: 71393 153207 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$O#4f'
Debug: 71430 153208 riscv-013.c:3076 write_memory_bus_v1(): transferring burst starting at address 0x6001f048
Debug: 71431 153208 riscv-013.c:2072 log_memory_access(): M[0x6001f048] writes 0x00000000
Debug: 71441 153209 batch.c:164 dump_field(): 41b 5i w 00000000 @3c -> + 00000000 @39
Debug: 71442 153209 batch.c:164 dump_field(): 41b 5i - 00000000 @00 -> + 00000000 @3c
Debug: 71452 153209 command.c:143 script_debug(): command - mww mww 0x60020064 0x50D83AA1
Debug: 71472 153210 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$O#4f'
Debug: 71509 153211 riscv-013.c:3076 write_memory_bus_v1(): transferring burst starting at address 0x60020064
Debug: 71510 153211 riscv-013.c:2072 log_memory_access(): M[0x60020064] writes 0x50d83aa1
Debug: 71520 153211 batch.c:164 dump_field(): 41b 5i w 50d83aa1 @3c -> + 00000000 @39
Debug: 71521 153211 batch.c:164 dump_field(): 41b 5i - 00000000 @00 -> + 50d83aa1 @3c
Debug: 71531 153212 command.c:143 script_debug(): command - mww mww 0x60020048 0
Debug: 71551 153212 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$O#4f'
Debug: 71588 153214 riscv-013.c:3076 write_memory_bus_v1(): transferring burst starting at address 0x60020048
Debug: 71589 153214 riscv-013.c:2072 log_memory_access(): M[0x60020048] writes 0x00000000
Debug: 71599 153214 batch.c:164 dump_field(): 41b 5i w 00000000 @3c -> + 00000000 @39
Debug: 71600 153214 batch.c:164 dump_field(): 41b 5i - 00000000 @00 -> + 00000000 @3c
Debug: 71610 153214 command.c:143 script_debug(): command - mww mww 0x600080a8 0x50D83AA1
Debug: 71630 153215 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$O#4f'
Debug: 71667 153216 riscv-013.c:3076 write_memory_bus_v1(): transferring burst starting at address 0x600080a8
Debug: 71668 153216 riscv-013.c:2072 log_memory_access(): M[0x600080a8] writes 0x50d83aa1
Debug: 71678 153217 batch.c:164 dump_field(): 41b 5i w 50d83aa1 @3c -> + 00000000 @39
Debug: 71679 153217 batch.c:164 dump_field(): 41b 5i - 00000000 @00 -> + 50d83aa1 @3c
Debug: 71689 153217 command.c:143 script_debug(): command - mww mww 0x60008090 0
Debug: 71709 153218 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$O#4f'
Debug: 71746 153219 riscv-013.c:3076 write_memory_bus_v1(): transferring burst starting at address 0x60008090
Debug: 71747 153219 riscv-013.c:2072 log_memory_access(): M[0x60008090] writes 0x00000000
Debug: 71757 153219 batch.c:164 dump_field(): 41b 5i w 00000000 @3c -> + 00000000 @39
Debug: 71758 153219 batch.c:164 dump_field(): 41b 5i - 00000000 @00 -> + 00000000 @3c
Debug: 71768 153220 target.c:1634 target_call_event_callbacks(): target event 6 (gdb-end) for core esp32c3
Debug: 71787 153220 FreeRTOS.c:694 FreeRTOS_update_threads(): FreeRTOS_update_threads
Debug: 71842 153222 riscv-013.c:2072 log_memory_access(): M[0x3fc97e8c] reads 0x00000004
Debug: 71861 153223 target.c:2447 target_read_u32(): address: 0x3fc97e8c, value: 0x00000004
Debug: 71862 153223 FreeRTOS.c:745 FreeRTOS_update_threads(): Read uxCurrentNumberOfTasks at 0x3fc97e8c, value 4
Debug: 71917 153225 riscv-013.c:2072 log_memory_access(): M[0x3fc97e98] reads 0x00000004
Debug: 71936 153225 target.c:2447 target_read_u32(): address: 0x3fc97e98, value: 0x00000004
Debug: 71937 153225 FreeRTOS.c:766 FreeRTOS_update_threads(): Read uxTaskNumber at 0x3fc97e98, value 4
Error: 71938 153225 FreeRTOS.c:771 FreeRTOS_update_threads(): FreeRTOS uxTaskNumber seems to be corrupted!
Debug: 71939 153225 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$O4672656552544f532075785461736b4e756d626572207365656d7320746f20626520636f72727570746564210a#38'
Debug: 71940 153225 FreeRTOS.c:405 FreeRTOS_find_target_from_threadid(): Find target for thr 0x3fc9ed78
Debug: 71941 153225 FreeRTOS.c:433 FreeRTOS_target_for_threadid(): target found : esp32c3
Debug: 71942 153225 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$T05thread:3fc9ed78;#13'
Debug: 71943 153226 gdb_server.c:3358 gdb_input_inner(): received packet: 'g'
Debug: 71944 153226 riscv.c:1357 riscv_get_gdb_reg_list_internal(): rtos_hartid=0, current_hartid=0, reg_class=1, read=1
Debug: 71945 153226 riscv-013.c:3416 riscv013_get_register(): [0] reading register zero on hart 0
Debug: 71946 153226 riscv.c:2795 riscv_get_register_on_hart(): {0} zero: 0
Debug: 71947 153226 riscv.c:3071 register_get(): [0]{0} read 0x0 from zero (valid=1)
Debug: 71948 153226 riscv-013.c:3416 riscv013_get_register(): [0] reading register ra on hart 0
Debug: 71949 153226 riscv-013.c:765 execute_abstract_command(): command=0x221001; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1001
Debug: 71995 153227 riscv-013.c:1415 register_read_direct(): {0} ra = 0x420082c8
Debug: 71996 153227 riscv.c:2795 riscv_get_register_on_hart(): {0} ra: 420082c8
Debug: 71997 153227 riscv.c:3071 register_get(): [0]{0} read 0x420082c8 from ra (valid=1)
Debug: 71998 153227 riscv-013.c:3416 riscv013_get_register(): [0] reading register sp on hart 0
Debug: 71999 153227 riscv-013.c:765 execute_abstract_command(): command=0x221002; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1002
Debug: 72045 153229 riscv-013.c:1415 register_read_direct(): {0} sp = 0x3fc9e0e0
Debug: 72046 153229 riscv.c:2795 riscv_get_register_on_hart(): {0} sp: 3fc9e0e0
Debug: 72047 153229 riscv.c:3071 register_get(): [0]{0} read 0x3fc9e0e0 from sp (valid=1)
Debug: 72048 153229 riscv-013.c:3416 riscv013_get_register(): [0] reading register gp on hart 0
Debug: 72049 153229 riscv-013.c:765 execute_abstract_command(): command=0x221003; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1003
Debug: 72095 153230 riscv-013.c:1415 register_read_direct(): {0} gp = 0x3fc8fc00
Debug: 72096 153230 riscv.c:2795 riscv_get_register_on_hart(): {0} gp: 3fc8fc00
Debug: 72097 153230 riscv.c:3071 register_get(): [0]{0} read 0x3fc8fc00 from gp (valid=1)
Debug: 72098 153230 riscv-013.c:3416 riscv013_get_register(): [0] reading register tp on hart 0
Debug: 72099 153231 riscv-013.c:765 execute_abstract_command(): command=0x221004; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1004
Debug: 72145 153232 riscv-013.c:1415 register_read_direct(): {0} tp = 0x3fc78f28
Debug: 72146 153232 riscv.c:2795 riscv_get_register_on_hart(): {0} tp: 3fc78f28
Debug: 72147 153232 riscv.c:3071 register_get(): [0]{0} read 0x3fc78f28 from tp (valid=1)
Debug: 72148 153232 riscv-013.c:3416 riscv013_get_register(): [0] reading register t0 on hart 0
Debug: 72149 153232 riscv-013.c:765 execute_abstract_command(): command=0x221005; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1005
Debug: 72195 153234 riscv-013.c:1415 register_read_direct(): {0} t0 = 0x40057fa6
Debug: 72196 153234 riscv.c:2795 riscv_get_register_on_hart(): {0} t0: 40057fa6
Debug: 72197 153234 riscv.c:3071 register_get(): [0]{0} read 0x40057fa6 from t0 (valid=1)
Debug: 72198 153234 riscv-013.c:3416 riscv013_get_register(): [0] reading register t1 on hart 0
Debug: 72199 153234 riscv-013.c:765 execute_abstract_command(): command=0x221006; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1006
Debug: 72245 153235 riscv-013.c:1415 register_read_direct(): {0} t1 = 0xf
Debug: 72246 153235 riscv.c:2795 riscv_get_register_on_hart(): {0} t1: f
Debug: 72247 153235 riscv.c:3071 register_get(): [0]{0} read 0xf from t1 (valid=1)
Debug: 72248 153235 riscv-013.c:3416 riscv013_get_register(): [0] reading register t2 on hart 0
Debug: 72249 153235 riscv-013.c:765 execute_abstract_command(): command=0x221007; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1007
Debug: 72295 153237 riscv-013.c:1415 register_read_direct(): {0} t2 = 0x0
Debug: 72296 153237 riscv.c:2795 riscv_get_register_on_hart(): {0} t2: 0
Debug: 72297 153237 riscv.c:3071 register_get(): [0]{0} read 0x0 from t2 (valid=1)
Debug: 72298 153237 riscv-013.c:3416 riscv013_get_register(): [0] reading register s0 on hart 0
Debug: 72299 153237 riscv-013.c:765 execute_abstract_command(): command=0x221008; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1008
Debug: 72345 153238 riscv-013.c:1415 register_read_direct(): {0} s0 = 0x0
Debug: 72346 153238 riscv.c:2795 riscv_get_register_on_hart(): {0} s0: 0
Debug: 72347 153238 riscv.c:3071 register_get(): [0]{0} read 0x0 from fp (valid=1)
Debug: 72348 153238 riscv-013.c:3416 riscv013_get_register(): [0] reading register s1 on hart 0
Debug: 72349 153238 riscv-013.c:765 execute_abstract_command(): command=0x221009; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1009
Debug: 72395 153240 riscv-013.c:1415 register_read_direct(): {0} s1 = 0x0
Debug: 72396 153240 riscv.c:2795 riscv_get_register_on_hart(): {0} s1: 0
Debug: 72397 153240 riscv.c:3071 register_get(): [0]{0} read 0x0 from s1 (valid=1)
Debug: 72398 153240 riscv-013.c:3416 riscv013_get_register(): [0] reading register a0 on hart 0
Debug: 72399 153240 riscv-013.c:765 execute_abstract_command(): command=0x22100a; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100a
Debug: 72445 153242 riscv-013.c:1415 register_read_direct(): {0} a0 = 0x1
Debug: 72446 153242 riscv.c:2795 riscv_get_register_on_hart(): {0} a0: 1
Debug: 72447 153242 riscv.c:3071 register_get(): [0]{0} read 0x1 from a0 (valid=1)
Debug: 72448 153242 riscv-013.c:3416 riscv013_get_register(): [0] reading register a1 on hart 0
Debug: 72449 153242 riscv-013.c:765 execute_abstract_command(): command=0x22100b; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100b
Debug: 72495 153243 riscv-013.c:1415 register_read_direct(): {0} a1 = 0x0
Debug: 72496 153243 riscv.c:2795 riscv_get_register_on_hart(): {0} a1: 0
Debug: 72497 153243 riscv.c:3071 register_get(): [0]{0} read 0x0 from a1 (valid=1)
Debug: 72498 153243 riscv-013.c:3416 riscv013_get_register(): [0] reading register a2 on hart 0
Debug: 72499 153243 riscv-013.c:765 execute_abstract_command(): command=0x22100c; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100c
Debug: 72545 153245 riscv-013.c:1415 register_read_direct(): {0} a2 = 0x3
Debug: 72546 153245 riscv.c:2795 riscv_get_register_on_hart(): {0} a2: 3
Debug: 72547 153245 riscv.c:3071 register_get(): [0]{0} read 0x3 from a2 (valid=1)
Debug: 72548 153245 riscv-013.c:3416 riscv013_get_register(): [0] reading register a3 on hart 0
Debug: 72549 153245 riscv-013.c:765 execute_abstract_command(): command=0x22100d; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100d
Debug: 72595 153246 riscv-013.c:1415 register_read_direct(): {0} a3 = 0x0
Debug: 72596 153246 riscv.c:2795 riscv_get_register_on_hart(): {0} a3: 0
Debug: 72597 153246 riscv.c:3071 register_get(): [0]{0} read 0x0 from a3 (valid=1)
Debug: 72598 153246 riscv-013.c:3416 riscv013_get_register(): [0] reading register a4 on hart 0
Debug: 72599 153246 riscv-013.c:765 execute_abstract_command(): command=0x22100e; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100e
Debug: 72645 153248 riscv-013.c:1415 register_read_direct(): {0} a4 = 0x1
Debug: 72646 153248 riscv.c:2795 riscv_get_register_on_hart(): {0} a4: 1
Debug: 72647 153248 riscv.c:3071 register_get(): [0]{0} read 0x1 from a4 (valid=1)
Debug: 72648 153248 riscv-013.c:3416 riscv013_get_register(): [0] reading register a5 on hart 0
Debug: 72649 153248 riscv-013.c:765 execute_abstract_command(): command=0x22100f; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100f
Debug: 72695 153249 riscv-013.c:1415 register_read_direct(): {0} a5 = 0x600c2000
Debug: 72696 153249 riscv.c:2795 riscv_get_register_on_hart(): {0} a5: 600c2000
Debug: 72697 153249 riscv.c:3071 register_get(): [0]{0} read 0x600c2000 from a5 (valid=1)
Debug: 72698 153249 riscv-013.c:3416 riscv013_get_register(): [0] reading register a6 on hart 0
Debug: 72699 153250 riscv-013.c:765 execute_abstract_command(): command=0x221010; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1010
Debug: 72745 153251 riscv-013.c:1415 register_read_direct(): {0} a6 = 0x1
Debug: 72746 153251 riscv.c:2795 riscv_get_register_on_hart(): {0} a6: 1
Debug: 72747 153251 riscv.c:3071 register_get(): [0]{0} read 0x1 from a6 (valid=1)
Debug: 72748 153251 riscv-013.c:3416 riscv013_get_register(): [0] reading register a7 on hart 0
Debug: 72749 153251 riscv-013.c:765 execute_abstract_command(): command=0x221011; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1011
Debug: 72795 153253 riscv-013.c:1415 register_read_direct(): {0} a7 = 0x3fc9f82c
Debug: 72796 153253 riscv.c:2795 riscv_get_register_on_hart(): {0} a7: 3fc9f82c
Debug: 72797 153253 riscv.c:3071 register_get(): [0]{0} read 0x3fc9f82c from a7 (valid=1)
Debug: 72798 153253 riscv-013.c:3416 riscv013_get_register(): [0] reading register s2 on hart 0
Debug: 72799 153253 riscv-013.c:765 execute_abstract_command(): command=0x221012; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1012
Debug: 72845 153254 riscv-013.c:1415 register_read_direct(): {0} s2 = 0x0
Debug: 72846 153254 riscv.c:2795 riscv_get_register_on_hart(): {0} s2: 0
Debug: 72847 153254 riscv.c:3071 register_get(): [0]{0} read 0x0 from s2 (valid=1)
Debug: 72848 153254 riscv-013.c:3416 riscv013_get_register(): [0] reading register s3 on hart 0
Debug: 72849 153254 riscv-013.c:765 execute_abstract_command(): command=0x221013; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1013
Debug: 72895 153256 riscv-013.c:1415 register_read_direct(): {0} s3 = 0x0
Debug: 72896 153256 riscv.c:2795 riscv_get_register_on_hart(): {0} s3: 0
Debug: 72897 153256 riscv.c:3071 register_get(): [0]{0} read 0x0 from s3 (valid=1)
Debug: 72898 153256 riscv-013.c:3416 riscv013_get_register(): [0] reading register s4 on hart 0
Debug: 72899 153256 riscv-013.c:765 execute_abstract_command(): command=0x221014; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1014
Debug: 72945 153257 riscv-013.c:1415 register_read_direct(): {0} s4 = 0x0
Debug: 72946 153257 riscv.c:2795 riscv_get_register_on_hart(): {0} s4: 0
Debug: 72947 153257 riscv.c:3071 register_get(): [0]{0} read 0x0 from s4 (valid=1)
Debug: 72948 153257 riscv-013.c:3416 riscv013_get_register(): [0] reading register s5 on hart 0
Debug: 72949 153257 riscv-013.c:765 execute_abstract_command(): command=0x221015; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1015
Debug: 72995 153259 riscv-013.c:1415 register_read_direct(): {0} s5 = 0x0
Debug: 72996 153259 riscv.c:2795 riscv_get_register_on_hart(): {0} s5: 0
Debug: 72997 153259 riscv.c:3071 register_get(): [0]{0} read 0x0 from s5 (valid=1)
Debug: 72998 153259 riscv-013.c:3416 riscv013_get_register(): [0] reading register s6 on hart 0
Debug: 72999 153259 riscv-013.c:765 execute_abstract_command(): command=0x221016; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1016
Debug: 73045 153260 riscv-013.c:1415 register_read_direct(): {0} s6 = 0x0
Debug: 73046 153260 riscv.c:2795 riscv_get_register_on_hart(): {0} s6: 0
Debug: 73047 153260 riscv.c:3071 register_get(): [0]{0} read 0x0 from s6 (valid=1)
Debug: 73048 153260 riscv-013.c:3416 riscv013_get_register(): [0] reading register s7 on hart 0
Debug: 73049 153260 riscv-013.c:765 execute_abstract_command(): command=0x221017; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1017
Debug: 73095 153262 riscv-013.c:1415 register_read_direct(): {0} s7 = 0x0
Debug: 73096 153262 riscv.c:2795 riscv_get_register_on_hart(): {0} s7: 0
Debug: 73097 153262 riscv.c:3071 register_get(): [0]{0} read 0x0 from s7 (valid=1)
Debug: 73098 153262 riscv-013.c:3416 riscv013_get_register(): [0] reading register s8 on hart 0
Debug: 73099 153262 riscv-013.c:765 execute_abstract_command(): command=0x221018; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1018
Debug: 73145 153264 riscv-013.c:1415 register_read_direct(): {0} s8 = 0x0
Debug: 73146 153264 riscv.c:2795 riscv_get_register_on_hart(): {0} s8: 0
Debug: 73147 153264 riscv.c:3071 register_get(): [0]{0} read 0x0 from s8 (valid=1)
Debug: 73148 153264 riscv-013.c:3416 riscv013_get_register(): [0] reading register s9 on hart 0
Debug: 73149 153264 riscv-013.c:765 execute_abstract_command(): command=0x221019; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1019
Debug: 73195 153265 riscv-013.c:1415 register_read_direct(): {0} s9 = 0x0
Debug: 73196 153265 riscv.c:2795 riscv_get_register_on_hart(): {0} s9: 0
Debug: 73197 153265 riscv.c:3071 register_get(): [0]{0} read 0x0 from s9 (valid=1)
Debug: 73198 153265 riscv-013.c:3416 riscv013_get_register(): [0] reading register s10 on hart 0
Debug: 73199 153265 riscv-013.c:765 execute_abstract_command(): command=0x22101a; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101a
Debug: 73245 153267 riscv-013.c:1415 register_read_direct(): {0} s10 = 0x0
Debug: 73246 153267 riscv.c:2795 riscv_get_register_on_hart(): {0} s10: 0
Debug: 73247 153267 riscv.c:3071 register_get(): [0]{0} read 0x0 from s10 (valid=1)
Debug: 73248 153267 riscv-013.c:3416 riscv013_get_register(): [0] reading register s11 on hart 0
Debug: 73249 153267 riscv-013.c:765 execute_abstract_command(): command=0x22101b; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101b
Debug: 73295 153268 riscv-013.c:1415 register_read_direct(): {0} s11 = 0x0
Debug: 73296 153268 riscv.c:2795 riscv_get_register_on_hart(): {0} s11: 0
Debug: 73297 153268 riscv.c:3071 register_get(): [0]{0} read 0x0 from s11 (valid=1)
Debug: 73298 153268 riscv-013.c:3416 riscv013_get_register(): [0] reading register t3 on hart 0
Debug: 73299 153268 riscv-013.c:765 execute_abstract_command(): command=0x22101c; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101c
Debug: 73345 153270 riscv-013.c:1415 register_read_direct(): {0} t3 = 0x0
Debug: 73346 153270 riscv.c:2795 riscv_get_register_on_hart(): {0} t3: 0
Debug: 73347 153270 riscv.c:3071 register_get(): [0]{0} read 0x0 from t3 (valid=1)
Debug: 73348 153270 riscv-013.c:3416 riscv013_get_register(): [0] reading register t4 on hart 0
Debug: 73349 153270 riscv-013.c:765 execute_abstract_command(): command=0x22101d; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101d
Debug: 73395 153271 riscv-013.c:1415 register_read_direct(): {0} t4 = 0x0
Debug: 73396 153271 riscv.c:2795 riscv_get_register_on_hart(): {0} t4: 0
Debug: 73397 153271 riscv.c:3071 register_get(): [0]{0} read 0x0 from t4 (valid=1)
Debug: 73398 153271 riscv-013.c:3416 riscv013_get_register(): [0] reading register t5 on hart 0
Debug: 73399 153271 riscv-013.c:765 execute_abstract_command(): command=0x22101e; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101e
Debug: 73445 153273 riscv-013.c:1415 register_read_direct(): {0} t5 = 0x0
Debug: 73446 153273 riscv.c:2795 riscv_get_register_on_hart(): {0} t5: 0
Debug: 73447 153273 riscv.c:3071 register_get(): [0]{0} read 0x0 from t5 (valid=1)
Debug: 73448 153273 riscv-013.c:3416 riscv013_get_register(): [0] reading register t6 on hart 0
Debug: 73449 153273 riscv-013.c:765 execute_abstract_command(): command=0x22101f; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101f
Debug: 73495 153275 riscv-013.c:1415 register_read_direct(): {0} t6 = 0x0
Debug: 73496 153275 riscv.c:2795 riscv_get_register_on_hart(): {0} t6: 0
Debug: 73497 153275 riscv.c:3071 register_get(): [0]{0} read 0x0 from t6 (valid=1)
Debug: 73498 153275 riscv-013.c:3416 riscv013_get_register(): [0] reading register pc on hart 0
Debug: 73499 153275 riscv-013.c:765 execute_abstract_command(): command=0x2207b1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b1
Debug: 73545 153276 riscv-013.c:1415 register_read_direct(): {0} dpc = 0x4202a014
Debug: 73546 153276 riscv-013.c:3424 riscv013_get_register(): [0] read PC from DPC: 0x4202a014
Debug: 73547 153276 riscv.c:2795 riscv_get_register_on_hart(): {0} pc: 4202a014
Debug: 73548 153276 riscv.c:3071 register_get(): [0]{0} read 0x4202a014 from pc (valid=1)
Debug: 73549 153276 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$00000000c8820042e0e0c93f00fcc83f288fc73fa67f05400f000000000000000000000000000000010000000000000003000000000000000100000000200c60010000002cf8c93f000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000014a00242#5c'
Debug: 73550 153276 gdb_server.c:3358 gdb_input_inner(): received packet: 'vCont;s:3fc9ed78;c'
Debug: 73551 153276 FreeRTOS.c:405 FreeRTOS_find_target_from_threadid(): Find target for thr 0x3fc9ed78
Debug: 73552 153276 FreeRTOS.c:433 FreeRTOS_target_for_threadid(): target found : esp32c3
Debug: 73553 153276 gdb_server.c:2912 gdb_handle_vcont_packet(): target esp32c3 single-step thread 3fc9ed78
Debug: 73554 153276 target.c:1634 target_call_event_callbacks(): target event 5 (gdb-start) for core esp32c3
Debug: 73555 153276 riscv.c:965 old_or_new_riscv_step(): handle_breakpoints=0
Debug: 73556 153276 riscv.c:1845 riscv_openocd_step(): stepping rtos hart
Debug: 73557 153276 riscv.c:2624 riscv_step_rtos_hart(): stepping hart 0
Debug: 73576 153277 riscv.c:2699 riscv_invalidate_register_cache(): [0]
Debug: 73577 153277 program.c:33 riscv_program_write(): debug_buffer[00] = DASM(0x0000100f)
Debug: 73578 153277 riscv-013.c:3695 riscv013_write_debug_buffer(): cache hit for 0x100f @0
Debug: 73579 153277 program.c:33 riscv_program_write(): debug_buffer[01] = DASM(0x0000000f)
Debug: 73580 153277 riscv-013.c:3695 riscv013_write_debug_buffer(): cache hit for 0xf @1
Debug: 73581 153277 program.c:33 riscv_program_write(): debug_buffer[02] = DASM(0x00100073)
Debug: 73582 153277 riscv-013.c:3695 riscv013_write_debug_buffer(): cache hit for 0x100073 @2
Debug: 73583 153277 riscv-013.c:765 execute_abstract_command(): command=0x241000; access register, size=32, postexec=1, transfer=0, write=0, regno=0x1000
Debug: 73611 153278 program.c:33 riscv_program_write(): debug_buffer[00] = DASM(0x0000100f)
Debug: 73612 153278 riscv-013.c:3695 riscv013_write_debug_buffer(): cache hit for 0x100f @0
Debug: 73613 153278 program.c:33 riscv_program_write(): debug_buffer[01] = DASM(0x0000000f)
Debug: 73614 153278 riscv-013.c:3695 riscv013_write_debug_buffer(): cache hit for 0xf @1
Debug: 73615 153278 program.c:33 riscv_program_write(): debug_buffer[02] = DASM(0x00100073)
Debug: 73616 153278 riscv-013.c:3695 riscv013_write_debug_buffer(): cache hit for 0x100073 @2
Debug: 73617 153278 riscv-013.c:765 execute_abstract_command(): command=0x241000; access register, size=32, postexec=1, transfer=0, write=0, regno=0x1000
Debug: 73645 153279 riscv-013.c:765 execute_abstract_command(): command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0
Debug: 73691 153280 riscv-013.c:1415 register_read_direct(): {0} dcsr = 0x4000b107
Debug: 73692 153280 riscv.c:2756 riscv_set_register_on_hart(): {0} dcsr <- 4000b107
Debug: 73693 153280 riscv-013.c:3440 riscv013_set_register(): [0] writing 0x4000b107 to register dcsr on hart 0
Debug: 73694 153280 riscv-013.c:1227 register_write_direct(): {0} dcsr <- 0x4000b107
Debug: 73713 153281 riscv-013.c:765 execute_abstract_command(): command=0x2307b0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b0
Debug: 73741 153282 riscv-013.c:4130 riscv013_step_or_resume_current_hart(): resuming hart 0 (for step?=1)
Debug: 73814 153285 riscv.c:2699 riscv_invalidate_register_cache(): [0]
Debug: 73833 153285 target.c:1634 target_call_event_callbacks(): target event 2 (resumed) for core esp32c3
Debug: 73834 153285 target.c:1634 target_call_event_callbacks(): target event 0 (gdb-halt) for core esp32c3
Debug: 73835 153285 target.c:1634 target_call_event_callbacks(): target event 1 (halted) for core esp32c3
Debug: 73836 153285 target.c:4631 target_handle_event(): target(0): esp32c3 (riscv) event: 1 (halted) action:  esp32c3_wdt_disable 
Debug: 73837 153285 command.c:143 script_debug(): command - command command mode
Debug: 73838 153285 command.c:143 script_debug(): command - mww mww 0x6001f064 0x50D83AA1
Debug: 73858 153286 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$O#4f'
Debug: 73895 153287 riscv-013.c:3076 write_memory_bus_v1(): transferring burst starting at address 0x6001f064
Debug: 73896 153287 riscv-013.c:2072 log_memory_access(): M[0x6001f064] writes 0x50d83aa1
Debug: 73906 153287 batch.c:164 dump_field(): 41b 5i w 50d83aa1 @3c -> + 00000000 @39
Debug: 73907 153288 batch.c:164 dump_field(): 41b 5i - 00000000 @00 -> + 50d83aa1 @3c
Debug: 73917 153288 command.c:143 script_debug(): command - mww mww 0x6001F048 0
Debug: 73937 153288 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$O#4f'
Debug: 73974 153290 riscv-013.c:3076 write_memory_bus_v1(): transferring burst starting at address 0x6001f048
Debug: 73975 153290 riscv-013.c:2072 log_memory_access(): M[0x6001f048] writes 0x00000000
Debug: 73985 153290 batch.c:164 dump_field(): 41b 5i w 00000000 @3c -> + 00000000 @39
Debug: 73986 153290 batch.c:164 dump_field(): 41b 5i - 00000000 @00 -> + 00000000 @3c
Debug: 73996 153290 command.c:143 script_debug(): command - mww mww 0x60020064 0x50D83AA1
Debug: 74016 153291 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$O#4f'
Debug: 74053 153292 riscv-013.c:3076 write_memory_bus_v1(): transferring burst starting at address 0x60020064
Debug: 74054 153292 riscv-013.c:2072 log_memory_access(): M[0x60020064] writes 0x50d83aa1
Debug: 74064 153293 batch.c:164 dump_field(): 41b 5i w 50d83aa1 @3c -> + 00000000 @39
Debug: 74065 153293 batch.c:164 dump_field(): 41b 5i - 00000000 @00 -> + 50d83aa1 @3c
Debug: 74075 153293 command.c:143 script_debug(): command - mww mww 0x60020048 0
Debug: 74095 153294 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$O#4f'
Debug: 74132 153295 riscv-013.c:3076 write_memory_bus_v1(): transferring burst starting at address 0x60020048
Debug: 74133 153295 riscv-013.c:2072 log_memory_access(): M[0x60020048] writes 0x00000000
Debug: 74143 153295 batch.c:164 dump_field(): 41b 5i w 00000000 @3c -> + 00000000 @39
Debug: 74144 153295 batch.c:164 dump_field(): 41b 5i - 00000000 @00 -> + 00000000 @3c
Debug: 74154 153296 command.c:143 script_debug(): command - mww mww 0x600080a8 0x50D83AA1
Debug: 74174 153296 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$O#4f'
Debug: 74211 153298 riscv-013.c:3076 write_memory_bus_v1(): transferring burst starting at address 0x600080a8
Debug: 74212 153298 riscv-013.c:2072 log_memory_access(): M[0x600080a8] writes 0x50d83aa1
Debug: 74222 153298 batch.c:164 dump_field(): 41b 5i w 50d83aa1 @3c -> + 00000000 @39
Debug: 74223 153298 batch.c:164 dump_field(): 41b 5i - 00000000 @00 -> + 50d83aa1 @3c
Debug: 74233 153298 command.c:143 script_debug(): command - mww mww 0x60008090 0
Debug: 74253 153299 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$O#4f'
Debug: 74290 153300 riscv-013.c:3076 write_memory_bus_v1(): transferring burst starting at address 0x60008090
Debug: 74291 153300 riscv-013.c:2072 log_memory_access(): M[0x60008090] writes 0x00000000
Debug: 74301 153301 batch.c:164 dump_field(): 41b 5i w 00000000 @3c -> + 00000000 @39
Debug: 74302 153301 batch.c:164 dump_field(): 41b 5i - 00000000 @00 -> + 00000000 @3c
Debug: 74312 153301 target.c:1634 target_call_event_callbacks(): target event 6 (gdb-end) for core esp32c3
Debug: 74331 153302 FreeRTOS.c:694 FreeRTOS_update_threads(): FreeRTOS_update_threads
Debug: 74386 153303 riscv-013.c:2072 log_memory_access(): M[0x3fc97e8c] reads 0x00000004
Debug: 74405 153304 target.c:2447 target_read_u32(): address: 0x3fc97e8c, value: 0x00000004
Debug: 74406 153304 FreeRTOS.c:745 FreeRTOS_update_threads(): Read uxCurrentNumberOfTasks at 0x3fc97e8c, value 4
Debug: 74461 153305 riscv-013.c:2072 log_memory_access(): M[0x3fc97e98] reads 0x00000004
Debug: 74480 153306 target.c:2447 target_read_u32(): address: 0x3fc97e98, value: 0x00000004
Debug: 74481 153306 FreeRTOS.c:766 FreeRTOS_update_threads(): Read uxTaskNumber at 0x3fc97e98, value 4
Error: 74482 153306 FreeRTOS.c:771 FreeRTOS_update_threads(): FreeRTOS uxTaskNumber seems to be corrupted!
Debug: 74483 153306 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$O4672656552544f532075785461736b4e756d626572207365656d7320746f20626520636f72727570746564210a#38'
Debug: 74484 153306 FreeRTOS.c:405 FreeRTOS_find_target_from_threadid(): Find target for thr 0x3fc9ed78
Debug: 74485 153306 FreeRTOS.c:433 FreeRTOS_target_for_threadid(): target found : esp32c3
Debug: 74486 153306 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$T05thread:3fc9ed78;#13'
Debug: 74487 153306 gdb_server.c:3358 gdb_input_inner(): received packet: 'g'
Debug: 74488 153306 riscv.c:1357 riscv_get_gdb_reg_list_internal(): rtos_hartid=0, current_hartid=0, reg_class=1, read=1
Debug: 74489 153306 riscv-013.c:3416 riscv013_get_register(): [0] reading register zero on hart 0
Debug: 74490 153306 riscv.c:2795 riscv_get_register_on_hart(): {0} zero: 0
Debug: 74491 153306 riscv.c:3071 register_get(): [0]{0} read 0x0 from zero (valid=1)
Debug: 74492 153306 riscv-013.c:3416 riscv013_get_register(): [0] reading register ra on hart 0
Debug: 74493 153306 riscv-013.c:765 execute_abstract_command(): command=0x221001; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1001
Debug: 74539 153308 riscv-013.c:1415 register_read_direct(): {0} ra = 0x420082c8
Debug: 74540 153308 riscv.c:2795 riscv_get_register_on_hart(): {0} ra: 420082c8
Debug: 74541 153308 riscv.c:3071 register_get(): [0]{0} read 0x420082c8 from ra (valid=1)
Debug: 74542 153308 riscv-013.c:3416 riscv013_get_register(): [0] reading register sp on hart 0
Debug: 74543 153308 riscv-013.c:765 execute_abstract_command(): command=0x221002; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1002
Debug: 74589 153309 riscv-013.c:1415 register_read_direct(): {0} sp = 0x3fc9e0e0
Debug: 74590 153309 riscv.c:2795 riscv_get_register_on_hart(): {0} sp: 3fc9e0e0
Debug: 74591 153309 riscv.c:3071 register_get(): [0]{0} read 0x3fc9e0e0 from sp (valid=1)
Debug: 74592 153309 riscv-013.c:3416 riscv013_get_register(): [0] reading register gp on hart 0
Debug: 74593 153309 riscv-013.c:765 execute_abstract_command(): command=0x221003; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1003
Debug: 74639 153310 riscv-013.c:1415 register_read_direct(): {0} gp = 0x3fc8fc00
Debug: 74640 153310 riscv.c:2795 riscv_get_register_on_hart(): {0} gp: 3fc8fc00
Debug: 74641 153310 riscv.c:3071 register_get(): [0]{0} read 0x3fc8fc00 from gp (valid=1)
Debug: 74642 153310 riscv-013.c:3416 riscv013_get_register(): [0] reading register tp on hart 0
Debug: 74643 153310 riscv-013.c:765 execute_abstract_command(): command=0x221004; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1004
Debug: 74689 153312 riscv-013.c:1415 register_read_direct(): {0} tp = 0x3fc78f28
Debug: 74690 153312 riscv.c:2795 riscv_get_register_on_hart(): {0} tp: 3fc78f28
Debug: 74691 153312 riscv.c:3071 register_get(): [0]{0} read 0x3fc78f28 from tp (valid=1)
Debug: 74692 153312 riscv-013.c:3416 riscv013_get_register(): [0] reading register t0 on hart 0
Debug: 74693 153312 riscv-013.c:765 execute_abstract_command(): command=0x221005; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1005
Debug: 74739 153313 riscv-013.c:1415 register_read_direct(): {0} t0 = 0x40057fa6
Debug: 74740 153313 riscv.c:2795 riscv_get_register_on_hart(): {0} t0: 40057fa6
Debug: 74741 153313 riscv.c:3071 register_get(): [0]{0} read 0x40057fa6 from t0 (valid=1)
Debug: 74742 153313 riscv-013.c:3416 riscv013_get_register(): [0] reading register t1 on hart 0
Debug: 74743 153313 riscv-013.c:765 execute_abstract_command(): command=0x221006; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1006
Debug: 74789 153315 riscv-013.c:1415 register_read_direct(): {0} t1 = 0xf
Debug: 74790 153315 riscv.c:2795 riscv_get_register_on_hart(): {0} t1: f
Debug: 74791 153315 riscv.c:3071 register_get(): [0]{0} read 0xf from t1 (valid=1)
Debug: 74792 153315 riscv-013.c:3416 riscv013_get_register(): [0] reading register t2 on hart 0
Debug: 74793 153315 riscv-013.c:765 execute_abstract_command(): command=0x221007; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1007
Debug: 74839 153316 riscv-013.c:1415 register_read_direct(): {0} t2 = 0x0
Debug: 74840 153316 riscv.c:2795 riscv_get_register_on_hart(): {0} t2: 0
Debug: 74841 153316 riscv.c:3071 register_get(): [0]{0} read 0x0 from t2 (valid=1)
Debug: 74842 153316 riscv-013.c:3416 riscv013_get_register(): [0] reading register s0 on hart 0
Debug: 74843 153316 riscv-013.c:765 execute_abstract_command(): command=0x221008; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1008
Debug: 74889 153318 riscv-013.c:1415 register_read_direct(): {0} s0 = 0x0
Debug: 74890 153318 riscv.c:2795 riscv_get_register_on_hart(): {0} s0: 0
Debug: 74891 153318 riscv.c:3071 register_get(): [0]{0} read 0x0 from fp (valid=1)
Debug: 74892 153318 riscv-013.c:3416 riscv013_get_register(): [0] reading register s1 on hart 0
Debug: 74893 153318 riscv-013.c:765 execute_abstract_command(): command=0x221009; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1009
Debug: 74939 153319 riscv-013.c:1415 register_read_direct(): {0} s1 = 0x0
Debug: 74940 153319 riscv.c:2795 riscv_get_register_on_hart(): {0} s1: 0
Debug: 74941 153319 riscv.c:3071 register_get(): [0]{0} read 0x0 from s1 (valid=1)
Debug: 74942 153319 riscv-013.c:3416 riscv013_get_register(): [0] reading register a0 on hart 0
Debug: 74943 153319 riscv-013.c:765 execute_abstract_command(): command=0x22100a; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100a
Debug: 74989 153321 riscv-013.c:1415 register_read_direct(): {0} a0 = 0x1
Debug: 74990 153321 riscv.c:2795 riscv_get_register_on_hart(): {0} a0: 1
Debug: 74991 153321 riscv.c:3071 register_get(): [0]{0} read 0x1 from a0 (valid=1)
Debug: 74992 153321 riscv-013.c:3416 riscv013_get_register(): [0] reading register a1 on hart 0
Debug: 74993 153321 riscv-013.c:765 execute_abstract_command(): command=0x22100b; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100b
Debug: 75039 153322 riscv-013.c:1415 register_read_direct(): {0} a1 = 0x0
Debug: 75040 153322 riscv.c:2795 riscv_get_register_on_hart(): {0} a1: 0
Debug: 75041 153322 riscv.c:3071 register_get(): [0]{0} read 0x0 from a1 (valid=1)
Debug: 75042 153322 riscv-013.c:3416 riscv013_get_register(): [0] reading register a2 on hart 0
Debug: 75043 153322 riscv-013.c:765 execute_abstract_command(): command=0x22100c; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100c
Debug: 75089 153324 riscv-013.c:1415 register_read_direct(): {0} a2 = 0x3
Debug: 75090 153324 riscv.c:2795 riscv_get_register_on_hart(): {0} a2: 3
Debug: 75091 153324 riscv.c:3071 register_get(): [0]{0} read 0x3 from a2 (valid=1)
Debug: 75092 153324 riscv-013.c:3416 riscv013_get_register(): [0] reading register a3 on hart 0
Debug: 75093 153324 riscv-013.c:765 execute_abstract_command(): command=0x22100d; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100d
Debug: 75139 153326 riscv-013.c:1415 register_read_direct(): {0} a3 = 0x0
Debug: 75140 153326 riscv.c:2795 riscv_get_register_on_hart(): {0} a3: 0
Debug: 75141 153326 riscv.c:3071 register_get(): [0]{0} read 0x0 from a3 (valid=1)
Debug: 75142 153326 riscv-013.c:3416 riscv013_get_register(): [0] reading register a4 on hart 0
Debug: 75143 153326 riscv-013.c:765 execute_abstract_command(): command=0x22100e; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100e
Debug: 75189 153327 riscv-013.c:1415 register_read_direct(): {0} a4 = 0x1
Debug: 75190 153327 riscv.c:2795 riscv_get_register_on_hart(): {0} a4: 1
Debug: 75191 153327 riscv.c:3071 register_get(): [0]{0} read 0x1 from a4 (valid=1)
Debug: 75192 153327 riscv-013.c:3416 riscv013_get_register(): [0] reading register a5 on hart 0
Debug: 75193 153327 riscv-013.c:765 execute_abstract_command(): command=0x22100f; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100f
Debug: 75239 153329 riscv-013.c:1415 register_read_direct(): {0} a5 = 0x600c2000
Debug: 75240 153329 riscv.c:2795 riscv_get_register_on_hart(): {0} a5: 600c2000
Debug: 75241 153329 riscv.c:3071 register_get(): [0]{0} read 0x600c2000 from a5 (valid=1)
Debug: 75242 153329 riscv-013.c:3416 riscv013_get_register(): [0] reading register a6 on hart 0
Debug: 75243 153329 riscv-013.c:765 execute_abstract_command(): command=0x221010; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1010
Debug: 75289 153330 riscv-013.c:1415 register_read_direct(): {0} a6 = 0x1
Debug: 75290 153330 riscv.c:2795 riscv_get_register_on_hart(): {0} a6: 1
Debug: 75291 153330 riscv.c:3071 register_get(): [0]{0} read 0x1 from a6 (valid=1)
Debug: 75292 153330 riscv-013.c:3416 riscv013_get_register(): [0] reading register a7 on hart 0
Debug: 75293 153330 riscv-013.c:765 execute_abstract_command(): command=0x221011; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1011
Debug: 75339 153332 riscv-013.c:1415 register_read_direct(): {0} a7 = 0x3fc9f82c
Debug: 75340 153332 riscv.c:2795 riscv_get_register_on_hart(): {0} a7: 3fc9f82c
Debug: 75341 153332 riscv.c:3071 register_get(): [0]{0} read 0x3fc9f82c from a7 (valid=1)
Debug: 75342 153332 riscv-013.c:3416 riscv013_get_register(): [0] reading register s2 on hart 0
Debug: 75343 153332 riscv-013.c:765 execute_abstract_command(): command=0x221012; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1012
Debug: 75389 153334 riscv-013.c:1415 register_read_direct(): {0} s2 = 0x0
Debug: 75390 153334 riscv.c:2795 riscv_get_register_on_hart(): {0} s2: 0
Debug: 75391 153334 riscv.c:3071 register_get(): [0]{0} read 0x0 from s2 (valid=1)
Debug: 75392 153334 riscv-013.c:3416 riscv013_get_register(): [0] reading register s3 on hart 0
Debug: 75393 153334 riscv-013.c:765 execute_abstract_command(): command=0x221013; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1013
Debug: 75439 153335 riscv-013.c:1415 register_read_direct(): {0} s3 = 0x0
Debug: 75440 153335 riscv.c:2795 riscv_get_register_on_hart(): {0} s3: 0
Debug: 75441 153335 riscv.c:3071 register_get(): [0]{0} read 0x0 from s3 (valid=1)
Debug: 75442 153335 riscv-013.c:3416 riscv013_get_register(): [0] reading register s4 on hart 0
Debug: 75443 153335 riscv-013.c:765 execute_abstract_command(): command=0x221014; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1014
Debug: 75489 153337 riscv-013.c:1415 register_read_direct(): {0} s4 = 0x0
Debug: 75490 153337 riscv.c:2795 riscv_get_register_on_hart(): {0} s4: 0
Debug: 75491 153337 riscv.c:3071 register_get(): [0]{0} read 0x0 from s4 (valid=1)
Debug: 75492 153337 riscv-013.c:3416 riscv013_get_register(): [0] reading register s5 on hart 0
Debug: 75493 153337 riscv-013.c:765 execute_abstract_command(): command=0x221015; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1015
Debug: 75539 153338 riscv-013.c:1415 register_read_direct(): {0} s5 = 0x0
Debug: 75540 153338 riscv.c:2795 riscv_get_register_on_hart(): {0} s5: 0
Debug: 75541 153338 riscv.c:3071 register_get(): [0]{0} read 0x0 from s5 (valid=1)
Debug: 75542 153338 riscv-013.c:3416 riscv013_get_register(): [0] reading register s6 on hart 0
Debug: 75543 153338 riscv-013.c:765 execute_abstract_command(): command=0x221016; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1016
Debug: 75589 153340 riscv-013.c:1415 register_read_direct(): {0} s6 = 0x0
Debug: 75590 153340 riscv.c:2795 riscv_get_register_on_hart(): {0} s6: 0
Debug: 75591 153340 riscv.c:3071 register_get(): [0]{0} read 0x0 from s6 (valid=1)
Debug: 75592 153340 riscv-013.c:3416 riscv013_get_register(): [0] reading register s7 on hart 0
Debug: 75593 153340 riscv-013.c:765 execute_abstract_command(): command=0x221017; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1017
Debug: 75639 153342 riscv-013.c:1415 register_read_direct(): {0} s7 = 0x0
Debug: 75640 153342 riscv.c:2795 riscv_get_register_on_hart(): {0} s7: 0
Debug: 75641 153342 riscv.c:3071 register_get(): [0]{0} read 0x0 from s7 (valid=1)
Debug: 75642 153342 riscv-013.c:3416 riscv013_get_register(): [0] reading register s8 on hart 0
Debug: 75643 153342 riscv-013.c:765 execute_abstract_command(): command=0x221018; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1018
Debug: 75689 153343 riscv-013.c:1415 register_read_direct(): {0} s8 = 0x0
Debug: 75690 153343 riscv.c:2795 riscv_get_register_on_hart(): {0} s8: 0
Debug: 75691 153343 riscv.c:3071 register_get(): [0]{0} read 0x0 from s8 (valid=1)
Debug: 75692 153343 riscv-013.c:3416 riscv013_get_register(): [0] reading register s9 on hart 0
Debug: 75693 153343 riscv-013.c:765 execute_abstract_command(): command=0x221019; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1019
Debug: 75739 153345 riscv-013.c:1415 register_read_direct(): {0} s9 = 0x0
Debug: 75740 153345 riscv.c:2795 riscv_get_register_on_hart(): {0} s9: 0
Debug: 75741 153345 riscv.c:3071 register_get(): [0]{0} read 0x0 from s9 (valid=1)
Debug: 75742 153345 riscv-013.c:3416 riscv013_get_register(): [0] reading register s10 on hart 0
Debug: 75743 153345 riscv-013.c:765 execute_abstract_command(): command=0x22101a; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101a
Debug: 75789 153346 riscv-013.c:1415 register_read_direct(): {0} s10 = 0x0
Debug: 75790 153346 riscv.c:2795 riscv_get_register_on_hart(): {0} s10: 0
Debug: 75791 153346 riscv.c:3071 register_get(): [0]{0} read 0x0 from s10 (valid=1)
Debug: 75792 153346 riscv-013.c:3416 riscv013_get_register(): [0] reading register s11 on hart 0
Debug: 75793 153346 riscv-013.c:765 execute_abstract_command(): command=0x22101b; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101b
Debug: 75839 153348 riscv-013.c:1415 register_read_direct(): {0} s11 = 0x0
Debug: 75840 153348 riscv.c:2795 riscv_get_register_on_hart(): {0} s11: 0
Debug: 75841 153348 riscv.c:3071 register_get(): [0]{0} read 0x0 from s11 (valid=1)
Debug: 75842 153348 riscv-013.c:3416 riscv013_get_register(): [0] reading register t3 on hart 0
Debug: 75843 153348 riscv-013.c:765 execute_abstract_command(): command=0x22101c; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101c
Debug: 75889 153349 riscv-013.c:1415 register_read_direct(): {0} t3 = 0x0
Debug: 75890 153349 riscv.c:2795 riscv_get_register_on_hart(): {0} t3: 0
Debug: 75891 153349 riscv.c:3071 register_get(): [0]{0} read 0x0 from t3 (valid=1)
Debug: 75892 153349 riscv-013.c:3416 riscv013_get_register(): [0] reading register t4 on hart 0
Debug: 75893 153349 riscv-013.c:765 execute_abstract_command(): command=0x22101d; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101d
Debug: 75939 153351 riscv-013.c:1415 register_read_direct(): {0} t4 = 0x0
Debug: 75940 153351 riscv.c:2795 riscv_get_register_on_hart(): {0} t4: 0
Debug: 75941 153351 riscv.c:3071 register_get(): [0]{0} read 0x0 from t4 (valid=1)
Debug: 75942 153351 riscv-013.c:3416 riscv013_get_register(): [0] reading register t5 on hart 0
Debug: 75943 153351 riscv-013.c:765 execute_abstract_command(): command=0x22101e; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101e
Debug: 75989 153353 riscv-013.c:1415 register_read_direct(): {0} t5 = 0x0
Debug: 75990 153353 riscv.c:2795 riscv_get_register_on_hart(): {0} t5: 0
Debug: 75991 153353 riscv.c:3071 register_get(): [0]{0} read 0x0 from t5 (valid=1)
Debug: 75992 153353 riscv-013.c:3416 riscv013_get_register(): [0] reading register t6 on hart 0
Debug: 75993 153353 riscv-013.c:765 execute_abstract_command(): command=0x22101f; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101f
Debug: 76039 153354 riscv-013.c:1415 register_read_direct(): {0} t6 = 0x0
Debug: 76040 153354 riscv.c:2795 riscv_get_register_on_hart(): {0} t6: 0
Debug: 76041 153354 riscv.c:3071 register_get(): [0]{0} read 0x0 from t6 (valid=1)
Debug: 76042 153354 riscv-013.c:3416 riscv013_get_register(): [0] reading register pc on hart 0
Debug: 76043 153354 riscv-013.c:765 execute_abstract_command(): command=0x2207b1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b1
Debug: 76089 153356 riscv-013.c:1415 register_read_direct(): {0} dpc = 0x4202a016
Debug: 76090 153356 riscv-013.c:3424 riscv013_get_register(): [0] read PC from DPC: 0x4202a016
Debug: 76091 153356 riscv.c:2795 riscv_get_register_on_hart(): {0} pc: 4202a016
Debug: 76092 153356 riscv.c:3071 register_get(): [0]{0} read 0x4202a016 from pc (valid=1)
Debug: 76093 153356 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$00000000c8820042e0e0c93f00fcc83f288fc73fa67f05400f000000000000000000000000000000010000000000000003000000000000000100000000200c60010000002cf8c93f000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000016a00242#5e'
Debug: 76094 153356 gdb_server.c:3358 gdb_input_inner(): received packet: 'vCont;s:3fc9ed78;c'
Debug: 76095 153356 FreeRTOS.c:405 FreeRTOS_find_target_from_threadid(): Find target for thr 0x3fc9ed78
Debug: 76096 153356 FreeRTOS.c:433 FreeRTOS_target_for_threadid(): target found : esp32c3
Debug: 76097 153356 gdb_server.c:2912 gdb_handle_vcont_packet(): target esp32c3 single-step thread 3fc9ed78
Debug: 76098 153356 target.c:1634 target_call_event_callbacks(): target event 5 (gdb-start) for core esp32c3
Debug: 76099 153356 riscv.c:965 old_or_new_riscv_step(): handle_breakpoints=0
Debug: 76100 153356 riscv.c:1845 riscv_openocd_step(): stepping rtos hart
Debug: 76101 153356 riscv.c:2624 riscv_step_rtos_hart(): stepping hart 0
Debug: 76120 153357 riscv.c:2699 riscv_invalidate_register_cache(): [0]
Debug: 76121 153357 program.c:33 riscv_program_write(): debug_buffer[00] = DASM(0x0000100f)
Debug: 76122 153357 riscv-013.c:3695 riscv013_write_debug_buffer(): cache hit for 0x100f @0
Debug: 76123 153357 program.c:33 riscv_program_write(): debug_buffer[01] = DASM(0x0000000f)
Debug: 76124 153357 riscv-013.c:3695 riscv013_write_debug_buffer(): cache hit for 0xf @1
Debug: 76125 153357 program.c:33 riscv_program_write(): debug_buffer[02] = DASM(0x00100073)
Debug: 76126 153357 riscv-013.c:3695 riscv013_write_debug_buffer(): cache hit for 0x100073 @2
Debug: 76127 153357 riscv-013.c:765 execute_abstract_command(): command=0x241000; access register, size=32, postexec=1, transfer=0, write=0, regno=0x1000
Debug: 76155 153358 program.c:33 riscv_program_write(): debug_buffer[00] = DASM(0x0000100f)
Debug: 76156 153358 riscv-013.c:3695 riscv013_write_debug_buffer(): cache hit for 0x100f @0
Debug: 76157 153358 program.c:33 riscv_program_write(): debug_buffer[01] = DASM(0x0000000f)
Debug: 76158 153358 riscv-013.c:3695 riscv013_write_debug_buffer(): cache hit for 0xf @1
Debug: 76159 153358 program.c:33 riscv_program_write(): debug_buffer[02] = DASM(0x00100073)
Debug: 76160 153358 riscv-013.c:3695 riscv013_write_debug_buffer(): cache hit for 0x100073 @2
Debug: 76161 153358 riscv-013.c:765 execute_abstract_command(): command=0x241000; access register, size=32, postexec=1, transfer=0, write=0, regno=0x1000
Debug: 76189 153359 riscv-013.c:765 execute_abstract_command(): command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0
Debug: 76235 153360 riscv-013.c:1415 register_read_direct(): {0} dcsr = 0x4000b107
Debug: 76236 153360 riscv.c:2756 riscv_set_register_on_hart(): {0} dcsr <- 4000b107
Debug: 76237 153360 riscv-013.c:3440 riscv013_set_register(): [0] writing 0x4000b107 to register dcsr on hart 0
Debug: 76238 153360 riscv-013.c:1227 register_write_direct(): {0} dcsr <- 0x4000b107
Debug: 76257 153361 riscv-013.c:765 execute_abstract_command(): command=0x2307b0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b0
Debug: 76285 153362 riscv-013.c:4130 riscv013_step_or_resume_current_hart(): resuming hart 0 (for step?=1)
Debug: 76358 153364 riscv.c:2699 riscv_invalidate_register_cache(): [0]
Debug: 76377 153365 target.c:1634 target_call_event_callbacks(): target event 2 (resumed) for core esp32c3
Debug: 76378 153365 target.c:1634 target_call_event_callbacks(): target event 0 (gdb-halt) for core esp32c3
Debug: 76379 153365 target.c:1634 target_call_event_callbacks(): target event 1 (halted) for core esp32c3
Debug: 76380 153365 target.c:4631 target_handle_event(): target(0): esp32c3 (riscv) event: 1 (halted) action:  esp32c3_wdt_disable 
Debug: 76381 153365 command.c:143 script_debug(): command - command command mode
Debug: 76382 153365 command.c:143 script_debug(): command - mww mww 0x6001f064 0x50D83AA1
Debug: 76402 153366 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$O#4f'
Debug: 76439 153367 riscv-013.c:3076 write_memory_bus_v1(): transferring burst starting at address 0x6001f064
Debug: 76440 153367 riscv-013.c:2072 log_memory_access(): M[0x6001f064] writes 0x50d83aa1
Debug: 76450 153367 batch.c:164 dump_field(): 41b 5i w 50d83aa1 @3c -> + 00000000 @39
Debug: 76451 153367 batch.c:164 dump_field(): 41b 5i - 00000000 @00 -> + 50d83aa1 @3c
Debug: 76461 153368 command.c:143 script_debug(): command - mww mww 0x6001F048 0
Debug: 76481 153368 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$O#4f'
Debug: 76518 153370 riscv-013.c:3076 write_memory_bus_v1(): transferring burst starting at address 0x6001f048
Debug: 76519 153370 riscv-013.c:2072 log_memory_access(): M[0x6001f048] writes 0x00000000
Debug: 76529 153370 batch.c:164 dump_field(): 41b 5i w 00000000 @3c -> + 00000000 @39
Debug: 76530 153370 batch.c:164 dump_field(): 41b 5i - 00000000 @00 -> + 00000000 @3c
Debug: 76540 153370 command.c:143 script_debug(): command - mww mww 0x60020064 0x50D83AA1
Debug: 76560 153371 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$O#4f'
Debug: 76597 153372 riscv-013.c:3076 write_memory_bus_v1(): transferring burst starting at address 0x60020064
Debug: 76598 153372 riscv-013.c:2072 log_memory_access(): M[0x60020064] writes 0x50d83aa1
Debug: 76608 153373 batch.c:164 dump_field(): 41b 5i w 50d83aa1 @3c -> + 00000000 @39
Debug: 76609 153373 batch.c:164 dump_field(): 41b 5i - 00000000 @00 -> + 50d83aa1 @3c
Debug: 76619 153373 command.c:143 script_debug(): command - mww mww 0x60020048 0
Debug: 76639 153374 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$O#4f'
Debug: 76676 153375 riscv-013.c:3076 write_memory_bus_v1(): transferring burst starting at address 0x60020048
Debug: 76677 153375 riscv-013.c:2072 log_memory_access(): M[0x60020048] writes 0x00000000
Debug: 76687 153375 batch.c:164 dump_field(): 41b 5i w 00000000 @3c -> + 00000000 @39
Debug: 76688 153375 batch.c:164 dump_field(): 41b 5i - 00000000 @00 -> + 00000000 @3c
Debug: 76698 153376 command.c:143 script_debug(): command - mww mww 0x600080a8 0x50D83AA1
Debug: 76718 153376 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$O#4f'
Debug: 76755 153378 riscv-013.c:3076 write_memory_bus_v1(): transferring burst starting at address 0x600080a8
Debug: 76756 153378 riscv-013.c:2072 log_memory_access(): M[0x600080a8] writes 0x50d83aa1
Debug: 76766 153378 batch.c:164 dump_field(): 41b 5i w 50d83aa1 @3c -> + 00000000 @39
Debug: 76767 153378 batch.c:164 dump_field(): 41b 5i - 00000000 @00 -> + 50d83aa1 @3c
Debug: 76777 153378 command.c:143 script_debug(): command - mww mww 0x60008090 0
Debug: 76797 153379 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$O#4f'
Debug: 76834 153380 riscv-013.c:3076 write_memory_bus_v1(): transferring burst starting at address 0x60008090
Debug: 76835 153380 riscv-013.c:2072 log_memory_access(): M[0x60008090] writes 0x00000000
Debug: 76845 153380 batch.c:164 dump_field(): 41b 5i w 00000000 @3c -> + 00000000 @39
Debug: 76846 153381 batch.c:164 dump_field(): 41b 5i - 00000000 @00 -> + 00000000 @3c
Debug: 76856 153381 target.c:1634 target_call_event_callbacks(): target event 6 (gdb-end) for core esp32c3
Debug: 76875 153381 FreeRTOS.c:694 FreeRTOS_update_threads(): FreeRTOS_update_threads
Debug: 76930 153383 riscv-013.c:2072 log_memory_access(): M[0x3fc97e8c] reads 0x00000004
Debug: 76949 153384 target.c:2447 target_read_u32(): address: 0x3fc97e8c, value: 0x00000004
Debug: 76950 153384 FreeRTOS.c:745 FreeRTOS_update_threads(): Read uxCurrentNumberOfTasks at 0x3fc97e8c, value 4
Debug: 77005 153386 riscv-013.c:2072 log_memory_access(): M[0x3fc97e98] reads 0x00000004
Debug: 77024 153387 target.c:2447 target_read_u32(): address: 0x3fc97e98, value: 0x00000004
Debug: 77025 153387 FreeRTOS.c:766 FreeRTOS_update_threads(): Read uxTaskNumber at 0x3fc97e98, value 4
Error: 77026 153387 FreeRTOS.c:771 FreeRTOS_update_threads(): FreeRTOS uxTaskNumber seems to be corrupted!
Debug: 77027 153387 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$O4672656552544f532075785461736b4e756d626572207365656d7320746f20626520636f72727570746564210a#38'
Debug: 77028 153387 FreeRTOS.c:405 FreeRTOS_find_target_from_threadid(): Find target for thr 0x3fc9ed78
Debug: 77029 153387 FreeRTOS.c:433 FreeRTOS_target_for_threadid(): target found : esp32c3
Debug: 77030 153387 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$T05thread:3fc9ed78;#13'
Debug: 77031 153387 gdb_server.c:3358 gdb_input_inner(): received packet: 'g'
Debug: 77032 153387 riscv.c:1357 riscv_get_gdb_reg_list_internal(): rtos_hartid=0, current_hartid=0, reg_class=1, read=1
Debug: 77033 153387 riscv-013.c:3416 riscv013_get_register(): [0] reading register zero on hart 0
Debug: 77034 153387 riscv.c:2795 riscv_get_register_on_hart(): {0} zero: 0
Debug: 77035 153387 riscv.c:3071 register_get(): [0]{0} read 0x0 from zero (valid=1)
Debug: 77036 153387 riscv-013.c:3416 riscv013_get_register(): [0] reading register ra on hart 0
Debug: 77037 153387 riscv-013.c:765 execute_abstract_command(): command=0x221001; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1001
Debug: 77083 153388 riscv-013.c:1415 register_read_direct(): {0} ra = 0x40388016
Debug: 77084 153388 riscv.c:2795 riscv_get_register_on_hart(): {0} ra: 40388016
Debug: 77085 153388 riscv.c:3071 register_get(): [0]{0} read 0x40388016 from ra (valid=1)
Debug: 77086 153388 riscv-013.c:3416 riscv013_get_register(): [0] reading register sp on hart 0
Debug: 77087 153388 riscv-013.c:765 execute_abstract_command(): command=0x221002; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1002
Debug: 77133 153390 riscv-013.c:1415 register_read_direct(): {0} sp = 0x3fc9e0e0
Debug: 77134 153390 riscv.c:2795 riscv_get_register_on_hart(): {0} sp: 3fc9e0e0
Debug: 77135 153390 riscv.c:3071 register_get(): [0]{0} read 0x3fc9e0e0 from sp (valid=1)
Debug: 77136 153390 riscv-013.c:3416 riscv013_get_register(): [0] reading register gp on hart 0
Debug: 77137 153390 riscv-013.c:765 execute_abstract_command(): command=0x221003; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1003
Debug: 77183 153391 riscv-013.c:1415 register_read_direct(): {0} gp = 0x3fc8fc00
Debug: 77184 153391 riscv.c:2795 riscv_get_register_on_hart(): {0} gp: 3fc8fc00
Debug: 77185 153391 riscv.c:3071 register_get(): [0]{0} read 0x3fc8fc00 from gp (valid=1)
Debug: 77186 153391 riscv-013.c:3416 riscv013_get_register(): [0] reading register tp on hart 0
Debug: 77187 153391 riscv-013.c:765 execute_abstract_command(): command=0x221004; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1004
Debug: 77233 153393 riscv-013.c:1415 register_read_direct(): {0} tp = 0x3fc78f28
Debug: 77234 153393 riscv.c:2795 riscv_get_register_on_hart(): {0} tp: 3fc78f28
Debug: 77235 153393 riscv.c:3071 register_get(): [0]{0} read 0x3fc78f28 from tp (valid=1)
Debug: 77236 153393 riscv-013.c:3416 riscv013_get_register(): [0] reading register t0 on hart 0
Debug: 77237 153393 riscv-013.c:765 execute_abstract_command(): command=0x221005; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1005
Debug: 77283 153395 riscv-013.c:1415 register_read_direct(): {0} t0 = 0x40057fa6
Debug: 77284 153395 riscv.c:2795 riscv_get_register_on_hart(): {0} t0: 40057fa6
Debug: 77285 153395 riscv.c:3071 register_get(): [0]{0} read 0x40057fa6 from t0 (valid=1)
Debug: 77286 153395 riscv-013.c:3416 riscv013_get_register(): [0] reading register t1 on hart 0
Debug: 77287 153395 riscv-013.c:765 execute_abstract_command(): command=0x221006; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1006
Debug: 77333 153396 riscv-013.c:1415 register_read_direct(): {0} t1 = 0xf
Debug: 77334 153396 riscv.c:2795 riscv_get_register_on_hart(): {0} t1: f
Debug: 77335 153396 riscv.c:3071 register_get(): [0]{0} read 0xf from t1 (valid=1)
Debug: 77336 153396 riscv-013.c:3416 riscv013_get_register(): [0] reading register t2 on hart 0
Debug: 77337 153396 riscv-013.c:765 execute_abstract_command(): command=0x221007; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1007
Debug: 77383 153398 riscv-013.c:1415 register_read_direct(): {0} t2 = 0x0
Debug: 77384 153398 riscv.c:2795 riscv_get_register_on_hart(): {0} t2: 0
Debug: 77385 153398 riscv.c:3071 register_get(): [0]{0} read 0x0 from t2 (valid=1)
Debug: 77386 153398 riscv-013.c:3416 riscv013_get_register(): [0] reading register s0 on hart 0
Debug: 77387 153398 riscv-013.c:765 execute_abstract_command(): command=0x221008; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1008
Debug: 77433 153399 riscv-013.c:1415 register_read_direct(): {0} s0 = 0x0
Debug: 77434 153399 riscv.c:2795 riscv_get_register_on_hart(): {0} s0: 0
Debug: 77435 153399 riscv.c:3071 register_get(): [0]{0} read 0x0 from fp (valid=1)
Debug: 77436 153399 riscv-013.c:3416 riscv013_get_register(): [0] reading register s1 on hart 0
Debug: 77437 153399 riscv-013.c:765 execute_abstract_command(): command=0x221009; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1009
Debug: 77483 153401 riscv-013.c:1415 register_read_direct(): {0} s1 = 0x0
Debug: 77484 153401 riscv.c:2795 riscv_get_register_on_hart(): {0} s1: 0
Debug: 77485 153401 riscv.c:3071 register_get(): [0]{0} read 0x0 from s1 (valid=1)
Debug: 77486 153401 riscv-013.c:3416 riscv013_get_register(): [0] reading register a0 on hart 0
Debug: 77487 153401 riscv-013.c:765 execute_abstract_command(): command=0x22100a; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100a
Debug: 77533 153402 riscv-013.c:1415 register_read_direct(): {0} a0 = 0x1
Debug: 77534 153402 riscv.c:2795 riscv_get_register_on_hart(): {0} a0: 1
Debug: 77535 153402 riscv.c:3071 register_get(): [0]{0} read 0x1 from a0 (valid=1)
Debug: 77536 153402 riscv-013.c:3416 riscv013_get_register(): [0] reading register a1 on hart 0
Debug: 77537 153402 riscv-013.c:765 execute_abstract_command(): command=0x22100b; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100b
Debug: 77583 153404 riscv-013.c:1415 register_read_direct(): {0} a1 = 0x0
Debug: 77584 153404 riscv.c:2795 riscv_get_register_on_hart(): {0} a1: 0
Debug: 77585 153404 riscv.c:3071 register_get(): [0]{0} read 0x0 from a1 (valid=1)
Debug: 77586 153404 riscv-013.c:3416 riscv013_get_register(): [0] reading register a2 on hart 0
Debug: 77587 153404 riscv-013.c:765 execute_abstract_command(): command=0x22100c; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100c
Debug: 77633 153406 riscv-013.c:1415 register_read_direct(): {0} a2 = 0x3
Debug: 77634 153406 riscv.c:2795 riscv_get_register_on_hart(): {0} a2: 3
Debug: 77635 153406 riscv.c:3071 register_get(): [0]{0} read 0x3 from a2 (valid=1)
Debug: 77636 153406 riscv-013.c:3416 riscv013_get_register(): [0] reading register a3 on hart 0
Debug: 77637 153406 riscv-013.c:765 execute_abstract_command(): command=0x22100d; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100d
Debug: 77683 153407 riscv-013.c:1415 register_read_direct(): {0} a3 = 0x0
Debug: 77684 153407 riscv.c:2795 riscv_get_register_on_hart(): {0} a3: 0
Debug: 77685 153407 riscv.c:3071 register_get(): [0]{0} read 0x0 from a3 (valid=1)
Debug: 77686 153407 riscv-013.c:3416 riscv013_get_register(): [0] reading register a4 on hart 0
Debug: 77687 153407 riscv-013.c:765 execute_abstract_command(): command=0x22100e; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100e
Debug: 77733 153409 riscv-013.c:1415 register_read_direct(): {0} a4 = 0x1
Debug: 77734 153409 riscv.c:2795 riscv_get_register_on_hart(): {0} a4: 1
Debug: 77735 153409 riscv.c:3071 register_get(): [0]{0} read 0x1 from a4 (valid=1)
Debug: 77736 153409 riscv-013.c:3416 riscv013_get_register(): [0] reading register a5 on hart 0
Debug: 77737 153409 riscv-013.c:765 execute_abstract_command(): command=0x22100f; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100f
Debug: 77783 153410 riscv-013.c:1415 register_read_direct(): {0} a5 = 0x600c2000
Debug: 77784 153410 riscv.c:2795 riscv_get_register_on_hart(): {0} a5: 600c2000
Debug: 77785 153410 riscv.c:3071 register_get(): [0]{0} read 0x600c2000 from a5 (valid=1)
Debug: 77786 153410 riscv-013.c:3416 riscv013_get_register(): [0] reading register a6 on hart 0
Debug: 77787 153410 riscv-013.c:765 execute_abstract_command(): command=0x221010; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1010
Debug: 77833 153412 riscv-013.c:1415 register_read_direct(): {0} a6 = 0x1
Debug: 77834 153412 riscv.c:2795 riscv_get_register_on_hart(): {0} a6: 1
Debug: 77835 153412 riscv.c:3071 register_get(): [0]{0} read 0x1 from a6 (valid=1)
Debug: 77836 153412 riscv-013.c:3416 riscv013_get_register(): [0] reading register a7 on hart 0
Debug: 77837 153412 riscv-013.c:765 execute_abstract_command(): command=0x221011; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1011
Debug: 77883 153413 riscv-013.c:1415 register_read_direct(): {0} a7 = 0x3fc9f82c
Debug: 77884 153413 riscv.c:2795 riscv_get_register_on_hart(): {0} a7: 3fc9f82c
Debug: 77885 153413 riscv.c:3071 register_get(): [0]{0} read 0x3fc9f82c from a7 (valid=1)
Debug: 77886 153413 riscv-013.c:3416 riscv013_get_register(): [0] reading register s2 on hart 0
Debug: 77887 153413 riscv-013.c:765 execute_abstract_command(): command=0x221012; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1012
Debug: 77933 153415 riscv-013.c:1415 register_read_direct(): {0} s2 = 0x0
Debug: 77934 153415 riscv.c:2795 riscv_get_register_on_hart(): {0} s2: 0
Debug: 77935 153415 riscv.c:3071 register_get(): [0]{0} read 0x0 from s2 (valid=1)
Debug: 77936 153415 riscv-013.c:3416 riscv013_get_register(): [0] reading register s3 on hart 0
Debug: 77937 153415 riscv-013.c:765 execute_abstract_command(): command=0x221013; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1013
Debug: 77983 153416 riscv-013.c:1415 register_read_direct(): {0} s3 = 0x0
Debug: 77984 153416 riscv.c:2795 riscv_get_register_on_hart(): {0} s3: 0
Debug: 77985 153416 riscv.c:3071 register_get(): [0]{0} read 0x0 from s3 (valid=1)
Debug: 77986 153416 riscv-013.c:3416 riscv013_get_register(): [0] reading register s4 on hart 0
Debug: 77987 153416 riscv-013.c:765 execute_abstract_command(): command=0x221014; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1014
Debug: 78033 153418 riscv-013.c:1415 register_read_direct(): {0} s4 = 0x0
Debug: 78034 153418 riscv.c:2795 riscv_get_register_on_hart(): {0} s4: 0
Debug: 78035 153418 riscv.c:3071 register_get(): [0]{0} read 0x0 from s4 (valid=1)
Debug: 78036 153418 riscv-013.c:3416 riscv013_get_register(): [0] reading register s5 on hart 0
Debug: 78037 153418 riscv-013.c:765 execute_abstract_command(): command=0x221015; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1015
Debug: 78083 153420 riscv-013.c:1415 register_read_direct(): {0} s5 = 0x0
Debug: 78084 153420 riscv.c:2795 riscv_get_register_on_hart(): {0} s5: 0
Debug: 78085 153420 riscv.c:3071 register_get(): [0]{0} read 0x0 from s5 (valid=1)
Debug: 78086 153420 riscv-013.c:3416 riscv013_get_register(): [0] reading register s6 on hart 0
Debug: 78087 153420 riscv-013.c:765 execute_abstract_command(): command=0x221016; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1016
Debug: 78133 153421 riscv-013.c:1415 register_read_direct(): {0} s6 = 0x0
Debug: 78134 153421 riscv.c:2795 riscv_get_register_on_hart(): {0} s6: 0
Debug: 78135 153421 riscv.c:3071 register_get(): [0]{0} read 0x0 from s6 (valid=1)
Debug: 78136 153421 riscv-013.c:3416 riscv013_get_register(): [0] reading register s7 on hart 0
Debug: 78137 153421 riscv-013.c:765 execute_abstract_command(): command=0x221017; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1017
Debug: 78183 153423 riscv-013.c:1415 register_read_direct(): {0} s7 = 0x0
Debug: 78184 153423 riscv.c:2795 riscv_get_register_on_hart(): {0} s7: 0
Debug: 78185 153423 riscv.c:3071 register_get(): [0]{0} read 0x0 from s7 (valid=1)
Debug: 78186 153423 riscv-013.c:3416 riscv013_get_register(): [0] reading register s8 on hart 0
Debug: 78187 153423 riscv-013.c:765 execute_abstract_command(): command=0x221018; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1018
Debug: 78233 153424 riscv-013.c:1415 register_read_direct(): {0} s8 = 0x0
Debug: 78234 153424 riscv.c:2795 riscv_get_register_on_hart(): {0} s8: 0
Debug: 78235 153424 riscv.c:3071 register_get(): [0]{0} read 0x0 from s8 (valid=1)
Debug: 78236 153424 riscv-013.c:3416 riscv013_get_register(): [0] reading register s9 on hart 0
Debug: 78237 153424 riscv-013.c:765 execute_abstract_command(): command=0x221019; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1019
Debug: 78283 153426 riscv-013.c:1415 register_read_direct(): {0} s9 = 0x0
Debug: 78284 153426 riscv.c:2795 riscv_get_register_on_hart(): {0} s9: 0
Debug: 78285 153426 riscv.c:3071 register_get(): [0]{0} read 0x0 from s9 (valid=1)
Debug: 78286 153426 riscv-013.c:3416 riscv013_get_register(): [0] reading register s10 on hart 0
Debug: 78287 153426 riscv-013.c:765 execute_abstract_command(): command=0x22101a; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101a
Debug: 78333 153427 riscv-013.c:1415 register_read_direct(): {0} s10 = 0x0
Debug: 78334 153427 riscv.c:2795 riscv_get_register_on_hart(): {0} s10: 0
Debug: 78335 153427 riscv.c:3071 register_get(): [0]{0} read 0x0 from s10 (valid=1)
Debug: 78336 153427 riscv-013.c:3416 riscv013_get_register(): [0] reading register s11 on hart 0
Debug: 78337 153427 riscv-013.c:765 execute_abstract_command(): command=0x22101b; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101b
Debug: 78383 153429 riscv-013.c:1415 register_read_direct(): {0} s11 = 0x0
Debug: 78384 153429 riscv.c:2795 riscv_get_register_on_hart(): {0} s11: 0
Debug: 78385 153429 riscv.c:3071 register_get(): [0]{0} read 0x0 from s11 (valid=1)
Debug: 78386 153429 riscv-013.c:3416 riscv013_get_register(): [0] reading register t3 on hart 0
Debug: 78387 153429 riscv-013.c:765 execute_abstract_command(): command=0x22101c; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101c
Debug: 78433 153430 riscv-013.c:1415 register_read_direct(): {0} t3 = 0x0
Debug: 78434 153430 riscv.c:2795 riscv_get_register_on_hart(): {0} t3: 0
Debug: 78435 153430 riscv.c:3071 register_get(): [0]{0} read 0x0 from t3 (valid=1)
Debug: 78436 153430 riscv-013.c:3416 riscv013_get_register(): [0] reading register t4 on hart 0
Debug: 78437 153430 riscv-013.c:765 execute_abstract_command(): command=0x22101d; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101d
Debug: 78483 153432 riscv-013.c:1415 register_read_direct(): {0} t4 = 0x0
Debug: 78484 153432 riscv.c:2795 riscv_get_register_on_hart(): {0} t4: 0
Debug: 78485 153432 riscv.c:3071 register_get(): [0]{0} read 0x0 from t4 (valid=1)
Debug: 78486 153432 riscv-013.c:3416 riscv013_get_register(): [0] reading register t5 on hart 0
Debug: 78487 153432 riscv-013.c:765 execute_abstract_command(): command=0x22101e; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101e
Debug: 78533 153434 riscv-013.c:1415 register_read_direct(): {0} t5 = 0x0
Debug: 78534 153434 riscv.c:2795 riscv_get_register_on_hart(): {0} t5: 0
Debug: 78535 153434 riscv.c:3071 register_get(): [0]{0} read 0x0 from t5 (valid=1)
Debug: 78536 153434 riscv-013.c:3416 riscv013_get_register(): [0] reading register t6 on hart 0
Debug: 78537 153434 riscv-013.c:765 execute_abstract_command(): command=0x22101f; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101f
Debug: 78583 153435 riscv-013.c:1415 register_read_direct(): {0} t6 = 0x0
Debug: 78584 153435 riscv.c:2795 riscv_get_register_on_hart(): {0} t6: 0
Debug: 78585 153435 riscv.c:3071 register_get(): [0]{0} read 0x0 from t6 (valid=1)
Debug: 78586 153435 riscv-013.c:3416 riscv013_get_register(): [0] reading register pc on hart 0
Debug: 78587 153435 riscv-013.c:765 execute_abstract_command(): command=0x2207b1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b1
Debug: 78633 153437 riscv-013.c:1415 register_read_direct(): {0} dpc = 0x4202a01a
Debug: 78634 153437 riscv-013.c:3424 riscv013_get_register(): [0] read PC from DPC: 0x4202a01a
Debug: 78635 153437 riscv.c:2795 riscv_get_register_on_hart(): {0} pc: 4202a01a
Debug: 78636 153437 riscv.c:3071 register_get(): [0]{0} read 0x4202a01a from pc (valid=1)
Debug: 78637 153437 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$0000000016803840e0e0c93f00fcc83f288fc73fa67f05400f000000000000000000000000000000010000000000000003000000000000000100000000200c60010000002cf8c93f00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001aa00242#5c'
Debug: 78638 153437 gdb_server.c:3358 gdb_input_inner(): received packet: 'vCont;s:3fc9ed78;c'
Debug: 78639 153437 FreeRTOS.c:405 FreeRTOS_find_target_from_threadid(): Find target for thr 0x3fc9ed78
Debug: 78640 153437 FreeRTOS.c:433 FreeRTOS_target_for_threadid(): target found : esp32c3
Debug: 78641 153437 gdb_server.c:2912 gdb_handle_vcont_packet(): target esp32c3 single-step thread 3fc9ed78
Debug: 78642 153437 target.c:1634 target_call_event_callbacks(): target event 5 (gdb-start) for core esp32c3
Debug: 78643 153437 riscv.c:965 old_or_new_riscv_step(): handle_breakpoints=0
Debug: 78644 153437 riscv.c:1845 riscv_openocd_step(): stepping rtos hart
Debug: 78645 153437 riscv.c:2624 riscv_step_rtos_hart(): stepping hart 0
Debug: 78664 153438 riscv.c:2699 riscv_invalidate_register_cache(): [0]
Debug: 78665 153438 program.c:33 riscv_program_write(): debug_buffer[00] = DASM(0x0000100f)
Debug: 78666 153438 riscv-013.c:3695 riscv013_write_debug_buffer(): cache hit for 0x100f @0
Debug: 78667 153438 program.c:33 riscv_program_write(): debug_buffer[01] = DASM(0x0000000f)
Debug: 78668 153438 riscv-013.c:3695 riscv013_write_debug_buffer(): cache hit for 0xf @1
Debug: 78669 153438 program.c:33 riscv_program_write(): debug_buffer[02] = DASM(0x00100073)
Debug: 78670 153438 riscv-013.c:3695 riscv013_write_debug_buffer(): cache hit for 0x100073 @2
Debug: 78671 153438 riscv-013.c:765 execute_abstract_command(): command=0x241000; access register, size=32, postexec=1, transfer=0, write=0, regno=0x1000
Debug: 78699 153439 program.c:33 riscv_program_write(): debug_buffer[00] = DASM(0x0000100f)
Debug: 78700 153439 riscv-013.c:3695 riscv013_write_debug_buffer(): cache hit for 0x100f @0
Debug: 78701 153439 program.c:33 riscv_program_write(): debug_buffer[01] = DASM(0x0000000f)
Debug: 78702 153439 riscv-013.c:3695 riscv013_write_debug_buffer(): cache hit for 0xf @1
Debug: 78703 153439 program.c:33 riscv_program_write(): debug_buffer[02] = DASM(0x00100073)
Debug: 78704 153439 riscv-013.c:3695 riscv013_write_debug_buffer(): cache hit for 0x100073 @2
Debug: 78705 153439 riscv-013.c:765 execute_abstract_command(): command=0x241000; access register, size=32, postexec=1, transfer=0, write=0, regno=0x1000
Debug: 78733 153439 riscv-013.c:765 execute_abstract_command(): command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0
Debug: 78779 153441 riscv-013.c:1415 register_read_direct(): {0} dcsr = 0x4000b107
Debug: 78780 153441 riscv.c:2756 riscv_set_register_on_hart(): {0} dcsr <- 4000b107
Debug: 78781 153441 riscv-013.c:3440 riscv013_set_register(): [0] writing 0x4000b107 to register dcsr on hart 0
Debug: 78782 153441 riscv-013.c:1227 register_write_direct(): {0} dcsr <- 0x4000b107
Debug: 78801 153442 riscv-013.c:765 execute_abstract_command(): command=0x2307b0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b0
Debug: 78829 153442 riscv-013.c:4130 riscv013_step_or_resume_current_hart(): resuming hart 0 (for step?=1)
Debug: 78902 153445 riscv.c:2699 riscv_invalidate_register_cache(): [0]
Debug: 78921 153446 target.c:1634 target_call_event_callbacks(): target event 2 (resumed) for core esp32c3
Debug: 78922 153446 target.c:1634 target_call_event_callbacks(): target event 0 (gdb-halt) for core esp32c3
Debug: 78923 153446 target.c:1634 target_call_event_callbacks(): target event 1 (halted) for core esp32c3
Debug: 78924 153446 target.c:4631 target_handle_event(): target(0): esp32c3 (riscv) event: 1 (halted) action:  esp32c3_wdt_disable 
Debug: 78925 153446 command.c:143 script_debug(): command - command command mode
Debug: 78926 153446 command.c:143 script_debug(): command - mww mww 0x6001f064 0x50D83AA1
Debug: 78946 153446 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$O#4f'
Debug: 78983 153448 riscv-013.c:3076 write_memory_bus_v1(): transferring burst starting at address 0x6001f064
Debug: 78984 153448 riscv-013.c:2072 log_memory_access(): M[0x6001f064] writes 0x50d83aa1
Debug: 78994 153448 batch.c:164 dump_field(): 41b 5i w 50d83aa1 @3c -> + 00000000 @39
Debug: 78995 153448 batch.c:164 dump_field(): 41b 5i - 00000000 @00 -> + 50d83aa1 @3c
Debug: 79005 153448 command.c:143 script_debug(): command - mww mww 0x6001F048 0
Debug: 79025 153449 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$O#4f'
Debug: 79062 153450 riscv-013.c:3076 write_memory_bus_v1(): transferring burst starting at address 0x6001f048
Debug: 79063 153450 riscv-013.c:2072 log_memory_access(): M[0x6001f048] writes 0x00000000
Debug: 79073 153451 batch.c:164 dump_field(): 41b 5i w 00000000 @3c -> + 00000000 @39
Debug: 79074 153451 batch.c:164 dump_field(): 41b 5i - 00000000 @00 -> + 00000000 @3c
Debug: 79084 153451 command.c:143 script_debug(): command - mww mww 0x60020064 0x50D83AA1
Debug: 79104 153452 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$O#4f'
Debug: 79141 153453 riscv-013.c:3076 write_memory_bus_v1(): transferring burst starting at address 0x60020064
Debug: 79142 153453 riscv-013.c:2072 log_memory_access(): M[0x60020064] writes 0x50d83aa1
Debug: 79152 153453 batch.c:164 dump_field(): 41b 5i w 50d83aa1 @3c -> + 00000000 @39
Debug: 79153 153453 batch.c:164 dump_field(): 41b 5i - 00000000 @00 -> + 50d83aa1 @3c
Debug: 79163 153453 command.c:143 script_debug(): command - mww mww 0x60020048 0
Debug: 79183 153454 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$O#4f'
Debug: 79220 153455 riscv-013.c:3076 write_memory_bus_v1(): transferring burst starting at address 0x60020048
Debug: 79221 153455 riscv-013.c:2072 log_memory_access(): M[0x60020048] writes 0x00000000
Debug: 79231 153456 batch.c:164 dump_field(): 41b 5i w 00000000 @3c -> + 00000000 @39
Debug: 79232 153456 batch.c:164 dump_field(): 41b 5i - 00000000 @00 -> + 00000000 @3c
Debug: 79242 153456 command.c:143 script_debug(): command - mww mww 0x600080a8 0x50D83AA1
Debug: 79262 153457 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$O#4f'
Debug: 79299 153458 riscv-013.c:3076 write_memory_bus_v1(): transferring burst starting at address 0x600080a8
Debug: 79300 153458 riscv-013.c:2072 log_memory_access(): M[0x600080a8] writes 0x50d83aa1
Debug: 79310 153458 batch.c:164 dump_field(): 41b 5i w 50d83aa1 @3c -> + 00000000 @39
Debug: 79311 153458 batch.c:164 dump_field(): 41b 5i - 00000000 @00 -> + 50d83aa1 @3c
Debug: 79321 153459 command.c:143 script_debug(): command - mww mww 0x60008090 0
Debug: 79341 153459 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$O#4f'
Debug: 79378 153461 riscv-013.c:3076 write_memory_bus_v1(): transferring burst starting at address 0x60008090
Debug: 79379 153461 riscv-013.c:2072 log_memory_access(): M[0x60008090] writes 0x00000000
Debug: 79389 153461 batch.c:164 dump_field(): 41b 5i w 00000000 @3c -> + 00000000 @39
Debug: 79390 153461 batch.c:164 dump_field(): 41b 5i - 00000000 @00 -> + 00000000 @3c
Debug: 79400 153461 target.c:1634 target_call_event_callbacks(): target event 6 (gdb-end) for core esp32c3
Debug: 79419 153462 FreeRTOS.c:694 FreeRTOS_update_threads(): FreeRTOS_update_threads
Debug: 79474 153464 riscv-013.c:2072 log_memory_access(): M[0x3fc97e8c] reads 0x00000004
Debug: 79493 153465 target.c:2447 target_read_u32(): address: 0x3fc97e8c, value: 0x00000004
Debug: 79494 153465 FreeRTOS.c:745 FreeRTOS_update_threads(): Read uxCurrentNumberOfTasks at 0x3fc97e8c, value 4
Debug: 79549 153467 riscv-013.c:2072 log_memory_access(): M[0x3fc97e98] reads 0x00000004
Debug: 79568 153467 target.c:2447 target_read_u32(): address: 0x3fc97e98, value: 0x00000004
Debug: 79569 153467 FreeRTOS.c:766 FreeRTOS_update_threads(): Read uxTaskNumber at 0x3fc97e98, value 4
Error: 79570 153467 FreeRTOS.c:771 FreeRTOS_update_threads(): FreeRTOS uxTaskNumber seems to be corrupted!
Debug: 79571 153467 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$O4672656552544f532075785461736b4e756d626572207365656d7320746f20626520636f72727570746564210a#38'
Debug: 79572 153467 FreeRTOS.c:405 FreeRTOS_find_target_from_threadid(): Find target for thr 0x3fc9ed78
Debug: 79573 153467 FreeRTOS.c:433 FreeRTOS_target_for_threadid(): target found : esp32c3
Debug: 79574 153467 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$T05thread:3fc9ed78;#13'
Debug: 79575 153467 gdb_server.c:3358 gdb_input_inner(): received packet: 'g'
Debug: 79576 153467 riscv.c:1357 riscv_get_gdb_reg_list_internal(): rtos_hartid=0, current_hartid=0, reg_class=1, read=1
Debug: 79577 153467 riscv-013.c:3416 riscv013_get_register(): [0] reading register zero on hart 0
Debug: 79578 153467 riscv.c:2795 riscv_get_register_on_hart(): {0} zero: 0
Debug: 79579 153467 riscv.c:3071 register_get(): [0]{0} read 0x0 from zero (valid=1)
Debug: 79580 153467 riscv-013.c:3416 riscv013_get_register(): [0] reading register ra on hart 0
Debug: 79581 153467 riscv-013.c:765 execute_abstract_command(): command=0x221001; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1001
Debug: 79627 153469 riscv-013.c:1415 register_read_direct(): {0} ra = 0x4202a01e
Debug: 79628 153469 riscv.c:2795 riscv_get_register_on_hart(): {0} ra: 4202a01e
Debug: 79629 153469 riscv.c:3071 register_get(): [0]{0} read 0x4202a01e from ra (valid=1)
Debug: 79630 153469 riscv-013.c:3416 riscv013_get_register(): [0] reading register sp on hart 0
Debug: 79631 153469 riscv-013.c:765 execute_abstract_command(): command=0x221002; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1002
Debug: 79677 153470 riscv-013.c:1415 register_read_direct(): {0} sp = 0x3fc9e0e0
Debug: 79678 153470 riscv.c:2795 riscv_get_register_on_hart(): {0} sp: 3fc9e0e0
Debug: 79679 153470 riscv.c:3071 register_get(): [0]{0} read 0x3fc9e0e0 from sp (valid=1)
Debug: 79680 153470 riscv-013.c:3416 riscv013_get_register(): [0] reading register gp on hart 0
Debug: 79681 153470 riscv-013.c:765 execute_abstract_command(): command=0x221003; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1003
Debug: 79727 153472 riscv-013.c:1415 register_read_direct(): {0} gp = 0x3fc8fc00
Debug: 79728 153472 riscv.c:2795 riscv_get_register_on_hart(): {0} gp: 3fc8fc00
Debug: 79729 153472 riscv.c:3071 register_get(): [0]{0} read 0x3fc8fc00 from gp (valid=1)
Debug: 79730 153472 riscv-013.c:3416 riscv013_get_register(): [0] reading register tp on hart 0
Debug: 79731 153472 riscv-013.c:765 execute_abstract_command(): command=0x221004; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1004
Debug: 79777 153473 riscv-013.c:1415 register_read_direct(): {0} tp = 0x3fc78f28
Debug: 79778 153473 riscv.c:2795 riscv_get_register_on_hart(): {0} tp: 3fc78f28
Debug: 79779 153473 riscv.c:3071 register_get(): [0]{0} read 0x3fc78f28 from tp (valid=1)
Debug: 79780 153473 riscv-013.c:3416 riscv013_get_register(): [0] reading register t0 on hart 0
Debug: 79781 153473 riscv-013.c:765 execute_abstract_command(): command=0x221005; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1005
Debug: 79827 153475 riscv-013.c:1415 register_read_direct(): {0} t0 = 0x40057fa6
Debug: 79828 153475 riscv.c:2795 riscv_get_register_on_hart(): {0} t0: 40057fa6
Debug: 79829 153475 riscv.c:3071 register_get(): [0]{0} read 0x40057fa6 from t0 (valid=1)
Debug: 79830 153475 riscv-013.c:3416 riscv013_get_register(): [0] reading register t1 on hart 0
Debug: 79831 153475 riscv-013.c:765 execute_abstract_command(): command=0x221006; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1006
Debug: 79877 153477 riscv-013.c:1415 register_read_direct(): {0} t1 = 0xf
Debug: 79878 153477 riscv.c:2795 riscv_get_register_on_hart(): {0} t1: f
Debug: 79879 153477 riscv.c:3071 register_get(): [0]{0} read 0xf from t1 (valid=1)
Debug: 79880 153477 riscv-013.c:3416 riscv013_get_register(): [0] reading register t2 on hart 0
Debug: 79881 153477 riscv-013.c:765 execute_abstract_command(): command=0x221007; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1007
Debug: 79927 153478 riscv-013.c:1415 register_read_direct(): {0} t2 = 0x0
Debug: 79928 153478 riscv.c:2795 riscv_get_register_on_hart(): {0} t2: 0
Debug: 79929 153478 riscv.c:3071 register_get(): [0]{0} read 0x0 from t2 (valid=1)
Debug: 79930 153478 riscv-013.c:3416 riscv013_get_register(): [0] reading register s0 on hart 0
Debug: 79931 153478 riscv-013.c:765 execute_abstract_command(): command=0x221008; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1008
Debug: 79977 153480 riscv-013.c:1415 register_read_direct(): {0} s0 = 0x0
Debug: 79978 153480 riscv.c:2795 riscv_get_register_on_hart(): {0} s0: 0
Debug: 79979 153480 riscv.c:3071 register_get(): [0]{0} read 0x0 from fp (valid=1)
Debug: 79980 153480 riscv-013.c:3416 riscv013_get_register(): [0] reading register s1 on hart 0
Debug: 79981 153480 riscv-013.c:765 execute_abstract_command(): command=0x221009; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1009
Debug: 80027 153481 riscv-013.c:1415 register_read_direct(): {0} s1 = 0x0
Debug: 80028 153481 riscv.c:2795 riscv_get_register_on_hart(): {0} s1: 0
Debug: 80029 153481 riscv.c:3071 register_get(): [0]{0} read 0x0 from s1 (valid=1)
Debug: 80030 153481 riscv-013.c:3416 riscv013_get_register(): [0] reading register a0 on hart 0
Debug: 80031 153481 riscv-013.c:765 execute_abstract_command(): command=0x22100a; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100a
Debug: 80077 153483 riscv-013.c:1415 register_read_direct(): {0} a0 = 0x1
Debug: 80078 153483 riscv.c:2795 riscv_get_register_on_hart(): {0} a0: 1
Debug: 80079 153483 riscv.c:3071 register_get(): [0]{0} read 0x1 from a0 (valid=1)
Debug: 80080 153483 riscv-013.c:3416 riscv013_get_register(): [0] reading register a1 on hart 0
Debug: 80081 153483 riscv-013.c:765 execute_abstract_command(): command=0x22100b; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100b
Debug: 80127 153484 riscv-013.c:1415 register_read_direct(): {0} a1 = 0x0
Debug: 80128 153484 riscv.c:2795 riscv_get_register_on_hart(): {0} a1: 0
Debug: 80129 153484 riscv.c:3071 register_get(): [0]{0} read 0x0 from a1 (valid=1)
Debug: 80130 153484 riscv-013.c:3416 riscv013_get_register(): [0] reading register a2 on hart 0
Debug: 80131 153484 riscv-013.c:765 execute_abstract_command(): command=0x22100c; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100c
Debug: 80177 153486 riscv-013.c:1415 register_read_direct(): {0} a2 = 0x3
Debug: 80178 153486 riscv.c:2795 riscv_get_register_on_hart(): {0} a2: 3
Debug: 80179 153486 riscv.c:3071 register_get(): [0]{0} read 0x3 from a2 (valid=1)
Debug: 80180 153486 riscv-013.c:3416 riscv013_get_register(): [0] reading register a3 on hart 0
Debug: 80181 153486 riscv-013.c:765 execute_abstract_command(): command=0x22100d; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100d
Debug: 80227 153487 riscv-013.c:1415 register_read_direct(): {0} a3 = 0x0
Debug: 80228 153487 riscv.c:2795 riscv_get_register_on_hart(): {0} a3: 0
Debug: 80229 153487 riscv.c:3071 register_get(): [0]{0} read 0x0 from a3 (valid=1)
Debug: 80230 153487 riscv-013.c:3416 riscv013_get_register(): [0] reading register a4 on hart 0
Debug: 80231 153487 riscv-013.c:765 execute_abstract_command(): command=0x22100e; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100e
Debug: 80277 153489 riscv-013.c:1415 register_read_direct(): {0} a4 = 0x1
Debug: 80278 153489 riscv.c:2795 riscv_get_register_on_hart(): {0} a4: 1
Debug: 80279 153489 riscv.c:3071 register_get(): [0]{0} read 0x1 from a4 (valid=1)
Debug: 80280 153489 riscv-013.c:3416 riscv013_get_register(): [0] reading register a5 on hart 0
Debug: 80281 153489 riscv-013.c:765 execute_abstract_command(): command=0x22100f; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100f
Debug: 80327 153491 riscv-013.c:1415 register_read_direct(): {0} a5 = 0x600c2000
Debug: 80328 153491 riscv.c:2795 riscv_get_register_on_hart(): {0} a5: 600c2000
Debug: 80329 153491 riscv.c:3071 register_get(): [0]{0} read 0x600c2000 from a5 (valid=1)
Debug: 80330 153491 riscv-013.c:3416 riscv013_get_register(): [0] reading register a6 on hart 0
Debug: 80331 153491 riscv-013.c:765 execute_abstract_command(): command=0x221010; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1010
Debug: 80377 153492 riscv-013.c:1415 register_read_direct(): {0} a6 = 0x1
Debug: 80378 153492 riscv.c:2795 riscv_get_register_on_hart(): {0} a6: 1
Debug: 80379 153492 riscv.c:3071 register_get(): [0]{0} read 0x1 from a6 (valid=1)
Debug: 80380 153492 riscv-013.c:3416 riscv013_get_register(): [0] reading register a7 on hart 0
Debug: 80381 153492 riscv-013.c:765 execute_abstract_command(): command=0x221011; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1011
Debug: 80427 153494 riscv-013.c:1415 register_read_direct(): {0} a7 = 0x3fc9f82c
Debug: 80428 153494 riscv.c:2795 riscv_get_register_on_hart(): {0} a7: 3fc9f82c
Debug: 80429 153494 riscv.c:3071 register_get(): [0]{0} read 0x3fc9f82c from a7 (valid=1)
Debug: 80430 153494 riscv-013.c:3416 riscv013_get_register(): [0] reading register s2 on hart 0
Debug: 80431 153494 riscv-013.c:765 execute_abstract_command(): command=0x221012; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1012
Debug: 80477 153496 riscv-013.c:1415 register_read_direct(): {0} s2 = 0x0
Debug: 80478 153496 riscv.c:2795 riscv_get_register_on_hart(): {0} s2: 0
Debug: 80479 153496 riscv.c:3071 register_get(): [0]{0} read 0x0 from s2 (valid=1)
Debug: 80480 153496 riscv-013.c:3416 riscv013_get_register(): [0] reading register s3 on hart 0
Debug: 80481 153496 riscv-013.c:765 execute_abstract_command(): command=0x221013; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1013
Debug: 80527 153497 riscv-013.c:1415 register_read_direct(): {0} s3 = 0x0
Debug: 80528 153497 riscv.c:2795 riscv_get_register_on_hart(): {0} s3: 0
Debug: 80529 153497 riscv.c:3071 register_get(): [0]{0} read 0x0 from s3 (valid=1)
Debug: 80530 153497 riscv-013.c:3416 riscv013_get_register(): [0] reading register s4 on hart 0
Debug: 80531 153497 riscv-013.c:765 execute_abstract_command(): command=0x221014; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1014
Debug: 80577 153499 riscv-013.c:1415 register_read_direct(): {0} s4 = 0x0
Debug: 80578 153499 riscv.c:2795 riscv_get_register_on_hart(): {0} s4: 0
Debug: 80579 153499 riscv.c:3071 register_get(): [0]{0} read 0x0 from s4 (valid=1)
Debug: 80580 153499 riscv-013.c:3416 riscv013_get_register(): [0] reading register s5 on hart 0
Debug: 80581 153499 riscv-013.c:765 execute_abstract_command(): command=0x221015; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1015
Debug: 80627 153500 riscv-013.c:1415 register_read_direct(): {0} s5 = 0x0
Debug: 80628 153500 riscv.c:2795 riscv_get_register_on_hart(): {0} s5: 0
Debug: 80629 153500 riscv.c:3071 register_get(): [0]{0} read 0x0 from s5 (valid=1)
Debug: 80630 153500 riscv-013.c:3416 riscv013_get_register(): [0] reading register s6 on hart 0
Debug: 80631 153500 riscv-013.c:765 execute_abstract_command(): command=0x221016; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1016
Debug: 80677 153502 riscv-013.c:1415 register_read_direct(): {0} s6 = 0x0
Debug: 80678 153502 riscv.c:2795 riscv_get_register_on_hart(): {0} s6: 0
Debug: 80679 153502 riscv.c:3071 register_get(): [0]{0} read 0x0 from s6 (valid=1)
Debug: 80680 153502 riscv-013.c:3416 riscv013_get_register(): [0] reading register s7 on hart 0
Debug: 80681 153502 riscv-013.c:765 execute_abstract_command(): command=0x221017; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1017
Debug: 80727 153504 riscv-013.c:1415 register_read_direct(): {0} s7 = 0x0
Debug: 80728 153504 riscv.c:2795 riscv_get_register_on_hart(): {0} s7: 0
Debug: 80729 153504 riscv.c:3071 register_get(): [0]{0} read 0x0 from s7 (valid=1)
Debug: 80730 153504 riscv-013.c:3416 riscv013_get_register(): [0] reading register s8 on hart 0
Debug: 80731 153504 riscv-013.c:765 execute_abstract_command(): command=0x221018; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1018
Debug: 80777 153505 riscv-013.c:1415 register_read_direct(): {0} s8 = 0x0
Debug: 80778 153505 riscv.c:2795 riscv_get_register_on_hart(): {0} s8: 0
Debug: 80779 153505 riscv.c:3071 register_get(): [0]{0} read 0x0 from s8 (valid=1)
Debug: 80780 153505 riscv-013.c:3416 riscv013_get_register(): [0] reading register s9 on hart 0
Debug: 80781 153505 riscv-013.c:765 execute_abstract_command(): command=0x221019; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1019
Debug: 80827 153507 riscv-013.c:1415 register_read_direct(): {0} s9 = 0x0
Debug: 80828 153507 riscv.c:2795 riscv_get_register_on_hart(): {0} s9: 0
Debug: 80829 153507 riscv.c:3071 register_get(): [0]{0} read 0x0 from s9 (valid=1)
Debug: 80830 153507 riscv-013.c:3416 riscv013_get_register(): [0] reading register s10 on hart 0
Debug: 80831 153507 riscv-013.c:765 execute_abstract_command(): command=0x22101a; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101a
Debug: 80877 153508 riscv-013.c:1415 register_read_direct(): {0} s10 = 0x0
Debug: 80878 153508 riscv.c:2795 riscv_get_register_on_hart(): {0} s10: 0
Debug: 80879 153508 riscv.c:3071 register_get(): [0]{0} read 0x0 from s10 (valid=1)
Debug: 80880 153508 riscv-013.c:3416 riscv013_get_register(): [0] reading register s11 on hart 0
Debug: 80881 153508 riscv-013.c:765 execute_abstract_command(): command=0x22101b; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101b
Debug: 80927 153510 riscv-013.c:1415 register_read_direct(): {0} s11 = 0x0
Debug: 80928 153510 riscv.c:2795 riscv_get_register_on_hart(): {0} s11: 0
Debug: 80929 153510 riscv.c:3071 register_get(): [0]{0} read 0x0 from s11 (valid=1)
Debug: 80930 153510 riscv-013.c:3416 riscv013_get_register(): [0] reading register t3 on hart 0
Debug: 80931 153510 riscv-013.c:765 execute_abstract_command(): command=0x22101c; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101c
Debug: 80977 153511 riscv-013.c:1415 register_read_direct(): {0} t3 = 0x0
Debug: 80978 153511 riscv.c:2795 riscv_get_register_on_hart(): {0} t3: 0
Debug: 80979 153511 riscv.c:3071 register_get(): [0]{0} read 0x0 from t3 (valid=1)
Debug: 80980 153511 riscv-013.c:3416 riscv013_get_register(): [0] reading register t4 on hart 0
Debug: 80981 153511 riscv-013.c:765 execute_abstract_command(): command=0x22101d; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101d
Debug: 81027 153513 riscv-013.c:1415 register_read_direct(): {0} t4 = 0x0
Debug: 81028 153513 riscv.c:2795 riscv_get_register_on_hart(): {0} t4: 0
Debug: 81029 153513 riscv.c:3071 register_get(): [0]{0} read 0x0 from t4 (valid=1)
Debug: 81030 153513 riscv-013.c:3416 riscv013_get_register(): [0] reading register t5 on hart 0
Debug: 81031 153513 riscv-013.c:765 execute_abstract_command(): command=0x22101e; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101e
Debug: 81077 153514 riscv-013.c:1415 register_read_direct(): {0} t5 = 0x0
Debug: 81078 153514 riscv.c:2795 riscv_get_register_on_hart(): {0} t5: 0
Debug: 81079 153514 riscv.c:3071 register_get(): [0]{0} read 0x0 from t5 (valid=1)
Debug: 81080 153514 riscv-013.c:3416 riscv013_get_register(): [0] reading register t6 on hart 0
Debug: 81081 153514 riscv-013.c:765 execute_abstract_command(): command=0x22101f; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101f
Debug: 81127 153516 riscv-013.c:1415 register_read_direct(): {0} t6 = 0x0
Debug: 81128 153516 riscv.c:2795 riscv_get_register_on_hart(): {0} t6: 0
Debug: 81129 153516 riscv.c:3071 register_get(): [0]{0} read 0x0 from t6 (valid=1)
Debug: 81130 153516 riscv-013.c:3416 riscv013_get_register(): [0] reading register pc on hart 0
Debug: 81131 153516 riscv-013.c:765 execute_abstract_command(): command=0x2207b1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b1
Debug: 81177 153518 riscv-013.c:1415 register_read_direct(): {0} dpc = 0x403881ec
Debug: 81178 153518 riscv-013.c:3424 riscv013_get_register(): [0] read PC from DPC: 0x403881ec
Debug: 81179 153518 riscv.c:2795 riscv_get_register_on_hart(): {0} pc: 403881ec
Debug: 81180 153518 riscv.c:3071 register_get(): [0]{0} read 0x403881ec from pc (valid=1)
Debug: 81181 153518 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$000000001ea00242e0e0c93f00fcc83f288fc73fa67f05400f000000000000000000000000000000010000000000000003000000000000000100000000200c60010000002cf8c93f0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ec813840#c2'
Debug: 81182 153519 gdb_server.c:3358 gdb_input_inner(): received packet: 'z0,420cea64,4'
Debug: 81183 153519 gdb_server.c:1650 gdb_breakpoint_watchpoint_packet(): [esp32c3]
Debug: 81184 153519 riscv.c:777 remove_trigger(): [0] Stop using resource 0 for bp 2
Debug: 81185 153519 riscv-013.c:3416 riscv013_get_register(): [0] reading register tselect on hart 0
Debug: 81186 153519 riscv-013.c:765 execute_abstract_command(): command=0x2207a0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a0
Debug: 81232 153520 riscv-013.c:1415 register_read_direct(): {0} tselect = 0x0
Debug: 81233 153520 riscv.c:2795 riscv_get_register_on_hart(): {0} tselect: 0
Debug: 81234 153520 riscv.c:2756 riscv_set_register_on_hart(): {0} tselect <- 0
Debug: 81235 153520 riscv-013.c:3440 riscv013_set_register(): [0] writing 0x0 to register tselect on hart 0
Debug: 81236 153520 riscv-013.c:1227 register_write_direct(): {0} tselect <- 0x0
Debug: 81255 153521 riscv-013.c:765 execute_abstract_command(): command=0x2307a0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a0
Debug: 81283 153522 riscv.c:2756 riscv_set_register_on_hart(): {0} tdata1 <- 0
Debug: 81284 153522 riscv-013.c:3440 riscv013_set_register(): [0] writing 0x0 to register tdata1 on hart 0
Debug: 81285 153522 riscv-013.c:1227 register_write_direct(): {0} tdata1 <- 0x0
Debug: 81304 153522 riscv-013.c:765 execute_abstract_command(): command=0x2307a1; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a1
Debug: 81332 153523 riscv.c:2756 riscv_set_register_on_hart(): {0} tselect <- 0
Debug: 81333 153523 riscv-013.c:3440 riscv013_set_register(): [0] writing 0x0 to register tselect on hart 0
Debug: 81334 153523 riscv-013.c:1227 register_write_direct(): {0} tselect <- 0x0
Debug: 81353 153524 riscv-013.c:765 execute_abstract_command(): command=0x2307a0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a0
Debug: 81381 153525 breakpoints.c:311 breakpoint_free(): free BPID: 2 --> 0
Debug: 81382 153525 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$OK#9a'
Debug: 81383 153525 gdb_server.c:3358 gdb_input_inner(): received packet: 'qXfer:threads:read::0,1000'
Debug: 81384 153525 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$l<?xml version="1.0"?>
<threads>
<thread id="3fc9ed78">Name: IDLE</thread>
<thread id="3fca5f08">Name: tiT</thread>
<thread id="3fc9e31c">Name: main</thread>
<thread id="3fca490c">Name: uart_event_task</thread>
<thread id="3fca34dc">Name: sys_evt</thread>
<thread id="3fc9f6d4">Name: Tmr Svc</thread>
<thread id="3fc99f80">Name: esp_timer</thread>
</threads>
#1e'