From eadfc387c4491b3d93c747a40f0998877586b6fb Mon Sep 17 00:00:00 2001 From: Erhan Kurubas Date: Tue, 21 Feb 2023 00:24:10 +0100 Subject: [PATCH] esp/testing: enable remaining tests --- .gitlab/ci/build-test-app.yml | 2 +- .gitlab/ci/test.yml | 2 +- .gitlab/ci/util.yml | 1 + tcl/target/esp32c6.cfg | 2 +- tcl/target/esp32h2.cfg | 2 +- tcl/target/esp_common.cfg | 6 +++--- testing/esp/debug_backend_tests.py | 2 +- testing/esp/test_special.py | 6 +++--- 8 files changed, 12 insertions(+), 11 deletions(-) diff --git a/.gitlab/ci/build-test-app.yml b/.gitlab/ci/build-test-app.yml index 7d2dfa741e..cd92ce6b98 100644 --- a/.gitlab/ci/build-test-app.yml +++ b/.gitlab/ci/build-test-app.yml @@ -176,7 +176,7 @@ build_test_app_esp32c6: CHIP_NAME: "esp32c6" TOOLCHAIN_PREFIX: "riscv32-esp" BUILD_TEST_APP_DIR: "build_test_app_esp32c6" - TEST_APP_CONFIGS: "single_core apptrace_gcov_single" + TEST_APP_CONFIGS: "single_core svtrace_single apptrace_gcov_single" extends: .build_idf5x_test_app_template build_test_app_esp32_idf4.x: diff --git a/.gitlab/ci/test.yml b/.gitlab/ci/test.yml index 65ad51a984..b8c56585c8 100644 --- a/.gitlab/ci/test.yml +++ b/.gitlab/ci/test.yml @@ -310,7 +310,7 @@ tests_armhf_esp32c6_builtin_usb_jtag: TOOLCHAIN_PREFIX: "riscv32-esp" ESP_TOOLCHAIN: "${ESP_MASTER_RISCV_TOOLCHAIN_VER}" TEST_RUN_DIR: "build_test_app_esp32c6" - TEST_RUN_EXTRA_OPTS: "-i latest -b esp32c6-builtin -p test_apptrace*.*Single test_bp*.*Single test_step*.*Single test_thread*.*Single test_flasher*.*Single" + TEST_RUN_EXTRA_OPTS: "-i latest -b esp32c6-builtin -p test_*.*Single -u /dev/ttyACM0" tests_win_simple_esp32: stage: test_windows diff --git a/.gitlab/ci/util.yml b/.gitlab/ci/util.yml index 2cbf2b0e7c..cc22fd6c09 100644 --- a/.gitlab/ci/util.yml +++ b/.gitlab/ci/util.yml @@ -27,6 +27,7 @@ .export_toolchain_snippet: &export_toolchain_snippet | export PATH=${HOME}/.espressif/tools/${TOOLCHAIN_PREFIX}-elf/${ESP_TOOLCHAIN}/${TOOLCHAIN_PREFIX}-elf/bin:${PATH} source /opt/pyenv/activate && pyenv global ${TEST_IMAGE_PYTHON_VER} + pip install esptool==4.5 if [ "${GDB_ARMHF_DISTRO_URL:-test}" != "test" ]; then case $CI_JOB_NAME in "tests_armhf_"*) echo "Replacing GDBs from $GDB_ARMHF_DISTRO_URL" diff --git a/tcl/target/esp32c6.cfg b/tcl/target/esp32c6.cfg index b065ae7b5c..d7fda6f904 100644 --- a/tcl/target/esp32c6.cfg +++ b/tcl/target/esp32c6.cfg @@ -11,7 +11,7 @@ source [find mmr_helpers.tcl] source [find target/esp_common.cfg] # Target specific registers -set EFUSE_MAC_ADDR_REG 0x60008844 +set EFUSE_MAC_ADDR_REG 0x600B0844 if { [info exists CHIPNAME] } { set _CHIPNAME $CHIPNAME diff --git a/tcl/target/esp32h2.cfg b/tcl/target/esp32h2.cfg index c93e4e5b03..876c707317 100644 --- a/tcl/target/esp32h2.cfg +++ b/tcl/target/esp32h2.cfg @@ -11,7 +11,7 @@ source [find mmr_helpers.tcl] source [find target/esp_common.cfg] # Target specific registers -set EFUSE_MAC_ADDR_REG 0x60008844 +set EFUSE_MAC_ADDR_REG 0x600B0844 if { [info exists CHIPNAME] } { set _CHIPNAME $CHIPNAME diff --git a/tcl/target/esp_common.cfg b/tcl/target/esp_common.cfg index dbd66f010c..90bff943a0 100644 --- a/tcl/target/esp_common.cfg +++ b/tcl/target/esp_common.cfg @@ -309,12 +309,12 @@ proc esp_get_mac {args} { } } - if { [string equal [target current] esp32c3] || [string equal [target current] esp32c2] } { - set mac_list [read_memory $EFUSE_MAC_ADDR_REG 8 6] - } else { + if { [string equal [target current] esp32] || [string equal [target current] esp32s2] || [string equal [target current] esp32s3] } { xtensa set_permissive 1 set mac_list [read_memory $EFUSE_MAC_ADDR_REG 8 6] xtensa set_permissive 0 + } else { + set mac_list [read_memory $EFUSE_MAC_ADDR_REG 8 6] } set i 0 diff --git a/testing/esp/debug_backend_tests.py b/testing/esp/debug_backend_tests.py index cdc8d85547..6231e4992c 100644 --- a/testing/esp/debug_backend_tests.py +++ b/testing/esp/debug_backend_tests.py @@ -436,7 +436,7 @@ def stop_exec(self): if state != dbg.TARGET_STATE_STOPPED: self.gdb.exec_interrupt() rsn = self.gdb.wait_target_state(dbg.TARGET_STATE_STOPPED, 10) - self.assertEqual(rsn, dbg.TARGET_STOP_REASON_SIGINT) + self.assertTrue(rsn == dbg.TARGET_STOP_REASON_SIGINT or rsn == dbg.TARGET_STOP_REASON_SIGTRAP) def resume_exec(self, loc=None): """ Resumes target execution and ensures that it is in RUNNING state diff --git a/testing/esp/test_special.py b/testing/esp/test_special.py index a79e54b293..48abd67fd8 100644 --- a/testing/esp/test_special.py +++ b/testing/esp/test_special.py @@ -86,7 +86,7 @@ def _do_test_bp_and_wp_set_by_program(self): # watchpoint hit on read var in 'target_bp_func2' self.run_to_bp_and_check_location(dbg.TARGET_STOP_REASON_SIGTRAP, 'target_bp_func2', 'target_wp_var2_2') - @skip_for_chip(['esp32c2']) + @skip_for_chip(['esp32c2', 'esp32c6', 'esp32h2']) def test_bp_and_wp_set_by_program(self): """ This test checks that breakpoints and watchpoints set by program on target work. @@ -97,7 +97,7 @@ def test_bp_and_wp_set_by_program(self): self._do_test_bp_and_wp_set_by_program() @only_for_arch(['riscv32']) - @skip_for_chip(['esp32c2']) + @skip_for_chip(['esp32c2', 'esp32c6', 'esp32h2']) def test_wp_reconfigure_by_program(self): """ This test checks that watchpoints can be reconfigured by target w/o removing them. @@ -259,7 +259,7 @@ def test_gdb_regs_mapping(self): """ # should fail for any new chip. # just to be sure that this test is revised when new chip support is added - self.fail_if_not_hw_id([r'esp32-[.]*', r'esp32s2-[.]*', r'esp32c2-[.]*', r'esp32c3-[.]*', r'esp32s3-[.]*']) + self.fail_if_not_hw_id([r'esp32-[.]*', r'esp32s2-[.]*', r'esp32c2-[.]*', r'esp32c3-[.]*', r'esp32s3-[.]*', r'esp32c6-[.]*']) regs = self.gdb.get_reg_names() i = 10