esp32c3.cfg

# The ESP32-C3 only supports JTAG.
transport select jtag

# TODO: remove when flash support is ready
set ESP_FLASH_SIZE "0"

# Source the ESP common configuration file
source [find target/esp_common.cfg]

if { [info exists CHIPNAME] } {
	set _CHIPNAME $CHIPNAME
} else {
	set _CHIPNAME esp32c3
}

if { [info exists CPUTAPID] } {
	set _CPUTAPID $CPUTAPID
} else {
	set _CPUTAPID 0x00005c25
}

set _TARGETNAME $_CHIPNAME
set _CPUNAME cpu
set _TAPNAME $_CHIPNAME.$_CPUNAME

jtag newtap $_CHIPNAME $_CPUNAME -irlen 5 -expected-id $_CPUTAPID

proc esp32c3_wdt_disable { } {
    # Halt event can occur during config phase (before "init" is done).
    # Ignore it since mww commands don't work at that time.
    if { [string compare [command mode] config] == 0 } {
        return
    }

    # Timer Group 0 & 1 WDTs
    mww 0x6001f064 0x50D83AA1
    mww 0x6001F048 0
    mww 0x60020064 0x50D83AA1
    mww 0x60020048 0
    # RTC WDT
    mww 0x600080a8 0x50D83AA1
    mww 0x60008090 0
}

proc esp32c3_soc_reset { } {
    # This procedure does "digital system reset", i.e. resets
    # all the peripherals except for the RTC block.
    # It is called from reset-assert-post target event callback,
    # after assert_reset procedure was called.
    # Since we need the hart to to execute a write to RTC_CNTL_SW_SYS_RST,
    # temporarily take it out of reset. Save the dmcontrol state before
    # doing so.
    riscv dmi_write 0x10 0x80000001
    # If SBA is used to trigger the reset, the debug module gets stuck
    # in a busy state waiting for the bus write to complete (HW quirk?),
    # so trigger the reset by CPU instead.
    riscv set_prefer_sba off
    mww 0x60008000 0x9c00a000
    # Wait for the reset to happen
    sleep 10
    poll
    # Restore SBA setting
    riscv set_prefer_sba on
    # Disable the watchdogs again
    esp32c3_wdt_disable
    # Put the hart back into reset state. Note that we need to keep haltreq set.
    riscv dmi_write 0x10 0x80000003
}


if { $_RTOS == "none" } {
    target create $_TARGETNAME riscv -chain-position $_TAPNAME
} else {
    target create $_TARGETNAME riscv -chain-position $_TAPNAME -rtos $_RTOS
}

$_TARGETNAME configure -event reset-assert-post { esp32c3_soc_reset }
$_TARGETNAME configure -event halted { esp32c3_wdt_disable }

configure_esp_workarea $_TARGETNAME 0x4037C000 0x4000 0x3FC80000 0x6000

# TODO: Add support
# configure_esp_flash_bank $_TARGETNAME $_TARGETNAME $_FLASH_SIZE

if { $_FLASH_SIZE == 0 } {
	gdb_breakpoint_override hard
}

riscv set_reset_timeout_sec 2
riscv set_command_timeout_sec 5
riscv set_prefer_sba on