ESP-IDF 4.X on arduino platform breaks ETH PHY support (IDFGH-5356)

[rtu-dataframe]

Hi guys, as i've reported in the esp32-arduino repo, starting from the IDF 4.x version, there are in place a lot of changes that breaks Ethernet on most of third party boards (Like Olimex, etc...).

For example, the driver initialization doesn't have the CLK GPIO option selectable and nowhere is documented that.

This represent for the overall esp32-arduino users a big problem to face...: here there are all details, scope traces and informations: ISSUE HERE

[negativekelvin]

It's a compile time option so when libraries are precompiled for Arduino the choice is locked. I think it could be made configurable at runtime, there's not really any penalty. This could also benefit micropython and other platforms that need to support multiple hardware configurations. What do you think @suda-morris ?

esp-idf/components/hal/esp32/emac_hal.c

Lines 84 to 130 in 1f54d17

	#if CONFIG_ETH_RMII_CLK_INPUT
	#if CONFIG_ETH_RMII_CLK_IN_GPIO == 0
	/* RMII clock (50MHz) input to GPIO0 */
	gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO0_U, FUNC_GPIO0_EMAC_TX_CLK);
	PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[0]);
	#else
	#error "ESP32 EMAC only support input RMII clock to GPIO0"
	#endif
	#endif
	#if CONFIG_ETH_RMII_CLK_OUTPUT
	#if CONFIG_ETH_RMII_CLK_OUTPUT_GPIO0
	/* APLL clock output to GPIO0 (must be configured to 50MHz!) */
	gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO0_U, FUNC_GPIO0_CLK_OUT1);
	PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[0]);
	#elif CONFIG_ETH_RMII_CLK_OUT_GPIO == 16
	/* RMII CLK (50MHz) output to GPIO16 */
	gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO16_U, FUNC_GPIO16_EMAC_CLK_OUT);
	PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[16]);
	#elif CONFIG_ETH_RMII_CLK_OUT_GPIO == 17
	/* RMII CLK (50MHz) output to GPIO17 */
	gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO17_U, FUNC_GPIO17_EMAC_CLK_OUT_180);
	PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[17]);
	#endif
	#endif // CONFIG_ETH_RMII_CLK_OUTPUT
	/* Clock configuration */
	#if CONFIG_ETH_PHY_INTERFACE_MII
	hal->ext_regs->ex_phyinf_conf.phy_intf_sel = 0;
	hal->ext_regs->ex_clk_ctrl.mii_clk_rx_en = 1;
	hal->ext_regs->ex_clk_ctrl.mii_clk_tx_en = 1;
	#elif CONFIG_ETH_PHY_INTERFACE_RMII
	hal->ext_regs->ex_phyinf_conf.phy_intf_sel = 4;
	#if CONFIG_ETH_RMII_CLK_INPUT
	hal->ext_regs->ex_clk_ctrl.ext_en = 1;
	hal->ext_regs->ex_clk_ctrl.int_en = 0;
	hal->ext_regs->ex_oscclk_conf.clk_sel = 1;
	#elif CONFIG_ETH_RMII_CLK_OUTPUT
	hal->ext_regs->ex_clk_ctrl.ext_en = 0;
	hal->ext_regs->ex_clk_ctrl.int_en = 1;
	hal->ext_regs->ex_oscclk_conf.clk_sel = 0;
	emac_config_apll_clock();
	hal->ext_regs->ex_clkout_conf.div_num = 0;
	hal->ext_regs->ex_clkout_conf.h_div_num = 0;
	#if CONFIG_ETH_RMII_CLK_OUTPUT_GPIO0
	/* Choose the APLL clock to output on GPIO */
	REG_WRITE(PIN_CTRL, 6);
	#endif // CONFIG_RMII_CLK_OUTPUT_GPIO0
	#endif // CONFIG_ETH_RMII_CLK_INPUT

[atanisoft]

@negativekelvin in IDF v3.x it was runtime configurable.

[suda-morris]

Thanks for reporting, IDF will add that runtime "mac clock config" option back soon.

[rtu-dataframe]

Thanks @suda-morris, we are waiting for that! :)

[rtu-dataframe]

@suda-morris, any news about this issue?

[kostaond]

@Simonefardella It's going to be worked very soon. There is EMAC HAL code refactor update pending to be merged which needs to be finished first. It's been already review so we could start "mac clock config" soon. Thank you for your patience.

[kostaond]

@Simonefardella just FYI, the update is in review.