From 466d42359c7237c895f45d54e531ad3717e89b3f Mon Sep 17 00:00:00 2001 From: cjin Date: Fri, 2 Aug 2024 12:05:10 +0800 Subject: [PATCH 1/2] fix(ble): remove ble wakeup before entering light sleep --- components/bt/controller/esp32h2/bt.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/components/bt/controller/esp32h2/bt.c b/components/bt/controller/esp32h2/bt.c index 0a06ad654c9..7c41dc246c0 100644 --- a/components/bt/controller/esp32h2/bt.c +++ b/components/bt/controller/esp32h2/bt.c @@ -129,6 +129,9 @@ extern void os_msys_deinit(void); extern sleep_retention_entries_config_t *r_esp_ble_mac_retention_link_get(uint8_t *size, uint8_t extra); extern void r_esp_ble_set_wakeup_overhead(uint32_t overhead); #endif /* CONFIG_FREERTOS_USE_TICKLESS_IDLE */ +#if CONFIG_PM_ENABLE +extern void esp_ble_stop_wakeup_timing(void); +#endif // CONFIG_PM_ENABLE extern void r_esp_ble_change_rtc_freq(uint32_t freq); extern int ble_sm_alg_gen_dhkey(const uint8_t *peer_pub_key_x, const uint8_t *peer_pub_key_y, @@ -613,6 +616,9 @@ esp_err_t controller_sleep_init(void) if (rc != ESP_OK) { goto error; } + + rc = esp_deep_sleep_register_hook(&esp_ble_stop_wakeup_timing); + assert(rc == 0); #if CONFIG_FREERTOS_USE_TICKLESS_IDLE /* Create a new regdma link for BLE related register restoration */ rc = sleep_modem_ble_mac_modem_state_init(0); @@ -633,6 +639,7 @@ esp_err_t controller_sleep_init(void) esp_sleep_disable_bt_wakeup(); esp_pm_unregister_inform_out_light_sleep_overhead_callback(sleep_modem_light_sleep_overhead_set); #endif /* CONFIG_FREERTOS_USE_TICKLESS_IDLE */ + esp_deep_sleep_deregister_hook(&esp_ble_stop_wakeup_timing); /*lock should release first and then delete*/ if (s_pm_lock != NULL) { esp_pm_lock_delete(s_pm_lock); @@ -652,6 +659,7 @@ void controller_sleep_deinit(void) esp_pm_unregister_inform_out_light_sleep_overhead_callback(sleep_modem_light_sleep_overhead_set); #endif /* CONFIG_FREERTOS_USE_TICKLESS_IDLE */ #ifdef CONFIG_PM_ENABLE + esp_deep_sleep_deregister_hook(&esp_ble_stop_wakeup_timing); /* lock should be released first */ esp_pm_lock_delete(s_pm_lock); s_pm_lock = NULL; From 41502dbf64c61aacbf236b5794ef6bd9e40ed9db Mon Sep 17 00:00:00 2001 From: cjin Date: Mon, 19 Aug 2024 19:33:37 +0800 Subject: [PATCH 2/2] feat(ble): add internal api to change ble slow clock source --- components/bt/controller/esp32c2/bt.c | 66 +++++++------ components/bt/controller/esp32c6/bt.c | 85 +++++++++++------ components/bt/controller/esp32h2/bt.c | 93 ++++++++++++------- .../bt/include/esp32c2/include/esp_bt.h | 7 ++ .../bt/include/esp32c6/include/esp_bt.h | 7 ++ .../bt/include/esp32h2/include/esp_bt.h | 7 ++ 6 files changed, 175 insertions(+), 90 deletions(-) diff --git a/components/bt/controller/esp32c2/bt.c b/components/bt/controller/esp32c2/bt.c index 3c5bf0b1b28..d421df3bdac 100644 --- a/components/bt/controller/esp32c2/bt.c +++ b/components/bt/controller/esp32c2/bt.c @@ -47,6 +47,7 @@ #if CONFIG_FREERTOS_USE_TICKLESS_IDLE #include "esp_private/sleep_modem.h" #endif // CONFIG_FREERTOS_USE_TICKLESS_IDLE +#include "esp_private/esp_modem_clock.h" #include "freertos/FreeRTOS.h" #include "freertos/task.h" @@ -73,11 +74,6 @@ #define EXT_FUNC_MAGIC_VALUE 0xA5A5A5A5 #define BT_ASSERT_PRINT ets_printf -typedef enum ble_rtc_slow_clk_src { - BT_SLOW_CLK_SRC_MAIN_XTAL, - BT_SLOW_CLK_SRC_32K_XTAL_ON_PIN0, -} ble_rtc_slow_clk_src_t; - /* Types definition ************************************************************************ */ @@ -440,6 +436,7 @@ static bool s_ble_active = false; static DRAM_ATTR esp_pm_lock_handle_t s_pm_lock = NULL; #define BTDM_MIN_TIMER_UNCERTAINTY_US (200) #endif // CONFIG_PM_ENABLE +static DRAM_ATTR modem_clock_lpclk_src_t s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_INVALID; #define BLE_RTC_DELAY_US (1800) @@ -554,6 +551,20 @@ void sleep_modem_light_sleep_overhead_set(uint32_t overhead) } #endif /* CONFIG_FREERTOS_USE_TICKLESS_IDLE */ +modem_clock_lpclk_src_t esp_bt_get_lpclk_src(void) +{ + return s_bt_lpclk_src; +} + +void esp_bt_set_lpclk_src(modem_clock_lpclk_src_t clk_src) +{ + if (clk_src >= MODEM_CLOCK_LPCLK_SRC_MAX) { + return; + } + + s_bt_lpclk_src = clk_src; +} + IRAM_ATTR void controller_sleep_cb(uint32_t enable_tick, void *arg) { if (!s_ble_active) { @@ -580,7 +591,7 @@ IRAM_ATTR void controller_wakeup_cb(void *arg) s_ble_active = true; } -esp_err_t controller_sleep_init(ble_rtc_slow_clk_src_t slow_clk_src) +esp_err_t controller_sleep_init(modem_clock_lpclk_src_t slow_clk_src) { esp_err_t rc = 0; #ifdef CONFIG_BT_LE_SLEEP_ENABLE @@ -588,7 +599,7 @@ esp_err_t controller_sleep_init(ble_rtc_slow_clk_src_t slow_clk_src) r_ble_lll_rfmgmt_set_sleep_cb(controller_sleep_cb, controller_wakeup_cb, 0, 0, 500 + BLE_RTC_DELAY_US); #ifdef CONFIG_PM_ENABLE - if (slow_clk_src == BT_SLOW_CLK_SRC_MAIN_XTAL) { + if (slow_clk_src == MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL) { esp_sleep_pd_config(ESP_PD_DOMAIN_XTAL, ESP_PD_OPTION_ON); } else { esp_sleep_pd_config(ESP_PD_DOMAIN_XTAL, ESP_PD_OPTION_AUTO); @@ -643,11 +654,11 @@ void controller_sleep_deinit(void) #endif //CONFIG_PM_ENABLE } -static void esp_bt_rtc_slow_clk_select(ble_rtc_slow_clk_src_t slow_clk_src) +static void esp_bt_rtc_slow_clk_select(modem_clock_lpclk_src_t slow_clk_src) { /* Select slow clock source for BT momdule */ switch (slow_clk_src) { - case BT_SLOW_CLK_SRC_MAIN_XTAL: + case MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL: ESP_LOGI(NIMBLE_PORT_LOG_TAG, "Using main XTAL as clock source"); SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, 1, 0, MODEM_CLKRST_LP_TIMER_SEL_XTAL32K_S); SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, 1, 1, MODEM_CLKRST_LP_TIMER_SEL_XTAL_S); @@ -659,7 +670,7 @@ static void esp_bt_rtc_slow_clk_select(ble_rtc_slow_clk_src_t slow_clk_src) SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM, 249, MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM_S); #endif // CONFIG_XTAL_FREQ_26 break; - case BT_SLOW_CLK_SRC_32K_XTAL_ON_PIN0: + case MODEM_CLOCK_LPCLK_SRC_EXT32K: ESP_LOGI(NIMBLE_PORT_LOG_TAG, "Using external 32.768 kHz XTAL as clock source"); SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, 1, 1, MODEM_CLKRST_LP_TIMER_SEL_XTAL32K_S); SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, 1, 0, MODEM_CLKRST_LP_TIMER_SEL_XTAL_S); @@ -676,40 +687,39 @@ static void esp_bt_rtc_slow_clk_select(ble_rtc_slow_clk_src_t slow_clk_src) SET_PERI_REG_BITS(MODEM_CLKRST_ETM_CLK_CONF_REG, 1, 0, MODEM_CLKRST_ETM_CLK_SEL_S); } -static ble_rtc_slow_clk_src_t ble_rtc_clk_init(esp_bt_controller_config_t *cfg) +static modem_clock_lpclk_src_t ble_rtc_clk_init(esp_bt_controller_config_t *cfg) { - ble_rtc_slow_clk_src_t slow_clk_src; - + if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_INVALID) { #if CONFIG_BT_LE_LP_CLK_SRC_MAIN_XTAL -#ifdef CONFIG_XTAL_FREQ_26 - cfg->rtc_freq = 40000; -#else - cfg->rtc_freq = 32000; -#endif // CONFIG_XTAL_FREQ_26 - slow_clk_src = BT_SLOW_CLK_SRC_MAIN_XTAL; + s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL; #else - if (rtc_clk_slow_src_get() == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) { + if (rtc_clk_slow_src_get() == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) { + s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_EXT32K; + } else { + ESP_LOGW(NIMBLE_PORT_LOG_TAG, "32.768kHz XTAL not detected, fall back to main XTAL as Bluetooth sleep clock"); + s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL; + } +#endif // CONFIG_BT_LE_LP_CLK_SRC_MAIN_XTAL + } + + if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_EXT32K) { cfg->rtc_freq = 32768; - slow_clk_src = BT_SLOW_CLK_SRC_32K_XTAL_ON_PIN0; - } else { - ESP_LOGW(NIMBLE_PORT_LOG_TAG, "32.768kHz XTAL not detected, fall back to main XTAL as Bluetooth sleep clock"); + } else if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL) { #ifdef CONFIG_XTAL_FREQ_26 cfg->rtc_freq = 40000; #else cfg->rtc_freq = 32000; #endif // CONFIG_XTAL_FREQ_26 - slow_clk_src = BT_SLOW_CLK_SRC_MAIN_XTAL; } -#endif /* CONFIG_BT_LE_LP_CLK_SRC_MAIN_XTAL */ - esp_bt_rtc_slow_clk_select(slow_clk_src); - return slow_clk_src; + esp_bt_rtc_slow_clk_select(s_bt_lpclk_src); + return s_bt_lpclk_src; } esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg) { esp_err_t ret = ESP_OK; ble_npl_count_info_t npl_info; - ble_rtc_slow_clk_src_t rtc_clk_src; + modem_clock_lpclk_src_t rtc_clk_src; uint8_t hci_transport_mode; memset(&npl_info, 0, sizeof(ble_npl_count_info_t)); diff --git a/components/bt/controller/esp32c6/bt.c b/components/bt/controller/esp32c6/bt.c index c3e8526d71e..d5c9813df55 100644 --- a/components/bt/controller/esp32c6/bt.c +++ b/components/bt/controller/esp32c6/bt.c @@ -391,6 +391,7 @@ static bool s_ble_active = false; static DRAM_ATTR esp_pm_lock_handle_t s_pm_lock = NULL; #define BTDM_MIN_TIMER_UNCERTAINTY_US (200) #endif // CONFIG_PM_ENABLE +static DRAM_ATTR modem_clock_lpclk_src_t s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_INVALID; #define BLE_RTC_DELAY_US_LIGHT_SLEEP (2500) #define BLE_RTC_DELAY_US_MODEM_SLEEP (500) @@ -534,6 +535,20 @@ void esp_bt_rtc_slow_clk_select(uint8_t slow_clk_src) } } +modem_clock_lpclk_src_t esp_bt_get_lpclk_src(void) +{ + return s_bt_lpclk_src; +} + +void esp_bt_set_lpclk_src(modem_clock_lpclk_src_t clk_src) +{ + if (clk_src >= MODEM_CLOCK_LPCLK_SRC_MAX) { + return; + } + + s_bt_lpclk_src = clk_src; +} + IRAM_ATTR void controller_sleep_cb(uint32_t enable_tick, void *arg) { if (!s_ble_active) { @@ -757,12 +772,51 @@ void ble_controller_scan_duplicate_config(void) ble_vhci_disc_duplicate_set_max_cache_size(cache_size); } +static void ble_rtc_clk_init(esp_bt_controller_config_t *cfg) +{ + if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_INVALID) { +#if CONFIG_BT_LE_LP_CLK_SRC_MAIN_XTAL + s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL; +#else +#if CONFIG_RTC_CLK_SRC_INT_RC + s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_RC_SLOW; +#elif CONFIG_RTC_CLK_SRC_EXT_CRYS + if (rtc_clk_slow_src_get() == SOC_RTC_SLOW_CLK_SRC_XTAL32K) { + s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_XTAL32K; + } else { + ESP_LOGW(NIMBLE_PORT_LOG_TAG, "32.768kHz XTAL not detected, fall back to main XTAL as Bluetooth sleep clock"); + s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL; + } +#elif CONFIG_RTC_CLK_SRC_INT_RC32K + s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_RC32K; +#elif CONFIG_RTC_CLK_SRC_EXT_OSC + s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_EXT32K; +#else + ESP_LOGE(NIMBLE_PORT_LOG_TAG, "Unsupported clock source"); + assert(0); +#endif +#endif /* CONFIG_BT_LE_LP_CLK_SRC_MAIN_XTAL */ + } + + if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL) { + cfg->rtc_freq = 100000; + } else if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_XTAL32K) { + cfg->rtc_freq = 32768; + } else if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_RC_SLOW) { + cfg->rtc_freq = 30000; + } else if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_RC32K) { + cfg->rtc_freq = 32000; + } else if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_EXT32K) { + cfg->rtc_freq = 32000; + } + esp_bt_rtc_slow_clk_select(s_bt_lpclk_src); +} + esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg) { uint8_t mac[6]; esp_err_t ret = ESP_OK; ble_npl_count_info_t npl_info; - uint32_t slow_clk_freq = 0; uint8_t hci_transport_mode; memset(&npl_info, 0, sizeof(ble_npl_count_info_t)); @@ -814,33 +868,7 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg) modem_clock_module_enable(PERIPH_BT_MODULE); modem_clock_module_mac_reset(PERIPH_BT_MODULE); /* Select slow clock source for BT momdule */ -#if CONFIG_BT_LE_LP_CLK_SRC_MAIN_XTAL - esp_bt_rtc_slow_clk_select(MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL); - slow_clk_freq = 100000; -#else -#if CONFIG_RTC_CLK_SRC_INT_RC - esp_bt_rtc_slow_clk_select(MODEM_CLOCK_LPCLK_SRC_RC_SLOW); - slow_clk_freq = 30000; -#elif CONFIG_RTC_CLK_SRC_EXT_CRYS - if (rtc_clk_slow_src_get() == SOC_RTC_SLOW_CLK_SRC_XTAL32K) { - esp_bt_rtc_slow_clk_select(MODEM_CLOCK_LPCLK_SRC_XTAL32K); - slow_clk_freq = 32768; - } else { - ESP_LOGW(NIMBLE_PORT_LOG_TAG, "32.768kHz XTAL not detected, fall back to main XTAL as Bluetooth sleep clock"); - esp_bt_rtc_slow_clk_select(MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL); - slow_clk_freq = 100000; - } -#elif CONFIG_RTC_CLK_SRC_INT_RC32K - esp_bt_rtc_slow_clk_select(MODEM_CLOCK_LPCLK_SRC_RC32K); - slow_clk_freq = 32000; -#elif CONFIG_RTC_CLK_SRC_EXT_OSC - esp_bt_rtc_slow_clk_select(MODEM_CLOCK_LPCLK_SRC_EXT32K); - slow_clk_freq = 32000; -#else - ESP_LOGE(NIMBLE_PORT_LOG_TAG, "Unsupported clock source"); - assert(0); -#endif -#endif /* CONFIG_BT_LE_LP_CLK_SRC_MAIN_XTAL */ + ble_rtc_clk_init(cfg); esp_phy_modem_init(); if (ble_osi_coex_funcs_register((struct osi_coex_funcs_t *)&s_osi_coex_funcs_ro) != 0) { @@ -873,7 +901,6 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg) } ESP_LOGI(NIMBLE_PORT_LOG_TAG, "ble controller commit:[%s]", ble_controller_get_compile_version()); - r_esp_ble_change_rtc_freq(slow_clk_freq); ble_controller_scan_duplicate_config(); diff --git a/components/bt/controller/esp32h2/bt.c b/components/bt/controller/esp32h2/bt.c index 7c41dc246c0..e667fa6b99f 100644 --- a/components/bt/controller/esp32h2/bt.c +++ b/components/bt/controller/esp32h2/bt.c @@ -130,7 +130,7 @@ extern sleep_retention_entries_config_t *r_esp_ble_mac_retention_link_get(uint8_ extern void r_esp_ble_set_wakeup_overhead(uint32_t overhead); #endif /* CONFIG_FREERTOS_USE_TICKLESS_IDLE */ #if CONFIG_PM_ENABLE -extern void esp_ble_stop_wakeup_timing(void); +extern void r_esp_ble_stop_wakeup_timing(void); #endif // CONFIG_PM_ENABLE extern void r_esp_ble_change_rtc_freq(uint32_t freq); extern int ble_sm_alg_gen_dhkey(const uint8_t *peer_pub_key_x, @@ -387,6 +387,7 @@ static bool s_ble_active = false; static DRAM_ATTR esp_pm_lock_handle_t s_pm_lock = NULL; #define BTDM_MIN_TIMER_UNCERTAINTY_US (200) #endif // CONFIG_PM_ENABLE +static DRAM_ATTR modem_clock_lpclk_src_t s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_INVALID; #define BLE_RTC_DELAY_US_LIGHT_SLEEP (5100) #define BLE_RTC_DELAY_US_MODEM_SLEEP (1500) @@ -525,6 +526,20 @@ void esp_bt_rtc_slow_clk_select(uint8_t slow_clk_src) } } +modem_clock_lpclk_src_t esp_bt_get_lpclk_src(void) +{ + return s_bt_lpclk_src; +} + +void esp_bt_set_lpclk_src(modem_clock_lpclk_src_t clk_src) +{ + if (clk_src >= MODEM_CLOCK_LPCLK_SRC_MAX) { + return; + } + + s_bt_lpclk_src = clk_src; +} + IRAM_ATTR void controller_sleep_cb(uint32_t enable_tick, void *arg) { if (!s_ble_active) { @@ -617,7 +632,7 @@ esp_err_t controller_sleep_init(void) goto error; } - rc = esp_deep_sleep_register_hook(&esp_ble_stop_wakeup_timing); + rc = esp_deep_sleep_register_hook(&r_esp_ble_stop_wakeup_timing); assert(rc == 0); #if CONFIG_FREERTOS_USE_TICKLESS_IDLE /* Create a new regdma link for BLE related register restoration */ @@ -639,7 +654,7 @@ esp_err_t controller_sleep_init(void) esp_sleep_disable_bt_wakeup(); esp_pm_unregister_inform_out_light_sleep_overhead_callback(sleep_modem_light_sleep_overhead_set); #endif /* CONFIG_FREERTOS_USE_TICKLESS_IDLE */ - esp_deep_sleep_deregister_hook(&esp_ble_stop_wakeup_timing); + esp_deep_sleep_deregister_hook(&r_esp_ble_stop_wakeup_timing); /*lock should release first and then delete*/ if (s_pm_lock != NULL) { esp_pm_lock_delete(s_pm_lock); @@ -659,7 +674,7 @@ void controller_sleep_deinit(void) esp_pm_unregister_inform_out_light_sleep_overhead_callback(sleep_modem_light_sleep_overhead_set); #endif /* CONFIG_FREERTOS_USE_TICKLESS_IDLE */ #ifdef CONFIG_PM_ENABLE - esp_deep_sleep_deregister_hook(&esp_ble_stop_wakeup_timing); + esp_deep_sleep_deregister_hook(&r_esp_ble_stop_wakeup_timing); /* lock should be released first */ esp_pm_lock_delete(s_pm_lock); s_pm_lock = NULL; @@ -737,12 +752,51 @@ void ble_controller_scan_duplicate_config(void) ble_vhci_disc_duplicate_set_max_cache_size(cache_size); } +static void ble_rtc_clk_init(esp_bt_controller_config_t *cfg) +{ + if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_INVALID) { +#if CONFIG_BT_LE_LP_CLK_SRC_MAIN_XTAL + s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL; +#else +#if CONFIG_RTC_CLK_SRC_INT_RC + s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_RC_SLOW; +#elif CONFIG_RTC_CLK_SRC_EXT_CRYS + if (rtc_clk_slow_src_get() == SOC_RTC_SLOW_CLK_SRC_XTAL32K) { + s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_XTAL32K; + } else { + ESP_LOGW(NIMBLE_PORT_LOG_TAG, "32.768kHz XTAL not detected, fall back to main XTAL as Bluetooth sleep clock"); + s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL; + } +#elif CONFIG_RTC_CLK_SRC_INT_RC32K + s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_RC32K; +#elif CONFIG_RTC_CLK_SRC_EXT_OSC + s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_EXT32K; +#else + ESP_LOGE(NIMBLE_PORT_LOG_TAG, "Unsupported clock source"); + assert(0); +#endif +#endif /* CONFIG_BT_LE_LP_CLK_SRC_MAIN_XTAL */ + } + + if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL) { + cfg->rtc_freq = 100000; + } else if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_XTAL32K) { + cfg->rtc_freq = 32768; + } else if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_RC_SLOW) { + cfg->rtc_freq = 30000; + } else if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_RC32K) { + cfg->rtc_freq = 32000; + } else if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_EXT32K) { + cfg->rtc_freq = 32000; + } + esp_bt_rtc_slow_clk_select(s_bt_lpclk_src); +} + esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg) { uint8_t mac[6]; esp_err_t ret = ESP_OK; ble_npl_count_info_t npl_info; - uint32_t slow_clk_freq = 0; uint8_t hci_transport_mode; memset(&npl_info, 0, sizeof(ble_npl_count_info_t)); @@ -794,33 +848,7 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg) modem_clock_module_enable(PERIPH_BT_MODULE); modem_clock_module_mac_reset(PERIPH_BT_MODULE); /* Select slow clock source for BT momdule */ -#if CONFIG_BT_LE_LP_CLK_SRC_MAIN_XTAL - esp_bt_rtc_slow_clk_select(MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL); - slow_clk_freq = 100000; -#else -#if CONFIG_RTC_CLK_SRC_INT_RC - esp_bt_rtc_slow_clk_select(MODEM_CLOCK_LPCLK_SRC_RC_SLOW); - slow_clk_freq = 30000; -#elif CONFIG_RTC_CLK_SRC_EXT_CRYS - if (rtc_clk_slow_src_get() == SOC_RTC_SLOW_CLK_SRC_XTAL32K) { - esp_bt_rtc_slow_clk_select(MODEM_CLOCK_LPCLK_SRC_XTAL32K); - slow_clk_freq = 32768; - } else { - ESP_LOGW(NIMBLE_PORT_LOG_TAG, "32.768kHz XTAL not detected, fall back to main XTAL as Bluetooth sleep clock"); - esp_bt_rtc_slow_clk_select(MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL); - slow_clk_freq = 100000; - } -#elif CONFIG_RTC_CLK_SRC_INT_RC32K - esp_bt_rtc_slow_clk_select(MODEM_CLOCK_LPCLK_SRC_RC32K); - slow_clk_freq = 32000; -#elif CONFIG_RTC_CLK_SRC_EXT_OSC - esp_bt_rtc_slow_clk_select(MODEM_CLOCK_LPCLK_SRC_EXT32K); - slow_clk_freq = 32000; -#else - ESP_LOGE(NIMBLE_PORT_LOG_TAG, "Unsupported clock source"); - assert(0); -#endif -#endif /* CONFIG_BT_LE_LP_CLK_SRC_MAIN_XTAL */ + ble_rtc_clk_init(cfg); if (ble_osi_coex_funcs_register((struct osi_coex_funcs_t *)&s_osi_coex_funcs_ro) != 0) { ESP_LOGW(NIMBLE_PORT_LOG_TAG, "osi coex funcs reg failed"); @@ -852,7 +880,6 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg) } ESP_LOGI(NIMBLE_PORT_LOG_TAG, "ble controller commit:[%s]", ble_controller_get_compile_version()); - r_esp_ble_change_rtc_freq(slow_clk_freq); ble_controller_scan_duplicate_config(); diff --git a/components/bt/include/esp32c2/include/esp_bt.h b/components/bt/include/esp32c2/include/esp_bt.h index c73d4cb9243..148f615b6d0 100644 --- a/components/bt/include/esp32c2/include/esp_bt.h +++ b/components/bt/include/esp32c2/include/esp_bt.h @@ -16,6 +16,7 @@ #include "nimble/nimble_npl.h" #include "../../../../controller/esp32c2/esp_bt_cfg.h" #include "hal/efuse_hal.h" +#include "esp_private/esp_modem_clock.h" #ifdef CONFIG_BT_LE_HCI_INTERFACE_USE_UART #include "driver/uart.h" @@ -428,6 +429,12 @@ extern int esp_ble_hw_get_static_addr(esp_ble_addr_t *addr); void esp_ble_controller_log_dump_all(bool output); #endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED +#if CONFIG_PM_ENABLE +modem_clock_lpclk_src_t esp_bt_get_lpclk_src(void); + +void esp_bt_set_lpclk_src(modem_clock_lpclk_src_t clk_src); +#endif // CONFIG_PM_ENABLE + #ifdef __cplusplus } #endif diff --git a/components/bt/include/esp32c6/include/esp_bt.h b/components/bt/include/esp32c6/include/esp_bt.h index ea272287228..f5ad1947f3f 100644 --- a/components/bt/include/esp32c6/include/esp_bt.h +++ b/components/bt/include/esp32c6/include/esp_bt.h @@ -16,6 +16,7 @@ #include "nimble/nimble_npl.h" #include "../../../../controller/esp32c6/esp_bt_cfg.h" #include "hal/efuse_hal.h" +#include "esp_private/esp_modem_clock.h" #ifdef CONFIG_BT_LE_HCI_INTERFACE_USE_UART #include "driver/uart.h" @@ -414,6 +415,12 @@ extern int esp_ble_hw_get_static_addr(esp_ble_addr_t *addr); void esp_ble_controller_log_dump_all(bool output); #endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED +#if CONFIG_PM_ENABLE +modem_clock_lpclk_src_t esp_bt_get_lpclk_src(void); + +void esp_bt_set_lpclk_src(modem_clock_lpclk_src_t clk_src); +#endif // CONFIG_PM_ENABLE + #ifdef __cplusplus } #endif diff --git a/components/bt/include/esp32h2/include/esp_bt.h b/components/bt/include/esp32h2/include/esp_bt.h index bbecb64072f..95cf36cc58a 100644 --- a/components/bt/include/esp32h2/include/esp_bt.h +++ b/components/bt/include/esp32h2/include/esp_bt.h @@ -15,6 +15,7 @@ #include "nimble/nimble_npl.h" #include "../../../../controller/esp32h2/esp_bt_cfg.h" +#include "esp_private/esp_modem_clock.h" #ifdef CONFIG_BT_LE_HCI_INTERFACE_USE_UART #include "driver/uart.h" @@ -418,6 +419,12 @@ extern int esp_ble_hw_get_static_addr(esp_ble_addr_t *addr); void esp_ble_controller_log_dump_all(bool output); #endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED +#if CONFIG_PM_ENABLE +modem_clock_lpclk_src_t esp_bt_get_lpclk_src(void); + +void esp_bt_set_lpclk_src(modem_clock_lpclk_src_t clk_src); +#endif // CONFIG_PM_ENABLE + #ifdef __cplusplus } #endif