From 3bfd8f5d5fd2cd6d8cc8318877ed3ffb36456c24 Mon Sep 17 00:00:00 2001 From: morris Date: Tue, 24 Aug 2021 14:42:07 +0800 Subject: [PATCH] mcpwm: update register file according to TRM --- components/hal/esp32/include/hal/mcpwm_ll.h | 337 +- components/hal/esp32s3/include/hal/mcpwm_ll.h | 345 +- components/soc/esp32/include/soc/mcpwm_reg.h | 6572 +++++++++-------- .../soc/esp32/include/soc/mcpwm_struct.h | 1899 +++-- .../soc/esp32s3/include/soc/mcpwm_reg.h | 6515 +++++++++------- .../soc/esp32s3/include/soc/mcpwm_struct.h | 1905 +++-- 6 files changed, 10662 insertions(+), 6911 deletions(-) diff --git a/components/hal/esp32/include/hal/mcpwm_ll.h b/components/hal/esp32/include/hal/mcpwm_ll.h index f2e3b34183e..ab443f6019a 100644 --- a/components/hal/esp32/include/hal/mcpwm_ll.h +++ b/components/hal/esp32/include/hal/mcpwm_ll.h @@ -41,15 +41,20 @@ extern "C" { /********************* Group registers *******************/ -// Set/Get group clock: PWM_clk = CLK_160M / (clk_cfg.prescale + 1) +// Set/Get group clock: PWM_clk = CLK_160M / (prescale + 1) static inline void mcpwm_ll_group_set_clock_prescale(mcpwm_dev_t *mcpwm, int pre_scale) { - mcpwm->clk_cfg.prescale = pre_scale - 1; + // In case the compiler optimise a 32bit instruction (e.g. s32i) into 8bit instruction (e.g. s8i, which is not allowed to access a register) + // We take care of the "read-modify-write" procedure by ourselves. + mcpwm_clk_cfg_reg_t clkcfg = mcpwm->clk_cfg; + clkcfg.clk_prescale = pre_scale - 1; + mcpwm->clk_cfg = clkcfg; } static inline uint32_t mcpwm_ll_group_get_clock_prescale(mcpwm_dev_t *mcpwm) { - return mcpwm->clk_cfg.prescale + 1; + mcpwm_clk_cfg_reg_t clkcfg = mcpwm->clk_cfg; + return clkcfg.clk_prescale + 1; } static inline void mcpwm_ll_group_enable_shadow_mode(mcpwm_dev_t *mcpwm) @@ -265,20 +270,25 @@ static inline void mcpwm_ll_intr_enable_capture(mcpwm_dev_t *mcpwm, uint32_t cap static inline void mcpwm_ll_timer_set_clock_prescale(mcpwm_dev_t *mcpwm, int timer_id, uint32_t prescale) { - mcpwm->timer[timer_id].period.prescale = prescale - 1; + // In case the compiler optimise a 32bit instruction (e.g. s32i) into 8bit instruction (e.g. s8i, which is not allowed to access a register) + // We take care of the "read-modify-write" procedure by ourselves. + mcpwm_timer_cfg0_reg_t cfg0 = mcpwm->timer[timer_id].timer_cfg0; + cfg0.timer_prescale = prescale - 1; + mcpwm->timer[timer_id].timer_cfg0 = cfg0; } static inline uint32_t mcpwm_ll_timer_get_clock_prescale(mcpwm_dev_t *mcpwm, int timer_id) { - return mcpwm->timer[timer_id].period.prescale + 1; + mcpwm_timer_cfg0_reg_t cfg0 = mcpwm->timer[timer_id].timer_cfg0; + return cfg0.timer_prescale + 1; } static inline void mcpwm_ll_timer_set_peak(mcpwm_dev_t *mcpwm, int timer_id, uint32_t peak, bool symmetric) { if (!symmetric) { // in asymmetric mode, period = [0,peak-1] - mcpwm->timer[timer_id].period.period = peak - 1; + mcpwm->timer[timer_id].timer_cfg0.timer_period = peak - 1; } else { // in symmetric mode, period = [0,peak-1] + [peak,1] - mcpwm->timer[timer_id].period.period = peak; + mcpwm->timer[timer_id].timer_cfg0.timer_period = peak; } } @@ -286,32 +296,32 @@ static inline uint32_t mcpwm_ll_timer_get_peak(mcpwm_dev_t *mcpwm, int timer_id, { // asymmetric mode if (!symmetric) { - return mcpwm->timer[timer_id].period.period + 1; + return mcpwm->timer[timer_id].timer_cfg0.timer_period + 1; } // symmetric mode - return mcpwm->timer[timer_id].period.period; + return mcpwm->timer[timer_id].timer_cfg0.timer_period; } static inline void mcpwm_ll_timer_update_period_at_once(mcpwm_dev_t *mcpwm, int timer_id) { - mcpwm->timer[timer_id].period.upmethod = 0; + mcpwm->timer[timer_id].timer_cfg0.timer_period_upmethod = 0; } static inline void mcpwm_ll_timer_enable_update_period_on_tez(mcpwm_dev_t *mcpwm, int timer_id, bool enable) { if (enable) { - mcpwm->timer[timer_id].period.upmethod |= 0x01; + mcpwm->timer[timer_id].timer_cfg0.timer_period_upmethod |= 0x01; } else { - mcpwm->timer[timer_id].period.upmethod &= ~0x01; + mcpwm->timer[timer_id].timer_cfg0.timer_period_upmethod &= ~0x01; } } static inline void mcpwm_ll_timer_enable_update_period_on_sync(mcpwm_dev_t *mcpwm, int timer_id, bool enable) { if (enable) { - mcpwm->timer[timer_id].period.upmethod |= 0x02; + mcpwm->timer[timer_id].timer_cfg0.timer_period_upmethod |= 0x02; } else { - mcpwm->timer[timer_id].period.upmethod &= ~0x02; + mcpwm->timer[timer_id].timer_cfg0.timer_period_upmethod &= ~0x02; } } @@ -319,23 +329,23 @@ static inline void mcpwm_ll_timer_set_count_mode(mcpwm_dev_t *mcpwm, int timer_i { switch (mode) { case MCPWM_TIMER_COUNT_MODE_PAUSE: - mcpwm->timer[timer_id].mode.mode = 0; + mcpwm->timer[timer_id].timer_cfg1.timer_mod = 0; break; case MCPWM_TIMER_COUNT_MODE_UP: - mcpwm->timer[timer_id].mode.mode = 1; + mcpwm->timer[timer_id].timer_cfg1.timer_mod = 1; break; case MCPWM_TIMER_COUNT_MODE_DOWN: - mcpwm->timer[timer_id].mode.mode = 2; + mcpwm->timer[timer_id].timer_cfg1.timer_mod = 2; break; case MCPWM_TIMER_COUNT_MODE_UP_DOWN: - mcpwm->timer[timer_id].mode.mode = 3; + mcpwm->timer[timer_id].timer_cfg1.timer_mod = 3; break; } } static inline mcpwm_timer_count_mode_t mcpwm_ll_timer_get_count_mode(mcpwm_dev_t *mcpwm, int timer_id) { - switch (mcpwm->timer[timer_id].mode.mode) { + switch (mcpwm->timer[timer_id].timer_cfg1.timer_mod) { case 0: return MCPWM_TIMER_COUNT_MODE_PAUSE; case 1: @@ -344,6 +354,9 @@ static inline mcpwm_timer_count_mode_t mcpwm_ll_timer_get_count_mode(mcpwm_dev_t return MCPWM_TIMER_COUNT_MODE_DOWN; case 3: return MCPWM_TIMER_COUNT_MODE_UP_DOWN; + default: + HAL_ASSERT(false && "unknown count mode"); + return mcpwm->timer[timer_id].timer_cfg1.timer_mod; } } @@ -351,74 +364,74 @@ static inline void mcpwm_ll_timer_set_execute_command(mcpwm_dev_t *mcpwm, int ti { switch (cmd) { case MCPWM_TIMER_STOP_AT_ZERO: - mcpwm->timer[timer_id].mode.start = 0; + mcpwm->timer[timer_id].timer_cfg1.timer_start = 0; break; case MCPWM_TIMER_STOP_AT_PEAK: - mcpwm->timer[timer_id].mode.start = 1; + mcpwm->timer[timer_id].timer_cfg1.timer_start = 1; break; case MCPWM_TIMER_START_NO_STOP: - mcpwm->timer[timer_id].mode.start = 2; + mcpwm->timer[timer_id].timer_cfg1.timer_start = 2; break; case MCPWM_TIMER_START_STOP_AT_ZERO: - mcpwm->timer[timer_id].mode.start = 3; + mcpwm->timer[timer_id].timer_cfg1.timer_start = 3; break; case MCPWM_TIMER_START_STOP_AT_PEAK: - mcpwm->timer[timer_id].mode.start = 4; + mcpwm->timer[timer_id].timer_cfg1.timer_start = 4; break; } } static inline uint32_t mcpwm_ll_timer_get_count_value(mcpwm_dev_t *mcpwm, int timer_id) { - return mcpwm->timer[timer_id].status.value; + return mcpwm->timer[timer_id].timer_status.timer_value; } static inline mcpwm_timer_direction_t mcpwm_ll_timer_get_count_direction(mcpwm_dev_t *mcpwm, int timer_id) { - return mcpwm->timer[timer_id].status.direction ? MCPWM_TIMER_DIRECTION_DOWN : MCPWM_TIMER_DIRECTION_UP; + return mcpwm->timer[timer_id].timer_status.timer_direction ? MCPWM_TIMER_DIRECTION_DOWN : MCPWM_TIMER_DIRECTION_UP; } static inline void mcpwm_ll_timer_enable_sync_input(mcpwm_dev_t *mcpwm, int timer_id, bool enable) { - mcpwm->timer[timer_id].sync.in_en = enable; + mcpwm->timer[timer_id].timer_sync.timer_synci_en = enable; } static inline void mcpwm_ll_timer_sync_out_penetrate(mcpwm_dev_t *mcpwm, int timer_id) { // sync_out is selected to sync_in - mcpwm->timer[timer_id].sync.out_sel = 0; + mcpwm->timer[timer_id].timer_sync.timer_synco_sel = 0; } static inline void mcpwm_ll_timer_sync_out_on_timer_event(mcpwm_dev_t *mcpwm, int timer_id, mcpwm_timer_event_t event) { if (event == MCPWM_TIMER_EVENT_ZERO) { - mcpwm->timer[timer_id].sync.out_sel = 1; + mcpwm->timer[timer_id].timer_sync.timer_synco_sel = 1; } else if (event == MCPWM_TIMER_EVENT_PEAK) { - mcpwm->timer[timer_id].sync.out_sel = 2; + mcpwm->timer[timer_id].timer_sync.timer_synco_sel = 2; } else { - HAL_ASSERT(false); + HAL_ASSERT(false && "unknown sync out event"); } } static inline void mcpwm_ll_timer_disable_sync_out(mcpwm_dev_t *mcpwm, int timer_id) { // sync_out will always be zero - mcpwm->timer[timer_id].sync.out_sel = 3; + mcpwm->timer[timer_id].timer_sync.timer_synco_sel = 3; } static inline void mcpwm_ll_timer_trigger_soft_sync(mcpwm_dev_t *mcpwm, int timer_id) { - mcpwm->timer[timer_id].sync.sync_sw = ~mcpwm->timer[timer_id].sync.sync_sw; + mcpwm->timer[timer_id].timer_sync.timer_sync_sw = ~mcpwm->timer[timer_id].timer_sync.timer_sync_sw; } static inline void mcpwm_ll_timer_set_sync_phase_value(mcpwm_dev_t *mcpwm, int timer_id, uint32_t phase_value) { - mcpwm->timer[timer_id].sync.timer_phase = phase_value; + mcpwm->timer[timer_id].timer_sync.timer_phase = phase_value; } static inline void mcpwm_ll_timer_set_sync_phase_direction(mcpwm_dev_t *mcpwm, int timer_id, mcpwm_timer_direction_t direction) { - mcpwm->timer[timer_id].sync.phase_direct = direction; + mcpwm->timer[timer_id].timer_sync.timer_phase_direction = direction; } static inline void mcpwm_ll_timer_set_gpio_synchro(mcpwm_dev_t *mcpwm, int timer, int gpio_sync_id) @@ -458,117 +471,117 @@ static inline void mcpwm_ll_operator_flush_shadow(mcpwm_dev_t *mcpwm, int operat static inline void mcpwm_ll_operator_select_timer(mcpwm_dev_t *mcpwm, int operator_id, int timer_id) { if (operator_id == 0) { - mcpwm->timer_sel.operator0_sel = timer_id; + mcpwm->operator_timersel.operator0_timersel = timer_id; } else if (operator_id == 1) { - mcpwm->timer_sel.operator1_sel = timer_id; + mcpwm->operator_timersel.operator1_timersel = timer_id; } else { - mcpwm->timer_sel.operator2_sel = timer_id; + mcpwm->operator_timersel.operator2_timersel = timer_id; } } static inline void mcpwm_ll_operator_update_compare_at_once(mcpwm_dev_t *mcpwm, int operator_id, int compare_id) { - mcpwm->channel[operator_id].cmpr_cfg.val &= ~(0x0F << (4 * compare_id)); + mcpwm->operator[operator_id].gen_stmp_cfg.val &= ~(0x0F << (4 * compare_id)); } static inline void mcpwm_ll_operator_enable_update_compare_on_tez(mcpwm_dev_t *mcpwm, int operator_id, int compare_id, bool enable) { if (enable) { - mcpwm->channel[operator_id].cmpr_cfg.val |= (1 << 0) << (4 * compare_id); + mcpwm->operator[operator_id].gen_stmp_cfg.val |= (1 << 0) << (4 * compare_id); } else { - mcpwm->channel[operator_id].cmpr_cfg.val &= ~((1 << 0) << (4 * compare_id)); + mcpwm->operator[operator_id].gen_stmp_cfg.val &= ~((1 << 0) << (4 * compare_id)); } } static inline void mcpwm_ll_operator_enable_update_compare_on_tep(mcpwm_dev_t *mcpwm, int operator_id, int compare_id, bool enable) { if (enable) { - mcpwm->channel[operator_id].cmpr_cfg.val |= (1 << 1) << (4 * compare_id); + mcpwm->operator[operator_id].gen_stmp_cfg.val |= (1 << 1) << (4 * compare_id); } else { - mcpwm->channel[operator_id].cmpr_cfg.val &= ~((1 << 1) << (4 * compare_id)); + mcpwm->operator[operator_id].gen_stmp_cfg.val &= ~((1 << 1) << (4 * compare_id)); } } static inline void mcpwm_ll_operator_enable_update_compare_on_sync(mcpwm_dev_t *mcpwm, int operator_id, int compare_id, bool enable) { if (enable) { - mcpwm->channel[operator_id].cmpr_cfg.val |= (1 << 2) << (4 * compare_id); + mcpwm->operator[operator_id].gen_stmp_cfg.val |= (1 << 2) << (4 * compare_id); } else { - mcpwm->channel[operator_id].cmpr_cfg.val &= ~((1 << 2) << (4 * compare_id)); + mcpwm->operator[operator_id].gen_stmp_cfg.val &= ~((1 << 2) << (4 * compare_id)); } } static inline void mcpwm_ll_operator_set_compare_value(mcpwm_dev_t *mcpwm, int operator_id, int compare_id, uint32_t compare_value) { - mcpwm->channel[operator_id].cmpr_value[compare_id].cmpr_val = compare_value; + mcpwm->operator[operator_id].timestamp[compare_id].gen = compare_value; } static inline uint32_t mcpwm_ll_operator_get_compare_value(mcpwm_dev_t *mcpwm, int operator_id, int compare_id) { - return mcpwm->channel[operator_id].cmpr_value[compare_id].cmpr_val; + return mcpwm->operator[operator_id].timestamp[compare_id].gen; } static inline void mcpwm_ll_operator_update_action_at_once(mcpwm_dev_t *mcpwm, int operator_id) { - mcpwm->channel[operator_id].gen_cfg0.upmethod = 0; + mcpwm->operator[operator_id].gen_cfg0.gen_cfg_upmethod = 0; } static inline void mcpwm_ll_operator_enable_update_action_on_tez(mcpwm_dev_t *mcpwm, int operator_id, bool enable) { if (enable) { - mcpwm->channel[operator_id].gen_cfg0.upmethod |= 1 << 0; + mcpwm->operator[operator_id].gen_cfg0.gen_cfg_upmethod |= 1 << 0; } else { - mcpwm->channel[operator_id].gen_cfg0.upmethod &= ~(1 << 0); + mcpwm->operator[operator_id].gen_cfg0.gen_cfg_upmethod &= ~(1 << 0); } } static inline void mcpwm_ll_operator_enable_update_action_on_tep(mcpwm_dev_t *mcpwm, int operator_id, bool enable) { if (enable) { - mcpwm->channel[operator_id].gen_cfg0.upmethod |= 1 << 1; + mcpwm->operator[operator_id].gen_cfg0.gen_cfg_upmethod |= 1 << 1; } else { - mcpwm->channel[operator_id].gen_cfg0.upmethod &= ~(1 << 1); + mcpwm->operator[operator_id].gen_cfg0.gen_cfg_upmethod &= ~(1 << 1); } } static inline void mcpwm_ll_operator_enable_update_action_on_sync(mcpwm_dev_t *mcpwm, int operator_id, bool enable) { if (enable) { - mcpwm->channel[operator_id].gen_cfg0.upmethod |= 1 << 2; + mcpwm->operator[operator_id].gen_cfg0.gen_cfg_upmethod |= 1 << 2; } else { - mcpwm->channel[operator_id].gen_cfg0.upmethod &= ~(1 << 2); + mcpwm->operator[operator_id].gen_cfg0.gen_cfg_upmethod &= ~(1 << 2); } } static inline void mcpwm_ll_operator_set_trigger_gpio_fault(mcpwm_dev_t *mcpwm, int operator_id, int trig_id, int fault_id) { - mcpwm->channel[operator_id].gen_cfg0.val &= ~(0x07 << (4 + 3 * trig_id)); - mcpwm->channel[operator_id].gen_cfg0.val |= (fault_id << (4 + 3 * trig_id)); + mcpwm->operator[operator_id].gen_cfg0.val &= ~(0x07 << (4 + 3 * trig_id)); + mcpwm->operator[operator_id].gen_cfg0.val |= (fault_id << (4 + 3 * trig_id)); } static inline void mcpwm_ll_operator_set_trigger_timer_sync(mcpwm_dev_t *mcpwm, int operator_id, int trig_id) { // the timer here is not selectable, must be the one connected with the operator - mcpwm->channel[operator_id].gen_cfg0.val &= ~(0x07 << (4 + 3 * trig_id)); - mcpwm->channel[operator_id].gen_cfg0.val |= (3 << (4 + 3 * trig_id)); + mcpwm->operator[operator_id].gen_cfg0.val &= ~(0x07 << (4 + 3 * trig_id)); + mcpwm->operator[operator_id].gen_cfg0.val |= (3 << (4 + 3 * trig_id)); } /********************* Generator registers *******************/ static inline void mcpwm_ll_generator_reset_actions(mcpwm_dev_t *mcpwm, int operator_id, int generator_id) { - mcpwm->channel[operator_id].generator[generator_id].val = 0; + mcpwm->operator[operator_id].generator[generator_id].val = 0; } static inline void mcpwm_ll_generator_set_action_on_timer_event(mcpwm_dev_t *mcpwm, int operator_id, int generator_id, mcpwm_timer_direction_t direction, mcpwm_timer_event_t event, mcpwm_generator_action_t action) { if (direction == MCPWM_TIMER_DIRECTION_UP) { // utez, utep - mcpwm->channel[operator_id].generator[generator_id].val &= ~(0x03 << (event * 2)); - mcpwm->channel[operator_id].generator[generator_id].val |= action << (event * 2); + mcpwm->operator[operator_id].generator[generator_id].val &= ~(0x03 << (event * 2)); + mcpwm->operator[operator_id].generator[generator_id].val |= action << (event * 2); } else if (direction == MCPWM_TIMER_DIRECTION_DOWN) { // dtez, dtep - mcpwm->channel[operator_id].generator[generator_id].val &= ~(0x03 << (event * 2 + 12)); - mcpwm->channel[operator_id].generator[generator_id].val |= action << (event * 2 + 12); + mcpwm->operator[operator_id].generator[generator_id].val &= ~(0x03 << (event * 2 + 12)); + mcpwm->operator[operator_id].generator[generator_id].val |= action << (event * 2 + 12); } } @@ -576,11 +589,11 @@ static inline void mcpwm_ll_generator_set_action_on_compare_event(mcpwm_dev_t *m mcpwm_timer_direction_t direction, int cmp_id, int action) { if (direction == MCPWM_TIMER_DIRECTION_UP) { // utea, uteb - mcpwm->channel[operator_id].generator[generator_id].val &= ~(0x03 << (cmp_id * 2 + 4)); - mcpwm->channel[operator_id].generator[generator_id].val |= action << (cmp_id * 2 + 4); + mcpwm->operator[operator_id].generator[generator_id].val &= ~(0x03 << (cmp_id * 2 + 4)); + mcpwm->operator[operator_id].generator[generator_id].val |= action << (cmp_id * 2 + 4); } else if (direction == MCPWM_TIMER_DIRECTION_DOWN) { // dtea, dteb - mcpwm->channel[operator_id].generator[generator_id].val &= ~(0x03 << (cmp_id * 2 + 16)); - mcpwm->channel[operator_id].generator[generator_id].val |= action << (cmp_id * 2 + 16); + mcpwm->operator[operator_id].generator[generator_id].val &= ~(0x03 << (cmp_id * 2 + 16)); + mcpwm->operator[operator_id].generator[generator_id].val |= action << (cmp_id * 2 + 16); } } @@ -588,58 +601,58 @@ static inline void mcpwm_ll_generator_set_action_on_trigger_event(mcpwm_dev_t *m mcpwm_timer_direction_t direction, int trig_id, int action) { if (direction == MCPWM_TIMER_DIRECTION_UP) { // ut0, ut1 - mcpwm->channel[operator_id].generator[generator_id].val &= ~(0x03 << (trig_id * 2 + 8)); - mcpwm->channel[operator_id].generator[generator_id].val |= action << (trig_id * 2 + 8); + mcpwm->operator[operator_id].generator[generator_id].val &= ~(0x03 << (trig_id * 2 + 8)); + mcpwm->operator[operator_id].generator[generator_id].val |= action << (trig_id * 2 + 8); } else if (direction == MCPWM_TIMER_DIRECTION_DOWN) { // dt0, dt1 - mcpwm->channel[operator_id].generator[generator_id].val &= ~(0x03 << (trig_id * 2 + 20)); - mcpwm->channel[operator_id].generator[generator_id].val |= action << (trig_id * 2 + 20); + mcpwm->operator[operator_id].generator[generator_id].val &= ~(0x03 << (trig_id * 2 + 20)); + mcpwm->operator[operator_id].generator[generator_id].val |= action << (trig_id * 2 + 20); } } static inline void mcpwm_ll_gen_trigger_noncontinue_force_action(mcpwm_dev_t *mcpwm, int operator_id, int generator_id) { if (generator_id == 0) { - mcpwm->channel[operator_id].gen_force.a_nciforce = ~mcpwm->channel[operator_id].gen_force.a_nciforce; + mcpwm->operator[operator_id].gen_force.gen_a_nciforce = ~mcpwm->operator[operator_id].gen_force.gen_a_nciforce; } else { - mcpwm->channel[operator_id].gen_force.b_nciforce = ~mcpwm->channel[operator_id].gen_force.b_nciforce; + mcpwm->operator[operator_id].gen_force.gen_b_nciforce = ~mcpwm->operator[operator_id].gen_force.gen_b_nciforce; } } static inline void mcpwm_ll_gen_disable_continue_force_action(mcpwm_dev_t *mcpwm, int operator_id, int generator_id) { - mcpwm->channel[operator_id].gen_force.cntu_force_upmethod = 0; // update force method immediately + mcpwm->operator[operator_id].gen_force.gen_cntuforce_upmethod = 0; // update force method immediately if (generator_id == 0) { - mcpwm->channel[operator_id].gen_force.a_cntuforce_mode = 0; + mcpwm->operator[operator_id].gen_force.gen_a_cntuforce_mode = 0; } else { - mcpwm->channel[operator_id].gen_force.b_cntuforce_mode = 0; + mcpwm->operator[operator_id].gen_force.gen_b_cntuforce_mode = 0; } } static inline void mcpwm_ll_gen_disable_noncontinue_force_action(mcpwm_dev_t *mcpwm, int operator_id, int generator_id) { if (generator_id == 0) { - mcpwm->channel[operator_id].gen_force.a_nciforce_mode = 0; + mcpwm->operator[operator_id].gen_force.gen_a_nciforce_mode = 0; } else { - mcpwm->channel[operator_id].gen_force.b_nciforce_mode = 0; + mcpwm->operator[operator_id].gen_force.gen_b_nciforce_mode = 0; } } static inline void mcpwm_ll_gen_set_continue_force_level(mcpwm_dev_t *mcpwm, int operator_id, int generator_id, int level) { - mcpwm->channel[operator_id].gen_force.cntu_force_upmethod = 0; // update force method immediately + mcpwm->operator[operator_id].gen_force.gen_cntuforce_upmethod = 0; // update force method immediately if (generator_id == 0) { - mcpwm->channel[operator_id].gen_force.a_cntuforce_mode = level + 1; + mcpwm->operator[operator_id].gen_force.gen_a_cntuforce_mode = level + 1; } else { - mcpwm->channel[operator_id].gen_force.b_cntuforce_mode = level + 1; + mcpwm->operator[operator_id].gen_force.gen_b_cntuforce_mode = level + 1; } } static inline void mcpwm_ll_gen_set_noncontinue_force_level(mcpwm_dev_t *mcpwm, int operator_id, int generator_id, int level) { if (generator_id == 0) { - mcpwm->channel[operator_id].gen_force.a_nciforce_mode = level + 1; + mcpwm->operator[operator_id].gen_force.gen_a_nciforce_mode = level + 1; } else { - mcpwm->channel[operator_id].gen_force.b_nciforce_mode = level + 1; + mcpwm->operator[operator_id].gen_force.gen_b_nciforce_mode = level + 1; } } @@ -648,116 +661,116 @@ static inline void mcpwm_ll_gen_set_noncontinue_force_level(mcpwm_dev_t *mcpwm, static inline void mcpwm_ll_deadtime_resolution_to_timer(mcpwm_dev_t *mcpwm, int operator_id, bool same) { // whether to make the resolution of dead time delay module the same to the timer connected with operator - mcpwm->channel[operator_id].db_cfg.clk_sel = same; + mcpwm->operator[operator_id].dt_cfg.dt_clk_sel = same; } static inline void mcpwm_ll_deadtime_red_select_generator(mcpwm_dev_t *mcpwm, int operator_id, int generator) { - mcpwm->channel[operator_id].db_cfg.red_insel = generator; + mcpwm->operator[operator_id].dt_cfg.dt_red_insel = generator; } static inline void mcpwm_ll_deadtime_fed_select_generator(mcpwm_dev_t *mcpwm, int operator_id, int generator) { - mcpwm->channel[operator_id].db_cfg.fed_insel = generator; + mcpwm->operator[operator_id].dt_cfg.dt_fed_insel = generator; } static inline void mcpwm_ll_deadtime_bypass_path(mcpwm_dev_t *mcpwm, int operator_id, int path, bool bypass) { if (bypass) { - mcpwm->channel[operator_id].db_cfg.val |= 1 << (path + 15); + mcpwm->operator[operator_id].dt_cfg.val |= 1 << (path + 15); } else { - mcpwm->channel[operator_id].db_cfg.val &= ~(1 << (path + 15)); + mcpwm->operator[operator_id].dt_cfg.val &= ~(1 << (path + 15)); } } static inline void mcpwm_ll_deadtime_invert_outpath(mcpwm_dev_t *mcpwm, int operator_id, int path, bool invert) { if (invert) { - mcpwm->channel[operator_id].db_cfg.val |= 1 << (path + 13); + mcpwm->operator[operator_id].dt_cfg.val |= 1 << (path + 13); } else { - mcpwm->channel[operator_id].db_cfg.val &= ~(1 << (path + 13)); + mcpwm->operator[operator_id].dt_cfg.val &= ~(1 << (path + 13)); } } static inline void mcpwm_ll_deadtime_swap_out_path(mcpwm_dev_t *mcpwm, int operator_id, int path, bool swap) { if (swap) { - mcpwm->channel[operator_id].db_cfg.val |= 1 << (path + 9); + mcpwm->operator[operator_id].dt_cfg.val |= 1 << (path + 9); } else { - mcpwm->channel[operator_id].db_cfg.val &= ~(1 << (path + 9)); + mcpwm->operator[operator_id].dt_cfg.val &= ~(1 << (path + 9)); } } static inline void mcpwm_ll_deadtime_enable_deb(mcpwm_dev_t *mcpwm, int operator_id, bool enable) { - mcpwm->channel[operator_id].db_cfg.deb_mode = enable; + mcpwm->operator[operator_id].dt_cfg.dt_deb_mode = enable; } static inline uint32_t mcpwm_ll_deadtime_get_switch_topology(mcpwm_dev_t *mcpwm, int operator_id) { - return (mcpwm->channel[operator_id].db_cfg.deb_mode << 8) | (mcpwm->channel[operator_id].db_cfg.b_outswap << 7) | - (mcpwm->channel[operator_id].db_cfg.a_outswap << 6) | (mcpwm->channel[operator_id].db_cfg.fed_insel << 5) | - (mcpwm->channel[operator_id].db_cfg.red_insel << 4) | (mcpwm->channel[operator_id].db_cfg.fed_outinvert << 3) | - (mcpwm->channel[operator_id].db_cfg.red_outinvert << 2) | (mcpwm->channel[operator_id].db_cfg.a_outbypass << 1) | - (mcpwm->channel[operator_id].db_cfg.b_outbypass << 0); + return (mcpwm->operator[operator_id].dt_cfg.dt_deb_mode << 8) | (mcpwm->operator[operator_id].dt_cfg.dt_b_outswap << 7) | + (mcpwm->operator[operator_id].dt_cfg.dt_a_outswap << 6) | (mcpwm->operator[operator_id].dt_cfg.dt_fed_insel << 5) | + (mcpwm->operator[operator_id].dt_cfg.dt_red_insel << 4) | (mcpwm->operator[operator_id].dt_cfg.dt_fed_outinvert << 3) | + (mcpwm->operator[operator_id].dt_cfg.dt_red_outinvert << 2) | (mcpwm->operator[operator_id].dt_cfg.dt_a_outbypass << 1) | + (mcpwm->operator[operator_id].dt_cfg.dt_b_outbypass << 0); } static inline void mcpwm_ll_deadtime_set_falling_delay(mcpwm_dev_t *mcpwm, int operator_id, uint32_t fed) { - mcpwm->channel[operator_id].db_fed_cfg.fed = fed - 1; + mcpwm->operator[operator_id].dt_fed_cfg.dt_fed = fed - 1; } static inline uint32_t mcpwm_ll_deadtime_get_falling_delay(mcpwm_dev_t *mcpwm, int operator_id) { - return mcpwm->channel[operator_id].db_fed_cfg.fed + 1; + return mcpwm->operator[operator_id].dt_fed_cfg.dt_fed + 1; } static inline void mcpwm_ll_deadtime_set_rising_delay(mcpwm_dev_t *mcpwm, int operator_id, uint32_t red) { - mcpwm->channel[operator_id].db_red_cfg.red = red - 1; + mcpwm->operator[operator_id].dt_red_cfg.dt_red = red - 1; } static inline uint32_t mcpwm_ll_deadtime_get_rising_delay(mcpwm_dev_t *mcpwm, int operator_id) { - return mcpwm->channel[operator_id].db_red_cfg.red + 1; + return mcpwm->operator[operator_id].dt_red_cfg.dt_red + 1; } static inline void mcpwm_ll_deadtime_update_delay_at_once(mcpwm_dev_t *mcpwm, int operator_id) { - mcpwm->channel[operator_id].db_cfg.fed_upmethod = 0; - mcpwm->channel[operator_id].db_cfg.red_upmethod = 0; + mcpwm->operator[operator_id].dt_cfg.dt_fed_upmethod = 0; + mcpwm->operator[operator_id].dt_cfg.dt_red_upmethod = 0; } static inline void mcpwm_ll_deadtime_enable_update_delay_on_tez(mcpwm_dev_t *mcpwm, int operator_id, bool enable) { if (enable) { - mcpwm->channel[operator_id].db_cfg.fed_upmethod |= 1 << 0; - mcpwm->channel[operator_id].db_cfg.red_upmethod |= 1 << 0; + mcpwm->operator[operator_id].dt_cfg.dt_fed_upmethod |= 1 << 0; + mcpwm->operator[operator_id].dt_cfg.dt_red_upmethod |= 1 << 0; } else { - mcpwm->channel[operator_id].db_cfg.fed_upmethod &= ~(1 << 0); - mcpwm->channel[operator_id].db_cfg.red_upmethod &= ~(1 << 0); + mcpwm->operator[operator_id].dt_cfg.dt_fed_upmethod &= ~(1 << 0); + mcpwm->operator[operator_id].dt_cfg.dt_red_upmethod &= ~(1 << 0); } } static inline void mcpwm_ll_deadtime_enable_update_delay_on_tep(mcpwm_dev_t *mcpwm, int operator_id, bool enable) { if (enable) { - mcpwm->channel[operator_id].db_cfg.fed_upmethod |= 1 << 1; - mcpwm->channel[operator_id].db_cfg.red_upmethod |= 1 << 1; + mcpwm->operator[operator_id].dt_cfg.dt_fed_upmethod |= 1 << 1; + mcpwm->operator[operator_id].dt_cfg.dt_red_upmethod |= 1 << 1; } else { - mcpwm->channel[operator_id].db_cfg.fed_upmethod &= ~(1 << 1); - mcpwm->channel[operator_id].db_cfg.red_upmethod &= ~(1 << 1); + mcpwm->operator[operator_id].dt_cfg.dt_fed_upmethod &= ~(1 << 1); + mcpwm->operator[operator_id].dt_cfg.dt_red_upmethod &= ~(1 << 1); } } static inline void mcpwm_ll_deadtime_enable_update_delay_on_sync(mcpwm_dev_t *mcpwm, int operator_id, bool enable) { if (enable) { - mcpwm->channel[operator_id].db_cfg.fed_upmethod |= 1 << 2; - mcpwm->channel[operator_id].db_cfg.red_upmethod |= 1 << 2; + mcpwm->operator[operator_id].dt_cfg.dt_fed_upmethod |= 1 << 2; + mcpwm->operator[operator_id].dt_cfg.dt_red_upmethod |= 1 << 2; } else { - mcpwm->channel[operator_id].db_cfg.fed_upmethod &= ~(1 << 2); - mcpwm->channel[operator_id].db_cfg.red_upmethod &= ~(1 << 2); + mcpwm->operator[operator_id].dt_cfg.dt_fed_upmethod &= ~(1 << 2); + mcpwm->operator[operator_id].dt_cfg.dt_red_upmethod &= ~(1 << 2); } } @@ -765,47 +778,47 @@ static inline void mcpwm_ll_deadtime_enable_update_delay_on_sync(mcpwm_dev_t *mc static inline void mcpwm_ll_carrier_enable(mcpwm_dev_t *mcpwm, int operator_id, bool enable) { - mcpwm->channel[operator_id].carrier_cfg.en = enable; + mcpwm->operator[operator_id].carrier_cfg.carrier_en = enable; } static inline void mcpwm_ll_carrier_set_prescale(mcpwm_dev_t *mcpwm, int operator_id, uint8_t prescale) { - mcpwm->channel[operator_id].carrier_cfg.prescale = prescale - 1; + mcpwm->operator[operator_id].carrier_cfg.carrier_prescale = prescale - 1; } static inline uint8_t mcpwm_ll_carrier_get_prescale(mcpwm_dev_t *mcpwm, int operator_id) { - return mcpwm->channel[operator_id].carrier_cfg.prescale + 1; + return mcpwm->operator[operator_id].carrier_cfg.carrier_prescale + 1; } static inline void mcpwm_ll_carrier_set_duty(mcpwm_dev_t *mcpwm, int operator_id, uint8_t carrier_duty) { - mcpwm->channel[operator_id].carrier_cfg.duty = carrier_duty; + mcpwm->operator[operator_id].carrier_cfg.carrier_duty = carrier_duty; } static inline uint8_t mcpwm_ll_carrier_get_duty(mcpwm_dev_t *mcpwm, int operator_id) { - return mcpwm->channel[operator_id].carrier_cfg.duty; + return mcpwm->operator[operator_id].carrier_cfg.carrier_duty; } static inline void mcpwm_ll_carrier_out_invert(mcpwm_dev_t *mcpwm, int operator_id, bool invert) { - mcpwm->channel[operator_id].carrier_cfg.out_invert = invert; + mcpwm->operator[operator_id].carrier_cfg.carrier_out_invert = invert; } static inline void mcpwm_ll_carrier_in_invert(mcpwm_dev_t *mcpwm, int operator_id, bool invert) { - mcpwm->channel[operator_id].carrier_cfg.in_invert = invert; + mcpwm->operator[operator_id].carrier_cfg.carrier_in_invert = invert; } static inline void mcpwm_ll_carrier_set_oneshot_width(mcpwm_dev_t *mcpwm, int operator_id, uint8_t pulse_width) { - mcpwm->channel[operator_id].carrier_cfg.oshtwth = pulse_width - 1; + mcpwm->operator[operator_id].carrier_cfg.carrier_oshtwth = pulse_width - 1; } static inline uint8_t mcpwm_ll_carrier_get_oneshot_width(mcpwm_dev_t *mcpwm, int operator_id) { - return mcpwm->channel[operator_id].carrier_cfg.oshtwth + 1; + return mcpwm->operator[operator_id].carrier_cfg.carrier_oshtwth + 1; } /********************* Fault detector registers *******************/ @@ -831,155 +844,155 @@ static inline void mcpwm_ll_fault_set_active_level(mcpwm_dev_t *mcpwm, int fault static inline void mcpwm_ll_fault_clear_ost(mcpwm_dev_t *mcpwm, int operator_id) { // a posedge can clear the ost fault status - mcpwm->channel[operator_id].tz_cfg1.clr_ost = 0; - mcpwm->channel[operator_id].tz_cfg1.clr_ost = 1; + mcpwm->operator[operator_id].fh_cfg1.fh_clr_ost = 0; + mcpwm->operator[operator_id].fh_cfg1.fh_clr_ost = 1; } static inline void mcpwm_ll_fault_enable_oneshot_mode(mcpwm_dev_t *mcpwm, int operator_id, int fault_sig, bool enable) { - mcpwm->channel[operator_id].tz_cfg0.val &= ~(1 << (7 - fault_sig)); - mcpwm->channel[operator_id].tz_cfg0.val |= (enable << (7 - fault_sig)); + mcpwm->operator[operator_id].fh_cfg0.val &= ~(1 << (7 - fault_sig)); + mcpwm->operator[operator_id].fh_cfg0.val |= (enable << (7 - fault_sig)); } static inline void mcpwm_ll_fault_enable_cbc_mode(mcpwm_dev_t *mcpwm, int operator_id, int fault_sig, bool enable) { - mcpwm->channel[operator_id].tz_cfg0.val &= ~(1 << (3 - fault_sig)); - mcpwm->channel[operator_id].tz_cfg0.val |= (enable << (3 - fault_sig)); + mcpwm->operator[operator_id].fh_cfg0.val &= ~(1 << (3 - fault_sig)); + mcpwm->operator[operator_id].fh_cfg0.val |= (enable << (3 - fault_sig)); } static inline void mcpwm_ll_fault_enable_cbc_refresh_on_tez(mcpwm_dev_t *mcpwm, int operator_id, bool enable) { if (enable) { - mcpwm->channel[operator_id].tz_cfg1.val |= 1 << 1; + mcpwm->operator[operator_id].fh_cfg1.val |= 1 << 1; } else { - mcpwm->channel[operator_id].tz_cfg1.val &= ~(1 << 1); + mcpwm->operator[operator_id].fh_cfg1.val &= ~(1 << 1); } } static inline void mcpwm_ll_fault_enable_cbc_refresh_on_tep(mcpwm_dev_t *mcpwm, int operator_id, bool enable) { if (enable) { - mcpwm->channel[operator_id].tz_cfg1.val |= 1 << 2; + mcpwm->operator[operator_id].fh_cfg1.val |= 1 << 2; } else { - mcpwm->channel[operator_id].tz_cfg1.val &= ~(1 << 2); + mcpwm->operator[operator_id].fh_cfg1.val &= ~(1 << 2); } } static inline void mcpwm_ll_fault_enable_sw_cbc(mcpwm_dev_t *mcpwm, int operator_id, bool enable) { - mcpwm->channel[operator_id].tz_cfg0.sw_cbc = enable; + mcpwm->operator[operator_id].fh_cfg0.fh_sw_cbc = enable; } static inline void mcpwm_ll_fault_enable_sw_oneshot(mcpwm_dev_t *mcpwm, int operator_id, bool enable) { - mcpwm->channel[operator_id].tz_cfg0.sw_ost = enable; + mcpwm->operator[operator_id].fh_cfg0.fh_sw_ost = enable; } static inline void mcpwm_ll_fault_trigger_sw_cbc(mcpwm_dev_t *mcpwm, int operator_id) { - mcpwm->channel[operator_id].tz_cfg1.force_cbc = ~mcpwm->channel[operator_id].tz_cfg1.force_cbc; + mcpwm->operator[operator_id].fh_cfg1.fh_force_cbc = ~mcpwm->operator[operator_id].fh_cfg1.fh_force_cbc; } static inline void mcpwm_ll_fault_trigger_sw_ost(mcpwm_dev_t *mcpwm, int operator_id) { - mcpwm->channel[operator_id].tz_cfg1.force_ost = ~mcpwm->channel[operator_id].tz_cfg1.force_ost; + mcpwm->operator[operator_id].fh_cfg1.fh_force_ost = ~mcpwm->operator[operator_id].fh_cfg1.fh_force_ost; } static inline void mcpwm_ll_generator_set_action_on_trip_event(mcpwm_dev_t *mcpwm, int operator_id, int generator_id, mcpwm_timer_direction_t direction, mcpwm_trip_type_t trip, int action) { if (direction == MCPWM_TIMER_DIRECTION_UP) { - mcpwm->channel[operator_id].tz_cfg0.val &= ~(0x03 << (8 + 8 * generator_id + 4 * trip + 2)); - mcpwm->channel[operator_id].tz_cfg0.val |= action << (8 + 8 * generator_id + 4 * trip + 2); + mcpwm->operator[operator_id].fh_cfg0.val &= ~(0x03 << (8 + 8 * generator_id + 4 * trip + 2)); + mcpwm->operator[operator_id].fh_cfg0.val |= action << (8 + 8 * generator_id + 4 * trip + 2); } else if (direction == MCPWM_TIMER_DIRECTION_DOWN) { - mcpwm->channel[operator_id].tz_cfg0.val &= ~(0x03 << (8 + 8 * generator_id + 4 * trip)); - mcpwm->channel[operator_id].tz_cfg0.val |= action << (8 + 8 * generator_id + 4 * trip); + mcpwm->operator[operator_id].fh_cfg0.val &= ~(0x03 << (8 + 8 * generator_id + 4 * trip)); + mcpwm->operator[operator_id].fh_cfg0.val |= action << (8 + 8 * generator_id + 4 * trip); } } static inline bool mcpwm_ll_fault_is_ost_on(mcpwm_dev_t *mcpwm, int op) { - return mcpwm->channel[op].tz_status.ost_on; + return mcpwm->operator[op].fh_status.fh_ost_on; } static inline bool mcpwm_ll_fault_is_cbc_on(mcpwm_dev_t *mcpwm, int op) { - return mcpwm->channel[op].tz_status.cbc_on; + return mcpwm->operator[op].fh_status.fh_cbc_on; } /********************* Capture registers *******************/ static inline void mcpwm_ll_capture_enable_timer(mcpwm_dev_t *mcpwm, bool enable) { - mcpwm->cap_timer_cfg.timer_en = enable; + mcpwm->cap_timer_cfg.cap_timer_en = enable; } static inline void mcpwm_ll_capture_enable_channel(mcpwm_dev_t *mcpwm, int channel, bool enable) { - mcpwm->cap_cfg_ch[channel].en = enable; + mcpwm->cap_chn_cfg[channel].capn_en = enable; } static inline void mcpwm_ll_capture_set_sync_phase_value(mcpwm_dev_t *mcpwm, uint32_t phase_value) { - mcpwm->cap_timer_phase = phase_value; + mcpwm->cap_timer_phase.cap_timer_phase = phase_value; } static inline uint32_t mcpwm_ll_capture_get_sync_phase_value(mcpwm_dev_t *mcpwm) { - return mcpwm->cap_timer_phase; + return mcpwm->cap_timer_phase.cap_timer_phase; } static inline void mcpwm_ll_capture_enable_timer_sync(mcpwm_dev_t *mcpwm, bool enable) { - mcpwm->cap_timer_cfg.synci_en = enable; + mcpwm->cap_timer_cfg.cap_synci_en = enable; } static inline void mcpwm_ll_capture_set_internal_timer_synchro(mcpwm_dev_t *mcpwm, int sync_out_timer) { - mcpwm->cap_timer_cfg.synci_sel = sync_out_timer + 1; + mcpwm->cap_timer_cfg.cap_synci_sel = sync_out_timer + 1; } static inline void mcpwm_ll_capture_set_external_synchro(mcpwm_dev_t *mcpwm, int extern_synchro) { - mcpwm->cap_timer_cfg.synci_sel = extern_synchro + 4; + mcpwm->cap_timer_cfg.cap_synci_sel = extern_synchro + 4; } static inline void mcpwm_ll_capture_trigger_sw_sync(mcpwm_dev_t *mcpwm) { - mcpwm->cap_timer_cfg.sync_sw = 1; // auto clear + mcpwm->cap_timer_cfg.cap_sync_sw = 1; // auto clear } static inline void mcpwm_ll_capture_enable_posedge(mcpwm_dev_t *mcpwm, int channel, bool enable) { if (enable) { - mcpwm->cap_cfg_ch[channel].val |= 1 << 2; + mcpwm->cap_chn_cfg[channel].val |= 1 << 2; } else { - mcpwm->cap_cfg_ch[channel].val &= ~(1 << 2); + mcpwm->cap_chn_cfg[channel].val &= ~(1 << 2); } } static inline void mcpwm_ll_capture_enable_negedge(mcpwm_dev_t *mcpwm, int channel, bool enable) { if (enable) { - mcpwm->cap_cfg_ch[channel].val |= 1 << 1; + mcpwm->cap_chn_cfg[channel].val |= 1 << 1; } else { - mcpwm->cap_cfg_ch[channel].val &= ~(1 << 1); + mcpwm->cap_chn_cfg[channel].val &= ~(1 << 1); } } static inline void mcpwm_ll_invert_input(mcpwm_dev_t *mcpwm, int channel, bool invert) { - mcpwm->cap_cfg_ch[channel].in_invert = invert; + mcpwm->cap_chn_cfg[channel].capn_in_invert = invert; } static inline void mcpwm_ll_trigger_soft_capture(mcpwm_dev_t *mcpwm, int channel) { - mcpwm->cap_cfg_ch[channel].sw = 1; // auto clear + mcpwm->cap_chn_cfg[channel].capn_sw = 1; // auto clear } static inline uint32_t mcpwm_ll_capture_get_value(mcpwm_dev_t *mcpwm, int channel) { - return mcpwm->cap_val_ch[channel]; + return mcpwm->cap_chn[channel].capn_value; } static inline bool mcpwm_ll_capture_is_negedge(mcpwm_dev_t *mcpwm, int channel) @@ -989,12 +1002,12 @@ static inline bool mcpwm_ll_capture_is_negedge(mcpwm_dev_t *mcpwm, int channel) static inline void mcpwm_ll_capture_set_prescale(mcpwm_dev_t *mcpwm, int channel, uint32_t prescale) { - mcpwm->cap_cfg_ch[channel].prescale = prescale - 1; + mcpwm->cap_chn_cfg[channel].capn_prescale = prescale - 1; } static inline uint32_t mcpwm_ll_capture_get_prescale(mcpwm_dev_t *mcpwm, int channel) { - return mcpwm->cap_cfg_ch[channel].prescale + 1; + return mcpwm->cap_chn_cfg[channel].capn_prescale + 1; } #ifdef __cplusplus diff --git a/components/hal/esp32s3/include/hal/mcpwm_ll.h b/components/hal/esp32s3/include/hal/mcpwm_ll.h index 93f44e24707..8790aa42b81 100644 --- a/components/hal/esp32s3/include/hal/mcpwm_ll.h +++ b/components/hal/esp32s3/include/hal/mcpwm_ll.h @@ -41,20 +41,20 @@ extern "C" { /********************* Group registers *******************/ -// Set/Get group clock: PWM_clk = CLK_160M / (clk_cfg.prescale + 1) +// Set/Get group clock: PWM_clk = CLK_160M / (prescale + 1) static inline void mcpwm_ll_group_set_clock_prescale(mcpwm_dev_t *mcpwm, int pre_scale) { // In case the compiler optimise a 32bit instruction (e.g. s32i) into 8bit instruction (e.g. s8i, which is not allowed to access a register) // We take care of the "read-modify-write" procedure by ourselves. - typeof(mcpwm->clk_cfg) clkcfg = mcpwm->clk_cfg; - clkcfg.prescale = pre_scale - 1; + mcpwm_clk_cfg_reg_t clkcfg = mcpwm->clk_cfg; + clkcfg.clk_prescale = pre_scale - 1; mcpwm->clk_cfg = clkcfg; } static inline uint32_t mcpwm_ll_group_get_clock_prescale(mcpwm_dev_t *mcpwm) { - typeof(mcpwm->clk_cfg) clkcfg = mcpwm->clk_cfg; - return clkcfg.prescale + 1; + mcpwm_clk_cfg_reg_t clkcfg = mcpwm->clk_cfg; + return clkcfg.clk_prescale + 1; } static inline void mcpwm_ll_group_enable_shadow_mode(mcpwm_dev_t *mcpwm) @@ -272,23 +272,23 @@ static inline void mcpwm_ll_timer_set_clock_prescale(mcpwm_dev_t *mcpwm, int tim { // In case the compiler optimise a 32bit instruction (e.g. s32i) into 8bit instruction (e.g. s8i, which is not allowed to access a register) // We take care of the "read-modify-write" procedure by ourselves. - typeof(mcpwm->timer[timer_id].period) period = mcpwm->timer[timer_id].period; - period.prescale = prescale - 1; - mcpwm->timer[timer_id].period = period; + mcpwm_timer_cfg0_reg_t cfg0 = mcpwm->timer[timer_id].timer_cfg0; + cfg0.timer_prescale = prescale - 1; + mcpwm->timer[timer_id].timer_cfg0 = cfg0; } static inline uint32_t mcpwm_ll_timer_get_clock_prescale(mcpwm_dev_t *mcpwm, int timer_id) { - typeof(mcpwm->timer[timer_id].period) period = mcpwm->timer[timer_id].period; - return period.prescale + 1; + mcpwm_timer_cfg0_reg_t cfg0 = mcpwm->timer[timer_id].timer_cfg0; + return cfg0.timer_prescale + 1; } static inline void mcpwm_ll_timer_set_peak(mcpwm_dev_t *mcpwm, int timer_id, uint32_t peak, bool symmetric) { if (!symmetric) { // in asymmetric mode, period = [0,peak-1] - mcpwm->timer[timer_id].period.period = peak - 1; + mcpwm->timer[timer_id].timer_cfg0.timer_period = peak - 1; } else { // in symmetric mode, period = [0,peak-1] + [peak,1] - mcpwm->timer[timer_id].period.period = peak; + mcpwm->timer[timer_id].timer_cfg0.timer_period = peak; } } @@ -296,32 +296,32 @@ static inline uint32_t mcpwm_ll_timer_get_peak(mcpwm_dev_t *mcpwm, int timer_id, { // asymmetric mode if (!symmetric) { - return mcpwm->timer[timer_id].period.period + 1; + return mcpwm->timer[timer_id].timer_cfg0.timer_period + 1; } // symmetric mode - return mcpwm->timer[timer_id].period.period; + return mcpwm->timer[timer_id].timer_cfg0.timer_period; } static inline void mcpwm_ll_timer_update_period_at_once(mcpwm_dev_t *mcpwm, int timer_id) { - mcpwm->timer[timer_id].period.upmethod = 0; + mcpwm->timer[timer_id].timer_cfg0.timer_period_upmethod = 0; } static inline void mcpwm_ll_timer_enable_update_period_on_tez(mcpwm_dev_t *mcpwm, int timer_id, bool enable) { if (enable) { - mcpwm->timer[timer_id].period.upmethod |= 0x01; + mcpwm->timer[timer_id].timer_cfg0.timer_period_upmethod |= 0x01; } else { - mcpwm->timer[timer_id].period.upmethod &= ~0x01; + mcpwm->timer[timer_id].timer_cfg0.timer_period_upmethod &= ~0x01; } } static inline void mcpwm_ll_timer_enable_update_period_on_sync(mcpwm_dev_t *mcpwm, int timer_id, bool enable) { if (enable) { - mcpwm->timer[timer_id].period.upmethod |= 0x02; + mcpwm->timer[timer_id].timer_cfg0.timer_period_upmethod |= 0x02; } else { - mcpwm->timer[timer_id].period.upmethod &= ~0x02; + mcpwm->timer[timer_id].timer_cfg0.timer_period_upmethod &= ~0x02; } } @@ -329,23 +329,23 @@ static inline void mcpwm_ll_timer_set_count_mode(mcpwm_dev_t *mcpwm, int timer_i { switch (mode) { case MCPWM_TIMER_COUNT_MODE_PAUSE: - mcpwm->timer[timer_id].mode.mode = 0; + mcpwm->timer[timer_id].timer_cfg1.timer_mod = 0; break; case MCPWM_TIMER_COUNT_MODE_UP: - mcpwm->timer[timer_id].mode.mode = 1; + mcpwm->timer[timer_id].timer_cfg1.timer_mod = 1; break; case MCPWM_TIMER_COUNT_MODE_DOWN: - mcpwm->timer[timer_id].mode.mode = 2; + mcpwm->timer[timer_id].timer_cfg1.timer_mod = 2; break; case MCPWM_TIMER_COUNT_MODE_UP_DOWN: - mcpwm->timer[timer_id].mode.mode = 3; + mcpwm->timer[timer_id].timer_cfg1.timer_mod = 3; break; } } static inline mcpwm_timer_count_mode_t mcpwm_ll_timer_get_count_mode(mcpwm_dev_t *mcpwm, int timer_id) { - switch (mcpwm->timer[timer_id].mode.mode) { + switch (mcpwm->timer[timer_id].timer_cfg1.timer_mod) { case 0: return MCPWM_TIMER_COUNT_MODE_PAUSE; case 1: @@ -354,6 +354,9 @@ static inline mcpwm_timer_count_mode_t mcpwm_ll_timer_get_count_mode(mcpwm_dev_t return MCPWM_TIMER_COUNT_MODE_DOWN; case 3: return MCPWM_TIMER_COUNT_MODE_UP_DOWN; + default: + HAL_ASSERT(false && "unknown count mode"); + return mcpwm->timer[timer_id].timer_cfg1.timer_mod; } } @@ -361,19 +364,19 @@ static inline void mcpwm_ll_timer_set_execute_command(mcpwm_dev_t *mcpwm, int ti { switch (cmd) { case MCPWM_TIMER_STOP_AT_ZERO: - mcpwm->timer[timer_id].mode.start = 0; + mcpwm->timer[timer_id].timer_cfg1.timer_start = 0; break; case MCPWM_TIMER_STOP_AT_PEAK: - mcpwm->timer[timer_id].mode.start = 1; + mcpwm->timer[timer_id].timer_cfg1.timer_start = 1; break; case MCPWM_TIMER_START_NO_STOP: - mcpwm->timer[timer_id].mode.start = 2; + mcpwm->timer[timer_id].timer_cfg1.timer_start = 2; break; case MCPWM_TIMER_START_STOP_AT_ZERO: - mcpwm->timer[timer_id].mode.start = 3; + mcpwm->timer[timer_id].timer_cfg1.timer_start = 3; break; case MCPWM_TIMER_START_STOP_AT_PEAK: - mcpwm->timer[timer_id].mode.start = 4; + mcpwm->timer[timer_id].timer_cfg1.timer_start = 4; break; } } @@ -382,62 +385,62 @@ static inline uint32_t mcpwm_ll_timer_get_count_value(mcpwm_dev_t *mcpwm, int ti { // status.value saves the "next count value", so need an extra round up here to get the current count value according to count mode // timer is paused - if (mcpwm->timer[timer_id].mode.mode == 0) { - return mcpwm->timer[timer_id].status.value; + if (mcpwm->timer[timer_id].timer_cfg1.timer_mod == 0) { + return mcpwm->timer[timer_id].timer_status.timer_value; } - if (mcpwm->timer[timer_id].status.direction) { // down direction - return (mcpwm->timer[timer_id].status.value + 1) % (mcpwm->timer[timer_id].period.period + 1); + if (mcpwm->timer[timer_id].timer_status.timer_direction) { // down direction + return (mcpwm->timer[timer_id].timer_status.timer_value + 1) % (mcpwm->timer[timer_id].timer_cfg0.timer_period + 1); } // up direction - return (mcpwm->timer[timer_id].status.value + mcpwm->timer[timer_id].period.period) % (mcpwm->timer[timer_id].period.period + 1); + return (mcpwm->timer[timer_id].timer_status.timer_value + mcpwm->timer[timer_id].timer_cfg0.timer_period) % (mcpwm->timer[timer_id].timer_cfg0.timer_period + 1); } static inline mcpwm_timer_direction_t mcpwm_ll_timer_get_count_direction(mcpwm_dev_t *mcpwm, int timer_id) { - return mcpwm->timer[timer_id].status.direction ? MCPWM_TIMER_DIRECTION_DOWN : MCPWM_TIMER_DIRECTION_UP; + return mcpwm->timer[timer_id].timer_status.timer_direction ? MCPWM_TIMER_DIRECTION_DOWN : MCPWM_TIMER_DIRECTION_UP; } static inline void mcpwm_ll_timer_enable_sync_input(mcpwm_dev_t *mcpwm, int timer_id, bool enable) { - mcpwm->timer[timer_id].sync.in_en = enable; + mcpwm->timer[timer_id].timer_sync.timer_synci_en = enable; } static inline void mcpwm_ll_timer_sync_out_penetrate(mcpwm_dev_t *mcpwm, int timer_id) { // sync_out is selected to sync_in - mcpwm->timer[timer_id].sync.out_sel = 0; + mcpwm->timer[timer_id].timer_sync.timer_synco_sel = 0; } static inline void mcpwm_ll_timer_sync_out_on_timer_event(mcpwm_dev_t *mcpwm, int timer_id, mcpwm_timer_event_t event) { if (event == MCPWM_TIMER_EVENT_ZERO) { - mcpwm->timer[timer_id].sync.out_sel = 1; + mcpwm->timer[timer_id].timer_sync.timer_synco_sel = 1; } else if (event == MCPWM_TIMER_EVENT_PEAK) { - mcpwm->timer[timer_id].sync.out_sel = 2; + mcpwm->timer[timer_id].timer_sync.timer_synco_sel = 2; } else { - HAL_ASSERT(false); + HAL_ASSERT(false && "unknown sync out event"); } } static inline void mcpwm_ll_timer_disable_sync_out(mcpwm_dev_t *mcpwm, int timer_id) { // sync_out will always be zero - mcpwm->timer[timer_id].sync.out_sel = 3; + mcpwm->timer[timer_id].timer_sync.timer_synco_sel = 3; } static inline void mcpwm_ll_timer_trigger_soft_sync(mcpwm_dev_t *mcpwm, int timer_id) { - mcpwm->timer[timer_id].sync.sync_sw = ~mcpwm->timer[timer_id].sync.sync_sw; + mcpwm->timer[timer_id].timer_sync.timer_sync_sw = ~mcpwm->timer[timer_id].timer_sync.timer_sync_sw; } static inline void mcpwm_ll_timer_set_sync_phase_value(mcpwm_dev_t *mcpwm, int timer_id, uint32_t phase_value) { - mcpwm->timer[timer_id].sync.timer_phase = phase_value; + mcpwm->timer[timer_id].timer_sync.timer_phase = phase_value; } static inline void mcpwm_ll_timer_set_sync_phase_direction(mcpwm_dev_t *mcpwm, int timer_id, mcpwm_timer_direction_t direction) { - mcpwm->timer[timer_id].sync.phase_direct = direction; + mcpwm->timer[timer_id].timer_sync.timer_phase_direction = direction; } static inline void mcpwm_ll_timer_set_gpio_synchro(mcpwm_dev_t *mcpwm, int timer, int gpio_sync_id) @@ -477,117 +480,117 @@ static inline void mcpwm_ll_operator_flush_shadow(mcpwm_dev_t *mcpwm, int operat static inline void mcpwm_ll_operator_select_timer(mcpwm_dev_t *mcpwm, int operator_id, int timer_id) { if (operator_id == 0) { - mcpwm->timer_sel.operator0_sel = timer_id; + mcpwm->operator_timersel.operator0_timersel = timer_id; } else if (operator_id == 1) { - mcpwm->timer_sel.operator1_sel = timer_id; + mcpwm->operator_timersel.operator1_timersel = timer_id; } else { - mcpwm->timer_sel.operator2_sel = timer_id; + mcpwm->operator_timersel.operator2_timersel = timer_id; } } static inline void mcpwm_ll_operator_update_compare_at_once(mcpwm_dev_t *mcpwm, int operator_id, int compare_id) { - mcpwm->channel[operator_id].cmpr_cfg.val &= ~(0x0F << (4 * compare_id)); + mcpwm->operator[operator_id].gen_stmp_cfg.val &= ~(0x0F << (4 * compare_id)); } static inline void mcpwm_ll_operator_enable_update_compare_on_tez(mcpwm_dev_t *mcpwm, int operator_id, int compare_id, bool enable) { if (enable) { - mcpwm->channel[operator_id].cmpr_cfg.val |= (1 << 0) << (4 * compare_id); + mcpwm->operator[operator_id].gen_stmp_cfg.val |= (1 << 0) << (4 * compare_id); } else { - mcpwm->channel[operator_id].cmpr_cfg.val &= ~((1 << 0) << (4 * compare_id)); + mcpwm->operator[operator_id].gen_stmp_cfg.val &= ~((1 << 0) << (4 * compare_id)); } } static inline void mcpwm_ll_operator_enable_update_compare_on_tep(mcpwm_dev_t *mcpwm, int operator_id, int compare_id, bool enable) { if (enable) { - mcpwm->channel[operator_id].cmpr_cfg.val |= (1 << 1) << (4 * compare_id); + mcpwm->operator[operator_id].gen_stmp_cfg.val |= (1 << 1) << (4 * compare_id); } else { - mcpwm->channel[operator_id].cmpr_cfg.val &= ~((1 << 1) << (4 * compare_id)); + mcpwm->operator[operator_id].gen_stmp_cfg.val &= ~((1 << 1) << (4 * compare_id)); } } static inline void mcpwm_ll_operator_enable_update_compare_on_sync(mcpwm_dev_t *mcpwm, int operator_id, int compare_id, bool enable) { if (enable) { - mcpwm->channel[operator_id].cmpr_cfg.val |= (1 << 2) << (4 * compare_id); + mcpwm->operator[operator_id].gen_stmp_cfg.val |= (1 << 2) << (4 * compare_id); } else { - mcpwm->channel[operator_id].cmpr_cfg.val &= ~((1 << 2) << (4 * compare_id)); + mcpwm->operator[operator_id].gen_stmp_cfg.val &= ~((1 << 2) << (4 * compare_id)); } } static inline void mcpwm_ll_operator_set_compare_value(mcpwm_dev_t *mcpwm, int operator_id, int compare_id, uint32_t compare_value) { - mcpwm->channel[operator_id].cmpr_value[compare_id].cmpr_val = compare_value; + mcpwm->operator[operator_id].timestamp[compare_id].gen = compare_value; } static inline uint32_t mcpwm_ll_operator_get_compare_value(mcpwm_dev_t *mcpwm, int operator_id, int compare_id) { - return mcpwm->channel[operator_id].cmpr_value[compare_id].cmpr_val; + return mcpwm->operator[operator_id].timestamp[compare_id].gen; } static inline void mcpwm_ll_operator_update_action_at_once(mcpwm_dev_t *mcpwm, int operator_id) { - mcpwm->channel[operator_id].gen_cfg0.upmethod = 0; + mcpwm->operator[operator_id].gen_cfg0.gen_cfg_upmethod = 0; } static inline void mcpwm_ll_operator_enable_update_action_on_tez(mcpwm_dev_t *mcpwm, int operator_id, bool enable) { if (enable) { - mcpwm->channel[operator_id].gen_cfg0.upmethod |= 1 << 0; + mcpwm->operator[operator_id].gen_cfg0.gen_cfg_upmethod |= 1 << 0; } else { - mcpwm->channel[operator_id].gen_cfg0.upmethod &= ~(1 << 0); + mcpwm->operator[operator_id].gen_cfg0.gen_cfg_upmethod &= ~(1 << 0); } } static inline void mcpwm_ll_operator_enable_update_action_on_tep(mcpwm_dev_t *mcpwm, int operator_id, bool enable) { if (enable) { - mcpwm->channel[operator_id].gen_cfg0.upmethod |= 1 << 1; + mcpwm->operator[operator_id].gen_cfg0.gen_cfg_upmethod |= 1 << 1; } else { - mcpwm->channel[operator_id].gen_cfg0.upmethod &= ~(1 << 1); + mcpwm->operator[operator_id].gen_cfg0.gen_cfg_upmethod &= ~(1 << 1); } } static inline void mcpwm_ll_operator_enable_update_action_on_sync(mcpwm_dev_t *mcpwm, int operator_id, bool enable) { if (enable) { - mcpwm->channel[operator_id].gen_cfg0.upmethod |= 1 << 2; + mcpwm->operator[operator_id].gen_cfg0.gen_cfg_upmethod |= 1 << 2; } else { - mcpwm->channel[operator_id].gen_cfg0.upmethod &= ~(1 << 2); + mcpwm->operator[operator_id].gen_cfg0.gen_cfg_upmethod &= ~(1 << 2); } } static inline void mcpwm_ll_operator_set_trigger_gpio_fault(mcpwm_dev_t *mcpwm, int operator_id, int trig_id, int fault_id) { - mcpwm->channel[operator_id].gen_cfg0.val &= ~(0x07 << (4 + 3 * trig_id)); - mcpwm->channel[operator_id].gen_cfg0.val |= (fault_id << (4 + 3 * trig_id)); + mcpwm->operator[operator_id].gen_cfg0.val &= ~(0x07 << (4 + 3 * trig_id)); + mcpwm->operator[operator_id].gen_cfg0.val |= (fault_id << (4 + 3 * trig_id)); } static inline void mcpwm_ll_operator_set_trigger_timer_sync(mcpwm_dev_t *mcpwm, int operator_id, int trig_id) { // the timer here is not selectable, must be the one connected with the operator - mcpwm->channel[operator_id].gen_cfg0.val &= ~(0x07 << (4 + 3 * trig_id)); - mcpwm->channel[operator_id].gen_cfg0.val |= (3 << (4 + 3 * trig_id)); + mcpwm->operator[operator_id].gen_cfg0.val &= ~(0x07 << (4 + 3 * trig_id)); + mcpwm->operator[operator_id].gen_cfg0.val |= (3 << (4 + 3 * trig_id)); } /********************* Generator registers *******************/ static inline void mcpwm_ll_generator_reset_actions(mcpwm_dev_t *mcpwm, int operator_id, int generator_id) { - mcpwm->channel[operator_id].generator[generator_id].val = 0; + mcpwm->operator[operator_id].generator[generator_id].val = 0; } static inline void mcpwm_ll_generator_set_action_on_timer_event(mcpwm_dev_t *mcpwm, int operator_id, int generator_id, mcpwm_timer_direction_t direction, mcpwm_timer_event_t event, mcpwm_generator_action_t action) { if (direction == MCPWM_TIMER_DIRECTION_UP) { // utez, utep - mcpwm->channel[operator_id].generator[generator_id].val &= ~(0x03 << (event * 2)); - mcpwm->channel[operator_id].generator[generator_id].val |= action << (event * 2); + mcpwm->operator[operator_id].generator[generator_id].val &= ~(0x03 << (event * 2)); + mcpwm->operator[operator_id].generator[generator_id].val |= action << (event * 2); } else if (direction == MCPWM_TIMER_DIRECTION_DOWN) { // dtez, dtep - mcpwm->channel[operator_id].generator[generator_id].val &= ~(0x03 << (event * 2 + 12)); - mcpwm->channel[operator_id].generator[generator_id].val |= action << (event * 2 + 12); + mcpwm->operator[operator_id].generator[generator_id].val &= ~(0x03 << (event * 2 + 12)); + mcpwm->operator[operator_id].generator[generator_id].val |= action << (event * 2 + 12); } } @@ -595,11 +598,11 @@ static inline void mcpwm_ll_generator_set_action_on_compare_event(mcpwm_dev_t *m mcpwm_timer_direction_t direction, int cmp_id, int action) { if (direction == MCPWM_TIMER_DIRECTION_UP) { // utea, uteb - mcpwm->channel[operator_id].generator[generator_id].val &= ~(0x03 << (cmp_id * 2 + 4)); - mcpwm->channel[operator_id].generator[generator_id].val |= action << (cmp_id * 2 + 4); + mcpwm->operator[operator_id].generator[generator_id].val &= ~(0x03 << (cmp_id * 2 + 4)); + mcpwm->operator[operator_id].generator[generator_id].val |= action << (cmp_id * 2 + 4); } else if (direction == MCPWM_TIMER_DIRECTION_DOWN) { // dtea, dteb - mcpwm->channel[operator_id].generator[generator_id].val &= ~(0x03 << (cmp_id * 2 + 16)); - mcpwm->channel[operator_id].generator[generator_id].val |= action << (cmp_id * 2 + 16); + mcpwm->operator[operator_id].generator[generator_id].val &= ~(0x03 << (cmp_id * 2 + 16)); + mcpwm->operator[operator_id].generator[generator_id].val |= action << (cmp_id * 2 + 16); } } @@ -607,58 +610,58 @@ static inline void mcpwm_ll_generator_set_action_on_trigger_event(mcpwm_dev_t *m mcpwm_timer_direction_t direction, int trig_id, int action) { if (direction == MCPWM_TIMER_DIRECTION_UP) { // ut0, ut1 - mcpwm->channel[operator_id].generator[generator_id].val &= ~(0x03 << (trig_id * 2 + 8)); - mcpwm->channel[operator_id].generator[generator_id].val |= action << (trig_id * 2 + 8); + mcpwm->operator[operator_id].generator[generator_id].val &= ~(0x03 << (trig_id * 2 + 8)); + mcpwm->operator[operator_id].generator[generator_id].val |= action << (trig_id * 2 + 8); } else if (direction == MCPWM_TIMER_DIRECTION_DOWN) { // dt0, dt1 - mcpwm->channel[operator_id].generator[generator_id].val &= ~(0x03 << (trig_id * 2 + 20)); - mcpwm->channel[operator_id].generator[generator_id].val |= action << (trig_id * 2 + 20); + mcpwm->operator[operator_id].generator[generator_id].val &= ~(0x03 << (trig_id * 2 + 20)); + mcpwm->operator[operator_id].generator[generator_id].val |= action << (trig_id * 2 + 20); } } static inline void mcpwm_ll_gen_trigger_noncontinue_force_action(mcpwm_dev_t *mcpwm, int operator_id, int generator_id) { if (generator_id == 0) { - mcpwm->channel[operator_id].gen_force.a_nciforce = ~mcpwm->channel[operator_id].gen_force.a_nciforce; + mcpwm->operator[operator_id].gen_force.gen_a_nciforce = ~mcpwm->operator[operator_id].gen_force.gen_a_nciforce; } else { - mcpwm->channel[operator_id].gen_force.b_nciforce = ~mcpwm->channel[operator_id].gen_force.b_nciforce; + mcpwm->operator[operator_id].gen_force.gen_b_nciforce = ~mcpwm->operator[operator_id].gen_force.gen_b_nciforce; } } static inline void mcpwm_ll_gen_disable_continue_force_action(mcpwm_dev_t *mcpwm, int operator_id, int generator_id) { - mcpwm->channel[operator_id].gen_force.cntu_force_upmethod = 0; // update force method immediately + mcpwm->operator[operator_id].gen_force.gen_cntuforce_upmethod = 0; // update force method immediately if (generator_id == 0) { - mcpwm->channel[operator_id].gen_force.a_cntuforce_mode = 0; + mcpwm->operator[operator_id].gen_force.gen_a_cntuforce_mode = 0; } else { - mcpwm->channel[operator_id].gen_force.b_cntuforce_mode = 0; + mcpwm->operator[operator_id].gen_force.gen_b_cntuforce_mode = 0; } } static inline void mcpwm_ll_gen_disable_noncontinue_force_action(mcpwm_dev_t *mcpwm, int operator_id, int generator_id) { if (generator_id == 0) { - mcpwm->channel[operator_id].gen_force.a_nciforce_mode = 0; + mcpwm->operator[operator_id].gen_force.gen_a_nciforce_mode = 0; } else { - mcpwm->channel[operator_id].gen_force.b_nciforce_mode = 0; + mcpwm->operator[operator_id].gen_force.gen_b_nciforce_mode = 0; } } static inline void mcpwm_ll_gen_set_continue_force_level(mcpwm_dev_t *mcpwm, int operator_id, int generator_id, int level) { - mcpwm->channel[operator_id].gen_force.cntu_force_upmethod = 0; // update force method immediately + mcpwm->operator[operator_id].gen_force.gen_cntuforce_upmethod = 0; // update force method immediately if (generator_id == 0) { - mcpwm->channel[operator_id].gen_force.a_cntuforce_mode = level + 1; + mcpwm->operator[operator_id].gen_force.gen_a_cntuforce_mode = level + 1; } else { - mcpwm->channel[operator_id].gen_force.b_cntuforce_mode = level + 1; + mcpwm->operator[operator_id].gen_force.gen_b_cntuforce_mode = level + 1; } } static inline void mcpwm_ll_gen_set_noncontinue_force_level(mcpwm_dev_t *mcpwm, int operator_id, int generator_id, int level) { if (generator_id == 0) { - mcpwm->channel[operator_id].gen_force.a_nciforce_mode = level + 1; + mcpwm->operator[operator_id].gen_force.gen_a_nciforce_mode = level + 1; } else { - mcpwm->channel[operator_id].gen_force.b_nciforce_mode = level + 1; + mcpwm->operator[operator_id].gen_force.gen_b_nciforce_mode = level + 1; } } @@ -667,116 +670,116 @@ static inline void mcpwm_ll_gen_set_noncontinue_force_level(mcpwm_dev_t *mcpwm, static inline void mcpwm_ll_deadtime_resolution_to_timer(mcpwm_dev_t *mcpwm, int operator_id, bool same) { // whether to make the resolution of dead time delay module the same to the timer connected with operator - mcpwm->channel[operator_id].db_cfg.clk_sel = same; + mcpwm->operator[operator_id].dt_cfg.dt_clk_sel = same; } static inline void mcpwm_ll_deadtime_red_select_generator(mcpwm_dev_t *mcpwm, int operator_id, int generator) { - mcpwm->channel[operator_id].db_cfg.red_insel = generator; + mcpwm->operator[operator_id].dt_cfg.dt_red_insel = generator; } static inline void mcpwm_ll_deadtime_fed_select_generator(mcpwm_dev_t *mcpwm, int operator_id, int generator) { - mcpwm->channel[operator_id].db_cfg.fed_insel = generator; + mcpwm->operator[operator_id].dt_cfg.dt_fed_insel = generator; } static inline void mcpwm_ll_deadtime_bypass_path(mcpwm_dev_t *mcpwm, int operator_id, int path, bool bypass) { if (bypass) { - mcpwm->channel[operator_id].db_cfg.val |= 1 << (path + 15); + mcpwm->operator[operator_id].dt_cfg.val |= 1 << (path + 15); } else { - mcpwm->channel[operator_id].db_cfg.val &= ~(1 << (path + 15)); + mcpwm->operator[operator_id].dt_cfg.val &= ~(1 << (path + 15)); } } static inline void mcpwm_ll_deadtime_invert_outpath(mcpwm_dev_t *mcpwm, int operator_id, int path, bool invert) { if (invert) { - mcpwm->channel[operator_id].db_cfg.val |= 1 << (path + 13); + mcpwm->operator[operator_id].dt_cfg.val |= 1 << (path + 13); } else { - mcpwm->channel[operator_id].db_cfg.val &= ~(1 << (path + 13)); + mcpwm->operator[operator_id].dt_cfg.val &= ~(1 << (path + 13)); } } static inline void mcpwm_ll_deadtime_swap_out_path(mcpwm_dev_t *mcpwm, int operator_id, int path, bool swap) { if (swap) { - mcpwm->channel[operator_id].db_cfg.val |= 1 << (path + 9); + mcpwm->operator[operator_id].dt_cfg.val |= 1 << (path + 9); } else { - mcpwm->channel[operator_id].db_cfg.val &= ~(1 << (path + 9)); + mcpwm->operator[operator_id].dt_cfg.val &= ~(1 << (path + 9)); } } static inline void mcpwm_ll_deadtime_enable_deb(mcpwm_dev_t *mcpwm, int operator_id, bool enable) { - mcpwm->channel[operator_id].db_cfg.deb_mode = enable; + mcpwm->operator[operator_id].dt_cfg.dt_deb_mode = enable; } static inline uint32_t mcpwm_ll_deadtime_get_switch_topology(mcpwm_dev_t *mcpwm, int operator_id) { - return (mcpwm->channel[operator_id].db_cfg.deb_mode << 8) | (mcpwm->channel[operator_id].db_cfg.b_outswap << 7) | - (mcpwm->channel[operator_id].db_cfg.a_outswap << 6) | (mcpwm->channel[operator_id].db_cfg.fed_insel << 5) | - (mcpwm->channel[operator_id].db_cfg.red_insel << 4) | (mcpwm->channel[operator_id].db_cfg.fed_outinvert << 3) | - (mcpwm->channel[operator_id].db_cfg.red_outinvert << 2) | (mcpwm->channel[operator_id].db_cfg.a_outbypass << 1) | - (mcpwm->channel[operator_id].db_cfg.b_outbypass << 0); + return (mcpwm->operator[operator_id].dt_cfg.dt_deb_mode << 8) | (mcpwm->operator[operator_id].dt_cfg.dt_b_outswap << 7) | + (mcpwm->operator[operator_id].dt_cfg.dt_a_outswap << 6) | (mcpwm->operator[operator_id].dt_cfg.dt_fed_insel << 5) | + (mcpwm->operator[operator_id].dt_cfg.dt_red_insel << 4) | (mcpwm->operator[operator_id].dt_cfg.dt_fed_outinvert << 3) | + (mcpwm->operator[operator_id].dt_cfg.dt_red_outinvert << 2) | (mcpwm->operator[operator_id].dt_cfg.dt_a_outbypass << 1) | + (mcpwm->operator[operator_id].dt_cfg.dt_b_outbypass << 0); } static inline void mcpwm_ll_deadtime_set_falling_delay(mcpwm_dev_t *mcpwm, int operator_id, uint32_t fed) { - mcpwm->channel[operator_id].db_fed_cfg.fed = fed - 1; + mcpwm->operator[operator_id].dt_fed_cfg.dt_fed = fed - 1; } static inline uint32_t mcpwm_ll_deadtime_get_falling_delay(mcpwm_dev_t *mcpwm, int operator_id) { - return mcpwm->channel[operator_id].db_fed_cfg.fed + 1; + return mcpwm->operator[operator_id].dt_fed_cfg.dt_fed + 1; } static inline void mcpwm_ll_deadtime_set_rising_delay(mcpwm_dev_t *mcpwm, int operator_id, uint32_t red) { - mcpwm->channel[operator_id].db_red_cfg.red = red - 1; + mcpwm->operator[operator_id].dt_red_cfg.dt_red = red - 1; } static inline uint32_t mcpwm_ll_deadtime_get_rising_delay(mcpwm_dev_t *mcpwm, int operator_id) { - return mcpwm->channel[operator_id].db_red_cfg.red + 1; + return mcpwm->operator[operator_id].dt_red_cfg.dt_red + 1; } static inline void mcpwm_ll_deadtime_update_delay_at_once(mcpwm_dev_t *mcpwm, int operator_id) { - mcpwm->channel[operator_id].db_cfg.fed_upmethod = 0; - mcpwm->channel[operator_id].db_cfg.red_upmethod = 0; + mcpwm->operator[operator_id].dt_cfg.dt_fed_upmethod = 0; + mcpwm->operator[operator_id].dt_cfg.dt_red_upmethod = 0; } static inline void mcpwm_ll_deadtime_enable_update_delay_on_tez(mcpwm_dev_t *mcpwm, int operator_id, bool enable) { if (enable) { - mcpwm->channel[operator_id].db_cfg.fed_upmethod |= 1 << 0; - mcpwm->channel[operator_id].db_cfg.red_upmethod |= 1 << 0; + mcpwm->operator[operator_id].dt_cfg.dt_fed_upmethod |= 1 << 0; + mcpwm->operator[operator_id].dt_cfg.dt_red_upmethod |= 1 << 0; } else { - mcpwm->channel[operator_id].db_cfg.fed_upmethod &= ~(1 << 0); - mcpwm->channel[operator_id].db_cfg.red_upmethod &= ~(1 << 0); + mcpwm->operator[operator_id].dt_cfg.dt_fed_upmethod &= ~(1 << 0); + mcpwm->operator[operator_id].dt_cfg.dt_red_upmethod &= ~(1 << 0); } } static inline void mcpwm_ll_deadtime_enable_update_delay_on_tep(mcpwm_dev_t *mcpwm, int operator_id, bool enable) { if (enable) { - mcpwm->channel[operator_id].db_cfg.fed_upmethod |= 1 << 1; - mcpwm->channel[operator_id].db_cfg.red_upmethod |= 1 << 1; + mcpwm->operator[operator_id].dt_cfg.dt_fed_upmethod |= 1 << 1; + mcpwm->operator[operator_id].dt_cfg.dt_red_upmethod |= 1 << 1; } else { - mcpwm->channel[operator_id].db_cfg.fed_upmethod &= ~(1 << 1); - mcpwm->channel[operator_id].db_cfg.red_upmethod &= ~(1 << 1); + mcpwm->operator[operator_id].dt_cfg.dt_fed_upmethod &= ~(1 << 1); + mcpwm->operator[operator_id].dt_cfg.dt_red_upmethod &= ~(1 << 1); } } static inline void mcpwm_ll_deadtime_enable_update_delay_on_sync(mcpwm_dev_t *mcpwm, int operator_id, bool enable) { if (enable) { - mcpwm->channel[operator_id].db_cfg.fed_upmethod |= 1 << 2; - mcpwm->channel[operator_id].db_cfg.red_upmethod |= 1 << 2; + mcpwm->operator[operator_id].dt_cfg.dt_fed_upmethod |= 1 << 2; + mcpwm->operator[operator_id].dt_cfg.dt_red_upmethod |= 1 << 2; } else { - mcpwm->channel[operator_id].db_cfg.fed_upmethod &= ~(1 << 2); - mcpwm->channel[operator_id].db_cfg.red_upmethod &= ~(1 << 2); + mcpwm->operator[operator_id].dt_cfg.dt_fed_upmethod &= ~(1 << 2); + mcpwm->operator[operator_id].dt_cfg.dt_red_upmethod &= ~(1 << 2); } } @@ -784,47 +787,47 @@ static inline void mcpwm_ll_deadtime_enable_update_delay_on_sync(mcpwm_dev_t *mc static inline void mcpwm_ll_carrier_enable(mcpwm_dev_t *mcpwm, int operator_id, bool enable) { - mcpwm->channel[operator_id].carrier_cfg.en = enable; + mcpwm->operator[operator_id].carrier_cfg.carrier_en = enable; } static inline void mcpwm_ll_carrier_set_prescale(mcpwm_dev_t *mcpwm, int operator_id, uint8_t prescale) { - mcpwm->channel[operator_id].carrier_cfg.prescale = prescale - 1; + mcpwm->operator[operator_id].carrier_cfg.carrier_prescale = prescale - 1; } static inline uint8_t mcpwm_ll_carrier_get_prescale(mcpwm_dev_t *mcpwm, int operator_id) { - return mcpwm->channel[operator_id].carrier_cfg.prescale + 1; + return mcpwm->operator[operator_id].carrier_cfg.carrier_prescale + 1; } static inline void mcpwm_ll_carrier_set_duty(mcpwm_dev_t *mcpwm, int operator_id, uint8_t carrier_duty) { - mcpwm->channel[operator_id].carrier_cfg.duty = carrier_duty; + mcpwm->operator[operator_id].carrier_cfg.carrier_duty = carrier_duty; } static inline uint8_t mcpwm_ll_carrier_get_duty(mcpwm_dev_t *mcpwm, int operator_id) { - return mcpwm->channel[operator_id].carrier_cfg.duty; + return mcpwm->operator[operator_id].carrier_cfg.carrier_duty; } static inline void mcpwm_ll_carrier_out_invert(mcpwm_dev_t *mcpwm, int operator_id, bool invert) { - mcpwm->channel[operator_id].carrier_cfg.out_invert = invert; + mcpwm->operator[operator_id].carrier_cfg.carrier_out_invert = invert; } static inline void mcpwm_ll_carrier_in_invert(mcpwm_dev_t *mcpwm, int operator_id, bool invert) { - mcpwm->channel[operator_id].carrier_cfg.in_invert = invert; + mcpwm->operator[operator_id].carrier_cfg.carrier_in_invert = invert; } static inline void mcpwm_ll_carrier_set_oneshot_width(mcpwm_dev_t *mcpwm, int operator_id, uint8_t pulse_width) { - mcpwm->channel[operator_id].carrier_cfg.oshtwth = pulse_width - 1; + mcpwm->operator[operator_id].carrier_cfg.carrier_oshtwth = pulse_width - 1; } static inline uint8_t mcpwm_ll_carrier_get_oneshot_width(mcpwm_dev_t *mcpwm, int operator_id) { - return mcpwm->channel[operator_id].carrier_cfg.oshtwth + 1; + return mcpwm->operator[operator_id].carrier_cfg.carrier_oshtwth + 1; } /********************* Fault detector registers *******************/ @@ -850,155 +853,155 @@ static inline void mcpwm_ll_fault_set_active_level(mcpwm_dev_t *mcpwm, int fault static inline void mcpwm_ll_fault_clear_ost(mcpwm_dev_t *mcpwm, int operator_id) { // a posedge can clear the ost fault status - mcpwm->channel[operator_id].tz_cfg1.clr_ost = 0; - mcpwm->channel[operator_id].tz_cfg1.clr_ost = 1; + mcpwm->operator[operator_id].fh_cfg1.fh_clr_ost = 0; + mcpwm->operator[operator_id].fh_cfg1.fh_clr_ost = 1; } static inline void mcpwm_ll_fault_enable_oneshot_mode(mcpwm_dev_t *mcpwm, int operator_id, int fault_sig, bool enable) { - mcpwm->channel[operator_id].tz_cfg0.val &= ~(1 << (7 - fault_sig)); - mcpwm->channel[operator_id].tz_cfg0.val |= (enable << (7 - fault_sig)); + mcpwm->operator[operator_id].fh_cfg0.val &= ~(1 << (7 - fault_sig)); + mcpwm->operator[operator_id].fh_cfg0.val |= (enable << (7 - fault_sig)); } static inline void mcpwm_ll_fault_enable_cbc_mode(mcpwm_dev_t *mcpwm, int operator_id, int fault_sig, bool enable) { - mcpwm->channel[operator_id].tz_cfg0.val &= ~(1 << (3 - fault_sig)); - mcpwm->channel[operator_id].tz_cfg0.val |= (enable << (3 - fault_sig)); + mcpwm->operator[operator_id].fh_cfg0.val &= ~(1 << (3 - fault_sig)); + mcpwm->operator[operator_id].fh_cfg0.val |= (enable << (3 - fault_sig)); } static inline void mcpwm_ll_fault_enable_cbc_refresh_on_tez(mcpwm_dev_t *mcpwm, int operator_id, bool enable) { if (enable) { - mcpwm->channel[operator_id].tz_cfg1.val |= 1 << 1; + mcpwm->operator[operator_id].fh_cfg1.val |= 1 << 1; } else { - mcpwm->channel[operator_id].tz_cfg1.val &= ~(1 << 1); + mcpwm->operator[operator_id].fh_cfg1.val &= ~(1 << 1); } } static inline void mcpwm_ll_fault_enable_cbc_refresh_on_tep(mcpwm_dev_t *mcpwm, int operator_id, bool enable) { if (enable) { - mcpwm->channel[operator_id].tz_cfg1.val |= 1 << 2; + mcpwm->operator[operator_id].fh_cfg1.val |= 1 << 2; } else { - mcpwm->channel[operator_id].tz_cfg1.val &= ~(1 << 2); + mcpwm->operator[operator_id].fh_cfg1.val &= ~(1 << 2); } } static inline void mcpwm_ll_fault_enable_sw_cbc(mcpwm_dev_t *mcpwm, int operator_id, bool enable) { - mcpwm->channel[operator_id].tz_cfg0.sw_cbc = enable; + mcpwm->operator[operator_id].fh_cfg0.fh_sw_cbc = enable; } static inline void mcpwm_ll_fault_enable_sw_oneshot(mcpwm_dev_t *mcpwm, int operator_id, bool enable) { - mcpwm->channel[operator_id].tz_cfg0.sw_ost = enable; + mcpwm->operator[operator_id].fh_cfg0.fh_sw_ost = enable; } static inline void mcpwm_ll_fault_trigger_sw_cbc(mcpwm_dev_t *mcpwm, int operator_id) { - mcpwm->channel[operator_id].tz_cfg1.force_cbc = ~mcpwm->channel[operator_id].tz_cfg1.force_cbc; + mcpwm->operator[operator_id].fh_cfg1.fh_force_cbc = ~mcpwm->operator[operator_id].fh_cfg1.fh_force_cbc; } static inline void mcpwm_ll_fault_trigger_sw_ost(mcpwm_dev_t *mcpwm, int operator_id) { - mcpwm->channel[operator_id].tz_cfg1.force_ost = ~mcpwm->channel[operator_id].tz_cfg1.force_ost; + mcpwm->operator[operator_id].fh_cfg1.fh_force_ost = ~mcpwm->operator[operator_id].fh_cfg1.fh_force_ost; } static inline void mcpwm_ll_generator_set_action_on_trip_event(mcpwm_dev_t *mcpwm, int operator_id, int generator_id, mcpwm_timer_direction_t direction, mcpwm_trip_type_t trip, int action) { if (direction == MCPWM_TIMER_DIRECTION_UP) { - mcpwm->channel[operator_id].tz_cfg0.val &= ~(0x03 << (8 + 8 * generator_id + 4 * trip + 2)); - mcpwm->channel[operator_id].tz_cfg0.val |= action << (8 + 8 * generator_id + 4 * trip + 2); + mcpwm->operator[operator_id].fh_cfg0.val &= ~(0x03 << (8 + 8 * generator_id + 4 * trip + 2)); + mcpwm->operator[operator_id].fh_cfg0.val |= action << (8 + 8 * generator_id + 4 * trip + 2); } else if (direction == MCPWM_TIMER_DIRECTION_DOWN) { - mcpwm->channel[operator_id].tz_cfg0.val &= ~(0x03 << (8 + 8 * generator_id + 4 * trip)); - mcpwm->channel[operator_id].tz_cfg0.val |= action << (8 + 8 * generator_id + 4 * trip); + mcpwm->operator[operator_id].fh_cfg0.val &= ~(0x03 << (8 + 8 * generator_id + 4 * trip)); + mcpwm->operator[operator_id].fh_cfg0.val |= action << (8 + 8 * generator_id + 4 * trip); } } static inline bool mcpwm_ll_fault_is_ost_on(mcpwm_dev_t *mcpwm, int op) { - return mcpwm->channel[op].tz_status.ost_on; + return mcpwm->operator[op].fh_status.fh_ost_on; } static inline bool mcpwm_ll_fault_is_cbc_on(mcpwm_dev_t *mcpwm, int op) { - return mcpwm->channel[op].tz_status.cbc_on; + return mcpwm->operator[op].fh_status.fh_cbc_on; } /********************* Capture registers *******************/ static inline void mcpwm_ll_capture_enable_timer(mcpwm_dev_t *mcpwm, bool enable) { - mcpwm->cap_timer_cfg.timer_en = enable; + mcpwm->cap_timer_cfg.cap_timer_en = enable; } static inline void mcpwm_ll_capture_enable_channel(mcpwm_dev_t *mcpwm, int channel, bool enable) { - mcpwm->cap_cfg_ch[channel].en = enable; + mcpwm->cap_chn_cfg[channel].capn_en = enable; } static inline void mcpwm_ll_capture_set_sync_phase_value(mcpwm_dev_t *mcpwm, uint32_t phase_value) { - mcpwm->cap_timer_phase = phase_value; + mcpwm->cap_timer_phase.cap_timer_phase = phase_value; } static inline uint32_t mcpwm_ll_capture_get_sync_phase_value(mcpwm_dev_t *mcpwm) { - return mcpwm->cap_timer_phase; + return mcpwm->cap_timer_phase.cap_timer_phase; } static inline void mcpwm_ll_capture_enable_timer_sync(mcpwm_dev_t *mcpwm, bool enable) { - mcpwm->cap_timer_cfg.synci_en = enable; + mcpwm->cap_timer_cfg.cap_synci_en = enable; } static inline void mcpwm_ll_capture_set_internal_timer_synchro(mcpwm_dev_t *mcpwm, int sync_out_timer) { - mcpwm->cap_timer_cfg.synci_sel = sync_out_timer + 1; + mcpwm->cap_timer_cfg.cap_synci_sel = sync_out_timer + 1; } static inline void mcpwm_ll_capture_set_external_synchro(mcpwm_dev_t *mcpwm, int extern_synchro) { - mcpwm->cap_timer_cfg.synci_sel = extern_synchro + 4; + mcpwm->cap_timer_cfg.cap_synci_sel = extern_synchro + 4; } static inline void mcpwm_ll_capture_trigger_sw_sync(mcpwm_dev_t *mcpwm) { - mcpwm->cap_timer_cfg.sync_sw = 1; // auto clear + mcpwm->cap_timer_cfg.cap_sync_sw = 1; // auto clear } static inline void mcpwm_ll_capture_enable_posedge(mcpwm_dev_t *mcpwm, int channel, bool enable) { if (enable) { - mcpwm->cap_cfg_ch[channel].val |= 1 << 2; + mcpwm->cap_chn_cfg[channel].val |= 1 << 2; } else { - mcpwm->cap_cfg_ch[channel].val &= ~(1 << 2); + mcpwm->cap_chn_cfg[channel].val &= ~(1 << 2); } } static inline void mcpwm_ll_capture_enable_negedge(mcpwm_dev_t *mcpwm, int channel, bool enable) { if (enable) { - mcpwm->cap_cfg_ch[channel].val |= 1 << 1; + mcpwm->cap_chn_cfg[channel].val |= 1 << 1; } else { - mcpwm->cap_cfg_ch[channel].val &= ~(1 << 1); + mcpwm->cap_chn_cfg[channel].val &= ~(1 << 1); } } static inline void mcpwm_ll_invert_input(mcpwm_dev_t *mcpwm, int channel, bool invert) { - mcpwm->cap_cfg_ch[channel].in_invert = invert; + mcpwm->cap_chn_cfg[channel].capn_in_invert = invert; } static inline void mcpwm_ll_trigger_soft_capture(mcpwm_dev_t *mcpwm, int channel) { - mcpwm->cap_cfg_ch[channel].sw = 1; // auto clear + mcpwm->cap_chn_cfg[channel].capn_sw = 1; // auto clear } static inline uint32_t mcpwm_ll_capture_get_value(mcpwm_dev_t *mcpwm, int channel) { - return mcpwm->cap_val_ch[channel]; + return mcpwm->cap_chn[channel].capn_value; } static inline bool mcpwm_ll_capture_is_negedge(mcpwm_dev_t *mcpwm, int channel) @@ -1008,12 +1011,12 @@ static inline bool mcpwm_ll_capture_is_negedge(mcpwm_dev_t *mcpwm, int channel) static inline void mcpwm_ll_capture_set_prescale(mcpwm_dev_t *mcpwm, int channel, uint32_t prescale) { - mcpwm->cap_cfg_ch[channel].prescale = prescale - 1; + mcpwm->cap_chn_cfg[channel].capn_prescale = prescale - 1; } static inline uint32_t mcpwm_ll_capture_get_prescale(mcpwm_dev_t *mcpwm, int channel) { - return mcpwm->cap_cfg_ch[channel].prescale + 1; + return mcpwm->cap_chn_cfg[channel].capn_prescale + 1; } #ifdef __cplusplus diff --git a/components/soc/esp32/include/soc/mcpwm_reg.h b/components/soc/esp32/include/soc/mcpwm_reg.h index e919d16a704..6a370aa6910 100644 --- a/components/soc/esp32/include/soc/mcpwm_reg.h +++ b/components/soc/esp32/include/soc/mcpwm_reg.h @@ -1,3027 +1,3829 @@ -// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at - -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -#ifndef _SOC_MCPWM_REG_H_ -#define _SOC_MCPWM_REG_H_ -#include "soc.h" - -#define REG_MCPWM_BASE(i) (DR_REG_PWM0_BASE + i * (0xE000)) - -#define MCPWM_CLK_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x0000) -/* MCPWM_CLK_PRESCALE : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ -/*description: Period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1)*/ -#define MCPWM_CLK_PRESCALE 0x000000FF -#define MCPWM_CLK_PRESCALE_M ((MCPWM_CLK_PRESCALE_V)<<(MCPWM_CLK_PRESCALE_S)) -#define MCPWM_CLK_PRESCALE_V 0xFF +/** + * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +#define DR_REG_MCPWM_BASE(i) (DR_REG_PWM0_BASE + i * (0xE000)) + +/** MCPWM_CLK_CFG_REG register + * PWM clock prescaler register. + */ +#define MCPWM_CLK_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0x0) +/** MCPWM_CLK_PRESCALE : R/W; bitpos: [7:0]; default: 0; + * Period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1) + */ +#define MCPWM_CLK_PRESCALE 0x000000FFU +#define MCPWM_CLK_PRESCALE_M (MCPWM_CLK_PRESCALE_V << MCPWM_CLK_PRESCALE_S) +#define MCPWM_CLK_PRESCALE_V 0x000000FFU #define MCPWM_CLK_PRESCALE_S 0 -#define MCPWM_TIMER0_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x0004) -/* MCPWM_TIMER0_PERIOD_UPMETHOD : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ -/*description: Update method for active reg of PWM timer0 period 0: immediate - 1: TEZ 2: sync 3: TEZ or sync. TEZ here and below means timer equal zero event*/ -#define MCPWM_TIMER0_PERIOD_UPMETHOD 0x00000003 -#define MCPWM_TIMER0_PERIOD_UPMETHOD_M ((MCPWM_TIMER0_PERIOD_UPMETHOD_V)<<(MCPWM_TIMER0_PERIOD_UPMETHOD_S)) -#define MCPWM_TIMER0_PERIOD_UPMETHOD_V 0x3 -#define MCPWM_TIMER0_PERIOD_UPMETHOD_S 24 -/* MCPWM_TIMER0_PERIOD : R/W ;bitpos:[23:8] ;default: 16'h00ff ; */ -/*description: Period shadow reg of PWM timer0*/ -#define MCPWM_TIMER0_PERIOD 0x0000FFFF -#define MCPWM_TIMER0_PERIOD_M ((MCPWM_TIMER0_PERIOD_V)<<(MCPWM_TIMER0_PERIOD_S)) -#define MCPWM_TIMER0_PERIOD_V 0xFFFF -#define MCPWM_TIMER0_PERIOD_S 8 -/* MCPWM_TIMER0_PRESCALE : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ -/*description: Period of PT0_clk = Period of PWM_clk * (PWM_TIMER0_PRESCALE + 1)*/ -#define MCPWM_TIMER0_PRESCALE 0x000000FF -#define MCPWM_TIMER0_PRESCALE_M ((MCPWM_TIMER0_PRESCALE_V)<<(MCPWM_TIMER0_PRESCALE_S)) -#define MCPWM_TIMER0_PRESCALE_V 0xFF +/** MCPWM_TIMER0_CFG0_REG register + * PWM timer0 period and update method configuration register. + */ +#define MCPWM_TIMER0_CFG0_REG(i) (DR_REG_MCPWM_BASE(i) + 0x4) +/** MCPWM_TIMER0_PRESCALE : R/W; bitpos: [7:0]; default: 0; + * Configure the divisor of PT0_clk, takes effect when PWM timer0 stops and starts + * agsin. period of PT0_clk = Period of PWM_clk * (PWM_TIMER0_PRESCALE + 1) + */ +#define MCPWM_TIMER0_PRESCALE 0x000000FFU +#define MCPWM_TIMER0_PRESCALE_M (MCPWM_TIMER0_PRESCALE_V << MCPWM_TIMER0_PRESCALE_S) +#define MCPWM_TIMER0_PRESCALE_V 0x000000FFU #define MCPWM_TIMER0_PRESCALE_S 0 +/** MCPWM_TIMER0_PERIOD : R/W; bitpos: [23:8]; default: 255; + * period shadow register of PWM timer0 + */ +#define MCPWM_TIMER0_PERIOD 0x0000FFFFU +#define MCPWM_TIMER0_PERIOD_M (MCPWM_TIMER0_PERIOD_V << MCPWM_TIMER0_PERIOD_S) +#define MCPWM_TIMER0_PERIOD_V 0x0000FFFFU +#define MCPWM_TIMER0_PERIOD_S 8 +/** MCPWM_TIMER0_PERIOD_UPMETHOD : R/W; bitpos: [25:24]; default: 0; + * Update method for active register of PWM timer0 period, 0: immediate, 1: TEZ, 2: + * sync, 3: TEZ or sync. TEZ here and below means timer equal zero event + */ +#define MCPWM_TIMER0_PERIOD_UPMETHOD 0x00000003U +#define MCPWM_TIMER0_PERIOD_UPMETHOD_M (MCPWM_TIMER0_PERIOD_UPMETHOD_V << MCPWM_TIMER0_PERIOD_UPMETHOD_S) +#define MCPWM_TIMER0_PERIOD_UPMETHOD_V 0x00000003U +#define MCPWM_TIMER0_PERIOD_UPMETHOD_S 24 -#define MCPWM_TIMER0_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0x0008) -/* MCPWM_TIMER0_MOD : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: PWM timer0 working mode 0: freeze 1: increase mod 2: decrease - mod 3: up-down mod*/ -#define MCPWM_TIMER0_MOD 0x00000003 -#define MCPWM_TIMER0_MOD_M ((MCPWM_TIMER0_MOD_V)<<(MCPWM_TIMER0_MOD_S)) -#define MCPWM_TIMER0_MOD_V 0x3 -#define MCPWM_TIMER0_MOD_S 3 -/* MCPWM_TIMER0_START : R/W ;bitpos:[2:0] ;default: 3'h0 ; */ -/*description: PWM timer0 start and stop control. 0: stop @ TEZ 1: stop @ TEP - 2: free run 3: start and stop @ next TEZ 4: start and stop @ next TEP. TEP here and below means timer equal period event*/ -#define MCPWM_TIMER0_START 0x00000007 -#define MCPWM_TIMER0_START_M ((MCPWM_TIMER0_START_V)<<(MCPWM_TIMER0_START_S)) -#define MCPWM_TIMER0_START_V 0x7 +/** MCPWM_TIMER0_CFG1_REG register + * PWM timer0 working mode and start/stop control configuration register. + */ +#define MCPWM_TIMER0_CFG1_REG(i) (DR_REG_MCPWM_BASE(i) + 0x8) +/** MCPWM_TIMER0_START : R/W/SC; bitpos: [2:0]; default: 0; + * PWM timer0 start and stop control. 0: if PWM timer0 starts, then stops at TEZ, 1: + * if timer0 starts, then stops at TEP, 2: PWM timer0 starts and runs on, 3: timer0 + * starts and stops at the next TEZ, 4: timer0 starts and stops at the next TEP. TEP + * here and below means the event that happens when the timer equals to period + */ +#define MCPWM_TIMER0_START 0x00000007U +#define MCPWM_TIMER0_START_M (MCPWM_TIMER0_START_V << MCPWM_TIMER0_START_S) +#define MCPWM_TIMER0_START_V 0x00000007U #define MCPWM_TIMER0_START_S 0 +/** MCPWM_TIMER0_MOD : R/W; bitpos: [4:3]; default: 0; + * PWM timer0 working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down + * mode + */ +#define MCPWM_TIMER0_MOD 0x00000003U +#define MCPWM_TIMER0_MOD_M (MCPWM_TIMER0_MOD_V << MCPWM_TIMER0_MOD_S) +#define MCPWM_TIMER0_MOD_V 0x00000003U +#define MCPWM_TIMER0_MOD_S 3 -#define MCPWM_TIMER0_SYNC_REG(i) (REG_MCPWM_BASE(i) + 0x000c) -/* MCPWM_TIMER0_PHASE : R/W ;bitpos:[20:4] ;default: 17'd0 ; */ -/*description: Phase for timer reload on sync event*/ -#define MCPWM_TIMER0_PHASE 0x0001FFFF -#define MCPWM_TIMER0_PHASE_M ((MCPWM_TIMER0_PHASE_V)<<(MCPWM_TIMER0_PHASE_S)) -#define MCPWM_TIMER0_PHASE_V 0x1FFFF -#define MCPWM_TIMER0_PHASE_S 4 -/* MCPWM_TIMER0_SYNCO_SEL : R/W ;bitpos:[3:2] ;default: 2'd0 ; */ -/*description: PWM timer0 synco selection 0: synci 1: TEZ 2: TEP else 0*/ -#define MCPWM_TIMER0_SYNCO_SEL 0x00000003 -#define MCPWM_TIMER0_SYNCO_SEL_M ((MCPWM_TIMER0_SYNCO_SEL_V)<<(MCPWM_TIMER0_SYNCO_SEL_S)) -#define MCPWM_TIMER0_SYNCO_SEL_V 0x3 -#define MCPWM_TIMER0_SYNCO_SEL_S 2 -/* MCPWM_TIMER0_SYNC_SW : R/W ;bitpos:[1] ;default: 1'h0 ; */ -/*description: Toggling this bit will trigger a software sync*/ -#define MCPWM_TIMER0_SYNC_SW (BIT(1)) -#define MCPWM_TIMER0_SYNC_SW_M (BIT(1)) -#define MCPWM_TIMER0_SYNC_SW_V 0x1 -#define MCPWM_TIMER0_SYNC_SW_S 1 -/* MCPWM_TIMER0_SYNCI_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: When set timer reload with phase on sync input event is enabled*/ -#define MCPWM_TIMER0_SYNCI_EN (BIT(0)) -#define MCPWM_TIMER0_SYNCI_EN_M (BIT(0)) -#define MCPWM_TIMER0_SYNCI_EN_V 0x1 +/** MCPWM_TIMER0_SYNC_REG register + * PWM timer0 sync function configuration register. + */ +#define MCPWM_TIMER0_SYNC_REG(i) (DR_REG_MCPWM_BASE(i) + 0xc) +/** MCPWM_TIMER0_SYNCI_EN : R/W; bitpos: [0]; default: 0; + * When set, timer reloading with phase on sync input event is enabled. + */ +#define MCPWM_TIMER0_SYNCI_EN (BIT(0)) +#define MCPWM_TIMER0_SYNCI_EN_M (MCPWM_TIMER0_SYNCI_EN_V << MCPWM_TIMER0_SYNCI_EN_S) +#define MCPWM_TIMER0_SYNCI_EN_V 0x00000001U #define MCPWM_TIMER0_SYNCI_EN_S 0 - -#define MCPWM_TIMER0_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x0010) -/* MCPWM_TIMER0_DIRECTION : RO ;bitpos:[16] ;default: 1'd0 ; */ -/*description: Current PWM timer0 counter direction 0: increment 1: decrement*/ -#define MCPWM_TIMER0_DIRECTION (BIT(16)) -#define MCPWM_TIMER0_DIRECTION_M (BIT(16)) -#define MCPWM_TIMER0_DIRECTION_V 0x1 -#define MCPWM_TIMER0_DIRECTION_S 16 -/* MCPWM_TIMER0_VALUE : RO ;bitpos:[15:0] ;default: 16'd0 ; */ -/*description: Current PWM timer0 counter value*/ -#define MCPWM_TIMER0_VALUE 0x0000FFFF -#define MCPWM_TIMER0_VALUE_M ((MCPWM_TIMER0_VALUE_V)<<(MCPWM_TIMER0_VALUE_S)) -#define MCPWM_TIMER0_VALUE_V 0xFFFF +/** MCPWM_TIMER0_SYNC_SW : R/W; bitpos: [1]; default: 0; + * Toggling this bit will trigger a software sync. + */ +#define MCPWM_TIMER0_SYNC_SW (BIT(1)) +#define MCPWM_TIMER0_SYNC_SW_M (MCPWM_TIMER0_SYNC_SW_V << MCPWM_TIMER0_SYNC_SW_S) +#define MCPWM_TIMER0_SYNC_SW_V 0x00000001U +#define MCPWM_TIMER0_SYNC_SW_S 1 +/** MCPWM_TIMER0_SYNCO_SEL : R/W; bitpos: [3:2]; default: 0; + * PWM timer0 sync_out selection, 0: sync_in, 1: TEZ, 2: TEP, and sync out will always + * generate when toggling the reg_timer0_sync_sw bit + */ +#define MCPWM_TIMER0_SYNCO_SEL 0x00000003U +#define MCPWM_TIMER0_SYNCO_SEL_M (MCPWM_TIMER0_SYNCO_SEL_V << MCPWM_TIMER0_SYNCO_SEL_S) +#define MCPWM_TIMER0_SYNCO_SEL_V 0x00000003U +#define MCPWM_TIMER0_SYNCO_SEL_S 2 +/** MCPWM_TIMER0_PHASE : R/W; bitpos: [19:4]; default: 0; + * phase for timer reload on sync event + */ +#define MCPWM_TIMER0_PHASE 0x0000FFFFU +#define MCPWM_TIMER0_PHASE_M (MCPWM_TIMER0_PHASE_V << MCPWM_TIMER0_PHASE_S) +#define MCPWM_TIMER0_PHASE_V 0x0000FFFFU +#define MCPWM_TIMER0_PHASE_S 4 +/** MCPWM_TIMER0_PHASE_DIRECTION : R/W; bitpos: [20]; default: 0; + * Configure the PWM timer0's direction at the time sync event occurs when timer0 mode + * is up-down mode: 0-increase,1-decrease + */ +#define MCPWM_TIMER0_PHASE_DIRECTION (BIT(20)) +#define MCPWM_TIMER0_PHASE_DIRECTION_M (MCPWM_TIMER0_PHASE_DIRECTION_V << MCPWM_TIMER0_PHASE_DIRECTION_S) +#define MCPWM_TIMER0_PHASE_DIRECTION_V 0x00000001U +#define MCPWM_TIMER0_PHASE_DIRECTION_S 20 + +/** MCPWM_TIMER0_STATUS_REG register + * PWM timer0 status register. + */ +#define MCPWM_TIMER0_STATUS_REG(i) (DR_REG_MCPWM_BASE(i) + 0x10) +/** MCPWM_TIMER0_VALUE : RO; bitpos: [15:0]; default: 0; + * current PWM timer0 counter value + */ +#define MCPWM_TIMER0_VALUE 0x0000FFFFU +#define MCPWM_TIMER0_VALUE_M (MCPWM_TIMER0_VALUE_V << MCPWM_TIMER0_VALUE_S) +#define MCPWM_TIMER0_VALUE_V 0x0000FFFFU #define MCPWM_TIMER0_VALUE_S 0 +/** MCPWM_TIMER0_DIRECTION : RO; bitpos: [16]; default: 0; + * current PWM timer0 counter direction, 0: increment 1: decrement + */ +#define MCPWM_TIMER0_DIRECTION (BIT(16)) +#define MCPWM_TIMER0_DIRECTION_M (MCPWM_TIMER0_DIRECTION_V << MCPWM_TIMER0_DIRECTION_S) +#define MCPWM_TIMER0_DIRECTION_V 0x00000001U +#define MCPWM_TIMER0_DIRECTION_S 16 -#define MCPWM_TIMER1_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x0014) -/* MCPWM_TIMER1_PERIOD_UPMETHOD : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ -/*description: Update method for active reg of PWM timer1 period 0: immediate - 1: TEZ 2: sync 3: TEZ or sync*/ -#define MCPWM_TIMER1_PERIOD_UPMETHOD 0x00000003 -#define MCPWM_TIMER1_PERIOD_UPMETHOD_M ((MCPWM_TIMER1_PERIOD_UPMETHOD_V)<<(MCPWM_TIMER1_PERIOD_UPMETHOD_S)) -#define MCPWM_TIMER1_PERIOD_UPMETHOD_V 0x3 -#define MCPWM_TIMER1_PERIOD_UPMETHOD_S 24 -/* MCPWM_TIMER1_PERIOD : R/W ;bitpos:[23:8] ;default: 16'h00ff ; */ -/*description: Period shadow reg of PWM timer1*/ -#define MCPWM_TIMER1_PERIOD 0x0000FFFF -#define MCPWM_TIMER1_PERIOD_M ((MCPWM_TIMER1_PERIOD_V)<<(MCPWM_TIMER1_PERIOD_S)) -#define MCPWM_TIMER1_PERIOD_V 0xFFFF -#define MCPWM_TIMER1_PERIOD_S 8 -/* MCPWM_TIMER1_PRESCALE : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ -/*description: Period of PT1_clk = Period of PWM_clk * (PWM_TIMER1_PRESCALE + 1)*/ -#define MCPWM_TIMER1_PRESCALE 0x000000FF -#define MCPWM_TIMER1_PRESCALE_M ((MCPWM_TIMER1_PRESCALE_V)<<(MCPWM_TIMER1_PRESCALE_S)) -#define MCPWM_TIMER1_PRESCALE_V 0xFF +/** MCPWM_TIMER1_CFG0_REG register + * PWM timer1 period and update method configuration register. + */ +#define MCPWM_TIMER1_CFG0_REG(i) (DR_REG_MCPWM_BASE(i) + 0x14) +/** MCPWM_TIMER1_PRESCALE : R/W; bitpos: [7:0]; default: 0; + * Configure the divisor of PT1_clk, takes effect when PWM timer1 stops and starts + * agsin. period of PT1_clk = Period of PWM_clk * (PWM_TIMER1_PRESCALE + 1) + */ +#define MCPWM_TIMER1_PRESCALE 0x000000FFU +#define MCPWM_TIMER1_PRESCALE_M (MCPWM_TIMER1_PRESCALE_V << MCPWM_TIMER1_PRESCALE_S) +#define MCPWM_TIMER1_PRESCALE_V 0x000000FFU #define MCPWM_TIMER1_PRESCALE_S 0 +/** MCPWM_TIMER1_PERIOD : R/W; bitpos: [23:8]; default: 255; + * period shadow register of PWM timer1 + */ +#define MCPWM_TIMER1_PERIOD 0x0000FFFFU +#define MCPWM_TIMER1_PERIOD_M (MCPWM_TIMER1_PERIOD_V << MCPWM_TIMER1_PERIOD_S) +#define MCPWM_TIMER1_PERIOD_V 0x0000FFFFU +#define MCPWM_TIMER1_PERIOD_S 8 +/** MCPWM_TIMER1_PERIOD_UPMETHOD : R/W; bitpos: [25:24]; default: 0; + * Update method for active register of PWM timer1 period, 0: immediate, 1: TEZ, 2: + * sync, 3: TEZ | sync. TEZ here and below means timer equal zero event + */ +#define MCPWM_TIMER1_PERIOD_UPMETHOD 0x00000003U +#define MCPWM_TIMER1_PERIOD_UPMETHOD_M (MCPWM_TIMER1_PERIOD_UPMETHOD_V << MCPWM_TIMER1_PERIOD_UPMETHOD_S) +#define MCPWM_TIMER1_PERIOD_UPMETHOD_V 0x00000003U +#define MCPWM_TIMER1_PERIOD_UPMETHOD_S 24 -#define MCPWM_TIMER1_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0x0018) -/* MCPWM_TIMER1_MOD : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: PWM timer1 working mode 0: freeze 1: increase mod 2: decrease - mod 3: up-down mod*/ -#define MCPWM_TIMER1_MOD 0x00000003 -#define MCPWM_TIMER1_MOD_M ((MCPWM_TIMER1_MOD_V)<<(MCPWM_TIMER1_MOD_S)) -#define MCPWM_TIMER1_MOD_V 0x3 -#define MCPWM_TIMER1_MOD_S 3 -/* MCPWM_TIMER1_START : R/W ;bitpos:[2:0] ;default: 3'h0 ; */ -/*description: PWM timer1 start and stop control. 0: stop @ TEZ 1: stop @ TEP - 2: free run 3: start and stop @ next TEZ 4: start and stop @ next TEP.*/ -#define MCPWM_TIMER1_START 0x00000007 -#define MCPWM_TIMER1_START_M ((MCPWM_TIMER1_START_V)<<(MCPWM_TIMER1_START_S)) -#define MCPWM_TIMER1_START_V 0x7 +/** MCPWM_TIMER1_CFG1_REG register + * PWM timer1 working mode and start/stop control configuration register. + */ +#define MCPWM_TIMER1_CFG1_REG(i) (DR_REG_MCPWM_BASE(i) + 0x18) +/** MCPWM_TIMER1_START : R/W/SC; bitpos: [2:0]; default: 0; + * PWM timer1 start and stop control. 0: if PWM timer1 starts, then stops at TEZ, 1: + * if timer1 starts, then stops at TEP, 2: PWM timer1 starts and runs on, 3: timer1 + * starts and stops at the next TEZ, 4: timer1 starts and stops at the next TEP. TEP + * here and below means the event that happens when the timer equals to period + */ +#define MCPWM_TIMER1_START 0x00000007U +#define MCPWM_TIMER1_START_M (MCPWM_TIMER1_START_V << MCPWM_TIMER1_START_S) +#define MCPWM_TIMER1_START_V 0x00000007U #define MCPWM_TIMER1_START_S 0 +/** MCPWM_TIMER1_MOD : R/W; bitpos: [4:3]; default: 0; + * PWM timer1 working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down + * mode + */ +#define MCPWM_TIMER1_MOD 0x00000003U +#define MCPWM_TIMER1_MOD_M (MCPWM_TIMER1_MOD_V << MCPWM_TIMER1_MOD_S) +#define MCPWM_TIMER1_MOD_V 0x00000003U +#define MCPWM_TIMER1_MOD_S 3 -#define MCPWM_TIMER1_SYNC_REG(i) (REG_MCPWM_BASE(i) + 0x001c) -/* MCPWM_TIMER1_PHASE : R/W ;bitpos:[20:4] ;default: 17'd0 ; */ -/*description: Phase for timer reload on sync event*/ -#define MCPWM_TIMER1_PHASE 0x0001FFFF -#define MCPWM_TIMER1_PHASE_M ((MCPWM_TIMER1_PHASE_V)<<(MCPWM_TIMER1_PHASE_S)) -#define MCPWM_TIMER1_PHASE_V 0x1FFFF -#define MCPWM_TIMER1_PHASE_S 4 -/* MCPWM_TIMER1_SYNCO_SEL : R/W ;bitpos:[3:2] ;default: 2'd0 ; */ -/*description: PWM timer1 synco selection 0: synci 1: TEZ 2: TEP else 0*/ -#define MCPWM_TIMER1_SYNCO_SEL 0x00000003 -#define MCPWM_TIMER1_SYNCO_SEL_M ((MCPWM_TIMER1_SYNCO_SEL_V)<<(MCPWM_TIMER1_SYNCO_SEL_S)) -#define MCPWM_TIMER1_SYNCO_SEL_V 0x3 -#define MCPWM_TIMER1_SYNCO_SEL_S 2 -/* MCPWM_TIMER1_SYNC_SW : R/W ;bitpos:[1] ;default: 1'h0 ; */ -/*description: Toggling this bit will trigger a software sync*/ -#define MCPWM_TIMER1_SYNC_SW (BIT(1)) -#define MCPWM_TIMER1_SYNC_SW_M (BIT(1)) -#define MCPWM_TIMER1_SYNC_SW_V 0x1 -#define MCPWM_TIMER1_SYNC_SW_S 1 -/* MCPWM_TIMER1_SYNCI_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: When set timer reload with phase on sync input event is enabled*/ -#define MCPWM_TIMER1_SYNCI_EN (BIT(0)) -#define MCPWM_TIMER1_SYNCI_EN_M (BIT(0)) -#define MCPWM_TIMER1_SYNCI_EN_V 0x1 +/** MCPWM_TIMER1_SYNC_REG register + * PWM timer1 sync function configuration register. + */ +#define MCPWM_TIMER1_SYNC_REG(i) (DR_REG_MCPWM_BASE(i) + 0x1c) +/** MCPWM_TIMER1_SYNCI_EN : R/W; bitpos: [0]; default: 0; + * When set, timer reloading with phase on sync input event is enabled. + */ +#define MCPWM_TIMER1_SYNCI_EN (BIT(0)) +#define MCPWM_TIMER1_SYNCI_EN_M (MCPWM_TIMER1_SYNCI_EN_V << MCPWM_TIMER1_SYNCI_EN_S) +#define MCPWM_TIMER1_SYNCI_EN_V 0x00000001U #define MCPWM_TIMER1_SYNCI_EN_S 0 - -#define MCPWM_TIMER1_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x0020) -/* MCPWM_TIMER1_DIRECTION : RO ;bitpos:[16] ;default: 1'd0 ; */ -/*description: Current PWM timer1 counter direction 0: increment 1: decrement*/ -#define MCPWM_TIMER1_DIRECTION (BIT(16)) -#define MCPWM_TIMER1_DIRECTION_M (BIT(16)) -#define MCPWM_TIMER1_DIRECTION_V 0x1 -#define MCPWM_TIMER1_DIRECTION_S 16 -/* MCPWM_TIMER1_VALUE : RO ;bitpos:[15:0] ;default: 16'd0 ; */ -/*description: Current PWM timer1 counter value*/ -#define MCPWM_TIMER1_VALUE 0x0000FFFF -#define MCPWM_TIMER1_VALUE_M ((MCPWM_TIMER1_VALUE_V)<<(MCPWM_TIMER1_VALUE_S)) -#define MCPWM_TIMER1_VALUE_V 0xFFFF +/** MCPWM_TIMER1_SYNC_SW : R/W; bitpos: [1]; default: 0; + * Toggling this bit will trigger a software sync. + */ +#define MCPWM_TIMER1_SYNC_SW (BIT(1)) +#define MCPWM_TIMER1_SYNC_SW_M (MCPWM_TIMER1_SYNC_SW_V << MCPWM_TIMER1_SYNC_SW_S) +#define MCPWM_TIMER1_SYNC_SW_V 0x00000001U +#define MCPWM_TIMER1_SYNC_SW_S 1 +/** MCPWM_TIMER1_SYNCO_SEL : R/W; bitpos: [3:2]; default: 0; + * PWM timer1 sync_out selection, 0: sync_in, 1: TEZ, 2: TEP, and sync out will always + * generate when toggling the reg_timer1_sync_sw bit + */ +#define MCPWM_TIMER1_SYNCO_SEL 0x00000003U +#define MCPWM_TIMER1_SYNCO_SEL_M (MCPWM_TIMER1_SYNCO_SEL_V << MCPWM_TIMER1_SYNCO_SEL_S) +#define MCPWM_TIMER1_SYNCO_SEL_V 0x00000003U +#define MCPWM_TIMER1_SYNCO_SEL_S 2 +/** MCPWM_TIMER1_PHASE : R/W; bitpos: [19:4]; default: 0; + * phase for timer reload on sync event + */ +#define MCPWM_TIMER1_PHASE 0x0000FFFFU +#define MCPWM_TIMER1_PHASE_M (MCPWM_TIMER1_PHASE_V << MCPWM_TIMER1_PHASE_S) +#define MCPWM_TIMER1_PHASE_V 0x0000FFFFU +#define MCPWM_TIMER1_PHASE_S 4 +/** MCPWM_TIMER1_PHASE_DIRECTION : R/W; bitpos: [20]; default: 0; + * Configure the PWM timer1's direction at the time sync event occurs when timer1 mode + * is up-down mode: 0-increase,1-decrease + */ +#define MCPWM_TIMER1_PHASE_DIRECTION (BIT(20)) +#define MCPWM_TIMER1_PHASE_DIRECTION_M (MCPWM_TIMER1_PHASE_DIRECTION_V << MCPWM_TIMER1_PHASE_DIRECTION_S) +#define MCPWM_TIMER1_PHASE_DIRECTION_V 0x00000001U +#define MCPWM_TIMER1_PHASE_DIRECTION_S 20 + +/** MCPWM_TIMER1_STATUS_REG register + * PWM timer1 status register. + */ +#define MCPWM_TIMER1_STATUS_REG(i) (DR_REG_MCPWM_BASE(i) + 0x20) +/** MCPWM_TIMER1_VALUE : RO; bitpos: [15:0]; default: 0; + * current PWM timer1 counter value + */ +#define MCPWM_TIMER1_VALUE 0x0000FFFFU +#define MCPWM_TIMER1_VALUE_M (MCPWM_TIMER1_VALUE_V << MCPWM_TIMER1_VALUE_S) +#define MCPWM_TIMER1_VALUE_V 0x0000FFFFU #define MCPWM_TIMER1_VALUE_S 0 +/** MCPWM_TIMER1_DIRECTION : RO; bitpos: [16]; default: 0; + * current PWM timer1 counter direction, 0: increment 1: decrement + */ +#define MCPWM_TIMER1_DIRECTION (BIT(16)) +#define MCPWM_TIMER1_DIRECTION_M (MCPWM_TIMER1_DIRECTION_V << MCPWM_TIMER1_DIRECTION_S) +#define MCPWM_TIMER1_DIRECTION_V 0x00000001U +#define MCPWM_TIMER1_DIRECTION_S 16 -#define MCPWM_TIMER2_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x0024) -/* MCPWM_TIMER2_PERIOD_UPMETHOD : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ -/*description: Update method for active reg of PWM timer2 period 0: immediate - 1: TEZ 2: sync 3: TEZ or sync*/ -#define MCPWM_TIMER2_PERIOD_UPMETHOD 0x00000003 -#define MCPWM_TIMER2_PERIOD_UPMETHOD_M ((MCPWM_TIMER2_PERIOD_UPMETHOD_V)<<(MCPWM_TIMER2_PERIOD_UPMETHOD_S)) -#define MCPWM_TIMER2_PERIOD_UPMETHOD_V 0x3 -#define MCPWM_TIMER2_PERIOD_UPMETHOD_S 24 -/* MCPWM_TIMER2_PERIOD : R/W ;bitpos:[23:8] ;default: 16'h00ff ; */ -/*description: Period shadow reg of PWM timer2*/ -#define MCPWM_TIMER2_PERIOD 0x0000FFFF -#define MCPWM_TIMER2_PERIOD_M ((MCPWM_TIMER2_PERIOD_V)<<(MCPWM_TIMER2_PERIOD_S)) -#define MCPWM_TIMER2_PERIOD_V 0xFFFF -#define MCPWM_TIMER2_PERIOD_S 8 -/* MCPWM_TIMER2_PRESCALE : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ -/*description: Period of PT2_clk = Period of PWM_clk * (PWM_TIMER2_PRESCALE + 1)*/ -#define MCPWM_TIMER2_PRESCALE 0x000000FF -#define MCPWM_TIMER2_PRESCALE_M ((MCPWM_TIMER2_PRESCALE_V)<<(MCPWM_TIMER2_PRESCALE_S)) -#define MCPWM_TIMER2_PRESCALE_V 0xFF +/** MCPWM_TIMER2_CFG0_REG register + * PWM timer2 period and update method configuration register. + */ +#define MCPWM_TIMER2_CFG0_REG(i) (DR_REG_MCPWM_BASE(i) + 0x24) +/** MCPWM_TIMER2_PRESCALE : R/W; bitpos: [7:0]; default: 0; + * Configure the divisor of PT2_clk, takes effect when PWM timer2 stops and starts + * agsin. period of PT2_clk = Period of PWM_clk * (PWM_TIMER2_PRESCALE + 1) + */ +#define MCPWM_TIMER2_PRESCALE 0x000000FFU +#define MCPWM_TIMER2_PRESCALE_M (MCPWM_TIMER2_PRESCALE_V << MCPWM_TIMER2_PRESCALE_S) +#define MCPWM_TIMER2_PRESCALE_V 0x000000FFU #define MCPWM_TIMER2_PRESCALE_S 0 +/** MCPWM_TIMER2_PERIOD : R/W; bitpos: [23:8]; default: 255; + * period shadow register of PWM timer2 + */ +#define MCPWM_TIMER2_PERIOD 0x0000FFFFU +#define MCPWM_TIMER2_PERIOD_M (MCPWM_TIMER2_PERIOD_V << MCPWM_TIMER2_PERIOD_S) +#define MCPWM_TIMER2_PERIOD_V 0x0000FFFFU +#define MCPWM_TIMER2_PERIOD_S 8 +/** MCPWM_TIMER2_PERIOD_UPMETHOD : R/W; bitpos: [25:24]; default: 0; + * Update method for active register of PWM timer2 period, 0: immediate, 1: TEZ, 2: + * sync, 3: TEZ | sync. TEZ here and below means timer equal zero event + */ +#define MCPWM_TIMER2_PERIOD_UPMETHOD 0x00000003U +#define MCPWM_TIMER2_PERIOD_UPMETHOD_M (MCPWM_TIMER2_PERIOD_UPMETHOD_V << MCPWM_TIMER2_PERIOD_UPMETHOD_S) +#define MCPWM_TIMER2_PERIOD_UPMETHOD_V 0x00000003U +#define MCPWM_TIMER2_PERIOD_UPMETHOD_S 24 -#define MCPWM_TIMER2_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0x0028) -/* MCPWM_TIMER2_MOD : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: PWM timer2 working mode 0: freeze 1: increase mod 2: decrease - mod 3: up-down mod*/ -#define MCPWM_TIMER2_MOD 0x00000003 -#define MCPWM_TIMER2_MOD_M ((MCPWM_TIMER2_MOD_V)<<(MCPWM_TIMER2_MOD_S)) -#define MCPWM_TIMER2_MOD_V 0x3 -#define MCPWM_TIMER2_MOD_S 3 -/* MCPWM_TIMER2_START : R/W ;bitpos:[2:0] ;default: 3'h0 ; */ -/*description: PWM timer2 start and stop control. 0: stop @ TEZ 1: stop @ TEP - 2: free run 3: start and stop @ next TEZ 4: start and stop @ next TEP.*/ -#define MCPWM_TIMER2_START 0x00000007 -#define MCPWM_TIMER2_START_M ((MCPWM_TIMER2_START_V)<<(MCPWM_TIMER2_START_S)) -#define MCPWM_TIMER2_START_V 0x7 +/** MCPWM_TIMER2_CFG1_REG register + * PWM timer2 working mode and start/stop control configuration register. + */ +#define MCPWM_TIMER2_CFG1_REG(i) (DR_REG_MCPWM_BASE(i) + 0x28) +/** MCPWM_TIMER2_START : R/W/SC; bitpos: [2:0]; default: 0; + * PWM timer2 start and stop control. 0: if PWM timer2 starts, then stops at TEZ, 1: + * if timer2 starts, then stops at TEP, 2: PWM timer2 starts and runs on, 3: timer2 + * starts and stops at the next TEZ, 4: timer2 starts and stops at the next TEP. TEP + * here and below means the event that happens when the timer equals to period + */ +#define MCPWM_TIMER2_START 0x00000007U +#define MCPWM_TIMER2_START_M (MCPWM_TIMER2_START_V << MCPWM_TIMER2_START_S) +#define MCPWM_TIMER2_START_V 0x00000007U #define MCPWM_TIMER2_START_S 0 +/** MCPWM_TIMER2_MOD : R/W; bitpos: [4:3]; default: 0; + * PWM timer2 working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down + * mode + */ +#define MCPWM_TIMER2_MOD 0x00000003U +#define MCPWM_TIMER2_MOD_M (MCPWM_TIMER2_MOD_V << MCPWM_TIMER2_MOD_S) +#define MCPWM_TIMER2_MOD_V 0x00000003U +#define MCPWM_TIMER2_MOD_S 3 -#define MCPWM_TIMER2_SYNC_REG(i) (REG_MCPWM_BASE(i) + 0x002c) -/* MCPWM_TIMER2_PHASE : R/W ;bitpos:[20:4] ;default: 17'd0 ; */ -/*description: Phase for timer reload on sync event*/ -#define MCPWM_TIMER2_PHASE 0x0001FFFF -#define MCPWM_TIMER2_PHASE_M ((MCPWM_TIMER2_PHASE_V)<<(MCPWM_TIMER2_PHASE_S)) -#define MCPWM_TIMER2_PHASE_V 0x1FFFF -#define MCPWM_TIMER2_PHASE_S 4 -/* MCPWM_TIMER2_SYNCO_SEL : R/W ;bitpos:[3:2] ;default: 2'd0 ; */ -/*description: PWM timer2 synco selection 0: synci 1: TEZ 2: TEP else 0*/ -#define MCPWM_TIMER2_SYNCO_SEL 0x00000003 -#define MCPWM_TIMER2_SYNCO_SEL_M ((MCPWM_TIMER2_SYNCO_SEL_V)<<(MCPWM_TIMER2_SYNCO_SEL_S)) -#define MCPWM_TIMER2_SYNCO_SEL_V 0x3 -#define MCPWM_TIMER2_SYNCO_SEL_S 2 -/* MCPWM_TIMER2_SYNC_SW : R/W ;bitpos:[1] ;default: 1'h0 ; */ -/*description: Toggling this bit will trigger a software sync*/ -#define MCPWM_TIMER2_SYNC_SW (BIT(1)) -#define MCPWM_TIMER2_SYNC_SW_M (BIT(1)) -#define MCPWM_TIMER2_SYNC_SW_V 0x1 -#define MCPWM_TIMER2_SYNC_SW_S 1 -/* MCPWM_TIMER2_SYNCI_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: When set timer reload with phase on sync input event is enabled*/ -#define MCPWM_TIMER2_SYNCI_EN (BIT(0)) -#define MCPWM_TIMER2_SYNCI_EN_M (BIT(0)) -#define MCPWM_TIMER2_SYNCI_EN_V 0x1 +/** MCPWM_TIMER2_SYNC_REG register + * PWM timer2 sync function configuration register. + */ +#define MCPWM_TIMER2_SYNC_REG(i) (DR_REG_MCPWM_BASE(i) + 0x2c) +/** MCPWM_TIMER2_SYNCI_EN : R/W; bitpos: [0]; default: 0; + * When set, timer reloading with phase on sync input event is enabled. + */ +#define MCPWM_TIMER2_SYNCI_EN (BIT(0)) +#define MCPWM_TIMER2_SYNCI_EN_M (MCPWM_TIMER2_SYNCI_EN_V << MCPWM_TIMER2_SYNCI_EN_S) +#define MCPWM_TIMER2_SYNCI_EN_V 0x00000001U #define MCPWM_TIMER2_SYNCI_EN_S 0 - -#define MCPWM_TIMER2_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x0030) -/* MCPWM_TIMER2_DIRECTION : RO ;bitpos:[16] ;default: 1'd0 ; */ -/*description: Current PWM timer2 counter direction 0: increment 1: decrement*/ -#define MCPWM_TIMER2_DIRECTION (BIT(16)) -#define MCPWM_TIMER2_DIRECTION_M (BIT(16)) -#define MCPWM_TIMER2_DIRECTION_V 0x1 -#define MCPWM_TIMER2_DIRECTION_S 16 -/* MCPWM_TIMER2_VALUE : RO ;bitpos:[15:0] ;default: 16'd0 ; */ -/*description: Current PWM timer2 counter value*/ -#define MCPWM_TIMER2_VALUE 0x0000FFFF -#define MCPWM_TIMER2_VALUE_M ((MCPWM_TIMER2_VALUE_V)<<(MCPWM_TIMER2_VALUE_S)) -#define MCPWM_TIMER2_VALUE_V 0xFFFF +/** MCPWM_TIMER2_SYNC_SW : R/W; bitpos: [1]; default: 0; + * Toggling this bit will trigger a software sync. + */ +#define MCPWM_TIMER2_SYNC_SW (BIT(1)) +#define MCPWM_TIMER2_SYNC_SW_M (MCPWM_TIMER2_SYNC_SW_V << MCPWM_TIMER2_SYNC_SW_S) +#define MCPWM_TIMER2_SYNC_SW_V 0x00000001U +#define MCPWM_TIMER2_SYNC_SW_S 1 +/** MCPWM_TIMER2_SYNCO_SEL : R/W; bitpos: [3:2]; default: 0; + * PWM timer2 sync_out selection, 0: sync_in, 1: TEZ, 2: TEP, and sync out will always + * generate when toggling the reg_timer0_sync_sw bit + */ +#define MCPWM_TIMER2_SYNCO_SEL 0x00000003U +#define MCPWM_TIMER2_SYNCO_SEL_M (MCPWM_TIMER2_SYNCO_SEL_V << MCPWM_TIMER2_SYNCO_SEL_S) +#define MCPWM_TIMER2_SYNCO_SEL_V 0x00000003U +#define MCPWM_TIMER2_SYNCO_SEL_S 2 +/** MCPWM_TIMER2_PHASE : R/W; bitpos: [19:4]; default: 0; + * phase for timer reload on sync event + */ +#define MCPWM_TIMER2_PHASE 0x0000FFFFU +#define MCPWM_TIMER2_PHASE_M (MCPWM_TIMER2_PHASE_V << MCPWM_TIMER2_PHASE_S) +#define MCPWM_TIMER2_PHASE_V 0x0000FFFFU +#define MCPWM_TIMER2_PHASE_S 4 +/** MCPWM_TIMER2_PHASE_DIRECTION : R/W; bitpos: [20]; default: 0; + * Configure the PWM timer2's direction at the time sync event occurs when timer2 mode + * is up-down mode: 0-increase,1-decrease + */ +#define MCPWM_TIMER2_PHASE_DIRECTION (BIT(20)) +#define MCPWM_TIMER2_PHASE_DIRECTION_M (MCPWM_TIMER2_PHASE_DIRECTION_V << MCPWM_TIMER2_PHASE_DIRECTION_S) +#define MCPWM_TIMER2_PHASE_DIRECTION_V 0x00000001U +#define MCPWM_TIMER2_PHASE_DIRECTION_S 20 + +/** MCPWM_TIMER2_STATUS_REG register + * PWM timer2 status register. + */ +#define MCPWM_TIMER2_STATUS_REG(i) (DR_REG_MCPWM_BASE(i) + 0x30) +/** MCPWM_TIMER2_VALUE : RO; bitpos: [15:0]; default: 0; + * current PWM timer2 counter value + */ +#define MCPWM_TIMER2_VALUE 0x0000FFFFU +#define MCPWM_TIMER2_VALUE_M (MCPWM_TIMER2_VALUE_V << MCPWM_TIMER2_VALUE_S) +#define MCPWM_TIMER2_VALUE_V 0x0000FFFFU #define MCPWM_TIMER2_VALUE_S 0 +/** MCPWM_TIMER2_DIRECTION : RO; bitpos: [16]; default: 0; + * current PWM timer2 counter direction, 0: increment 1: decrement + */ +#define MCPWM_TIMER2_DIRECTION (BIT(16)) +#define MCPWM_TIMER2_DIRECTION_M (MCPWM_TIMER2_DIRECTION_V << MCPWM_TIMER2_DIRECTION_S) +#define MCPWM_TIMER2_DIRECTION_V 0x00000001U +#define MCPWM_TIMER2_DIRECTION_S 16 -#define MCPWM_TIMER_SYNCI_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x0034) -/* MCPWM_EXTERNAL_SYNCI2_INVERT : R/W ;bitpos:[11] ;default: 1'd0 ; */ -/*description: Onvert SYNC2 from GPIO matrix*/ -#define MCPWM_EXTERNAL_SYNCI2_INVERT (BIT(11)) -#define MCPWM_EXTERNAL_SYNCI2_INVERT_M (BIT(11)) -#define MCPWM_EXTERNAL_SYNCI2_INVERT_V 0x1 -#define MCPWM_EXTERNAL_SYNCI2_INVERT_S 11 -/* MCPWM_EXTERNAL_SYNCI1_INVERT : R/W ;bitpos:[10] ;default: 1'd0 ; */ -/*description: Invert SYNC1 from GPIO matrix*/ -#define MCPWM_EXTERNAL_SYNCI1_INVERT (BIT(10)) -#define MCPWM_EXTERNAL_SYNCI1_INVERT_M (BIT(10)) -#define MCPWM_EXTERNAL_SYNCI1_INVERT_V 0x1 -#define MCPWM_EXTERNAL_SYNCI1_INVERT_S 10 -/* MCPWM_EXTERNAL_SYNCI0_INVERT : R/W ;bitpos:[9] ;default: 1'd0 ; */ -/*description: Invert SYNC0 from GPIO matrix*/ -#define MCPWM_EXTERNAL_SYNCI0_INVERT (BIT(9)) -#define MCPWM_EXTERNAL_SYNCI0_INVERT_M (BIT(9)) -#define MCPWM_EXTERNAL_SYNCI0_INVERT_V 0x1 -#define MCPWM_EXTERNAL_SYNCI0_INVERT_S 9 -/* MCPWM_TIMER2_SYNCISEL : R/W ;bitpos:[8:6] ;default: 3'd0 ; */ -/*description: Select sync input for PWM timer2 1: PWM timer0 synco 2: PWM - timer1 synco 3: PWM timer2 synco 4: SYNC0 from GPIO matrix 5: SYNC1 from GPIO matrix 6: SYNC2 from GPIO matrix other values: no sync input selected*/ -#define MCPWM_TIMER2_SYNCISEL 0x00000007 -#define MCPWM_TIMER2_SYNCISEL_M ((MCPWM_TIMER2_SYNCISEL_V)<<(MCPWM_TIMER2_SYNCISEL_S)) -#define MCPWM_TIMER2_SYNCISEL_V 0x7 -#define MCPWM_TIMER2_SYNCISEL_S 6 -/* MCPWM_TIMER1_SYNCISEL : R/W ;bitpos:[5:3] ;default: 3'd0 ; */ -/*description: Select sync input for PWM timer1 1: PWM timer0 synco 2: PWM - timer1 synco 3: PWM timer2 synco 4: SYNC0 from GPIO matrix 5: SYNC1 from GPIO matrix 6: SYNC2 from GPIO matrix other values: no sync input selected*/ -#define MCPWM_TIMER1_SYNCISEL 0x00000007 -#define MCPWM_TIMER1_SYNCISEL_M ((MCPWM_TIMER1_SYNCISEL_V)<<(MCPWM_TIMER1_SYNCISEL_S)) -#define MCPWM_TIMER1_SYNCISEL_V 0x7 -#define MCPWM_TIMER1_SYNCISEL_S 3 -/* MCPWM_TIMER0_SYNCISEL : R/W ;bitpos:[2:0] ;default: 3'd0 ; */ -/*description: Select sync input for PWM timer0 1: PWM timer0 synco 2: PWM - timer1 synco 3: PWM timer2 synco 4: SYNC0 from GPIO matrix 5: SYNC1 from GPIO matrix 6: SYNC2 from GPIO matrix other values: no sync input selected*/ -#define MCPWM_TIMER0_SYNCISEL 0x00000007 -#define MCPWM_TIMER0_SYNCISEL_M ((MCPWM_TIMER0_SYNCISEL_V)<<(MCPWM_TIMER0_SYNCISEL_S)) -#define MCPWM_TIMER0_SYNCISEL_V 0x7 +/** MCPWM_TIMER_SYNCI_CFG_REG register + * Synchronization input selection for three PWM timers. + */ +#define MCPWM_TIMER_SYNCI_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0x34) +/** MCPWM_TIMER0_SYNCISEL : R/W; bitpos: [2:0]; default: 0; + * select sync input for PWM timer0, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, + * 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: + * SYNC2 from GPIO matrix, other values: no sync input selected + */ +#define MCPWM_TIMER0_SYNCISEL 0x00000007U +#define MCPWM_TIMER0_SYNCISEL_M (MCPWM_TIMER0_SYNCISEL_V << MCPWM_TIMER0_SYNCISEL_S) +#define MCPWM_TIMER0_SYNCISEL_V 0x00000007U #define MCPWM_TIMER0_SYNCISEL_S 0 +/** MCPWM_TIMER1_SYNCISEL : R/W; bitpos: [5:3]; default: 0; + * select sync input for PWM timer1, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, + * 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: + * SYNC2 from GPIO matrix, other values: no sync input selected + */ +#define MCPWM_TIMER1_SYNCISEL 0x00000007U +#define MCPWM_TIMER1_SYNCISEL_M (MCPWM_TIMER1_SYNCISEL_V << MCPWM_TIMER1_SYNCISEL_S) +#define MCPWM_TIMER1_SYNCISEL_V 0x00000007U +#define MCPWM_TIMER1_SYNCISEL_S 3 +/** MCPWM_TIMER2_SYNCISEL : R/W; bitpos: [8:6]; default: 0; + * select sync input for PWM timer2, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, + * 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: + * SYNC2 from GPIO matrix, other values: no sync input selected + */ +#define MCPWM_TIMER2_SYNCISEL 0x00000007U +#define MCPWM_TIMER2_SYNCISEL_M (MCPWM_TIMER2_SYNCISEL_V << MCPWM_TIMER2_SYNCISEL_S) +#define MCPWM_TIMER2_SYNCISEL_V 0x00000007U +#define MCPWM_TIMER2_SYNCISEL_S 6 +/** MCPWM_EXTERNAL_SYNCI0_INVERT : R/W; bitpos: [9]; default: 0; + * invert SYNC0 from GPIO matrix + */ +#define MCPWM_EXTERNAL_SYNCI0_INVERT (BIT(9)) +#define MCPWM_EXTERNAL_SYNCI0_INVERT_M (MCPWM_EXTERNAL_SYNCI0_INVERT_V << MCPWM_EXTERNAL_SYNCI0_INVERT_S) +#define MCPWM_EXTERNAL_SYNCI0_INVERT_V 0x00000001U +#define MCPWM_EXTERNAL_SYNCI0_INVERT_S 9 +/** MCPWM_EXTERNAL_SYNCI1_INVERT : R/W; bitpos: [10]; default: 0; + * invert SYNC1 from GPIO matrix + */ +#define MCPWM_EXTERNAL_SYNCI1_INVERT (BIT(10)) +#define MCPWM_EXTERNAL_SYNCI1_INVERT_M (MCPWM_EXTERNAL_SYNCI1_INVERT_V << MCPWM_EXTERNAL_SYNCI1_INVERT_S) +#define MCPWM_EXTERNAL_SYNCI1_INVERT_V 0x00000001U +#define MCPWM_EXTERNAL_SYNCI1_INVERT_S 10 +/** MCPWM_EXTERNAL_SYNCI2_INVERT : R/W; bitpos: [11]; default: 0; + * invert SYNC2 from GPIO matrix + */ +#define MCPWM_EXTERNAL_SYNCI2_INVERT (BIT(11)) +#define MCPWM_EXTERNAL_SYNCI2_INVERT_M (MCPWM_EXTERNAL_SYNCI2_INVERT_V << MCPWM_EXTERNAL_SYNCI2_INVERT_S) +#define MCPWM_EXTERNAL_SYNCI2_INVERT_V 0x00000001U +#define MCPWM_EXTERNAL_SYNCI2_INVERT_S 11 -#define MCPWM_OPERATOR_TIMERSEL_REG(i) (REG_MCPWM_BASE(i) + 0x0038) -/* MCPWM_OPERATOR2_TIMERSEL : R/W ;bitpos:[5:4] ;default: 2'd0 ; */ -/*description: Select which PWM timer's is the timing reference for PWM operator2 - 0: timer0 1: timer1 2: timer2*/ -#define MCPWM_OPERATOR2_TIMERSEL 0x00000003 -#define MCPWM_OPERATOR2_TIMERSEL_M ((MCPWM_OPERATOR2_TIMERSEL_V)<<(MCPWM_OPERATOR2_TIMERSEL_S)) -#define MCPWM_OPERATOR2_TIMERSEL_V 0x3 -#define MCPWM_OPERATOR2_TIMERSEL_S 4 -/* MCPWM_OPERATOR1_TIMERSEL : R/W ;bitpos:[3:2] ;default: 2'd0 ; */ -/*description: Select which PWM timer's is the timing reference for PWM operator1 - 0: timer0 1: timer1 2: timer2*/ -#define MCPWM_OPERATOR1_TIMERSEL 0x00000003 -#define MCPWM_OPERATOR1_TIMERSEL_M ((MCPWM_OPERATOR1_TIMERSEL_V)<<(MCPWM_OPERATOR1_TIMERSEL_S)) -#define MCPWM_OPERATOR1_TIMERSEL_V 0x3 -#define MCPWM_OPERATOR1_TIMERSEL_S 2 -/* MCPWM_OPERATOR0_TIMERSEL : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: Select which PWM timer's is the timing reference for PWM operator0 - 0: timer0 1: timer1 2: timer2*/ -#define MCPWM_OPERATOR0_TIMERSEL 0x00000003 -#define MCPWM_OPERATOR0_TIMERSEL_M ((MCPWM_OPERATOR0_TIMERSEL_V)<<(MCPWM_OPERATOR0_TIMERSEL_S)) -#define MCPWM_OPERATOR0_TIMERSEL_V 0x3 +/** MCPWM_OPERATOR_TIMERSEL_REG register + * Select specific timer for PWM operators. + */ +#define MCPWM_OPERATOR_TIMERSEL_REG(i) (DR_REG_MCPWM_BASE(i) + 0x38) +/** MCPWM_OPERATOR0_TIMERSEL : R/W; bitpos: [1:0]; default: 0; + * Select which PWM timer is the timing reference for PWM operator0, 0: timer0, 1: + * timer1, 2: timer2 + */ +#define MCPWM_OPERATOR0_TIMERSEL 0x00000003U +#define MCPWM_OPERATOR0_TIMERSEL_M (MCPWM_OPERATOR0_TIMERSEL_V << MCPWM_OPERATOR0_TIMERSEL_S) +#define MCPWM_OPERATOR0_TIMERSEL_V 0x00000003U #define MCPWM_OPERATOR0_TIMERSEL_S 0 +/** MCPWM_OPERATOR1_TIMERSEL : R/W; bitpos: [3:2]; default: 0; + * Select which PWM timer is the timing reference for PWM operator1, 0: timer0, 1: + * timer1, 2: timer2 + */ +#define MCPWM_OPERATOR1_TIMERSEL 0x00000003U +#define MCPWM_OPERATOR1_TIMERSEL_M (MCPWM_OPERATOR1_TIMERSEL_V << MCPWM_OPERATOR1_TIMERSEL_S) +#define MCPWM_OPERATOR1_TIMERSEL_V 0x00000003U +#define MCPWM_OPERATOR1_TIMERSEL_S 2 +/** MCPWM_OPERATOR2_TIMERSEL : R/W; bitpos: [5:4]; default: 0; + * Select which PWM timer is the timing reference for PWM operator2, 0: timer0, 1: + * timer1, 2: timer2 + */ +#define MCPWM_OPERATOR2_TIMERSEL 0x00000003U +#define MCPWM_OPERATOR2_TIMERSEL_M (MCPWM_OPERATOR2_TIMERSEL_V << MCPWM_OPERATOR2_TIMERSEL_S) +#define MCPWM_OPERATOR2_TIMERSEL_V 0x00000003U +#define MCPWM_OPERATOR2_TIMERSEL_S 4 -#define MCPWM_GEN0_STMP_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x003c) -/* MCPWM_GEN0_B_SHDW_FULL : RO ;bitpos:[9] ;default: 1'd0 ; */ -/*description: Set and reset by hardware. If set PWM generator 0 time stamp - B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared B's active reg has been updated with shadow reg latest value*/ -#define MCPWM_GEN0_B_SHDW_FULL (BIT(9)) -#define MCPWM_GEN0_B_SHDW_FULL_M (BIT(9)) -#define MCPWM_GEN0_B_SHDW_FULL_V 0x1 -#define MCPWM_GEN0_B_SHDW_FULL_S 9 -/* MCPWM_GEN0_A_SHDW_FULL : RO ;bitpos:[8] ;default: 1'd0 ; */ -/*description: Set and reset by hardware. If set PWM generator 0 time stamp - A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared A's active reg has been updated with shadow reg latest value*/ -#define MCPWM_GEN0_A_SHDW_FULL (BIT(8)) -#define MCPWM_GEN0_A_SHDW_FULL_M (BIT(8)) -#define MCPWM_GEN0_A_SHDW_FULL_V 0x1 -#define MCPWM_GEN0_A_SHDW_FULL_S 8 -/* MCPWM_GEN0_B_UPMETHOD : R/W ;bitpos:[7:4] ;default: 4'd0 ; */ -/*description: Update method for PWM generator 0 time stamp B's active reg. - 0: immediate bit0: TEZ bit1: TEP bit2: sync bit3: disable update*/ -#define MCPWM_GEN0_B_UPMETHOD 0x0000000F -#define MCPWM_GEN0_B_UPMETHOD_M ((MCPWM_GEN0_B_UPMETHOD_V)<<(MCPWM_GEN0_B_UPMETHOD_S)) -#define MCPWM_GEN0_B_UPMETHOD_V 0xF -#define MCPWM_GEN0_B_UPMETHOD_S 4 -/* MCPWM_GEN0_A_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: Update method for PWM generator 0 time stamp A's active reg. - 0: immediate bit0: TEZ bit1: TEP bit2: sync bit3: disable update*/ -#define MCPWM_GEN0_A_UPMETHOD 0x0000000F -#define MCPWM_GEN0_A_UPMETHOD_M ((MCPWM_GEN0_A_UPMETHOD_V)<<(MCPWM_GEN0_A_UPMETHOD_S)) -#define MCPWM_GEN0_A_UPMETHOD_V 0xF +/** MCPWM_GEN0_STMP_CFG_REG register + * Transfer status and update method for time stamp registers A and B + */ +#define MCPWM_GEN0_STMP_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0x3c) +/** MCPWM_GEN0_A_UPMETHOD : R/W; bitpos: [3:0]; default: 0; + * Update method for PWM generator 0 time stamp A's active register. When all bits are + * set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when + * bit2 is set to 1: sync, when bit3 is set to 1: disable the update. + */ +#define MCPWM_GEN0_A_UPMETHOD 0x0000000FU +#define MCPWM_GEN0_A_UPMETHOD_M (MCPWM_GEN0_A_UPMETHOD_V << MCPWM_GEN0_A_UPMETHOD_S) +#define MCPWM_GEN0_A_UPMETHOD_V 0x0000000FU #define MCPWM_GEN0_A_UPMETHOD_S 0 +/** MCPWM_GEN0_B_UPMETHOD : R/W; bitpos: [7:4]; default: 0; + * Update method for PWM generator 0 time stamp B's active register. When all bits are + * set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when + * bit2 is set to 1: sync, when bit3 is set to 1: disable the update. + */ +#define MCPWM_GEN0_B_UPMETHOD 0x0000000FU +#define MCPWM_GEN0_B_UPMETHOD_M (MCPWM_GEN0_B_UPMETHOD_V << MCPWM_GEN0_B_UPMETHOD_S) +#define MCPWM_GEN0_B_UPMETHOD_V 0x0000000FU +#define MCPWM_GEN0_B_UPMETHOD_S 4 +/** MCPWM_GEN0_A_SHDW_FULL : R/W/WTC/SC; bitpos: [8]; default: 0; + * Set and reset by hardware. If set, PWM generator 0 time stamp A's shadow reg is + * filled and waiting to be transferred to A's active reg. If cleared, A's active reg + * has been updated with shadow register latest value + */ +#define MCPWM_GEN0_A_SHDW_FULL (BIT(8)) +#define MCPWM_GEN0_A_SHDW_FULL_M (MCPWM_GEN0_A_SHDW_FULL_V << MCPWM_GEN0_A_SHDW_FULL_S) +#define MCPWM_GEN0_A_SHDW_FULL_V 0x00000001U +#define MCPWM_GEN0_A_SHDW_FULL_S 8 +/** MCPWM_GEN0_B_SHDW_FULL : R/W/WTC/SC; bitpos: [9]; default: 0; + * Set and reset by hardware. If set, PWM generator 0 time stamp B's shadow reg is + * filled and waiting to be transferred to B's active reg. If cleared, B's active reg + * has been updated with shadow register latest value + */ +#define MCPWM_GEN0_B_SHDW_FULL (BIT(9)) +#define MCPWM_GEN0_B_SHDW_FULL_M (MCPWM_GEN0_B_SHDW_FULL_V << MCPWM_GEN0_B_SHDW_FULL_S) +#define MCPWM_GEN0_B_SHDW_FULL_V 0x00000001U +#define MCPWM_GEN0_B_SHDW_FULL_S 9 -#define MCPWM_GEN0_TSTMP_A_REG(i) (REG_MCPWM_BASE(i) + 0x0040) -/* MCPWM_GEN0_A : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ -/*description: PWM generator 0 time stamp A's shadow reg*/ -#define MCPWM_GEN0_A 0x0000FFFF -#define MCPWM_GEN0_A_M ((MCPWM_GEN0_A_V)<<(MCPWM_GEN0_A_S)) -#define MCPWM_GEN0_A_V 0xFFFF +/** MCPWM_GEN0_TSTMP_A_REG register + * PWM generator 0 shadow register for timer stamp A. + */ +#define MCPWM_GEN0_TSTMP_A_REG(i) (DR_REG_MCPWM_BASE(i) + 0x40) +/** MCPWM_GEN0_A : R/W; bitpos: [15:0]; default: 0; + * PWM generator 0 time stamp A's shadow register + */ +#define MCPWM_GEN0_A 0x0000FFFFU +#define MCPWM_GEN0_A_M (MCPWM_GEN0_A_V << MCPWM_GEN0_A_S) +#define MCPWM_GEN0_A_V 0x0000FFFFU #define MCPWM_GEN0_A_S 0 -#define MCPWM_GEN0_TSTMP_B_REG(i) (REG_MCPWM_BASE(i) + 0x0044) -/* MCPWM_GEN0_B : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ -/*description: PWM generator 0 time stamp B's shadow reg*/ -#define MCPWM_GEN0_B 0x0000FFFF -#define MCPWM_GEN0_B_M ((MCPWM_GEN0_B_V)<<(MCPWM_GEN0_B_S)) -#define MCPWM_GEN0_B_V 0xFFFF +/** MCPWM_GEN0_TSTMP_B_REG register + * PWM generator 0 shadow register for timer stamp B. + */ +#define MCPWM_GEN0_TSTMP_B_REG(i) (DR_REG_MCPWM_BASE(i) + 0x44) +/** MCPWM_GEN0_B : R/W; bitpos: [15:0]; default: 0; + * PWM generator 0 time stamp B's shadow register + */ +#define MCPWM_GEN0_B 0x0000FFFFU +#define MCPWM_GEN0_B_M (MCPWM_GEN0_B_V << MCPWM_GEN0_B_S) +#define MCPWM_GEN0_B_V 0x0000FFFFU #define MCPWM_GEN0_B_S 0 -#define MCPWM_GEN0_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x0048) -/* MCPWM_GEN0_T1_SEL : R/W ;bitpos:[9:7] ;default: 3'd0 ; */ -/*description: Source selection for PWM generator 0 event_t1 take effect immediately - 0: fault_event0 1: fault_event1 2: fault_event2 3: sync_taken 4: none*/ -#define MCPWM_GEN0_T1_SEL 0x00000007 -#define MCPWM_GEN0_T1_SEL_M ((MCPWM_GEN0_T1_SEL_V)<<(MCPWM_GEN0_T1_SEL_S)) -#define MCPWM_GEN0_T1_SEL_V 0x7 -#define MCPWM_GEN0_T1_SEL_S 7 -/* MCPWM_GEN0_T0_SEL : R/W ;bitpos:[6:4] ;default: 3'd0 ; */ -/*description: Source selection for PWM generator 0 event_t0 take effect immediately - 0: fault_event0 1: fault_event1 2: fault_event2 3: sync_taken 4: none*/ -#define MCPWM_GEN0_T0_SEL 0x00000007 -#define MCPWM_GEN0_T0_SEL_M ((MCPWM_GEN0_T0_SEL_V)<<(MCPWM_GEN0_T0_SEL_S)) -#define MCPWM_GEN0_T0_SEL_V 0x7 -#define MCPWM_GEN0_T0_SEL_S 4 -/* MCPWM_GEN0_CFG_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: Update method for PWM generator 0's active reg of configuration. - 0: immediate bit0: TEZ bit1: TEP bit2: sync. bit3: disable update*/ -#define MCPWM_GEN0_CFG_UPMETHOD 0x0000000F -#define MCPWM_GEN0_CFG_UPMETHOD_M ((MCPWM_GEN0_CFG_UPMETHOD_V)<<(MCPWM_GEN0_CFG_UPMETHOD_S)) -#define MCPWM_GEN0_CFG_UPMETHOD_V 0xF +/** MCPWM_GEN0_CFG0_REG register + * PWM generator 0 event T0 and T1 handling + */ +#define MCPWM_GEN0_CFG0_REG(i) (DR_REG_MCPWM_BASE(i) + 0x48) +/** MCPWM_GEN0_CFG_UPMETHOD : R/W; bitpos: [3:0]; default: 0; + * Update method for PWM generator 0's active register of configuration. When all bits + * are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to + * 1:TEP,when bit2 is set to 1:sync,when bit3 is set to 1:disable the update + */ +#define MCPWM_GEN0_CFG_UPMETHOD 0x0000000FU +#define MCPWM_GEN0_CFG_UPMETHOD_M (MCPWM_GEN0_CFG_UPMETHOD_V << MCPWM_GEN0_CFG_UPMETHOD_S) +#define MCPWM_GEN0_CFG_UPMETHOD_V 0x0000000FU #define MCPWM_GEN0_CFG_UPMETHOD_S 0 +/** MCPWM_GEN0_T0_SEL : R/W; bitpos: [6:4]; default: 0; + * Source selection for PWM generator 0 event_t0, take effect immediately, 0: + * fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none + */ +#define MCPWM_GEN0_T0_SEL 0x00000007U +#define MCPWM_GEN0_T0_SEL_M (MCPWM_GEN0_T0_SEL_V << MCPWM_GEN0_T0_SEL_S) +#define MCPWM_GEN0_T0_SEL_V 0x00000007U +#define MCPWM_GEN0_T0_SEL_S 4 +/** MCPWM_GEN0_T1_SEL : R/W; bitpos: [9:7]; default: 0; + * Source selection for PWM generator 0 event_t1, take effect immediately, 0: + * fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none + */ +#define MCPWM_GEN0_T1_SEL 0x00000007U +#define MCPWM_GEN0_T1_SEL_M (MCPWM_GEN0_T1_SEL_V << MCPWM_GEN0_T1_SEL_S) +#define MCPWM_GEN0_T1_SEL_V 0x00000007U +#define MCPWM_GEN0_T1_SEL_S 7 -#define MCPWM_GEN0_FORCE_REG(i) (REG_MCPWM_BASE(i) + 0x004c) -/* MCPWM_GEN0_B_NCIFORCE_MODE : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ -/*description: Non-continuous immediate software force mode for PWM0B 0: disabled - 1: low 2: high 3: disabled*/ -#define MCPWM_GEN0_B_NCIFORCE_MODE 0x00000003 -#define MCPWM_GEN0_B_NCIFORCE_MODE_M ((MCPWM_GEN0_B_NCIFORCE_MODE_V)<<(MCPWM_GEN0_B_NCIFORCE_MODE_S)) -#define MCPWM_GEN0_B_NCIFORCE_MODE_V 0x3 -#define MCPWM_GEN0_B_NCIFORCE_MODE_S 14 -/* MCPWM_GEN0_B_NCIFORCE : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: Non-continuous immediate software force trigger for PWM0B a - toggle will trigger a force event*/ -#define MCPWM_GEN0_B_NCIFORCE (BIT(13)) -#define MCPWM_GEN0_B_NCIFORCE_M (BIT(13)) -#define MCPWM_GEN0_B_NCIFORCE_V 0x1 -#define MCPWM_GEN0_B_NCIFORCE_S 13 -/* MCPWM_GEN0_A_NCIFORCE_MODE : R/W ;bitpos:[12:11] ;default: 2'd0 ; */ -/*description: Non-continuous immediate software force mode for PWM0A 0: disabled - 1: low 2: high 3: disabled*/ -#define MCPWM_GEN0_A_NCIFORCE_MODE 0x00000003 -#define MCPWM_GEN0_A_NCIFORCE_MODE_M ((MCPWM_GEN0_A_NCIFORCE_MODE_V)<<(MCPWM_GEN0_A_NCIFORCE_MODE_S)) -#define MCPWM_GEN0_A_NCIFORCE_MODE_V 0x3 -#define MCPWM_GEN0_A_NCIFORCE_MODE_S 11 -/* MCPWM_GEN0_A_NCIFORCE : R/W ;bitpos:[10] ;default: 1'd0 ; */ -/*description: Non-continuous immediate software force trigger for PWM0A a - toggle will trigger a force event*/ -#define MCPWM_GEN0_A_NCIFORCE (BIT(10)) -#define MCPWM_GEN0_A_NCIFORCE_M (BIT(10)) -#define MCPWM_GEN0_A_NCIFORCE_V 0x1 -#define MCPWM_GEN0_A_NCIFORCE_S 10 -/* MCPWM_GEN0_B_CNTUFORCE_MODE : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ -/*description: Continuous software force mode for PWM0B. 0: disabled 1: low - 2: high 3: disabled*/ -#define MCPWM_GEN0_B_CNTUFORCE_MODE 0x00000003 -#define MCPWM_GEN0_B_CNTUFORCE_MODE_M ((MCPWM_GEN0_B_CNTUFORCE_MODE_V)<<(MCPWM_GEN0_B_CNTUFORCE_MODE_S)) -#define MCPWM_GEN0_B_CNTUFORCE_MODE_V 0x3 -#define MCPWM_GEN0_B_CNTUFORCE_MODE_S 8 -/* MCPWM_GEN0_A_CNTUFORCE_MODE : R/W ;bitpos:[7:6] ;default: 2'd0 ; */ -/*description: Continuous software force mode for PWM0A. 0: disabled 1: low - 2: high 3: disabled*/ -#define MCPWM_GEN0_A_CNTUFORCE_MODE 0x00000003 -#define MCPWM_GEN0_A_CNTUFORCE_MODE_M ((MCPWM_GEN0_A_CNTUFORCE_MODE_V)<<(MCPWM_GEN0_A_CNTUFORCE_MODE_S)) -#define MCPWM_GEN0_A_CNTUFORCE_MODE_V 0x3 -#define MCPWM_GEN0_A_CNTUFORCE_MODE_S 6 -/* MCPWM_GEN0_CNTUFORCE_UPMETHOD : R/W ;bitpos:[5:0] ;default: 6'h20 ; */ -/*description: Update method for continuous software force of PWM generator0. - 0: immediate bit0: TEZ bit1: TEP bit2: TEA bit3: TEB bit4: sync bit5: disable update. (TEA/B here and below means an event generated when timer value equals A/B register)*/ -#define MCPWM_GEN0_CNTUFORCE_UPMETHOD 0x0000003F -#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_M ((MCPWM_GEN0_CNTUFORCE_UPMETHOD_V)<<(MCPWM_GEN0_CNTUFORCE_UPMETHOD_S)) -#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_V 0x3F +/** MCPWM_GEN0_FORCE_REG register + * Permissives to force PWM0A and PWM0B outputs by software + */ +#define MCPWM_GEN0_FORCE_REG(i) (DR_REG_MCPWM_BASE(i) + 0x4c) +/** MCPWM_GEN0_CNTUFORCE_UPMETHOD : R/W; bitpos: [5:0]; default: 32; + * Updating method for continuous software force of PWM generator0. When all bits are + * set to 0: immediately, when bit0 is set to 1: TEZ,,when bit1 is set to 1: TEP, when + * bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync, + * when bit5 is set to 1: disable update. (TEA/B here and below means an event + * generated when the timer's value equals to that of register A/B.) + */ +#define MCPWM_GEN0_CNTUFORCE_UPMETHOD 0x0000003FU +#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_M (MCPWM_GEN0_CNTUFORCE_UPMETHOD_V << MCPWM_GEN0_CNTUFORCE_UPMETHOD_S) +#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_V 0x0000003FU #define MCPWM_GEN0_CNTUFORCE_UPMETHOD_S 0 +/** MCPWM_GEN0_A_CNTUFORCE_MODE : R/W; bitpos: [7:6]; default: 0; + * Continuous software force mode for PWM0A. 0: disabled, 1: low, 2: high, 3: disabled + */ +#define MCPWM_GEN0_A_CNTUFORCE_MODE 0x00000003U +#define MCPWM_GEN0_A_CNTUFORCE_MODE_M (MCPWM_GEN0_A_CNTUFORCE_MODE_V << MCPWM_GEN0_A_CNTUFORCE_MODE_S) +#define MCPWM_GEN0_A_CNTUFORCE_MODE_V 0x00000003U +#define MCPWM_GEN0_A_CNTUFORCE_MODE_S 6 +/** MCPWM_GEN0_B_CNTUFORCE_MODE : R/W; bitpos: [9:8]; default: 0; + * Continuous software force mode for PWM0B. 0: disabled, 1: low, 2: high, 3: disabled + */ +#define MCPWM_GEN0_B_CNTUFORCE_MODE 0x00000003U +#define MCPWM_GEN0_B_CNTUFORCE_MODE_M (MCPWM_GEN0_B_CNTUFORCE_MODE_V << MCPWM_GEN0_B_CNTUFORCE_MODE_S) +#define MCPWM_GEN0_B_CNTUFORCE_MODE_V 0x00000003U +#define MCPWM_GEN0_B_CNTUFORCE_MODE_S 8 +/** MCPWM_GEN0_A_NCIFORCE : R/W; bitpos: [10]; default: 0; + * Trigger of non-continuous immediate software-force event for PWM0A, a toggle will + * trigger a force event. + */ +#define MCPWM_GEN0_A_NCIFORCE (BIT(10)) +#define MCPWM_GEN0_A_NCIFORCE_M (MCPWM_GEN0_A_NCIFORCE_V << MCPWM_GEN0_A_NCIFORCE_S) +#define MCPWM_GEN0_A_NCIFORCE_V 0x00000001U +#define MCPWM_GEN0_A_NCIFORCE_S 10 +/** MCPWM_GEN0_A_NCIFORCE_MODE : R/W; bitpos: [12:11]; default: 0; + * non-continuous immediate software force mode for PWM0A, 0: disabled, 1: low, 2: + * high, 3: disabled + */ +#define MCPWM_GEN0_A_NCIFORCE_MODE 0x00000003U +#define MCPWM_GEN0_A_NCIFORCE_MODE_M (MCPWM_GEN0_A_NCIFORCE_MODE_V << MCPWM_GEN0_A_NCIFORCE_MODE_S) +#define MCPWM_GEN0_A_NCIFORCE_MODE_V 0x00000003U +#define MCPWM_GEN0_A_NCIFORCE_MODE_S 11 +/** MCPWM_GEN0_B_NCIFORCE : R/W; bitpos: [13]; default: 0; + * Trigger of non-continuous immediate software-force event for PWM0B, a toggle will + * trigger a force event. + */ +#define MCPWM_GEN0_B_NCIFORCE (BIT(13)) +#define MCPWM_GEN0_B_NCIFORCE_M (MCPWM_GEN0_B_NCIFORCE_V << MCPWM_GEN0_B_NCIFORCE_S) +#define MCPWM_GEN0_B_NCIFORCE_V 0x00000001U +#define MCPWM_GEN0_B_NCIFORCE_S 13 +/** MCPWM_GEN0_B_NCIFORCE_MODE : R/W; bitpos: [15:14]; default: 0; + * non-continuous immediate software force mode for PWM0B, 0: disabled, 1: low, 2: + * high, 3: disabled + */ +#define MCPWM_GEN0_B_NCIFORCE_MODE 0x00000003U +#define MCPWM_GEN0_B_NCIFORCE_MODE_M (MCPWM_GEN0_B_NCIFORCE_MODE_V << MCPWM_GEN0_B_NCIFORCE_MODE_S) +#define MCPWM_GEN0_B_NCIFORCE_MODE_V 0x00000003U +#define MCPWM_GEN0_B_NCIFORCE_MODE_S 14 -#define MCPWM_GEN0_A_REG(i) (REG_MCPWM_BASE(i) + 0x0050) -/* MCPWM_GEN0_A_DT1 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ -/*description: Action on PWM0A triggered by event_t1 when timer decreasing. - 0: no change 1: low 2: high 3: toggle*/ -#define MCPWM_GEN0_A_DT1 0x00000003 -#define MCPWM_GEN0_A_DT1_M ((MCPWM_GEN0_A_DT1_V)<<(MCPWM_GEN0_A_DT1_S)) -#define MCPWM_GEN0_A_DT1_V 0x3 -#define MCPWM_GEN0_A_DT1_S 22 -/* MCPWM_GEN0_A_DT0 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ -/*description: Action on PWM0A triggered by event_t0 when timer decreasing*/ -#define MCPWM_GEN0_A_DT0 0x00000003 -#define MCPWM_GEN0_A_DT0_M ((MCPWM_GEN0_A_DT0_V)<<(MCPWM_GEN0_A_DT0_S)) -#define MCPWM_GEN0_A_DT0_V 0x3 -#define MCPWM_GEN0_A_DT0_S 20 -/* MCPWM_GEN0_A_DTEB : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ -/*description: Action on PWM0A triggered by event TEB when timer decreasing*/ -#define MCPWM_GEN0_A_DTEB 0x00000003 -#define MCPWM_GEN0_A_DTEB_M ((MCPWM_GEN0_A_DTEB_V)<<(MCPWM_GEN0_A_DTEB_S)) -#define MCPWM_GEN0_A_DTEB_V 0x3 -#define MCPWM_GEN0_A_DTEB_S 18 -/* MCPWM_GEN0_A_DTEA : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ -/*description: Action on PWM0A triggered by event TEA when timer decreasing*/ -#define MCPWM_GEN0_A_DTEA 0x00000003 -#define MCPWM_GEN0_A_DTEA_M ((MCPWM_GEN0_A_DTEA_V)<<(MCPWM_GEN0_A_DTEA_S)) -#define MCPWM_GEN0_A_DTEA_V 0x3 -#define MCPWM_GEN0_A_DTEA_S 16 -/* MCPWM_GEN0_A_DTEP : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ -/*description: Action on PWM0A triggered by event TEP when timer decreasing*/ -#define MCPWM_GEN0_A_DTEP 0x00000003 -#define MCPWM_GEN0_A_DTEP_M ((MCPWM_GEN0_A_DTEP_V)<<(MCPWM_GEN0_A_DTEP_S)) -#define MCPWM_GEN0_A_DTEP_V 0x3 -#define MCPWM_GEN0_A_DTEP_S 14 -/* MCPWM_GEN0_A_DTEZ : R/W ;bitpos:[13:12] ;default: 2'd0 ; */ -/*description: Action on PWM0A triggered by event TEZ when timer decreasing*/ -#define MCPWM_GEN0_A_DTEZ 0x00000003 -#define MCPWM_GEN0_A_DTEZ_M ((MCPWM_GEN0_A_DTEZ_V)<<(MCPWM_GEN0_A_DTEZ_S)) -#define MCPWM_GEN0_A_DTEZ_V 0x3 -#define MCPWM_GEN0_A_DTEZ_S 12 -/* MCPWM_GEN0_A_UT1 : R/W ;bitpos:[11:10] ;default: 2'd0 ; */ -/*description: Action on PWM0A triggered by event_t1 when timer increasing*/ -#define MCPWM_GEN0_A_UT1 0x00000003 -#define MCPWM_GEN0_A_UT1_M ((MCPWM_GEN0_A_UT1_V)<<(MCPWM_GEN0_A_UT1_S)) -#define MCPWM_GEN0_A_UT1_V 0x3 -#define MCPWM_GEN0_A_UT1_S 10 -/* MCPWM_GEN0_A_UT0 : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ -/*description: Action on PWM0A triggered by event_t0 when timer increasing*/ -#define MCPWM_GEN0_A_UT0 0x00000003 -#define MCPWM_GEN0_A_UT0_M ((MCPWM_GEN0_A_UT0_V)<<(MCPWM_GEN0_A_UT0_S)) -#define MCPWM_GEN0_A_UT0_V 0x3 -#define MCPWM_GEN0_A_UT0_S 8 -/* MCPWM_GEN0_A_UTEB : R/W ;bitpos:[7:6] ;default: 2'd0 ; */ -/*description: Action on PWM0A triggered by event TEB when timer increasing*/ -#define MCPWM_GEN0_A_UTEB 0x00000003 -#define MCPWM_GEN0_A_UTEB_M ((MCPWM_GEN0_A_UTEB_V)<<(MCPWM_GEN0_A_UTEB_S)) -#define MCPWM_GEN0_A_UTEB_V 0x3 -#define MCPWM_GEN0_A_UTEB_S 6 -/* MCPWM_GEN0_A_UTEA : R/W ;bitpos:[5:4] ;default: 2'd0 ; */ -/*description: Action on PWM0A triggered by event TEA when timer increasing*/ -#define MCPWM_GEN0_A_UTEA 0x00000003 -#define MCPWM_GEN0_A_UTEA_M ((MCPWM_GEN0_A_UTEA_V)<<(MCPWM_GEN0_A_UTEA_S)) -#define MCPWM_GEN0_A_UTEA_V 0x3 -#define MCPWM_GEN0_A_UTEA_S 4 -/* MCPWM_GEN0_A_UTEP : R/W ;bitpos:[3:2] ;default: 2'd0 ; */ -/*description: Action on PWM0A triggered by event TEP when timer increasing*/ -#define MCPWM_GEN0_A_UTEP 0x00000003 -#define MCPWM_GEN0_A_UTEP_M ((MCPWM_GEN0_A_UTEP_V)<<(MCPWM_GEN0_A_UTEP_S)) -#define MCPWM_GEN0_A_UTEP_V 0x3 -#define MCPWM_GEN0_A_UTEP_S 2 -/* MCPWM_GEN0_A_UTEZ : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: Action on PWM0A triggered by event TEZ when timer increasing*/ -#define MCPWM_GEN0_A_UTEZ 0x00000003 -#define MCPWM_GEN0_A_UTEZ_M ((MCPWM_GEN0_A_UTEZ_V)<<(MCPWM_GEN0_A_UTEZ_S)) -#define MCPWM_GEN0_A_UTEZ_V 0x3 +/** MCPWM_GEN0_A_REG register + * Actions triggered by events on PWM0A + */ +#define MCPWM_GEN0_A_REG(i) (DR_REG_MCPWM_BASE(i) + 0x50) +/** MCPWM_GEN0_A_UTEZ : R/W; bitpos: [1:0]; default: 0; + * Action on PWM0A triggered by event TEZ when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN0_A_UTEZ 0x00000003U +#define MCPWM_GEN0_A_UTEZ_M (MCPWM_GEN0_A_UTEZ_V << MCPWM_GEN0_A_UTEZ_S) +#define MCPWM_GEN0_A_UTEZ_V 0x00000003U #define MCPWM_GEN0_A_UTEZ_S 0 +/** MCPWM_GEN0_A_UTEP : R/W; bitpos: [3:2]; default: 0; + * Action on PWM0A triggered by event TEP when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN0_A_UTEP 0x00000003U +#define MCPWM_GEN0_A_UTEP_M (MCPWM_GEN0_A_UTEP_V << MCPWM_GEN0_A_UTEP_S) +#define MCPWM_GEN0_A_UTEP_V 0x00000003U +#define MCPWM_GEN0_A_UTEP_S 2 +/** MCPWM_GEN0_A_UTEA : R/W; bitpos: [5:4]; default: 0; + * Action on PWM0A triggered by event TEA when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN0_A_UTEA 0x00000003U +#define MCPWM_GEN0_A_UTEA_M (MCPWM_GEN0_A_UTEA_V << MCPWM_GEN0_A_UTEA_S) +#define MCPWM_GEN0_A_UTEA_V 0x00000003U +#define MCPWM_GEN0_A_UTEA_S 4 +/** MCPWM_GEN0_A_UTEB : R/W; bitpos: [7:6]; default: 0; + * Action on PWM0A triggered by event TEB when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN0_A_UTEB 0x00000003U +#define MCPWM_GEN0_A_UTEB_M (MCPWM_GEN0_A_UTEB_V << MCPWM_GEN0_A_UTEB_S) +#define MCPWM_GEN0_A_UTEB_V 0x00000003U +#define MCPWM_GEN0_A_UTEB_S 6 +/** MCPWM_GEN0_A_UT0 : R/W; bitpos: [9:8]; default: 0; + * Action on PWM0A triggered by event_t0 when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN0_A_UT0 0x00000003U +#define MCPWM_GEN0_A_UT0_M (MCPWM_GEN0_A_UT0_V << MCPWM_GEN0_A_UT0_S) +#define MCPWM_GEN0_A_UT0_V 0x00000003U +#define MCPWM_GEN0_A_UT0_S 8 +/** MCPWM_GEN0_A_UT1 : R/W; bitpos: [11:10]; default: 0; + * Action on PWM0A triggered by event_t1 when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN0_A_UT1 0x00000003U +#define MCPWM_GEN0_A_UT1_M (MCPWM_GEN0_A_UT1_V << MCPWM_GEN0_A_UT1_S) +#define MCPWM_GEN0_A_UT1_V 0x00000003U +#define MCPWM_GEN0_A_UT1_S 10 +/** MCPWM_GEN0_A_DTEZ : R/W; bitpos: [13:12]; default: 0; + * Action on PWM0A triggered by event TEZ when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN0_A_DTEZ 0x00000003U +#define MCPWM_GEN0_A_DTEZ_M (MCPWM_GEN0_A_DTEZ_V << MCPWM_GEN0_A_DTEZ_S) +#define MCPWM_GEN0_A_DTEZ_V 0x00000003U +#define MCPWM_GEN0_A_DTEZ_S 12 +/** MCPWM_GEN0_A_DTEP : R/W; bitpos: [15:14]; default: 0; + * Action on PWM0A triggered by event TEP when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN0_A_DTEP 0x00000003U +#define MCPWM_GEN0_A_DTEP_M (MCPWM_GEN0_A_DTEP_V << MCPWM_GEN0_A_DTEP_S) +#define MCPWM_GEN0_A_DTEP_V 0x00000003U +#define MCPWM_GEN0_A_DTEP_S 14 +/** MCPWM_GEN0_A_DTEA : R/W; bitpos: [17:16]; default: 0; + * Action on PWM0A triggered by event TEA when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN0_A_DTEA 0x00000003U +#define MCPWM_GEN0_A_DTEA_M (MCPWM_GEN0_A_DTEA_V << MCPWM_GEN0_A_DTEA_S) +#define MCPWM_GEN0_A_DTEA_V 0x00000003U +#define MCPWM_GEN0_A_DTEA_S 16 +/** MCPWM_GEN0_A_DTEB : R/W; bitpos: [19:18]; default: 0; + * Action on PWM0A triggered by event TEB when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN0_A_DTEB 0x00000003U +#define MCPWM_GEN0_A_DTEB_M (MCPWM_GEN0_A_DTEB_V << MCPWM_GEN0_A_DTEB_S) +#define MCPWM_GEN0_A_DTEB_V 0x00000003U +#define MCPWM_GEN0_A_DTEB_S 18 +/** MCPWM_GEN0_A_DT0 : R/W; bitpos: [21:20]; default: 0; + * Action on PWM0A triggered by event_t0 when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN0_A_DT0 0x00000003U +#define MCPWM_GEN0_A_DT0_M (MCPWM_GEN0_A_DT0_V << MCPWM_GEN0_A_DT0_S) +#define MCPWM_GEN0_A_DT0_V 0x00000003U +#define MCPWM_GEN0_A_DT0_S 20 +/** MCPWM_GEN0_A_DT1 : R/W; bitpos: [23:22]; default: 0; + * Action on PWM0A triggered by event_t1 when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN0_A_DT1 0x00000003U +#define MCPWM_GEN0_A_DT1_M (MCPWM_GEN0_A_DT1_V << MCPWM_GEN0_A_DT1_S) +#define MCPWM_GEN0_A_DT1_V 0x00000003U +#define MCPWM_GEN0_A_DT1_S 22 -#define MCPWM_GEN0_B_REG(i) (REG_MCPWM_BASE(i) + 0x0054) -/* MCPWM_GEN0_B_DT1 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ -/*description: Action on PWM0B triggered by event_t1 when timer decreasing. - 0: no change 1: low 2: high 3: toggle*/ -#define MCPWM_GEN0_B_DT1 0x00000003 -#define MCPWM_GEN0_B_DT1_M ((MCPWM_GEN0_B_DT1_V)<<(MCPWM_GEN0_B_DT1_S)) -#define MCPWM_GEN0_B_DT1_V 0x3 -#define MCPWM_GEN0_B_DT1_S 22 -/* MCPWM_GEN0_B_DT0 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ -/*description: Action on PWM0B triggered by event_t0 when timer decreasing*/ -#define MCPWM_GEN0_B_DT0 0x00000003 -#define MCPWM_GEN0_B_DT0_M ((MCPWM_GEN0_B_DT0_V)<<(MCPWM_GEN0_B_DT0_S)) -#define MCPWM_GEN0_B_DT0_V 0x3 -#define MCPWM_GEN0_B_DT0_S 20 -/* MCPWM_GEN0_B_DTEB : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ -/*description: Action on PWM0B triggered by event TEB when timer decreasing*/ -#define MCPWM_GEN0_B_DTEB 0x00000003 -#define MCPWM_GEN0_B_DTEB_M ((MCPWM_GEN0_B_DTEB_V)<<(MCPWM_GEN0_B_DTEB_S)) -#define MCPWM_GEN0_B_DTEB_V 0x3 -#define MCPWM_GEN0_B_DTEB_S 18 -/* MCPWM_GEN0_B_DTEA : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ -/*description: Action on PWM0B triggered by event TEA when timer decreasing*/ -#define MCPWM_GEN0_B_DTEA 0x00000003 -#define MCPWM_GEN0_B_DTEA_M ((MCPWM_GEN0_B_DTEA_V)<<(MCPWM_GEN0_B_DTEA_S)) -#define MCPWM_GEN0_B_DTEA_V 0x3 -#define MCPWM_GEN0_B_DTEA_S 16 -/* MCPWM_GEN0_B_DTEP : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ -/*description: Action on PWM0B triggered by event TEP when timer decreasing*/ -#define MCPWM_GEN0_B_DTEP 0x00000003 -#define MCPWM_GEN0_B_DTEP_M ((MCPWM_GEN0_B_DTEP_V)<<(MCPWM_GEN0_B_DTEP_S)) -#define MCPWM_GEN0_B_DTEP_V 0x3 -#define MCPWM_GEN0_B_DTEP_S 14 -/* MCPWM_GEN0_B_DTEZ : R/W ;bitpos:[13:12] ;default: 2'd0 ; */ -/*description: Action on PWM0B triggered by event TEZ when timer decreasing*/ -#define MCPWM_GEN0_B_DTEZ 0x00000003 -#define MCPWM_GEN0_B_DTEZ_M ((MCPWM_GEN0_B_DTEZ_V)<<(MCPWM_GEN0_B_DTEZ_S)) -#define MCPWM_GEN0_B_DTEZ_V 0x3 -#define MCPWM_GEN0_B_DTEZ_S 12 -/* MCPWM_GEN0_B_UT1 : R/W ;bitpos:[11:10] ;default: 2'd0 ; */ -/*description: Action on PWM0B triggered by event_t1 when timer increasing*/ -#define MCPWM_GEN0_B_UT1 0x00000003 -#define MCPWM_GEN0_B_UT1_M ((MCPWM_GEN0_B_UT1_V)<<(MCPWM_GEN0_B_UT1_S)) -#define MCPWM_GEN0_B_UT1_V 0x3 -#define MCPWM_GEN0_B_UT1_S 10 -/* MCPWM_GEN0_B_UT0 : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ -/*description: Action on PWM0B triggered by event_t0 when timer increasing*/ -#define MCPWM_GEN0_B_UT0 0x00000003 -#define MCPWM_GEN0_B_UT0_M ((MCPWM_GEN0_B_UT0_V)<<(MCPWM_GEN0_B_UT0_S)) -#define MCPWM_GEN0_B_UT0_V 0x3 -#define MCPWM_GEN0_B_UT0_S 8 -/* MCPWM_GEN0_B_UTEB : R/W ;bitpos:[7:6] ;default: 2'd0 ; */ -/*description: Action on PWM0B triggered by event TEB when timer increasing*/ -#define MCPWM_GEN0_B_UTEB 0x00000003 -#define MCPWM_GEN0_B_UTEB_M ((MCPWM_GEN0_B_UTEB_V)<<(MCPWM_GEN0_B_UTEB_S)) -#define MCPWM_GEN0_B_UTEB_V 0x3 -#define MCPWM_GEN0_B_UTEB_S 6 -/* MCPWM_GEN0_B_UTEA : R/W ;bitpos:[5:4] ;default: 2'd0 ; */ -/*description: Action on PWM0B triggered by event TEA when timer increasing*/ -#define MCPWM_GEN0_B_UTEA 0x00000003 -#define MCPWM_GEN0_B_UTEA_M ((MCPWM_GEN0_B_UTEA_V)<<(MCPWM_GEN0_B_UTEA_S)) -#define MCPWM_GEN0_B_UTEA_V 0x3 -#define MCPWM_GEN0_B_UTEA_S 4 -/* MCPWM_GEN0_B_UTEP : R/W ;bitpos:[3:2] ;default: 2'd0 ; */ -/*description: Action on PWM0B triggered by event TEP when timer increasing*/ -#define MCPWM_GEN0_B_UTEP 0x00000003 -#define MCPWM_GEN0_B_UTEP_M ((MCPWM_GEN0_B_UTEP_V)<<(MCPWM_GEN0_B_UTEP_S)) -#define MCPWM_GEN0_B_UTEP_V 0x3 -#define MCPWM_GEN0_B_UTEP_S 2 -/* MCPWM_GEN0_B_UTEZ : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: Action on PWM0B triggered by event TEZ when timer increasing*/ -#define MCPWM_GEN0_B_UTEZ 0x00000003 -#define MCPWM_GEN0_B_UTEZ_M ((MCPWM_GEN0_B_UTEZ_V)<<(MCPWM_GEN0_B_UTEZ_S)) -#define MCPWM_GEN0_B_UTEZ_V 0x3 +/** MCPWM_GEN0_B_REG register + * Actions triggered by events on PWM0B + */ +#define MCPWM_GEN0_B_REG(i) (DR_REG_MCPWM_BASE(i) + 0x54) +/** MCPWM_GEN0_B_UTEZ : R/W; bitpos: [1:0]; default: 0; + * Action on PWM0B triggered by event TEZ when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN0_B_UTEZ 0x00000003U +#define MCPWM_GEN0_B_UTEZ_M (MCPWM_GEN0_B_UTEZ_V << MCPWM_GEN0_B_UTEZ_S) +#define MCPWM_GEN0_B_UTEZ_V 0x00000003U #define MCPWM_GEN0_B_UTEZ_S 0 +/** MCPWM_GEN0_B_UTEP : R/W; bitpos: [3:2]; default: 0; + * Action on PWM0B triggered by event TEP when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN0_B_UTEP 0x00000003U +#define MCPWM_GEN0_B_UTEP_M (MCPWM_GEN0_B_UTEP_V << MCPWM_GEN0_B_UTEP_S) +#define MCPWM_GEN0_B_UTEP_V 0x00000003U +#define MCPWM_GEN0_B_UTEP_S 2 +/** MCPWM_GEN0_B_UTEA : R/W; bitpos: [5:4]; default: 0; + * Action on PWM0B triggered by event TEA when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN0_B_UTEA 0x00000003U +#define MCPWM_GEN0_B_UTEA_M (MCPWM_GEN0_B_UTEA_V << MCPWM_GEN0_B_UTEA_S) +#define MCPWM_GEN0_B_UTEA_V 0x00000003U +#define MCPWM_GEN0_B_UTEA_S 4 +/** MCPWM_GEN0_B_UTEB : R/W; bitpos: [7:6]; default: 0; + * Action on PWM0B triggered by event TEB when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN0_B_UTEB 0x00000003U +#define MCPWM_GEN0_B_UTEB_M (MCPWM_GEN0_B_UTEB_V << MCPWM_GEN0_B_UTEB_S) +#define MCPWM_GEN0_B_UTEB_V 0x00000003U +#define MCPWM_GEN0_B_UTEB_S 6 +/** MCPWM_GEN0_B_UT0 : R/W; bitpos: [9:8]; default: 0; + * Action on PWM0B triggered by event_t0 when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN0_B_UT0 0x00000003U +#define MCPWM_GEN0_B_UT0_M (MCPWM_GEN0_B_UT0_V << MCPWM_GEN0_B_UT0_S) +#define MCPWM_GEN0_B_UT0_V 0x00000003U +#define MCPWM_GEN0_B_UT0_S 8 +/** MCPWM_GEN0_B_UT1 : R/W; bitpos: [11:10]; default: 0; + * Action on PWM0B triggered by event_t1 when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN0_B_UT1 0x00000003U +#define MCPWM_GEN0_B_UT1_M (MCPWM_GEN0_B_UT1_V << MCPWM_GEN0_B_UT1_S) +#define MCPWM_GEN0_B_UT1_V 0x00000003U +#define MCPWM_GEN0_B_UT1_S 10 +/** MCPWM_GEN0_B_DTEZ : R/W; bitpos: [13:12]; default: 0; + * Action on PWM0B triggered by event TEZ when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN0_B_DTEZ 0x00000003U +#define MCPWM_GEN0_B_DTEZ_M (MCPWM_GEN0_B_DTEZ_V << MCPWM_GEN0_B_DTEZ_S) +#define MCPWM_GEN0_B_DTEZ_V 0x00000003U +#define MCPWM_GEN0_B_DTEZ_S 12 +/** MCPWM_GEN0_B_DTEP : R/W; bitpos: [15:14]; default: 0; + * Action on PWM0B triggered by event TEP when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN0_B_DTEP 0x00000003U +#define MCPWM_GEN0_B_DTEP_M (MCPWM_GEN0_B_DTEP_V << MCPWM_GEN0_B_DTEP_S) +#define MCPWM_GEN0_B_DTEP_V 0x00000003U +#define MCPWM_GEN0_B_DTEP_S 14 +/** MCPWM_GEN0_B_DTEA : R/W; bitpos: [17:16]; default: 0; + * Action on PWM0B triggered by event TEA when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN0_B_DTEA 0x00000003U +#define MCPWM_GEN0_B_DTEA_M (MCPWM_GEN0_B_DTEA_V << MCPWM_GEN0_B_DTEA_S) +#define MCPWM_GEN0_B_DTEA_V 0x00000003U +#define MCPWM_GEN0_B_DTEA_S 16 +/** MCPWM_GEN0_B_DTEB : R/W; bitpos: [19:18]; default: 0; + * Action on PWM0B triggered by event TEB when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN0_B_DTEB 0x00000003U +#define MCPWM_GEN0_B_DTEB_M (MCPWM_GEN0_B_DTEB_V << MCPWM_GEN0_B_DTEB_S) +#define MCPWM_GEN0_B_DTEB_V 0x00000003U +#define MCPWM_GEN0_B_DTEB_S 18 +/** MCPWM_GEN0_B_DT0 : R/W; bitpos: [21:20]; default: 0; + * Action on PWM0B triggered by event_t0 when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN0_B_DT0 0x00000003U +#define MCPWM_GEN0_B_DT0_M (MCPWM_GEN0_B_DT0_V << MCPWM_GEN0_B_DT0_S) +#define MCPWM_GEN0_B_DT0_V 0x00000003U +#define MCPWM_GEN0_B_DT0_S 20 +/** MCPWM_GEN0_B_DT1 : R/W; bitpos: [23:22]; default: 0; + * Action on PWM0B triggered by event_t1 when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN0_B_DT1 0x00000003U +#define MCPWM_GEN0_B_DT1_M (MCPWM_GEN0_B_DT1_V << MCPWM_GEN0_B_DT1_S) +#define MCPWM_GEN0_B_DT1_V 0x00000003U +#define MCPWM_GEN0_B_DT1_S 22 -#define MCPWM_DT0_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x0058) -/* MCPWM_DT0_CLK_SEL : R/W ;bitpos:[17] ;default: 1'd0 ; */ -/*description: Dead time generator 0 clock selection. 0: PWM_clk 1: PT_clk*/ -#define MCPWM_DT0_CLK_SEL (BIT(17)) -#define MCPWM_DT0_CLK_SEL_M (BIT(17)) -#define MCPWM_DT0_CLK_SEL_V 0x1 -#define MCPWM_DT0_CLK_SEL_S 17 -/* MCPWM_DT0_B_OUTBYPASS : R/W ;bitpos:[16] ;default: 1'd1 ; */ -/*description: S0 in documentation*/ -#define MCPWM_DT0_B_OUTBYPASS (BIT(16)) -#define MCPWM_DT0_B_OUTBYPASS_M (BIT(16)) -#define MCPWM_DT0_B_OUTBYPASS_V 0x1 -#define MCPWM_DT0_B_OUTBYPASS_S 16 -/* MCPWM_DT0_A_OUTBYPASS : R/W ;bitpos:[15] ;default: 1'd1 ; */ -/*description: S1 in documentation*/ -#define MCPWM_DT0_A_OUTBYPASS (BIT(15)) -#define MCPWM_DT0_A_OUTBYPASS_M (BIT(15)) -#define MCPWM_DT0_A_OUTBYPASS_V 0x1 -#define MCPWM_DT0_A_OUTBYPASS_S 15 -/* MCPWM_DT0_FED_OUTINVERT : R/W ;bitpos:[14] ;default: 1'd0 ; */ -/*description: S3 in documentation*/ -#define MCPWM_DT0_FED_OUTINVERT (BIT(14)) -#define MCPWM_DT0_FED_OUTINVERT_M (BIT(14)) -#define MCPWM_DT0_FED_OUTINVERT_V 0x1 -#define MCPWM_DT0_FED_OUTINVERT_S 14 -/* MCPWM_DT0_RED_OUTINVERT : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: S2 in documentation*/ -#define MCPWM_DT0_RED_OUTINVERT (BIT(13)) -#define MCPWM_DT0_RED_OUTINVERT_M (BIT(13)) -#define MCPWM_DT0_RED_OUTINVERT_V 0x1 -#define MCPWM_DT0_RED_OUTINVERT_S 13 -/* MCPWM_DT0_FED_INSEL : R/W ;bitpos:[12] ;default: 1'd0 ; */ -/*description: S5 in documentation*/ -#define MCPWM_DT0_FED_INSEL (BIT(12)) -#define MCPWM_DT0_FED_INSEL_M (BIT(12)) -#define MCPWM_DT0_FED_INSEL_V 0x1 -#define MCPWM_DT0_FED_INSEL_S 12 -/* MCPWM_DT0_RED_INSEL : R/W ;bitpos:[11] ;default: 1'd0 ; */ -/*description: S4 in documentation*/ -#define MCPWM_DT0_RED_INSEL (BIT(11)) -#define MCPWM_DT0_RED_INSEL_M (BIT(11)) -#define MCPWM_DT0_RED_INSEL_V 0x1 -#define MCPWM_DT0_RED_INSEL_S 11 -/* MCPWM_DT0_B_OUTSWAP : R/W ;bitpos:[10] ;default: 1'd0 ; */ -/*description: S7 in documentation*/ -#define MCPWM_DT0_B_OUTSWAP (BIT(10)) -#define MCPWM_DT0_B_OUTSWAP_M (BIT(10)) -#define MCPWM_DT0_B_OUTSWAP_V 0x1 -#define MCPWM_DT0_B_OUTSWAP_S 10 -/* MCPWM_DT0_A_OUTSWAP : R/W ;bitpos:[9] ;default: 1'd0 ; */ -/*description: S6 in documentation*/ -#define MCPWM_DT0_A_OUTSWAP (BIT(9)) -#define MCPWM_DT0_A_OUTSWAP_M (BIT(9)) -#define MCPWM_DT0_A_OUTSWAP_V 0x1 -#define MCPWM_DT0_A_OUTSWAP_S 9 -/* MCPWM_DT0_DEB_MODE : R/W ;bitpos:[8] ;default: 1'd0 ; */ -/*description: S8 in documentation dual-edge B mode 0: FED/RED take effect - on different path separately 1: FED/RED take effect on B path A out is in bypass or normal operation mode*/ -#define MCPWM_DT0_DEB_MODE (BIT(8)) -#define MCPWM_DT0_DEB_MODE_M (BIT(8)) -#define MCPWM_DT0_DEB_MODE_V 0x1 -#define MCPWM_DT0_DEB_MODE_S 8 -/* MCPWM_DT0_RED_UPMETHOD : R/W ;bitpos:[7:4] ;default: 4'd0 ; */ -/*description: Update method for RED (rising edge delay) active reg. 0: immediate - bit0: TEZ bit1: TEP bit2: sync bit3: disable update*/ -#define MCPWM_DT0_RED_UPMETHOD 0x0000000F -#define MCPWM_DT0_RED_UPMETHOD_M ((MCPWM_DT0_RED_UPMETHOD_V)<<(MCPWM_DT0_RED_UPMETHOD_S)) -#define MCPWM_DT0_RED_UPMETHOD_V 0xF -#define MCPWM_DT0_RED_UPMETHOD_S 4 -/* MCPWM_DT0_FED_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: Update method for FED (falling edge delay) active reg. 0: immediate - bit0: TEZ bit1: TEP bit2: sync bit3: disable update*/ -#define MCPWM_DT0_FED_UPMETHOD 0x0000000F -#define MCPWM_DT0_FED_UPMETHOD_M ((MCPWM_DT0_FED_UPMETHOD_V)<<(MCPWM_DT0_FED_UPMETHOD_S)) -#define MCPWM_DT0_FED_UPMETHOD_V 0xF +/** MCPWM_DT0_CFG_REG register + * PWM generator 0 dead time type selection and configuration + */ +#define MCPWM_DT0_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0x58) +/** MCPWM_DT0_FED_UPMETHOD : R/W; bitpos: [3:0]; default: 0; + * Update method for FED (rising edge delay) active register. 0: immediate, when bit0 + * is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when + * bit3 is set to 1: disable the update + */ +#define MCPWM_DT0_FED_UPMETHOD 0x0000000FU +#define MCPWM_DT0_FED_UPMETHOD_M (MCPWM_DT0_FED_UPMETHOD_V << MCPWM_DT0_FED_UPMETHOD_S) +#define MCPWM_DT0_FED_UPMETHOD_V 0x0000000FU #define MCPWM_DT0_FED_UPMETHOD_S 0 +/** MCPWM_DT0_RED_UPMETHOD : R/W; bitpos: [7:4]; default: 0; + * Update method for RED (rising edge delay) active register. 0: immediate, when bit0 + * is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when + * bit3 is set to 1: disable the update + */ +#define MCPWM_DT0_RED_UPMETHOD 0x0000000FU +#define MCPWM_DT0_RED_UPMETHOD_M (MCPWM_DT0_RED_UPMETHOD_V << MCPWM_DT0_RED_UPMETHOD_S) +#define MCPWM_DT0_RED_UPMETHOD_V 0x0000000FU +#define MCPWM_DT0_RED_UPMETHOD_S 4 +/** MCPWM_DT0_DEB_MODE : R/W; bitpos: [8]; default: 0; + * S8 in table, dual-edge B mode, 0: fed/red take effect on different path separately, + * 1: fed/red take effect on B path, A out is in bypass or dulpB mode + */ +#define MCPWM_DT0_DEB_MODE (BIT(8)) +#define MCPWM_DT0_DEB_MODE_M (MCPWM_DT0_DEB_MODE_V << MCPWM_DT0_DEB_MODE_S) +#define MCPWM_DT0_DEB_MODE_V 0x00000001U +#define MCPWM_DT0_DEB_MODE_S 8 +/** MCPWM_DT0_A_OUTSWAP : R/W; bitpos: [9]; default: 0; + * S6 in table + */ +#define MCPWM_DT0_A_OUTSWAP (BIT(9)) +#define MCPWM_DT0_A_OUTSWAP_M (MCPWM_DT0_A_OUTSWAP_V << MCPWM_DT0_A_OUTSWAP_S) +#define MCPWM_DT0_A_OUTSWAP_V 0x00000001U +#define MCPWM_DT0_A_OUTSWAP_S 9 +/** MCPWM_DT0_B_OUTSWAP : R/W; bitpos: [10]; default: 0; + * S7 in table + */ +#define MCPWM_DT0_B_OUTSWAP (BIT(10)) +#define MCPWM_DT0_B_OUTSWAP_M (MCPWM_DT0_B_OUTSWAP_V << MCPWM_DT0_B_OUTSWAP_S) +#define MCPWM_DT0_B_OUTSWAP_V 0x00000001U +#define MCPWM_DT0_B_OUTSWAP_S 10 +/** MCPWM_DT0_RED_INSEL : R/W; bitpos: [11]; default: 0; + * S4 in table + */ +#define MCPWM_DT0_RED_INSEL (BIT(11)) +#define MCPWM_DT0_RED_INSEL_M (MCPWM_DT0_RED_INSEL_V << MCPWM_DT0_RED_INSEL_S) +#define MCPWM_DT0_RED_INSEL_V 0x00000001U +#define MCPWM_DT0_RED_INSEL_S 11 +/** MCPWM_DT0_FED_INSEL : R/W; bitpos: [12]; default: 0; + * S5 in table + */ +#define MCPWM_DT0_FED_INSEL (BIT(12)) +#define MCPWM_DT0_FED_INSEL_M (MCPWM_DT0_FED_INSEL_V << MCPWM_DT0_FED_INSEL_S) +#define MCPWM_DT0_FED_INSEL_V 0x00000001U +#define MCPWM_DT0_FED_INSEL_S 12 +/** MCPWM_DT0_RED_OUTINVERT : R/W; bitpos: [13]; default: 0; + * S2 in table + */ +#define MCPWM_DT0_RED_OUTINVERT (BIT(13)) +#define MCPWM_DT0_RED_OUTINVERT_M (MCPWM_DT0_RED_OUTINVERT_V << MCPWM_DT0_RED_OUTINVERT_S) +#define MCPWM_DT0_RED_OUTINVERT_V 0x00000001U +#define MCPWM_DT0_RED_OUTINVERT_S 13 +/** MCPWM_DT0_FED_OUTINVERT : R/W; bitpos: [14]; default: 0; + * S3 in table + */ +#define MCPWM_DT0_FED_OUTINVERT (BIT(14)) +#define MCPWM_DT0_FED_OUTINVERT_M (MCPWM_DT0_FED_OUTINVERT_V << MCPWM_DT0_FED_OUTINVERT_S) +#define MCPWM_DT0_FED_OUTINVERT_V 0x00000001U +#define MCPWM_DT0_FED_OUTINVERT_S 14 +/** MCPWM_DT0_A_OUTBYPASS : R/W; bitpos: [15]; default: 1; + * S1 in table + */ +#define MCPWM_DT0_A_OUTBYPASS (BIT(15)) +#define MCPWM_DT0_A_OUTBYPASS_M (MCPWM_DT0_A_OUTBYPASS_V << MCPWM_DT0_A_OUTBYPASS_S) +#define MCPWM_DT0_A_OUTBYPASS_V 0x00000001U +#define MCPWM_DT0_A_OUTBYPASS_S 15 +/** MCPWM_DT0_B_OUTBYPASS : R/W; bitpos: [16]; default: 1; + * S0 in table + */ +#define MCPWM_DT0_B_OUTBYPASS (BIT(16)) +#define MCPWM_DT0_B_OUTBYPASS_M (MCPWM_DT0_B_OUTBYPASS_V << MCPWM_DT0_B_OUTBYPASS_S) +#define MCPWM_DT0_B_OUTBYPASS_V 0x00000001U +#define MCPWM_DT0_B_OUTBYPASS_S 16 +/** MCPWM_DT0_CLK_SEL : R/W; bitpos: [17]; default: 0; + * Dead time clock selection. 0: PWM_clk, 1: PT_clk + */ +#define MCPWM_DT0_CLK_SEL (BIT(17)) +#define MCPWM_DT0_CLK_SEL_M (MCPWM_DT0_CLK_SEL_V << MCPWM_DT0_CLK_SEL_S) +#define MCPWM_DT0_CLK_SEL_V 0x00000001U +#define MCPWM_DT0_CLK_SEL_S 17 -#define MCPWM_DT0_FED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x005c) -/* MCPWM_DT0_FED : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ -/*description: Shadow reg for FED*/ -#define MCPWM_DT0_FED 0x0000FFFF -#define MCPWM_DT0_FED_M ((MCPWM_DT0_FED_V)<<(MCPWM_DT0_FED_S)) -#define MCPWM_DT0_FED_V 0xFFFF +/** MCPWM_DT0_FED_CFG_REG register + * PWM generator 0 shadow register for falling edge delay (FED). + */ +#define MCPWM_DT0_FED_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0x5c) +/** MCPWM_DT0_FED : R/W; bitpos: [15:0]; default: 0; + * Shadow register for FED + */ +#define MCPWM_DT0_FED 0x0000FFFFU +#define MCPWM_DT0_FED_M (MCPWM_DT0_FED_V << MCPWM_DT0_FED_S) +#define MCPWM_DT0_FED_V 0x0000FFFFU #define MCPWM_DT0_FED_S 0 -#define MCPWM_DT0_RED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x0060) -/* MCPWM_DT0_RED : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ -/*description: Shadow reg for RED*/ -#define MCPWM_DT0_RED 0x0000FFFF -#define MCPWM_DT0_RED_M ((MCPWM_DT0_RED_V)<<(MCPWM_DT0_RED_S)) -#define MCPWM_DT0_RED_V 0xFFFF +/** MCPWM_DT0_RED_CFG_REG register + * PWM generator 0 shadow register for rising edge delay (RED). + */ +#define MCPWM_DT0_RED_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0x60) +/** MCPWM_DT0_RED : R/W; bitpos: [15:0]; default: 0; + * Shadow register for RED + */ +#define MCPWM_DT0_RED 0x0000FFFFU +#define MCPWM_DT0_RED_M (MCPWM_DT0_RED_V << MCPWM_DT0_RED_S) +#define MCPWM_DT0_RED_V 0x0000FFFFU #define MCPWM_DT0_RED_S 0 -#define MCPWM_CARRIER0_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x0064) -/* MCPWM_CARRIER0_IN_INVERT : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: When set invert the input of PWM0A and PWM0B for this submodule*/ -#define MCPWM_CARRIER0_IN_INVERT (BIT(13)) -#define MCPWM_CARRIER0_IN_INVERT_M (BIT(13)) -#define MCPWM_CARRIER0_IN_INVERT_V 0x1 -#define MCPWM_CARRIER0_IN_INVERT_S 13 -/* MCPWM_CARRIER0_OUT_INVERT : R/W ;bitpos:[12] ;default: 1'd0 ; */ -/*description: When set invert the output of PWM0A and PWM0B for this submodule*/ -#define MCPWM_CARRIER0_OUT_INVERT (BIT(12)) -#define MCPWM_CARRIER0_OUT_INVERT_M (BIT(12)) -#define MCPWM_CARRIER0_OUT_INVERT_V 0x1 -#define MCPWM_CARRIER0_OUT_INVERT_S 12 -/* MCPWM_CARRIER0_OSHWTH : R/W ;bitpos:[11:8] ;default: 4'd0 ; */ -/*description: Width of the fist pulse in number of periods of the carrier*/ -#define MCPWM_CARRIER0_OSHWTH 0x0000000F -#define MCPWM_CARRIER0_OSHWTH_M ((MCPWM_CARRIER0_OSHWTH_V)<<(MCPWM_CARRIER0_OSHWTH_S)) -#define MCPWM_CARRIER0_OSHWTH_V 0xF -#define MCPWM_CARRIER0_OSHWTH_S 8 -/* MCPWM_CARRIER0_DUTY : R/W ;bitpos:[7:5] ;default: 3'd0 ; */ -/*description: Carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8*/ -#define MCPWM_CARRIER0_DUTY 0x00000007 -#define MCPWM_CARRIER0_DUTY_M ((MCPWM_CARRIER0_DUTY_V)<<(MCPWM_CARRIER0_DUTY_S)) -#define MCPWM_CARRIER0_DUTY_V 0x7 -#define MCPWM_CARRIER0_DUTY_S 5 -/* MCPWM_CARRIER0_PRESCALE : R/W ;bitpos:[4:1] ;default: 4'd0 ; */ -/*description: PWM carrier0 clock (PC_clk) prescale value. Period of PC_clk - = period of PWM_clk * (PWM_CARRIER0_PRESCALE + 1)*/ -#define MCPWM_CARRIER0_PRESCALE 0x0000000F -#define MCPWM_CARRIER0_PRESCALE_M ((MCPWM_CARRIER0_PRESCALE_V)<<(MCPWM_CARRIER0_PRESCALE_S)) -#define MCPWM_CARRIER0_PRESCALE_V 0xF -#define MCPWM_CARRIER0_PRESCALE_S 1 -/* MCPWM_CARRIER0_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */ -/*description: When set carrier0 function is enabled. When cleared carrier0 is bypassed*/ -#define MCPWM_CARRIER0_EN (BIT(0)) -#define MCPWM_CARRIER0_EN_M (BIT(0)) -#define MCPWM_CARRIER0_EN_V 0x1 +/** MCPWM_CARRIER0_CFG_REG register + * PWM generator 0 carrier enable and configuratoin + */ +#define MCPWM_CARRIER0_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0x64) +/** MCPWM_CARRIER0_EN : R/W; bitpos: [0]; default: 0; + * When set, carrier0 function is enabled. When cleared, carrier0 is bypassed + */ +#define MCPWM_CARRIER0_EN (BIT(0)) +#define MCPWM_CARRIER0_EN_M (MCPWM_CARRIER0_EN_V << MCPWM_CARRIER0_EN_S) +#define MCPWM_CARRIER0_EN_V 0x00000001U #define MCPWM_CARRIER0_EN_S 0 +/** MCPWM_CARRIER0_PRESCALE : R/W; bitpos: [4:1]; default: 0; + * PWM carrier0 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk * + * (PWM_CARRIER0_PRESCALE + 1) + */ +#define MCPWM_CARRIER0_PRESCALE 0x0000000FU +#define MCPWM_CARRIER0_PRESCALE_M (MCPWM_CARRIER0_PRESCALE_V << MCPWM_CARRIER0_PRESCALE_S) +#define MCPWM_CARRIER0_PRESCALE_V 0x0000000FU +#define MCPWM_CARRIER0_PRESCALE_S 1 +/** MCPWM_CARRIER0_DUTY : R/W; bitpos: [7:5]; default: 0; + * carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8 + */ +#define MCPWM_CARRIER0_DUTY 0x00000007U +#define MCPWM_CARRIER0_DUTY_M (MCPWM_CARRIER0_DUTY_V << MCPWM_CARRIER0_DUTY_S) +#define MCPWM_CARRIER0_DUTY_V 0x00000007U +#define MCPWM_CARRIER0_DUTY_S 5 +/** MCPWM_CARRIER0_OSHTWTH : R/W; bitpos: [11:8]; default: 0; + * width of the first pulse in number of periods of the carrier + */ +#define MCPWM_CARRIER0_OSHTWTH 0x0000000FU +#define MCPWM_CARRIER0_OSHTWTH_M (MCPWM_CARRIER0_OSHTWTH_V << MCPWM_CARRIER0_OSHTWTH_S) +#define MCPWM_CARRIER0_OSHTWTH_V 0x0000000FU +#define MCPWM_CARRIER0_OSHTWTH_S 8 +/** MCPWM_CARRIER0_OUT_INVERT : R/W; bitpos: [12]; default: 0; + * when set, invert the output of PWM0A and PWM0B for this submodule + */ +#define MCPWM_CARRIER0_OUT_INVERT (BIT(12)) +#define MCPWM_CARRIER0_OUT_INVERT_M (MCPWM_CARRIER0_OUT_INVERT_V << MCPWM_CARRIER0_OUT_INVERT_S) +#define MCPWM_CARRIER0_OUT_INVERT_V 0x00000001U +#define MCPWM_CARRIER0_OUT_INVERT_S 12 +/** MCPWM_CARRIER0_IN_INVERT : R/W; bitpos: [13]; default: 0; + * when set, invert the input of PWM0A and PWM0B for this submodule + */ +#define MCPWM_CARRIER0_IN_INVERT (BIT(13)) +#define MCPWM_CARRIER0_IN_INVERT_M (MCPWM_CARRIER0_IN_INVERT_V << MCPWM_CARRIER0_IN_INVERT_S) +#define MCPWM_CARRIER0_IN_INVERT_V 0x00000001U +#define MCPWM_CARRIER0_IN_INVERT_S 13 -#define MCPWM_FH0_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x0068) -/* MCPWM_FH0_B_OST_U : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ -/*description: One-shot mode action on PWM0B when fault event occurs and timer - is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ -#define MCPWM_FH0_B_OST_U 0x00000003 -#define MCPWM_FH0_B_OST_U_M ((MCPWM_FH0_B_OST_U_V)<<(MCPWM_FH0_B_OST_U_S)) -#define MCPWM_FH0_B_OST_U_V 0x3 -#define MCPWM_FH0_B_OST_U_S 22 -/* MCPWM_FH0_B_OST_D : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ -/*description: One-shot mode action on PWM0B when fault event occurs and timer - is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ -#define MCPWM_FH0_B_OST_D 0x00000003 -#define MCPWM_FH0_B_OST_D_M ((MCPWM_FH0_B_OST_D_V)<<(MCPWM_FH0_B_OST_D_S)) -#define MCPWM_FH0_B_OST_D_V 0x3 -#define MCPWM_FH0_B_OST_D_S 20 -/* MCPWM_FH0_B_CBC_U : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ -/*description: Cycle-by-cycle mode action on PWM0B when fault event occurs and - timer is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ -#define MCPWM_FH0_B_CBC_U 0x00000003 -#define MCPWM_FH0_B_CBC_U_M ((MCPWM_FH0_B_CBC_U_V)<<(MCPWM_FH0_B_CBC_U_S)) -#define MCPWM_FH0_B_CBC_U_V 0x3 -#define MCPWM_FH0_B_CBC_U_S 18 -/* MCPWM_FH0_B_CBC_D : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ -/*description: Cycle-by-cycle mode action on PWM0B when fault event occurs and - timer is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ -#define MCPWM_FH0_B_CBC_D 0x00000003 -#define MCPWM_FH0_B_CBC_D_M ((MCPWM_FH0_B_CBC_D_V)<<(MCPWM_FH0_B_CBC_D_S)) -#define MCPWM_FH0_B_CBC_D_V 0x3 -#define MCPWM_FH0_B_CBC_D_S 16 -/* MCPWM_FH0_A_OST_U : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ -/*description: One-shot mode action on PWM0A when fault event occurs and timer - is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ -#define MCPWM_FH0_A_OST_U 0x00000003 -#define MCPWM_FH0_A_OST_U_M ((MCPWM_FH0_A_OST_U_V)<<(MCPWM_FH0_A_OST_U_S)) -#define MCPWM_FH0_A_OST_U_V 0x3 -#define MCPWM_FH0_A_OST_U_S 14 -/* MCPWM_FH0_A_OST_D : R/W ;bitpos:[13:12] ;default: 2'd0 ; */ -/*description: One-shot mode action on PWM0A when fault event occurs and timer - is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ -#define MCPWM_FH0_A_OST_D 0x00000003 -#define MCPWM_FH0_A_OST_D_M ((MCPWM_FH0_A_OST_D_V)<<(MCPWM_FH0_A_OST_D_S)) -#define MCPWM_FH0_A_OST_D_V 0x3 -#define MCPWM_FH0_A_OST_D_S 12 -/* MCPWM_FH0_A_CBC_U : R/W ;bitpos:[11:10] ;default: 2'd0 ; */ -/*description: Cycle-by-cycle mode action on PWM0A when fault event occurs and - timer is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ -#define MCPWM_FH0_A_CBC_U 0x00000003 -#define MCPWM_FH0_A_CBC_U_M ((MCPWM_FH0_A_CBC_U_V)<<(MCPWM_FH0_A_CBC_U_S)) -#define MCPWM_FH0_A_CBC_U_V 0x3 -#define MCPWM_FH0_A_CBC_U_S 10 -/* MCPWM_FH0_A_CBC_D : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ -/*description: Cycle-by-cycle mode action on PWM0A when fault event occurs and - timer is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ -#define MCPWM_FH0_A_CBC_D 0x00000003 -#define MCPWM_FH0_A_CBC_D_M ((MCPWM_FH0_A_CBC_D_V)<<(MCPWM_FH0_A_CBC_D_S)) -#define MCPWM_FH0_A_CBC_D_V 0x3 -#define MCPWM_FH0_A_CBC_D_S 8 -/* MCPWM_FH0_F0_OST : R/W ;bitpos:[7] ;default: 1'd0 ; */ -/*description: event_f0 will trigger one-shot mode action. 0: disable 1: enable*/ -#define MCPWM_FH0_F0_OST (BIT(7)) -#define MCPWM_FH0_F0_OST_M (BIT(7)) -#define MCPWM_FH0_F0_OST_V 0x1 -#define MCPWM_FH0_F0_OST_S 7 -/* MCPWM_FH0_F1_OST : R/W ;bitpos:[6] ;default: 1'd0 ; */ -/*description: event_f1 will trigger one-shot mode action. 0: disable 1: enable*/ -#define MCPWM_FH0_F1_OST (BIT(6)) -#define MCPWM_FH0_F1_OST_M (BIT(6)) -#define MCPWM_FH0_F1_OST_V 0x1 -#define MCPWM_FH0_F1_OST_S 6 -/* MCPWM_FH0_F2_OST : R/W ;bitpos:[5] ;default: 1'd0 ; */ -/*description: event_f2 will trigger one-shot mode action. 0: disable 1: enable*/ -#define MCPWM_FH0_F2_OST (BIT(5)) -#define MCPWM_FH0_F2_OST_M (BIT(5)) -#define MCPWM_FH0_F2_OST_V 0x1 -#define MCPWM_FH0_F2_OST_S 5 -/* MCPWM_FH0_SW_OST : R/W ;bitpos:[4] ;default: 1'd0 ; */ -/*description: Enable register for software force one-shot mode action. 0: disable 1: enable*/ -#define MCPWM_FH0_SW_OST (BIT(4)) -#define MCPWM_FH0_SW_OST_M (BIT(4)) -#define MCPWM_FH0_SW_OST_V 0x1 -#define MCPWM_FH0_SW_OST_S 4 -/* MCPWM_FH0_F0_CBC : R/W ;bitpos:[3] ;default: 1'd0 ; */ -/*description: event_f0 will trigger cycle-by-cycle mode action. 0: disable 1: enable*/ -#define MCPWM_FH0_F0_CBC (BIT(3)) -#define MCPWM_FH0_F0_CBC_M (BIT(3)) -#define MCPWM_FH0_F0_CBC_V 0x1 -#define MCPWM_FH0_F0_CBC_S 3 -/* MCPWM_FH0_F1_CBC : R/W ;bitpos:[2] ;default: 1'd0 ; */ -/*description: event_f1 will trigger cycle-by-cycle mode action. 0: disable 1: enable*/ -#define MCPWM_FH0_F1_CBC (BIT(2)) -#define MCPWM_FH0_F1_CBC_M (BIT(2)) -#define MCPWM_FH0_F1_CBC_V 0x1 -#define MCPWM_FH0_F1_CBC_S 2 -/* MCPWM_FH0_F2_CBC : R/W ;bitpos:[1] ;default: 1'd0 ; */ -/*description: event_f2 will trigger cycle-by-cycle mode action. 0: disable 1: enable*/ -#define MCPWM_FH0_F2_CBC (BIT(1)) -#define MCPWM_FH0_F2_CBC_M (BIT(1)) -#define MCPWM_FH0_F2_CBC_V 0x1 -#define MCPWM_FH0_F2_CBC_S 1 -/* MCPWM_FH0_SW_CBC : R/W ;bitpos:[0] ;default: 1'd0 ; */ -/*description: Enable register for software force cycle-by-cycle mode action. - 0: disable 1: enable*/ -#define MCPWM_FH0_SW_CBC (BIT(0)) -#define MCPWM_FH0_SW_CBC_M (BIT(0)) -#define MCPWM_FH0_SW_CBC_V 0x1 +/** MCPWM_FH0_CFG0_REG register + * Actions on PWM0A and PWM0B trip events + */ +#define MCPWM_FH0_CFG0_REG(i) (DR_REG_MCPWM_BASE(i) + 0x68) +/** MCPWM_FH0_SW_CBC : R/W; bitpos: [0]; default: 0; + * Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable + */ +#define MCPWM_FH0_SW_CBC (BIT(0)) +#define MCPWM_FH0_SW_CBC_M (MCPWM_FH0_SW_CBC_V << MCPWM_FH0_SW_CBC_S) +#define MCPWM_FH0_SW_CBC_V 0x00000001U #define MCPWM_FH0_SW_CBC_S 0 +/** MCPWM_FH0_F2_CBC : R/W; bitpos: [1]; default: 0; + * fault_event2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + */ +#define MCPWM_FH0_F2_CBC (BIT(1)) +#define MCPWM_FH0_F2_CBC_M (MCPWM_FH0_F2_CBC_V << MCPWM_FH0_F2_CBC_S) +#define MCPWM_FH0_F2_CBC_V 0x00000001U +#define MCPWM_FH0_F2_CBC_S 1 +/** MCPWM_FH0_F1_CBC : R/W; bitpos: [2]; default: 0; + * fault_event1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + */ +#define MCPWM_FH0_F1_CBC (BIT(2)) +#define MCPWM_FH0_F1_CBC_M (MCPWM_FH0_F1_CBC_V << MCPWM_FH0_F1_CBC_S) +#define MCPWM_FH0_F1_CBC_V 0x00000001U +#define MCPWM_FH0_F1_CBC_S 2 +/** MCPWM_FH0_F0_CBC : R/W; bitpos: [3]; default: 0; + * fault_event0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + */ +#define MCPWM_FH0_F0_CBC (BIT(3)) +#define MCPWM_FH0_F0_CBC_M (MCPWM_FH0_F0_CBC_V << MCPWM_FH0_F0_CBC_S) +#define MCPWM_FH0_F0_CBC_V 0x00000001U +#define MCPWM_FH0_F0_CBC_S 3 +/** MCPWM_FH0_SW_OST : R/W; bitpos: [4]; default: 0; + * Enable register for software force one-shot mode action. 0: disable, 1: enable + */ +#define MCPWM_FH0_SW_OST (BIT(4)) +#define MCPWM_FH0_SW_OST_M (MCPWM_FH0_SW_OST_V << MCPWM_FH0_SW_OST_S) +#define MCPWM_FH0_SW_OST_V 0x00000001U +#define MCPWM_FH0_SW_OST_S 4 +/** MCPWM_FH0_F2_OST : R/W; bitpos: [5]; default: 0; + * fault_event2 will trigger one-shot mode action. 0: disable, 1: enable + */ +#define MCPWM_FH0_F2_OST (BIT(5)) +#define MCPWM_FH0_F2_OST_M (MCPWM_FH0_F2_OST_V << MCPWM_FH0_F2_OST_S) +#define MCPWM_FH0_F2_OST_V 0x00000001U +#define MCPWM_FH0_F2_OST_S 5 +/** MCPWM_FH0_F1_OST : R/W; bitpos: [6]; default: 0; + * fault_event1 will trigger one-shot mode action. 0: disable, 1: enable + */ +#define MCPWM_FH0_F1_OST (BIT(6)) +#define MCPWM_FH0_F1_OST_M (MCPWM_FH0_F1_OST_V << MCPWM_FH0_F1_OST_S) +#define MCPWM_FH0_F1_OST_V 0x00000001U +#define MCPWM_FH0_F1_OST_S 6 +/** MCPWM_FH0_F0_OST : R/W; bitpos: [7]; default: 0; + * fault_event0 will trigger one-shot mode action. 0: disable, 1: enable + */ +#define MCPWM_FH0_F0_OST (BIT(7)) +#define MCPWM_FH0_F0_OST_M (MCPWM_FH0_F0_OST_V << MCPWM_FH0_F0_OST_S) +#define MCPWM_FH0_F0_OST_V 0x00000001U +#define MCPWM_FH0_F0_OST_S 7 +/** MCPWM_FH0_A_CBC_D : R/W; bitpos: [9:8]; default: 0; + * Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is + * decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_FH0_A_CBC_D 0x00000003U +#define MCPWM_FH0_A_CBC_D_M (MCPWM_FH0_A_CBC_D_V << MCPWM_FH0_A_CBC_D_S) +#define MCPWM_FH0_A_CBC_D_V 0x00000003U +#define MCPWM_FH0_A_CBC_D_S 8 +/** MCPWM_FH0_A_CBC_U : R/W; bitpos: [11:10]; default: 0; + * Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is + * increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_FH0_A_CBC_U 0x00000003U +#define MCPWM_FH0_A_CBC_U_M (MCPWM_FH0_A_CBC_U_V << MCPWM_FH0_A_CBC_U_S) +#define MCPWM_FH0_A_CBC_U_V 0x00000003U +#define MCPWM_FH0_A_CBC_U_S 10 +/** MCPWM_FH0_A_OST_D : R/W; bitpos: [13:12]; default: 0; + * One-shot mode action on PWM0A when fault event occurs and timer is decreasing. 0: + * do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_FH0_A_OST_D 0x00000003U +#define MCPWM_FH0_A_OST_D_M (MCPWM_FH0_A_OST_D_V << MCPWM_FH0_A_OST_D_S) +#define MCPWM_FH0_A_OST_D_V 0x00000003U +#define MCPWM_FH0_A_OST_D_S 12 +/** MCPWM_FH0_A_OST_U : R/W; bitpos: [15:14]; default: 0; + * One-shot mode action on PWM0A when fault event occurs and timer is increasing. 0: + * do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_FH0_A_OST_U 0x00000003U +#define MCPWM_FH0_A_OST_U_M (MCPWM_FH0_A_OST_U_V << MCPWM_FH0_A_OST_U_S) +#define MCPWM_FH0_A_OST_U_V 0x00000003U +#define MCPWM_FH0_A_OST_U_S 14 +/** MCPWM_FH0_B_CBC_D : R/W; bitpos: [17:16]; default: 0; + * Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is + * decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_FH0_B_CBC_D 0x00000003U +#define MCPWM_FH0_B_CBC_D_M (MCPWM_FH0_B_CBC_D_V << MCPWM_FH0_B_CBC_D_S) +#define MCPWM_FH0_B_CBC_D_V 0x00000003U +#define MCPWM_FH0_B_CBC_D_S 16 +/** MCPWM_FH0_B_CBC_U : R/W; bitpos: [19:18]; default: 0; + * Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is + * increasing. 0: do nothing,1: force low, 2: force high, 3: toggle + */ +#define MCPWM_FH0_B_CBC_U 0x00000003U +#define MCPWM_FH0_B_CBC_U_M (MCPWM_FH0_B_CBC_U_V << MCPWM_FH0_B_CBC_U_S) +#define MCPWM_FH0_B_CBC_U_V 0x00000003U +#define MCPWM_FH0_B_CBC_U_S 18 +/** MCPWM_FH0_B_OST_D : R/W; bitpos: [21:20]; default: 0; + * One-shot mode action on PWM0B when fault event occurs and timer is decreasing. 0: + * do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_FH0_B_OST_D 0x00000003U +#define MCPWM_FH0_B_OST_D_M (MCPWM_FH0_B_OST_D_V << MCPWM_FH0_B_OST_D_S) +#define MCPWM_FH0_B_OST_D_V 0x00000003U +#define MCPWM_FH0_B_OST_D_S 20 +/** MCPWM_FH0_B_OST_U : R/W; bitpos: [23:22]; default: 0; + * One-shot mode action on PWM0B when fault event occurs and timer is increasing. 0: + * do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_FH0_B_OST_U 0x00000003U +#define MCPWM_FH0_B_OST_U_M (MCPWM_FH0_B_OST_U_V << MCPWM_FH0_B_OST_U_S) +#define MCPWM_FH0_B_OST_U_V 0x00000003U +#define MCPWM_FH0_B_OST_U_S 22 -#define MCPWM_FH0_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0x006c) -/* MCPWM_FH0_FORCE_OST : R/W ;bitpos:[4] ;default: 1'd0 ; */ -/*description: A toggle (software negation of value of this bit) triggers a - one-shot mode action*/ -#define MCPWM_FH0_FORCE_OST (BIT(4)) -#define MCPWM_FH0_FORCE_OST_M (BIT(4)) -#define MCPWM_FH0_FORCE_OST_V 0x1 -#define MCPWM_FH0_FORCE_OST_S 4 -/* MCPWM_FH0_FORCE_CBC : R/W ;bitpos:[3] ;default: 1'd0 ; */ -/*description: A toggle triggers a cycle-by-cycle mode action*/ -#define MCPWM_FH0_FORCE_CBC (BIT(3)) -#define MCPWM_FH0_FORCE_CBC_M (BIT(3)) -#define MCPWM_FH0_FORCE_CBC_V 0x1 -#define MCPWM_FH0_FORCE_CBC_S 3 -/* MCPWM_FH0_CBCPULSE : R/W ;bitpos:[2:1] ;default: 2'd0 ; */ -/*description: The cycle-by-cycle mode action refresh moment selection. Bit0: TEZ bit1:TEP*/ -#define MCPWM_FH0_CBCPULSE 0x00000003 -#define MCPWM_FH0_CBCPULSE_M ((MCPWM_FH0_CBCPULSE_V)<<(MCPWM_FH0_CBCPULSE_S)) -#define MCPWM_FH0_CBCPULSE_V 0x3 -#define MCPWM_FH0_CBCPULSE_S 1 -/* MCPWM_FH0_CLR_OST : R/W ;bitpos:[0] ;default: 1'd0 ; */ -/*description: A toggle will clear on going one-shot mode action*/ -#define MCPWM_FH0_CLR_OST (BIT(0)) -#define MCPWM_FH0_CLR_OST_M (BIT(0)) -#define MCPWM_FH0_CLR_OST_V 0x1 +/** MCPWM_FH0_CFG1_REG register + * Software triggers for fault handler actions + */ +#define MCPWM_FH0_CFG1_REG(i) (DR_REG_MCPWM_BASE(i) + 0x6c) +/** MCPWM_FH0_CLR_OST : R/W; bitpos: [0]; default: 0; + * a rising edge will clear on going one-shot mode action + */ +#define MCPWM_FH0_CLR_OST (BIT(0)) +#define MCPWM_FH0_CLR_OST_M (MCPWM_FH0_CLR_OST_V << MCPWM_FH0_CLR_OST_S) +#define MCPWM_FH0_CLR_OST_V 0x00000001U #define MCPWM_FH0_CLR_OST_S 0 +/** MCPWM_FH0_CBCPULSE : R/W; bitpos: [2:1]; default: 0; + * cycle-by-cycle mode action refresh moment selection. When bit0 is set to 1: TEZ, + * when bit1 is set to 1:TEP, when bit0 and bit1 both set to 0: stop refresh, when + * bit0 and bit1 both set to 1: refresh at TEP/TEZ + */ +#define MCPWM_FH0_CBCPULSE 0x00000003U +#define MCPWM_FH0_CBCPULSE_M (MCPWM_FH0_CBCPULSE_V << MCPWM_FH0_CBCPULSE_S) +#define MCPWM_FH0_CBCPULSE_V 0x00000003U +#define MCPWM_FH0_CBCPULSE_S 1 +/** MCPWM_FH0_FORCE_CBC : R/W; bitpos: [3]; default: 0; + * a toggle trigger a cycle-by-cycle mode action + */ +#define MCPWM_FH0_FORCE_CBC (BIT(3)) +#define MCPWM_FH0_FORCE_CBC_M (MCPWM_FH0_FORCE_CBC_V << MCPWM_FH0_FORCE_CBC_S) +#define MCPWM_FH0_FORCE_CBC_V 0x00000001U +#define MCPWM_FH0_FORCE_CBC_S 3 +/** MCPWM_FH0_FORCE_OST : R/W; bitpos: [4]; default: 0; + * a toggle (software negate its value) triggers a one-shot mode action + */ +#define MCPWM_FH0_FORCE_OST (BIT(4)) +#define MCPWM_FH0_FORCE_OST_M (MCPWM_FH0_FORCE_OST_V << MCPWM_FH0_FORCE_OST_S) +#define MCPWM_FH0_FORCE_OST_V 0x00000001U +#define MCPWM_FH0_FORCE_OST_S 4 -#define MCPWM_FH0_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x0070) -/* MCPWM_FH0_OST_ON : RO ;bitpos:[1] ;default: 1'd0 ; */ -/*description: Set and reset by hardware. If set an one-shot mode action is on going*/ -#define MCPWM_FH0_OST_ON (BIT(1)) -#define MCPWM_FH0_OST_ON_M (BIT(1)) -#define MCPWM_FH0_OST_ON_V 0x1 -#define MCPWM_FH0_OST_ON_S 1 -/* MCPWM_FH0_CBC_ON : RO ;bitpos:[0] ;default: 1'd0 ; */ -/*description: Set and reset by hardware. If set an cycle-by-cycle mode action is on going*/ -#define MCPWM_FH0_CBC_ON (BIT(0)) -#define MCPWM_FH0_CBC_ON_M (BIT(0)) -#define MCPWM_FH0_CBC_ON_V 0x1 +/** MCPWM_FH0_STATUS_REG register + * Status of fault events. + */ +#define MCPWM_FH0_STATUS_REG(i) (DR_REG_MCPWM_BASE(i) + 0x70) +/** MCPWM_FH0_CBC_ON : RO; bitpos: [0]; default: 0; + * Set and reset by hardware. If set, a cycle-by-cycle mode action is on going + */ +#define MCPWM_FH0_CBC_ON (BIT(0)) +#define MCPWM_FH0_CBC_ON_M (MCPWM_FH0_CBC_ON_V << MCPWM_FH0_CBC_ON_S) +#define MCPWM_FH0_CBC_ON_V 0x00000001U #define MCPWM_FH0_CBC_ON_S 0 +/** MCPWM_FH0_OST_ON : RO; bitpos: [1]; default: 0; + * Set and reset by hardware. If set, an one-shot mode action is on going + */ +#define MCPWM_FH0_OST_ON (BIT(1)) +#define MCPWM_FH0_OST_ON_M (MCPWM_FH0_OST_ON_V << MCPWM_FH0_OST_ON_S) +#define MCPWM_FH0_OST_ON_V 0x00000001U +#define MCPWM_FH0_OST_ON_S 1 -#define MCPWM_GEN1_STMP_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x0074) -/* MCPWM_GEN1_B_SHDW_FULL : RO ;bitpos:[9] ;default: 1'd0 ; */ -/*description: Set and reset by hardware. If set PWM generator 1 time stamp - B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared B's active reg has been updated with shadow reg latest value*/ -#define MCPWM_GEN1_B_SHDW_FULL (BIT(9)) -#define MCPWM_GEN1_B_SHDW_FULL_M (BIT(9)) -#define MCPWM_GEN1_B_SHDW_FULL_V 0x1 -#define MCPWM_GEN1_B_SHDW_FULL_S 9 -/* MCPWM_GEN1_A_SHDW_FULL : RO ;bitpos:[8] ;default: 1'd0 ; */ -/*description: Set and reset by hardware. If set PWM generator 1 time stamp - A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared A's active reg has been updated with shadow reg latest value*/ -#define MCPWM_GEN1_A_SHDW_FULL (BIT(8)) -#define MCPWM_GEN1_A_SHDW_FULL_M (BIT(8)) -#define MCPWM_GEN1_A_SHDW_FULL_V 0x1 -#define MCPWM_GEN1_A_SHDW_FULL_S 8 -/* MCPWM_GEN1_B_UPMETHOD : R/W ;bitpos:[7:4] ;default: 4'd0 ; */ -/*description: Update method for PWM generator 1 time stamp B's active reg. - 0: immediate bit0: TEZ bit1: TEP bit2: sync bit3: disable update*/ -#define MCPWM_GEN1_B_UPMETHOD 0x0000000F -#define MCPWM_GEN1_B_UPMETHOD_M ((MCPWM_GEN1_B_UPMETHOD_V)<<(MCPWM_GEN1_B_UPMETHOD_S)) -#define MCPWM_GEN1_B_UPMETHOD_V 0xF -#define MCPWM_GEN1_B_UPMETHOD_S 4 -/* MCPWM_GEN1_A_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: Update method for PWM generator 1 time stamp A's active reg. - 0: immediate bit0: TEZ bit1: TEP bit2: sync bit3: disable update*/ -#define MCPWM_GEN1_A_UPMETHOD 0x0000000F -#define MCPWM_GEN1_A_UPMETHOD_M ((MCPWM_GEN1_A_UPMETHOD_V)<<(MCPWM_GEN1_A_UPMETHOD_S)) -#define MCPWM_GEN1_A_UPMETHOD_V 0xF +/** MCPWM_GEN1_STMP_CFG_REG register + * Transfer status and update method for time stamp registers A and B + */ +#define MCPWM_GEN1_STMP_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0x74) +/** MCPWM_GEN1_A_UPMETHOD : R/W; bitpos: [3:0]; default: 0; + * Update method for PWM generator 1 time stamp A's active register. When all bits are + * set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when + * bit2 is set to 1: sync, when bit3 is set to 1: disable the update. + */ +#define MCPWM_GEN1_A_UPMETHOD 0x0000000FU +#define MCPWM_GEN1_A_UPMETHOD_M (MCPWM_GEN1_A_UPMETHOD_V << MCPWM_GEN1_A_UPMETHOD_S) +#define MCPWM_GEN1_A_UPMETHOD_V 0x0000000FU #define MCPWM_GEN1_A_UPMETHOD_S 0 +/** MCPWM_GEN1_B_UPMETHOD : R/W; bitpos: [7:4]; default: 0; + * Update method for PWM generator 1 time stamp B's active register. When all bits are + * set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when + * bit2 is set to 1: sync, when bit3 is set to 1: disable the update. + */ +#define MCPWM_GEN1_B_UPMETHOD 0x0000000FU +#define MCPWM_GEN1_B_UPMETHOD_M (MCPWM_GEN1_B_UPMETHOD_V << MCPWM_GEN1_B_UPMETHOD_S) +#define MCPWM_GEN1_B_UPMETHOD_V 0x0000000FU +#define MCPWM_GEN1_B_UPMETHOD_S 4 +/** MCPWM_GEN1_A_SHDW_FULL : R/W/WTC/SC; bitpos: [8]; default: 0; + * Set and reset by hardware. If set, PWM generator 1 time stamp A's shadow reg is + * filled and waiting to be transferred to A's active reg. If cleared, A's active reg + * has been updated with shadow register latest value + */ +#define MCPWM_GEN1_A_SHDW_FULL (BIT(8)) +#define MCPWM_GEN1_A_SHDW_FULL_M (MCPWM_GEN1_A_SHDW_FULL_V << MCPWM_GEN1_A_SHDW_FULL_S) +#define MCPWM_GEN1_A_SHDW_FULL_V 0x00000001U +#define MCPWM_GEN1_A_SHDW_FULL_S 8 +/** MCPWM_GEN1_B_SHDW_FULL : R/W/WTC/SC; bitpos: [9]; default: 0; + * Set and reset by hardware. If set, PWM generator 1 time stamp B's shadow reg is + * filled and waiting to be transferred to B's active reg. If cleared, B's active reg + * has been updated with shadow register latest value + */ +#define MCPWM_GEN1_B_SHDW_FULL (BIT(9)) +#define MCPWM_GEN1_B_SHDW_FULL_M (MCPWM_GEN1_B_SHDW_FULL_V << MCPWM_GEN1_B_SHDW_FULL_S) +#define MCPWM_GEN1_B_SHDW_FULL_V 0x00000001U +#define MCPWM_GEN1_B_SHDW_FULL_S 9 -#define MCPWM_GEN1_TSTMP_A_REG(i) (REG_MCPWM_BASE(i) + 0x0078) -/* MCPWM_GEN1_A : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ -/*description: PWM generator 1 time stamp A's shadow reg*/ -#define MCPWM_GEN1_A 0x0000FFFF -#define MCPWM_GEN1_A_M ((MCPWM_GEN1_A_V)<<(MCPWM_GEN1_A_S)) -#define MCPWM_GEN1_A_V 0xFFFF +/** MCPWM_GEN1_TSTMP_A_REG register + * PWM generator 1 shadow register for timer stamp A. + */ +#define MCPWM_GEN1_TSTMP_A_REG(i) (DR_REG_MCPWM_BASE(i) + 0x78) +/** MCPWM_GEN1_A : R/W; bitpos: [15:0]; default: 0; + * PWM generator 1 time stamp A's shadow register + */ +#define MCPWM_GEN1_A 0x0000FFFFU +#define MCPWM_GEN1_A_M (MCPWM_GEN1_A_V << MCPWM_GEN1_A_S) +#define MCPWM_GEN1_A_V 0x0000FFFFU #define MCPWM_GEN1_A_S 0 -#define MCPWM_GEN1_TSTMP_B_REG(i) (REG_MCPWM_BASE(i) + 0x007c) -/* MCPWM_GEN1_B : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ -/*description: PWM generator 1 time stamp B's shadow reg*/ -#define MCPWM_GEN1_B 0x0000FFFF -#define MCPWM_GEN1_B_M ((MCPWM_GEN1_B_V)<<(MCPWM_GEN1_B_S)) -#define MCPWM_GEN1_B_V 0xFFFF +/** MCPWM_GEN1_TSTMP_B_REG register + * PWM generator 1 shadow register for timer stamp B. + */ +#define MCPWM_GEN1_TSTMP_B_REG(i) (DR_REG_MCPWM_BASE(i) + 0x7c) +/** MCPWM_GEN1_B : R/W; bitpos: [15:0]; default: 0; + * PWM generator 1 time stamp B's shadow register + */ +#define MCPWM_GEN1_B 0x0000FFFFU +#define MCPWM_GEN1_B_M (MCPWM_GEN1_B_V << MCPWM_GEN1_B_S) +#define MCPWM_GEN1_B_V 0x0000FFFFU #define MCPWM_GEN1_B_S 0 -#define MCPWM_GEN1_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x0080) -/* MCPWM_GEN1_T1_SEL : R/W ;bitpos:[9:7] ;default: 3'd0 ; */ -/*description: Source selection for PWM generate1 event_t1 take effect immediately - 0: fault_event0 1: fault_event1 2: fault_event2 3: sync_taken 4: none*/ -#define MCPWM_GEN1_T1_SEL 0x00000007 -#define MCPWM_GEN1_T1_SEL_M ((MCPWM_GEN1_T1_SEL_V)<<(MCPWM_GEN1_T1_SEL_S)) -#define MCPWM_GEN1_T1_SEL_V 0x7 -#define MCPWM_GEN1_T1_SEL_S 7 -/* MCPWM_GEN1_T0_SEL : R/W ;bitpos:[6:4] ;default: 3'd0 ; */ -/*description: Source selection for PWM generate1 event_t0 take effect immediately - 0: fault_event0 1: fault_event1 2: fault_event2 3: sync_taken 4: none*/ -#define MCPWM_GEN1_T0_SEL 0x00000007 -#define MCPWM_GEN1_T0_SEL_M ((MCPWM_GEN1_T0_SEL_V)<<(MCPWM_GEN1_T0_SEL_S)) -#define MCPWM_GEN1_T0_SEL_V 0x7 -#define MCPWM_GEN1_T0_SEL_S 4 -/* MCPWM_GEN1_CFG_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: Update method for PWM generate1's active reg of configuration. - 0: immediate bit0: TEZ bit1: TEP bit2: sync. bit3: disable update*/ -#define MCPWM_GEN1_CFG_UPMETHOD 0x0000000F -#define MCPWM_GEN1_CFG_UPMETHOD_M ((MCPWM_GEN1_CFG_UPMETHOD_V)<<(MCPWM_GEN1_CFG_UPMETHOD_S)) -#define MCPWM_GEN1_CFG_UPMETHOD_V 0xF +/** MCPWM_GEN1_CFG0_REG register + * PWM generator 1 event T0 and T1 handling + */ +#define MCPWM_GEN1_CFG0_REG(i) (DR_REG_MCPWM_BASE(i) + 0x80) +/** MCPWM_GEN1_CFG_UPMETHOD : R/W; bitpos: [3:0]; default: 0; + * Update method for PWM generator 1's active register of configuration. When all bits + * are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to + * 1:sync;when bit3 is set to 1:disable the update. + */ +#define MCPWM_GEN1_CFG_UPMETHOD 0x0000000FU +#define MCPWM_GEN1_CFG_UPMETHOD_M (MCPWM_GEN1_CFG_UPMETHOD_V << MCPWM_GEN1_CFG_UPMETHOD_S) +#define MCPWM_GEN1_CFG_UPMETHOD_V 0x0000000FU #define MCPWM_GEN1_CFG_UPMETHOD_S 0 +/** MCPWM_GEN1_T0_SEL : R/W; bitpos: [6:4]; default: 0; + * Source selection for PWM generator 1 event_t0, take effect immediately, 0: + * fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none + */ +#define MCPWM_GEN1_T0_SEL 0x00000007U +#define MCPWM_GEN1_T0_SEL_M (MCPWM_GEN1_T0_SEL_V << MCPWM_GEN1_T0_SEL_S) +#define MCPWM_GEN1_T0_SEL_V 0x00000007U +#define MCPWM_GEN1_T0_SEL_S 4 +/** MCPWM_GEN1_T1_SEL : R/W; bitpos: [9:7]; default: 0; + * Source selection for PWM generator 1 event_t1, take effect immediately, 0: + * fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none + */ +#define MCPWM_GEN1_T1_SEL 0x00000007U +#define MCPWM_GEN1_T1_SEL_M (MCPWM_GEN1_T1_SEL_V << MCPWM_GEN1_T1_SEL_S) +#define MCPWM_GEN1_T1_SEL_V 0x00000007U +#define MCPWM_GEN1_T1_SEL_S 7 -#define MCPWM_GEN1_FORCE_REG(i) (REG_MCPWM_BASE(i) + 0x0084) -/* MCPWM_GEN1_B_NCIFORCE_MODE : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ -/*description: Non-continuous immediate software force mode for PWM1B 0: disabled - 1: low 2: high 3: disabled*/ -#define MCPWM_GEN1_B_NCIFORCE_MODE 0x00000003 -#define MCPWM_GEN1_B_NCIFORCE_MODE_M ((MCPWM_GEN1_B_NCIFORCE_MODE_V)<<(MCPWM_GEN1_B_NCIFORCE_MODE_S)) -#define MCPWM_GEN1_B_NCIFORCE_MODE_V 0x3 -#define MCPWM_GEN1_B_NCIFORCE_MODE_S 14 -/* MCPWM_GEN1_B_NCIFORCE : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: Non-continuous immediate software force trigger for PWM1B a - toggle will trigger a force event*/ -#define MCPWM_GEN1_B_NCIFORCE (BIT(13)) -#define MCPWM_GEN1_B_NCIFORCE_M (BIT(13)) -#define MCPWM_GEN1_B_NCIFORCE_V 0x1 -#define MCPWM_GEN1_B_NCIFORCE_S 13 -/* MCPWM_GEN1_A_NCIFORCE_MODE : R/W ;bitpos:[12:11] ;default: 2'd0 ; */ -/*description: Non-continuous immediate software force mode for PWM1A 0: disabled - 1: low 2: high 3: disabled*/ -#define MCPWM_GEN1_A_NCIFORCE_MODE 0x00000003 -#define MCPWM_GEN1_A_NCIFORCE_MODE_M ((MCPWM_GEN1_A_NCIFORCE_MODE_V)<<(MCPWM_GEN1_A_NCIFORCE_MODE_S)) -#define MCPWM_GEN1_A_NCIFORCE_MODE_V 0x3 -#define MCPWM_GEN1_A_NCIFORCE_MODE_S 11 -/* MCPWM_GEN1_A_NCIFORCE : R/W ;bitpos:[10] ;default: 1'd0 ; */ -/*description: Non-continuous immediate software force trigger for PWM1A a - toggle will trigger a force event*/ -#define MCPWM_GEN1_A_NCIFORCE (BIT(10)) -#define MCPWM_GEN1_A_NCIFORCE_M (BIT(10)) -#define MCPWM_GEN1_A_NCIFORCE_V 0x1 -#define MCPWM_GEN1_A_NCIFORCE_S 10 -/* MCPWM_GEN1_B_CNTUFORCE_MODE : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ -/*description: Continuous software force mode for PWM1B. 0: disabled 1: low - 2: high 3: disabled*/ -#define MCPWM_GEN1_B_CNTUFORCE_MODE 0x00000003 -#define MCPWM_GEN1_B_CNTUFORCE_MODE_M ((MCPWM_GEN1_B_CNTUFORCE_MODE_V)<<(MCPWM_GEN1_B_CNTUFORCE_MODE_S)) -#define MCPWM_GEN1_B_CNTUFORCE_MODE_V 0x3 -#define MCPWM_GEN1_B_CNTUFORCE_MODE_S 8 -/* MCPWM_GEN1_A_CNTUFORCE_MODE : R/W ;bitpos:[7:6] ;default: 2'd0 ; */ -/*description: Continuous software force mode for PWM1A. 0: disabled 1: low - 2: high 3: disabled*/ -#define MCPWM_GEN1_A_CNTUFORCE_MODE 0x00000003 -#define MCPWM_GEN1_A_CNTUFORCE_MODE_M ((MCPWM_GEN1_A_CNTUFORCE_MODE_V)<<(MCPWM_GEN1_A_CNTUFORCE_MODE_S)) -#define MCPWM_GEN1_A_CNTUFORCE_MODE_V 0x3 -#define MCPWM_GEN1_A_CNTUFORCE_MODE_S 6 -/* MCPWM_GEN1_CNTUFORCE_UPMETHOD : R/W ;bitpos:[5:0] ;default: 6'h20 ; */ -/*description: Update method for continuous software force of PWM generator1. - 0: immediate bit0: TEZ bit1: TEP bit2: TEA bit3: TEB bit4: sync bit5: disable update. (TEA/B here and below means an event generated when timer value equals A/B register)*/ -#define MCPWM_GEN1_CNTUFORCE_UPMETHOD 0x0000003F -#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_M ((MCPWM_GEN1_CNTUFORCE_UPMETHOD_V)<<(MCPWM_GEN1_CNTUFORCE_UPMETHOD_S)) -#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_V 0x3F +/** MCPWM_GEN1_FORCE_REG register + * Permissives to force PWM1A and PWM1B outputs by software + */ +#define MCPWM_GEN1_FORCE_REG(i) (DR_REG_MCPWM_BASE(i) + 0x84) +/** MCPWM_GEN1_CNTUFORCE_UPMETHOD : R/W; bitpos: [5:0]; default: 32; + * Updating method for continuous software force of PWM generator 1. When all bits are + * set to 0: immediately, when bit0 is set to 1: TEZ,when bit1 is set to 1: TEP, when + * bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync, + * when bit5 is set to 1: disable update. (TEA/B here and below means an event + * generated when the timer's value equals to that of register A/B.) + */ +#define MCPWM_GEN1_CNTUFORCE_UPMETHOD 0x0000003FU +#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_M (MCPWM_GEN1_CNTUFORCE_UPMETHOD_V << MCPWM_GEN1_CNTUFORCE_UPMETHOD_S) +#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_V 0x0000003FU #define MCPWM_GEN1_CNTUFORCE_UPMETHOD_S 0 +/** MCPWM_GEN1_A_CNTUFORCE_MODE : R/W; bitpos: [7:6]; default: 0; + * Continuous software force mode for PWM1A. 0: disabled, 1: low, 2: high, 3: disabled + */ +#define MCPWM_GEN1_A_CNTUFORCE_MODE 0x00000003U +#define MCPWM_GEN1_A_CNTUFORCE_MODE_M (MCPWM_GEN1_A_CNTUFORCE_MODE_V << MCPWM_GEN1_A_CNTUFORCE_MODE_S) +#define MCPWM_GEN1_A_CNTUFORCE_MODE_V 0x00000003U +#define MCPWM_GEN1_A_CNTUFORCE_MODE_S 6 +/** MCPWM_GEN1_B_CNTUFORCE_MODE : R/W; bitpos: [9:8]; default: 0; + * Continuous software force mode for PWM1B. 0: disabled, 1: low, 2: high, 3: disabled + */ +#define MCPWM_GEN1_B_CNTUFORCE_MODE 0x00000003U +#define MCPWM_GEN1_B_CNTUFORCE_MODE_M (MCPWM_GEN1_B_CNTUFORCE_MODE_V << MCPWM_GEN1_B_CNTUFORCE_MODE_S) +#define MCPWM_GEN1_B_CNTUFORCE_MODE_V 0x00000003U +#define MCPWM_GEN1_B_CNTUFORCE_MODE_S 8 +/** MCPWM_GEN1_A_NCIFORCE : R/W; bitpos: [10]; default: 0; + * Trigger of non-continuous immediate software-force event for PWM1A, a toggle will + * trigger a force event. + */ +#define MCPWM_GEN1_A_NCIFORCE (BIT(10)) +#define MCPWM_GEN1_A_NCIFORCE_M (MCPWM_GEN1_A_NCIFORCE_V << MCPWM_GEN1_A_NCIFORCE_S) +#define MCPWM_GEN1_A_NCIFORCE_V 0x00000001U +#define MCPWM_GEN1_A_NCIFORCE_S 10 +/** MCPWM_GEN1_A_NCIFORCE_MODE : R/W; bitpos: [12:11]; default: 0; + * non-continuous immediate software force mode for PWM1A, 0: disabled, 1: low, 2: + * high, 3: disabled + */ +#define MCPWM_GEN1_A_NCIFORCE_MODE 0x00000003U +#define MCPWM_GEN1_A_NCIFORCE_MODE_M (MCPWM_GEN1_A_NCIFORCE_MODE_V << MCPWM_GEN1_A_NCIFORCE_MODE_S) +#define MCPWM_GEN1_A_NCIFORCE_MODE_V 0x00000003U +#define MCPWM_GEN1_A_NCIFORCE_MODE_S 11 +/** MCPWM_GEN1_B_NCIFORCE : R/W; bitpos: [13]; default: 0; + * Trigger of non-continuous immediate software-force event for PWM1B, a toggle will + * trigger a force event. + */ +#define MCPWM_GEN1_B_NCIFORCE (BIT(13)) +#define MCPWM_GEN1_B_NCIFORCE_M (MCPWM_GEN1_B_NCIFORCE_V << MCPWM_GEN1_B_NCIFORCE_S) +#define MCPWM_GEN1_B_NCIFORCE_V 0x00000001U +#define MCPWM_GEN1_B_NCIFORCE_S 13 +/** MCPWM_GEN1_B_NCIFORCE_MODE : R/W; bitpos: [15:14]; default: 0; + * non-continuous immediate software force mode for PWM1B, 0: disabled, 1: low, 2: + * high, 3: disabled + */ +#define MCPWM_GEN1_B_NCIFORCE_MODE 0x00000003U +#define MCPWM_GEN1_B_NCIFORCE_MODE_M (MCPWM_GEN1_B_NCIFORCE_MODE_V << MCPWM_GEN1_B_NCIFORCE_MODE_S) +#define MCPWM_GEN1_B_NCIFORCE_MODE_V 0x00000003U +#define MCPWM_GEN1_B_NCIFORCE_MODE_S 14 -#define MCPWM_GEN1_A_REG(i) (REG_MCPWM_BASE(i) + 0x0088) -/* MCPWM_GEN1_A_DT1 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ -/*description: Action on PWM1A triggered by event_t1 when timer decreasing. - 0: no change 1: low 2: high 3: toggle*/ -#define MCPWM_GEN1_A_DT1 0x00000003 -#define MCPWM_GEN1_A_DT1_M ((MCPWM_GEN1_A_DT1_V)<<(MCPWM_GEN1_A_DT1_S)) -#define MCPWM_GEN1_A_DT1_V 0x3 -#define MCPWM_GEN1_A_DT1_S 22 -/* MCPWM_GEN1_A_DT0 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ -/*description: Action on PWM1A triggered by event_t0 when timer decreasing*/ -#define MCPWM_GEN1_A_DT0 0x00000003 -#define MCPWM_GEN1_A_DT0_M ((MCPWM_GEN1_A_DT0_V)<<(MCPWM_GEN1_A_DT0_S)) -#define MCPWM_GEN1_A_DT0_V 0x3 -#define MCPWM_GEN1_A_DT0_S 20 -/* MCPWM_GEN1_A_DTEB : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ -/*description: Action on PWM1A triggered by event TEB when timer decreasing*/ -#define MCPWM_GEN1_A_DTEB 0x00000003 -#define MCPWM_GEN1_A_DTEB_M ((MCPWM_GEN1_A_DTEB_V)<<(MCPWM_GEN1_A_DTEB_S)) -#define MCPWM_GEN1_A_DTEB_V 0x3 -#define MCPWM_GEN1_A_DTEB_S 18 -/* MCPWM_GEN1_A_DTEA : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ -/*description: Action on PWM1A triggered by event TEA when timer decreasing*/ -#define MCPWM_GEN1_A_DTEA 0x00000003 -#define MCPWM_GEN1_A_DTEA_M ((MCPWM_GEN1_A_DTEA_V)<<(MCPWM_GEN1_A_DTEA_S)) -#define MCPWM_GEN1_A_DTEA_V 0x3 -#define MCPWM_GEN1_A_DTEA_S 16 -/* MCPWM_GEN1_A_DTEP : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ -/*description: Action on PWM1A triggered by event TEP when timer decreasing*/ -#define MCPWM_GEN1_A_DTEP 0x00000003 -#define MCPWM_GEN1_A_DTEP_M ((MCPWM_GEN1_A_DTEP_V)<<(MCPWM_GEN1_A_DTEP_S)) -#define MCPWM_GEN1_A_DTEP_V 0x3 -#define MCPWM_GEN1_A_DTEP_S 14 -/* MCPWM_GEN1_A_DTEZ : R/W ;bitpos:[13:12] ;default: 2'd0 ; */ -/*description: Action on PWM1A triggered by event TEZ when timer decreasing*/ -#define MCPWM_GEN1_A_DTEZ 0x00000003 -#define MCPWM_GEN1_A_DTEZ_M ((MCPWM_GEN1_A_DTEZ_V)<<(MCPWM_GEN1_A_DTEZ_S)) -#define MCPWM_GEN1_A_DTEZ_V 0x3 -#define MCPWM_GEN1_A_DTEZ_S 12 -/* MCPWM_GEN1_A_UT1 : R/W ;bitpos:[11:10] ;default: 2'd0 ; */ -/*description: Action on PWM1A triggered by event_t1 when timer increasing*/ -#define MCPWM_GEN1_A_UT1 0x00000003 -#define MCPWM_GEN1_A_UT1_M ((MCPWM_GEN1_A_UT1_V)<<(MCPWM_GEN1_A_UT1_S)) -#define MCPWM_GEN1_A_UT1_V 0x3 -#define MCPWM_GEN1_A_UT1_S 10 -/* MCPWM_GEN1_A_UT0 : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ -/*description: Action on PWM1A triggered by event_t0 when timer increasing*/ -#define MCPWM_GEN1_A_UT0 0x00000003 -#define MCPWM_GEN1_A_UT0_M ((MCPWM_GEN1_A_UT0_V)<<(MCPWM_GEN1_A_UT0_S)) -#define MCPWM_GEN1_A_UT0_V 0x3 -#define MCPWM_GEN1_A_UT0_S 8 -/* MCPWM_GEN1_A_UTEB : R/W ;bitpos:[7:6] ;default: 2'd0 ; */ -/*description: Action on PWM1A triggered by event TEB when timer increasing*/ -#define MCPWM_GEN1_A_UTEB 0x00000003 -#define MCPWM_GEN1_A_UTEB_M ((MCPWM_GEN1_A_UTEB_V)<<(MCPWM_GEN1_A_UTEB_S)) -#define MCPWM_GEN1_A_UTEB_V 0x3 -#define MCPWM_GEN1_A_UTEB_S 6 -/* MCPWM_GEN1_A_UTEA : R/W ;bitpos:[5:4] ;default: 2'd0 ; */ -/*description: Action on PWM1A triggered by event TEA when timer increasing*/ -#define MCPWM_GEN1_A_UTEA 0x00000003 -#define MCPWM_GEN1_A_UTEA_M ((MCPWM_GEN1_A_UTEA_V)<<(MCPWM_GEN1_A_UTEA_S)) -#define MCPWM_GEN1_A_UTEA_V 0x3 -#define MCPWM_GEN1_A_UTEA_S 4 -/* MCPWM_GEN1_A_UTEP : R/W ;bitpos:[3:2] ;default: 2'd0 ; */ -/*description: Action on PWM1A triggered by event TEP when timer increasing*/ -#define MCPWM_GEN1_A_UTEP 0x00000003 -#define MCPWM_GEN1_A_UTEP_M ((MCPWM_GEN1_A_UTEP_V)<<(MCPWM_GEN1_A_UTEP_S)) -#define MCPWM_GEN1_A_UTEP_V 0x3 -#define MCPWM_GEN1_A_UTEP_S 2 -/* MCPWM_GEN1_A_UTEZ : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: Action on PWM1A triggered by event TEZ when timer increasing*/ -#define MCPWM_GEN1_A_UTEZ 0x00000003 -#define MCPWM_GEN1_A_UTEZ_M ((MCPWM_GEN1_A_UTEZ_V)<<(MCPWM_GEN1_A_UTEZ_S)) -#define MCPWM_GEN1_A_UTEZ_V 0x3 +/** MCPWM_GEN1_A_REG register + * Actions triggered by events on PWM1A + */ +#define MCPWM_GEN1_A_REG(i) (DR_REG_MCPWM_BASE(i) + 0x88) +/** MCPWM_GEN1_A_UTEZ : R/W; bitpos: [1:0]; default: 0; + * Action on PWM1A triggered by event TEZ when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN1_A_UTEZ 0x00000003U +#define MCPWM_GEN1_A_UTEZ_M (MCPWM_GEN1_A_UTEZ_V << MCPWM_GEN1_A_UTEZ_S) +#define MCPWM_GEN1_A_UTEZ_V 0x00000003U #define MCPWM_GEN1_A_UTEZ_S 0 +/** MCPWM_GEN1_A_UTEP : R/W; bitpos: [3:2]; default: 0; + * Action on PWM1A triggered by event TEP when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN1_A_UTEP 0x00000003U +#define MCPWM_GEN1_A_UTEP_M (MCPWM_GEN1_A_UTEP_V << MCPWM_GEN1_A_UTEP_S) +#define MCPWM_GEN1_A_UTEP_V 0x00000003U +#define MCPWM_GEN1_A_UTEP_S 2 +/** MCPWM_GEN1_A_UTEA : R/W; bitpos: [5:4]; default: 0; + * Action on PWM1A triggered by event TEA when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN1_A_UTEA 0x00000003U +#define MCPWM_GEN1_A_UTEA_M (MCPWM_GEN1_A_UTEA_V << MCPWM_GEN1_A_UTEA_S) +#define MCPWM_GEN1_A_UTEA_V 0x00000003U +#define MCPWM_GEN1_A_UTEA_S 4 +/** MCPWM_GEN1_A_UTEB : R/W; bitpos: [7:6]; default: 0; + * Action on PWM1A triggered by event TEB when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN1_A_UTEB 0x00000003U +#define MCPWM_GEN1_A_UTEB_M (MCPWM_GEN1_A_UTEB_V << MCPWM_GEN1_A_UTEB_S) +#define MCPWM_GEN1_A_UTEB_V 0x00000003U +#define MCPWM_GEN1_A_UTEB_S 6 +/** MCPWM_GEN1_A_UT0 : R/W; bitpos: [9:8]; default: 0; + * Action on PWM1A triggered by event_t0 when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN1_A_UT0 0x00000003U +#define MCPWM_GEN1_A_UT0_M (MCPWM_GEN1_A_UT0_V << MCPWM_GEN1_A_UT0_S) +#define MCPWM_GEN1_A_UT0_V 0x00000003U +#define MCPWM_GEN1_A_UT0_S 8 +/** MCPWM_GEN1_A_UT1 : R/W; bitpos: [11:10]; default: 0; + * Action on PWM1A triggered by event_t1 when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN1_A_UT1 0x00000003U +#define MCPWM_GEN1_A_UT1_M (MCPWM_GEN1_A_UT1_V << MCPWM_GEN1_A_UT1_S) +#define MCPWM_GEN1_A_UT1_V 0x00000003U +#define MCPWM_GEN1_A_UT1_S 10 +/** MCPWM_GEN1_A_DTEZ : R/W; bitpos: [13:12]; default: 0; + * Action on PWM1A triggered by event TEZ when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN1_A_DTEZ 0x00000003U +#define MCPWM_GEN1_A_DTEZ_M (MCPWM_GEN1_A_DTEZ_V << MCPWM_GEN1_A_DTEZ_S) +#define MCPWM_GEN1_A_DTEZ_V 0x00000003U +#define MCPWM_GEN1_A_DTEZ_S 12 +/** MCPWM_GEN1_A_DTEP : R/W; bitpos: [15:14]; default: 0; + * Action on PWM1A triggered by event TEP when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN1_A_DTEP 0x00000003U +#define MCPWM_GEN1_A_DTEP_M (MCPWM_GEN1_A_DTEP_V << MCPWM_GEN1_A_DTEP_S) +#define MCPWM_GEN1_A_DTEP_V 0x00000003U +#define MCPWM_GEN1_A_DTEP_S 14 +/** MCPWM_GEN1_A_DTEA : R/W; bitpos: [17:16]; default: 0; + * Action on PWM1A triggered by event TEA when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN1_A_DTEA 0x00000003U +#define MCPWM_GEN1_A_DTEA_M (MCPWM_GEN1_A_DTEA_V << MCPWM_GEN1_A_DTEA_S) +#define MCPWM_GEN1_A_DTEA_V 0x00000003U +#define MCPWM_GEN1_A_DTEA_S 16 +/** MCPWM_GEN1_A_DTEB : R/W; bitpos: [19:18]; default: 0; + * Action on PWM1A triggered by event TEB when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN1_A_DTEB 0x00000003U +#define MCPWM_GEN1_A_DTEB_M (MCPWM_GEN1_A_DTEB_V << MCPWM_GEN1_A_DTEB_S) +#define MCPWM_GEN1_A_DTEB_V 0x00000003U +#define MCPWM_GEN1_A_DTEB_S 18 +/** MCPWM_GEN1_A_DT0 : R/W; bitpos: [21:20]; default: 0; + * Action on PWM1A triggered by event_t0 when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN1_A_DT0 0x00000003U +#define MCPWM_GEN1_A_DT0_M (MCPWM_GEN1_A_DT0_V << MCPWM_GEN1_A_DT0_S) +#define MCPWM_GEN1_A_DT0_V 0x00000003U +#define MCPWM_GEN1_A_DT0_S 20 +/** MCPWM_GEN1_A_DT1 : R/W; bitpos: [23:22]; default: 0; + * Action on PWM1A triggered by event_t1 when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN1_A_DT1 0x00000003U +#define MCPWM_GEN1_A_DT1_M (MCPWM_GEN1_A_DT1_V << MCPWM_GEN1_A_DT1_S) +#define MCPWM_GEN1_A_DT1_V 0x00000003U +#define MCPWM_GEN1_A_DT1_S 22 -#define MCPWM_GEN1_B_REG(i) (REG_MCPWM_BASE(i) + 0x008c) -/* MCPWM_GEN1_B_DT1 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ -/*description: Action on PWM1B triggered by event_t1 when timer decreasing. - 0: no change 1: low 2: high 3: toggle*/ -#define MCPWM_GEN1_B_DT1 0x00000003 -#define MCPWM_GEN1_B_DT1_M ((MCPWM_GEN1_B_DT1_V)<<(MCPWM_GEN1_B_DT1_S)) -#define MCPWM_GEN1_B_DT1_V 0x3 -#define MCPWM_GEN1_B_DT1_S 22 -/* MCPWM_GEN1_B_DT0 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ -/*description: Action on PWM1B triggered by event_t0 when timer decreasing*/ -#define MCPWM_GEN1_B_DT0 0x00000003 -#define MCPWM_GEN1_B_DT0_M ((MCPWM_GEN1_B_DT0_V)<<(MCPWM_GEN1_B_DT0_S)) -#define MCPWM_GEN1_B_DT0_V 0x3 -#define MCPWM_GEN1_B_DT0_S 20 -/* MCPWM_GEN1_B_DTEB : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ -/*description: Action on PWM1B triggered by event TEB when timer decreasing*/ -#define MCPWM_GEN1_B_DTEB 0x00000003 -#define MCPWM_GEN1_B_DTEB_M ((MCPWM_GEN1_B_DTEB_V)<<(MCPWM_GEN1_B_DTEB_S)) -#define MCPWM_GEN1_B_DTEB_V 0x3 -#define MCPWM_GEN1_B_DTEB_S 18 -/* MCPWM_GEN1_B_DTEA : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ -/*description: Action on PWM1B triggered by event TEA when timer decreasing*/ -#define MCPWM_GEN1_B_DTEA 0x00000003 -#define MCPWM_GEN1_B_DTEA_M ((MCPWM_GEN1_B_DTEA_V)<<(MCPWM_GEN1_B_DTEA_S)) -#define MCPWM_GEN1_B_DTEA_V 0x3 -#define MCPWM_GEN1_B_DTEA_S 16 -/* MCPWM_GEN1_B_DTEP : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ -/*description: Action on PWM1B triggered by event TEP when timer decreasing*/ -#define MCPWM_GEN1_B_DTEP 0x00000003 -#define MCPWM_GEN1_B_DTEP_M ((MCPWM_GEN1_B_DTEP_V)<<(MCPWM_GEN1_B_DTEP_S)) -#define MCPWM_GEN1_B_DTEP_V 0x3 -#define MCPWM_GEN1_B_DTEP_S 14 -/* MCPWM_GEN1_B_DTEZ : R/W ;bitpos:[13:12] ;default: 2'd0 ; */ -/*description: Action on PWM1B triggered by event TEZ when timer decreasing*/ -#define MCPWM_GEN1_B_DTEZ 0x00000003 -#define MCPWM_GEN1_B_DTEZ_M ((MCPWM_GEN1_B_DTEZ_V)<<(MCPWM_GEN1_B_DTEZ_S)) -#define MCPWM_GEN1_B_DTEZ_V 0x3 -#define MCPWM_GEN1_B_DTEZ_S 12 -/* MCPWM_GEN1_B_UT1 : R/W ;bitpos:[11:10] ;default: 2'd0 ; */ -/*description: Action on PWM1B triggered by event_t1 when timer increasing*/ -#define MCPWM_GEN1_B_UT1 0x00000003 -#define MCPWM_GEN1_B_UT1_M ((MCPWM_GEN1_B_UT1_V)<<(MCPWM_GEN1_B_UT1_S)) -#define MCPWM_GEN1_B_UT1_V 0x3 -#define MCPWM_GEN1_B_UT1_S 10 -/* MCPWM_GEN1_B_UT0 : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ -/*description: Action on PWM1B triggered by event_t0 when timer increasing*/ -#define MCPWM_GEN1_B_UT0 0x00000003 -#define MCPWM_GEN1_B_UT0_M ((MCPWM_GEN1_B_UT0_V)<<(MCPWM_GEN1_B_UT0_S)) -#define MCPWM_GEN1_B_UT0_V 0x3 -#define MCPWM_GEN1_B_UT0_S 8 -/* MCPWM_GEN1_B_UTEB : R/W ;bitpos:[7:6] ;default: 2'd0 ; */ -/*description: Action on PWM1B triggered by event TEB when timer increasing*/ -#define MCPWM_GEN1_B_UTEB 0x00000003 -#define MCPWM_GEN1_B_UTEB_M ((MCPWM_GEN1_B_UTEB_V)<<(MCPWM_GEN1_B_UTEB_S)) -#define MCPWM_GEN1_B_UTEB_V 0x3 -#define MCPWM_GEN1_B_UTEB_S 6 -/* MCPWM_GEN1_B_UTEA : R/W ;bitpos:[5:4] ;default: 2'd0 ; */ -/*description: Action on PWM1B triggered by event TEA when timer increasing*/ -#define MCPWM_GEN1_B_UTEA 0x00000003 -#define MCPWM_GEN1_B_UTEA_M ((MCPWM_GEN1_B_UTEA_V)<<(MCPWM_GEN1_B_UTEA_S)) -#define MCPWM_GEN1_B_UTEA_V 0x3 -#define MCPWM_GEN1_B_UTEA_S 4 -/* MCPWM_GEN1_B_UTEP : R/W ;bitpos:[3:2] ;default: 2'd0 ; */ -/*description: Action on PWM1B triggered by event TEP when timer increasing*/ -#define MCPWM_GEN1_B_UTEP 0x00000003 -#define MCPWM_GEN1_B_UTEP_M ((MCPWM_GEN1_B_UTEP_V)<<(MCPWM_GEN1_B_UTEP_S)) -#define MCPWM_GEN1_B_UTEP_V 0x3 -#define MCPWM_GEN1_B_UTEP_S 2 -/* MCPWM_GEN1_B_UTEZ : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: Action on PWM1B triggered by event TEZ when timer increasing*/ -#define MCPWM_GEN1_B_UTEZ 0x00000003 -#define MCPWM_GEN1_B_UTEZ_M ((MCPWM_GEN1_B_UTEZ_V)<<(MCPWM_GEN1_B_UTEZ_S)) -#define MCPWM_GEN1_B_UTEZ_V 0x3 +/** MCPWM_GEN1_B_REG register + * Actions triggered by events on PWM1B + */ +#define MCPWM_GEN1_B_REG(i) (DR_REG_MCPWM_BASE(i) + 0x8c) +/** MCPWM_GEN1_B_UTEZ : R/W; bitpos: [1:0]; default: 0; + * Action on PWM1B triggered by event TEZ when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN1_B_UTEZ 0x00000003U +#define MCPWM_GEN1_B_UTEZ_M (MCPWM_GEN1_B_UTEZ_V << MCPWM_GEN1_B_UTEZ_S) +#define MCPWM_GEN1_B_UTEZ_V 0x00000003U #define MCPWM_GEN1_B_UTEZ_S 0 - -#define MCPWM_DT1_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x0090) -/* MCPWM_DT1_CLK_SEL : R/W ;bitpos:[17] ;default: 1'd0 ; */ -/*description: Dead time generator 1 clock selection. 0: PWM_clk 1: PT_clk*/ -#define MCPWM_DT1_CLK_SEL (BIT(17)) -#define MCPWM_DT1_CLK_SEL_M (BIT(17)) -#define MCPWM_DT1_CLK_SEL_V 0x1 -#define MCPWM_DT1_CLK_SEL_S 17 -/* MCPWM_DT1_B_OUTBYPASS : R/W ;bitpos:[16] ;default: 1'd1 ; */ -/*description: S0 in documentation*/ -#define MCPWM_DT1_B_OUTBYPASS (BIT(16)) -#define MCPWM_DT1_B_OUTBYPASS_M (BIT(16)) -#define MCPWM_DT1_B_OUTBYPASS_V 0x1 -#define MCPWM_DT1_B_OUTBYPASS_S 16 -/* MCPWM_DT1_A_OUTBYPASS : R/W ;bitpos:[15] ;default: 1'd1 ; */ -/*description: S1 in documentation*/ -#define MCPWM_DT1_A_OUTBYPASS (BIT(15)) -#define MCPWM_DT1_A_OUTBYPASS_M (BIT(15)) -#define MCPWM_DT1_A_OUTBYPASS_V 0x1 -#define MCPWM_DT1_A_OUTBYPASS_S 15 -/* MCPWM_DT1_FED_OUTINVERT : R/W ;bitpos:[14] ;default: 1'd0 ; */ -/*description: S3 in documentation*/ -#define MCPWM_DT1_FED_OUTINVERT (BIT(14)) -#define MCPWM_DT1_FED_OUTINVERT_M (BIT(14)) -#define MCPWM_DT1_FED_OUTINVERT_V 0x1 -#define MCPWM_DT1_FED_OUTINVERT_S 14 -/* MCPWM_DT1_RED_OUTINVERT : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: S2 in documentation*/ -#define MCPWM_DT1_RED_OUTINVERT (BIT(13)) -#define MCPWM_DT1_RED_OUTINVERT_M (BIT(13)) -#define MCPWM_DT1_RED_OUTINVERT_V 0x1 -#define MCPWM_DT1_RED_OUTINVERT_S 13 -/* MCPWM_DT1_FED_INSEL : R/W ;bitpos:[12] ;default: 1'd0 ; */ -/*description: S5 in documentation*/ -#define MCPWM_DT1_FED_INSEL (BIT(12)) -#define MCPWM_DT1_FED_INSEL_M (BIT(12)) -#define MCPWM_DT1_FED_INSEL_V 0x1 -#define MCPWM_DT1_FED_INSEL_S 12 -/* MCPWM_DT1_RED_INSEL : R/W ;bitpos:[11] ;default: 1'd0 ; */ -/*description: S4 in documentation*/ -#define MCPWM_DT1_RED_INSEL (BIT(11)) -#define MCPWM_DT1_RED_INSEL_M (BIT(11)) -#define MCPWM_DT1_RED_INSEL_V 0x1 -#define MCPWM_DT1_RED_INSEL_S 11 -/* MCPWM_DT1_B_OUTSWAP : R/W ;bitpos:[10] ;default: 1'd0 ; */ -/*description: S7 in documentation*/ -#define MCPWM_DT1_B_OUTSWAP (BIT(10)) -#define MCPWM_DT1_B_OUTSWAP_M (BIT(10)) -#define MCPWM_DT1_B_OUTSWAP_V 0x1 -#define MCPWM_DT1_B_OUTSWAP_S 10 -/* MCPWM_DT1_A_OUTSWAP : R/W ;bitpos:[9] ;default: 1'd0 ; */ -/*description: S6 in documentation*/ -#define MCPWM_DT1_A_OUTSWAP (BIT(9)) -#define MCPWM_DT1_A_OUTSWAP_M (BIT(9)) -#define MCPWM_DT1_A_OUTSWAP_V 0x1 -#define MCPWM_DT1_A_OUTSWAP_S 9 -/* MCPWM_DT1_DEB_MODE : R/W ;bitpos:[8] ;default: 1'd0 ; */ -/*description: S8 in documentation dual-edge B mode 0: FED/RED take effect - on different path separately 1: FED/RED take effect on B path A out is in bypass or normal operation mode*/ -#define MCPWM_DT1_DEB_MODE (BIT(8)) -#define MCPWM_DT1_DEB_MODE_M (BIT(8)) -#define MCPWM_DT1_DEB_MODE_V 0x1 -#define MCPWM_DT1_DEB_MODE_S 8 -/* MCPWM_DT1_RED_UPMETHOD : R/W ;bitpos:[7:4] ;default: 4'd0 ; */ -/*description: Update method for RED (rising edge delay) active reg. 0: immediate - bit0: TEZ bit1: TEP bit2: sync bit3: disable update*/ -#define MCPWM_DT1_RED_UPMETHOD 0x0000000F -#define MCPWM_DT1_RED_UPMETHOD_M ((MCPWM_DT1_RED_UPMETHOD_V)<<(MCPWM_DT1_RED_UPMETHOD_S)) -#define MCPWM_DT1_RED_UPMETHOD_V 0xF -#define MCPWM_DT1_RED_UPMETHOD_S 4 -/* MCPWM_DT1_FED_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: Update method for FED (falling edge delay) active reg. 0: immediate - bit0: TEZ bit1: TEP bit2: sync bit3: disable update*/ -#define MCPWM_DT1_FED_UPMETHOD 0x0000000F -#define MCPWM_DT1_FED_UPMETHOD_M ((MCPWM_DT1_FED_UPMETHOD_V)<<(MCPWM_DT1_FED_UPMETHOD_S)) -#define MCPWM_DT1_FED_UPMETHOD_V 0xF +/** MCPWM_GEN1_B_UTEP : R/W; bitpos: [3:2]; default: 0; + * Action on PWM1B triggered by event TEP when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN1_B_UTEP 0x00000003U +#define MCPWM_GEN1_B_UTEP_M (MCPWM_GEN1_B_UTEP_V << MCPWM_GEN1_B_UTEP_S) +#define MCPWM_GEN1_B_UTEP_V 0x00000003U +#define MCPWM_GEN1_B_UTEP_S 2 +/** MCPWM_GEN1_B_UTEA : R/W; bitpos: [5:4]; default: 0; + * Action on PWM1B triggered by event TEA when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN1_B_UTEA 0x00000003U +#define MCPWM_GEN1_B_UTEA_M (MCPWM_GEN1_B_UTEA_V << MCPWM_GEN1_B_UTEA_S) +#define MCPWM_GEN1_B_UTEA_V 0x00000003U +#define MCPWM_GEN1_B_UTEA_S 4 +/** MCPWM_GEN1_B_UTEB : R/W; bitpos: [7:6]; default: 0; + * Action on PWM1B triggered by event TEB when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN1_B_UTEB 0x00000003U +#define MCPWM_GEN1_B_UTEB_M (MCPWM_GEN1_B_UTEB_V << MCPWM_GEN1_B_UTEB_S) +#define MCPWM_GEN1_B_UTEB_V 0x00000003U +#define MCPWM_GEN1_B_UTEB_S 6 +/** MCPWM_GEN1_B_UT0 : R/W; bitpos: [9:8]; default: 0; + * Action on PWM1B triggered by event_t0 when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN1_B_UT0 0x00000003U +#define MCPWM_GEN1_B_UT0_M (MCPWM_GEN1_B_UT0_V << MCPWM_GEN1_B_UT0_S) +#define MCPWM_GEN1_B_UT0_V 0x00000003U +#define MCPWM_GEN1_B_UT0_S 8 +/** MCPWM_GEN1_B_UT1 : R/W; bitpos: [11:10]; default: 0; + * Action on PWM1B triggered by event_t1 when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN1_B_UT1 0x00000003U +#define MCPWM_GEN1_B_UT1_M (MCPWM_GEN1_B_UT1_V << MCPWM_GEN1_B_UT1_S) +#define MCPWM_GEN1_B_UT1_V 0x00000003U +#define MCPWM_GEN1_B_UT1_S 10 +/** MCPWM_GEN1_B_DTEZ : R/W; bitpos: [13:12]; default: 0; + * Action on PWM1B triggered by event TEZ when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN1_B_DTEZ 0x00000003U +#define MCPWM_GEN1_B_DTEZ_M (MCPWM_GEN1_B_DTEZ_V << MCPWM_GEN1_B_DTEZ_S) +#define MCPWM_GEN1_B_DTEZ_V 0x00000003U +#define MCPWM_GEN1_B_DTEZ_S 12 +/** MCPWM_GEN1_B_DTEP : R/W; bitpos: [15:14]; default: 0; + * Action on PWM1B triggered by event TEP when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN1_B_DTEP 0x00000003U +#define MCPWM_GEN1_B_DTEP_M (MCPWM_GEN1_B_DTEP_V << MCPWM_GEN1_B_DTEP_S) +#define MCPWM_GEN1_B_DTEP_V 0x00000003U +#define MCPWM_GEN1_B_DTEP_S 14 +/** MCPWM_GEN1_B_DTEA : R/W; bitpos: [17:16]; default: 0; + * Action on PWM1B triggered by event TEA when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN1_B_DTEA 0x00000003U +#define MCPWM_GEN1_B_DTEA_M (MCPWM_GEN1_B_DTEA_V << MCPWM_GEN1_B_DTEA_S) +#define MCPWM_GEN1_B_DTEA_V 0x00000003U +#define MCPWM_GEN1_B_DTEA_S 16 +/** MCPWM_GEN1_B_DTEB : R/W; bitpos: [19:18]; default: 0; + * Action on PWM1B triggered by event TEB when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN1_B_DTEB 0x00000003U +#define MCPWM_GEN1_B_DTEB_M (MCPWM_GEN1_B_DTEB_V << MCPWM_GEN1_B_DTEB_S) +#define MCPWM_GEN1_B_DTEB_V 0x00000003U +#define MCPWM_GEN1_B_DTEB_S 18 +/** MCPWM_GEN1_B_DT0 : R/W; bitpos: [21:20]; default: 0; + * Action on PWM1B triggered by event_t0 when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN1_B_DT0 0x00000003U +#define MCPWM_GEN1_B_DT0_M (MCPWM_GEN1_B_DT0_V << MCPWM_GEN1_B_DT0_S) +#define MCPWM_GEN1_B_DT0_V 0x00000003U +#define MCPWM_GEN1_B_DT0_S 20 +/** MCPWM_GEN1_B_DT1 : R/W; bitpos: [23:22]; default: 0; + * Action on PWM1B triggered by event_t1 when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN1_B_DT1 0x00000003U +#define MCPWM_GEN1_B_DT1_M (MCPWM_GEN1_B_DT1_V << MCPWM_GEN1_B_DT1_S) +#define MCPWM_GEN1_B_DT1_V 0x00000003U +#define MCPWM_GEN1_B_DT1_S 22 + +/** MCPWM_DT1_CFG_REG register + * PWM generator 1 dead time type selection and configuration + */ +#define MCPWM_DT1_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0x90) +/** MCPWM_DT1_FED_UPMETHOD : R/W; bitpos: [3:0]; default: 0; + * Update method for FED (falling edge delay) active register. 0: immediate, when bit0 + * is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when + * bit3 is set to 1: disable the update + */ +#define MCPWM_DT1_FED_UPMETHOD 0x0000000FU +#define MCPWM_DT1_FED_UPMETHOD_M (MCPWM_DT1_FED_UPMETHOD_V << MCPWM_DT1_FED_UPMETHOD_S) +#define MCPWM_DT1_FED_UPMETHOD_V 0x0000000FU #define MCPWM_DT1_FED_UPMETHOD_S 0 +/** MCPWM_DT1_RED_UPMETHOD : R/W; bitpos: [7:4]; default: 0; + * Update method for RED (rising edge delay) active register. 0: immediate,when bit0 + * is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when + * bit3 is set to 1: disable the update + */ +#define MCPWM_DT1_RED_UPMETHOD 0x0000000FU +#define MCPWM_DT1_RED_UPMETHOD_M (MCPWM_DT1_RED_UPMETHOD_V << MCPWM_DT1_RED_UPMETHOD_S) +#define MCPWM_DT1_RED_UPMETHOD_V 0x0000000FU +#define MCPWM_DT1_RED_UPMETHOD_S 4 +/** MCPWM_DT1_DEB_MODE : R/W; bitpos: [8]; default: 0; + * S8 in table, dual-edge B mode, 0: fed/red take effect on different path separately, + * 1: fed/red take effect on B path, A out is in bypass or dulpB mode + */ +#define MCPWM_DT1_DEB_MODE (BIT(8)) +#define MCPWM_DT1_DEB_MODE_M (MCPWM_DT1_DEB_MODE_V << MCPWM_DT1_DEB_MODE_S) +#define MCPWM_DT1_DEB_MODE_V 0x00000001U +#define MCPWM_DT1_DEB_MODE_S 8 +/** MCPWM_DT1_A_OUTSWAP : R/W; bitpos: [9]; default: 0; + * S6 in table + */ +#define MCPWM_DT1_A_OUTSWAP (BIT(9)) +#define MCPWM_DT1_A_OUTSWAP_M (MCPWM_DT1_A_OUTSWAP_V << MCPWM_DT1_A_OUTSWAP_S) +#define MCPWM_DT1_A_OUTSWAP_V 0x00000001U +#define MCPWM_DT1_A_OUTSWAP_S 9 +/** MCPWM_DT1_B_OUTSWAP : R/W; bitpos: [10]; default: 0; + * S7 in table + */ +#define MCPWM_DT1_B_OUTSWAP (BIT(10)) +#define MCPWM_DT1_B_OUTSWAP_M (MCPWM_DT1_B_OUTSWAP_V << MCPWM_DT1_B_OUTSWAP_S) +#define MCPWM_DT1_B_OUTSWAP_V 0x00000001U +#define MCPWM_DT1_B_OUTSWAP_S 10 +/** MCPWM_DT1_RED_INSEL : R/W; bitpos: [11]; default: 0; + * S4 in table + */ +#define MCPWM_DT1_RED_INSEL (BIT(11)) +#define MCPWM_DT1_RED_INSEL_M (MCPWM_DT1_RED_INSEL_V << MCPWM_DT1_RED_INSEL_S) +#define MCPWM_DT1_RED_INSEL_V 0x00000001U +#define MCPWM_DT1_RED_INSEL_S 11 +/** MCPWM_DT1_FED_INSEL : R/W; bitpos: [12]; default: 0; + * S5 in table + */ +#define MCPWM_DT1_FED_INSEL (BIT(12)) +#define MCPWM_DT1_FED_INSEL_M (MCPWM_DT1_FED_INSEL_V << MCPWM_DT1_FED_INSEL_S) +#define MCPWM_DT1_FED_INSEL_V 0x00000001U +#define MCPWM_DT1_FED_INSEL_S 12 +/** MCPWM_DT1_RED_OUTINVERT : R/W; bitpos: [13]; default: 0; + * S2 in table + */ +#define MCPWM_DT1_RED_OUTINVERT (BIT(13)) +#define MCPWM_DT1_RED_OUTINVERT_M (MCPWM_DT1_RED_OUTINVERT_V << MCPWM_DT1_RED_OUTINVERT_S) +#define MCPWM_DT1_RED_OUTINVERT_V 0x00000001U +#define MCPWM_DT1_RED_OUTINVERT_S 13 +/** MCPWM_DT1_FED_OUTINVERT : R/W; bitpos: [14]; default: 0; + * S3 in table + */ +#define MCPWM_DT1_FED_OUTINVERT (BIT(14)) +#define MCPWM_DT1_FED_OUTINVERT_M (MCPWM_DT1_FED_OUTINVERT_V << MCPWM_DT1_FED_OUTINVERT_S) +#define MCPWM_DT1_FED_OUTINVERT_V 0x00000001U +#define MCPWM_DT1_FED_OUTINVERT_S 14 +/** MCPWM_DT1_A_OUTBYPASS : R/W; bitpos: [15]; default: 1; + * S1 in table + */ +#define MCPWM_DT1_A_OUTBYPASS (BIT(15)) +#define MCPWM_DT1_A_OUTBYPASS_M (MCPWM_DT1_A_OUTBYPASS_V << MCPWM_DT1_A_OUTBYPASS_S) +#define MCPWM_DT1_A_OUTBYPASS_V 0x00000001U +#define MCPWM_DT1_A_OUTBYPASS_S 15 +/** MCPWM_DT1_B_OUTBYPASS : R/W; bitpos: [16]; default: 1; + * S0 in table + */ +#define MCPWM_DT1_B_OUTBYPASS (BIT(16)) +#define MCPWM_DT1_B_OUTBYPASS_M (MCPWM_DT1_B_OUTBYPASS_V << MCPWM_DT1_B_OUTBYPASS_S) +#define MCPWM_DT1_B_OUTBYPASS_V 0x00000001U +#define MCPWM_DT1_B_OUTBYPASS_S 16 +/** MCPWM_DT1_CLK_SEL : R/W; bitpos: [17]; default: 0; + * Dead time clock selection. 0: PWM_clk, 1: PT_clk + */ +#define MCPWM_DT1_CLK_SEL (BIT(17)) +#define MCPWM_DT1_CLK_SEL_M (MCPWM_DT1_CLK_SEL_V << MCPWM_DT1_CLK_SEL_S) +#define MCPWM_DT1_CLK_SEL_V 0x00000001U +#define MCPWM_DT1_CLK_SEL_S 17 -#define MCPWM_DT1_FED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x0094) -/* MCPWM_DT1_FED : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ -/*description: Shadow reg for FED*/ -#define MCPWM_DT1_FED 0x0000FFFF -#define MCPWM_DT1_FED_M ((MCPWM_DT1_FED_V)<<(MCPWM_DT1_FED_S)) -#define MCPWM_DT1_FED_V 0xFFFF +/** MCPWM_DT1_FED_CFG_REG register + * PWM generator 1 shadow register for falling edge delay (FED). + */ +#define MCPWM_DT1_FED_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0x94) +/** MCPWM_DT1_FED : R/W; bitpos: [15:0]; default: 0; + * Shadow register for FED + */ +#define MCPWM_DT1_FED 0x0000FFFFU +#define MCPWM_DT1_FED_M (MCPWM_DT1_FED_V << MCPWM_DT1_FED_S) +#define MCPWM_DT1_FED_V 0x0000FFFFU #define MCPWM_DT1_FED_S 0 -#define MCPWM_DT1_RED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x0098) -/* MCPWM_DT1_RED : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ -/*description: Shadow reg for RED*/ -#define MCPWM_DT1_RED 0x0000FFFF -#define MCPWM_DT1_RED_M ((MCPWM_DT1_RED_V)<<(MCPWM_DT1_RED_S)) -#define MCPWM_DT1_RED_V 0xFFFF +/** MCPWM_DT1_RED_CFG_REG register + * PWM generator 1 shadow register for rising edge delay (RED). + */ +#define MCPWM_DT1_RED_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0x98) +/** MCPWM_DT1_RED : R/W; bitpos: [15:0]; default: 0; + * Shadow register for RED + */ +#define MCPWM_DT1_RED 0x0000FFFFU +#define MCPWM_DT1_RED_M (MCPWM_DT1_RED_V << MCPWM_DT1_RED_S) +#define MCPWM_DT1_RED_V 0x0000FFFFU #define MCPWM_DT1_RED_S 0 -#define MCPWM_CARRIER1_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x009c) -/* MCPWM_CARRIER1_IN_INVERT : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: When set invert the input of PWM1A and PWM1B for this submodule*/ -#define MCPWM_CARRIER1_IN_INVERT (BIT(13)) -#define MCPWM_CARRIER1_IN_INVERT_M (BIT(13)) -#define MCPWM_CARRIER1_IN_INVERT_V 0x1 -#define MCPWM_CARRIER1_IN_INVERT_S 13 -/* MCPWM_CARRIER1_OUT_INVERT : R/W ;bitpos:[12] ;default: 1'd0 ; */ -/*description: When set invert the output of PWM1A and PWM1B for this submodule*/ -#define MCPWM_CARRIER1_OUT_INVERT (BIT(12)) -#define MCPWM_CARRIER1_OUT_INVERT_M (BIT(12)) -#define MCPWM_CARRIER1_OUT_INVERT_V 0x1 -#define MCPWM_CARRIER1_OUT_INVERT_S 12 -/* MCPWM_CARRIER1_OSHWTH : R/W ;bitpos:[11:8] ;default: 4'd0 ; */ -/*description: Width of the fist pulse in number of periods of the carrier*/ -#define MCPWM_CARRIER1_OSHWTH 0x0000000F -#define MCPWM_CARRIER1_OSHWTH_M ((MCPWM_CARRIER1_OSHWTH_V)<<(MCPWM_CARRIER1_OSHWTH_S)) -#define MCPWM_CARRIER1_OSHWTH_V 0xF -#define MCPWM_CARRIER1_OSHWTH_S 8 -/* MCPWM_CARRIER1_DUTY : R/W ;bitpos:[7:5] ;default: 3'd0 ; */ -/*description: Carrier duty selection. Duty = PWM_CARRIER1_DUTY / 8*/ -#define MCPWM_CARRIER1_DUTY 0x00000007 -#define MCPWM_CARRIER1_DUTY_M ((MCPWM_CARRIER1_DUTY_V)<<(MCPWM_CARRIER1_DUTY_S)) -#define MCPWM_CARRIER1_DUTY_V 0x7 -#define MCPWM_CARRIER1_DUTY_S 5 -/* MCPWM_CARRIER1_PRESCALE : R/W ;bitpos:[4:1] ;default: 4'd0 ; */ -/*description: PWM carrier1 clock (PC_clk) prescale value. Period of PC_clk - = period of PWM_clk * (PWM_CARRIER1_PRESCALE + 1)*/ -#define MCPWM_CARRIER1_PRESCALE 0x0000000F -#define MCPWM_CARRIER1_PRESCALE_M ((MCPWM_CARRIER1_PRESCALE_V)<<(MCPWM_CARRIER1_PRESCALE_S)) -#define MCPWM_CARRIER1_PRESCALE_V 0xF -#define MCPWM_CARRIER1_PRESCALE_S 1 -/* MCPWM_CARRIER1_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */ -/*description: When set carrier1 function is enabled. When cleared carrier1 is bypassed*/ -#define MCPWM_CARRIER1_EN (BIT(0)) -#define MCPWM_CARRIER1_EN_M (BIT(0)) -#define MCPWM_CARRIER1_EN_V 0x1 +/** MCPWM_CARRIER1_CFG_REG register + * PWM generator 1 carrier enable and configuratoin + */ +#define MCPWM_CARRIER1_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0x9c) +/** MCPWM_CARRIER1_EN : R/W; bitpos: [0]; default: 0; + * When set, carrier1 function is enabled. When cleared, carrier1 is bypassed + */ +#define MCPWM_CARRIER1_EN (BIT(0)) +#define MCPWM_CARRIER1_EN_M (MCPWM_CARRIER1_EN_V << MCPWM_CARRIER1_EN_S) +#define MCPWM_CARRIER1_EN_V 0x00000001U #define MCPWM_CARRIER1_EN_S 0 +/** MCPWM_CARRIER1_PRESCALE : R/W; bitpos: [4:1]; default: 0; + * PWM carrier1 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk * + * (PWM_CARRIER0_PRESCALE + 1) + */ +#define MCPWM_CARRIER1_PRESCALE 0x0000000FU +#define MCPWM_CARRIER1_PRESCALE_M (MCPWM_CARRIER1_PRESCALE_V << MCPWM_CARRIER1_PRESCALE_S) +#define MCPWM_CARRIER1_PRESCALE_V 0x0000000FU +#define MCPWM_CARRIER1_PRESCALE_S 1 +/** MCPWM_CARRIER1_DUTY : R/W; bitpos: [7:5]; default: 0; + * carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8 + */ +#define MCPWM_CARRIER1_DUTY 0x00000007U +#define MCPWM_CARRIER1_DUTY_M (MCPWM_CARRIER1_DUTY_V << MCPWM_CARRIER1_DUTY_S) +#define MCPWM_CARRIER1_DUTY_V 0x00000007U +#define MCPWM_CARRIER1_DUTY_S 5 +/** MCPWM_CARRIER1_OSHTWTH : R/W; bitpos: [11:8]; default: 0; + * width of the first pulse in number of periods of the carrier + */ +#define MCPWM_CARRIER1_OSHTWTH 0x0000000FU +#define MCPWM_CARRIER1_OSHTWTH_M (MCPWM_CARRIER1_OSHTWTH_V << MCPWM_CARRIER1_OSHTWTH_S) +#define MCPWM_CARRIER1_OSHTWTH_V 0x0000000FU +#define MCPWM_CARRIER1_OSHTWTH_S 8 +/** MCPWM_CARRIER1_OUT_INVERT : R/W; bitpos: [12]; default: 0; + * when set, invert the output of PWM1A and PWM1B for this submodule + */ +#define MCPWM_CARRIER1_OUT_INVERT (BIT(12)) +#define MCPWM_CARRIER1_OUT_INVERT_M (MCPWM_CARRIER1_OUT_INVERT_V << MCPWM_CARRIER1_OUT_INVERT_S) +#define MCPWM_CARRIER1_OUT_INVERT_V 0x00000001U +#define MCPWM_CARRIER1_OUT_INVERT_S 12 +/** MCPWM_CARRIER1_IN_INVERT : R/W; bitpos: [13]; default: 0; + * when set, invert the input of PWM1A and PWM1B for this submodule + */ +#define MCPWM_CARRIER1_IN_INVERT (BIT(13)) +#define MCPWM_CARRIER1_IN_INVERT_M (MCPWM_CARRIER1_IN_INVERT_V << MCPWM_CARRIER1_IN_INVERT_S) +#define MCPWM_CARRIER1_IN_INVERT_V 0x00000001U +#define MCPWM_CARRIER1_IN_INVERT_S 13 -#define MCPWM_FH1_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x00a0) -/* MCPWM_FH1_B_OST_U : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ -/*description: One-shot mode action on PWM1B when fault event occurs and timer - is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ -#define MCPWM_FH1_B_OST_U 0x00000003 -#define MCPWM_FH1_B_OST_U_M ((MCPWM_FH1_B_OST_U_V)<<(MCPWM_FH1_B_OST_U_S)) -#define MCPWM_FH1_B_OST_U_V 0x3 -#define MCPWM_FH1_B_OST_U_S 22 -/* MCPWM_FH1_B_OST_D : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ -/*description: One-shot mode action on PWM1B when fault event occurs and timer - is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ -#define MCPWM_FH1_B_OST_D 0x00000003 -#define MCPWM_FH1_B_OST_D_M ((MCPWM_FH1_B_OST_D_V)<<(MCPWM_FH1_B_OST_D_S)) -#define MCPWM_FH1_B_OST_D_V 0x3 -#define MCPWM_FH1_B_OST_D_S 20 -/* MCPWM_FH1_B_CBC_U : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ -/*description: Cycle-by-cycle mode action on PWM1B when fault event occurs and - timer is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ -#define MCPWM_FH1_B_CBC_U 0x00000003 -#define MCPWM_FH1_B_CBC_U_M ((MCPWM_FH1_B_CBC_U_V)<<(MCPWM_FH1_B_CBC_U_S)) -#define MCPWM_FH1_B_CBC_U_V 0x3 -#define MCPWM_FH1_B_CBC_U_S 18 -/* MCPWM_FH1_B_CBC_D : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ -/*description: Cycle-by-cycle mode action on PWM1B when fault event occurs and - timer is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ -#define MCPWM_FH1_B_CBC_D 0x00000003 -#define MCPWM_FH1_B_CBC_D_M ((MCPWM_FH1_B_CBC_D_V)<<(MCPWM_FH1_B_CBC_D_S)) -#define MCPWM_FH1_B_CBC_D_V 0x3 -#define MCPWM_FH1_B_CBC_D_S 16 -/* MCPWM_FH1_A_OST_U : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ -/*description: One-shot mode action on PWM1A when fault event occurs and timer - is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ -#define MCPWM_FH1_A_OST_U 0x00000003 -#define MCPWM_FH1_A_OST_U_M ((MCPWM_FH1_A_OST_U_V)<<(MCPWM_FH1_A_OST_U_S)) -#define MCPWM_FH1_A_OST_U_V 0x3 -#define MCPWM_FH1_A_OST_U_S 14 -/* MCPWM_FH1_A_OST_D : R/W ;bitpos:[13:12] ;default: 2'd0 ; */ -/*description: One-shot mode action on PWM1A when fault event occurs and timer - is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ -#define MCPWM_FH1_A_OST_D 0x00000003 -#define MCPWM_FH1_A_OST_D_M ((MCPWM_FH1_A_OST_D_V)<<(MCPWM_FH1_A_OST_D_S)) -#define MCPWM_FH1_A_OST_D_V 0x3 -#define MCPWM_FH1_A_OST_D_S 12 -/* MCPWM_FH1_A_CBC_U : R/W ;bitpos:[11:10] ;default: 2'd0 ; */ -/*description: Cycle-by-cycle mode action on PWM1A when fault event occurs and - timer is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ -#define MCPWM_FH1_A_CBC_U 0x00000003 -#define MCPWM_FH1_A_CBC_U_M ((MCPWM_FH1_A_CBC_U_V)<<(MCPWM_FH1_A_CBC_U_S)) -#define MCPWM_FH1_A_CBC_U_V 0x3 -#define MCPWM_FH1_A_CBC_U_S 10 -/* MCPWM_FH1_A_CBC_D : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ -/*description: Cycle-by-cycle mode action on PWM1A when fault event occurs and - timer is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ -#define MCPWM_FH1_A_CBC_D 0x00000003 -#define MCPWM_FH1_A_CBC_D_M ((MCPWM_FH1_A_CBC_D_V)<<(MCPWM_FH1_A_CBC_D_S)) -#define MCPWM_FH1_A_CBC_D_V 0x3 -#define MCPWM_FH1_A_CBC_D_S 8 -/* MCPWM_FH1_F0_OST : R/W ;bitpos:[7] ;default: 1'd0 ; */ -/*description: event_f0 will trigger one-shot mode action. 0: disable 1: enable*/ -#define MCPWM_FH1_F0_OST (BIT(7)) -#define MCPWM_FH1_F0_OST_M (BIT(7)) -#define MCPWM_FH1_F0_OST_V 0x1 -#define MCPWM_FH1_F0_OST_S 7 -/* MCPWM_FH1_F1_OST : R/W ;bitpos:[6] ;default: 1'd0 ; */ -/*description: event_f1 will trigger one-shot mode action. 0: disable 1: enable*/ -#define MCPWM_FH1_F1_OST (BIT(6)) -#define MCPWM_FH1_F1_OST_M (BIT(6)) -#define MCPWM_FH1_F1_OST_V 0x1 -#define MCPWM_FH1_F1_OST_S 6 -/* MCPWM_FH1_F2_OST : R/W ;bitpos:[5] ;default: 1'd0 ; */ -/*description: event_f2 will trigger one-shot mode action. 0: disable 1: enable*/ -#define MCPWM_FH1_F2_OST (BIT(5)) -#define MCPWM_FH1_F2_OST_M (BIT(5)) -#define MCPWM_FH1_F2_OST_V 0x1 -#define MCPWM_FH1_F2_OST_S 5 -/* MCPWM_FH1_SW_OST : R/W ;bitpos:[4] ;default: 1'd0 ; */ -/*description: Enable register for software force one-shot mode action. 0: disable 1: enable*/ -#define MCPWM_FH1_SW_OST (BIT(4)) -#define MCPWM_FH1_SW_OST_M (BIT(4)) -#define MCPWM_FH1_SW_OST_V 0x1 -#define MCPWM_FH1_SW_OST_S 4 -/* MCPWM_FH1_F0_CBC : R/W ;bitpos:[3] ;default: 1'd0 ; */ -/*description: event_f0 will trigger cycle-by-cycle mode action. 0: disable 1: enable*/ -#define MCPWM_FH1_F0_CBC (BIT(3)) -#define MCPWM_FH1_F0_CBC_M (BIT(3)) -#define MCPWM_FH1_F0_CBC_V 0x1 -#define MCPWM_FH1_F0_CBC_S 3 -/* MCPWM_FH1_F1_CBC : R/W ;bitpos:[2] ;default: 1'd0 ; */ -/*description: event_f1 will trigger cycle-by-cycle mode action. 0: disable 1: enable*/ -#define MCPWM_FH1_F1_CBC (BIT(2)) -#define MCPWM_FH1_F1_CBC_M (BIT(2)) -#define MCPWM_FH1_F1_CBC_V 0x1 -#define MCPWM_FH1_F1_CBC_S 2 -/* MCPWM_FH1_F2_CBC : R/W ;bitpos:[1] ;default: 1'd0 ; */ -/*description: event_f2 will trigger cycle-by-cycle mode action. 0: disable 1: enable*/ -#define MCPWM_FH1_F2_CBC (BIT(1)) -#define MCPWM_FH1_F2_CBC_M (BIT(1)) -#define MCPWM_FH1_F2_CBC_V 0x1 -#define MCPWM_FH1_F2_CBC_S 1 -/* MCPWM_FH1_SW_CBC : R/W ;bitpos:[0] ;default: 1'd0 ; */ -/*description: Enable register for software force cycle-by-cycle mode action. - 0: disable 1: enable*/ -#define MCPWM_FH1_SW_CBC (BIT(0)) -#define MCPWM_FH1_SW_CBC_M (BIT(0)) -#define MCPWM_FH1_SW_CBC_V 0x1 +/** MCPWM_FH1_CFG0_REG register + * Actions on PWM1A and PWM1B trip events + */ +#define MCPWM_FH1_CFG0_REG(i) (DR_REG_MCPWM_BASE(i) + 0xa0) +/** MCPWM_FH1_SW_CBC : R/W; bitpos: [0]; default: 0; + * Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable + */ +#define MCPWM_FH1_SW_CBC (BIT(0)) +#define MCPWM_FH1_SW_CBC_M (MCPWM_FH1_SW_CBC_V << MCPWM_FH1_SW_CBC_S) +#define MCPWM_FH1_SW_CBC_V 0x00000001U #define MCPWM_FH1_SW_CBC_S 0 +/** MCPWM_FH1_F2_CBC : R/W; bitpos: [1]; default: 0; + * fault_event2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + */ +#define MCPWM_FH1_F2_CBC (BIT(1)) +#define MCPWM_FH1_F2_CBC_M (MCPWM_FH1_F2_CBC_V << MCPWM_FH1_F2_CBC_S) +#define MCPWM_FH1_F2_CBC_V 0x00000001U +#define MCPWM_FH1_F2_CBC_S 1 +/** MCPWM_FH1_F1_CBC : R/W; bitpos: [2]; default: 0; + * fault_event1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + */ +#define MCPWM_FH1_F1_CBC (BIT(2)) +#define MCPWM_FH1_F1_CBC_M (MCPWM_FH1_F1_CBC_V << MCPWM_FH1_F1_CBC_S) +#define MCPWM_FH1_F1_CBC_V 0x00000001U +#define MCPWM_FH1_F1_CBC_S 2 +/** MCPWM_FH1_F0_CBC : R/W; bitpos: [3]; default: 0; + * fault_event0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + */ +#define MCPWM_FH1_F0_CBC (BIT(3)) +#define MCPWM_FH1_F0_CBC_M (MCPWM_FH1_F0_CBC_V << MCPWM_FH1_F0_CBC_S) +#define MCPWM_FH1_F0_CBC_V 0x00000001U +#define MCPWM_FH1_F0_CBC_S 3 +/** MCPWM_FH1_SW_OST : R/W; bitpos: [4]; default: 0; + * Enable register for software force one-shot mode action. 0: disable, 1: enable + */ +#define MCPWM_FH1_SW_OST (BIT(4)) +#define MCPWM_FH1_SW_OST_M (MCPWM_FH1_SW_OST_V << MCPWM_FH1_SW_OST_S) +#define MCPWM_FH1_SW_OST_V 0x00000001U +#define MCPWM_FH1_SW_OST_S 4 +/** MCPWM_FH1_F2_OST : R/W; bitpos: [5]; default: 0; + * fault_event2 will trigger one-shot mode action. 0: disable, 1: enable + */ +#define MCPWM_FH1_F2_OST (BIT(5)) +#define MCPWM_FH1_F2_OST_M (MCPWM_FH1_F2_OST_V << MCPWM_FH1_F2_OST_S) +#define MCPWM_FH1_F2_OST_V 0x00000001U +#define MCPWM_FH1_F2_OST_S 5 +/** MCPWM_FH1_F1_OST : R/W; bitpos: [6]; default: 0; + * fault_event1 will trigger one-shot mode action. 0: disable, 1: enable + */ +#define MCPWM_FH1_F1_OST (BIT(6)) +#define MCPWM_FH1_F1_OST_M (MCPWM_FH1_F1_OST_V << MCPWM_FH1_F1_OST_S) +#define MCPWM_FH1_F1_OST_V 0x00000001U +#define MCPWM_FH1_F1_OST_S 6 +/** MCPWM_FH1_F0_OST : R/W; bitpos: [7]; default: 0; + * fault_event0 will trigger one-shot mode action. 0: disable, 1: enable + */ +#define MCPWM_FH1_F0_OST (BIT(7)) +#define MCPWM_FH1_F0_OST_M (MCPWM_FH1_F0_OST_V << MCPWM_FH1_F0_OST_S) +#define MCPWM_FH1_F0_OST_V 0x00000001U +#define MCPWM_FH1_F0_OST_S 7 +/** MCPWM_FH1_A_CBC_D : R/W; bitpos: [9:8]; default: 0; + * Cycle-by-cycle mode action on PWM1A when fault event occurs and timer is + * decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_FH1_A_CBC_D 0x00000003U +#define MCPWM_FH1_A_CBC_D_M (MCPWM_FH1_A_CBC_D_V << MCPWM_FH1_A_CBC_D_S) +#define MCPWM_FH1_A_CBC_D_V 0x00000003U +#define MCPWM_FH1_A_CBC_D_S 8 +/** MCPWM_FH1_A_CBC_U : R/W; bitpos: [11:10]; default: 0; + * Cycle-by-cycle mode action on PWM1A when fault event occurs and timer is + * increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_FH1_A_CBC_U 0x00000003U +#define MCPWM_FH1_A_CBC_U_M (MCPWM_FH1_A_CBC_U_V << MCPWM_FH1_A_CBC_U_S) +#define MCPWM_FH1_A_CBC_U_V 0x00000003U +#define MCPWM_FH1_A_CBC_U_S 10 +/** MCPWM_FH1_A_OST_D : R/W; bitpos: [13:12]; default: 0; + * One-shot mode action on PWM1A when fault event occurs and timer is decreasing. 0: + * do nothing,1: force low, 2: force high, 3: toggle + */ +#define MCPWM_FH1_A_OST_D 0x00000003U +#define MCPWM_FH1_A_OST_D_M (MCPWM_FH1_A_OST_D_V << MCPWM_FH1_A_OST_D_S) +#define MCPWM_FH1_A_OST_D_V 0x00000003U +#define MCPWM_FH1_A_OST_D_S 12 +/** MCPWM_FH1_A_OST_U : R/W; bitpos: [15:14]; default: 0; + * One-shot mode action on PWM1A when fault event occurs and timer is increasing. 0: + * do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_FH1_A_OST_U 0x00000003U +#define MCPWM_FH1_A_OST_U_M (MCPWM_FH1_A_OST_U_V << MCPWM_FH1_A_OST_U_S) +#define MCPWM_FH1_A_OST_U_V 0x00000003U +#define MCPWM_FH1_A_OST_U_S 14 +/** MCPWM_FH1_B_CBC_D : R/W; bitpos: [17:16]; default: 0; + * Cycle-by-cycle mode action on PWM1B when fault event occurs and timer is + * decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_FH1_B_CBC_D 0x00000003U +#define MCPWM_FH1_B_CBC_D_M (MCPWM_FH1_B_CBC_D_V << MCPWM_FH1_B_CBC_D_S) +#define MCPWM_FH1_B_CBC_D_V 0x00000003U +#define MCPWM_FH1_B_CBC_D_S 16 +/** MCPWM_FH1_B_CBC_U : R/W; bitpos: [19:18]; default: 0; + * Cycle-by-cycle mode action on PWM1B when fault event occurs and timer is + * increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_FH1_B_CBC_U 0x00000003U +#define MCPWM_FH1_B_CBC_U_M (MCPWM_FH1_B_CBC_U_V << MCPWM_FH1_B_CBC_U_S) +#define MCPWM_FH1_B_CBC_U_V 0x00000003U +#define MCPWM_FH1_B_CBC_U_S 18 +/** MCPWM_FH1_B_OST_D : R/W; bitpos: [21:20]; default: 0; + * One-shot mode action on PWM1B when fault event occurs and timer is decreasing. 0: + * do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_FH1_B_OST_D 0x00000003U +#define MCPWM_FH1_B_OST_D_M (MCPWM_FH1_B_OST_D_V << MCPWM_FH1_B_OST_D_S) +#define MCPWM_FH1_B_OST_D_V 0x00000003U +#define MCPWM_FH1_B_OST_D_S 20 +/** MCPWM_FH1_B_OST_U : R/W; bitpos: [23:22]; default: 0; + * One-shot mode action on PWM1B when fault event occurs and timer is increasing. 0: + * do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_FH1_B_OST_U 0x00000003U +#define MCPWM_FH1_B_OST_U_M (MCPWM_FH1_B_OST_U_V << MCPWM_FH1_B_OST_U_S) +#define MCPWM_FH1_B_OST_U_V 0x00000003U +#define MCPWM_FH1_B_OST_U_S 22 -#define MCPWM_FH1_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0x00a4) -/* MCPWM_FH1_FORCE_OST : R/W ;bitpos:[4] ;default: 1'd0 ; */ -/*description: A toggle (software negation of value of this bit) triggers a - one-shot mode action*/ -#define MCPWM_FH1_FORCE_OST (BIT(4)) -#define MCPWM_FH1_FORCE_OST_M (BIT(4)) -#define MCPWM_FH1_FORCE_OST_V 0x1 -#define MCPWM_FH1_FORCE_OST_S 4 -/* MCPWM_FH1_FORCE_CBC : R/W ;bitpos:[3] ;default: 1'd0 ; */ -/*description: A toggle triggers a cycle-by-cycle mode action*/ -#define MCPWM_FH1_FORCE_CBC (BIT(3)) -#define MCPWM_FH1_FORCE_CBC_M (BIT(3)) -#define MCPWM_FH1_FORCE_CBC_V 0x1 -#define MCPWM_FH1_FORCE_CBC_S 3 -/* MCPWM_FH1_CBCPULSE : R/W ;bitpos:[2:1] ;default: 2'd0 ; */ -/*description: The cycle-by-cycle mode action refresh moment selection. Bit0: TEZ bit1:TEP*/ -#define MCPWM_FH1_CBCPULSE 0x00000003 -#define MCPWM_FH1_CBCPULSE_M ((MCPWM_FH1_CBCPULSE_V)<<(MCPWM_FH1_CBCPULSE_S)) -#define MCPWM_FH1_CBCPULSE_V 0x3 -#define MCPWM_FH1_CBCPULSE_S 1 -/* MCPWM_FH1_CLR_OST : R/W ;bitpos:[0] ;default: 1'd0 ; */ -/*description: A toggle will clear on going one-shot mode action*/ -#define MCPWM_FH1_CLR_OST (BIT(0)) -#define MCPWM_FH1_CLR_OST_M (BIT(0)) -#define MCPWM_FH1_CLR_OST_V 0x1 +/** MCPWM_FH1_CFG1_REG register + * Software triggers for fault handler actions + */ +#define MCPWM_FH1_CFG1_REG(i) (DR_REG_MCPWM_BASE(i) + 0xa4) +/** MCPWM_FH1_CLR_OST : R/W; bitpos: [0]; default: 0; + * a rising edge will clear on going one-shot mode action + */ +#define MCPWM_FH1_CLR_OST (BIT(0)) +#define MCPWM_FH1_CLR_OST_M (MCPWM_FH1_CLR_OST_V << MCPWM_FH1_CLR_OST_S) +#define MCPWM_FH1_CLR_OST_V 0x00000001U #define MCPWM_FH1_CLR_OST_S 0 +/** MCPWM_FH1_CBCPULSE : R/W; bitpos: [2:1]; default: 0; + * cycle-by-cycle mode action refresh moment selection. When bit0 is set to 1: TEZ, + * when bit1 is set to 1:TEP + */ +#define MCPWM_FH1_CBCPULSE 0x00000003U +#define MCPWM_FH1_CBCPULSE_M (MCPWM_FH1_CBCPULSE_V << MCPWM_FH1_CBCPULSE_S) +#define MCPWM_FH1_CBCPULSE_V 0x00000003U +#define MCPWM_FH1_CBCPULSE_S 1 +/** MCPWM_FH1_FORCE_CBC : R/W; bitpos: [3]; default: 0; + * a toggle trigger a cycle-by-cycle mode action + */ +#define MCPWM_FH1_FORCE_CBC (BIT(3)) +#define MCPWM_FH1_FORCE_CBC_M (MCPWM_FH1_FORCE_CBC_V << MCPWM_FH1_FORCE_CBC_S) +#define MCPWM_FH1_FORCE_CBC_V 0x00000001U +#define MCPWM_FH1_FORCE_CBC_S 3 +/** MCPWM_FH1_FORCE_OST : R/W; bitpos: [4]; default: 0; + * a toggle (software negate its value) triggers a one-shot mode action + */ +#define MCPWM_FH1_FORCE_OST (BIT(4)) +#define MCPWM_FH1_FORCE_OST_M (MCPWM_FH1_FORCE_OST_V << MCPWM_FH1_FORCE_OST_S) +#define MCPWM_FH1_FORCE_OST_V 0x00000001U +#define MCPWM_FH1_FORCE_OST_S 4 -#define MCPWM_FH1_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x00a8) -/* MCPWM_FH1_OST_ON : RO ;bitpos:[1] ;default: 1'd0 ; */ -/*description: Set and reset by hardware. If set an one-shot mode action is on going*/ -#define MCPWM_FH1_OST_ON (BIT(1)) -#define MCPWM_FH1_OST_ON_M (BIT(1)) -#define MCPWM_FH1_OST_ON_V 0x1 -#define MCPWM_FH1_OST_ON_S 1 -/* MCPWM_FH1_CBC_ON : RO ;bitpos:[0] ;default: 1'd0 ; */ -/*description: Set and reset by hardware. If set an cycle-by-cycle mode action is on going*/ -#define MCPWM_FH1_CBC_ON (BIT(0)) -#define MCPWM_FH1_CBC_ON_M (BIT(0)) -#define MCPWM_FH1_CBC_ON_V 0x1 +/** MCPWM_FH1_STATUS_REG register + * Status of fault events. + */ +#define MCPWM_FH1_STATUS_REG(i) (DR_REG_MCPWM_BASE(i) + 0xa8) +/** MCPWM_FH1_CBC_ON : RO; bitpos: [0]; default: 0; + * Set and reset by hardware. If set, a cycle-by-cycle mode action is on going + */ +#define MCPWM_FH1_CBC_ON (BIT(0)) +#define MCPWM_FH1_CBC_ON_M (MCPWM_FH1_CBC_ON_V << MCPWM_FH1_CBC_ON_S) +#define MCPWM_FH1_CBC_ON_V 0x00000001U #define MCPWM_FH1_CBC_ON_S 0 +/** MCPWM_FH1_OST_ON : RO; bitpos: [1]; default: 0; + * Set and reset by hardware. If set, an one-shot mode action is on going + */ +#define MCPWM_FH1_OST_ON (BIT(1)) +#define MCPWM_FH1_OST_ON_M (MCPWM_FH1_OST_ON_V << MCPWM_FH1_OST_ON_S) +#define MCPWM_FH1_OST_ON_V 0x00000001U +#define MCPWM_FH1_OST_ON_S 1 -#define MCPWM_GEN2_STMP_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x00ac) -/* MCPWM_GEN2_B_SHDW_FULL : RO ;bitpos:[9] ;default: 1'd0 ; */ -/*description: Set and reset by hardware. If set PWM generator 2 time stamp - B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared B's active reg has been updated with shadow reg latest value*/ -#define MCPWM_GEN2_B_SHDW_FULL (BIT(9)) -#define MCPWM_GEN2_B_SHDW_FULL_M (BIT(9)) -#define MCPWM_GEN2_B_SHDW_FULL_V 0x1 -#define MCPWM_GEN2_B_SHDW_FULL_S 9 -/* MCPWM_GEN2_A_SHDW_FULL : RO ;bitpos:[8] ;default: 1'd0 ; */ -/*description: Set and reset by hardware. If set PWM generator 2 time stamp - A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared A's active reg has been updated with shadow reg latest value*/ -#define MCPWM_GEN2_A_SHDW_FULL (BIT(8)) -#define MCPWM_GEN2_A_SHDW_FULL_M (BIT(8)) -#define MCPWM_GEN2_A_SHDW_FULL_V 0x1 -#define MCPWM_GEN2_A_SHDW_FULL_S 8 -/* MCPWM_GEN2_B_UPMETHOD : R/W ;bitpos:[7:4] ;default: 4'd0 ; */ -/*description: Update method for PWM generator 2 time stamp B's active reg. - 0: immediate bit0: TEZ bit1: TEP bit2: sync bit3: disable update*/ -#define MCPWM_GEN2_B_UPMETHOD 0x0000000F -#define MCPWM_GEN2_B_UPMETHOD_M ((MCPWM_GEN2_B_UPMETHOD_V)<<(MCPWM_GEN2_B_UPMETHOD_S)) -#define MCPWM_GEN2_B_UPMETHOD_V 0xF -#define MCPWM_GEN2_B_UPMETHOD_S 4 -/* MCPWM_GEN2_A_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: Update method for PWM generator 2 time stamp A's active reg. - 0: immediate bit0: TEZ bit1: TEP bit2: sync bit3: disable update*/ -#define MCPWM_GEN2_A_UPMETHOD 0x0000000F -#define MCPWM_GEN2_A_UPMETHOD_M ((MCPWM_GEN2_A_UPMETHOD_V)<<(MCPWM_GEN2_A_UPMETHOD_S)) -#define MCPWM_GEN2_A_UPMETHOD_V 0xF +/** MCPWM_GEN2_STMP_CFG_REG register + * Transfer status and update method for time stamp registers A and B + */ +#define MCPWM_GEN2_STMP_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0xac) +/** MCPWM_GEN2_A_UPMETHOD : R/W; bitpos: [3:0]; default: 0; + * Update method for PWM generator 2 time stamp A's active register. When all bits are + * set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when + * bit2 is set to 1: sync, when bit3 is set to 1: disable the update. + */ +#define MCPWM_GEN2_A_UPMETHOD 0x0000000FU +#define MCPWM_GEN2_A_UPMETHOD_M (MCPWM_GEN2_A_UPMETHOD_V << MCPWM_GEN2_A_UPMETHOD_S) +#define MCPWM_GEN2_A_UPMETHOD_V 0x0000000FU #define MCPWM_GEN2_A_UPMETHOD_S 0 +/** MCPWM_GEN2_B_UPMETHOD : R/W; bitpos: [7:4]; default: 0; + * Update method for PWM generator 2 time stamp B's active register. When all bits are + * set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when + * bit2 is set to 1: sync, when bit3 is set to 1: disable the update. + */ +#define MCPWM_GEN2_B_UPMETHOD 0x0000000FU +#define MCPWM_GEN2_B_UPMETHOD_M (MCPWM_GEN2_B_UPMETHOD_V << MCPWM_GEN2_B_UPMETHOD_S) +#define MCPWM_GEN2_B_UPMETHOD_V 0x0000000FU +#define MCPWM_GEN2_B_UPMETHOD_S 4 +/** MCPWM_GEN2_A_SHDW_FULL : R/W/WTC/SC; bitpos: [8]; default: 0; + * Set and reset by hardware. If set, PWM generator 2 time stamp A's shadow reg is + * filled and waiting to be transferred to A's active reg. If cleared, A's active reg + * has been updated with shadow register latest value + */ +#define MCPWM_GEN2_A_SHDW_FULL (BIT(8)) +#define MCPWM_GEN2_A_SHDW_FULL_M (MCPWM_GEN2_A_SHDW_FULL_V << MCPWM_GEN2_A_SHDW_FULL_S) +#define MCPWM_GEN2_A_SHDW_FULL_V 0x00000001U +#define MCPWM_GEN2_A_SHDW_FULL_S 8 +/** MCPWM_GEN2_B_SHDW_FULL : R/W/WTC/SC; bitpos: [9]; default: 0; + * Set and reset by hardware. If set, PWM generator 2 time stamp B's shadow reg is + * filled and waiting to be transferred to B's active reg. If cleared, B's active reg + * has been updated with shadow register latest value + */ +#define MCPWM_GEN2_B_SHDW_FULL (BIT(9)) +#define MCPWM_GEN2_B_SHDW_FULL_M (MCPWM_GEN2_B_SHDW_FULL_V << MCPWM_GEN2_B_SHDW_FULL_S) +#define MCPWM_GEN2_B_SHDW_FULL_V 0x00000001U +#define MCPWM_GEN2_B_SHDW_FULL_S 9 -#define MCPWM_GEN2_TSTMP_A_REG(i) (REG_MCPWM_BASE(i) + 0x00b0) -/* MCPWM_GEN2_A : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ -/*description: PWM generator 2 time stamp A's shadow reg*/ -#define MCPWM_GEN2_A 0x0000FFFF -#define MCPWM_GEN2_A_M ((MCPWM_GEN2_A_V)<<(MCPWM_GEN2_A_S)) -#define MCPWM_GEN2_A_V 0xFFFF +/** MCPWM_GEN2_TSTMP_A_REG register + * PWM generator 2 shadow register for timer stamp A. + */ +#define MCPWM_GEN2_TSTMP_A_REG(i) (DR_REG_MCPWM_BASE(i) + 0xb0) +/** MCPWM_GEN2_A : R/W; bitpos: [15:0]; default: 0; + * PWM generator 2 time stamp A's shadow register + */ +#define MCPWM_GEN2_A 0x0000FFFFU +#define MCPWM_GEN2_A_M (MCPWM_GEN2_A_V << MCPWM_GEN2_A_S) +#define MCPWM_GEN2_A_V 0x0000FFFFU #define MCPWM_GEN2_A_S 0 -#define MCPWM_GEN2_TSTMP_B_REG(i) (REG_MCPWM_BASE(i) + 0x00b4) -/* MCPWM_GEN2_B : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ -/*description: PWM generator 2 time stamp B's shadow reg*/ -#define MCPWM_GEN2_B 0x0000FFFF -#define MCPWM_GEN2_B_M ((MCPWM_GEN2_B_V)<<(MCPWM_GEN2_B_S)) -#define MCPWM_GEN2_B_V 0xFFFF +/** MCPWM_GEN2_TSTMP_B_REG register + * PWM generator 2 shadow register for timer stamp A. + */ +#define MCPWM_GEN2_TSTMP_B_REG(i) (DR_REG_MCPWM_BASE(i) + 0xb4) +/** MCPWM_GEN2_B : R/W; bitpos: [15:0]; default: 0; + * PWM generator 2 time stamp B's shadow register + */ +#define MCPWM_GEN2_B 0x0000FFFFU +#define MCPWM_GEN2_B_M (MCPWM_GEN2_B_V << MCPWM_GEN2_B_S) +#define MCPWM_GEN2_B_V 0x0000FFFFU #define MCPWM_GEN2_B_S 0 -#define MCPWM_GEN2_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x00b8) -/* MCPWM_GEN2_T1_SEL : R/W ;bitpos:[9:7] ;default: 3'd0 ; */ -/*description: Source selection for PWM generate2 event_t1 take effect immediately - 0: fault_event0 1: fault_event1 2: fault_event2 3: sync_taken 4: none*/ -#define MCPWM_GEN2_T1_SEL 0x00000007 -#define MCPWM_GEN2_T1_SEL_M ((MCPWM_GEN2_T1_SEL_V)<<(MCPWM_GEN2_T1_SEL_S)) -#define MCPWM_GEN2_T1_SEL_V 0x7 -#define MCPWM_GEN2_T1_SEL_S 7 -/* MCPWM_GEN2_T0_SEL : R/W ;bitpos:[6:4] ;default: 3'd0 ; */ -/*description: Source selection for PWM generate2 event_t0 take effect immediately - 0: fault_event0 1: fault_event1 2: fault_event2 3: sync_taken 4: none*/ -#define MCPWM_GEN2_T0_SEL 0x00000007 -#define MCPWM_GEN2_T0_SEL_M ((MCPWM_GEN2_T0_SEL_V)<<(MCPWM_GEN2_T0_SEL_S)) -#define MCPWM_GEN2_T0_SEL_V 0x7 -#define MCPWM_GEN2_T0_SEL_S 4 -/* MCPWM_GEN2_CFG_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: Update method for PWM generate2's active reg of configuration. - 0: immediate bit0: TEZ bit1: TEP bit2: sync. bit3: disable update*/ -#define MCPWM_GEN2_CFG_UPMETHOD 0x0000000F -#define MCPWM_GEN2_CFG_UPMETHOD_M ((MCPWM_GEN2_CFG_UPMETHOD_V)<<(MCPWM_GEN2_CFG_UPMETHOD_S)) -#define MCPWM_GEN2_CFG_UPMETHOD_V 0xF +/** MCPWM_GEN2_CFG0_REG register + * PWM generator 2 event T0 and T1 handling + */ +#define MCPWM_GEN2_CFG0_REG(i) (DR_REG_MCPWM_BASE(i) + 0xb8) +/** MCPWM_GEN2_CFG_UPMETHOD : R/W; bitpos: [3:0]; default: 0; + * Update method for PWM generator 2's active register of configuration. 0: + * immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1:sync;when bit3 is + * set to 1:disable the update. + */ +#define MCPWM_GEN2_CFG_UPMETHOD 0x0000000FU +#define MCPWM_GEN2_CFG_UPMETHOD_M (MCPWM_GEN2_CFG_UPMETHOD_V << MCPWM_GEN2_CFG_UPMETHOD_S) +#define MCPWM_GEN2_CFG_UPMETHOD_V 0x0000000FU #define MCPWM_GEN2_CFG_UPMETHOD_S 0 +/** MCPWM_GEN2_T0_SEL : R/W; bitpos: [6:4]; default: 0; + * Source selection for PWM generator 2 event_t0, take effect immediately, 0: + * fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none + */ +#define MCPWM_GEN2_T0_SEL 0x00000007U +#define MCPWM_GEN2_T0_SEL_M (MCPWM_GEN2_T0_SEL_V << MCPWM_GEN2_T0_SEL_S) +#define MCPWM_GEN2_T0_SEL_V 0x00000007U +#define MCPWM_GEN2_T0_SEL_S 4 +/** MCPWM_GEN2_T1_SEL : R/W; bitpos: [9:7]; default: 0; + * Source selection for PWM generator 2 event_t1, take effect immediately, 0: + * fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none + */ +#define MCPWM_GEN2_T1_SEL 0x00000007U +#define MCPWM_GEN2_T1_SEL_M (MCPWM_GEN2_T1_SEL_V << MCPWM_GEN2_T1_SEL_S) +#define MCPWM_GEN2_T1_SEL_V 0x00000007U +#define MCPWM_GEN2_T1_SEL_S 7 -#define MCPWM_GEN2_FORCE_REG(i) (REG_MCPWM_BASE(i) + 0x00bc) -/* MCPWM_GEN2_B_NCIFORCE_MODE : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ -/*description: Non-continuous immediate software force mode for PWM2B 0: disabled - 1: low 2: high 3: disabled*/ -#define MCPWM_GEN2_B_NCIFORCE_MODE 0x00000003 -#define MCPWM_GEN2_B_NCIFORCE_MODE_M ((MCPWM_GEN2_B_NCIFORCE_MODE_V)<<(MCPWM_GEN2_B_NCIFORCE_MODE_S)) -#define MCPWM_GEN2_B_NCIFORCE_MODE_V 0x3 -#define MCPWM_GEN2_B_NCIFORCE_MODE_S 14 -/* MCPWM_GEN2_B_NCIFORCE : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: Non-continuous immediate software force trigger for PWM2B a - toggle will trigger a force event*/ -#define MCPWM_GEN2_B_NCIFORCE (BIT(13)) -#define MCPWM_GEN2_B_NCIFORCE_M (BIT(13)) -#define MCPWM_GEN2_B_NCIFORCE_V 0x1 -#define MCPWM_GEN2_B_NCIFORCE_S 13 -/* MCPWM_GEN2_A_NCIFORCE_MODE : R/W ;bitpos:[12:11] ;default: 2'd0 ; */ -/*description: Non-continuous immediate software force mode for PWM2A 0: disabled - 1: low 2: high 3: disabled*/ -#define MCPWM_GEN2_A_NCIFORCE_MODE 0x00000003 -#define MCPWM_GEN2_A_NCIFORCE_MODE_M ((MCPWM_GEN2_A_NCIFORCE_MODE_V)<<(MCPWM_GEN2_A_NCIFORCE_MODE_S)) -#define MCPWM_GEN2_A_NCIFORCE_MODE_V 0x3 -#define MCPWM_GEN2_A_NCIFORCE_MODE_S 11 -/* MCPWM_GEN2_A_NCIFORCE : R/W ;bitpos:[10] ;default: 1'd0 ; */ -/*description: Non-continuous immediate software force trigger for PWM2A a - toggle will trigger a force event*/ -#define MCPWM_GEN2_A_NCIFORCE (BIT(10)) -#define MCPWM_GEN2_A_NCIFORCE_M (BIT(10)) -#define MCPWM_GEN2_A_NCIFORCE_V 0x1 -#define MCPWM_GEN2_A_NCIFORCE_S 10 -/* MCPWM_GEN2_B_CNTUFORCE_MODE : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ -/*description: Continuous software force mode for PWM2B. 0: disabled 1: low - 2: high 3: disabled*/ -#define MCPWM_GEN2_B_CNTUFORCE_MODE 0x00000003 -#define MCPWM_GEN2_B_CNTUFORCE_MODE_M ((MCPWM_GEN2_B_CNTUFORCE_MODE_V)<<(MCPWM_GEN2_B_CNTUFORCE_MODE_S)) -#define MCPWM_GEN2_B_CNTUFORCE_MODE_V 0x3 -#define MCPWM_GEN2_B_CNTUFORCE_MODE_S 8 -/* MCPWM_GEN2_A_CNTUFORCE_MODE : R/W ;bitpos:[7:6] ;default: 2'd0 ; */ -/*description: Continuous software force mode for PWM2A. 0: disabled 1: low - 2: high 3: disabled*/ -#define MCPWM_GEN2_A_CNTUFORCE_MODE 0x00000003 -#define MCPWM_GEN2_A_CNTUFORCE_MODE_M ((MCPWM_GEN2_A_CNTUFORCE_MODE_V)<<(MCPWM_GEN2_A_CNTUFORCE_MODE_S)) -#define MCPWM_GEN2_A_CNTUFORCE_MODE_V 0x3 -#define MCPWM_GEN2_A_CNTUFORCE_MODE_S 6 -/* MCPWM_GEN2_CNTUFORCE_UPMETHOD : R/W ;bitpos:[5:0] ;default: 6'h20 ; */ -/*description: Update method for continuous software force of PWM generator2. - 0: immediate bit0: TEZ bit1: TEP bit2: TEA bit3: TEB bit4: sync bit5: disable update. (TEA/B here and below means an event generated when timer value equals A/B register)*/ -#define MCPWM_GEN2_CNTUFORCE_UPMETHOD 0x0000003F -#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_M ((MCPWM_GEN2_CNTUFORCE_UPMETHOD_V)<<(MCPWM_GEN2_CNTUFORCE_UPMETHOD_S)) -#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_V 0x3F +/** MCPWM_GEN2_FORCE_REG register + * Permissives to force PWM2A and PWM2B outputs by software + */ +#define MCPWM_GEN2_FORCE_REG(i) (DR_REG_MCPWM_BASE(i) + 0xbc) +/** MCPWM_GEN2_CNTUFORCE_UPMETHOD : R/W; bitpos: [5:0]; default: 32; + * Updating method for continuous software force of PWM generator 2. When all bits are + * set to 0: immediately, when bit0 is set to 1: TEZ,when bit1 is set to 1: TEP, when + * bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync, + * when bit5 is set to 1: disable update. (TEA/B here and below means an event + * generated when the timer's value equals to that of register A/B.) + */ +#define MCPWM_GEN2_CNTUFORCE_UPMETHOD 0x0000003FU +#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_M (MCPWM_GEN2_CNTUFORCE_UPMETHOD_V << MCPWM_GEN2_CNTUFORCE_UPMETHOD_S) +#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_V 0x0000003FU #define MCPWM_GEN2_CNTUFORCE_UPMETHOD_S 0 +/** MCPWM_GEN2_A_CNTUFORCE_MODE : R/W; bitpos: [7:6]; default: 0; + * Continuous software force mode for PWM2A. 0: disabled, 1: low, 2: high, 3: disabled + */ +#define MCPWM_GEN2_A_CNTUFORCE_MODE 0x00000003U +#define MCPWM_GEN2_A_CNTUFORCE_MODE_M (MCPWM_GEN2_A_CNTUFORCE_MODE_V << MCPWM_GEN2_A_CNTUFORCE_MODE_S) +#define MCPWM_GEN2_A_CNTUFORCE_MODE_V 0x00000003U +#define MCPWM_GEN2_A_CNTUFORCE_MODE_S 6 +/** MCPWM_GEN2_B_CNTUFORCE_MODE : R/W; bitpos: [9:8]; default: 0; + * Continuous software force mode for PWM2B. 0: disabled, 1: low, 2: high, 3: disabled + */ +#define MCPWM_GEN2_B_CNTUFORCE_MODE 0x00000003U +#define MCPWM_GEN2_B_CNTUFORCE_MODE_M (MCPWM_GEN2_B_CNTUFORCE_MODE_V << MCPWM_GEN2_B_CNTUFORCE_MODE_S) +#define MCPWM_GEN2_B_CNTUFORCE_MODE_V 0x00000003U +#define MCPWM_GEN2_B_CNTUFORCE_MODE_S 8 +/** MCPWM_GEN2_A_NCIFORCE : R/W; bitpos: [10]; default: 0; + * Trigger of non-continuous immediate software-force event for PWM2A, a toggle will + * trigger a force event. + */ +#define MCPWM_GEN2_A_NCIFORCE (BIT(10)) +#define MCPWM_GEN2_A_NCIFORCE_M (MCPWM_GEN2_A_NCIFORCE_V << MCPWM_GEN2_A_NCIFORCE_S) +#define MCPWM_GEN2_A_NCIFORCE_V 0x00000001U +#define MCPWM_GEN2_A_NCIFORCE_S 10 +/** MCPWM_GEN2_A_NCIFORCE_MODE : R/W; bitpos: [12:11]; default: 0; + * non-continuous immediate software force mode for PWM2A, 0: disabled, 1: low, 2: + * high, 3: disabled + */ +#define MCPWM_GEN2_A_NCIFORCE_MODE 0x00000003U +#define MCPWM_GEN2_A_NCIFORCE_MODE_M (MCPWM_GEN2_A_NCIFORCE_MODE_V << MCPWM_GEN2_A_NCIFORCE_MODE_S) +#define MCPWM_GEN2_A_NCIFORCE_MODE_V 0x00000003U +#define MCPWM_GEN2_A_NCIFORCE_MODE_S 11 +/** MCPWM_GEN2_B_NCIFORCE : R/W; bitpos: [13]; default: 0; + * Trigger of non-continuous immediate software-force event for PWM2B, a toggle will + * trigger a force event. + */ +#define MCPWM_GEN2_B_NCIFORCE (BIT(13)) +#define MCPWM_GEN2_B_NCIFORCE_M (MCPWM_GEN2_B_NCIFORCE_V << MCPWM_GEN2_B_NCIFORCE_S) +#define MCPWM_GEN2_B_NCIFORCE_V 0x00000001U +#define MCPWM_GEN2_B_NCIFORCE_S 13 +/** MCPWM_GEN2_B_NCIFORCE_MODE : R/W; bitpos: [15:14]; default: 0; + * non-continuous immediate software force mode for PWM2B, 0: disabled, 1: low, 2: + * high, 3: disabled + */ +#define MCPWM_GEN2_B_NCIFORCE_MODE 0x00000003U +#define MCPWM_GEN2_B_NCIFORCE_MODE_M (MCPWM_GEN2_B_NCIFORCE_MODE_V << MCPWM_GEN2_B_NCIFORCE_MODE_S) +#define MCPWM_GEN2_B_NCIFORCE_MODE_V 0x00000003U +#define MCPWM_GEN2_B_NCIFORCE_MODE_S 14 -#define MCPWM_GEN2_A_REG(i) (REG_MCPWM_BASE(i) + 0x00c0) -/* MCPWM_GEN2_A_DT1 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ -/*description: Action on PWM2A triggered by event_t1 when timer decreasing. - 0: no change 1: low 2: high 3: toggle*/ -#define MCPWM_GEN2_A_DT1 0x00000003 -#define MCPWM_GEN2_A_DT1_M ((MCPWM_GEN2_A_DT1_V)<<(MCPWM_GEN2_A_DT1_S)) -#define MCPWM_GEN2_A_DT1_V 0x3 -#define MCPWM_GEN2_A_DT1_S 22 -/* MCPWM_GEN2_A_DT0 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ -/*description: Action on PWM2A triggered by event_t0 when timer decreasing*/ -#define MCPWM_GEN2_A_DT0 0x00000003 -#define MCPWM_GEN2_A_DT0_M ((MCPWM_GEN2_A_DT0_V)<<(MCPWM_GEN2_A_DT0_S)) -#define MCPWM_GEN2_A_DT0_V 0x3 -#define MCPWM_GEN2_A_DT0_S 20 -/* MCPWM_GEN2_A_DTEB : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ -/*description: Action on PWM2A triggered by event TEB when timer decreasing*/ -#define MCPWM_GEN2_A_DTEB 0x00000003 -#define MCPWM_GEN2_A_DTEB_M ((MCPWM_GEN2_A_DTEB_V)<<(MCPWM_GEN2_A_DTEB_S)) -#define MCPWM_GEN2_A_DTEB_V 0x3 -#define MCPWM_GEN2_A_DTEB_S 18 -/* MCPWM_GEN2_A_DTEA : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ -/*description: Action on PWM2A triggered by event TEA when timer decreasing*/ -#define MCPWM_GEN2_A_DTEA 0x00000003 -#define MCPWM_GEN2_A_DTEA_M ((MCPWM_GEN2_A_DTEA_V)<<(MCPWM_GEN2_A_DTEA_S)) -#define MCPWM_GEN2_A_DTEA_V 0x3 -#define MCPWM_GEN2_A_DTEA_S 16 -/* MCPWM_GEN2_A_DTEP : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ -/*description: Action on PWM2A triggered by event TEP when timer decreasing*/ -#define MCPWM_GEN2_A_DTEP 0x00000003 -#define MCPWM_GEN2_A_DTEP_M ((MCPWM_GEN2_A_DTEP_V)<<(MCPWM_GEN2_A_DTEP_S)) -#define MCPWM_GEN2_A_DTEP_V 0x3 -#define MCPWM_GEN2_A_DTEP_S 14 -/* MCPWM_GEN2_A_DTEZ : R/W ;bitpos:[13:12] ;default: 2'd0 ; */ -/*description: Action on PWM2A triggered by event TEZ when timer decreasing*/ -#define MCPWM_GEN2_A_DTEZ 0x00000003 -#define MCPWM_GEN2_A_DTEZ_M ((MCPWM_GEN2_A_DTEZ_V)<<(MCPWM_GEN2_A_DTEZ_S)) -#define MCPWM_GEN2_A_DTEZ_V 0x3 -#define MCPWM_GEN2_A_DTEZ_S 12 -/* MCPWM_GEN2_A_UT1 : R/W ;bitpos:[11:10] ;default: 2'd0 ; */ -/*description: Action on PWM2A triggered by event_t1 when timer increasing*/ -#define MCPWM_GEN2_A_UT1 0x00000003 -#define MCPWM_GEN2_A_UT1_M ((MCPWM_GEN2_A_UT1_V)<<(MCPWM_GEN2_A_UT1_S)) -#define MCPWM_GEN2_A_UT1_V 0x3 -#define MCPWM_GEN2_A_UT1_S 10 -/* MCPWM_GEN2_A_UT0 : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ -/*description: Action on PWM2A triggered by event_t0 when timer increasing*/ -#define MCPWM_GEN2_A_UT0 0x00000003 -#define MCPWM_GEN2_A_UT0_M ((MCPWM_GEN2_A_UT0_V)<<(MCPWM_GEN2_A_UT0_S)) -#define MCPWM_GEN2_A_UT0_V 0x3 -#define MCPWM_GEN2_A_UT0_S 8 -/* MCPWM_GEN2_A_UTEB : R/W ;bitpos:[7:6] ;default: 2'd0 ; */ -/*description: Action on PWM2A triggered by event TEB when timer increasing*/ -#define MCPWM_GEN2_A_UTEB 0x00000003 -#define MCPWM_GEN2_A_UTEB_M ((MCPWM_GEN2_A_UTEB_V)<<(MCPWM_GEN2_A_UTEB_S)) -#define MCPWM_GEN2_A_UTEB_V 0x3 -#define MCPWM_GEN2_A_UTEB_S 6 -/* MCPWM_GEN2_A_UTEA : R/W ;bitpos:[5:4] ;default: 2'd0 ; */ -/*description: Action on PWM2A triggered by event TEA when timer increasing*/ -#define MCPWM_GEN2_A_UTEA 0x00000003 -#define MCPWM_GEN2_A_UTEA_M ((MCPWM_GEN2_A_UTEA_V)<<(MCPWM_GEN2_A_UTEA_S)) -#define MCPWM_GEN2_A_UTEA_V 0x3 -#define MCPWM_GEN2_A_UTEA_S 4 -/* MCPWM_GEN2_A_UTEP : R/W ;bitpos:[3:2] ;default: 2'd0 ; */ -/*description: Action on PWM2A triggered by event TEP when timer increasing*/ -#define MCPWM_GEN2_A_UTEP 0x00000003 -#define MCPWM_GEN2_A_UTEP_M ((MCPWM_GEN2_A_UTEP_V)<<(MCPWM_GEN2_A_UTEP_S)) -#define MCPWM_GEN2_A_UTEP_V 0x3 -#define MCPWM_GEN2_A_UTEP_S 2 -/* MCPWM_GEN2_A_UTEZ : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: Action on PWM2A triggered by event TEZ when timer increasing*/ -#define MCPWM_GEN2_A_UTEZ 0x00000003 -#define MCPWM_GEN2_A_UTEZ_M ((MCPWM_GEN2_A_UTEZ_V)<<(MCPWM_GEN2_A_UTEZ_S)) -#define MCPWM_GEN2_A_UTEZ_V 0x3 +/** MCPWM_GEN2_A_REG register + * Actions triggered by events on PWM2A + */ +#define MCPWM_GEN2_A_REG(i) (DR_REG_MCPWM_BASE(i) + 0xc0) +/** MCPWM_GEN2_A_UTEZ : R/W; bitpos: [1:0]; default: 0; + * Action on PWM2A triggered by event TEZ when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN2_A_UTEZ 0x00000003U +#define MCPWM_GEN2_A_UTEZ_M (MCPWM_GEN2_A_UTEZ_V << MCPWM_GEN2_A_UTEZ_S) +#define MCPWM_GEN2_A_UTEZ_V 0x00000003U #define MCPWM_GEN2_A_UTEZ_S 0 +/** MCPWM_GEN2_A_UTEP : R/W; bitpos: [3:2]; default: 0; + * Action on PWM2A triggered by event TEP when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN2_A_UTEP 0x00000003U +#define MCPWM_GEN2_A_UTEP_M (MCPWM_GEN2_A_UTEP_V << MCPWM_GEN2_A_UTEP_S) +#define MCPWM_GEN2_A_UTEP_V 0x00000003U +#define MCPWM_GEN2_A_UTEP_S 2 +/** MCPWM_GEN2_A_UTEA : R/W; bitpos: [5:4]; default: 0; + * Action on PWM2A triggered by event TEA when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN2_A_UTEA 0x00000003U +#define MCPWM_GEN2_A_UTEA_M (MCPWM_GEN2_A_UTEA_V << MCPWM_GEN2_A_UTEA_S) +#define MCPWM_GEN2_A_UTEA_V 0x00000003U +#define MCPWM_GEN2_A_UTEA_S 4 +/** MCPWM_GEN2_A_UTEB : R/W; bitpos: [7:6]; default: 0; + * Action on PWM2A triggered by event TEB when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN2_A_UTEB 0x00000003U +#define MCPWM_GEN2_A_UTEB_M (MCPWM_GEN2_A_UTEB_V << MCPWM_GEN2_A_UTEB_S) +#define MCPWM_GEN2_A_UTEB_V 0x00000003U +#define MCPWM_GEN2_A_UTEB_S 6 +/** MCPWM_GEN2_A_UT0 : R/W; bitpos: [9:8]; default: 0; + * Action on PWM2A triggered by event_t0 when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN2_A_UT0 0x00000003U +#define MCPWM_GEN2_A_UT0_M (MCPWM_GEN2_A_UT0_V << MCPWM_GEN2_A_UT0_S) +#define MCPWM_GEN2_A_UT0_V 0x00000003U +#define MCPWM_GEN2_A_UT0_S 8 +/** MCPWM_GEN2_A_UT1 : R/W; bitpos: [11:10]; default: 0; + * Action on PWM2A triggered by event_t1 when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN2_A_UT1 0x00000003U +#define MCPWM_GEN2_A_UT1_M (MCPWM_GEN2_A_UT1_V << MCPWM_GEN2_A_UT1_S) +#define MCPWM_GEN2_A_UT1_V 0x00000003U +#define MCPWM_GEN2_A_UT1_S 10 +/** MCPWM_GEN2_A_DTEZ : R/W; bitpos: [13:12]; default: 0; + * Action on PWM2A triggered by event TEZ when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN2_A_DTEZ 0x00000003U +#define MCPWM_GEN2_A_DTEZ_M (MCPWM_GEN2_A_DTEZ_V << MCPWM_GEN2_A_DTEZ_S) +#define MCPWM_GEN2_A_DTEZ_V 0x00000003U +#define MCPWM_GEN2_A_DTEZ_S 12 +/** MCPWM_GEN2_A_DTEP : R/W; bitpos: [15:14]; default: 0; + * Action on PWM2A triggered by event TEP when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN2_A_DTEP 0x00000003U +#define MCPWM_GEN2_A_DTEP_M (MCPWM_GEN2_A_DTEP_V << MCPWM_GEN2_A_DTEP_S) +#define MCPWM_GEN2_A_DTEP_V 0x00000003U +#define MCPWM_GEN2_A_DTEP_S 14 +/** MCPWM_GEN2_A_DTEA : R/W; bitpos: [17:16]; default: 0; + * Action on PWM2A triggered by event TEA when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN2_A_DTEA 0x00000003U +#define MCPWM_GEN2_A_DTEA_M (MCPWM_GEN2_A_DTEA_V << MCPWM_GEN2_A_DTEA_S) +#define MCPWM_GEN2_A_DTEA_V 0x00000003U +#define MCPWM_GEN2_A_DTEA_S 16 +/** MCPWM_GEN2_A_DTEB : R/W; bitpos: [19:18]; default: 0; + * Action on PWM2A triggered by event TEB when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN2_A_DTEB 0x00000003U +#define MCPWM_GEN2_A_DTEB_M (MCPWM_GEN2_A_DTEB_V << MCPWM_GEN2_A_DTEB_S) +#define MCPWM_GEN2_A_DTEB_V 0x00000003U +#define MCPWM_GEN2_A_DTEB_S 18 +/** MCPWM_GEN2_A_DT0 : R/W; bitpos: [21:20]; default: 0; + * Action on PWM2A triggered by event_t0 when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN2_A_DT0 0x00000003U +#define MCPWM_GEN2_A_DT0_M (MCPWM_GEN2_A_DT0_V << MCPWM_GEN2_A_DT0_S) +#define MCPWM_GEN2_A_DT0_V 0x00000003U +#define MCPWM_GEN2_A_DT0_S 20 +/** MCPWM_GEN2_A_DT1 : R/W; bitpos: [23:22]; default: 0; + * Action on PWM2A triggered by event_t1 when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN2_A_DT1 0x00000003U +#define MCPWM_GEN2_A_DT1_M (MCPWM_GEN2_A_DT1_V << MCPWM_GEN2_A_DT1_S) +#define MCPWM_GEN2_A_DT1_V 0x00000003U +#define MCPWM_GEN2_A_DT1_S 22 -#define MCPWM_GEN2_B_REG(i) (REG_MCPWM_BASE(i) + 0x00c4) -/* MCPWM_GEN2_B_DT1 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ -/*description: Action on PWM2B triggered by event_t1 when timer decreasing. - 0: no change 1: low 2: high 3: toggle*/ -#define MCPWM_GEN2_B_DT1 0x00000003 -#define MCPWM_GEN2_B_DT1_M ((MCPWM_GEN2_B_DT1_V)<<(MCPWM_GEN2_B_DT1_S)) -#define MCPWM_GEN2_B_DT1_V 0x3 -#define MCPWM_GEN2_B_DT1_S 22 -/* MCPWM_GEN2_B_DT0 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ -/*description: Action on PWM2B triggered by event_t0 when timer decreasing*/ -#define MCPWM_GEN2_B_DT0 0x00000003 -#define MCPWM_GEN2_B_DT0_M ((MCPWM_GEN2_B_DT0_V)<<(MCPWM_GEN2_B_DT0_S)) -#define MCPWM_GEN2_B_DT0_V 0x3 -#define MCPWM_GEN2_B_DT0_S 20 -/* MCPWM_GEN2_B_DTEB : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ -/*description: Action on PWM2B triggered by event TEB when timer decreasing*/ -#define MCPWM_GEN2_B_DTEB 0x00000003 -#define MCPWM_GEN2_B_DTEB_M ((MCPWM_GEN2_B_DTEB_V)<<(MCPWM_GEN2_B_DTEB_S)) -#define MCPWM_GEN2_B_DTEB_V 0x3 -#define MCPWM_GEN2_B_DTEB_S 18 -/* MCPWM_GEN2_B_DTEA : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ -/*description: Action on PWM2B triggered by event TEA when timer decreasing*/ -#define MCPWM_GEN2_B_DTEA 0x00000003 -#define MCPWM_GEN2_B_DTEA_M ((MCPWM_GEN2_B_DTEA_V)<<(MCPWM_GEN2_B_DTEA_S)) -#define MCPWM_GEN2_B_DTEA_V 0x3 -#define MCPWM_GEN2_B_DTEA_S 16 -/* MCPWM_GEN2_B_DTEP : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ -/*description: Action on PWM2B triggered by event TEP when timer decreasing*/ -#define MCPWM_GEN2_B_DTEP 0x00000003 -#define MCPWM_GEN2_B_DTEP_M ((MCPWM_GEN2_B_DTEP_V)<<(MCPWM_GEN2_B_DTEP_S)) -#define MCPWM_GEN2_B_DTEP_V 0x3 -#define MCPWM_GEN2_B_DTEP_S 14 -/* MCPWM_GEN2_B_DTEZ : R/W ;bitpos:[13:12] ;default: 2'd0 ; */ -/*description: Action on PWM2B triggered by event TEZ when timer decreasing*/ -#define MCPWM_GEN2_B_DTEZ 0x00000003 -#define MCPWM_GEN2_B_DTEZ_M ((MCPWM_GEN2_B_DTEZ_V)<<(MCPWM_GEN2_B_DTEZ_S)) -#define MCPWM_GEN2_B_DTEZ_V 0x3 -#define MCPWM_GEN2_B_DTEZ_S 12 -/* MCPWM_GEN2_B_UT1 : R/W ;bitpos:[11:10] ;default: 2'd0 ; */ -/*description: Action on PWM2B triggered by event_t1 when timer increasing*/ -#define MCPWM_GEN2_B_UT1 0x00000003 -#define MCPWM_GEN2_B_UT1_M ((MCPWM_GEN2_B_UT1_V)<<(MCPWM_GEN2_B_UT1_S)) -#define MCPWM_GEN2_B_UT1_V 0x3 -#define MCPWM_GEN2_B_UT1_S 10 -/* MCPWM_GEN2_B_UT0 : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ -/*description: Action on PWM2B triggered by event_t0 when timer increasing*/ -#define MCPWM_GEN2_B_UT0 0x00000003 -#define MCPWM_GEN2_B_UT0_M ((MCPWM_GEN2_B_UT0_V)<<(MCPWM_GEN2_B_UT0_S)) -#define MCPWM_GEN2_B_UT0_V 0x3 -#define MCPWM_GEN2_B_UT0_S 8 -/* MCPWM_GEN2_B_UTEB : R/W ;bitpos:[7:6] ;default: 2'd0 ; */ -/*description: Action on PWM2B triggered by event TEB when timer increasing*/ -#define MCPWM_GEN2_B_UTEB 0x00000003 -#define MCPWM_GEN2_B_UTEB_M ((MCPWM_GEN2_B_UTEB_V)<<(MCPWM_GEN2_B_UTEB_S)) -#define MCPWM_GEN2_B_UTEB_V 0x3 -#define MCPWM_GEN2_B_UTEB_S 6 -/* MCPWM_GEN2_B_UTEA : R/W ;bitpos:[5:4] ;default: 2'd0 ; */ -/*description: Action on PWM2B triggered by event TEA when timer increasing*/ -#define MCPWM_GEN2_B_UTEA 0x00000003 -#define MCPWM_GEN2_B_UTEA_M ((MCPWM_GEN2_B_UTEA_V)<<(MCPWM_GEN2_B_UTEA_S)) -#define MCPWM_GEN2_B_UTEA_V 0x3 -#define MCPWM_GEN2_B_UTEA_S 4 -/* MCPWM_GEN2_B_UTEP : R/W ;bitpos:[3:2] ;default: 2'd0 ; */ -/*description: Action on PWM2B triggered by event TEP when timer increasing*/ -#define MCPWM_GEN2_B_UTEP 0x00000003 -#define MCPWM_GEN2_B_UTEP_M ((MCPWM_GEN2_B_UTEP_V)<<(MCPWM_GEN2_B_UTEP_S)) -#define MCPWM_GEN2_B_UTEP_V 0x3 -#define MCPWM_GEN2_B_UTEP_S 2 -/* MCPWM_GEN2_B_UTEZ : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: Action on PWM2B triggered by event TEZ when timer increasing*/ -#define MCPWM_GEN2_B_UTEZ 0x00000003 -#define MCPWM_GEN2_B_UTEZ_M ((MCPWM_GEN2_B_UTEZ_V)<<(MCPWM_GEN2_B_UTEZ_S)) -#define MCPWM_GEN2_B_UTEZ_V 0x3 +/** MCPWM_GEN2_B_REG register + * Actions triggered by events on PWM2B + */ +#define MCPWM_GEN2_B_REG(i) (DR_REG_MCPWM_BASE(i) + 0xc4) +/** MCPWM_GEN2_B_UTEZ : R/W; bitpos: [1:0]; default: 0; + * Action on PWM2B triggered by event TEZ when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN2_B_UTEZ 0x00000003U +#define MCPWM_GEN2_B_UTEZ_M (MCPWM_GEN2_B_UTEZ_V << MCPWM_GEN2_B_UTEZ_S) +#define MCPWM_GEN2_B_UTEZ_V 0x00000003U #define MCPWM_GEN2_B_UTEZ_S 0 +/** MCPWM_GEN2_B_UTEP : R/W; bitpos: [3:2]; default: 0; + * Action on PWM2B triggered by event TEP when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN2_B_UTEP 0x00000003U +#define MCPWM_GEN2_B_UTEP_M (MCPWM_GEN2_B_UTEP_V << MCPWM_GEN2_B_UTEP_S) +#define MCPWM_GEN2_B_UTEP_V 0x00000003U +#define MCPWM_GEN2_B_UTEP_S 2 +/** MCPWM_GEN2_B_UTEA : R/W; bitpos: [5:4]; default: 0; + * Action on PWM2B triggered by event TEA when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN2_B_UTEA 0x00000003U +#define MCPWM_GEN2_B_UTEA_M (MCPWM_GEN2_B_UTEA_V << MCPWM_GEN2_B_UTEA_S) +#define MCPWM_GEN2_B_UTEA_V 0x00000003U +#define MCPWM_GEN2_B_UTEA_S 4 +/** MCPWM_GEN2_B_UTEB : R/W; bitpos: [7:6]; default: 0; + * Action on PWM2B triggered by event TEB when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN2_B_UTEB 0x00000003U +#define MCPWM_GEN2_B_UTEB_M (MCPWM_GEN2_B_UTEB_V << MCPWM_GEN2_B_UTEB_S) +#define MCPWM_GEN2_B_UTEB_V 0x00000003U +#define MCPWM_GEN2_B_UTEB_S 6 +/** MCPWM_GEN2_B_UT0 : R/W; bitpos: [9:8]; default: 0; + * Action on PWM2B triggered by event_t0 when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN2_B_UT0 0x00000003U +#define MCPWM_GEN2_B_UT0_M (MCPWM_GEN2_B_UT0_V << MCPWM_GEN2_B_UT0_S) +#define MCPWM_GEN2_B_UT0_V 0x00000003U +#define MCPWM_GEN2_B_UT0_S 8 +/** MCPWM_GEN2_B_UT1 : R/W; bitpos: [11:10]; default: 0; + * Action on PWM2B triggered by event_t1 when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN2_B_UT1 0x00000003U +#define MCPWM_GEN2_B_UT1_M (MCPWM_GEN2_B_UT1_V << MCPWM_GEN2_B_UT1_S) +#define MCPWM_GEN2_B_UT1_V 0x00000003U +#define MCPWM_GEN2_B_UT1_S 10 +/** MCPWM_GEN2_B_DTEZ : R/W; bitpos: [13:12]; default: 0; + * Action on PWM2B triggered by event TEZ when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN2_B_DTEZ 0x00000003U +#define MCPWM_GEN2_B_DTEZ_M (MCPWM_GEN2_B_DTEZ_V << MCPWM_GEN2_B_DTEZ_S) +#define MCPWM_GEN2_B_DTEZ_V 0x00000003U +#define MCPWM_GEN2_B_DTEZ_S 12 +/** MCPWM_GEN2_B_DTEP : R/W; bitpos: [15:14]; default: 0; + * Action on PWM2B triggered by event TEP when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN2_B_DTEP 0x00000003U +#define MCPWM_GEN2_B_DTEP_M (MCPWM_GEN2_B_DTEP_V << MCPWM_GEN2_B_DTEP_S) +#define MCPWM_GEN2_B_DTEP_V 0x00000003U +#define MCPWM_GEN2_B_DTEP_S 14 +/** MCPWM_GEN2_B_DTEA : R/W; bitpos: [17:16]; default: 0; + * Action on PWM2B triggered by event TEA when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN2_B_DTEA 0x00000003U +#define MCPWM_GEN2_B_DTEA_M (MCPWM_GEN2_B_DTEA_V << MCPWM_GEN2_B_DTEA_S) +#define MCPWM_GEN2_B_DTEA_V 0x00000003U +#define MCPWM_GEN2_B_DTEA_S 16 +/** MCPWM_GEN2_B_DTEB : R/W; bitpos: [19:18]; default: 0; + * Action on PWM2B triggered by event TEB when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN2_B_DTEB 0x00000003U +#define MCPWM_GEN2_B_DTEB_M (MCPWM_GEN2_B_DTEB_V << MCPWM_GEN2_B_DTEB_S) +#define MCPWM_GEN2_B_DTEB_V 0x00000003U +#define MCPWM_GEN2_B_DTEB_S 18 +/** MCPWM_GEN2_B_DT0 : R/W; bitpos: [21:20]; default: 0; + * Action on PWM2B triggered by event_t0 when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN2_B_DT0 0x00000003U +#define MCPWM_GEN2_B_DT0_M (MCPWM_GEN2_B_DT0_V << MCPWM_GEN2_B_DT0_S) +#define MCPWM_GEN2_B_DT0_V 0x00000003U +#define MCPWM_GEN2_B_DT0_S 20 +/** MCPWM_GEN2_B_DT1 : R/W; bitpos: [23:22]; default: 0; + * Action on PWM2B triggered by event_t1 when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN2_B_DT1 0x00000003U +#define MCPWM_GEN2_B_DT1_M (MCPWM_GEN2_B_DT1_V << MCPWM_GEN2_B_DT1_S) +#define MCPWM_GEN2_B_DT1_V 0x00000003U +#define MCPWM_GEN2_B_DT1_S 22 -#define MCPWM_DT2_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x00c8) -/* MCPWM_DT2_CLK_SEL : R/W ;bitpos:[17] ;default: 1'd0 ; */ -/*description: Dead time generator 1 clock selection. 0: PWM_clk 1: PT_clk*/ -#define MCPWM_DT2_CLK_SEL (BIT(17)) -#define MCPWM_DT2_CLK_SEL_M (BIT(17)) -#define MCPWM_DT2_CLK_SEL_V 0x1 -#define MCPWM_DT2_CLK_SEL_S 17 -/* MCPWM_DT2_B_OUTBYPASS : R/W ;bitpos:[16] ;default: 1'd1 ; */ -/*description: S0 in documentation*/ -#define MCPWM_DT2_B_OUTBYPASS (BIT(16)) -#define MCPWM_DT2_B_OUTBYPASS_M (BIT(16)) -#define MCPWM_DT2_B_OUTBYPASS_V 0x1 -#define MCPWM_DT2_B_OUTBYPASS_S 16 -/* MCPWM_DT2_A_OUTBYPASS : R/W ;bitpos:[15] ;default: 1'd1 ; */ -/*description: S1 in documentation*/ -#define MCPWM_DT2_A_OUTBYPASS (BIT(15)) -#define MCPWM_DT2_A_OUTBYPASS_M (BIT(15)) -#define MCPWM_DT2_A_OUTBYPASS_V 0x1 -#define MCPWM_DT2_A_OUTBYPASS_S 15 -/* MCPWM_DT2_FED_OUTINVERT : R/W ;bitpos:[14] ;default: 1'd0 ; */ -/*description: S3 in documentation*/ -#define MCPWM_DT2_FED_OUTINVERT (BIT(14)) -#define MCPWM_DT2_FED_OUTINVERT_M (BIT(14)) -#define MCPWM_DT2_FED_OUTINVERT_V 0x1 -#define MCPWM_DT2_FED_OUTINVERT_S 14 -/* MCPWM_DT2_RED_OUTINVERT : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: S2 in documentation*/ -#define MCPWM_DT2_RED_OUTINVERT (BIT(13)) -#define MCPWM_DT2_RED_OUTINVERT_M (BIT(13)) -#define MCPWM_DT2_RED_OUTINVERT_V 0x1 -#define MCPWM_DT2_RED_OUTINVERT_S 13 -/* MCPWM_DT2_FED_INSEL : R/W ;bitpos:[12] ;default: 1'd0 ; */ -/*description: S5 in documentation*/ -#define MCPWM_DT2_FED_INSEL (BIT(12)) -#define MCPWM_DT2_FED_INSEL_M (BIT(12)) -#define MCPWM_DT2_FED_INSEL_V 0x1 -#define MCPWM_DT2_FED_INSEL_S 12 -/* MCPWM_DT2_RED_INSEL : R/W ;bitpos:[11] ;default: 1'd0 ; */ -/*description: S4 in documentation*/ -#define MCPWM_DT2_RED_INSEL (BIT(11)) -#define MCPWM_DT2_RED_INSEL_M (BIT(11)) -#define MCPWM_DT2_RED_INSEL_V 0x1 -#define MCPWM_DT2_RED_INSEL_S 11 -/* MCPWM_DT2_B_OUTSWAP : R/W ;bitpos:[10] ;default: 1'd0 ; */ -/*description: S7 in documentation*/ -#define MCPWM_DT2_B_OUTSWAP (BIT(10)) -#define MCPWM_DT2_B_OUTSWAP_M (BIT(10)) -#define MCPWM_DT2_B_OUTSWAP_V 0x1 -#define MCPWM_DT2_B_OUTSWAP_S 10 -/* MCPWM_DT2_A_OUTSWAP : R/W ;bitpos:[9] ;default: 1'd0 ; */ -/*description: S6 in documentation*/ -#define MCPWM_DT2_A_OUTSWAP (BIT(9)) -#define MCPWM_DT2_A_OUTSWAP_M (BIT(9)) -#define MCPWM_DT2_A_OUTSWAP_V 0x1 -#define MCPWM_DT2_A_OUTSWAP_S 9 -/* MCPWM_DT2_DEB_MODE : R/W ;bitpos:[8] ;default: 1'd0 ; */ -/*description: S8 in documentation dual-edge B mode 0: FED/RED take effect - on different path separately 1: FED/RED take effect on B path A out is in bypass or normal operation mode*/ -#define MCPWM_DT2_DEB_MODE (BIT(8)) -#define MCPWM_DT2_DEB_MODE_M (BIT(8)) -#define MCPWM_DT2_DEB_MODE_V 0x1 -#define MCPWM_DT2_DEB_MODE_S 8 -/* MCPWM_DT2_RED_UPMETHOD : R/W ;bitpos:[7:4] ;default: 4'd0 ; */ -/*description: Update method for RED (rising edge delay) active reg. 0: immediate - bit0: TEZ bit1: TEP bit2: sync bit3: disable update*/ -#define MCPWM_DT2_RED_UPMETHOD 0x0000000F -#define MCPWM_DT2_RED_UPMETHOD_M ((MCPWM_DT2_RED_UPMETHOD_V)<<(MCPWM_DT2_RED_UPMETHOD_S)) -#define MCPWM_DT2_RED_UPMETHOD_V 0xF -#define MCPWM_DT2_RED_UPMETHOD_S 4 -/* MCPWM_DT2_FED_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: Update method for FED (falling edge delay) active reg. 0: immediate - bit0: TEZ bit1: TEP bit2: sync bit3: disable update*/ -#define MCPWM_DT2_FED_UPMETHOD 0x0000000F -#define MCPWM_DT2_FED_UPMETHOD_M ((MCPWM_DT2_FED_UPMETHOD_V)<<(MCPWM_DT2_FED_UPMETHOD_S)) -#define MCPWM_DT2_FED_UPMETHOD_V 0xF +/** MCPWM_DT2_CFG_REG register + * PWM generator 2 dead time type selection and configuration + */ +#define MCPWM_DT2_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0xc8) +/** MCPWM_DT2_FED_UPMETHOD : R/W; bitpos: [3:0]; default: 0; + * Update method for FED (falling edge delay) active register. 0: immediate,when bit0 + * is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when + * bit3 is set to 1: disable the update + */ +#define MCPWM_DT2_FED_UPMETHOD 0x0000000FU +#define MCPWM_DT2_FED_UPMETHOD_M (MCPWM_DT2_FED_UPMETHOD_V << MCPWM_DT2_FED_UPMETHOD_S) +#define MCPWM_DT2_FED_UPMETHOD_V 0x0000000FU #define MCPWM_DT2_FED_UPMETHOD_S 0 +/** MCPWM_DT2_RED_UPMETHOD : R/W; bitpos: [7:4]; default: 0; + * Update method for RED (rising edge delay) active register. 0: immediate,when bit0 + * is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when + * bit3 is set to 1: disable the update + */ +#define MCPWM_DT2_RED_UPMETHOD 0x0000000FU +#define MCPWM_DT2_RED_UPMETHOD_M (MCPWM_DT2_RED_UPMETHOD_V << MCPWM_DT2_RED_UPMETHOD_S) +#define MCPWM_DT2_RED_UPMETHOD_V 0x0000000FU +#define MCPWM_DT2_RED_UPMETHOD_S 4 +/** MCPWM_DT2_DEB_MODE : R/W; bitpos: [8]; default: 0; + * S8 in table, dual-edge B mode, 0: fed/red take effect on different path separately, + * 1: fed/red take effect on B path, A out is in bypass or dulpB mode + */ +#define MCPWM_DT2_DEB_MODE (BIT(8)) +#define MCPWM_DT2_DEB_MODE_M (MCPWM_DT2_DEB_MODE_V << MCPWM_DT2_DEB_MODE_S) +#define MCPWM_DT2_DEB_MODE_V 0x00000001U +#define MCPWM_DT2_DEB_MODE_S 8 +/** MCPWM_DT2_A_OUTSWAP : R/W; bitpos: [9]; default: 0; + * S6 in table + */ +#define MCPWM_DT2_A_OUTSWAP (BIT(9)) +#define MCPWM_DT2_A_OUTSWAP_M (MCPWM_DT2_A_OUTSWAP_V << MCPWM_DT2_A_OUTSWAP_S) +#define MCPWM_DT2_A_OUTSWAP_V 0x00000001U +#define MCPWM_DT2_A_OUTSWAP_S 9 +/** MCPWM_DT2_B_OUTSWAP : R/W; bitpos: [10]; default: 0; + * S7 in table + */ +#define MCPWM_DT2_B_OUTSWAP (BIT(10)) +#define MCPWM_DT2_B_OUTSWAP_M (MCPWM_DT2_B_OUTSWAP_V << MCPWM_DT2_B_OUTSWAP_S) +#define MCPWM_DT2_B_OUTSWAP_V 0x00000001U +#define MCPWM_DT2_B_OUTSWAP_S 10 +/** MCPWM_DT2_RED_INSEL : R/W; bitpos: [11]; default: 0; + * S4 in table + */ +#define MCPWM_DT2_RED_INSEL (BIT(11)) +#define MCPWM_DT2_RED_INSEL_M (MCPWM_DT2_RED_INSEL_V << MCPWM_DT2_RED_INSEL_S) +#define MCPWM_DT2_RED_INSEL_V 0x00000001U +#define MCPWM_DT2_RED_INSEL_S 11 +/** MCPWM_DT2_FED_INSEL : R/W; bitpos: [12]; default: 0; + * S5 in table + */ +#define MCPWM_DT2_FED_INSEL (BIT(12)) +#define MCPWM_DT2_FED_INSEL_M (MCPWM_DT2_FED_INSEL_V << MCPWM_DT2_FED_INSEL_S) +#define MCPWM_DT2_FED_INSEL_V 0x00000001U +#define MCPWM_DT2_FED_INSEL_S 12 +/** MCPWM_DT2_RED_OUTINVERT : R/W; bitpos: [13]; default: 0; + * S2 in table + */ +#define MCPWM_DT2_RED_OUTINVERT (BIT(13)) +#define MCPWM_DT2_RED_OUTINVERT_M (MCPWM_DT2_RED_OUTINVERT_V << MCPWM_DT2_RED_OUTINVERT_S) +#define MCPWM_DT2_RED_OUTINVERT_V 0x00000001U +#define MCPWM_DT2_RED_OUTINVERT_S 13 +/** MCPWM_DT2_FED_OUTINVERT : R/W; bitpos: [14]; default: 0; + * S3 in table + */ +#define MCPWM_DT2_FED_OUTINVERT (BIT(14)) +#define MCPWM_DT2_FED_OUTINVERT_M (MCPWM_DT2_FED_OUTINVERT_V << MCPWM_DT2_FED_OUTINVERT_S) +#define MCPWM_DT2_FED_OUTINVERT_V 0x00000001U +#define MCPWM_DT2_FED_OUTINVERT_S 14 +/** MCPWM_DT2_A_OUTBYPASS : R/W; bitpos: [15]; default: 1; + * S1 in table + */ +#define MCPWM_DT2_A_OUTBYPASS (BIT(15)) +#define MCPWM_DT2_A_OUTBYPASS_M (MCPWM_DT2_A_OUTBYPASS_V << MCPWM_DT2_A_OUTBYPASS_S) +#define MCPWM_DT2_A_OUTBYPASS_V 0x00000001U +#define MCPWM_DT2_A_OUTBYPASS_S 15 +/** MCPWM_DT2_B_OUTBYPASS : R/W; bitpos: [16]; default: 1; + * S0 in table + */ +#define MCPWM_DT2_B_OUTBYPASS (BIT(16)) +#define MCPWM_DT2_B_OUTBYPASS_M (MCPWM_DT2_B_OUTBYPASS_V << MCPWM_DT2_B_OUTBYPASS_S) +#define MCPWM_DT2_B_OUTBYPASS_V 0x00000001U +#define MCPWM_DT2_B_OUTBYPASS_S 16 +/** MCPWM_DT2_CLK_SEL : R/W; bitpos: [17]; default: 0; + * Dead time clock selection. 0: PWM_clk, 1: PT_clk + */ +#define MCPWM_DT2_CLK_SEL (BIT(17)) +#define MCPWM_DT2_CLK_SEL_M (MCPWM_DT2_CLK_SEL_V << MCPWM_DT2_CLK_SEL_S) +#define MCPWM_DT2_CLK_SEL_V 0x00000001U +#define MCPWM_DT2_CLK_SEL_S 17 -#define MCPWM_DT2_FED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x00cc) -/* MCPWM_DT2_FED : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ -/*description: Shadow reg for FED*/ -#define MCPWM_DT2_FED 0x0000FFFF -#define MCPWM_DT2_FED_M ((MCPWM_DT2_FED_V)<<(MCPWM_DT2_FED_S)) -#define MCPWM_DT2_FED_V 0xFFFF +/** MCPWM_DT2_FED_CFG_REG register + * PWM generator 2 shadow register for falling edge delay (FED). + */ +#define MCPWM_DT2_FED_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0xcc) +/** MCPWM_DT2_FED : R/W; bitpos: [15:0]; default: 0; + * Shadow register for FED + */ +#define MCPWM_DT2_FED 0x0000FFFFU +#define MCPWM_DT2_FED_M (MCPWM_DT2_FED_V << MCPWM_DT2_FED_S) +#define MCPWM_DT2_FED_V 0x0000FFFFU #define MCPWM_DT2_FED_S 0 -#define MCPWM_DT2_RED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x00d0) -/* MCPWM_DT2_RED : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ -/*description: Shadow reg for RED*/ -#define MCPWM_DT2_RED 0x0000FFFF -#define MCPWM_DT2_RED_M ((MCPWM_DT2_RED_V)<<(MCPWM_DT2_RED_S)) -#define MCPWM_DT2_RED_V 0xFFFF +/** MCPWM_DT2_RED_CFG_REG register + * PWM generator 2 shadow register for rising edge delay (RED). + */ +#define MCPWM_DT2_RED_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0xd0) +/** MCPWM_DT2_RED : R/W; bitpos: [15:0]; default: 0; + * Shadow register for RED + */ +#define MCPWM_DT2_RED 0x0000FFFFU +#define MCPWM_DT2_RED_M (MCPWM_DT2_RED_V << MCPWM_DT2_RED_S) +#define MCPWM_DT2_RED_V 0x0000FFFFU #define MCPWM_DT2_RED_S 0 -#define MCPWM_CARRIER2_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x00d4) -/* MCPWM_CARRIER2_IN_INVERT : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: When set invert the input of PWM2A and PWM2B for this submodule*/ -#define MCPWM_CARRIER2_IN_INVERT (BIT(13)) -#define MCPWM_CARRIER2_IN_INVERT_M (BIT(13)) -#define MCPWM_CARRIER2_IN_INVERT_V 0x1 -#define MCPWM_CARRIER2_IN_INVERT_S 13 -/* MCPWM_CARRIER2_OUT_INVERT : R/W ;bitpos:[12] ;default: 1'd0 ; */ -/*description: When set invert the output of PWM2A and PWM2B for this submodule*/ -#define MCPWM_CARRIER2_OUT_INVERT (BIT(12)) -#define MCPWM_CARRIER2_OUT_INVERT_M (BIT(12)) -#define MCPWM_CARRIER2_OUT_INVERT_V 0x1 -#define MCPWM_CARRIER2_OUT_INVERT_S 12 -/* MCPWM_CARRIER2_OSHWTH : R/W ;bitpos:[11:8] ;default: 4'd0 ; */ -/*description: Width of the fist pulse in number of periods of the carrier*/ -#define MCPWM_CARRIER2_OSHWTH 0x0000000F -#define MCPWM_CARRIER2_OSHWTH_M ((MCPWM_CARRIER2_OSHWTH_V)<<(MCPWM_CARRIER2_OSHWTH_S)) -#define MCPWM_CARRIER2_OSHWTH_V 0xF -#define MCPWM_CARRIER2_OSHWTH_S 8 -/* MCPWM_CARRIER2_DUTY : R/W ;bitpos:[7:5] ;default: 3'd0 ; */ -/*description: Carrier duty selection. Duty = PWM_CARRIER2_DUTY / 8*/ -#define MCPWM_CARRIER2_DUTY 0x00000007 -#define MCPWM_CARRIER2_DUTY_M ((MCPWM_CARRIER2_DUTY_V)<<(MCPWM_CARRIER2_DUTY_S)) -#define MCPWM_CARRIER2_DUTY_V 0x7 -#define MCPWM_CARRIER2_DUTY_S 5 -/* MCPWM_CARRIER2_PRESCALE : R/W ;bitpos:[4:1] ;default: 4'd0 ; */ -/*description: PWM carrier2 clock (PC_clk) prescale value. Period of PC_clk - = period of PWM_clk * (PWM_CARRIER2_PRESCALE + 1)*/ -#define MCPWM_CARRIER2_PRESCALE 0x0000000F -#define MCPWM_CARRIER2_PRESCALE_M ((MCPWM_CARRIER2_PRESCALE_V)<<(MCPWM_CARRIER2_PRESCALE_S)) -#define MCPWM_CARRIER2_PRESCALE_V 0xF -#define MCPWM_CARRIER2_PRESCALE_S 1 -/* MCPWM_CARRIER2_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */ -/*description: When set carrier2 function is enabled. When cleared carrier2 is bypassed*/ -#define MCPWM_CARRIER2_EN (BIT(0)) -#define MCPWM_CARRIER2_EN_M (BIT(0)) -#define MCPWM_CARRIER2_EN_V 0x1 +/** MCPWM_CARRIER2_CFG_REG register + * PWM generator 2 carrier enable and configuratoin + */ +#define MCPWM_CARRIER2_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0xd4) +/** MCPWM_CARRIER2_EN : R/W; bitpos: [0]; default: 0; + * When set, carrier2 function is enabled. When cleared, carrier2 is bypassed + */ +#define MCPWM_CARRIER2_EN (BIT(0)) +#define MCPWM_CARRIER2_EN_M (MCPWM_CARRIER2_EN_V << MCPWM_CARRIER2_EN_S) +#define MCPWM_CARRIER2_EN_V 0x00000001U #define MCPWM_CARRIER2_EN_S 0 +/** MCPWM_CARRIER2_PRESCALE : R/W; bitpos: [4:1]; default: 0; + * PWM carrier2 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk * + * (PWM_CARRIER0_PRESCALE + 1) + */ +#define MCPWM_CARRIER2_PRESCALE 0x0000000FU +#define MCPWM_CARRIER2_PRESCALE_M (MCPWM_CARRIER2_PRESCALE_V << MCPWM_CARRIER2_PRESCALE_S) +#define MCPWM_CARRIER2_PRESCALE_V 0x0000000FU +#define MCPWM_CARRIER2_PRESCALE_S 1 +/** MCPWM_CARRIER2_DUTY : R/W; bitpos: [7:5]; default: 0; + * carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8 + */ +#define MCPWM_CARRIER2_DUTY 0x00000007U +#define MCPWM_CARRIER2_DUTY_M (MCPWM_CARRIER2_DUTY_V << MCPWM_CARRIER2_DUTY_S) +#define MCPWM_CARRIER2_DUTY_V 0x00000007U +#define MCPWM_CARRIER2_DUTY_S 5 +/** MCPWM_CARRIER2_OSHTWTH : R/W; bitpos: [11:8]; default: 0; + * width of the first pulse in number of periods of the carrier + */ +#define MCPWM_CARRIER2_OSHTWTH 0x0000000FU +#define MCPWM_CARRIER2_OSHTWTH_M (MCPWM_CARRIER2_OSHTWTH_V << MCPWM_CARRIER2_OSHTWTH_S) +#define MCPWM_CARRIER2_OSHTWTH_V 0x0000000FU +#define MCPWM_CARRIER2_OSHTWTH_S 8 +/** MCPWM_CARRIER2_OUT_INVERT : R/W; bitpos: [12]; default: 0; + * when set, invert the output of PWM2A and PWM2B for this submodule + */ +#define MCPWM_CARRIER2_OUT_INVERT (BIT(12)) +#define MCPWM_CARRIER2_OUT_INVERT_M (MCPWM_CARRIER2_OUT_INVERT_V << MCPWM_CARRIER2_OUT_INVERT_S) +#define MCPWM_CARRIER2_OUT_INVERT_V 0x00000001U +#define MCPWM_CARRIER2_OUT_INVERT_S 12 +/** MCPWM_CARRIER2_IN_INVERT : R/W; bitpos: [13]; default: 0; + * when set, invert the input of PWM2A and PWM2B for this submodule + */ +#define MCPWM_CARRIER2_IN_INVERT (BIT(13)) +#define MCPWM_CARRIER2_IN_INVERT_M (MCPWM_CARRIER2_IN_INVERT_V << MCPWM_CARRIER2_IN_INVERT_S) +#define MCPWM_CARRIER2_IN_INVERT_V 0x00000001U +#define MCPWM_CARRIER2_IN_INVERT_S 13 -#define MCPWM_FH2_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x00d8) -/* MCPWM_FH2_B_OST_U : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ -/*description: One-shot mode action on PWM2B when fault event occurs and timer - is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ -#define MCPWM_FH2_B_OST_U 0x00000003 -#define MCPWM_FH2_B_OST_U_M ((MCPWM_FH2_B_OST_U_V)<<(MCPWM_FH2_B_OST_U_S)) -#define MCPWM_FH2_B_OST_U_V 0x3 -#define MCPWM_FH2_B_OST_U_S 22 -/* MCPWM_FH2_B_OST_D : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ -/*description: One-shot mode action on PWM2B when fault event occurs and timer - is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ -#define MCPWM_FH2_B_OST_D 0x00000003 -#define MCPWM_FH2_B_OST_D_M ((MCPWM_FH2_B_OST_D_V)<<(MCPWM_FH2_B_OST_D_S)) -#define MCPWM_FH2_B_OST_D_V 0x3 -#define MCPWM_FH2_B_OST_D_S 20 -/* MCPWM_FH2_B_CBC_U : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ -/*description: Cycle-by-cycle mode action on PWM2B when fault event occurs and - timer is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ -#define MCPWM_FH2_B_CBC_U 0x00000003 -#define MCPWM_FH2_B_CBC_U_M ((MCPWM_FH2_B_CBC_U_V)<<(MCPWM_FH2_B_CBC_U_S)) -#define MCPWM_FH2_B_CBC_U_V 0x3 -#define MCPWM_FH2_B_CBC_U_S 18 -/* MCPWM_FH2_B_CBC_D : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ -/*description: Cycle-by-cycle mode action on PWM2B when fault event occurs and - timer is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ -#define MCPWM_FH2_B_CBC_D 0x00000003 -#define MCPWM_FH2_B_CBC_D_M ((MCPWM_FH2_B_CBC_D_V)<<(MCPWM_FH2_B_CBC_D_S)) -#define MCPWM_FH2_B_CBC_D_V 0x3 -#define MCPWM_FH2_B_CBC_D_S 16 -/* MCPWM_FH2_A_OST_U : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ -/*description: One-shot mode action on PWM2A when fault event occurs and timer - is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ -#define MCPWM_FH2_A_OST_U 0x00000003 -#define MCPWM_FH2_A_OST_U_M ((MCPWM_FH2_A_OST_U_V)<<(MCPWM_FH2_A_OST_U_S)) -#define MCPWM_FH2_A_OST_U_V 0x3 -#define MCPWM_FH2_A_OST_U_S 14 -/* MCPWM_FH2_A_OST_D : R/W ;bitpos:[13:12] ;default: 2'd0 ; */ -/*description: One-shot mode action on PWM2A when fault event occurs and timer - is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ -#define MCPWM_FH2_A_OST_D 0x00000003 -#define MCPWM_FH2_A_OST_D_M ((MCPWM_FH2_A_OST_D_V)<<(MCPWM_FH2_A_OST_D_S)) -#define MCPWM_FH2_A_OST_D_V 0x3 -#define MCPWM_FH2_A_OST_D_S 12 -/* MCPWM_FH2_A_CBC_U : R/W ;bitpos:[11:10] ;default: 2'd0 ; */ -/*description: Cycle-by-cycle mode action on PWM2A when fault event occurs and - timer is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ -#define MCPWM_FH2_A_CBC_U 0x00000003 -#define MCPWM_FH2_A_CBC_U_M ((MCPWM_FH2_A_CBC_U_V)<<(MCPWM_FH2_A_CBC_U_S)) -#define MCPWM_FH2_A_CBC_U_V 0x3 -#define MCPWM_FH2_A_CBC_U_S 10 -/* MCPWM_FH2_A_CBC_D : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ -/*description: Cycle-by-cycle mode action on PWM2A when fault event occurs and - timer is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ -#define MCPWM_FH2_A_CBC_D 0x00000003 -#define MCPWM_FH2_A_CBC_D_M ((MCPWM_FH2_A_CBC_D_V)<<(MCPWM_FH2_A_CBC_D_S)) -#define MCPWM_FH2_A_CBC_D_V 0x3 -#define MCPWM_FH2_A_CBC_D_S 8 -/* MCPWM_FH2_F0_OST : R/W ;bitpos:[7] ;default: 1'd0 ; */ -/*description: event_f0 will trigger one-shot mode action. 0: disable 1: enable*/ -#define MCPWM_FH2_F0_OST (BIT(7)) -#define MCPWM_FH2_F0_OST_M (BIT(7)) -#define MCPWM_FH2_F0_OST_V 0x1 -#define MCPWM_FH2_F0_OST_S 7 -/* MCPWM_FH2_F1_OST : R/W ;bitpos:[6] ;default: 1'd0 ; */ -/*description: event_f1 will trigger one-shot mode action. 0: disable 1: enable*/ -#define MCPWM_FH2_F1_OST (BIT(6)) -#define MCPWM_FH2_F1_OST_M (BIT(6)) -#define MCPWM_FH2_F1_OST_V 0x1 -#define MCPWM_FH2_F1_OST_S 6 -/* MCPWM_FH2_F2_OST : R/W ;bitpos:[5] ;default: 1'd0 ; */ -/*description: event_f2 will trigger one-shot mode action. 0: disable 1: enable*/ -#define MCPWM_FH2_F2_OST (BIT(5)) -#define MCPWM_FH2_F2_OST_M (BIT(5)) -#define MCPWM_FH2_F2_OST_V 0x1 -#define MCPWM_FH2_F2_OST_S 5 -/* MCPWM_FH2_SW_OST : R/W ;bitpos:[4] ;default: 1'd0 ; */ -/*description: Enable register for software force one-shot mode action. 0: disable 1: enable*/ -#define MCPWM_FH2_SW_OST (BIT(4)) -#define MCPWM_FH2_SW_OST_M (BIT(4)) -#define MCPWM_FH2_SW_OST_V 0x1 -#define MCPWM_FH2_SW_OST_S 4 -/* MCPWM_FH2_F0_CBC : R/W ;bitpos:[3] ;default: 1'd0 ; */ -/*description: event_f0 will trigger cycle-by-cycle mode action. 0: disable 1: enable*/ -#define MCPWM_FH2_F0_CBC (BIT(3)) -#define MCPWM_FH2_F0_CBC_M (BIT(3)) -#define MCPWM_FH2_F0_CBC_V 0x1 -#define MCPWM_FH2_F0_CBC_S 3 -/* MCPWM_FH2_F1_CBC : R/W ;bitpos:[2] ;default: 1'd0 ; */ -/*description: event_f1 will trigger cycle-by-cycle mode action. 0: disable 1: enable*/ -#define MCPWM_FH2_F1_CBC (BIT(2)) -#define MCPWM_FH2_F1_CBC_M (BIT(2)) -#define MCPWM_FH2_F1_CBC_V 0x1 -#define MCPWM_FH2_F1_CBC_S 2 -/* MCPWM_FH2_F2_CBC : R/W ;bitpos:[1] ;default: 1'd0 ; */ -/*description: event_f2 will trigger cycle-by-cycle mode action. 0: disable 1: enable*/ -#define MCPWM_FH2_F2_CBC (BIT(1)) -#define MCPWM_FH2_F2_CBC_M (BIT(1)) -#define MCPWM_FH2_F2_CBC_V 0x1 -#define MCPWM_FH2_F2_CBC_S 1 -/* MCPWM_FH2_SW_CBC : R/W ;bitpos:[0] ;default: 1'd0 ; */ -/*description: Enable register for software force cycle-by-cycle mode action. - 0: disable 1: enable*/ -#define MCPWM_FH2_SW_CBC (BIT(0)) -#define MCPWM_FH2_SW_CBC_M (BIT(0)) -#define MCPWM_FH2_SW_CBC_V 0x1 +/** MCPWM_FH2_CFG0_REG register + * Actions on PWM2A and PWM2B trip events + */ +#define MCPWM_FH2_CFG0_REG(i) (DR_REG_MCPWM_BASE(i) + 0xd8) +/** MCPWM_FH2_SW_CBC : R/W; bitpos: [0]; default: 0; + * Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable + */ +#define MCPWM_FH2_SW_CBC (BIT(0)) +#define MCPWM_FH2_SW_CBC_M (MCPWM_FH2_SW_CBC_V << MCPWM_FH2_SW_CBC_S) +#define MCPWM_FH2_SW_CBC_V 0x00000001U #define MCPWM_FH2_SW_CBC_S 0 +/** MCPWM_FH2_F2_CBC : R/W; bitpos: [1]; default: 0; + * fault_event2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + */ +#define MCPWM_FH2_F2_CBC (BIT(1)) +#define MCPWM_FH2_F2_CBC_M (MCPWM_FH2_F2_CBC_V << MCPWM_FH2_F2_CBC_S) +#define MCPWM_FH2_F2_CBC_V 0x00000001U +#define MCPWM_FH2_F2_CBC_S 1 +/** MCPWM_FH2_F1_CBC : R/W; bitpos: [2]; default: 0; + * fault_event1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + */ +#define MCPWM_FH2_F1_CBC (BIT(2)) +#define MCPWM_FH2_F1_CBC_M (MCPWM_FH2_F1_CBC_V << MCPWM_FH2_F1_CBC_S) +#define MCPWM_FH2_F1_CBC_V 0x00000001U +#define MCPWM_FH2_F1_CBC_S 2 +/** MCPWM_FH2_F0_CBC : R/W; bitpos: [3]; default: 0; + * fault_event0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + */ +#define MCPWM_FH2_F0_CBC (BIT(3)) +#define MCPWM_FH2_F0_CBC_M (MCPWM_FH2_F0_CBC_V << MCPWM_FH2_F0_CBC_S) +#define MCPWM_FH2_F0_CBC_V 0x00000001U +#define MCPWM_FH2_F0_CBC_S 3 +/** MCPWM_FH2_SW_OST : R/W; bitpos: [4]; default: 0; + * Enable register for software force one-shot mode action. 0: disable, 1: enable + */ +#define MCPWM_FH2_SW_OST (BIT(4)) +#define MCPWM_FH2_SW_OST_M (MCPWM_FH2_SW_OST_V << MCPWM_FH2_SW_OST_S) +#define MCPWM_FH2_SW_OST_V 0x00000001U +#define MCPWM_FH2_SW_OST_S 4 +/** MCPWM_FH2_F2_OST : R/W; bitpos: [5]; default: 0; + * fault_event2 will trigger one-shot mode action. 0: disable, 1: enable + */ +#define MCPWM_FH2_F2_OST (BIT(5)) +#define MCPWM_FH2_F2_OST_M (MCPWM_FH2_F2_OST_V << MCPWM_FH2_F2_OST_S) +#define MCPWM_FH2_F2_OST_V 0x00000001U +#define MCPWM_FH2_F2_OST_S 5 +/** MCPWM_FH2_F1_OST : R/W; bitpos: [6]; default: 0; + * fault_event1 will trigger one-shot mode action. 0: disable, 1: enable + */ +#define MCPWM_FH2_F1_OST (BIT(6)) +#define MCPWM_FH2_F1_OST_M (MCPWM_FH2_F1_OST_V << MCPWM_FH2_F1_OST_S) +#define MCPWM_FH2_F1_OST_V 0x00000001U +#define MCPWM_FH2_F1_OST_S 6 +/** MCPWM_FH2_F0_OST : R/W; bitpos: [7]; default: 0; + * fault_event0 will trigger one-shot mode action. 0: disable, 1: enable + */ +#define MCPWM_FH2_F0_OST (BIT(7)) +#define MCPWM_FH2_F0_OST_M (MCPWM_FH2_F0_OST_V << MCPWM_FH2_F0_OST_S) +#define MCPWM_FH2_F0_OST_V 0x00000001U +#define MCPWM_FH2_F0_OST_S 7 +/** MCPWM_FH2_A_CBC_D : R/W; bitpos: [9:8]; default: 0; + * Cycle-by-cycle mode action on PWM2A when fault event occurs and timer is + * decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_FH2_A_CBC_D 0x00000003U +#define MCPWM_FH2_A_CBC_D_M (MCPWM_FH2_A_CBC_D_V << MCPWM_FH2_A_CBC_D_S) +#define MCPWM_FH2_A_CBC_D_V 0x00000003U +#define MCPWM_FH2_A_CBC_D_S 8 +/** MCPWM_FH2_A_CBC_U : R/W; bitpos: [11:10]; default: 0; + * Cycle-by-cycle mode action on PWM2A when fault event occurs and timer is + * increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_FH2_A_CBC_U 0x00000003U +#define MCPWM_FH2_A_CBC_U_M (MCPWM_FH2_A_CBC_U_V << MCPWM_FH2_A_CBC_U_S) +#define MCPWM_FH2_A_CBC_U_V 0x00000003U +#define MCPWM_FH2_A_CBC_U_S 10 +/** MCPWM_FH2_A_OST_D : R/W; bitpos: [13:12]; default: 0; + * One-shot mode action on PWM2A when fault event occurs and timer is decreasing. 0: + * do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_FH2_A_OST_D 0x00000003U +#define MCPWM_FH2_A_OST_D_M (MCPWM_FH2_A_OST_D_V << MCPWM_FH2_A_OST_D_S) +#define MCPWM_FH2_A_OST_D_V 0x00000003U +#define MCPWM_FH2_A_OST_D_S 12 +/** MCPWM_FH2_A_OST_U : R/W; bitpos: [15:14]; default: 0; + * One-shot mode action on PWM2A when fault event occurs and timer is increasing. 0: + * do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_FH2_A_OST_U 0x00000003U +#define MCPWM_FH2_A_OST_U_M (MCPWM_FH2_A_OST_U_V << MCPWM_FH2_A_OST_U_S) +#define MCPWM_FH2_A_OST_U_V 0x00000003U +#define MCPWM_FH2_A_OST_U_S 14 +/** MCPWM_FH2_B_CBC_D : R/W; bitpos: [17:16]; default: 0; + * Cycle-by-cycle mode action on PWM2B when fault event occurs and timer is + * decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_FH2_B_CBC_D 0x00000003U +#define MCPWM_FH2_B_CBC_D_M (MCPWM_FH2_B_CBC_D_V << MCPWM_FH2_B_CBC_D_S) +#define MCPWM_FH2_B_CBC_D_V 0x00000003U +#define MCPWM_FH2_B_CBC_D_S 16 +/** MCPWM_FH2_B_CBC_U : R/W; bitpos: [19:18]; default: 0; + * Cycle-by-cycle mode action on PWM2B when fault event occurs and timer is + * increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_FH2_B_CBC_U 0x00000003U +#define MCPWM_FH2_B_CBC_U_M (MCPWM_FH2_B_CBC_U_V << MCPWM_FH2_B_CBC_U_S) +#define MCPWM_FH2_B_CBC_U_V 0x00000003U +#define MCPWM_FH2_B_CBC_U_S 18 +/** MCPWM_FH2_B_OST_D : R/W; bitpos: [21:20]; default: 0; + * One-shot mode action on PWM2B when fault event occurs and timer is decreasing. 0: + * do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_FH2_B_OST_D 0x00000003U +#define MCPWM_FH2_B_OST_D_M (MCPWM_FH2_B_OST_D_V << MCPWM_FH2_B_OST_D_S) +#define MCPWM_FH2_B_OST_D_V 0x00000003U +#define MCPWM_FH2_B_OST_D_S 20 +/** MCPWM_FH2_B_OST_U : R/W; bitpos: [23:22]; default: 0; + * One-shot mode action on PWM2B when fault event occurs and timer is increasing. 0: + * do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_FH2_B_OST_U 0x00000003U +#define MCPWM_FH2_B_OST_U_M (MCPWM_FH2_B_OST_U_V << MCPWM_FH2_B_OST_U_S) +#define MCPWM_FH2_B_OST_U_V 0x00000003U +#define MCPWM_FH2_B_OST_U_S 22 -#define MCPWM_FH2_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0x00dc) -/* MCPWM_FH2_FORCE_OST : R/W ;bitpos:[4] ;default: 1'd0 ; */ -/*description: A toggle (software negation of value of this bit) triggers a - one-shot mode action*/ -#define MCPWM_FH2_FORCE_OST (BIT(4)) -#define MCPWM_FH2_FORCE_OST_M (BIT(4)) -#define MCPWM_FH2_FORCE_OST_V 0x1 -#define MCPWM_FH2_FORCE_OST_S 4 -/* MCPWM_FH2_FORCE_CBC : R/W ;bitpos:[3] ;default: 1'd0 ; */ -/*description: A toggle triggers a cycle-by-cycle mode action*/ -#define MCPWM_FH2_FORCE_CBC (BIT(3)) -#define MCPWM_FH2_FORCE_CBC_M (BIT(3)) -#define MCPWM_FH2_FORCE_CBC_V 0x1 -#define MCPWM_FH2_FORCE_CBC_S 3 -/* MCPWM_FH2_CBCPULSE : R/W ;bitpos:[2:1] ;default: 2'd0 ; */ -/*description: The cycle-by-cycle mode action refresh moment selection. Bit0: TEZ bit1:TEP*/ -#define MCPWM_FH2_CBCPULSE 0x00000003 -#define MCPWM_FH2_CBCPULSE_M ((MCPWM_FH2_CBCPULSE_V)<<(MCPWM_FH2_CBCPULSE_S)) -#define MCPWM_FH2_CBCPULSE_V 0x3 -#define MCPWM_FH2_CBCPULSE_S 1 -/* MCPWM_FH2_CLR_OST : R/W ;bitpos:[0] ;default: 1'd0 ; */ -/*description: A toggle will clear on going one-shot mode action*/ -#define MCPWM_FH2_CLR_OST (BIT(0)) -#define MCPWM_FH2_CLR_OST_M (BIT(0)) -#define MCPWM_FH2_CLR_OST_V 0x1 +/** MCPWM_FH2_CFG1_REG register + * Software triggers for fault handler actions + */ +#define MCPWM_FH2_CFG1_REG(i) (DR_REG_MCPWM_BASE(i) + 0xdc) +/** MCPWM_FH2_CLR_OST : R/W; bitpos: [0]; default: 0; + * a rising edge will clear on going one-shot mode action + */ +#define MCPWM_FH2_CLR_OST (BIT(0)) +#define MCPWM_FH2_CLR_OST_M (MCPWM_FH2_CLR_OST_V << MCPWM_FH2_CLR_OST_S) +#define MCPWM_FH2_CLR_OST_V 0x00000001U #define MCPWM_FH2_CLR_OST_S 0 +/** MCPWM_FH2_CBCPULSE : R/W; bitpos: [2:1]; default: 0; + * cycle-by-cycle mode action refresh moment selection. When bit0 is set to 1: TEZ, + * when bit1 is set to 1:TEP + */ +#define MCPWM_FH2_CBCPULSE 0x00000003U +#define MCPWM_FH2_CBCPULSE_M (MCPWM_FH2_CBCPULSE_V << MCPWM_FH2_CBCPULSE_S) +#define MCPWM_FH2_CBCPULSE_V 0x00000003U +#define MCPWM_FH2_CBCPULSE_S 1 +/** MCPWM_FH2_FORCE_CBC : R/W; bitpos: [3]; default: 0; + * a toggle trigger a cycle-by-cycle mode action + */ +#define MCPWM_FH2_FORCE_CBC (BIT(3)) +#define MCPWM_FH2_FORCE_CBC_M (MCPWM_FH2_FORCE_CBC_V << MCPWM_FH2_FORCE_CBC_S) +#define MCPWM_FH2_FORCE_CBC_V 0x00000001U +#define MCPWM_FH2_FORCE_CBC_S 3 +/** MCPWM_FH2_FORCE_OST : R/W; bitpos: [4]; default: 0; + * a toggle (software negate its value) triggers a one-shot mode action + */ +#define MCPWM_FH2_FORCE_OST (BIT(4)) +#define MCPWM_FH2_FORCE_OST_M (MCPWM_FH2_FORCE_OST_V << MCPWM_FH2_FORCE_OST_S) +#define MCPWM_FH2_FORCE_OST_V 0x00000001U +#define MCPWM_FH2_FORCE_OST_S 4 -#define MCPWM_FH2_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x00e0) -/* MCPWM_FH2_OST_ON : RO ;bitpos:[1] ;default: 1'd0 ; */ -/*description: Set and reset by hardware. If set an one-shot mode action is on going*/ -#define MCPWM_FH2_OST_ON (BIT(1)) -#define MCPWM_FH2_OST_ON_M (BIT(1)) -#define MCPWM_FH2_OST_ON_V 0x1 -#define MCPWM_FH2_OST_ON_S 1 -/* MCPWM_FH2_CBC_ON : RO ;bitpos:[0] ;default: 1'd0 ; */ -/*description: Set and reset by hardware. If set an cycle-by-cycle mode action is on going*/ -#define MCPWM_FH2_CBC_ON (BIT(0)) -#define MCPWM_FH2_CBC_ON_M (BIT(0)) -#define MCPWM_FH2_CBC_ON_V 0x1 +/** MCPWM_FH2_STATUS_REG register + * Status of fault events. + */ +#define MCPWM_FH2_STATUS_REG(i) (DR_REG_MCPWM_BASE(i) + 0xe0) +/** MCPWM_FH2_CBC_ON : RO; bitpos: [0]; default: 0; + * Set and reset by hardware. If set, a cycle-by-cycle mode action is on going + */ +#define MCPWM_FH2_CBC_ON (BIT(0)) +#define MCPWM_FH2_CBC_ON_M (MCPWM_FH2_CBC_ON_V << MCPWM_FH2_CBC_ON_S) +#define MCPWM_FH2_CBC_ON_V 0x00000001U #define MCPWM_FH2_CBC_ON_S 0 +/** MCPWM_FH2_OST_ON : RO; bitpos: [1]; default: 0; + * Set and reset by hardware. If set, an one-shot mode action is on going + */ +#define MCPWM_FH2_OST_ON (BIT(1)) +#define MCPWM_FH2_OST_ON_M (MCPWM_FH2_OST_ON_V << MCPWM_FH2_OST_ON_S) +#define MCPWM_FH2_OST_ON_V 0x00000001U +#define MCPWM_FH2_OST_ON_S 1 -#define MCPWM_FAULT_DETECT_REG(i) (REG_MCPWM_BASE(i) + 0x00e4) -/* MCPWM_EVENT_F2 : RO ;bitpos:[8] ;default: 1'd0 ; */ -/*description: Set and reset by hardware. If set event_f2 is on going*/ -#define MCPWM_EVENT_F2 (BIT(8)) -#define MCPWM_EVENT_F2_M (BIT(8)) -#define MCPWM_EVENT_F2_V 0x1 -#define MCPWM_EVENT_F2_S 8 -/* MCPWM_EVENT_F1 : RO ;bitpos:[7] ;default: 1'd0 ; */ -/*description: Set and reset by hardware. If set event_f1 is on going*/ -#define MCPWM_EVENT_F1 (BIT(7)) -#define MCPWM_EVENT_F1_M (BIT(7)) -#define MCPWM_EVENT_F1_V 0x1 -#define MCPWM_EVENT_F1_S 7 -/* MCPWM_EVENT_F0 : RO ;bitpos:[6] ;default: 1'd0 ; */ -/*description: Set and reset by hardware. If set event_f0 is on going*/ -#define MCPWM_EVENT_F0 (BIT(6)) -#define MCPWM_EVENT_F0_M (BIT(6)) -#define MCPWM_EVENT_F0_V 0x1 -#define MCPWM_EVENT_F0_S 6 -/* MCPWM_F2_POLE : R/W ;bitpos:[5] ;default: 1'd0 ; */ -/*description: Set event_f2 trigger polarity on FAULT2 source from GPIO matrix. - 0: level low 1: level high*/ -#define MCPWM_F2_POLE (BIT(5)) -#define MCPWM_F2_POLE_M (BIT(5)) -#define MCPWM_F2_POLE_V 0x1 -#define MCPWM_F2_POLE_S 5 -/* MCPWM_F1_POLE : R/W ;bitpos:[4] ;default: 1'd0 ; */ -/*description: Set event_f1 trigger polarity on FAULT2 source from GPIO matrix. - 0: level low 1: level high*/ -#define MCPWM_F1_POLE (BIT(4)) -#define MCPWM_F1_POLE_M (BIT(4)) -#define MCPWM_F1_POLE_V 0x1 -#define MCPWM_F1_POLE_S 4 -/* MCPWM_F0_POLE : R/W ;bitpos:[3] ;default: 1'd0 ; */ -/*description: Set event_f0 trigger polarity on FAULT2 source from GPIO matrix. - 0: level low 1: level high*/ -#define MCPWM_F0_POLE (BIT(3)) -#define MCPWM_F0_POLE_M (BIT(3)) -#define MCPWM_F0_POLE_V 0x1 -#define MCPWM_F0_POLE_S 3 -/* MCPWM_F2_EN : R/W ;bitpos:[2] ;default: 1'd0 ; */ -/*description: Set to enable generation of event_f2*/ -#define MCPWM_F2_EN (BIT(2)) -#define MCPWM_F2_EN_M (BIT(2)) -#define MCPWM_F2_EN_V 0x1 -#define MCPWM_F2_EN_S 2 -/* MCPWM_F1_EN : R/W ;bitpos:[1] ;default: 1'd0 ; */ -/*description: Set to enable generation of event_f1*/ -#define MCPWM_F1_EN (BIT(1)) -#define MCPWM_F1_EN_M (BIT(1)) -#define MCPWM_F1_EN_V 0x1 -#define MCPWM_F1_EN_S 1 -/* MCPWM_F0_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */ -/*description: Set to enable generation of event_f0*/ -#define MCPWM_F0_EN (BIT(0)) -#define MCPWM_F0_EN_M (BIT(0)) -#define MCPWM_F0_EN_V 0x1 +/** MCPWM_FAULT_DETECT_REG register + * Fault detection configuration and status + */ +#define MCPWM_FAULT_DETECT_REG(i) (DR_REG_MCPWM_BASE(i) + 0xe4) +/** MCPWM_F0_EN : R/W; bitpos: [0]; default: 0; + * When set, fault_event0 generation is enabled + */ +#define MCPWM_F0_EN (BIT(0)) +#define MCPWM_F0_EN_M (MCPWM_F0_EN_V << MCPWM_F0_EN_S) +#define MCPWM_F0_EN_V 0x00000001U #define MCPWM_F0_EN_S 0 +/** MCPWM_F1_EN : R/W; bitpos: [1]; default: 0; + * When set, fault_event1 generation is enabled + */ +#define MCPWM_F1_EN (BIT(1)) +#define MCPWM_F1_EN_M (MCPWM_F1_EN_V << MCPWM_F1_EN_S) +#define MCPWM_F1_EN_V 0x00000001U +#define MCPWM_F1_EN_S 1 +/** MCPWM_F2_EN : R/W; bitpos: [2]; default: 0; + * When set, fault_event2 generation is enabled + */ +#define MCPWM_F2_EN (BIT(2)) +#define MCPWM_F2_EN_M (MCPWM_F2_EN_V << MCPWM_F2_EN_S) +#define MCPWM_F2_EN_V 0x00000001U +#define MCPWM_F2_EN_S 2 +/** MCPWM_F0_POLE : R/W; bitpos: [3]; default: 0; + * Set fault_event0 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, + * 1: level high + */ +#define MCPWM_F0_POLE (BIT(3)) +#define MCPWM_F0_POLE_M (MCPWM_F0_POLE_V << MCPWM_F0_POLE_S) +#define MCPWM_F0_POLE_V 0x00000001U +#define MCPWM_F0_POLE_S 3 +/** MCPWM_F1_POLE : R/W; bitpos: [4]; default: 0; + * Set fault_event1 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, + * 1: level high + */ +#define MCPWM_F1_POLE (BIT(4)) +#define MCPWM_F1_POLE_M (MCPWM_F1_POLE_V << MCPWM_F1_POLE_S) +#define MCPWM_F1_POLE_V 0x00000001U +#define MCPWM_F1_POLE_S 4 +/** MCPWM_F2_POLE : R/W; bitpos: [5]; default: 0; + * Set fault_event2 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, + * 1: level high + */ +#define MCPWM_F2_POLE (BIT(5)) +#define MCPWM_F2_POLE_M (MCPWM_F2_POLE_V << MCPWM_F2_POLE_S) +#define MCPWM_F2_POLE_V 0x00000001U +#define MCPWM_F2_POLE_S 5 +/** MCPWM_EVENT_F0 : RO; bitpos: [6]; default: 0; + * Set and reset by hardware. If set, fault_event0 is on going + */ +#define MCPWM_EVENT_F0 (BIT(6)) +#define MCPWM_EVENT_F0_M (MCPWM_EVENT_F0_V << MCPWM_EVENT_F0_S) +#define MCPWM_EVENT_F0_V 0x00000001U +#define MCPWM_EVENT_F0_S 6 +/** MCPWM_EVENT_F1 : RO; bitpos: [7]; default: 0; + * Set and reset by hardware. If set, fault_event1 is on going + */ +#define MCPWM_EVENT_F1 (BIT(7)) +#define MCPWM_EVENT_F1_M (MCPWM_EVENT_F1_V << MCPWM_EVENT_F1_S) +#define MCPWM_EVENT_F1_V 0x00000001U +#define MCPWM_EVENT_F1_S 7 +/** MCPWM_EVENT_F2 : RO; bitpos: [8]; default: 0; + * Set and reset by hardware. If set, fault_event2 is on going + */ +#define MCPWM_EVENT_F2 (BIT(8)) +#define MCPWM_EVENT_F2_M (MCPWM_EVENT_F2_V << MCPWM_EVENT_F2_S) +#define MCPWM_EVENT_F2_V 0x00000001U +#define MCPWM_EVENT_F2_S 8 -#define MCPWM_CAP_TIMER_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x00e8) -/* MCPWM_CAP_SYNC_SW : WO ;bitpos:[5] ;default: 1'd0 ; */ -/*description: Set this bit to force a capture timer sync capture timer is - loaded with value in phase register.*/ -#define MCPWM_CAP_SYNC_SW (BIT(5)) -#define MCPWM_CAP_SYNC_SW_M (BIT(5)) -#define MCPWM_CAP_SYNC_SW_V 0x1 -#define MCPWM_CAP_SYNC_SW_S 5 -/* MCPWM_CAP_SYNCI_SEL : R/W ;bitpos:[4:2] ;default: 3'd0 ; */ -/*description: Capture module sync input selection. 0: none 1: timer0 synco - 2: timer1 synco 3: timer2 synco 4: SYNC0 from GPIO matrix 5: SYNC1 from GPIO matrix 6: SYNC2 from GPIO matrix*/ -#define MCPWM_CAP_SYNCI_SEL 0x00000007 -#define MCPWM_CAP_SYNCI_SEL_M ((MCPWM_CAP_SYNCI_SEL_V)<<(MCPWM_CAP_SYNCI_SEL_S)) -#define MCPWM_CAP_SYNCI_SEL_V 0x7 -#define MCPWM_CAP_SYNCI_SEL_S 2 -/* MCPWM_CAP_SYNCI_EN : R/W ;bitpos:[1] ;default: 1'd0 ; */ -/*description: When set capture timer sync is enabled.*/ -#define MCPWM_CAP_SYNCI_EN (BIT(1)) -#define MCPWM_CAP_SYNCI_EN_M (BIT(1)) -#define MCPWM_CAP_SYNCI_EN_V 0x1 -#define MCPWM_CAP_SYNCI_EN_S 1 -/* MCPWM_CAP_TIMER_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */ -/*description: When set capture timer incrementing under APB_clk is enabled.*/ -#define MCPWM_CAP_TIMER_EN (BIT(0)) -#define MCPWM_CAP_TIMER_EN_M (BIT(0)) -#define MCPWM_CAP_TIMER_EN_V 0x1 +/** MCPWM_CAP_TIMER_CFG_REG register + * Configure capture timer + */ +#define MCPWM_CAP_TIMER_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0xe8) +/** MCPWM_CAP_TIMER_EN : R/W; bitpos: [0]; default: 0; + * When set, capture timer incrementing under APB_clk is enabled. + */ +#define MCPWM_CAP_TIMER_EN (BIT(0)) +#define MCPWM_CAP_TIMER_EN_M (MCPWM_CAP_TIMER_EN_V << MCPWM_CAP_TIMER_EN_S) +#define MCPWM_CAP_TIMER_EN_V 0x00000001U #define MCPWM_CAP_TIMER_EN_S 0 +/** MCPWM_CAP_SYNCI_EN : R/W; bitpos: [1]; default: 0; + * When set, capture timer sync is enabled. + */ +#define MCPWM_CAP_SYNCI_EN (BIT(1)) +#define MCPWM_CAP_SYNCI_EN_M (MCPWM_CAP_SYNCI_EN_V << MCPWM_CAP_SYNCI_EN_S) +#define MCPWM_CAP_SYNCI_EN_V 0x00000001U +#define MCPWM_CAP_SYNCI_EN_S 1 +/** MCPWM_CAP_SYNCI_SEL : R/W; bitpos: [4:2]; default: 0; + * capture module sync input selection. 0: none, 1: timer0 sync_out, 2: timer1 + * sync_out, 3: timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, + * 6: SYNC2 from GPIO matrix + */ +#define MCPWM_CAP_SYNCI_SEL 0x00000007U +#define MCPWM_CAP_SYNCI_SEL_M (MCPWM_CAP_SYNCI_SEL_V << MCPWM_CAP_SYNCI_SEL_S) +#define MCPWM_CAP_SYNCI_SEL_V 0x00000007U +#define MCPWM_CAP_SYNCI_SEL_S 2 +/** MCPWM_CAP_SYNC_SW : WT; bitpos: [5]; default: 0; + * When reg_cap_synci_en is 1, write 1 will trigger a capture timer sync, capture + * timer is loaded with value in phase register. + */ +#define MCPWM_CAP_SYNC_SW (BIT(5)) +#define MCPWM_CAP_SYNC_SW_M (MCPWM_CAP_SYNC_SW_V << MCPWM_CAP_SYNC_SW_S) +#define MCPWM_CAP_SYNC_SW_V 0x00000001U +#define MCPWM_CAP_SYNC_SW_S 5 -#define MCPWM_CAP_TIMER_PHASE_REG(i) (REG_MCPWM_BASE(i) + 0x00ec) -/* MCPWM_CAP_PHASE : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: Phase value for capture timer sync operation.*/ -#define MCPWM_CAP_PHASE 0xFFFFFFFF -#define MCPWM_CAP_PHASE_M ((MCPWM_CAP_PHASE_V)<<(MCPWM_CAP_PHASE_S)) -#define MCPWM_CAP_PHASE_V 0xFFFFFFFF -#define MCPWM_CAP_PHASE_S 0 - -#define MCPWM_CAP_CH0_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x00f0) -/* MCPWM_CAP0_SW : WO ;bitpos:[12] ;default: 1'd0 ; */ -/*description: Write 1 will trigger a software forced capture on channel 0*/ -#define MCPWM_CAP0_SW (BIT(12)) -#define MCPWM_CAP0_SW_M (BIT(12)) -#define MCPWM_CAP0_SW_V 0x1 -#define MCPWM_CAP0_SW_S 12 -/* MCPWM_CAP0_IN_INVERT : R/W ;bitpos:[11] ;default: 1'd0 ; */ -/*description: When set CAP0 form GPIO matrix is inverted before prescale*/ -#define MCPWM_CAP0_IN_INVERT (BIT(11)) -#define MCPWM_CAP0_IN_INVERT_M (BIT(11)) -#define MCPWM_CAP0_IN_INVERT_V 0x1 -#define MCPWM_CAP0_IN_INVERT_S 11 -/* MCPWM_CAP0_PRESCALE : R/W ;bitpos:[10:3] ;default: 8'd0 ; */ -/*description: Value of prescale on possitive edge of CAP0. Prescale value = - PWM_CAP0_PRESCALE + 1*/ -#define MCPWM_CAP0_PRESCALE 0x000000FF -#define MCPWM_CAP0_PRESCALE_M ((MCPWM_CAP0_PRESCALE_V)<<(MCPWM_CAP0_PRESCALE_S)) -#define MCPWM_CAP0_PRESCALE_V 0xFF -#define MCPWM_CAP0_PRESCALE_S 3 -/* MCPWM_CAP0_MODE : R/W ;bitpos:[2:1] ;default: 2'd0 ; */ -/*description: Edge of capture on channel 0 after prescale. bit0: negedge cap - en bit1: posedge cap en*/ -#define MCPWM_CAP0_MODE 0x00000003 -#define MCPWM_CAP0_MODE_M ((MCPWM_CAP0_MODE_V)<<(MCPWM_CAP0_MODE_S)) -#define MCPWM_CAP0_MODE_V 0x3 -#define MCPWM_CAP0_MODE_S 1 -/* MCPWM_CAP0_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */ -/*description: When set capture on channel 0 is enabled*/ -#define MCPWM_CAP0_EN (BIT(0)) -#define MCPWM_CAP0_EN_M (BIT(0)) -#define MCPWM_CAP0_EN_V 0x1 +/** MCPWM_CAP_TIMER_PHASE_REG register + * Phase for capture timer sync + */ +#define MCPWM_CAP_TIMER_PHASE_REG(i) (DR_REG_MCPWM_BASE(i) + 0xec) +/** MCPWM_CAP_TIMER_PHASE : R/W; bitpos: [31:0]; default: 0; + * Phase value for capture timer sync operation. + */ +#define MCPWM_CAP_TIMER_PHASE 0xFFFFFFFFU +#define MCPWM_CAP_TIMER_PHASE_M (MCPWM_CAP_TIMER_PHASE_V << MCPWM_CAP_TIMER_PHASE_S) +#define MCPWM_CAP_TIMER_PHASE_V 0xFFFFFFFFU +#define MCPWM_CAP_TIMER_PHASE_S 0 + +/** MCPWM_CAP_CH0_CFG_REG register + * Capture channel 0 configuration and enable + */ +#define MCPWM_CAP_CH0_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0xf0) +/** MCPWM_CAP0_EN : R/W; bitpos: [0]; default: 0; + * When set, capture on channel 0 is enabled + */ +#define MCPWM_CAP0_EN (BIT(0)) +#define MCPWM_CAP0_EN_M (MCPWM_CAP0_EN_V << MCPWM_CAP0_EN_S) +#define MCPWM_CAP0_EN_V 0x00000001U #define MCPWM_CAP0_EN_S 0 +/** MCPWM_CAP0_MODE : R/W; bitpos: [2:1]; default: 0; + * Edge of capture on channel 0 after prescaling. When bit0 is set to 1: enable + * capture on the negative edge, When bit1 is set to 1: enable capture on the positive + * edge. + */ +#define MCPWM_CAP0_MODE 0x00000003U +#define MCPWM_CAP0_MODE_M (MCPWM_CAP0_MODE_V << MCPWM_CAP0_MODE_S) +#define MCPWM_CAP0_MODE_V 0x00000003U +#define MCPWM_CAP0_MODE_S 1 +/** MCPWM_CAP0_PRESCALE : R/W; bitpos: [10:3]; default: 0; + * Value of prescaling on possitive edge of CAP0. Prescale value = PWM_CAP0_PRESCALE + + * 1 + */ +#define MCPWM_CAP0_PRESCALE 0x000000FFU +#define MCPWM_CAP0_PRESCALE_M (MCPWM_CAP0_PRESCALE_V << MCPWM_CAP0_PRESCALE_S) +#define MCPWM_CAP0_PRESCALE_V 0x000000FFU +#define MCPWM_CAP0_PRESCALE_S 3 +/** MCPWM_CAP0_IN_INVERT : R/W; bitpos: [11]; default: 0; + * when set, CAP0 form GPIO matrix is inverted before prescale + */ +#define MCPWM_CAP0_IN_INVERT (BIT(11)) +#define MCPWM_CAP0_IN_INVERT_M (MCPWM_CAP0_IN_INVERT_V << MCPWM_CAP0_IN_INVERT_S) +#define MCPWM_CAP0_IN_INVERT_V 0x00000001U +#define MCPWM_CAP0_IN_INVERT_S 11 +/** MCPWM_CAP0_SW : WT; bitpos: [12]; default: 0; + * Write 1 will trigger a software forced capture on channel 0 + */ +#define MCPWM_CAP0_SW (BIT(12)) +#define MCPWM_CAP0_SW_M (MCPWM_CAP0_SW_V << MCPWM_CAP0_SW_S) +#define MCPWM_CAP0_SW_V 0x00000001U +#define MCPWM_CAP0_SW_S 12 -#define MCPWM_CAP_CH1_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x00f4) -/* MCPWM_CAP1_SW : WO ;bitpos:[12] ;default: 1'd0 ; */ -/*description: Write 1 will trigger a software forced capture on channel 1*/ -#define MCPWM_CAP1_SW (BIT(12)) -#define MCPWM_CAP1_SW_M (BIT(12)) -#define MCPWM_CAP1_SW_V 0x1 -#define MCPWM_CAP1_SW_S 12 -/* MCPWM_CAP1_IN_INVERT : R/W ;bitpos:[11] ;default: 1'd0 ; */ -/*description: When set CAP1 form GPIO matrix is inverted before prescale*/ -#define MCPWM_CAP1_IN_INVERT (BIT(11)) -#define MCPWM_CAP1_IN_INVERT_M (BIT(11)) -#define MCPWM_CAP1_IN_INVERT_V 0x1 -#define MCPWM_CAP1_IN_INVERT_S 11 -/* MCPWM_CAP1_PRESCALE : R/W ;bitpos:[10:3] ;default: 8'd0 ; */ -/*description: Value of prescale on possitive edge of CAP1. Prescale value = - PWM_CAP1_PRESCALE + 1*/ -#define MCPWM_CAP1_PRESCALE 0x000000FF -#define MCPWM_CAP1_PRESCALE_M ((MCPWM_CAP1_PRESCALE_V)<<(MCPWM_CAP1_PRESCALE_S)) -#define MCPWM_CAP1_PRESCALE_V 0xFF -#define MCPWM_CAP1_PRESCALE_S 3 -/* MCPWM_CAP1_MODE : R/W ;bitpos:[2:1] ;default: 2'd0 ; */ -/*description: Edge of capture on channel 1 after prescale. bit0: negedge cap - en bit1: posedge cap en*/ -#define MCPWM_CAP1_MODE 0x00000003 -#define MCPWM_CAP1_MODE_M ((MCPWM_CAP1_MODE_V)<<(MCPWM_CAP1_MODE_S)) -#define MCPWM_CAP1_MODE_V 0x3 -#define MCPWM_CAP1_MODE_S 1 -/* MCPWM_CAP1_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */ -/*description: When set capture on channel 1 is enabled*/ -#define MCPWM_CAP1_EN (BIT(0)) -#define MCPWM_CAP1_EN_M (BIT(0)) -#define MCPWM_CAP1_EN_V 0x1 +/** MCPWM_CAP_CH1_CFG_REG register + * Capture channel 1 configuration and enable + */ +#define MCPWM_CAP_CH1_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0xf4) +/** MCPWM_CAP1_EN : R/W; bitpos: [0]; default: 0; + * When set, capture on channel 2 is enabled + */ +#define MCPWM_CAP1_EN (BIT(0)) +#define MCPWM_CAP1_EN_M (MCPWM_CAP1_EN_V << MCPWM_CAP1_EN_S) +#define MCPWM_CAP1_EN_V 0x00000001U #define MCPWM_CAP1_EN_S 0 +/** MCPWM_CAP1_MODE : R/W; bitpos: [2:1]; default: 0; + * Edge of capture on channel 1 after prescaling. When bit0 is set to 1: enable + * capture on the negative edge, When bit1 is set to 1: enable capture on the positive + * edge. + */ +#define MCPWM_CAP1_MODE 0x00000003U +#define MCPWM_CAP1_MODE_M (MCPWM_CAP1_MODE_V << MCPWM_CAP1_MODE_S) +#define MCPWM_CAP1_MODE_V 0x00000003U +#define MCPWM_CAP1_MODE_S 1 +/** MCPWM_CAP1_PRESCALE : R/W; bitpos: [10:3]; default: 0; + * Value of prescaling on possitive edge of CAP1. Prescale value = PWM_CAP1_PRESCALE + + * 1 + */ +#define MCPWM_CAP1_PRESCALE 0x000000FFU +#define MCPWM_CAP1_PRESCALE_M (MCPWM_CAP1_PRESCALE_V << MCPWM_CAP1_PRESCALE_S) +#define MCPWM_CAP1_PRESCALE_V 0x000000FFU +#define MCPWM_CAP1_PRESCALE_S 3 +/** MCPWM_CAP1_IN_INVERT : R/W; bitpos: [11]; default: 0; + * when set, CAP1 form GPIO matrix is inverted before prescale + */ +#define MCPWM_CAP1_IN_INVERT (BIT(11)) +#define MCPWM_CAP1_IN_INVERT_M (MCPWM_CAP1_IN_INVERT_V << MCPWM_CAP1_IN_INVERT_S) +#define MCPWM_CAP1_IN_INVERT_V 0x00000001U +#define MCPWM_CAP1_IN_INVERT_S 11 +/** MCPWM_CAP1_SW : WT; bitpos: [12]; default: 0; + * Write 1 will trigger a software forced capture on channel 1 + */ +#define MCPWM_CAP1_SW (BIT(12)) +#define MCPWM_CAP1_SW_M (MCPWM_CAP1_SW_V << MCPWM_CAP1_SW_S) +#define MCPWM_CAP1_SW_V 0x00000001U +#define MCPWM_CAP1_SW_S 12 -#define MCPWM_CAP_CH2_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x00f8) -/* MCPWM_CAP2_SW : WO ;bitpos:[12] ;default: 1'd0 ; */ -/*description: Write 1 will trigger a software forced capture on channel 2*/ -#define MCPWM_CAP2_SW (BIT(12)) -#define MCPWM_CAP2_SW_M (BIT(12)) -#define MCPWM_CAP2_SW_V 0x1 -#define MCPWM_CAP2_SW_S 12 -/* MCPWM_CAP2_IN_INVERT : R/W ;bitpos:[11] ;default: 1'd0 ; */ -/*description: When set CAP2 form GPIO matrix is inverted before prescale*/ -#define MCPWM_CAP2_IN_INVERT (BIT(11)) -#define MCPWM_CAP2_IN_INVERT_M (BIT(11)) -#define MCPWM_CAP2_IN_INVERT_V 0x1 -#define MCPWM_CAP2_IN_INVERT_S 11 -/* MCPWM_CAP2_PRESCALE : R/W ;bitpos:[10:3] ;default: 8'd0 ; */ -/*description: Value of prescale on possitive edge of CAP2. Prescale value = - PWM_CAP2_PRESCALE + 1*/ -#define MCPWM_CAP2_PRESCALE 0x000000FF -#define MCPWM_CAP2_PRESCALE_M ((MCPWM_CAP2_PRESCALE_V)<<(MCPWM_CAP2_PRESCALE_S)) -#define MCPWM_CAP2_PRESCALE_V 0xFF -#define MCPWM_CAP2_PRESCALE_S 3 -/* MCPWM_CAP2_MODE : R/W ;bitpos:[2:1] ;default: 2'd0 ; */ -/*description: Edge of capture on channel 2 after prescale. bit0: negedge cap - en bit1: posedge cap en*/ -#define MCPWM_CAP2_MODE 0x00000003 -#define MCPWM_CAP2_MODE_M ((MCPWM_CAP2_MODE_V)<<(MCPWM_CAP2_MODE_S)) -#define MCPWM_CAP2_MODE_V 0x3 -#define MCPWM_CAP2_MODE_S 1 -/* MCPWM_CAP2_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */ -/*description: When set capture on channel 2 is enabled*/ -#define MCPWM_CAP2_EN (BIT(0)) -#define MCPWM_CAP2_EN_M (BIT(0)) -#define MCPWM_CAP2_EN_V 0x1 +/** MCPWM_CAP_CH2_CFG_REG register + * Capture channel 2 configuration and enable + */ +#define MCPWM_CAP_CH2_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0xf8) +/** MCPWM_CAP2_EN : R/W; bitpos: [0]; default: 0; + * When set, capture on channel 2 is enabled + */ +#define MCPWM_CAP2_EN (BIT(0)) +#define MCPWM_CAP2_EN_M (MCPWM_CAP2_EN_V << MCPWM_CAP2_EN_S) +#define MCPWM_CAP2_EN_V 0x00000001U #define MCPWM_CAP2_EN_S 0 +/** MCPWM_CAP2_MODE : R/W; bitpos: [2:1]; default: 0; + * Edge of capture on channel 2 after prescaling. When bit0 is set to 1: enable + * capture on the negative edge, When bit1 is set to 1: enable capture on the positive + * edge. + */ +#define MCPWM_CAP2_MODE 0x00000003U +#define MCPWM_CAP2_MODE_M (MCPWM_CAP2_MODE_V << MCPWM_CAP2_MODE_S) +#define MCPWM_CAP2_MODE_V 0x00000003U +#define MCPWM_CAP2_MODE_S 1 +/** MCPWM_CAP2_PRESCALE : R/W; bitpos: [10:3]; default: 0; + * Value of prescaling on possitive edge of CAP2. Prescale value = PWM_CAP2_PRESCALE + + * 1 + */ +#define MCPWM_CAP2_PRESCALE 0x000000FFU +#define MCPWM_CAP2_PRESCALE_M (MCPWM_CAP2_PRESCALE_V << MCPWM_CAP2_PRESCALE_S) +#define MCPWM_CAP2_PRESCALE_V 0x000000FFU +#define MCPWM_CAP2_PRESCALE_S 3 +/** MCPWM_CAP2_IN_INVERT : R/W; bitpos: [11]; default: 0; + * when set, CAP2 form GPIO matrix is inverted before prescale + */ +#define MCPWM_CAP2_IN_INVERT (BIT(11)) +#define MCPWM_CAP2_IN_INVERT_M (MCPWM_CAP2_IN_INVERT_V << MCPWM_CAP2_IN_INVERT_S) +#define MCPWM_CAP2_IN_INVERT_V 0x00000001U +#define MCPWM_CAP2_IN_INVERT_S 11 +/** MCPWM_CAP2_SW : WT; bitpos: [12]; default: 0; + * Write 1 will trigger a software forced capture on channel 2 + */ +#define MCPWM_CAP2_SW (BIT(12)) +#define MCPWM_CAP2_SW_M (MCPWM_CAP2_SW_V << MCPWM_CAP2_SW_S) +#define MCPWM_CAP2_SW_V 0x00000001U +#define MCPWM_CAP2_SW_S 12 -#define MCPWM_CAP_CH0_REG(i) (REG_MCPWM_BASE(i) + 0x00fc) -/* MCPWM_CAP0_VALUE : RO ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: Value of last capture on channel 0*/ -#define MCPWM_CAP0_VALUE 0xFFFFFFFF -#define MCPWM_CAP0_VALUE_M ((MCPWM_CAP0_VALUE_V)<<(MCPWM_CAP0_VALUE_S)) -#define MCPWM_CAP0_VALUE_V 0xFFFFFFFF +/** MCPWM_CAP_CH0_REG register + * ch0 capture value status register + */ +#define MCPWM_CAP_CH0_REG(i) (DR_REG_MCPWM_BASE(i) + 0xfc) +/** MCPWM_CAP0_VALUE : RO; bitpos: [31:0]; default: 0; + * Value of last capture on channel 0 + */ +#define MCPWM_CAP0_VALUE 0xFFFFFFFFU +#define MCPWM_CAP0_VALUE_M (MCPWM_CAP0_VALUE_V << MCPWM_CAP0_VALUE_S) +#define MCPWM_CAP0_VALUE_V 0xFFFFFFFFU #define MCPWM_CAP0_VALUE_S 0 -#define MCPWM_CAP_CH1_REG(i) (REG_MCPWM_BASE(i) + 0x0100) -/* MCPWM_CAP1_VALUE : RO ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: Value of last capture on channel 1*/ -#define MCPWM_CAP1_VALUE 0xFFFFFFFF -#define MCPWM_CAP1_VALUE_M ((MCPWM_CAP1_VALUE_V)<<(MCPWM_CAP1_VALUE_S)) -#define MCPWM_CAP1_VALUE_V 0xFFFFFFFF +/** MCPWM_CAP_CH1_REG register + * ch1 capture value status register + */ +#define MCPWM_CAP_CH1_REG(i) (DR_REG_MCPWM_BASE(i) + 0x100) +/** MCPWM_CAP1_VALUE : RO; bitpos: [31:0]; default: 0; + * Value of last capture on channel 1 + */ +#define MCPWM_CAP1_VALUE 0xFFFFFFFFU +#define MCPWM_CAP1_VALUE_M (MCPWM_CAP1_VALUE_V << MCPWM_CAP1_VALUE_S) +#define MCPWM_CAP1_VALUE_V 0xFFFFFFFFU #define MCPWM_CAP1_VALUE_S 0 -#define MCPWM_CAP_CH2_REG(i) (REG_MCPWM_BASE(i) + 0x0104) -/* MCPWM_CAP2_VALUE : RO ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: Value of last capture on channel 2*/ -#define MCPWM_CAP2_VALUE 0xFFFFFFFF -#define MCPWM_CAP2_VALUE_M ((MCPWM_CAP2_VALUE_V)<<(MCPWM_CAP2_VALUE_S)) -#define MCPWM_CAP2_VALUE_V 0xFFFFFFFF +/** MCPWM_CAP_CH2_REG register + * ch2 capture value status register + */ +#define MCPWM_CAP_CH2_REG(i) (DR_REG_MCPWM_BASE(i) + 0x104) +/** MCPWM_CAP2_VALUE : RO; bitpos: [31:0]; default: 0; + * Value of last capture on channel 2 + */ +#define MCPWM_CAP2_VALUE 0xFFFFFFFFU +#define MCPWM_CAP2_VALUE_M (MCPWM_CAP2_VALUE_V << MCPWM_CAP2_VALUE_S) +#define MCPWM_CAP2_VALUE_V 0xFFFFFFFFU #define MCPWM_CAP2_VALUE_S 0 -#define MCPWM_CAP_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x0108) -/* MCPWM_CAP2_EDGE : RO ;bitpos:[2] ;default: 1'd0 ; */ -/*description: Edge of last capture trigger on channel 2 0: posedge 1: negedge*/ -#define MCPWM_CAP2_EDGE (BIT(2)) -#define MCPWM_CAP2_EDGE_M (BIT(2)) -#define MCPWM_CAP2_EDGE_V 0x1 -#define MCPWM_CAP2_EDGE_S 2 -/* MCPWM_CAP1_EDGE : RO ;bitpos:[1] ;default: 1'd0 ; */ -/*description: Edge of last capture trigger on channel 1 0: posedge 1: negedge*/ -#define MCPWM_CAP1_EDGE (BIT(1)) -#define MCPWM_CAP1_EDGE_M (BIT(1)) -#define MCPWM_CAP1_EDGE_V 0x1 -#define MCPWM_CAP1_EDGE_S 1 -/* MCPWM_CAP0_EDGE : RO ;bitpos:[0] ;default: 1'd0 ; */ -/*description: Edge of last capture trigger on channel 0 0: posedge 1: negedge*/ -#define MCPWM_CAP0_EDGE (BIT(0)) -#define MCPWM_CAP0_EDGE_M (BIT(0)) -#define MCPWM_CAP0_EDGE_V 0x1 +/** MCPWM_CAP_STATUS_REG register + * Edge of last capture trigger + */ +#define MCPWM_CAP_STATUS_REG(i) (DR_REG_MCPWM_BASE(i) + 0x108) +/** MCPWM_CAP0_EDGE : RO; bitpos: [0]; default: 0; + * Edge of last capture trigger on channel 0, 0: posedge, 1: negedge + */ +#define MCPWM_CAP0_EDGE (BIT(0)) +#define MCPWM_CAP0_EDGE_M (MCPWM_CAP0_EDGE_V << MCPWM_CAP0_EDGE_S) +#define MCPWM_CAP0_EDGE_V 0x00000001U #define MCPWM_CAP0_EDGE_S 0 +/** MCPWM_CAP1_EDGE : RO; bitpos: [1]; default: 0; + * Edge of last capture trigger on channel 1, 0: posedge, 1: negedge + */ +#define MCPWM_CAP1_EDGE (BIT(1)) +#define MCPWM_CAP1_EDGE_M (MCPWM_CAP1_EDGE_V << MCPWM_CAP1_EDGE_S) +#define MCPWM_CAP1_EDGE_V 0x00000001U +#define MCPWM_CAP1_EDGE_S 1 +/** MCPWM_CAP2_EDGE : RO; bitpos: [2]; default: 0; + * Edge of last capture trigger on channel 2, 0: posedge, 1: negedge + */ +#define MCPWM_CAP2_EDGE (BIT(2)) +#define MCPWM_CAP2_EDGE_M (MCPWM_CAP2_EDGE_V << MCPWM_CAP2_EDGE_S) +#define MCPWM_CAP2_EDGE_V 0x00000001U +#define MCPWM_CAP2_EDGE_S 2 -#define MCPWM_UPDATE_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x010c) -/* MCPWM_OP2_FORCE_UP : R/W ;bitpos:[7] ;default: 1'd0 ; */ -/*description: A toggle (software negation of value of this bit) will trigger - a forced update of active registers in PWM operator 2*/ -#define MCPWM_OP2_FORCE_UP (BIT(7)) -#define MCPWM_OP2_FORCE_UP_M (BIT(7)) -#define MCPWM_OP2_FORCE_UP_V 0x1 -#define MCPWM_OP2_FORCE_UP_S 7 -/* MCPWM_OP2_UP_EN : R/W ;bitpos:[6] ;default: 1'd1 ; */ -/*description: When set and PWM_GLOBAL_UP_EN is set update of active registers - in PWM operator 2 are enabled*/ -#define MCPWM_OP2_UP_EN (BIT(6)) -#define MCPWM_OP2_UP_EN_M (BIT(6)) -#define MCPWM_OP2_UP_EN_V 0x1 -#define MCPWM_OP2_UP_EN_S 6 -/* MCPWM_OP1_FORCE_UP : R/W ;bitpos:[5] ;default: 1'd0 ; */ -/*description: A toggle (software negation of value of this bit) will trigger - a forced update of active registers in PWM operator 1*/ -#define MCPWM_OP1_FORCE_UP (BIT(5)) -#define MCPWM_OP1_FORCE_UP_M (BIT(5)) -#define MCPWM_OP1_FORCE_UP_V 0x1 -#define MCPWM_OP1_FORCE_UP_S 5 -/* MCPWM_OP1_UP_EN : R/W ;bitpos:[4] ;default: 1'd1 ; */ -/*description: When set and PWM_GLOBAL_UP_EN is set update of active registers - in PWM operator 1 are enabled*/ -#define MCPWM_OP1_UP_EN (BIT(4)) -#define MCPWM_OP1_UP_EN_M (BIT(4)) -#define MCPWM_OP1_UP_EN_V 0x1 -#define MCPWM_OP1_UP_EN_S 4 -/* MCPWM_OP0_FORCE_UP : R/W ;bitpos:[3] ;default: 1'd0 ; */ -/*description: A toggle (software negation of value of this bit) will trigger - a forced update of active registers in PWM operator 0*/ -#define MCPWM_OP0_FORCE_UP (BIT(3)) -#define MCPWM_OP0_FORCE_UP_M (BIT(3)) -#define MCPWM_OP0_FORCE_UP_V 0x1 -#define MCPWM_OP0_FORCE_UP_S 3 -/* MCPWM_OP0_UP_EN : R/W ;bitpos:[2] ;default: 1'd1 ; */ -/*description: When set and PWM_GLOBAL_UP_EN is set update of active registers - in PWM operator 0 are enabled*/ -#define MCPWM_OP0_UP_EN (BIT(2)) -#define MCPWM_OP0_UP_EN_M (BIT(2)) -#define MCPWM_OP0_UP_EN_V 0x1 -#define MCPWM_OP0_UP_EN_S 2 -/* MCPWM_GLOBAL_FORCE_UP : R/W ;bitpos:[1] ;default: 1'd0 ; */ -/*description: A toggle (software negation of value of this bit) will trigger - a forced update of all active registers in MCPWM module*/ -#define MCPWM_GLOBAL_FORCE_UP (BIT(1)) -#define MCPWM_GLOBAL_FORCE_UP_M (BIT(1)) -#define MCPWM_GLOBAL_FORCE_UP_V 0x1 -#define MCPWM_GLOBAL_FORCE_UP_S 1 -/* MCPWM_GLOBAL_UP_EN : R/W ;bitpos:[0] ;default: 1'd1 ; */ -/*description: The global enable of update of all active registers in MCPWM module*/ -#define MCPWM_GLOBAL_UP_EN (BIT(0)) -#define MCPWM_GLOBAL_UP_EN_M (BIT(0)) -#define MCPWM_GLOBAL_UP_EN_V 0x1 +/** MCPWM_UPDATE_CFG_REG register + * Enable update. + */ +#define MCPWM_UPDATE_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0x10c) +/** MCPWM_GLOBAL_UP_EN : R/W; bitpos: [0]; default: 1; + * The global enable of update of all active registers in MCPWM module + */ +#define MCPWM_GLOBAL_UP_EN (BIT(0)) +#define MCPWM_GLOBAL_UP_EN_M (MCPWM_GLOBAL_UP_EN_V << MCPWM_GLOBAL_UP_EN_S) +#define MCPWM_GLOBAL_UP_EN_V 0x00000001U #define MCPWM_GLOBAL_UP_EN_S 0 +/** MCPWM_GLOBAL_FORCE_UP : R/W; bitpos: [1]; default: 0; + * a toggle (software invert its value) will trigger a forced update of all active + * registers in MCPWM module + */ +#define MCPWM_GLOBAL_FORCE_UP (BIT(1)) +#define MCPWM_GLOBAL_FORCE_UP_M (MCPWM_GLOBAL_FORCE_UP_V << MCPWM_GLOBAL_FORCE_UP_S) +#define MCPWM_GLOBAL_FORCE_UP_V 0x00000001U +#define MCPWM_GLOBAL_FORCE_UP_S 1 +/** MCPWM_OP0_UP_EN : R/W; bitpos: [2]; default: 1; + * When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 0 + * are enabled + */ +#define MCPWM_OP0_UP_EN (BIT(2)) +#define MCPWM_OP0_UP_EN_M (MCPWM_OP0_UP_EN_V << MCPWM_OP0_UP_EN_S) +#define MCPWM_OP0_UP_EN_V 0x00000001U +#define MCPWM_OP0_UP_EN_S 2 +/** MCPWM_OP0_FORCE_UP : R/W; bitpos: [3]; default: 0; + * a toggle (software invert its value) will trigger a forced update of active + * registers in PWM operator 0 + */ +#define MCPWM_OP0_FORCE_UP (BIT(3)) +#define MCPWM_OP0_FORCE_UP_M (MCPWM_OP0_FORCE_UP_V << MCPWM_OP0_FORCE_UP_S) +#define MCPWM_OP0_FORCE_UP_V 0x00000001U +#define MCPWM_OP0_FORCE_UP_S 3 +/** MCPWM_OP1_UP_EN : R/W; bitpos: [4]; default: 1; + * When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 1 + * are enabled + */ +#define MCPWM_OP1_UP_EN (BIT(4)) +#define MCPWM_OP1_UP_EN_M (MCPWM_OP1_UP_EN_V << MCPWM_OP1_UP_EN_S) +#define MCPWM_OP1_UP_EN_V 0x00000001U +#define MCPWM_OP1_UP_EN_S 4 +/** MCPWM_OP1_FORCE_UP : R/W; bitpos: [5]; default: 0; + * a toggle (software invert its value) will trigger a forced update of active + * registers in PWM operator 1 + */ +#define MCPWM_OP1_FORCE_UP (BIT(5)) +#define MCPWM_OP1_FORCE_UP_M (MCPWM_OP1_FORCE_UP_V << MCPWM_OP1_FORCE_UP_S) +#define MCPWM_OP1_FORCE_UP_V 0x00000001U +#define MCPWM_OP1_FORCE_UP_S 5 +/** MCPWM_OP2_UP_EN : R/W; bitpos: [6]; default: 1; + * When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 2 + * are enabled + */ +#define MCPWM_OP2_UP_EN (BIT(6)) +#define MCPWM_OP2_UP_EN_M (MCPWM_OP2_UP_EN_V << MCPWM_OP2_UP_EN_S) +#define MCPWM_OP2_UP_EN_V 0x00000001U +#define MCPWM_OP2_UP_EN_S 6 +/** MCPWM_OP2_FORCE_UP : R/W; bitpos: [7]; default: 0; + * a toggle (software invert its value) will trigger a forced update of active + * registers in PWM operator 2 + */ +#define MCPWM_OP2_FORCE_UP (BIT(7)) +#define MCPWM_OP2_FORCE_UP_M (MCPWM_OP2_FORCE_UP_V << MCPWM_OP2_FORCE_UP_S) +#define MCPWM_OP2_FORCE_UP_V 0x00000001U +#define MCPWM_OP2_FORCE_UP_S 7 -#define MCMCPWM_INT_ENA_MCPWM_REG(i) (REG_MCPWM_BASE(i) + 0x0110) -/* MCPWM_CAP2_INT_ENA : R/W ;bitpos:[29] ;default: 1'd0 ; */ -/*description: The enable bit for interrupt triggered by captureon channel 2*/ -#define MCPWM_CAP2_INT_ENA (BIT(29)) -#define MCPWM_CAP2_INT_ENA_M (BIT(29)) -#define MCPWM_CAP2_INT_ENA_V 0x1 -#define MCPWM_CAP2_INT_ENA_S 29 -/* MCPWM_CAP1_INT_ENA : R/W ;bitpos:[28] ;default: 1'd0 ; */ -/*description: The enable bit for interrupt triggered by captureon channel 1*/ -#define MCPWM_CAP1_INT_ENA (BIT(28)) -#define MCPWM_CAP1_INT_ENA_M (BIT(28)) -#define MCPWM_CAP1_INT_ENA_V 0x1 -#define MCPWM_CAP1_INT_ENA_S 28 -/* MCPWM_CAP0_INT_ENA : R/W ;bitpos:[27] ;default: 1'd0 ; */ -/*description: The enable bit for interrupt triggered by captureon channel 0*/ -#define MCPWM_CAP0_INT_ENA (BIT(27)) -#define MCPWM_CAP0_INT_ENA_M (BIT(27)) -#define MCPWM_CAP0_INT_ENA_V 0x1 -#define MCPWM_CAP0_INT_ENA_S 27 -/* MCPWM_FH2_OST_INT_ENA : R/W ;bitpos:[26] ;default: 1'd0 ; */ -/*description: The enable bit for interrupt triggered by an one-shot mode action on PWM2*/ -#define MCPWM_FH2_OST_INT_ENA (BIT(26)) -#define MCPWM_FH2_OST_INT_ENA_M (BIT(26)) -#define MCPWM_FH2_OST_INT_ENA_V 0x1 -#define MCPWM_FH2_OST_INT_ENA_S 26 -/* MCPWM_FH1_OST_INT_ENA : R/W ;bitpos:[25] ;default: 1'd0 ; */ -/*description: The enable bit for interrupt triggered by an one-shot mode action on PWM0*/ -#define MCPWM_FH1_OST_INT_ENA (BIT(25)) -#define MCPWM_FH1_OST_INT_ENA_M (BIT(25)) -#define MCPWM_FH1_OST_INT_ENA_V 0x1 -#define MCPWM_FH1_OST_INT_ENA_S 25 -/* MCPWM_FH0_OST_INT_ENA : R/W ;bitpos:[24] ;default: 1'd0 ; */ -/*description: The enable bit for interrupt triggered by an one-shot mode action on PWM0*/ -#define MCPWM_FH0_OST_INT_ENA (BIT(24)) -#define MCPWM_FH0_OST_INT_ENA_M (BIT(24)) -#define MCPWM_FH0_OST_INT_ENA_V 0x1 -#define MCPWM_FH0_OST_INT_ENA_S 24 -/* MCPWM_FH2_CBC_INT_ENA : R/W ;bitpos:[23] ;default: 1'd0 ; */ -/*description: The enable bit for interrupt triggered by an cycle-by-cycle mode action on PWM2*/ -#define MCPWM_FH2_CBC_INT_ENA (BIT(23)) -#define MCPWM_FH2_CBC_INT_ENA_M (BIT(23)) -#define MCPWM_FH2_CBC_INT_ENA_V 0x1 -#define MCPWM_FH2_CBC_INT_ENA_S 23 -/* MCPWM_FH1_CBC_INT_ENA : R/W ;bitpos:[22] ;default: 1'd0 ; */ -/*description: The enable bit for interrupt triggered by an cycle-by-cycle mode action on PWM1*/ -#define MCPWM_FH1_CBC_INT_ENA (BIT(22)) -#define MCPWM_FH1_CBC_INT_ENA_M (BIT(22)) -#define MCPWM_FH1_CBC_INT_ENA_V 0x1 -#define MCPWM_FH1_CBC_INT_ENA_S 22 -/* MCPWM_FH0_CBC_INT_ENA : R/W ;bitpos:[21] ;default: 1'd0 ; */ -/*description: The enable bit for interrupt triggered by an cycle-by-cycle mode action on PWM0*/ -#define MCPWM_FH0_CBC_INT_ENA (BIT(21)) -#define MCPWM_FH0_CBC_INT_ENA_M (BIT(21)) -#define MCPWM_FH0_CBC_INT_ENA_V 0x1 -#define MCPWM_FH0_CBC_INT_ENA_S 21 -/* MCPWM_OP2_TEB_INT_ENA : R/W ;bitpos:[20] ;default: 1'd0 ; */ -/*description: The enable bit for interrupt triggered by a PWM operator 2 TEB event*/ -#define MCPWM_OP2_TEB_INT_ENA (BIT(20)) -#define MCPWM_OP2_TEB_INT_ENA_M (BIT(20)) -#define MCPWM_OP2_TEB_INT_ENA_V 0x1 -#define MCPWM_OP2_TEB_INT_ENA_S 20 -/* MCPWM_OP1_TEB_INT_ENA : R/W ;bitpos:[19] ;default: 1'd0 ; */ -/*description: The enable bit for interrupt triggered by a PWM operator 1 TEB event*/ -#define MCPWM_OP1_TEB_INT_ENA (BIT(19)) -#define MCPWM_OP1_TEB_INT_ENA_M (BIT(19)) -#define MCPWM_OP1_TEB_INT_ENA_V 0x1 -#define MCPWM_OP1_TEB_INT_ENA_S 19 -/* MCPWM_OP0_TEB_INT_ENA : R/W ;bitpos:[18] ;default: 1'd0 ; */ -/*description: The enable bit for interrupt triggered by a PWM operator 0 TEB event*/ -#define MCPWM_OP0_TEB_INT_ENA (BIT(18)) -#define MCPWM_OP0_TEB_INT_ENA_M (BIT(18)) -#define MCPWM_OP0_TEB_INT_ENA_V 0x1 -#define MCPWM_OP0_TEB_INT_ENA_S 18 -/* MCPWM_OP2_TEA_INT_ENA : R/W ;bitpos:[17] ;default: 1'd0 ; */ -/*description: The enable bit for interrupt triggered by a PWM operator 2 TEA event*/ -#define MCPWM_OP2_TEA_INT_ENA (BIT(17)) -#define MCPWM_OP2_TEA_INT_ENA_M (BIT(17)) -#define MCPWM_OP2_TEA_INT_ENA_V 0x1 -#define MCPWM_OP2_TEA_INT_ENA_S 17 -/* MCPWM_OP1_TEA_INT_ENA : R/W ;bitpos:[16] ;default: 1'd0 ; */ -/*description: The enable bit for interrupt triggered by a PWM operator 1 TEA event*/ -#define MCPWM_OP1_TEA_INT_ENA (BIT(16)) -#define MCPWM_OP1_TEA_INT_ENA_M (BIT(16)) -#define MCPWM_OP1_TEA_INT_ENA_V 0x1 -#define MCPWM_OP1_TEA_INT_ENA_S 16 -/* MCPWM_OP0_TEA_INT_ENA : R/W ;bitpos:[15] ;default: 1'd0 ; */ -/*description: The enable bit for interrupt triggered by a PWM operator 0 TEA event*/ -#define MCPWM_OP0_TEA_INT_ENA (BIT(15)) -#define MCPWM_OP0_TEA_INT_ENA_M (BIT(15)) -#define MCPWM_OP0_TEA_INT_ENA_V 0x1 -#define MCPWM_OP0_TEA_INT_ENA_S 15 -/* MCPWM_FAULT2_CLR_INT_ENA : R/W ;bitpos:[14] ;default: 1'd0 ; */ -/*description: The enable bit for interrupt triggered when event_f2 ends*/ -#define MCPWM_FAULT2_CLR_INT_ENA (BIT(14)) -#define MCPWM_FAULT2_CLR_INT_ENA_M (BIT(14)) -#define MCPWM_FAULT2_CLR_INT_ENA_V 0x1 -#define MCPWM_FAULT2_CLR_INT_ENA_S 14 -/* MCPWM_FAULT1_CLR_INT_ENA : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: The enable bit for interrupt triggered when event_f1 ends*/ -#define MCPWM_FAULT1_CLR_INT_ENA (BIT(13)) -#define MCPWM_FAULT1_CLR_INT_ENA_M (BIT(13)) -#define MCPWM_FAULT1_CLR_INT_ENA_V 0x1 -#define MCPWM_FAULT1_CLR_INT_ENA_S 13 -/* MCPWM_FAULT0_CLR_INT_ENA : R/W ;bitpos:[12] ;default: 1'd0 ; */ -/*description: The enable bit for interrupt triggered when event_f0 ends*/ -#define MCPWM_FAULT0_CLR_INT_ENA (BIT(12)) -#define MCPWM_FAULT0_CLR_INT_ENA_M (BIT(12)) -#define MCPWM_FAULT0_CLR_INT_ENA_V 0x1 -#define MCPWM_FAULT0_CLR_INT_ENA_S 12 -/* MCPWM_FAULT2_INT_ENA : R/W ;bitpos:[11] ;default: 1'd0 ; */ -/*description: The enable bit for interrupt triggered when event_f2 starts*/ -#define MCPWM_FAULT2_INT_ENA (BIT(11)) -#define MCPWM_FAULT2_INT_ENA_M (BIT(11)) -#define MCPWM_FAULT2_INT_ENA_V 0x1 -#define MCPWM_FAULT2_INT_ENA_S 11 -/* MCPWM_FAULT1_INT_ENA : R/W ;bitpos:[10] ;default: 1'd0 ; */ -/*description: The enable bit for interrupt triggered when event_f1 starts*/ -#define MCPWM_FAULT1_INT_ENA (BIT(10)) -#define MCPWM_FAULT1_INT_ENA_M (BIT(10)) -#define MCPWM_FAULT1_INT_ENA_V 0x1 -#define MCPWM_FAULT1_INT_ENA_S 10 -/* MCPWM_FAULT0_INT_ENA : R/W ;bitpos:[9] ;default: 1'd0 ; */ -/*description: The enable bit for interrupt triggered when event_f0 starts*/ -#define MCPWM_FAULT0_INT_ENA (BIT(9)) -#define MCPWM_FAULT0_INT_ENA_M (BIT(9)) -#define MCPWM_FAULT0_INT_ENA_V 0x1 -#define MCPWM_FAULT0_INT_ENA_S 9 -/* MCPWM_TIMER2_TEP_INT_ENA : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: The enable bit for interrupt triggered by a PWM timer 2 TEP event*/ -#define MCPWM_TIMER2_TEP_INT_ENA (BIT(8)) -#define MCPWM_TIMER2_TEP_INT_ENA_M (BIT(8)) -#define MCPWM_TIMER2_TEP_INT_ENA_V 0x1 -#define MCPWM_TIMER2_TEP_INT_ENA_S 8 -/* MCPWM_TIMER1_TEP_INT_ENA : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: The enable bit for interrupt triggered by a PWM timer 1 TEP event*/ -#define MCPWM_TIMER1_TEP_INT_ENA (BIT(7)) -#define MCPWM_TIMER1_TEP_INT_ENA_M (BIT(7)) -#define MCPWM_TIMER1_TEP_INT_ENA_V 0x1 -#define MCPWM_TIMER1_TEP_INT_ENA_S 7 -/* MCPWM_TIMER0_TEP_INT_ENA : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: The enable bit for interrupt triggered by a PWM timer 0 TEP event*/ -#define MCPWM_TIMER0_TEP_INT_ENA (BIT(6)) -#define MCPWM_TIMER0_TEP_INT_ENA_M (BIT(6)) -#define MCPWM_TIMER0_TEP_INT_ENA_V 0x1 -#define MCPWM_TIMER0_TEP_INT_ENA_S 6 -/* MCPWM_TIMER2_TEZ_INT_ENA : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: The enable bit for interrupt triggered by a PWM timer 2 TEZ event*/ -#define MCPWM_TIMER2_TEZ_INT_ENA (BIT(5)) -#define MCPWM_TIMER2_TEZ_INT_ENA_M (BIT(5)) -#define MCPWM_TIMER2_TEZ_INT_ENA_V 0x1 -#define MCPWM_TIMER2_TEZ_INT_ENA_S 5 -/* MCPWM_TIMER1_TEZ_INT_ENA : R/W ;bitpos:[4] ;default: 1'h0 ; */ -/*description: The enable bit for interrupt triggered by a PWM timer 1 TEZ event*/ -#define MCPWM_TIMER1_TEZ_INT_ENA (BIT(4)) -#define MCPWM_TIMER1_TEZ_INT_ENA_M (BIT(4)) -#define MCPWM_TIMER1_TEZ_INT_ENA_V 0x1 -#define MCPWM_TIMER1_TEZ_INT_ENA_S 4 -/* MCPWM_TIMER0_TEZ_INT_ENA : R/W ;bitpos:[3] ;default: 1'h0 ; */ -/*description: The enable bit for interrupt triggered by a PWM timer 0 TEZ event*/ -#define MCPWM_TIMER0_TEZ_INT_ENA (BIT(3)) -#define MCPWM_TIMER0_TEZ_INT_ENA_M (BIT(3)) -#define MCPWM_TIMER0_TEZ_INT_ENA_V 0x1 -#define MCPWM_TIMER0_TEZ_INT_ENA_S 3 -/* MCPWM_TIMER2_STOP_INT_ENA : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: The enable bit for interrupt triggered when timer 2 stops*/ -#define MCPWM_TIMER2_STOP_INT_ENA (BIT(2)) -#define MCPWM_TIMER2_STOP_INT_ENA_M (BIT(2)) -#define MCPWM_TIMER2_STOP_INT_ENA_V 0x1 -#define MCPWM_TIMER2_STOP_INT_ENA_S 2 -/* MCPWM_TIMER1_STOP_INT_ENA : R/W ;bitpos:[1] ;default: 1'h0 ; */ -/*description: The enable bit for interrupt triggered when timer 1 stops*/ -#define MCPWM_TIMER1_STOP_INT_ENA (BIT(1)) -#define MCPWM_TIMER1_STOP_INT_ENA_M (BIT(1)) -#define MCPWM_TIMER1_STOP_INT_ENA_V 0x1 -#define MCPWM_TIMER1_STOP_INT_ENA_S 1 -/* MCPWM_TIMER0_STOP_INT_ENA : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: The enable bit for interrupt triggered when timer 0 stops*/ -#define MCPWM_TIMER0_STOP_INT_ENA (BIT(0)) -#define MCPWM_TIMER0_STOP_INT_ENA_M (BIT(0)) -#define MCPWM_TIMER0_STOP_INT_ENA_V 0x1 +/** MCPWM_INT_ENA_REG register + * Interrupt enable bits + */ +#define MCPWM_INT_ENA_REG(i) (DR_REG_MCPWM_BASE(i) + 0x110) +/** MCPWM_TIMER0_STOP_INT_ENA : R/W; bitpos: [0]; default: 0; + * The enable bit for the interrupt triggered when the timer 0 stops. + */ +#define MCPWM_TIMER0_STOP_INT_ENA (BIT(0)) +#define MCPWM_TIMER0_STOP_INT_ENA_M (MCPWM_TIMER0_STOP_INT_ENA_V << MCPWM_TIMER0_STOP_INT_ENA_S) +#define MCPWM_TIMER0_STOP_INT_ENA_V 0x00000001U #define MCPWM_TIMER0_STOP_INT_ENA_S 0 +/** MCPWM_TIMER1_STOP_INT_ENA : R/W; bitpos: [1]; default: 0; + * The enable bit for the interrupt triggered when the timer 1 stops. + */ +#define MCPWM_TIMER1_STOP_INT_ENA (BIT(1)) +#define MCPWM_TIMER1_STOP_INT_ENA_M (MCPWM_TIMER1_STOP_INT_ENA_V << MCPWM_TIMER1_STOP_INT_ENA_S) +#define MCPWM_TIMER1_STOP_INT_ENA_V 0x00000001U +#define MCPWM_TIMER1_STOP_INT_ENA_S 1 +/** MCPWM_TIMER2_STOP_INT_ENA : R/W; bitpos: [2]; default: 0; + * The enable bit for the interrupt triggered when the timer 2 stops. + */ +#define MCPWM_TIMER2_STOP_INT_ENA (BIT(2)) +#define MCPWM_TIMER2_STOP_INT_ENA_M (MCPWM_TIMER2_STOP_INT_ENA_V << MCPWM_TIMER2_STOP_INT_ENA_S) +#define MCPWM_TIMER2_STOP_INT_ENA_V 0x00000001U +#define MCPWM_TIMER2_STOP_INT_ENA_S 2 +/** MCPWM_TIMER0_TEZ_INT_ENA : R/W; bitpos: [3]; default: 0; + * The enable bit for the interrupt triggered by a PWM timer 0 TEZ event. + */ +#define MCPWM_TIMER0_TEZ_INT_ENA (BIT(3)) +#define MCPWM_TIMER0_TEZ_INT_ENA_M (MCPWM_TIMER0_TEZ_INT_ENA_V << MCPWM_TIMER0_TEZ_INT_ENA_S) +#define MCPWM_TIMER0_TEZ_INT_ENA_V 0x00000001U +#define MCPWM_TIMER0_TEZ_INT_ENA_S 3 +/** MCPWM_TIMER1_TEZ_INT_ENA : R/W; bitpos: [4]; default: 0; + * The enable bit for the interrupt triggered by a PWM timer 1 TEZ event. + */ +#define MCPWM_TIMER1_TEZ_INT_ENA (BIT(4)) +#define MCPWM_TIMER1_TEZ_INT_ENA_M (MCPWM_TIMER1_TEZ_INT_ENA_V << MCPWM_TIMER1_TEZ_INT_ENA_S) +#define MCPWM_TIMER1_TEZ_INT_ENA_V 0x00000001U +#define MCPWM_TIMER1_TEZ_INT_ENA_S 4 +/** MCPWM_TIMER2_TEZ_INT_ENA : R/W; bitpos: [5]; default: 0; + * The enable bit for the interrupt triggered by a PWM timer 2 TEZ event. + */ +#define MCPWM_TIMER2_TEZ_INT_ENA (BIT(5)) +#define MCPWM_TIMER2_TEZ_INT_ENA_M (MCPWM_TIMER2_TEZ_INT_ENA_V << MCPWM_TIMER2_TEZ_INT_ENA_S) +#define MCPWM_TIMER2_TEZ_INT_ENA_V 0x00000001U +#define MCPWM_TIMER2_TEZ_INT_ENA_S 5 +/** MCPWM_TIMER0_TEP_INT_ENA : R/W; bitpos: [6]; default: 0; + * The enable bit for the interrupt triggered by a PWM timer 0 TEP event. + */ +#define MCPWM_TIMER0_TEP_INT_ENA (BIT(6)) +#define MCPWM_TIMER0_TEP_INT_ENA_M (MCPWM_TIMER0_TEP_INT_ENA_V << MCPWM_TIMER0_TEP_INT_ENA_S) +#define MCPWM_TIMER0_TEP_INT_ENA_V 0x00000001U +#define MCPWM_TIMER0_TEP_INT_ENA_S 6 +/** MCPWM_TIMER1_TEP_INT_ENA : R/W; bitpos: [7]; default: 0; + * The enable bit for the interrupt triggered by a PWM timer 1 TEP event. + */ +#define MCPWM_TIMER1_TEP_INT_ENA (BIT(7)) +#define MCPWM_TIMER1_TEP_INT_ENA_M (MCPWM_TIMER1_TEP_INT_ENA_V << MCPWM_TIMER1_TEP_INT_ENA_S) +#define MCPWM_TIMER1_TEP_INT_ENA_V 0x00000001U +#define MCPWM_TIMER1_TEP_INT_ENA_S 7 +/** MCPWM_TIMER2_TEP_INT_ENA : R/W; bitpos: [8]; default: 0; + * The enable bit for the interrupt triggered by a PWM timer 2 TEP event. + */ +#define MCPWM_TIMER2_TEP_INT_ENA (BIT(8)) +#define MCPWM_TIMER2_TEP_INT_ENA_M (MCPWM_TIMER2_TEP_INT_ENA_V << MCPWM_TIMER2_TEP_INT_ENA_S) +#define MCPWM_TIMER2_TEP_INT_ENA_V 0x00000001U +#define MCPWM_TIMER2_TEP_INT_ENA_S 8 +/** MCPWM_FAULT0_INT_ENA : R/W; bitpos: [9]; default: 0; + * The enable bit for the interrupt triggered when fault_event0 starts. + */ +#define MCPWM_FAULT0_INT_ENA (BIT(9)) +#define MCPWM_FAULT0_INT_ENA_M (MCPWM_FAULT0_INT_ENA_V << MCPWM_FAULT0_INT_ENA_S) +#define MCPWM_FAULT0_INT_ENA_V 0x00000001U +#define MCPWM_FAULT0_INT_ENA_S 9 +/** MCPWM_FAULT1_INT_ENA : R/W; bitpos: [10]; default: 0; + * The enable bit for the interrupt triggered when fault_event1 starts. + */ +#define MCPWM_FAULT1_INT_ENA (BIT(10)) +#define MCPWM_FAULT1_INT_ENA_M (MCPWM_FAULT1_INT_ENA_V << MCPWM_FAULT1_INT_ENA_S) +#define MCPWM_FAULT1_INT_ENA_V 0x00000001U +#define MCPWM_FAULT1_INT_ENA_S 10 +/** MCPWM_FAULT2_INT_ENA : R/W; bitpos: [11]; default: 0; + * The enable bit for the interrupt triggered when fault_event2 starts. + */ +#define MCPWM_FAULT2_INT_ENA (BIT(11)) +#define MCPWM_FAULT2_INT_ENA_M (MCPWM_FAULT2_INT_ENA_V << MCPWM_FAULT2_INT_ENA_S) +#define MCPWM_FAULT2_INT_ENA_V 0x00000001U +#define MCPWM_FAULT2_INT_ENA_S 11 +/** MCPWM_FAULT0_CLR_INT_ENA : R/W; bitpos: [12]; default: 0; + * The enable bit for the interrupt triggered when fault_event0 ends. + */ +#define MCPWM_FAULT0_CLR_INT_ENA (BIT(12)) +#define MCPWM_FAULT0_CLR_INT_ENA_M (MCPWM_FAULT0_CLR_INT_ENA_V << MCPWM_FAULT0_CLR_INT_ENA_S) +#define MCPWM_FAULT0_CLR_INT_ENA_V 0x00000001U +#define MCPWM_FAULT0_CLR_INT_ENA_S 12 +/** MCPWM_FAULT1_CLR_INT_ENA : R/W; bitpos: [13]; default: 0; + * The enable bit for the interrupt triggered when fault_event1 ends. + */ +#define MCPWM_FAULT1_CLR_INT_ENA (BIT(13)) +#define MCPWM_FAULT1_CLR_INT_ENA_M (MCPWM_FAULT1_CLR_INT_ENA_V << MCPWM_FAULT1_CLR_INT_ENA_S) +#define MCPWM_FAULT1_CLR_INT_ENA_V 0x00000001U +#define MCPWM_FAULT1_CLR_INT_ENA_S 13 +/** MCPWM_FAULT2_CLR_INT_ENA : R/W; bitpos: [14]; default: 0; + * The enable bit for the interrupt triggered when fault_event2 ends. + */ +#define MCPWM_FAULT2_CLR_INT_ENA (BIT(14)) +#define MCPWM_FAULT2_CLR_INT_ENA_M (MCPWM_FAULT2_CLR_INT_ENA_V << MCPWM_FAULT2_CLR_INT_ENA_S) +#define MCPWM_FAULT2_CLR_INT_ENA_V 0x00000001U +#define MCPWM_FAULT2_CLR_INT_ENA_S 14 +/** MCPWM_OP0_TEA_INT_ENA : R/W; bitpos: [15]; default: 0; + * The enable bit for the interrupt triggered by a PWM operator 0 TEA event + */ +#define MCPWM_OP0_TEA_INT_ENA (BIT(15)) +#define MCPWM_OP0_TEA_INT_ENA_M (MCPWM_OP0_TEA_INT_ENA_V << MCPWM_OP0_TEA_INT_ENA_S) +#define MCPWM_OP0_TEA_INT_ENA_V 0x00000001U +#define MCPWM_OP0_TEA_INT_ENA_S 15 +/** MCPWM_OP1_TEA_INT_ENA : R/W; bitpos: [16]; default: 0; + * The enable bit for the interrupt triggered by a PWM operator 1 TEA event + */ +#define MCPWM_OP1_TEA_INT_ENA (BIT(16)) +#define MCPWM_OP1_TEA_INT_ENA_M (MCPWM_OP1_TEA_INT_ENA_V << MCPWM_OP1_TEA_INT_ENA_S) +#define MCPWM_OP1_TEA_INT_ENA_V 0x00000001U +#define MCPWM_OP1_TEA_INT_ENA_S 16 +/** MCPWM_OP2_TEA_INT_ENA : R/W; bitpos: [17]; default: 0; + * The enable bit for the interrupt triggered by a PWM operator 2 TEA event + */ +#define MCPWM_OP2_TEA_INT_ENA (BIT(17)) +#define MCPWM_OP2_TEA_INT_ENA_M (MCPWM_OP2_TEA_INT_ENA_V << MCPWM_OP2_TEA_INT_ENA_S) +#define MCPWM_OP2_TEA_INT_ENA_V 0x00000001U +#define MCPWM_OP2_TEA_INT_ENA_S 17 +/** MCPWM_OP0_TEB_INT_ENA : R/W; bitpos: [18]; default: 0; + * The enable bit for the interrupt triggered by a PWM operator 0 TEB event + */ +#define MCPWM_OP0_TEB_INT_ENA (BIT(18)) +#define MCPWM_OP0_TEB_INT_ENA_M (MCPWM_OP0_TEB_INT_ENA_V << MCPWM_OP0_TEB_INT_ENA_S) +#define MCPWM_OP0_TEB_INT_ENA_V 0x00000001U +#define MCPWM_OP0_TEB_INT_ENA_S 18 +/** MCPWM_OP1_TEB_INT_ENA : R/W; bitpos: [19]; default: 0; + * The enable bit for the interrupt triggered by a PWM operator 1 TEB event + */ +#define MCPWM_OP1_TEB_INT_ENA (BIT(19)) +#define MCPWM_OP1_TEB_INT_ENA_M (MCPWM_OP1_TEB_INT_ENA_V << MCPWM_OP1_TEB_INT_ENA_S) +#define MCPWM_OP1_TEB_INT_ENA_V 0x00000001U +#define MCPWM_OP1_TEB_INT_ENA_S 19 +/** MCPWM_OP2_TEB_INT_ENA : R/W; bitpos: [20]; default: 0; + * The enable bit for the interrupt triggered by a PWM operator 2 TEB event + */ +#define MCPWM_OP2_TEB_INT_ENA (BIT(20)) +#define MCPWM_OP2_TEB_INT_ENA_M (MCPWM_OP2_TEB_INT_ENA_V << MCPWM_OP2_TEB_INT_ENA_S) +#define MCPWM_OP2_TEB_INT_ENA_V 0x00000001U +#define MCPWM_OP2_TEB_INT_ENA_S 20 +/** MCPWM_FH0_CBC_INT_ENA : R/W; bitpos: [21]; default: 0; + * The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0. + */ +#define MCPWM_FH0_CBC_INT_ENA (BIT(21)) +#define MCPWM_FH0_CBC_INT_ENA_M (MCPWM_FH0_CBC_INT_ENA_V << MCPWM_FH0_CBC_INT_ENA_S) +#define MCPWM_FH0_CBC_INT_ENA_V 0x00000001U +#define MCPWM_FH0_CBC_INT_ENA_S 21 +/** MCPWM_FH1_CBC_INT_ENA : R/W; bitpos: [22]; default: 0; + * The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1. + */ +#define MCPWM_FH1_CBC_INT_ENA (BIT(22)) +#define MCPWM_FH1_CBC_INT_ENA_M (MCPWM_FH1_CBC_INT_ENA_V << MCPWM_FH1_CBC_INT_ENA_S) +#define MCPWM_FH1_CBC_INT_ENA_V 0x00000001U +#define MCPWM_FH1_CBC_INT_ENA_S 22 +/** MCPWM_FH2_CBC_INT_ENA : R/W; bitpos: [23]; default: 0; + * The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2. + */ +#define MCPWM_FH2_CBC_INT_ENA (BIT(23)) +#define MCPWM_FH2_CBC_INT_ENA_M (MCPWM_FH2_CBC_INT_ENA_V << MCPWM_FH2_CBC_INT_ENA_S) +#define MCPWM_FH2_CBC_INT_ENA_V 0x00000001U +#define MCPWM_FH2_CBC_INT_ENA_S 23 +/** MCPWM_FH0_OST_INT_ENA : R/W; bitpos: [24]; default: 0; + * The enable bit for the interrupt triggered by a one-shot mode action on PWM0. + */ +#define MCPWM_FH0_OST_INT_ENA (BIT(24)) +#define MCPWM_FH0_OST_INT_ENA_M (MCPWM_FH0_OST_INT_ENA_V << MCPWM_FH0_OST_INT_ENA_S) +#define MCPWM_FH0_OST_INT_ENA_V 0x00000001U +#define MCPWM_FH0_OST_INT_ENA_S 24 +/** MCPWM_FH1_OST_INT_ENA : R/W; bitpos: [25]; default: 0; + * The enable bit for the interrupt triggered by a one-shot mode action on PWM1. + */ +#define MCPWM_FH1_OST_INT_ENA (BIT(25)) +#define MCPWM_FH1_OST_INT_ENA_M (MCPWM_FH1_OST_INT_ENA_V << MCPWM_FH1_OST_INT_ENA_S) +#define MCPWM_FH1_OST_INT_ENA_V 0x00000001U +#define MCPWM_FH1_OST_INT_ENA_S 25 +/** MCPWM_FH2_OST_INT_ENA : R/W; bitpos: [26]; default: 0; + * The enable bit for the interrupt triggered by a one-shot mode action on PWM2. + */ +#define MCPWM_FH2_OST_INT_ENA (BIT(26)) +#define MCPWM_FH2_OST_INT_ENA_M (MCPWM_FH2_OST_INT_ENA_V << MCPWM_FH2_OST_INT_ENA_S) +#define MCPWM_FH2_OST_INT_ENA_V 0x00000001U +#define MCPWM_FH2_OST_INT_ENA_S 26 +/** MCPWM_CAP0_INT_ENA : R/W; bitpos: [27]; default: 0; + * The enable bit for the interrupt triggered by capture on channel 0. + */ +#define MCPWM_CAP0_INT_ENA (BIT(27)) +#define MCPWM_CAP0_INT_ENA_M (MCPWM_CAP0_INT_ENA_V << MCPWM_CAP0_INT_ENA_S) +#define MCPWM_CAP0_INT_ENA_V 0x00000001U +#define MCPWM_CAP0_INT_ENA_S 27 +/** MCPWM_CAP1_INT_ENA : R/W; bitpos: [28]; default: 0; + * The enable bit for the interrupt triggered by capture on channel 1. + */ +#define MCPWM_CAP1_INT_ENA (BIT(28)) +#define MCPWM_CAP1_INT_ENA_M (MCPWM_CAP1_INT_ENA_V << MCPWM_CAP1_INT_ENA_S) +#define MCPWM_CAP1_INT_ENA_V 0x00000001U +#define MCPWM_CAP1_INT_ENA_S 28 +/** MCPWM_CAP2_INT_ENA : R/W; bitpos: [29]; default: 0; + * The enable bit for the interrupt triggered by capture on channel 2. + */ +#define MCPWM_CAP2_INT_ENA (BIT(29)) +#define MCPWM_CAP2_INT_ENA_M (MCPWM_CAP2_INT_ENA_V << MCPWM_CAP2_INT_ENA_S) +#define MCPWM_CAP2_INT_ENA_V 0x00000001U +#define MCPWM_CAP2_INT_ENA_S 29 -#define MCMCPWM_INT_RAW_MCPWM_REG(i) (REG_MCPWM_BASE(i) + 0x0114) -/* MCPWM_CAP2_INT_RAW : RO ;bitpos:[29] ;default: 1'd0 ; */ -/*description: The raw status bit for interrupt triggered by captureon channel 2*/ -#define MCPWM_CAP2_INT_RAW (BIT(29)) -#define MCPWM_CAP2_INT_RAW_M (BIT(29)) -#define MCPWM_CAP2_INT_RAW_V 0x1 -#define MCPWM_CAP2_INT_RAW_S 29 -/* MCPWM_CAP1_INT_RAW : RO ;bitpos:[28] ;default: 1'd0 ; */ -/*description: The raw status bit for interrupt triggered by captureon channel 1*/ -#define MCPWM_CAP1_INT_RAW (BIT(28)) -#define MCPWM_CAP1_INT_RAW_M (BIT(28)) -#define MCPWM_CAP1_INT_RAW_V 0x1 -#define MCPWM_CAP1_INT_RAW_S 28 -/* MCPWM_CAP0_INT_RAW : RO ;bitpos:[27] ;default: 1'd0 ; */ -/*description: The raw status bit for interrupt triggered by captureon channel 0*/ -#define MCPWM_CAP0_INT_RAW (BIT(27)) -#define MCPWM_CAP0_INT_RAW_M (BIT(27)) -#define MCPWM_CAP0_INT_RAW_V 0x1 -#define MCPWM_CAP0_INT_RAW_S 27 -/* MCPWM_FH2_OST_INT_RAW : RO ;bitpos:[26] ;default: 1'd0 ; */ -/*description: The raw status bit for interrupt triggered by an one-shot mode action on PWM2*/ -#define MCPWM_FH2_OST_INT_RAW (BIT(26)) -#define MCPWM_FH2_OST_INT_RAW_M (BIT(26)) -#define MCPWM_FH2_OST_INT_RAW_V 0x1 -#define MCPWM_FH2_OST_INT_RAW_S 26 -/* MCPWM_FH1_OST_INT_RAW : RO ;bitpos:[25] ;default: 1'd0 ; */ -/*description: The raw status bit for interrupt triggered by an one-shot mode action on PWM0*/ -#define MCPWM_FH1_OST_INT_RAW (BIT(25)) -#define MCPWM_FH1_OST_INT_RAW_M (BIT(25)) -#define MCPWM_FH1_OST_INT_RAW_V 0x1 -#define MCPWM_FH1_OST_INT_RAW_S 25 -/* MCPWM_FH0_OST_INT_RAW : RO ;bitpos:[24] ;default: 1'd0 ; */ -/*description: The raw status bit for interrupt triggered by an one-shot mode action on PWM0*/ -#define MCPWM_FH0_OST_INT_RAW (BIT(24)) -#define MCPWM_FH0_OST_INT_RAW_M (BIT(24)) -#define MCPWM_FH0_OST_INT_RAW_V 0x1 -#define MCPWM_FH0_OST_INT_RAW_S 24 -/* MCPWM_FH2_CBC_INT_RAW : RO ;bitpos:[23] ;default: 1'd0 ; */ -/*description: The raw status bit for interrupt triggered by an cycle-by-cycle - mode action on PWM2*/ -#define MCPWM_FH2_CBC_INT_RAW (BIT(23)) -#define MCPWM_FH2_CBC_INT_RAW_M (BIT(23)) -#define MCPWM_FH2_CBC_INT_RAW_V 0x1 -#define MCPWM_FH2_CBC_INT_RAW_S 23 -/* MCPWM_FH1_CBC_INT_RAW : RO ;bitpos:[22] ;default: 1'd0 ; */ -/*description: The raw status bit for interrupt triggered by an cycle-by-cycle - mode action on PWM1*/ -#define MCPWM_FH1_CBC_INT_RAW (BIT(22)) -#define MCPWM_FH1_CBC_INT_RAW_M (BIT(22)) -#define MCPWM_FH1_CBC_INT_RAW_V 0x1 -#define MCPWM_FH1_CBC_INT_RAW_S 22 -/* MCPWM_FH0_CBC_INT_RAW : RO ;bitpos:[21] ;default: 1'd0 ; */ -/*description: The raw status bit for interrupt triggered by an cycle-by-cycle - mode action on PWM0*/ -#define MCPWM_FH0_CBC_INT_RAW (BIT(21)) -#define MCPWM_FH0_CBC_INT_RAW_M (BIT(21)) -#define MCPWM_FH0_CBC_INT_RAW_V 0x1 -#define MCPWM_FH0_CBC_INT_RAW_S 21 -/* MCPWM_OP2_TEB_INT_RAW : RO ;bitpos:[20] ;default: 1'd0 ; */ -/*description: The raw status bit for interrupt triggered by a PWM operator 2 TEB event*/ -#define MCPWM_OP2_TEB_INT_RAW (BIT(20)) -#define MCPWM_OP2_TEB_INT_RAW_M (BIT(20)) -#define MCPWM_OP2_TEB_INT_RAW_V 0x1 -#define MCPWM_OP2_TEB_INT_RAW_S 20 -/* MCPWM_OP1_TEB_INT_RAW : RO ;bitpos:[19] ;default: 1'd0 ; */ -/*description: The raw status bit for interrupt triggered by a PWM operator 1 TEB event*/ -#define MCPWM_OP1_TEB_INT_RAW (BIT(19)) -#define MCPWM_OP1_TEB_INT_RAW_M (BIT(19)) -#define MCPWM_OP1_TEB_INT_RAW_V 0x1 -#define MCPWM_OP1_TEB_INT_RAW_S 19 -/* MCPWM_OP0_TEB_INT_RAW : RO ;bitpos:[18] ;default: 1'd0 ; */ -/*description: The raw status bit for interrupt triggered by a PWM operator 0 TEB event*/ -#define MCPWM_OP0_TEB_INT_RAW (BIT(18)) -#define MCPWM_OP0_TEB_INT_RAW_M (BIT(18)) -#define MCPWM_OP0_TEB_INT_RAW_V 0x1 -#define MCPWM_OP0_TEB_INT_RAW_S 18 -/* MCPWM_OP2_TEA_INT_RAW : RO ;bitpos:[17] ;default: 1'd0 ; */ -/*description: The raw status bit for interrupt triggered by a PWM operator 2 TEA event*/ -#define MCPWM_OP2_TEA_INT_RAW (BIT(17)) -#define MCPWM_OP2_TEA_INT_RAW_M (BIT(17)) -#define MCPWM_OP2_TEA_INT_RAW_V 0x1 -#define MCPWM_OP2_TEA_INT_RAW_S 17 -/* MCPWM_OP1_TEA_INT_RAW : RO ;bitpos:[16] ;default: 1'd0 ; */ -/*description: The raw status bit for interrupt triggered by a PWM operator 1 TEA event*/ -#define MCPWM_OP1_TEA_INT_RAW (BIT(16)) -#define MCPWM_OP1_TEA_INT_RAW_M (BIT(16)) -#define MCPWM_OP1_TEA_INT_RAW_V 0x1 -#define MCPWM_OP1_TEA_INT_RAW_S 16 -/* MCPWM_OP0_TEA_INT_RAW : RO ;bitpos:[15] ;default: 1'd0 ; */ -/*description: The raw status bit for interrupt triggered by a PWM operator 0 TEA event*/ -#define MCPWM_OP0_TEA_INT_RAW (BIT(15)) -#define MCPWM_OP0_TEA_INT_RAW_M (BIT(15)) -#define MCPWM_OP0_TEA_INT_RAW_V 0x1 -#define MCPWM_OP0_TEA_INT_RAW_S 15 -/* MCPWM_FAULT2_CLR_INT_RAW : RO ;bitpos:[14] ;default: 1'd0 ; */ -/*description: The raw status bit for interrupt triggered when event_f2 ends*/ -#define MCPWM_FAULT2_CLR_INT_RAW (BIT(14)) -#define MCPWM_FAULT2_CLR_INT_RAW_M (BIT(14)) -#define MCPWM_FAULT2_CLR_INT_RAW_V 0x1 -#define MCPWM_FAULT2_CLR_INT_RAW_S 14 -/* MCPWM_FAULT1_CLR_INT_RAW : RO ;bitpos:[13] ;default: 1'd0 ; */ -/*description: The raw status bit for interrupt triggered when event_f1 ends*/ -#define MCPWM_FAULT1_CLR_INT_RAW (BIT(13)) -#define MCPWM_FAULT1_CLR_INT_RAW_M (BIT(13)) -#define MCPWM_FAULT1_CLR_INT_RAW_V 0x1 -#define MCPWM_FAULT1_CLR_INT_RAW_S 13 -/* MCPWM_FAULT0_CLR_INT_RAW : RO ;bitpos:[12] ;default: 1'd0 ; */ -/*description: The raw status bit for interrupt triggered when event_f0 ends*/ -#define MCPWM_FAULT0_CLR_INT_RAW (BIT(12)) -#define MCPWM_FAULT0_CLR_INT_RAW_M (BIT(12)) -#define MCPWM_FAULT0_CLR_INT_RAW_V 0x1 -#define MCPWM_FAULT0_CLR_INT_RAW_S 12 -/* MCPWM_FAULT2_INT_RAW : RO ;bitpos:[11] ;default: 1'd0 ; */ -/*description: The raw status bit for interrupt triggered when event_f2 starts*/ -#define MCPWM_FAULT2_INT_RAW (BIT(11)) -#define MCPWM_FAULT2_INT_RAW_M (BIT(11)) -#define MCPWM_FAULT2_INT_RAW_V 0x1 -#define MCPWM_FAULT2_INT_RAW_S 11 -/* MCPWM_FAULT1_INT_RAW : RO ;bitpos:[10] ;default: 1'd0 ; */ -/*description: The raw status bit for interrupt triggered when event_f1 starts*/ -#define MCPWM_FAULT1_INT_RAW (BIT(10)) -#define MCPWM_FAULT1_INT_RAW_M (BIT(10)) -#define MCPWM_FAULT1_INT_RAW_V 0x1 -#define MCPWM_FAULT1_INT_RAW_S 10 -/* MCPWM_FAULT0_INT_RAW : RO ;bitpos:[9] ;default: 1'd0 ; */ -/*description: The raw status bit for interrupt triggered when event_f0 starts*/ -#define MCPWM_FAULT0_INT_RAW (BIT(9)) -#define MCPWM_FAULT0_INT_RAW_M (BIT(9)) -#define MCPWM_FAULT0_INT_RAW_V 0x1 -#define MCPWM_FAULT0_INT_RAW_S 9 -/* MCPWM_TIMER2_TEP_INT_RAW : RO ;bitpos:[8] ;default: 1'h0 ; */ -/*description: The raw status bit for interrupt triggered by a PWM timer 2 TEP event*/ -#define MCPWM_TIMER2_TEP_INT_RAW (BIT(8)) -#define MCPWM_TIMER2_TEP_INT_RAW_M (BIT(8)) -#define MCPWM_TIMER2_TEP_INT_RAW_V 0x1 -#define MCPWM_TIMER2_TEP_INT_RAW_S 8 -/* MCPWM_TIMER1_TEP_INT_RAW : RO ;bitpos:[7] ;default: 1'h0 ; */ -/*description: The raw status bit for interrupt triggered by a PWM timer 1 TEP event*/ -#define MCPWM_TIMER1_TEP_INT_RAW (BIT(7)) -#define MCPWM_TIMER1_TEP_INT_RAW_M (BIT(7)) -#define MCPWM_TIMER1_TEP_INT_RAW_V 0x1 -#define MCPWM_TIMER1_TEP_INT_RAW_S 7 -/* MCPWM_TIMER0_TEP_INT_RAW : RO ;bitpos:[6] ;default: 1'h0 ; */ -/*description: The raw status bit for interrupt triggered by a PWM timer 0 TEP event*/ -#define MCPWM_TIMER0_TEP_INT_RAW (BIT(6)) -#define MCPWM_TIMER0_TEP_INT_RAW_M (BIT(6)) -#define MCPWM_TIMER0_TEP_INT_RAW_V 0x1 -#define MCPWM_TIMER0_TEP_INT_RAW_S 6 -/* MCPWM_TIMER2_TEZ_INT_RAW : RO ;bitpos:[5] ;default: 1'h0 ; */ -/*description: The raw status bit for interrupt triggered by a PWM timer 2 TEZ event*/ -#define MCPWM_TIMER2_TEZ_INT_RAW (BIT(5)) -#define MCPWM_TIMER2_TEZ_INT_RAW_M (BIT(5)) -#define MCPWM_TIMER2_TEZ_INT_RAW_V 0x1 -#define MCPWM_TIMER2_TEZ_INT_RAW_S 5 -/* MCPWM_TIMER1_TEZ_INT_RAW : RO ;bitpos:[4] ;default: 1'h0 ; */ -/*description: The raw status bit for interrupt triggered by a PWM timer 1 TEZ event*/ -#define MCPWM_TIMER1_TEZ_INT_RAW (BIT(4)) -#define MCPWM_TIMER1_TEZ_INT_RAW_M (BIT(4)) -#define MCPWM_TIMER1_TEZ_INT_RAW_V 0x1 -#define MCPWM_TIMER1_TEZ_INT_RAW_S 4 -/* MCPWM_TIMER0_TEZ_INT_RAW : RO ;bitpos:[3] ;default: 1'h0 ; */ -/*description: The raw status bit for interrupt triggered by a PWM timer 0 TEZ event*/ -#define MCPWM_TIMER0_TEZ_INT_RAW (BIT(3)) -#define MCPWM_TIMER0_TEZ_INT_RAW_M (BIT(3)) -#define MCPWM_TIMER0_TEZ_INT_RAW_V 0x1 -#define MCPWM_TIMER0_TEZ_INT_RAW_S 3 -/* MCPWM_TIMER2_STOP_INT_RAW : RO ;bitpos:[2] ;default: 1'h0 ; */ -/*description: The raw status bit for interrupt triggered when timer 2 stops*/ -#define MCPWM_TIMER2_STOP_INT_RAW (BIT(2)) -#define MCPWM_TIMER2_STOP_INT_RAW_M (BIT(2)) -#define MCPWM_TIMER2_STOP_INT_RAW_V 0x1 -#define MCPWM_TIMER2_STOP_INT_RAW_S 2 -/* MCPWM_TIMER1_STOP_INT_RAW : RO ;bitpos:[1] ;default: 1'h0 ; */ -/*description: The raw status bit for interrupt triggered when timer 1 stops*/ -#define MCPWM_TIMER1_STOP_INT_RAW (BIT(1)) -#define MCPWM_TIMER1_STOP_INT_RAW_M (BIT(1)) -#define MCPWM_TIMER1_STOP_INT_RAW_V 0x1 -#define MCPWM_TIMER1_STOP_INT_RAW_S 1 -/* MCPWM_TIMER0_STOP_INT_RAW : RO ;bitpos:[0] ;default: 1'h0 ; */ -/*description: The raw status bit for interrupt triggered when timer 0 stops*/ -#define MCPWM_TIMER0_STOP_INT_RAW (BIT(0)) -#define MCPWM_TIMER0_STOP_INT_RAW_M (BIT(0)) -#define MCPWM_TIMER0_STOP_INT_RAW_V 0x1 +/** MCPWM_INT_RAW_REG register + * Raw interrupt status + */ +#define MCPWM_INT_RAW_REG(i) (DR_REG_MCPWM_BASE(i) + 0x114) +/** MCPWM_TIMER0_STOP_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw status bit for the interrupt triggered when the timer 0 stops. + */ +#define MCPWM_TIMER0_STOP_INT_RAW (BIT(0)) +#define MCPWM_TIMER0_STOP_INT_RAW_M (MCPWM_TIMER0_STOP_INT_RAW_V << MCPWM_TIMER0_STOP_INT_RAW_S) +#define MCPWM_TIMER0_STOP_INT_RAW_V 0x00000001U #define MCPWM_TIMER0_STOP_INT_RAW_S 0 +/** MCPWM_TIMER1_STOP_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw status bit for the interrupt triggered when the timer 1 stops. + */ +#define MCPWM_TIMER1_STOP_INT_RAW (BIT(1)) +#define MCPWM_TIMER1_STOP_INT_RAW_M (MCPWM_TIMER1_STOP_INT_RAW_V << MCPWM_TIMER1_STOP_INT_RAW_S) +#define MCPWM_TIMER1_STOP_INT_RAW_V 0x00000001U +#define MCPWM_TIMER1_STOP_INT_RAW_S 1 +/** MCPWM_TIMER2_STOP_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw status bit for the interrupt triggered when the timer 2 stops. + */ +#define MCPWM_TIMER2_STOP_INT_RAW (BIT(2)) +#define MCPWM_TIMER2_STOP_INT_RAW_M (MCPWM_TIMER2_STOP_INT_RAW_V << MCPWM_TIMER2_STOP_INT_RAW_S) +#define MCPWM_TIMER2_STOP_INT_RAW_V 0x00000001U +#define MCPWM_TIMER2_STOP_INT_RAW_S 2 +/** MCPWM_TIMER0_TEZ_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw status bit for the interrupt triggered by a PWM timer 0 TEZ event. + */ +#define MCPWM_TIMER0_TEZ_INT_RAW (BIT(3)) +#define MCPWM_TIMER0_TEZ_INT_RAW_M (MCPWM_TIMER0_TEZ_INT_RAW_V << MCPWM_TIMER0_TEZ_INT_RAW_S) +#define MCPWM_TIMER0_TEZ_INT_RAW_V 0x00000001U +#define MCPWM_TIMER0_TEZ_INT_RAW_S 3 +/** MCPWM_TIMER1_TEZ_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw status bit for the interrupt triggered by a PWM timer 1 TEZ event. + */ +#define MCPWM_TIMER1_TEZ_INT_RAW (BIT(4)) +#define MCPWM_TIMER1_TEZ_INT_RAW_M (MCPWM_TIMER1_TEZ_INT_RAW_V << MCPWM_TIMER1_TEZ_INT_RAW_S) +#define MCPWM_TIMER1_TEZ_INT_RAW_V 0x00000001U +#define MCPWM_TIMER1_TEZ_INT_RAW_S 4 +/** MCPWM_TIMER2_TEZ_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * The raw status bit for the interrupt triggered by a PWM timer 2 TEZ event. + */ +#define MCPWM_TIMER2_TEZ_INT_RAW (BIT(5)) +#define MCPWM_TIMER2_TEZ_INT_RAW_M (MCPWM_TIMER2_TEZ_INT_RAW_V << MCPWM_TIMER2_TEZ_INT_RAW_S) +#define MCPWM_TIMER2_TEZ_INT_RAW_V 0x00000001U +#define MCPWM_TIMER2_TEZ_INT_RAW_S 5 +/** MCPWM_TIMER0_TEP_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * The raw status bit for the interrupt triggered by a PWM timer 0 TEP event. + */ +#define MCPWM_TIMER0_TEP_INT_RAW (BIT(6)) +#define MCPWM_TIMER0_TEP_INT_RAW_M (MCPWM_TIMER0_TEP_INT_RAW_V << MCPWM_TIMER0_TEP_INT_RAW_S) +#define MCPWM_TIMER0_TEP_INT_RAW_V 0x00000001U +#define MCPWM_TIMER0_TEP_INT_RAW_S 6 +/** MCPWM_TIMER1_TEP_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * The raw status bit for the interrupt triggered by a PWM timer 1 TEP event. + */ +#define MCPWM_TIMER1_TEP_INT_RAW (BIT(7)) +#define MCPWM_TIMER1_TEP_INT_RAW_M (MCPWM_TIMER1_TEP_INT_RAW_V << MCPWM_TIMER1_TEP_INT_RAW_S) +#define MCPWM_TIMER1_TEP_INT_RAW_V 0x00000001U +#define MCPWM_TIMER1_TEP_INT_RAW_S 7 +/** MCPWM_TIMER2_TEP_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * The raw status bit for the interrupt triggered by a PWM timer 2 TEP event. + */ +#define MCPWM_TIMER2_TEP_INT_RAW (BIT(8)) +#define MCPWM_TIMER2_TEP_INT_RAW_M (MCPWM_TIMER2_TEP_INT_RAW_V << MCPWM_TIMER2_TEP_INT_RAW_S) +#define MCPWM_TIMER2_TEP_INT_RAW_V 0x00000001U +#define MCPWM_TIMER2_TEP_INT_RAW_S 8 +/** MCPWM_FAULT0_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * The raw status bit for the interrupt triggered when fault_event0 starts. + */ +#define MCPWM_FAULT0_INT_RAW (BIT(9)) +#define MCPWM_FAULT0_INT_RAW_M (MCPWM_FAULT0_INT_RAW_V << MCPWM_FAULT0_INT_RAW_S) +#define MCPWM_FAULT0_INT_RAW_V 0x00000001U +#define MCPWM_FAULT0_INT_RAW_S 9 +/** MCPWM_FAULT1_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * The raw status bit for the interrupt triggered when fault_event1 starts. + */ +#define MCPWM_FAULT1_INT_RAW (BIT(10)) +#define MCPWM_FAULT1_INT_RAW_M (MCPWM_FAULT1_INT_RAW_V << MCPWM_FAULT1_INT_RAW_S) +#define MCPWM_FAULT1_INT_RAW_V 0x00000001U +#define MCPWM_FAULT1_INT_RAW_S 10 +/** MCPWM_FAULT2_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; + * The raw status bit for the interrupt triggered when fault_event2 starts. + */ +#define MCPWM_FAULT2_INT_RAW (BIT(11)) +#define MCPWM_FAULT2_INT_RAW_M (MCPWM_FAULT2_INT_RAW_V << MCPWM_FAULT2_INT_RAW_S) +#define MCPWM_FAULT2_INT_RAW_V 0x00000001U +#define MCPWM_FAULT2_INT_RAW_S 11 +/** MCPWM_FAULT0_CLR_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * The raw status bit for the interrupt triggered when fault_event0 ends. + */ +#define MCPWM_FAULT0_CLR_INT_RAW (BIT(12)) +#define MCPWM_FAULT0_CLR_INT_RAW_M (MCPWM_FAULT0_CLR_INT_RAW_V << MCPWM_FAULT0_CLR_INT_RAW_S) +#define MCPWM_FAULT0_CLR_INT_RAW_V 0x00000001U +#define MCPWM_FAULT0_CLR_INT_RAW_S 12 +/** MCPWM_FAULT1_CLR_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; + * The raw status bit for the interrupt triggered when fault_event1 ends. + */ +#define MCPWM_FAULT1_CLR_INT_RAW (BIT(13)) +#define MCPWM_FAULT1_CLR_INT_RAW_M (MCPWM_FAULT1_CLR_INT_RAW_V << MCPWM_FAULT1_CLR_INT_RAW_S) +#define MCPWM_FAULT1_CLR_INT_RAW_V 0x00000001U +#define MCPWM_FAULT1_CLR_INT_RAW_S 13 +/** MCPWM_FAULT2_CLR_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; + * The raw status bit for the interrupt triggered when fault_event2 ends. + */ +#define MCPWM_FAULT2_CLR_INT_RAW (BIT(14)) +#define MCPWM_FAULT2_CLR_INT_RAW_M (MCPWM_FAULT2_CLR_INT_RAW_V << MCPWM_FAULT2_CLR_INT_RAW_S) +#define MCPWM_FAULT2_CLR_INT_RAW_V 0x00000001U +#define MCPWM_FAULT2_CLR_INT_RAW_S 14 +/** MCPWM_OP0_TEA_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; + * The raw status bit for the interrupt triggered by a PWM operator 0 TEA event + */ +#define MCPWM_OP0_TEA_INT_RAW (BIT(15)) +#define MCPWM_OP0_TEA_INT_RAW_M (MCPWM_OP0_TEA_INT_RAW_V << MCPWM_OP0_TEA_INT_RAW_S) +#define MCPWM_OP0_TEA_INT_RAW_V 0x00000001U +#define MCPWM_OP0_TEA_INT_RAW_S 15 +/** MCPWM_OP1_TEA_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0; + * The raw status bit for the interrupt triggered by a PWM operator 1 TEA event + */ +#define MCPWM_OP1_TEA_INT_RAW (BIT(16)) +#define MCPWM_OP1_TEA_INT_RAW_M (MCPWM_OP1_TEA_INT_RAW_V << MCPWM_OP1_TEA_INT_RAW_S) +#define MCPWM_OP1_TEA_INT_RAW_V 0x00000001U +#define MCPWM_OP1_TEA_INT_RAW_S 16 +/** MCPWM_OP2_TEA_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0; + * The raw status bit for the interrupt triggered by a PWM operator 2 TEA event + */ +#define MCPWM_OP2_TEA_INT_RAW (BIT(17)) +#define MCPWM_OP2_TEA_INT_RAW_M (MCPWM_OP2_TEA_INT_RAW_V << MCPWM_OP2_TEA_INT_RAW_S) +#define MCPWM_OP2_TEA_INT_RAW_V 0x00000001U +#define MCPWM_OP2_TEA_INT_RAW_S 17 +/** MCPWM_OP0_TEB_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0; + * The raw status bit for the interrupt triggered by a PWM operator 0 TEB event + */ +#define MCPWM_OP0_TEB_INT_RAW (BIT(18)) +#define MCPWM_OP0_TEB_INT_RAW_M (MCPWM_OP0_TEB_INT_RAW_V << MCPWM_OP0_TEB_INT_RAW_S) +#define MCPWM_OP0_TEB_INT_RAW_V 0x00000001U +#define MCPWM_OP0_TEB_INT_RAW_S 18 +/** MCPWM_OP1_TEB_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0; + * The raw status bit for the interrupt triggered by a PWM operator 1 TEB event + */ +#define MCPWM_OP1_TEB_INT_RAW (BIT(19)) +#define MCPWM_OP1_TEB_INT_RAW_M (MCPWM_OP1_TEB_INT_RAW_V << MCPWM_OP1_TEB_INT_RAW_S) +#define MCPWM_OP1_TEB_INT_RAW_V 0x00000001U +#define MCPWM_OP1_TEB_INT_RAW_S 19 +/** MCPWM_OP2_TEB_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0; + * The raw status bit for the interrupt triggered by a PWM operator 2 TEB event + */ +#define MCPWM_OP2_TEB_INT_RAW (BIT(20)) +#define MCPWM_OP2_TEB_INT_RAW_M (MCPWM_OP2_TEB_INT_RAW_V << MCPWM_OP2_TEB_INT_RAW_S) +#define MCPWM_OP2_TEB_INT_RAW_V 0x00000001U +#define MCPWM_OP2_TEB_INT_RAW_S 20 +/** MCPWM_FH0_CBC_INT_RAW : R/WTC/SS; bitpos: [21]; default: 0; + * The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on + * PWM0. + */ +#define MCPWM_FH0_CBC_INT_RAW (BIT(21)) +#define MCPWM_FH0_CBC_INT_RAW_M (MCPWM_FH0_CBC_INT_RAW_V << MCPWM_FH0_CBC_INT_RAW_S) +#define MCPWM_FH0_CBC_INT_RAW_V 0x00000001U +#define MCPWM_FH0_CBC_INT_RAW_S 21 +/** MCPWM_FH1_CBC_INT_RAW : R/WTC/SS; bitpos: [22]; default: 0; + * The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on + * PWM1. + */ +#define MCPWM_FH1_CBC_INT_RAW (BIT(22)) +#define MCPWM_FH1_CBC_INT_RAW_M (MCPWM_FH1_CBC_INT_RAW_V << MCPWM_FH1_CBC_INT_RAW_S) +#define MCPWM_FH1_CBC_INT_RAW_V 0x00000001U +#define MCPWM_FH1_CBC_INT_RAW_S 22 +/** MCPWM_FH2_CBC_INT_RAW : R/WTC/SS; bitpos: [23]; default: 0; + * The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on + * PWM2. + */ +#define MCPWM_FH2_CBC_INT_RAW (BIT(23)) +#define MCPWM_FH2_CBC_INT_RAW_M (MCPWM_FH2_CBC_INT_RAW_V << MCPWM_FH2_CBC_INT_RAW_S) +#define MCPWM_FH2_CBC_INT_RAW_V 0x00000001U +#define MCPWM_FH2_CBC_INT_RAW_S 23 +/** MCPWM_FH0_OST_INT_RAW : R/WTC/SS; bitpos: [24]; default: 0; + * The raw status bit for the interrupt triggered by a one-shot mode action on PWM0. + */ +#define MCPWM_FH0_OST_INT_RAW (BIT(24)) +#define MCPWM_FH0_OST_INT_RAW_M (MCPWM_FH0_OST_INT_RAW_V << MCPWM_FH0_OST_INT_RAW_S) +#define MCPWM_FH0_OST_INT_RAW_V 0x00000001U +#define MCPWM_FH0_OST_INT_RAW_S 24 +/** MCPWM_FH1_OST_INT_RAW : R/WTC/SS; bitpos: [25]; default: 0; + * The raw status bit for the interrupt triggered by a one-shot mode action on PWM1. + */ +#define MCPWM_FH1_OST_INT_RAW (BIT(25)) +#define MCPWM_FH1_OST_INT_RAW_M (MCPWM_FH1_OST_INT_RAW_V << MCPWM_FH1_OST_INT_RAW_S) +#define MCPWM_FH1_OST_INT_RAW_V 0x00000001U +#define MCPWM_FH1_OST_INT_RAW_S 25 +/** MCPWM_FH2_OST_INT_RAW : R/WTC/SS; bitpos: [26]; default: 0; + * The raw status bit for the interrupt triggered by a one-shot mode action on PWM2. + */ +#define MCPWM_FH2_OST_INT_RAW (BIT(26)) +#define MCPWM_FH2_OST_INT_RAW_M (MCPWM_FH2_OST_INT_RAW_V << MCPWM_FH2_OST_INT_RAW_S) +#define MCPWM_FH2_OST_INT_RAW_V 0x00000001U +#define MCPWM_FH2_OST_INT_RAW_S 26 +/** MCPWM_CAP0_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0; + * The raw status bit for the interrupt triggered by capture on channel 0. + */ +#define MCPWM_CAP0_INT_RAW (BIT(27)) +#define MCPWM_CAP0_INT_RAW_M (MCPWM_CAP0_INT_RAW_V << MCPWM_CAP0_INT_RAW_S) +#define MCPWM_CAP0_INT_RAW_V 0x00000001U +#define MCPWM_CAP0_INT_RAW_S 27 +/** MCPWM_CAP1_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0; + * The raw status bit for the interrupt triggered by capture on channel 1. + */ +#define MCPWM_CAP1_INT_RAW (BIT(28)) +#define MCPWM_CAP1_INT_RAW_M (MCPWM_CAP1_INT_RAW_V << MCPWM_CAP1_INT_RAW_S) +#define MCPWM_CAP1_INT_RAW_V 0x00000001U +#define MCPWM_CAP1_INT_RAW_S 28 +/** MCPWM_CAP2_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0; + * The raw status bit for the interrupt triggered by capture on channel 2. + */ +#define MCPWM_CAP2_INT_RAW (BIT(29)) +#define MCPWM_CAP2_INT_RAW_M (MCPWM_CAP2_INT_RAW_V << MCPWM_CAP2_INT_RAW_S) +#define MCPWM_CAP2_INT_RAW_V 0x00000001U +#define MCPWM_CAP2_INT_RAW_S 29 -#define MCMCPWM_INT_ST_MCPWM_REG(i) (REG_MCPWM_BASE(i) + 0x0118) -/* MCPWM_CAP2_INT_ST : RO ;bitpos:[29] ;default: 1'd0 ; */ -/*description: The masked status bit for interrupt triggered by captureon channel 2*/ -#define MCPWM_CAP2_INT_ST (BIT(29)) -#define MCPWM_CAP2_INT_ST_M (BIT(29)) -#define MCPWM_CAP2_INT_ST_V 0x1 -#define MCPWM_CAP2_INT_ST_S 29 -/* MCPWM_CAP1_INT_ST : RO ;bitpos:[28] ;default: 1'd0 ; */ -/*description: The masked status bit for interrupt triggered by captureon channel 1*/ -#define MCPWM_CAP1_INT_ST (BIT(28)) -#define MCPWM_CAP1_INT_ST_M (BIT(28)) -#define MCPWM_CAP1_INT_ST_V 0x1 -#define MCPWM_CAP1_INT_ST_S 28 -/* MCPWM_CAP0_INT_ST : RO ;bitpos:[27] ;default: 1'd0 ; */ -/*description: The masked status bit for interrupt triggered by captureon channel 0*/ -#define MCPWM_CAP0_INT_ST (BIT(27)) -#define MCPWM_CAP0_INT_ST_M (BIT(27)) -#define MCPWM_CAP0_INT_ST_V 0x1 -#define MCPWM_CAP0_INT_ST_S 27 -/* MCPWM_FH2_OST_INT_ST : RO ;bitpos:[26] ;default: 1'd0 ; */ -/*description: The masked status bit for interrupt triggered by an one-shot mode action on PWM2*/ -#define MCPWM_FH2_OST_INT_ST (BIT(26)) -#define MCPWM_FH2_OST_INT_ST_M (BIT(26)) -#define MCPWM_FH2_OST_INT_ST_V 0x1 -#define MCPWM_FH2_OST_INT_ST_S 26 -/* MCPWM_FH1_OST_INT_ST : RO ;bitpos:[25] ;default: 1'd0 ; */ -/*description: The masked status bit for interrupt triggered by an one-shot mode action on PWM0*/ -#define MCPWM_FH1_OST_INT_ST (BIT(25)) -#define MCPWM_FH1_OST_INT_ST_M (BIT(25)) -#define MCPWM_FH1_OST_INT_ST_V 0x1 -#define MCPWM_FH1_OST_INT_ST_S 25 -/* MCPWM_FH0_OST_INT_ST : RO ;bitpos:[24] ;default: 1'd0 ; */ -/*description: The masked status bit for interrupt triggered by an one-shot mode action on PWM0*/ -#define MCPWM_FH0_OST_INT_ST (BIT(24)) -#define MCPWM_FH0_OST_INT_ST_M (BIT(24)) -#define MCPWM_FH0_OST_INT_ST_V 0x1 -#define MCPWM_FH0_OST_INT_ST_S 24 -/* MCPWM_FH2_CBC_INT_ST : RO ;bitpos:[23] ;default: 1'd0 ; */ -/*description: The masked status bit for interrupt triggered by an cycle-by-cycle - mode action on PWM2*/ -#define MCPWM_FH2_CBC_INT_ST (BIT(23)) -#define MCPWM_FH2_CBC_INT_ST_M (BIT(23)) -#define MCPWM_FH2_CBC_INT_ST_V 0x1 -#define MCPWM_FH2_CBC_INT_ST_S 23 -/* MCPWM_FH1_CBC_INT_ST : RO ;bitpos:[22] ;default: 1'd0 ; */ -/*description: The masked status bit for interrupt triggered by an cycle-by-cycle - mode action on PWM1*/ -#define MCPWM_FH1_CBC_INT_ST (BIT(22)) -#define MCPWM_FH1_CBC_INT_ST_M (BIT(22)) -#define MCPWM_FH1_CBC_INT_ST_V 0x1 -#define MCPWM_FH1_CBC_INT_ST_S 22 -/* MCPWM_FH0_CBC_INT_ST : RO ;bitpos:[21] ;default: 1'd0 ; */ -/*description: The masked status bit for interrupt triggered by an cycle-by-cycle - mode action on PWM0*/ -#define MCPWM_FH0_CBC_INT_ST (BIT(21)) -#define MCPWM_FH0_CBC_INT_ST_M (BIT(21)) -#define MCPWM_FH0_CBC_INT_ST_V 0x1 -#define MCPWM_FH0_CBC_INT_ST_S 21 -/* MCPWM_OP2_TEB_INT_ST : RO ;bitpos:[20] ;default: 1'd0 ; */ -/*description: The masked status bit for interrupt triggered by a PWM operator 2 TEB event*/ -#define MCPWM_OP2_TEB_INT_ST (BIT(20)) -#define MCPWM_OP2_TEB_INT_ST_M (BIT(20)) -#define MCPWM_OP2_TEB_INT_ST_V 0x1 -#define MCPWM_OP2_TEB_INT_ST_S 20 -/* MCPWM_OP1_TEB_INT_ST : RO ;bitpos:[19] ;default: 1'd0 ; */ -/*description: The masked status bit for interrupt triggered by a PWM operator 1 TEB event*/ -#define MCPWM_OP1_TEB_INT_ST (BIT(19)) -#define MCPWM_OP1_TEB_INT_ST_M (BIT(19)) -#define MCPWM_OP1_TEB_INT_ST_V 0x1 -#define MCPWM_OP1_TEB_INT_ST_S 19 -/* MCPWM_OP0_TEB_INT_ST : RO ;bitpos:[18] ;default: 1'd0 ; */ -/*description: The masked status bit for interrupt triggered by a PWM operator 0 TEB event*/ -#define MCPWM_OP0_TEB_INT_ST (BIT(18)) -#define MCPWM_OP0_TEB_INT_ST_M (BIT(18)) -#define MCPWM_OP0_TEB_INT_ST_V 0x1 -#define MCPWM_OP0_TEB_INT_ST_S 18 -/* MCPWM_OP2_TEA_INT_ST : RO ;bitpos:[17] ;default: 1'd0 ; */ -/*description: The masked status bit for interrupt triggered by a PWM operator 2 TEA event*/ -#define MCPWM_OP2_TEA_INT_ST (BIT(17)) -#define MCPWM_OP2_TEA_INT_ST_M (BIT(17)) -#define MCPWM_OP2_TEA_INT_ST_V 0x1 -#define MCPWM_OP2_TEA_INT_ST_S 17 -/* MCPWM_OP1_TEA_INT_ST : RO ;bitpos:[16] ;default: 1'd0 ; */ -/*description: The masked status bit for interrupt triggered by a PWM operator 1 TEA event*/ -#define MCPWM_OP1_TEA_INT_ST (BIT(16)) -#define MCPWM_OP1_TEA_INT_ST_M (BIT(16)) -#define MCPWM_OP1_TEA_INT_ST_V 0x1 -#define MCPWM_OP1_TEA_INT_ST_S 16 -/* MCPWM_OP0_TEA_INT_ST : RO ;bitpos:[15] ;default: 1'd0 ; */ -/*description: The masked status bit for interrupt triggered by a PWM operator 0 TEA event*/ -#define MCPWM_OP0_TEA_INT_ST (BIT(15)) -#define MCPWM_OP0_TEA_INT_ST_M (BIT(15)) -#define MCPWM_OP0_TEA_INT_ST_V 0x1 -#define MCPWM_OP0_TEA_INT_ST_S 15 -/* MCPWM_FAULT2_CLR_INT_ST : RO ;bitpos:[14] ;default: 1'd0 ; */ -/*description: The masked status bit for interrupt triggered when event_f2 ends*/ -#define MCPWM_FAULT2_CLR_INT_ST (BIT(14)) -#define MCPWM_FAULT2_CLR_INT_ST_M (BIT(14)) -#define MCPWM_FAULT2_CLR_INT_ST_V 0x1 -#define MCPWM_FAULT2_CLR_INT_ST_S 14 -/* MCPWM_FAULT1_CLR_INT_ST : RO ;bitpos:[13] ;default: 1'd0 ; */ -/*description: The masked status bit for interrupt triggered when event_f1 ends*/ -#define MCPWM_FAULT1_CLR_INT_ST (BIT(13)) -#define MCPWM_FAULT1_CLR_INT_ST_M (BIT(13)) -#define MCPWM_FAULT1_CLR_INT_ST_V 0x1 -#define MCPWM_FAULT1_CLR_INT_ST_S 13 -/* MCPWM_FAULT0_CLR_INT_ST : RO ;bitpos:[12] ;default: 1'd0 ; */ -/*description: The masked status bit for interrupt triggered when event_f0 ends*/ -#define MCPWM_FAULT0_CLR_INT_ST (BIT(12)) -#define MCPWM_FAULT0_CLR_INT_ST_M (BIT(12)) -#define MCPWM_FAULT0_CLR_INT_ST_V 0x1 -#define MCPWM_FAULT0_CLR_INT_ST_S 12 -/* MCPWM_FAULT2_INT_ST : RO ;bitpos:[11] ;default: 1'd0 ; */ -/*description: The masked status bit for interrupt triggered when event_f2 starts*/ -#define MCPWM_FAULT2_INT_ST (BIT(11)) -#define MCPWM_FAULT2_INT_ST_M (BIT(11)) -#define MCPWM_FAULT2_INT_ST_V 0x1 -#define MCPWM_FAULT2_INT_ST_S 11 -/* MCPWM_FAULT1_INT_ST : RO ;bitpos:[10] ;default: 1'd0 ; */ -/*description: The masked status bit for interrupt triggered when event_f1 starts*/ -#define MCPWM_FAULT1_INT_ST (BIT(10)) -#define MCPWM_FAULT1_INT_ST_M (BIT(10)) -#define MCPWM_FAULT1_INT_ST_V 0x1 -#define MCPWM_FAULT1_INT_ST_S 10 -/* MCPWM_FAULT0_INT_ST : RO ;bitpos:[9] ;default: 1'd0 ; */ -/*description: The masked status bit for interrupt triggered when event_f0 starts*/ -#define MCPWM_FAULT0_INT_ST (BIT(9)) -#define MCPWM_FAULT0_INT_ST_M (BIT(9)) -#define MCPWM_FAULT0_INT_ST_V 0x1 -#define MCPWM_FAULT0_INT_ST_S 9 -/* MCPWM_TIMER2_TEP_INT_ST : RO ;bitpos:[8] ;default: 1'h0 ; */ -/*description: The masked status bit for interrupt triggered by a PWM timer 2 TEP event*/ -#define MCPWM_TIMER2_TEP_INT_ST (BIT(8)) -#define MCPWM_TIMER2_TEP_INT_ST_M (BIT(8)) -#define MCPWM_TIMER2_TEP_INT_ST_V 0x1 -#define MCPWM_TIMER2_TEP_INT_ST_S 8 -/* MCPWM_TIMER1_TEP_INT_ST : RO ;bitpos:[7] ;default: 1'h0 ; */ -/*description: The masked status bit for interrupt triggered by a PWM timer 1 TEP event*/ -#define MCPWM_TIMER1_TEP_INT_ST (BIT(7)) -#define MCPWM_TIMER1_TEP_INT_ST_M (BIT(7)) -#define MCPWM_TIMER1_TEP_INT_ST_V 0x1 -#define MCPWM_TIMER1_TEP_INT_ST_S 7 -/* MCPWM_TIMER0_TEP_INT_ST : RO ;bitpos:[6] ;default: 1'h0 ; */ -/*description: The masked status bit for interrupt triggered by a PWM timer 0 TEP event*/ -#define MCPWM_TIMER0_TEP_INT_ST (BIT(6)) -#define MCPWM_TIMER0_TEP_INT_ST_M (BIT(6)) -#define MCPWM_TIMER0_TEP_INT_ST_V 0x1 -#define MCPWM_TIMER0_TEP_INT_ST_S 6 -/* MCPWM_TIMER2_TEZ_INT_ST : RO ;bitpos:[5] ;default: 1'h0 ; */ -/*description: The masked status bit for interrupt triggered by a PWM timer 2 TEZ event*/ -#define MCPWM_TIMER2_TEZ_INT_ST (BIT(5)) -#define MCPWM_TIMER2_TEZ_INT_ST_M (BIT(5)) -#define MCPWM_TIMER2_TEZ_INT_ST_V 0x1 -#define MCPWM_TIMER2_TEZ_INT_ST_S 5 -/* MCPWM_TIMER1_TEZ_INT_ST : RO ;bitpos:[4] ;default: 1'h0 ; */ -/*description: The masked status bit for interrupt triggered by a PWM timer 1 TEZ event*/ -#define MCPWM_TIMER1_TEZ_INT_ST (BIT(4)) -#define MCPWM_TIMER1_TEZ_INT_ST_M (BIT(4)) -#define MCPWM_TIMER1_TEZ_INT_ST_V 0x1 -#define MCPWM_TIMER1_TEZ_INT_ST_S 4 -/* MCPWM_TIMER0_TEZ_INT_ST : RO ;bitpos:[3] ;default: 1'h0 ; */ -/*description: The masked status bit for interrupt triggered by a PWM timer 0 TEZ event*/ -#define MCPWM_TIMER0_TEZ_INT_ST (BIT(3)) -#define MCPWM_TIMER0_TEZ_INT_ST_M (BIT(3)) -#define MCPWM_TIMER0_TEZ_INT_ST_V 0x1 -#define MCPWM_TIMER0_TEZ_INT_ST_S 3 -/* MCPWM_TIMER2_STOP_INT_ST : RO ;bitpos:[2] ;default: 1'h0 ; */ -/*description: The masked status bit for interrupt triggered when timer 2 stops*/ -#define MCPWM_TIMER2_STOP_INT_ST (BIT(2)) -#define MCPWM_TIMER2_STOP_INT_ST_M (BIT(2)) -#define MCPWM_TIMER2_STOP_INT_ST_V 0x1 -#define MCPWM_TIMER2_STOP_INT_ST_S 2 -/* MCPWM_TIMER1_STOP_INT_ST : RO ;bitpos:[1] ;default: 1'h0 ; */ -/*description: The masked status bit for interrupt triggered when timer 1 stops*/ -#define MCPWM_TIMER1_STOP_INT_ST (BIT(1)) -#define MCPWM_TIMER1_STOP_INT_ST_M (BIT(1)) -#define MCPWM_TIMER1_STOP_INT_ST_V 0x1 -#define MCPWM_TIMER1_STOP_INT_ST_S 1 -/* MCPWM_TIMER0_STOP_INT_ST : RO ;bitpos:[0] ;default: 1'h0 ; */ -/*description: The masked status bit for interrupt triggered when timer 0 stops*/ -#define MCPWM_TIMER0_STOP_INT_ST (BIT(0)) -#define MCPWM_TIMER0_STOP_INT_ST_M (BIT(0)) -#define MCPWM_TIMER0_STOP_INT_ST_V 0x1 +/** MCPWM_INT_ST_REG register + * Masked interrupt status + */ +#define MCPWM_INT_ST_REG(i) (DR_REG_MCPWM_BASE(i) + 0x118) +/** MCPWM_TIMER0_STOP_INT_ST : RO; bitpos: [0]; default: 0; + * The masked status bit for the interrupt triggered when the timer 0 stops. + */ +#define MCPWM_TIMER0_STOP_INT_ST (BIT(0)) +#define MCPWM_TIMER0_STOP_INT_ST_M (MCPWM_TIMER0_STOP_INT_ST_V << MCPWM_TIMER0_STOP_INT_ST_S) +#define MCPWM_TIMER0_STOP_INT_ST_V 0x00000001U #define MCPWM_TIMER0_STOP_INT_ST_S 0 +/** MCPWM_TIMER1_STOP_INT_ST : RO; bitpos: [1]; default: 0; + * The masked status bit for the interrupt triggered when the timer 1 stops. + */ +#define MCPWM_TIMER1_STOP_INT_ST (BIT(1)) +#define MCPWM_TIMER1_STOP_INT_ST_M (MCPWM_TIMER1_STOP_INT_ST_V << MCPWM_TIMER1_STOP_INT_ST_S) +#define MCPWM_TIMER1_STOP_INT_ST_V 0x00000001U +#define MCPWM_TIMER1_STOP_INT_ST_S 1 +/** MCPWM_TIMER2_STOP_INT_ST : RO; bitpos: [2]; default: 0; + * The masked status bit for the interrupt triggered when the timer 2 stops. + */ +#define MCPWM_TIMER2_STOP_INT_ST (BIT(2)) +#define MCPWM_TIMER2_STOP_INT_ST_M (MCPWM_TIMER2_STOP_INT_ST_V << MCPWM_TIMER2_STOP_INT_ST_S) +#define MCPWM_TIMER2_STOP_INT_ST_V 0x00000001U +#define MCPWM_TIMER2_STOP_INT_ST_S 2 +/** MCPWM_TIMER0_TEZ_INT_ST : RO; bitpos: [3]; default: 0; + * The masked status bit for the interrupt triggered by a PWM timer 0 TEZ event. + */ +#define MCPWM_TIMER0_TEZ_INT_ST (BIT(3)) +#define MCPWM_TIMER0_TEZ_INT_ST_M (MCPWM_TIMER0_TEZ_INT_ST_V << MCPWM_TIMER0_TEZ_INT_ST_S) +#define MCPWM_TIMER0_TEZ_INT_ST_V 0x00000001U +#define MCPWM_TIMER0_TEZ_INT_ST_S 3 +/** MCPWM_TIMER1_TEZ_INT_ST : RO; bitpos: [4]; default: 0; + * The masked status bit for the interrupt triggered by a PWM timer 1 TEZ event. + */ +#define MCPWM_TIMER1_TEZ_INT_ST (BIT(4)) +#define MCPWM_TIMER1_TEZ_INT_ST_M (MCPWM_TIMER1_TEZ_INT_ST_V << MCPWM_TIMER1_TEZ_INT_ST_S) +#define MCPWM_TIMER1_TEZ_INT_ST_V 0x00000001U +#define MCPWM_TIMER1_TEZ_INT_ST_S 4 +/** MCPWM_TIMER2_TEZ_INT_ST : RO; bitpos: [5]; default: 0; + * The masked status bit for the interrupt triggered by a PWM timer 2 TEZ event. + */ +#define MCPWM_TIMER2_TEZ_INT_ST (BIT(5)) +#define MCPWM_TIMER2_TEZ_INT_ST_M (MCPWM_TIMER2_TEZ_INT_ST_V << MCPWM_TIMER2_TEZ_INT_ST_S) +#define MCPWM_TIMER2_TEZ_INT_ST_V 0x00000001U +#define MCPWM_TIMER2_TEZ_INT_ST_S 5 +/** MCPWM_TIMER0_TEP_INT_ST : RO; bitpos: [6]; default: 0; + * The masked status bit for the interrupt triggered by a PWM timer 0 TEP event. + */ +#define MCPWM_TIMER0_TEP_INT_ST (BIT(6)) +#define MCPWM_TIMER0_TEP_INT_ST_M (MCPWM_TIMER0_TEP_INT_ST_V << MCPWM_TIMER0_TEP_INT_ST_S) +#define MCPWM_TIMER0_TEP_INT_ST_V 0x00000001U +#define MCPWM_TIMER0_TEP_INT_ST_S 6 +/** MCPWM_TIMER1_TEP_INT_ST : RO; bitpos: [7]; default: 0; + * The masked status bit for the interrupt triggered by a PWM timer 1 TEP event. + */ +#define MCPWM_TIMER1_TEP_INT_ST (BIT(7)) +#define MCPWM_TIMER1_TEP_INT_ST_M (MCPWM_TIMER1_TEP_INT_ST_V << MCPWM_TIMER1_TEP_INT_ST_S) +#define MCPWM_TIMER1_TEP_INT_ST_V 0x00000001U +#define MCPWM_TIMER1_TEP_INT_ST_S 7 +/** MCPWM_TIMER2_TEP_INT_ST : RO; bitpos: [8]; default: 0; + * The masked status bit for the interrupt triggered by a PWM timer 2 TEP event. + */ +#define MCPWM_TIMER2_TEP_INT_ST (BIT(8)) +#define MCPWM_TIMER2_TEP_INT_ST_M (MCPWM_TIMER2_TEP_INT_ST_V << MCPWM_TIMER2_TEP_INT_ST_S) +#define MCPWM_TIMER2_TEP_INT_ST_V 0x00000001U +#define MCPWM_TIMER2_TEP_INT_ST_S 8 +/** MCPWM_FAULT0_INT_ST : RO; bitpos: [9]; default: 0; + * The masked status bit for the interrupt triggered when fault_event0 starts. + */ +#define MCPWM_FAULT0_INT_ST (BIT(9)) +#define MCPWM_FAULT0_INT_ST_M (MCPWM_FAULT0_INT_ST_V << MCPWM_FAULT0_INT_ST_S) +#define MCPWM_FAULT0_INT_ST_V 0x00000001U +#define MCPWM_FAULT0_INT_ST_S 9 +/** MCPWM_FAULT1_INT_ST : RO; bitpos: [10]; default: 0; + * The masked status bit for the interrupt triggered when fault_event1 starts. + */ +#define MCPWM_FAULT1_INT_ST (BIT(10)) +#define MCPWM_FAULT1_INT_ST_M (MCPWM_FAULT1_INT_ST_V << MCPWM_FAULT1_INT_ST_S) +#define MCPWM_FAULT1_INT_ST_V 0x00000001U +#define MCPWM_FAULT1_INT_ST_S 10 +/** MCPWM_FAULT2_INT_ST : RO; bitpos: [11]; default: 0; + * The masked status bit for the interrupt triggered when fault_event2 starts. + */ +#define MCPWM_FAULT2_INT_ST (BIT(11)) +#define MCPWM_FAULT2_INT_ST_M (MCPWM_FAULT2_INT_ST_V << MCPWM_FAULT2_INT_ST_S) +#define MCPWM_FAULT2_INT_ST_V 0x00000001U +#define MCPWM_FAULT2_INT_ST_S 11 +/** MCPWM_FAULT0_CLR_INT_ST : RO; bitpos: [12]; default: 0; + * The masked status bit for the interrupt triggered when fault_event0 ends. + */ +#define MCPWM_FAULT0_CLR_INT_ST (BIT(12)) +#define MCPWM_FAULT0_CLR_INT_ST_M (MCPWM_FAULT0_CLR_INT_ST_V << MCPWM_FAULT0_CLR_INT_ST_S) +#define MCPWM_FAULT0_CLR_INT_ST_V 0x00000001U +#define MCPWM_FAULT0_CLR_INT_ST_S 12 +/** MCPWM_FAULT1_CLR_INT_ST : RO; bitpos: [13]; default: 0; + * The masked status bit for the interrupt triggered when fault_event1 ends. + */ +#define MCPWM_FAULT1_CLR_INT_ST (BIT(13)) +#define MCPWM_FAULT1_CLR_INT_ST_M (MCPWM_FAULT1_CLR_INT_ST_V << MCPWM_FAULT1_CLR_INT_ST_S) +#define MCPWM_FAULT1_CLR_INT_ST_V 0x00000001U +#define MCPWM_FAULT1_CLR_INT_ST_S 13 +/** MCPWM_FAULT2_CLR_INT_ST : RO; bitpos: [14]; default: 0; + * The masked status bit for the interrupt triggered when fault_event2 ends. + */ +#define MCPWM_FAULT2_CLR_INT_ST (BIT(14)) +#define MCPWM_FAULT2_CLR_INT_ST_M (MCPWM_FAULT2_CLR_INT_ST_V << MCPWM_FAULT2_CLR_INT_ST_S) +#define MCPWM_FAULT2_CLR_INT_ST_V 0x00000001U +#define MCPWM_FAULT2_CLR_INT_ST_S 14 +/** MCPWM_OP0_TEA_INT_ST : RO; bitpos: [15]; default: 0; + * The masked status bit for the interrupt triggered by a PWM operator 0 TEA event + */ +#define MCPWM_OP0_TEA_INT_ST (BIT(15)) +#define MCPWM_OP0_TEA_INT_ST_M (MCPWM_OP0_TEA_INT_ST_V << MCPWM_OP0_TEA_INT_ST_S) +#define MCPWM_OP0_TEA_INT_ST_V 0x00000001U +#define MCPWM_OP0_TEA_INT_ST_S 15 +/** MCPWM_OP1_TEA_INT_ST : RO; bitpos: [16]; default: 0; + * The masked status bit for the interrupt triggered by a PWM operator 1 TEA event + */ +#define MCPWM_OP1_TEA_INT_ST (BIT(16)) +#define MCPWM_OP1_TEA_INT_ST_M (MCPWM_OP1_TEA_INT_ST_V << MCPWM_OP1_TEA_INT_ST_S) +#define MCPWM_OP1_TEA_INT_ST_V 0x00000001U +#define MCPWM_OP1_TEA_INT_ST_S 16 +/** MCPWM_OP2_TEA_INT_ST : RO; bitpos: [17]; default: 0; + * The masked status bit for the interrupt triggered by a PWM operator 2 TEA event + */ +#define MCPWM_OP2_TEA_INT_ST (BIT(17)) +#define MCPWM_OP2_TEA_INT_ST_M (MCPWM_OP2_TEA_INT_ST_V << MCPWM_OP2_TEA_INT_ST_S) +#define MCPWM_OP2_TEA_INT_ST_V 0x00000001U +#define MCPWM_OP2_TEA_INT_ST_S 17 +/** MCPWM_OP0_TEB_INT_ST : RO; bitpos: [18]; default: 0; + * The masked status bit for the interrupt triggered by a PWM operator 0 TEB event + */ +#define MCPWM_OP0_TEB_INT_ST (BIT(18)) +#define MCPWM_OP0_TEB_INT_ST_M (MCPWM_OP0_TEB_INT_ST_V << MCPWM_OP0_TEB_INT_ST_S) +#define MCPWM_OP0_TEB_INT_ST_V 0x00000001U +#define MCPWM_OP0_TEB_INT_ST_S 18 +/** MCPWM_OP1_TEB_INT_ST : RO; bitpos: [19]; default: 0; + * The masked status bit for the interrupt triggered by a PWM operator 1 TEB event + */ +#define MCPWM_OP1_TEB_INT_ST (BIT(19)) +#define MCPWM_OP1_TEB_INT_ST_M (MCPWM_OP1_TEB_INT_ST_V << MCPWM_OP1_TEB_INT_ST_S) +#define MCPWM_OP1_TEB_INT_ST_V 0x00000001U +#define MCPWM_OP1_TEB_INT_ST_S 19 +/** MCPWM_OP2_TEB_INT_ST : RO; bitpos: [20]; default: 0; + * The masked status bit for the interrupt triggered by a PWM operator 2 TEB event + */ +#define MCPWM_OP2_TEB_INT_ST (BIT(20)) +#define MCPWM_OP2_TEB_INT_ST_M (MCPWM_OP2_TEB_INT_ST_V << MCPWM_OP2_TEB_INT_ST_S) +#define MCPWM_OP2_TEB_INT_ST_V 0x00000001U +#define MCPWM_OP2_TEB_INT_ST_S 20 +/** MCPWM_FH0_CBC_INT_ST : RO; bitpos: [21]; default: 0; + * The masked status bit for the interrupt triggered by a cycle-by-cycle mode action + * on PWM0. + */ +#define MCPWM_FH0_CBC_INT_ST (BIT(21)) +#define MCPWM_FH0_CBC_INT_ST_M (MCPWM_FH0_CBC_INT_ST_V << MCPWM_FH0_CBC_INT_ST_S) +#define MCPWM_FH0_CBC_INT_ST_V 0x00000001U +#define MCPWM_FH0_CBC_INT_ST_S 21 +/** MCPWM_FH1_CBC_INT_ST : RO; bitpos: [22]; default: 0; + * The masked status bit for the interrupt triggered by a cycle-by-cycle mode action + * on PWM1. + */ +#define MCPWM_FH1_CBC_INT_ST (BIT(22)) +#define MCPWM_FH1_CBC_INT_ST_M (MCPWM_FH1_CBC_INT_ST_V << MCPWM_FH1_CBC_INT_ST_S) +#define MCPWM_FH1_CBC_INT_ST_V 0x00000001U +#define MCPWM_FH1_CBC_INT_ST_S 22 +/** MCPWM_FH2_CBC_INT_ST : RO; bitpos: [23]; default: 0; + * The masked status bit for the interrupt triggered by a cycle-by-cycle mode action + * on PWM2. + */ +#define MCPWM_FH2_CBC_INT_ST (BIT(23)) +#define MCPWM_FH2_CBC_INT_ST_M (MCPWM_FH2_CBC_INT_ST_V << MCPWM_FH2_CBC_INT_ST_S) +#define MCPWM_FH2_CBC_INT_ST_V 0x00000001U +#define MCPWM_FH2_CBC_INT_ST_S 23 +/** MCPWM_FH0_OST_INT_ST : RO; bitpos: [24]; default: 0; + * The masked status bit for the interrupt triggered by a one-shot mode action on PWM0. + */ +#define MCPWM_FH0_OST_INT_ST (BIT(24)) +#define MCPWM_FH0_OST_INT_ST_M (MCPWM_FH0_OST_INT_ST_V << MCPWM_FH0_OST_INT_ST_S) +#define MCPWM_FH0_OST_INT_ST_V 0x00000001U +#define MCPWM_FH0_OST_INT_ST_S 24 +/** MCPWM_FH1_OST_INT_ST : RO; bitpos: [25]; default: 0; + * The masked status bit for the interrupt triggered by a one-shot mode action on PWM1. + */ +#define MCPWM_FH1_OST_INT_ST (BIT(25)) +#define MCPWM_FH1_OST_INT_ST_M (MCPWM_FH1_OST_INT_ST_V << MCPWM_FH1_OST_INT_ST_S) +#define MCPWM_FH1_OST_INT_ST_V 0x00000001U +#define MCPWM_FH1_OST_INT_ST_S 25 +/** MCPWM_FH2_OST_INT_ST : RO; bitpos: [26]; default: 0; + * The masked status bit for the interrupt triggered by a one-shot mode action on PWM2. + */ +#define MCPWM_FH2_OST_INT_ST (BIT(26)) +#define MCPWM_FH2_OST_INT_ST_M (MCPWM_FH2_OST_INT_ST_V << MCPWM_FH2_OST_INT_ST_S) +#define MCPWM_FH2_OST_INT_ST_V 0x00000001U +#define MCPWM_FH2_OST_INT_ST_S 26 +/** MCPWM_CAP0_INT_ST : RO; bitpos: [27]; default: 0; + * The masked status bit for the interrupt triggered by capture on channel 0. + */ +#define MCPWM_CAP0_INT_ST (BIT(27)) +#define MCPWM_CAP0_INT_ST_M (MCPWM_CAP0_INT_ST_V << MCPWM_CAP0_INT_ST_S) +#define MCPWM_CAP0_INT_ST_V 0x00000001U +#define MCPWM_CAP0_INT_ST_S 27 +/** MCPWM_CAP1_INT_ST : RO; bitpos: [28]; default: 0; + * The masked status bit for the interrupt triggered by capture on channel 1. + */ +#define MCPWM_CAP1_INT_ST (BIT(28)) +#define MCPWM_CAP1_INT_ST_M (MCPWM_CAP1_INT_ST_V << MCPWM_CAP1_INT_ST_S) +#define MCPWM_CAP1_INT_ST_V 0x00000001U +#define MCPWM_CAP1_INT_ST_S 28 +/** MCPWM_CAP2_INT_ST : RO; bitpos: [29]; default: 0; + * The masked status bit for the interrupt triggered by capture on channel 2. + */ +#define MCPWM_CAP2_INT_ST (BIT(29)) +#define MCPWM_CAP2_INT_ST_M (MCPWM_CAP2_INT_ST_V << MCPWM_CAP2_INT_ST_S) +#define MCPWM_CAP2_INT_ST_V 0x00000001U +#define MCPWM_CAP2_INT_ST_S 29 -#define MCMCPWM_INT_CLR_MCPWM_REG(i) (REG_MCPWM_BASE(i) + 0x011c) -/* MCPWM_CAP2_INT_CLR : WO ;bitpos:[29] ;default: 1'd0 ; */ -/*description: Set this bit to clear interrupt triggered by captureon channel 2*/ -#define MCPWM_CAP2_INT_CLR (BIT(29)) -#define MCPWM_CAP2_INT_CLR_M (BIT(29)) -#define MCPWM_CAP2_INT_CLR_V 0x1 -#define MCPWM_CAP2_INT_CLR_S 29 -/* MCPWM_CAP1_INT_CLR : WO ;bitpos:[28] ;default: 1'd0 ; */ -/*description: Set this bit to clear interrupt triggered by captureon channel 1*/ -#define MCPWM_CAP1_INT_CLR (BIT(28)) -#define MCPWM_CAP1_INT_CLR_M (BIT(28)) -#define MCPWM_CAP1_INT_CLR_V 0x1 -#define MCPWM_CAP1_INT_CLR_S 28 -/* MCPWM_CAP0_INT_CLR : WO ;bitpos:[27] ;default: 1'd0 ; */ -/*description: Set this bit to clear interrupt triggered by captureon channel 0*/ -#define MCPWM_CAP0_INT_CLR (BIT(27)) -#define MCPWM_CAP0_INT_CLR_M (BIT(27)) -#define MCPWM_CAP0_INT_CLR_V 0x1 -#define MCPWM_CAP0_INT_CLR_S 27 -/* MCPWM_FH2_OST_INT_CLR : WO ;bitpos:[26] ;default: 1'd0 ; */ -/*description: Set this bit to clear interrupt triggered by an one-shot mode action on PWM2*/ -#define MCPWM_FH2_OST_INT_CLR (BIT(26)) -#define MCPWM_FH2_OST_INT_CLR_M (BIT(26)) -#define MCPWM_FH2_OST_INT_CLR_V 0x1 -#define MCPWM_FH2_OST_INT_CLR_S 26 -/* MCPWM_FH1_OST_INT_CLR : WO ;bitpos:[25] ;default: 1'd0 ; */ -/*description: Set this bit to clear interrupt triggered by an one-shot mode action on PWM0*/ -#define MCPWM_FH1_OST_INT_CLR (BIT(25)) -#define MCPWM_FH1_OST_INT_CLR_M (BIT(25)) -#define MCPWM_FH1_OST_INT_CLR_V 0x1 -#define MCPWM_FH1_OST_INT_CLR_S 25 -/* MCPWM_FH0_OST_INT_CLR : WO ;bitpos:[24] ;default: 1'd0 ; */ -/*description: Set this bit to clear interrupt triggered by an one-shot mode action on PWM0*/ -#define MCPWM_FH0_OST_INT_CLR (BIT(24)) -#define MCPWM_FH0_OST_INT_CLR_M (BIT(24)) -#define MCPWM_FH0_OST_INT_CLR_V 0x1 -#define MCPWM_FH0_OST_INT_CLR_S 24 -/* MCPWM_FH2_CBC_INT_CLR : WO ;bitpos:[23] ;default: 1'd0 ; */ -/*description: Set this bit to clear interrupt triggered by an cycle-by-cycle - mode action on PWM2*/ -#define MCPWM_FH2_CBC_INT_CLR (BIT(23)) -#define MCPWM_FH2_CBC_INT_CLR_M (BIT(23)) -#define MCPWM_FH2_CBC_INT_CLR_V 0x1 -#define MCPWM_FH2_CBC_INT_CLR_S 23 -/* MCPWM_FH1_CBC_INT_CLR : WO ;bitpos:[22] ;default: 1'd0 ; */ -/*description: Set this bit to clear interrupt triggered by an cycle-by-cycle - mode action on PWM1*/ -#define MCPWM_FH1_CBC_INT_CLR (BIT(22)) -#define MCPWM_FH1_CBC_INT_CLR_M (BIT(22)) -#define MCPWM_FH1_CBC_INT_CLR_V 0x1 -#define MCPWM_FH1_CBC_INT_CLR_S 22 -/* MCPWM_FH0_CBC_INT_CLR : WO ;bitpos:[21] ;default: 1'd0 ; */ -/*description: Set this bit to clear interrupt triggered by an cycle-by-cycle - mode action on PWM0*/ -#define MCPWM_FH0_CBC_INT_CLR (BIT(21)) -#define MCPWM_FH0_CBC_INT_CLR_M (BIT(21)) -#define MCPWM_FH0_CBC_INT_CLR_V 0x1 -#define MCPWM_FH0_CBC_INT_CLR_S 21 -/* MCPWM_OP2_TEB_INT_CLR : WO ;bitpos:[20] ;default: 1'd0 ; */ -/*description: Set this bit to clear interrupt triggered by a PWM operator 2 TEB event*/ -#define MCPWM_OP2_TEB_INT_CLR (BIT(20)) -#define MCPWM_OP2_TEB_INT_CLR_M (BIT(20)) -#define MCPWM_OP2_TEB_INT_CLR_V 0x1 -#define MCPWM_OP2_TEB_INT_CLR_S 20 -/* MCPWM_OP1_TEB_INT_CLR : WO ;bitpos:[19] ;default: 1'd0 ; */ -/*description: Set this bit to clear interrupt triggered by a PWM operator 1 TEB event*/ -#define MCPWM_OP1_TEB_INT_CLR (BIT(19)) -#define MCPWM_OP1_TEB_INT_CLR_M (BIT(19)) -#define MCPWM_OP1_TEB_INT_CLR_V 0x1 -#define MCPWM_OP1_TEB_INT_CLR_S 19 -/* MCPWM_OP0_TEB_INT_CLR : WO ;bitpos:[18] ;default: 1'd0 ; */ -/*description: Set this bit to clear interrupt triggered by a PWM operator 0 TEB event*/ -#define MCPWM_OP0_TEB_INT_CLR (BIT(18)) -#define MCPWM_OP0_TEB_INT_CLR_M (BIT(18)) -#define MCPWM_OP0_TEB_INT_CLR_V 0x1 -#define MCPWM_OP0_TEB_INT_CLR_S 18 -/* MCPWM_OP2_TEA_INT_CLR : WO ;bitpos:[17] ;default: 1'd0 ; */ -/*description: Set this bit to clear interrupt triggered by a PWM operator 2 TEA event*/ -#define MCPWM_OP2_TEA_INT_CLR (BIT(17)) -#define MCPWM_OP2_TEA_INT_CLR_M (BIT(17)) -#define MCPWM_OP2_TEA_INT_CLR_V 0x1 -#define MCPWM_OP2_TEA_INT_CLR_S 17 -/* MCPWM_OP1_TEA_INT_CLR : WO ;bitpos:[16] ;default: 1'd0 ; */ -/*description: Set this bit to clear interrupt triggered by a PWM operator 1 TEA event*/ -#define MCPWM_OP1_TEA_INT_CLR (BIT(16)) -#define MCPWM_OP1_TEA_INT_CLR_M (BIT(16)) -#define MCPWM_OP1_TEA_INT_CLR_V 0x1 -#define MCPWM_OP1_TEA_INT_CLR_S 16 -/* MCPWM_OP0_TEA_INT_CLR : WO ;bitpos:[15] ;default: 1'd0 ; */ -/*description: Set this bit to clear interrupt triggered by a PWM operator 0 TEA event*/ -#define MCPWM_OP0_TEA_INT_CLR (BIT(15)) -#define MCPWM_OP0_TEA_INT_CLR_M (BIT(15)) -#define MCPWM_OP0_TEA_INT_CLR_V 0x1 -#define MCPWM_OP0_TEA_INT_CLR_S 15 -/* MCPWM_FAULT2_CLR_INT_CLR : WO ;bitpos:[14] ;default: 1'd0 ; */ -/*description: Set this bit to clear interrupt triggered when event_f2 ends*/ -#define MCPWM_FAULT2_CLR_INT_CLR (BIT(14)) -#define MCPWM_FAULT2_CLR_INT_CLR_M (BIT(14)) -#define MCPWM_FAULT2_CLR_INT_CLR_V 0x1 -#define MCPWM_FAULT2_CLR_INT_CLR_S 14 -/* MCPWM_FAULT1_CLR_INT_CLR : WO ;bitpos:[13] ;default: 1'd0 ; */ -/*description: Set this bit to clear interrupt triggered when event_f1 ends*/ -#define MCPWM_FAULT1_CLR_INT_CLR (BIT(13)) -#define MCPWM_FAULT1_CLR_INT_CLR_M (BIT(13)) -#define MCPWM_FAULT1_CLR_INT_CLR_V 0x1 -#define MCPWM_FAULT1_CLR_INT_CLR_S 13 -/* MCPWM_FAULT0_CLR_INT_CLR : WO ;bitpos:[12] ;default: 1'd0 ; */ -/*description: Set this bit to clear interrupt triggered when event_f0 ends*/ -#define MCPWM_FAULT0_CLR_INT_CLR (BIT(12)) -#define MCPWM_FAULT0_CLR_INT_CLR_M (BIT(12)) -#define MCPWM_FAULT0_CLR_INT_CLR_V 0x1 -#define MCPWM_FAULT0_CLR_INT_CLR_S 12 -/* MCPWM_FAULT2_INT_CLR : WO ;bitpos:[11] ;default: 1'd0 ; */ -/*description: Set this bit to clear interrupt triggered when event_f2 starts*/ -#define MCPWM_FAULT2_INT_CLR (BIT(11)) -#define MCPWM_FAULT2_INT_CLR_M (BIT(11)) -#define MCPWM_FAULT2_INT_CLR_V 0x1 -#define MCPWM_FAULT2_INT_CLR_S 11 -/* MCPWM_FAULT1_INT_CLR : WO ;bitpos:[10] ;default: 1'd0 ; */ -/*description: Set this bit to clear interrupt triggered when event_f1 starts*/ -#define MCPWM_FAULT1_INT_CLR (BIT(10)) -#define MCPWM_FAULT1_INT_CLR_M (BIT(10)) -#define MCPWM_FAULT1_INT_CLR_V 0x1 -#define MCPWM_FAULT1_INT_CLR_S 10 -/* MCPWM_FAULT0_INT_CLR : WO ;bitpos:[9] ;default: 1'd0 ; */ -/*description: Set this bit to clear interrupt triggered when event_f0 starts*/ -#define MCPWM_FAULT0_INT_CLR (BIT(9)) -#define MCPWM_FAULT0_INT_CLR_M (BIT(9)) -#define MCPWM_FAULT0_INT_CLR_V 0x1 -#define MCPWM_FAULT0_INT_CLR_S 9 -/* MCPWM_TIMER2_TEP_INT_CLR : WO ;bitpos:[8] ;default: 1'h0 ; */ -/*description: Set this bit to clear interrupt triggered by a PWM timer 2 TEP event*/ -#define MCPWM_TIMER2_TEP_INT_CLR (BIT(8)) -#define MCPWM_TIMER2_TEP_INT_CLR_M (BIT(8)) -#define MCPWM_TIMER2_TEP_INT_CLR_V 0x1 -#define MCPWM_TIMER2_TEP_INT_CLR_S 8 -/* MCPWM_TIMER1_TEP_INT_CLR : WO ;bitpos:[7] ;default: 1'h0 ; */ -/*description: Set this bit to clear interrupt triggered by a PWM timer 1 TEP event*/ -#define MCPWM_TIMER1_TEP_INT_CLR (BIT(7)) -#define MCPWM_TIMER1_TEP_INT_CLR_M (BIT(7)) -#define MCPWM_TIMER1_TEP_INT_CLR_V 0x1 -#define MCPWM_TIMER1_TEP_INT_CLR_S 7 -/* MCPWM_TIMER0_TEP_INT_CLR : WO ;bitpos:[6] ;default: 1'h0 ; */ -/*description: Set this bit to clear interrupt triggered by a PWM timer 0 TEP event*/ -#define MCPWM_TIMER0_TEP_INT_CLR (BIT(6)) -#define MCPWM_TIMER0_TEP_INT_CLR_M (BIT(6)) -#define MCPWM_TIMER0_TEP_INT_CLR_V 0x1 -#define MCPWM_TIMER0_TEP_INT_CLR_S 6 -/* MCPWM_TIMER2_TEZ_INT_CLR : WO ;bitpos:[5] ;default: 1'h0 ; */ -/*description: Set this bit to clear interrupt triggered by a PWM timer 2 TEZ event*/ -#define MCPWM_TIMER2_TEZ_INT_CLR (BIT(5)) -#define MCPWM_TIMER2_TEZ_INT_CLR_M (BIT(5)) -#define MCPWM_TIMER2_TEZ_INT_CLR_V 0x1 -#define MCPWM_TIMER2_TEZ_INT_CLR_S 5 -/* MCPWM_TIMER1_TEZ_INT_CLR : WO ;bitpos:[4] ;default: 1'h0 ; */ -/*description: Set this bit to clear interrupt triggered by a PWM timer 1 TEZ event*/ -#define MCPWM_TIMER1_TEZ_INT_CLR (BIT(4)) -#define MCPWM_TIMER1_TEZ_INT_CLR_M (BIT(4)) -#define MCPWM_TIMER1_TEZ_INT_CLR_V 0x1 -#define MCPWM_TIMER1_TEZ_INT_CLR_S 4 -/* MCPWM_TIMER0_TEZ_INT_CLR : WO ;bitpos:[3] ;default: 1'h0 ; */ -/*description: Set this bit to clear interrupt triggered by a PWM timer 0 TEZ event*/ -#define MCPWM_TIMER0_TEZ_INT_CLR (BIT(3)) -#define MCPWM_TIMER0_TEZ_INT_CLR_M (BIT(3)) -#define MCPWM_TIMER0_TEZ_INT_CLR_V 0x1 -#define MCPWM_TIMER0_TEZ_INT_CLR_S 3 -/* MCPWM_TIMER2_STOP_INT_CLR : WO ;bitpos:[2] ;default: 1'h0 ; */ -/*description: Set this bit to clear interrupt triggered when timer 2 stops*/ -#define MCPWM_TIMER2_STOP_INT_CLR (BIT(2)) -#define MCPWM_TIMER2_STOP_INT_CLR_M (BIT(2)) -#define MCPWM_TIMER2_STOP_INT_CLR_V 0x1 -#define MCPWM_TIMER2_STOP_INT_CLR_S 2 -/* MCPWM_TIMER1_STOP_INT_CLR : WO ;bitpos:[1] ;default: 1'h0 ; */ -/*description: Set this bit to clear interrupt triggered when timer 1 stops*/ -#define MCPWM_TIMER1_STOP_INT_CLR (BIT(1)) -#define MCPWM_TIMER1_STOP_INT_CLR_M (BIT(1)) -#define MCPWM_TIMER1_STOP_INT_CLR_V 0x1 -#define MCPWM_TIMER1_STOP_INT_CLR_S 1 -/* MCPWM_TIMER0_STOP_INT_CLR : WO ;bitpos:[0] ;default: 1'h0 ; */ -/*description: Set this bit to clear interrupt triggered when timer 0 stops*/ -#define MCPWM_TIMER0_STOP_INT_CLR (BIT(0)) -#define MCPWM_TIMER0_STOP_INT_CLR_M (BIT(0)) -#define MCPWM_TIMER0_STOP_INT_CLR_V 0x1 +/** MCPWM_INT_CLR_REG register + * Interrupt clear bits + */ +#define MCPWM_INT_CLR_REG(i) (DR_REG_MCPWM_BASE(i) + 0x11c) +/** MCPWM_TIMER0_STOP_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the interrupt triggered when the timer 0 stops. + */ +#define MCPWM_TIMER0_STOP_INT_CLR (BIT(0)) +#define MCPWM_TIMER0_STOP_INT_CLR_M (MCPWM_TIMER0_STOP_INT_CLR_V << MCPWM_TIMER0_STOP_INT_CLR_S) +#define MCPWM_TIMER0_STOP_INT_CLR_V 0x00000001U #define MCPWM_TIMER0_STOP_INT_CLR_S 0 +/** MCPWM_TIMER1_STOP_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the interrupt triggered when the timer 1 stops. + */ +#define MCPWM_TIMER1_STOP_INT_CLR (BIT(1)) +#define MCPWM_TIMER1_STOP_INT_CLR_M (MCPWM_TIMER1_STOP_INT_CLR_V << MCPWM_TIMER1_STOP_INT_CLR_S) +#define MCPWM_TIMER1_STOP_INT_CLR_V 0x00000001U +#define MCPWM_TIMER1_STOP_INT_CLR_S 1 +/** MCPWM_TIMER2_STOP_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the interrupt triggered when the timer 2 stops. + */ +#define MCPWM_TIMER2_STOP_INT_CLR (BIT(2)) +#define MCPWM_TIMER2_STOP_INT_CLR_M (MCPWM_TIMER2_STOP_INT_CLR_V << MCPWM_TIMER2_STOP_INT_CLR_S) +#define MCPWM_TIMER2_STOP_INT_CLR_V 0x00000001U +#define MCPWM_TIMER2_STOP_INT_CLR_S 2 +/** MCPWM_TIMER0_TEZ_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM timer 0 TEZ event. + */ +#define MCPWM_TIMER0_TEZ_INT_CLR (BIT(3)) +#define MCPWM_TIMER0_TEZ_INT_CLR_M (MCPWM_TIMER0_TEZ_INT_CLR_V << MCPWM_TIMER0_TEZ_INT_CLR_S) +#define MCPWM_TIMER0_TEZ_INT_CLR_V 0x00000001U +#define MCPWM_TIMER0_TEZ_INT_CLR_S 3 +/** MCPWM_TIMER1_TEZ_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM timer 1 TEZ event. + */ +#define MCPWM_TIMER1_TEZ_INT_CLR (BIT(4)) +#define MCPWM_TIMER1_TEZ_INT_CLR_M (MCPWM_TIMER1_TEZ_INT_CLR_V << MCPWM_TIMER1_TEZ_INT_CLR_S) +#define MCPWM_TIMER1_TEZ_INT_CLR_V 0x00000001U +#define MCPWM_TIMER1_TEZ_INT_CLR_S 4 +/** MCPWM_TIMER2_TEZ_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM timer 2 TEZ event. + */ +#define MCPWM_TIMER2_TEZ_INT_CLR (BIT(5)) +#define MCPWM_TIMER2_TEZ_INT_CLR_M (MCPWM_TIMER2_TEZ_INT_CLR_V << MCPWM_TIMER2_TEZ_INT_CLR_S) +#define MCPWM_TIMER2_TEZ_INT_CLR_V 0x00000001U +#define MCPWM_TIMER2_TEZ_INT_CLR_S 5 +/** MCPWM_TIMER0_TEP_INT_CLR : WT; bitpos: [6]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM timer 0 TEP event. + */ +#define MCPWM_TIMER0_TEP_INT_CLR (BIT(6)) +#define MCPWM_TIMER0_TEP_INT_CLR_M (MCPWM_TIMER0_TEP_INT_CLR_V << MCPWM_TIMER0_TEP_INT_CLR_S) +#define MCPWM_TIMER0_TEP_INT_CLR_V 0x00000001U +#define MCPWM_TIMER0_TEP_INT_CLR_S 6 +/** MCPWM_TIMER1_TEP_INT_CLR : WT; bitpos: [7]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM timer 1 TEP event. + */ +#define MCPWM_TIMER1_TEP_INT_CLR (BIT(7)) +#define MCPWM_TIMER1_TEP_INT_CLR_M (MCPWM_TIMER1_TEP_INT_CLR_V << MCPWM_TIMER1_TEP_INT_CLR_S) +#define MCPWM_TIMER1_TEP_INT_CLR_V 0x00000001U +#define MCPWM_TIMER1_TEP_INT_CLR_S 7 +/** MCPWM_TIMER2_TEP_INT_CLR : WT; bitpos: [8]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM timer 2 TEP event. + */ +#define MCPWM_TIMER2_TEP_INT_CLR (BIT(8)) +#define MCPWM_TIMER2_TEP_INT_CLR_M (MCPWM_TIMER2_TEP_INT_CLR_V << MCPWM_TIMER2_TEP_INT_CLR_S) +#define MCPWM_TIMER2_TEP_INT_CLR_V 0x00000001U +#define MCPWM_TIMER2_TEP_INT_CLR_S 8 +/** MCPWM_FAULT0_INT_CLR : WT; bitpos: [9]; default: 0; + * Set this bit to clear the interrupt triggered when fault_event0 starts. + */ +#define MCPWM_FAULT0_INT_CLR (BIT(9)) +#define MCPWM_FAULT0_INT_CLR_M (MCPWM_FAULT0_INT_CLR_V << MCPWM_FAULT0_INT_CLR_S) +#define MCPWM_FAULT0_INT_CLR_V 0x00000001U +#define MCPWM_FAULT0_INT_CLR_S 9 +/** MCPWM_FAULT1_INT_CLR : WT; bitpos: [10]; default: 0; + * Set this bit to clear the interrupt triggered when fault_event1 starts. + */ +#define MCPWM_FAULT1_INT_CLR (BIT(10)) +#define MCPWM_FAULT1_INT_CLR_M (MCPWM_FAULT1_INT_CLR_V << MCPWM_FAULT1_INT_CLR_S) +#define MCPWM_FAULT1_INT_CLR_V 0x00000001U +#define MCPWM_FAULT1_INT_CLR_S 10 +/** MCPWM_FAULT2_INT_CLR : WT; bitpos: [11]; default: 0; + * Set this bit to clear the interrupt triggered when fault_event2 starts. + */ +#define MCPWM_FAULT2_INT_CLR (BIT(11)) +#define MCPWM_FAULT2_INT_CLR_M (MCPWM_FAULT2_INT_CLR_V << MCPWM_FAULT2_INT_CLR_S) +#define MCPWM_FAULT2_INT_CLR_V 0x00000001U +#define MCPWM_FAULT2_INT_CLR_S 11 +/** MCPWM_FAULT0_CLR_INT_CLR : WT; bitpos: [12]; default: 0; + * Set this bit to clear the interrupt triggered when fault_event0 ends. + */ +#define MCPWM_FAULT0_CLR_INT_CLR (BIT(12)) +#define MCPWM_FAULT0_CLR_INT_CLR_M (MCPWM_FAULT0_CLR_INT_CLR_V << MCPWM_FAULT0_CLR_INT_CLR_S) +#define MCPWM_FAULT0_CLR_INT_CLR_V 0x00000001U +#define MCPWM_FAULT0_CLR_INT_CLR_S 12 +/** MCPWM_FAULT1_CLR_INT_CLR : WT; bitpos: [13]; default: 0; + * Set this bit to clear the interrupt triggered when fault_event1 ends. + */ +#define MCPWM_FAULT1_CLR_INT_CLR (BIT(13)) +#define MCPWM_FAULT1_CLR_INT_CLR_M (MCPWM_FAULT1_CLR_INT_CLR_V << MCPWM_FAULT1_CLR_INT_CLR_S) +#define MCPWM_FAULT1_CLR_INT_CLR_V 0x00000001U +#define MCPWM_FAULT1_CLR_INT_CLR_S 13 +/** MCPWM_FAULT2_CLR_INT_CLR : WT; bitpos: [14]; default: 0; + * Set this bit to clear the interrupt triggered when fault_event2 ends. + */ +#define MCPWM_FAULT2_CLR_INT_CLR (BIT(14)) +#define MCPWM_FAULT2_CLR_INT_CLR_M (MCPWM_FAULT2_CLR_INT_CLR_V << MCPWM_FAULT2_CLR_INT_CLR_S) +#define MCPWM_FAULT2_CLR_INT_CLR_V 0x00000001U +#define MCPWM_FAULT2_CLR_INT_CLR_S 14 +/** MCPWM_OP0_TEA_INT_CLR : WT; bitpos: [15]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM operator 0 TEA event + */ +#define MCPWM_OP0_TEA_INT_CLR (BIT(15)) +#define MCPWM_OP0_TEA_INT_CLR_M (MCPWM_OP0_TEA_INT_CLR_V << MCPWM_OP0_TEA_INT_CLR_S) +#define MCPWM_OP0_TEA_INT_CLR_V 0x00000001U +#define MCPWM_OP0_TEA_INT_CLR_S 15 +/** MCPWM_OP1_TEA_INT_CLR : WT; bitpos: [16]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM operator 1 TEA event + */ +#define MCPWM_OP1_TEA_INT_CLR (BIT(16)) +#define MCPWM_OP1_TEA_INT_CLR_M (MCPWM_OP1_TEA_INT_CLR_V << MCPWM_OP1_TEA_INT_CLR_S) +#define MCPWM_OP1_TEA_INT_CLR_V 0x00000001U +#define MCPWM_OP1_TEA_INT_CLR_S 16 +/** MCPWM_OP2_TEA_INT_CLR : WT; bitpos: [17]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM operator 2 TEA event + */ +#define MCPWM_OP2_TEA_INT_CLR (BIT(17)) +#define MCPWM_OP2_TEA_INT_CLR_M (MCPWM_OP2_TEA_INT_CLR_V << MCPWM_OP2_TEA_INT_CLR_S) +#define MCPWM_OP2_TEA_INT_CLR_V 0x00000001U +#define MCPWM_OP2_TEA_INT_CLR_S 17 +/** MCPWM_OP0_TEB_INT_CLR : WT; bitpos: [18]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM operator 0 TEB event + */ +#define MCPWM_OP0_TEB_INT_CLR (BIT(18)) +#define MCPWM_OP0_TEB_INT_CLR_M (MCPWM_OP0_TEB_INT_CLR_V << MCPWM_OP0_TEB_INT_CLR_S) +#define MCPWM_OP0_TEB_INT_CLR_V 0x00000001U +#define MCPWM_OP0_TEB_INT_CLR_S 18 +/** MCPWM_OP1_TEB_INT_CLR : WT; bitpos: [19]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM operator 1 TEB event + */ +#define MCPWM_OP1_TEB_INT_CLR (BIT(19)) +#define MCPWM_OP1_TEB_INT_CLR_M (MCPWM_OP1_TEB_INT_CLR_V << MCPWM_OP1_TEB_INT_CLR_S) +#define MCPWM_OP1_TEB_INT_CLR_V 0x00000001U +#define MCPWM_OP1_TEB_INT_CLR_S 19 +/** MCPWM_OP2_TEB_INT_CLR : WT; bitpos: [20]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM operator 2 TEB event + */ +#define MCPWM_OP2_TEB_INT_CLR (BIT(20)) +#define MCPWM_OP2_TEB_INT_CLR_M (MCPWM_OP2_TEB_INT_CLR_V << MCPWM_OP2_TEB_INT_CLR_S) +#define MCPWM_OP2_TEB_INT_CLR_V 0x00000001U +#define MCPWM_OP2_TEB_INT_CLR_S 20 +/** MCPWM_FH0_CBC_INT_CLR : WT; bitpos: [21]; default: 0; + * Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on + * PWM0. + */ +#define MCPWM_FH0_CBC_INT_CLR (BIT(21)) +#define MCPWM_FH0_CBC_INT_CLR_M (MCPWM_FH0_CBC_INT_CLR_V << MCPWM_FH0_CBC_INT_CLR_S) +#define MCPWM_FH0_CBC_INT_CLR_V 0x00000001U +#define MCPWM_FH0_CBC_INT_CLR_S 21 +/** MCPWM_FH1_CBC_INT_CLR : WT; bitpos: [22]; default: 0; + * Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on + * PWM1. + */ +#define MCPWM_FH1_CBC_INT_CLR (BIT(22)) +#define MCPWM_FH1_CBC_INT_CLR_M (MCPWM_FH1_CBC_INT_CLR_V << MCPWM_FH1_CBC_INT_CLR_S) +#define MCPWM_FH1_CBC_INT_CLR_V 0x00000001U +#define MCPWM_FH1_CBC_INT_CLR_S 22 +/** MCPWM_FH2_CBC_INT_CLR : WT; bitpos: [23]; default: 0; + * Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on + * PWM2. + */ +#define MCPWM_FH2_CBC_INT_CLR (BIT(23)) +#define MCPWM_FH2_CBC_INT_CLR_M (MCPWM_FH2_CBC_INT_CLR_V << MCPWM_FH2_CBC_INT_CLR_S) +#define MCPWM_FH2_CBC_INT_CLR_V 0x00000001U +#define MCPWM_FH2_CBC_INT_CLR_S 23 +/** MCPWM_FH0_OST_INT_CLR : WT; bitpos: [24]; default: 0; + * Set this bit to clear the interrupt triggered by a one-shot mode action on PWM0. + */ +#define MCPWM_FH0_OST_INT_CLR (BIT(24)) +#define MCPWM_FH0_OST_INT_CLR_M (MCPWM_FH0_OST_INT_CLR_V << MCPWM_FH0_OST_INT_CLR_S) +#define MCPWM_FH0_OST_INT_CLR_V 0x00000001U +#define MCPWM_FH0_OST_INT_CLR_S 24 +/** MCPWM_FH1_OST_INT_CLR : WT; bitpos: [25]; default: 0; + * Set this bit to clear the interrupt triggered by a one-shot mode action on PWM1. + */ +#define MCPWM_FH1_OST_INT_CLR (BIT(25)) +#define MCPWM_FH1_OST_INT_CLR_M (MCPWM_FH1_OST_INT_CLR_V << MCPWM_FH1_OST_INT_CLR_S) +#define MCPWM_FH1_OST_INT_CLR_V 0x00000001U +#define MCPWM_FH1_OST_INT_CLR_S 25 +/** MCPWM_FH2_OST_INT_CLR : WT; bitpos: [26]; default: 0; + * Set this bit to clear the interrupt triggered by a one-shot mode action on PWM2. + */ +#define MCPWM_FH2_OST_INT_CLR (BIT(26)) +#define MCPWM_FH2_OST_INT_CLR_M (MCPWM_FH2_OST_INT_CLR_V << MCPWM_FH2_OST_INT_CLR_S) +#define MCPWM_FH2_OST_INT_CLR_V 0x00000001U +#define MCPWM_FH2_OST_INT_CLR_S 26 +/** MCPWM_CAP0_INT_CLR : WT; bitpos: [27]; default: 0; + * Set this bit to clear the interrupt triggered by capture on channel 0. + */ +#define MCPWM_CAP0_INT_CLR (BIT(27)) +#define MCPWM_CAP0_INT_CLR_M (MCPWM_CAP0_INT_CLR_V << MCPWM_CAP0_INT_CLR_S) +#define MCPWM_CAP0_INT_CLR_V 0x00000001U +#define MCPWM_CAP0_INT_CLR_S 27 +/** MCPWM_CAP1_INT_CLR : WT; bitpos: [28]; default: 0; + * Set this bit to clear the interrupt triggered by capture on channel 1. + */ +#define MCPWM_CAP1_INT_CLR (BIT(28)) +#define MCPWM_CAP1_INT_CLR_M (MCPWM_CAP1_INT_CLR_V << MCPWM_CAP1_INT_CLR_S) +#define MCPWM_CAP1_INT_CLR_V 0x00000001U +#define MCPWM_CAP1_INT_CLR_S 28 +/** MCPWM_CAP2_INT_CLR : WT; bitpos: [29]; default: 0; + * Set this bit to clear the interrupt triggered by capture on channel 2. + */ +#define MCPWM_CAP2_INT_CLR (BIT(29)) +#define MCPWM_CAP2_INT_CLR_M (MCPWM_CAP2_INT_CLR_V << MCPWM_CAP2_INT_CLR_S) +#define MCPWM_CAP2_INT_CLR_V 0x00000001U +#define MCPWM_CAP2_INT_CLR_S 29 -#define MCPWM_CLK_REG(i) (REG_MCPWM_BASE(i) + 0x0120) -/* MCPWM_CLK_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */ -/*description: Force clock on for this reg file*/ -#define MCPWM_CLK_EN (BIT(0)) -#define MCPWM_CLK_EN_M (BIT(0)) -#define MCPWM_CLK_EN_V 0x1 +/** MCPWM_CLK_REG register + * MCPWM APB configuration register + */ +#define MCPWM_CLK_REG(i) (DR_REG_MCPWM_BASE(i) + 0x120) +/** MCPWM_CLK_EN : R/W; bitpos: [0]; default: 0; + * Force clock on for this register file + */ +#define MCPWM_CLK_EN (BIT(0)) +#define MCPWM_CLK_EN_M (MCPWM_CLK_EN_V << MCPWM_CLK_EN_S) +#define MCPWM_CLK_EN_V 0x00000001U #define MCPWM_CLK_EN_S 0 -#define MCPWM_VERSION_REG(i) (REG_MCPWM_BASE(i) + 0x0124) -/* MCPWM_DATE : R/W ;bitpos:[27:0] ;default: 28'h1509110 ; */ -/*description: Version of this reg file*/ -#define MCPWM_DATE 0x0FFFFFFF -#define MCPWM_DATE_M ((MCPWM_DATE_V)<<(MCPWM_DATE_S)) -#define MCPWM_DATE_V 0xFFFFFFF +/** MCPWM_VERSION_REG register + * Version register. + */ +#define MCPWM_VERSION_REG(i) (DR_REG_MCPWM_BASE(i) + 0x124) +/** MCPWM_DATE : R/W; bitpos: [27:0]; default: 34632240; + * Version of this register file + */ +#define MCPWM_DATE 0x0FFFFFFFU +#define MCPWM_DATE_M (MCPWM_DATE_V << MCPWM_DATE_S) +#define MCPWM_DATE_V 0x0FFFFFFFU #define MCPWM_DATE_S 0 - - - -#endif /*_SOC_MCPWM_REG_H_ */ +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32/include/soc/mcpwm_struct.h b/components/soc/esp32/include/soc/mcpwm_struct.h index 87f3f227272..afd2a5633c4 100644 --- a/components/soc/esp32/include/soc/mcpwm_struct.h +++ b/components/soc/esp32/include/soc/mcpwm_struct.h @@ -1,461 +1,1468 @@ -// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/** + * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once #include - #ifdef __cplusplus extern "C" { #endif -typedef volatile struct mcpwm_dev_s { - union { - struct { - uint32_t prescale : 8; /*Period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1)*/ - uint32_t reserved8 : 24; - }; - uint32_t val; - } clk_cfg; - struct { - union { - struct { - uint32_t prescale : 8; /*period of PT0_clk = Period of PWM_clk * (PWM_TIMER0_PRESCALE + 1)*/ - uint32_t period : 16; /*period shadow reg of PWM timer0*/ - uint32_t upmethod : 2; /*Update method for active reg of PWM timer0 period 0: immediate 1: TEZ 2: sync 3: TEZ | sync. TEZ here and below means timer equal zero event*/ - uint32_t reserved26 : 6; - }; - uint32_t val; - } period; - union { - struct { - uint32_t start : 3; /*PWM timer0 start and stop control. 0: stop @ TEZ 1: stop @ TEP 2: free run 3: start and stop @ next TEZ 4: start and stop @ next TEP. TEP here and below means timer equal period event*/ - uint32_t mode : 2; /*PWM timer0 working mode 0: freeze 1: increase mod 2: decrease mod 3: up-down mod*/ - uint32_t reserved5 : 27; - }; - uint32_t val; - } mode; - union { - struct { - uint32_t in_en : 1; /*when set timer reload with phase on sync input event is enabled*/ - uint32_t sync_sw : 1; /*write the negate value will trigger a software sync*/ - uint32_t out_sel : 2; /*PWM timer0 synco selection 0: synci 1: TEZ 2: TEP else 0*/ - uint32_t timer_phase : 16; /*phase for timer reload on sync event*/ - uint32_t phase_direct : 1; /*counter direction to apply on sync event*/ - uint32_t reserved21 : 11; - }; - uint32_t val; - } sync; - union { - struct { - uint32_t value : 16; /*current PWM timer0 counter value*/ - uint32_t direction : 1; /*current PWM timer0 counter direction 0: increment 1: decrement*/ - uint32_t reserved17 : 15; - }; - uint32_t val; - } status; - } timer[3]; - - union { - struct { - uint32_t t0_in_sel : 3; /*select sync input for PWM timer0 1: PWM timer0 synco 2: PWM timer1 synco 3: PWM timer2 synco 4: SYNC0 from GPIO matrix 5: SYNC1 from GPIO matrix 6: SYNC2 from GPIO matrix else: none*/ - uint32_t t1_in_sel : 3; /*select sync input for PWM timer1 1: PWM timer0 synco 2: PWM timer1 synco 3: PWM timer2 synco 4: SYNC0 from GPIO matrix 5: SYNC1 from GPIO matrix 6: SYNC2 from GPIO matrix else: none*/ - uint32_t t2_in_sel : 3; /*select sync input for PWM timer2 1: PWM timer0 synco 2: PWM timer1 synco 3: PWM timer2 synco 4: SYNC0 from GPIO matrix 5: SYNC1 from GPIO matrix 6: SYNC2 from GPIO matrix else: none*/ - uint32_t ext_in0_inv : 1; /*invert SYNC0 from GPIO matrix*/ - uint32_t ext_in1_inv : 1; /*invert SYNC1 from GPIO matrix*/ - uint32_t ext_in2_inv : 1; /*invert SYNC2 from GPIO matrix*/ - uint32_t reserved12 : 20; - }; - uint32_t val; - } timer_synci_cfg; - union { - struct { - uint32_t operator0_sel : 2; /*Select which PWM timer's is the timing reference for PWM operator0 0: timer0 1: timer1 2: timer2*/ - uint32_t operator1_sel : 2; /*Select which PWM timer's is the timing reference for PWM operator1 0: timer0 1: timer1 2: timer2*/ - uint32_t operator2_sel : 2; /*Select which PWM timer's is the timing reference for PWM operator2 0: timer0 1: timer1 2: timer2*/ - uint32_t reserved6 : 26; - }; - uint32_t val; - } timer_sel; - - struct { - union { - struct { - uint32_t a_upmethod : 4; /*Update method for PWM compare0 A's active reg. 0: immediate bit0: TEZ bit1: TEP bit2: sync bit3: freeze*/ - uint32_t b_upmethod : 4; /*Update method for PWM compare0 B's active reg. 0: immediate bit0: TEZ bit1: TEP bit2: sync bit3: freeze*/ - uint32_t a_shdw_full : 1; /*Set and reset by hardware. If set PWM compare0 A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared A's active reg has been updated with shadow reg latest value*/ - uint32_t b_shdw_full : 1; /*Set and reset by hardware. If set PWM compare0 B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared B's active reg has been updated with shadow reg latest value*/ - uint32_t reserved10 : 22; - }; - uint32_t val; - } cmpr_cfg; - union { - struct { - uint32_t cmpr_val : 16; /*PWM compare0 A's shadow reg*/ - uint32_t reserved16 : 16; - }; - uint32_t val; - } cmpr_value[2]; - union { - struct { - uint32_t upmethod : 4; /*Update method for PWM generate0's active reg of configuration. 0: immediate bit0: TEZ bit1: TEP bit2: sync. bit3: freeze*/ - uint32_t t0_sel : 3; /*Source selection for PWM generate0 event_t0 take effect immediately 0: fault_event0 1: fault_event1 2: fault_event2 3: sync_taken 4: none*/ - uint32_t t1_sel : 3; /*Source selection for PWM generate0 event_t1 take effect immediately 0: fault_event0 1: fault_event1 2: fault_event2 3: sync_taken 4: none*/ - uint32_t reserved10 : 22; - }; - uint32_t val; - } gen_cfg0; - union { - struct { - uint32_t cntu_force_upmethod : 6; /*Update method for continuous software force of PWM generate0. 0: immediate bit0: TEZ bit1: TEP bit2: TEA bit3: TEB bit4: sync bit5: freeze. (TEA/B here and below means timer equals A/B event)*/ - uint32_t a_cntuforce_mode : 2; /*Continuous software force mode for PWM0A. 0: disabled 1: low 2: high 3: disabled*/ - uint32_t b_cntuforce_mode : 2; /*Continuous software force mode for PWM0B. 0: disabled 1: low 2: high 3: disabled*/ - uint32_t a_nciforce : 1; /*non-continuous immediate software force trigger for PWM0A a toggle will trigger a force event*/ - uint32_t a_nciforce_mode : 2; /*non-continuous immediate software force mode for PWM0A 0: disabled 1: low 2: high 3: disabled*/ - uint32_t b_nciforce : 1; /*non-continuous immediate software force trigger for PWM0B a toggle will trigger a force event*/ - uint32_t b_nciforce_mode : 2; /*non-continuous immediate software force mode for PWM0B 0: disabled 1: low 2: high 3: disabled*/ - uint32_t reserved16 : 16; - }; - uint32_t val; - } gen_force; - union { - struct { - uint32_t utez : 2; /*Action on PWM0A triggered by event TEZ when timer increasing*/ - uint32_t utep : 2; /*Action on PWM0A triggered by event TEP when timer increasing*/ - uint32_t utea : 2; /*Action on PWM0A triggered by event TEA when timer increasing*/ - uint32_t uteb : 2; /*Action on PWM0A triggered by event TEB when timer increasing*/ - uint32_t ut0 : 2; /*Action on PWM0A triggered by event_t0 when timer increasing*/ - uint32_t ut1 : 2; /*Action on PWM0A triggered by event_t1 when timer increasing*/ - uint32_t dtez : 2; /*Action on PWM0A triggered by event TEZ when timer decreasing*/ - uint32_t dtep : 2; /*Action on PWM0A triggered by event TEP when timer decreasing*/ - uint32_t dtea : 2; /*Action on PWM0A triggered by event TEA when timer decreasing*/ - uint32_t dteb : 2; /*Action on PWM0A triggered by event TEB when timer decreasing*/ - uint32_t dt0 : 2; /*Action on PWM0A triggered by event_t0 when timer decreasing*/ - uint32_t dt1 : 2; /*Action on PWM0A triggered by event_t1 when timer decreasing. 0: no change 1: low 2: high 3: toggle*/ - uint32_t reserved24 : 8; - }; - uint32_t val; - } generator[2]; - union { - struct { - uint32_t fed_upmethod : 4; /*Update method for FED (falling edge delay) active reg. 0: immediate bit0: tez bit1: tep bit2: sync bit3: freeze*/ - uint32_t red_upmethod : 4; /*Update method for RED (rising edge delay) active reg. 0: immediate bit0: tez bit1: tep bit2: sync bit3: freeze*/ - uint32_t deb_mode : 1; /*S8 in documentation dual-edge B mode 0: fed/red take effect on different path separately 1: fed/red take effect on B path A out is in bypass or dulpB mode*/ - uint32_t a_outswap : 1; /*S6 in documentation*/ - uint32_t b_outswap : 1; /*S7 in documentation*/ - uint32_t red_insel : 1; /*S4 in documentation*/ - uint32_t fed_insel : 1; /*S5 in documentation*/ - uint32_t red_outinvert : 1; /*S2 in documentation*/ - uint32_t fed_outinvert : 1; /*S3 in documentation*/ - uint32_t a_outbypass : 1; /*S1 in documentation*/ - uint32_t b_outbypass : 1; /*S0 in documentation*/ - uint32_t clk_sel : 1; /*Dead band0 clock selection. 0: PWM_clk 1: PT_clk*/ - uint32_t reserved18 : 14; - }; - uint32_t val; - } db_cfg; - union { - struct { - uint32_t fed : 16; /*Shadow reg for FED*/ - uint32_t reserved16 : 16; - }; - uint32_t val; - } db_fed_cfg; - union { - struct { - uint32_t red : 16; /*Shadow reg for RED*/ - uint32_t reserved16 : 16; - }; - uint32_t val; - } db_red_cfg; - union { - struct { - uint32_t en : 1; /*When set carrier0 function is enabled. When reset carrier0 is bypassed*/ - uint32_t prescale : 4; /*carrier0 clk (CP_clk) prescale value. Period of CP_clk = period of PWM_clk * (PWM_CARRIER0_PRESCALE + 1)*/ - uint32_t duty : 3; /*carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8*/ - uint32_t oshtwth : 4; /*width of the fist pulse in number of periods of the carrier*/ - uint32_t out_invert : 1; /*when set invert the output of PWM0A and PWM0B for this submodule*/ - uint32_t in_invert : 1; /*when set invert the input of PWM0A and PWM0B for this submodule*/ - uint32_t reserved14 : 18; - }; - uint32_t val; - } carrier_cfg; - union { - struct { - uint32_t sw_cbc : 1; /*Cycle-by-cycle tripping software force event will trigger cycle-by-cycle trip event. 0: disable 1: enable*/ - uint32_t f2_cbc : 1; /*event_f2 will trigger cycle-by-cycle trip event. 0: disable 1: enable*/ - uint32_t f1_cbc : 1; /*event_f1 will trigger cycle-by-cycle trip event. 0: disable 1: enable*/ - uint32_t f0_cbc : 1; /*event_f0 will trigger cycle-by-cycle trip event. 0: disable 1: enable*/ - uint32_t sw_ost : 1; /*one-shot tripping software force event will trigger one-shot trip event. 0: disable 1: enable*/ - uint32_t f2_ost : 1; /*event_f2 will trigger one-shot trip event. 0: disable 1: enable*/ - uint32_t f1_ost : 1; /*event_f1 will trigger one-shot trip event. 0: disable 1: enable*/ - uint32_t f0_ost : 1; /*event_f0 will trigger one-shot trip event. 0: disable 1: enable*/ - uint32_t a_cbc_d : 2; /*Action on PWM0A when cycle-by-cycle trip event occurs and timer is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ - uint32_t a_cbc_u : 2; /*Action on PWM0A when cycle-by-cycle trip event occurs and timer is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ - uint32_t a_ost_d : 2; /*Action on PWM0A when one-shot trip event occurs and timer is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ - uint32_t a_ost_u : 2; /*Action on PWM0A when one-shot trip event occurs and timer is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ - uint32_t b_cbc_d : 2; /*Action on PWM0B when cycle-by-cycle trip event occurs and timer is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ - uint32_t b_cbc_u : 2; /*Action on PWM0B when cycle-by-cycle trip event occurs and timer is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ - uint32_t b_ost_d : 2; /*Action on PWM0B when one-shot trip event occurs and timer is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ - uint32_t b_ost_u : 2; /*Action on PWM0B when one-shot trip event occurs and timer is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ - uint32_t reserved24 : 8; - }; - uint32_t val; - } tz_cfg0; - union { - struct { - uint32_t clr_ost : 1; /*a posedge will clear on going one-shot tripping*/ - uint32_t cbcpulse : 2; /*cycle-by-cycle tripping refresh moment selection. Bit0: TEZ bit1:TEP*/ - uint32_t force_cbc : 1; /*a toggle trigger a cycle-by-cycle tripping software force event*/ - uint32_t force_ost : 1; /*a toggle (software negate its value) trigger a one-shot tripping software force event*/ - uint32_t reserved5 : 27; - }; - uint32_t val; - } tz_cfg1; - union { - struct { - uint32_t cbc_on : 1; /*Set and reset by hardware. If set an cycle-by-cycle trip event is on going*/ - uint32_t ost_on : 1; /*Set and reset by hardware. If set an one-shot trip event is on going*/ - uint32_t reserved2 : 30; - }; - uint32_t val; - } tz_status; - } channel[3]; - - union { - struct { - uint32_t f0_en : 1; /*When set event_f0 generation is enabled*/ - uint32_t f1_en : 1; /*When set event_f1 generation is enabled*/ - uint32_t f2_en : 1; /*When set event_f2 generation is enabled*/ - uint32_t f0_pole : 1; /*Set event_f0 trigger polarity on FAULT0 source from GPIO matrix. 0: level low 1: level high*/ - uint32_t f1_pole : 1; /*Set event_f1 trigger polarity on FAULT1 source from GPIO matrix. 0: level low 1: level high*/ - uint32_t f2_pole : 1; /*Set event_f2 trigger polarity on FAULT2 source from GPIO matrix. 0: level low 1: level high*/ - uint32_t event_f0 : 1; /*Set and reset by hardware. If set event_f0 is on going*/ - uint32_t event_f1 : 1; /*Set and reset by hardware. If set event_f1 is on going*/ - uint32_t event_f2 : 1; /*Set and reset by hardware. If set event_f2 is on going*/ - uint32_t reserved9 : 23; - }; - uint32_t val; - } fault_detect; - union { - struct { - uint32_t timer_en : 1; /*When set capture timer incrementing under APB_clk is enabled.*/ - uint32_t synci_en : 1; /*When set capture timer sync is enabled.*/ - uint32_t synci_sel : 3; /*capture module sync input selection. 0: none 1: timer0 synco 2: timer1 synco 3: timer2 synco 4: SYNC0 from GPIO matrix 5: SYNC1 from GPIO matrix 6: SYNC2 from GPIO matrix*/ - uint32_t sync_sw : 1; /*Write 1 will force a capture timer sync capture timer is loaded with value in phase register.*/ - uint32_t reserved6 : 26; - }; - uint32_t val; - } cap_timer_cfg; - uint32_t cap_timer_phase; /*Phase value for capture timer sync operation.*/ - union { - struct { - uint32_t en : 1; /*When set capture on channel 0 is enabled*/ - uint32_t mode : 2; /*Edge of capture on channel 0 after prescale. bit0: negedge cap en bit1: posedge cap en*/ - uint32_t prescale : 8; /*Value of prescale on possitive edge of CAP0. Prescale value = PWM_CAP0_PRESCALE + 1*/ - uint32_t in_invert : 1; /*when set CAP0 form GPIO matrix is inverted before prescale*/ - uint32_t sw : 1; /*Write 1 will trigger a software forced capture on channel 0*/ - uint32_t reserved13 : 19; - }; - uint32_t val; - } cap_cfg_ch[3]; - uint32_t cap_val_ch[3]; /*Value of last capture on channel 0*/ - union { - struct { - uint32_t cap0_edge : 1; /*Edge of last capture trigger on channel 0 0: posedge 1: negedge*/ - uint32_t cap1_edge : 1; /*Edge of last capture trigger on channel 1 0: posedge 1: negedge*/ - uint32_t cap2_edge : 1; /*Edge of last capture trigger on channel 2 0: posedge 1: negedge*/ - uint32_t reserved3 : 29; - }; - uint32_t val; - } cap_status; - union { - struct { - uint32_t global_up_en : 1; /*The global enable of update of all active registers in MCPWM module*/ - uint32_t global_force_up : 1; /*a toggle (software invert its value) will trigger a forced update of all active registers in MCPWM module*/ - uint32_t op0_up_en : 1; /*When set and PWM_GLOBAL_UP_EN is set update of active registers in PWM operator 0 are enabled*/ - uint32_t op0_force_up : 1; /*a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 0*/ - uint32_t op1_up_en : 1; /*When set and PWM_GLOBAL_UP_EN is set update of active registers in PWM operator 1 are enabled*/ - uint32_t op1_force_up : 1; /*a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 1*/ - uint32_t op2_up_en : 1; /*When set and PWM_GLOBAL_UP_EN is set update of active registers in PWM operator 2 are enabled*/ - uint32_t op2_force_up : 1; /*a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 2*/ - uint32_t reserved8 : 24; - }; - uint32_t val; - } update_cfg; - union { - struct { - uint32_t timer0_stop_int_ena : 1; /*Interrupt when timer 0 stops*/ - uint32_t timer1_stop_int_ena : 1; /*Interrupt when timer 1 stops*/ - uint32_t timer2_stop_int_ena : 1; /*Interrupt when timer 2 stops*/ - uint32_t timer0_tez_int_ena : 1; /*A PWM timer 0 TEZ event will trigger this interrupt*/ - uint32_t timer1_tez_int_ena : 1; /*A PWM timer 1 TEZ event will trigger this interrupt*/ - uint32_t timer2_tez_int_ena : 1; /*A PWM timer 2 TEZ event will trigger this interrupt*/ - uint32_t timer0_tep_int_ena : 1; /*A PWM timer 0 TEP event will trigger this interrupt*/ - uint32_t timer1_tep_int_ena : 1; /*A PWM timer 1 TEP event will trigger this interrupt*/ - uint32_t timer2_tep_int_ena : 1; /*A PWM timer 2 TEP event will trigger this interrupt*/ - uint32_t fault0_int_ena : 1; /*Interrupt when event_f0 starts*/ - uint32_t fault1_int_ena : 1; /*Interrupt when event_f1 starts*/ - uint32_t fault2_int_ena : 1; /*Interrupt when event_f2 starts*/ - uint32_t fault0_clr_int_ena : 1; /*Interrupt when event_f0 ends*/ - uint32_t fault1_clr_int_ena : 1; /*Interrupt when event_f1 ends*/ - uint32_t fault2_clr_int_ena : 1; /*Interrupt when event_f2 ends*/ - uint32_t cmpr0_tea_int_ena : 1; /*A PWM operator 0 TEA event will trigger this interrupt*/ - uint32_t cmpr1_tea_int_ena : 1; /*A PWM operator 1 TEA event will trigger this interrupt*/ - uint32_t cmpr2_tea_int_ena : 1; /*A PWM operator 2 TEA event will trigger this interrupt*/ - uint32_t cmpr0_teb_int_ena : 1; /*A PWM operator 0 TEB event will trigger this interrupt*/ - uint32_t cmpr1_teb_int_ena : 1; /*A PWM operator 1 TEB event will trigger this interrupt*/ - uint32_t cmpr2_teb_int_ena : 1; /*A PWM operator 2 TEB event will trigger this interrupt*/ - uint32_t tz0_cbc_int_ena : 1; /*An cycle-by-cycle trip event on PWM0 will trigger this interrupt*/ - uint32_t tz1_cbc_int_ena : 1; /*An cycle-by-cycle trip event on PWM1 will trigger this interrupt*/ - uint32_t tz2_cbc_int_ena : 1; /*An cycle-by-cycle trip event on PWM2 will trigger this interrupt*/ - uint32_t tz0_ost_int_ena : 1; /*An one-shot trip event on PWM0 will trigger this interrupt*/ - uint32_t tz1_ost_int_ena : 1; /*An one-shot trip event on PWM1 will trigger this interrupt*/ - uint32_t tz2_ost_int_ena : 1; /*An one-shot trip event on PWM2 will trigger this interrupt*/ - uint32_t cap0_int_ena : 1; /*A capture on channel 0 will trigger this interrupt*/ - uint32_t cap1_int_ena : 1; /*A capture on channel 1 will trigger this interrupt*/ - uint32_t cap2_int_ena : 1; /*A capture on channel 2 will trigger this interrupt*/ - uint32_t reserved30 : 2; - }; - uint32_t val; - } int_ena; - union { - struct { - uint32_t timer0_stop_int_raw : 1; /*Interrupt when timer 0 stops*/ - uint32_t timer1_stop_int_raw : 1; /*Interrupt when timer 1 stops*/ - uint32_t timer2_stop_int_raw : 1; /*Interrupt when timer 2 stops*/ - uint32_t timer0_tez_int_raw : 1; /*A PWM timer 0 TEZ event will trigger this interrupt*/ - uint32_t timer1_tez_int_raw : 1; /*A PWM timer 1 TEZ event will trigger this interrupt*/ - uint32_t timer2_tez_int_raw : 1; /*A PWM timer 2 TEZ event will trigger this interrupt*/ - uint32_t timer0_tep_int_raw : 1; /*A PWM timer 0 TEP event will trigger this interrupt*/ - uint32_t timer1_tep_int_raw : 1; /*A PWM timer 1 TEP event will trigger this interrupt*/ - uint32_t timer2_tep_int_raw : 1; /*A PWM timer 2 TEP event will trigger this interrupt*/ - uint32_t fault0_int_raw : 1; /*Interrupt when event_f0 starts*/ - uint32_t fault1_int_raw : 1; /*Interrupt when event_f1 starts*/ - uint32_t fault2_int_raw : 1; /*Interrupt when event_f2 starts*/ - uint32_t fault0_clr_int_raw : 1; /*Interrupt when event_f0 ends*/ - uint32_t fault1_clr_int_raw : 1; /*Interrupt when event_f1 ends*/ - uint32_t fault2_clr_int_raw : 1; /*Interrupt when event_f2 ends*/ - uint32_t cmpr0_tea_int_raw : 1; /*A PWM operator 0 TEA event will trigger this interrupt*/ - uint32_t cmpr1_tea_int_raw : 1; /*A PWM operator 1 TEA event will trigger this interrupt*/ - uint32_t cmpr2_tea_int_raw : 1; /*A PWM operator 2 TEA event will trigger this interrupt*/ - uint32_t cmpr0_teb_int_raw : 1; /*A PWM operator 0 TEB event will trigger this interrupt*/ - uint32_t cmpr1_teb_int_raw : 1; /*A PWM operator 1 TEB event will trigger this interrupt*/ - uint32_t cmpr2_teb_int_raw : 1; /*A PWM operator 2 TEB event will trigger this interrupt*/ - uint32_t tz0_cbc_int_raw : 1; /*An cycle-by-cycle trip event on PWM0 will trigger this interrupt*/ - uint32_t tz1_cbc_int_raw : 1; /*An cycle-by-cycle trip event on PWM1 will trigger this interrupt*/ - uint32_t tz2_cbc_int_raw : 1; /*An cycle-by-cycle trip event on PWM2 will trigger this interrupt*/ - uint32_t tz0_ost_int_raw : 1; /*An one-shot trip event on PWM0 will trigger this interrupt*/ - uint32_t tz1_ost_int_raw : 1; /*An one-shot trip event on PWM1 will trigger this interrupt*/ - uint32_t tz2_ost_int_raw : 1; /*An one-shot trip event on PWM2 will trigger this interrupt*/ - uint32_t cap0_int_raw : 1; /*A capture on channel 0 will trigger this interrupt*/ - uint32_t cap1_int_raw : 1; /*A capture on channel 1 will trigger this interrupt*/ - uint32_t cap2_int_raw : 1; /*A capture on channel 2 will trigger this interrupt*/ - uint32_t reserved30 : 2; - }; - uint32_t val; - } int_raw; - union { - struct { - uint32_t timer0_stop_int_st : 1; /*Interrupt when timer 0 stops*/ - uint32_t timer1_stop_int_st : 1; /*Interrupt when timer 1 stops*/ - uint32_t timer2_stop_int_st : 1; /*Interrupt when timer 2 stops*/ - uint32_t timer0_tez_int_st : 1; /*A PWM timer 0 TEZ event will trigger this interrupt*/ - uint32_t timer1_tez_int_st : 1; /*A PWM timer 1 TEZ event will trigger this interrupt*/ - uint32_t timer2_tez_int_st : 1; /*A PWM timer 2 TEZ event will trigger this interrupt*/ - uint32_t timer0_tep_int_st : 1; /*A PWM timer 0 TEP event will trigger this interrupt*/ - uint32_t timer1_tep_int_st : 1; /*A PWM timer 1 TEP event will trigger this interrupt*/ - uint32_t timer2_tep_int_st : 1; /*A PWM timer 2 TEP event will trigger this interrupt*/ - uint32_t fault0_int_st : 1; /*Interrupt when event_f0 starts*/ - uint32_t fault1_int_st : 1; /*Interrupt when event_f1 starts*/ - uint32_t fault2_int_st : 1; /*Interrupt when event_f2 starts*/ - uint32_t fault0_clr_int_st : 1; /*Interrupt when event_f0 ends*/ - uint32_t fault1_clr_int_st : 1; /*Interrupt when event_f1 ends*/ - uint32_t fault2_clr_int_st : 1; /*Interrupt when event_f2 ends*/ - uint32_t cmpr0_tea_int_st : 1; /*A PWM operator 0 TEA event will trigger this interrupt*/ - uint32_t cmpr1_tea_int_st : 1; /*A PWM operator 1 TEA event will trigger this interrupt*/ - uint32_t cmpr2_tea_int_st : 1; /*A PWM operator 2 TEA event will trigger this interrupt*/ - uint32_t cmpr0_teb_int_st : 1; /*A PWM operator 0 TEB event will trigger this interrupt*/ - uint32_t cmpr1_teb_int_st : 1; /*A PWM operator 1 TEB event will trigger this interrupt*/ - uint32_t cmpr2_teb_int_st : 1; /*A PWM operator 2 TEB event will trigger this interrupt*/ - uint32_t tz0_cbc_int_st : 1; /*An cycle-by-cycle trip event on PWM0 will trigger this interrupt*/ - uint32_t tz1_cbc_int_st : 1; /*An cycle-by-cycle trip event on PWM1 will trigger this interrupt*/ - uint32_t tz2_cbc_int_st : 1; /*An cycle-by-cycle trip event on PWM2 will trigger this interrupt*/ - uint32_t tz0_ost_int_st : 1; /*An one-shot trip event on PWM0 will trigger this interrupt*/ - uint32_t tz1_ost_int_st : 1; /*An one-shot trip event on PWM1 will trigger this interrupt*/ - uint32_t tz2_ost_int_st : 1; /*An one-shot trip event on PWM2 will trigger this interrupt*/ - uint32_t cap0_int_st : 1; /*A capture on channel 0 will trigger this interrupt*/ - uint32_t cap1_int_st : 1; /*A capture on channel 1 will trigger this interrupt*/ - uint32_t cap2_int_st : 1; /*A capture on channel 2 will trigger this interrupt*/ - uint32_t reserved30 : 2; - }; - uint32_t val; - } int_st; - union { - struct { - uint32_t timer0_stop_int_clr : 1; /*Interrupt when timer 0 stops*/ - uint32_t timer1_stop_int_clr : 1; /*Interrupt when timer 1 stops*/ - uint32_t timer2_stop_int_clr : 1; /*Interrupt when timer 2 stops*/ - uint32_t timer0_tez_int_clr : 1; /*A PWM timer 0 TEZ event will trigger this interrupt*/ - uint32_t timer1_tez_int_clr : 1; /*A PWM timer 1 TEZ event will trigger this interrupt*/ - uint32_t timer2_tez_int_clr : 1; /*A PWM timer 2 TEZ event will trigger this interrupt*/ - uint32_t timer0_tep_int_clr : 1; /*A PWM timer 0 TEP event will trigger this interrupt*/ - uint32_t timer1_tep_int_clr : 1; /*A PWM timer 1 TEP event will trigger this interrupt*/ - uint32_t timer2_tep_int_clr : 1; /*A PWM timer 2 TEP event will trigger this interrupt*/ - uint32_t fault0_int_clr : 1; /*Interrupt when event_f0 starts*/ - uint32_t fault1_int_clr : 1; /*Interrupt when event_f1 starts*/ - uint32_t fault2_int_clr : 1; /*Interrupt when event_f2 starts*/ - uint32_t fault0_clr_int_clr : 1; /*Interrupt when event_f0 ends*/ - uint32_t fault1_clr_int_clr : 1; /*Interrupt when event_f1 ends*/ - uint32_t fault2_clr_int_clr : 1; /*Interrupt when event_f2 ends*/ - uint32_t cmpr0_tea_int_clr : 1; /*A PWM operator 0 TEA event will trigger this interrupt*/ - uint32_t cmpr1_tea_int_clr : 1; /*A PWM operator 1 TEA event will trigger this interrupt*/ - uint32_t cmpr2_tea_int_clr : 1; /*A PWM operator 2 TEA event will trigger this interrupt*/ - uint32_t cmpr0_teb_int_clr : 1; /*A PWM operator 0 TEB event will trigger this interrupt*/ - uint32_t cmpr1_teb_int_clr : 1; /*A PWM operator 1 TEB event will trigger this interrupt*/ - uint32_t cmpr2_teb_int_clr : 1; /*A PWM operator 2 TEB event will trigger this interrupt*/ - uint32_t tz0_cbc_int_clr : 1; /*An cycle-by-cycle trip event on PWM0 will trigger this interrupt*/ - uint32_t tz1_cbc_int_clr : 1; /*An cycle-by-cycle trip event on PWM1 will trigger this interrupt*/ - uint32_t tz2_cbc_int_clr : 1; /*An cycle-by-cycle trip event on PWM2 will trigger this interrupt*/ - uint32_t tz0_ost_int_clr : 1; /*An one-shot trip event on PWM0 will trigger this interrupt*/ - uint32_t tz1_ost_int_clr : 1; /*An one-shot trip event on PWM1 will trigger this interrupt*/ - uint32_t tz2_ost_int_clr : 1; /*An one-shot trip event on PWM2 will trigger this interrupt*/ - uint32_t cap0_int_clr : 1; /*A capture on channel 0 will trigger this interrupt*/ - uint32_t cap1_int_clr : 1; /*A capture on channel 1 will trigger this interrupt*/ - uint32_t cap2_int_clr : 1; /*A capture on channel 2 will trigger this interrupt*/ - uint32_t reserved30 : 2; - }; - uint32_t val; - } int_clr; - union { - struct { - uint32_t clk_en : 1; /*Force clock on for this reg file*/ - uint32_t reserved1 : 31; - }; - uint32_t val; - } reg_clk; - union { - struct { - uint32_t date : 28; /*Version of this reg file*/ - uint32_t reserved28 : 4; - }; - uint32_t val; - } version; +/** Group: Prescaler configuration */ +/** Type of clk_cfg register + * PWM clock prescaler register. + */ +typedef union { + struct { + /** clk_prescale : R/W; bitpos: [7:0]; default: 0; + * Period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1) + */ + uint32_t clk_prescale: 8; + uint32_t reserved_8: 24; + }; + uint32_t val; +} mcpwm_clk_cfg_reg_t; + + +/** Group: MCPWM Timer Configuration and status */ +/** Type of timer_cfg0 register + * PWM timer period and update method configuration register. + */ +typedef union { + struct { + /** timer_prescale : R/W; bitpos: [7:0]; default: 0; + * Configure the divisor of PT0_clk, takes effect when PWM timer stops and starts + * agsin. period of PT0_clk = Period of PWM_clk * (PWM_TIMER_PRESCALE + 1) + */ + uint32_t timer_prescale: 8; + /** timer_period : R/W; bitpos: [23:8]; default: 255; + * period shadow register of PWM timer + */ + uint32_t timer_period: 16; + /** timer_period_upmethod : R/W; bitpos: [25:24]; default: 0; + * Update method for active register of PWM timer period, 0: immediate, 1: TEZ, 2: + * sync, 3: TEZ or sync. TEZ here and below means timer equal zero event + */ + uint32_t timer_period_upmethod: 2; + uint32_t reserved_26: 6; + }; + uint32_t val; +} mcpwm_timer_cfg0_reg_t; + +/** Type of timer_cfg1 register + * PWM timer working mode and start/stop control configuration register. + */ +typedef union { + struct { + /** timer_start : R/W/SC; bitpos: [2:0]; default: 0; + * PWM timer start and stop control. 0: if PWM timer starts, then stops at TEZ, 1: + * if timer starts, then stops at TEP, 2: PWM timer starts and runs on, 3: timer + * starts and stops at the next TEZ, 4: timer starts and stops at the next TEP. TEP + * here and below means the event that happens when the timer equals to period + */ + uint32_t timer_start: 3; + /** timer_mod : R/W; bitpos: [4:3]; default: 0; + * PWM timer working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down + * mode + */ + uint32_t timer_mod: 2; + uint32_t reserved_5: 27; + }; + uint32_t val; +} mcpwm_timer_cfg1_reg_t; + +/** Type of timer_sync register + * PWM timer sync function configuration register. + */ +typedef union { + struct { + /** timer_synci_en : R/W; bitpos: [0]; default: 0; + * When set, timer reloading with phase on sync input event is enabled. + */ + uint32_t timer_synci_en: 1; + /** timer_sync_sw : R/W; bitpos: [1]; default: 0; + * Toggling this bit will trigger a software sync. + */ + uint32_t timer_sync_sw: 1; + /** timer_synco_sel : R/W; bitpos: [3:2]; default: 0; + * PWM timer sync_out selection, 0: sync_in, 1: TEZ, 2: TEP, and sync out will always + * generate when toggling the reg_timer_sync_sw bit + */ + uint32_t timer_synco_sel: 2; + /** timer_phase : R/W; bitpos: [19:4]; default: 0; + * phase for timer reload on sync event + */ + uint32_t timer_phase: 16; + /** timer_phase_direction : R/W; bitpos: [20]; default: 0; + * Configure the PWM timer's direction at the time sync event occurs when timer mode + * is up-down mode: 0-increase,1-decrease + */ + uint32_t timer_phase_direction: 1; + uint32_t reserved_21: 11; + }; + uint32_t val; +} mcpwm_timer_sync_reg_t; + +/** Type of timer_status register + * PWM timer status register. + */ +typedef union { + struct { + /** timer_value : RO; bitpos: [15:0]; default: 0; + * current PWM timer counter value + */ + uint32_t timer_value: 16; + /** timer_direction : RO; bitpos: [16]; default: 0; + * current PWM timer counter direction, 0: increment 1: decrement + */ + uint32_t timer_direction: 1; + uint32_t reserved_17: 15; + }; + uint32_t val; +} mcpwm_timer_status_reg_t; + + +/** Group: Common configuration for MCPWM timers */ +/** Type of timer_synci_cfg register + * Synchronization input selection for three PWM timers. + */ +typedef union { + struct { + /** timer0_syncisel : R/W; bitpos: [2:0]; default: 0; + * select sync input for PWM timer0, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, + * 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: + * SYNC2 from GPIO matrix, other values: no sync input selected + */ + uint32_t timer0_syncisel: 3; + /** timer1_syncisel : R/W; bitpos: [5:3]; default: 0; + * select sync input for PWM timer1, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, + * 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: + * SYNC2 from GPIO matrix, other values: no sync input selected + */ + uint32_t timer1_syncisel: 3; + /** timer2_syncisel : R/W; bitpos: [8:6]; default: 0; + * select sync input for PWM timer2, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, + * 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: + * SYNC2 from GPIO matrix, other values: no sync input selected + */ + uint32_t timer2_syncisel: 3; + /** external_synci0_invert : R/W; bitpos: [9]; default: 0; + * invert SYNC0 from GPIO matrix + */ + uint32_t external_synci0_invert: 1; + /** external_synci1_invert : R/W; bitpos: [10]; default: 0; + * invert SYNC1 from GPIO matrix + */ + uint32_t external_synci1_invert: 1; + /** external_synci2_invert : R/W; bitpos: [11]; default: 0; + * invert SYNC2 from GPIO matrix + */ + uint32_t external_synci2_invert: 1; + uint32_t reserved_12: 20; + }; + uint32_t val; +} mcpwm_timer_synci_cfg_reg_t; + +/** Type of operator_timersel register + * Select specific timer for PWM operators. + */ +typedef union { + struct { + /** operator0_timersel : R/W; bitpos: [1:0]; default: 0; + * Select which PWM timer is the timing reference for PWM operator0, 0: timer0, 1: + * timer1, 2: timer2 + */ + uint32_t operator0_timersel: 2; + /** operator1_timersel : R/W; bitpos: [3:2]; default: 0; + * Select which PWM timer is the timing reference for PWM operator1, 0: timer0, 1: + * timer1, 2: timer2 + */ + uint32_t operator1_timersel: 2; + /** operator2_timersel : R/W; bitpos: [5:4]; default: 0; + * Select which PWM timer is the timing reference for PWM operator2, 0: timer0, 1: + * timer1, 2: timer2 + */ + uint32_t operator2_timersel: 2; + uint32_t reserved_6: 26; + }; + uint32_t val; +} mcpwm_operator_timersel_reg_t; + + +/** Group: MCPWM Operator Configuration and Status */ +/** Type of gen_stmp_cfg register + * Transfer status and update method for time stamp registers A and B + */ +typedef union { + struct { + /** gen_a_upmethod : R/W; bitpos: [3:0]; default: 0; + * Update method for PWM generator time stamp A's active register. When all bits are + * set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when + * bit2 is set to 1: sync, when bit3 is set to 1: disable the update. + */ + uint32_t gen_a_upmethod: 4; + /** gen_b_upmethod : R/W; bitpos: [7:4]; default: 0; + * Update method for PWM generator time stamp B's active register. When all bits are + * set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when + * bit2 is set to 1: sync, when bit3 is set to 1: disable the update. + */ + uint32_t gen_b_upmethod: 4; + /** gen_a_shdw_full : R/W/WTC/SC; bitpos: [8]; default: 0; + * Set and reset by hardware. If set, PWM generator time stamp A's shadow reg is + * filled and waiting to be transferred to A's active reg. If cleared, A's active reg + * has been updated with shadow register latest value + */ + uint32_t gen_a_shdw_full: 1; + /** gen_b_shdw_full : R/W/WTC/SC; bitpos: [9]; default: 0; + * Set and reset by hardware. If set, PWM generator time stamp B's shadow reg is + * filled and waiting to be transferred to B's active reg. If cleared, B's active reg + * has been updated with shadow register latest value + */ + uint32_t gen_b_shdw_full: 1; + uint32_t reserved_10: 22; + }; + uint32_t val; +} mcpwm_gen_stmp_cfg_reg_t; + +/** Type of gen_tstmp register + * PWM generator shadow register for timer stamp + */ +typedef union { + struct { + /** gen : R/W; bitpos: [15:0]; default: 0; + * PWM generator time stamp's shadow register + */ + uint32_t gen: 16; + uint32_t reserved_16: 16; + }; + uint32_t val; +} mcpwm_gen_tstmp_reg_t; + +/** Type of gen_cfg0 register + * PWM generator event T0 and T1 handling + */ +typedef union { + struct { + /** gen_cfg_upmethod : R/W; bitpos: [3:0]; default: 0; + * Update method for PWM generator's active register of configuration. When all bits + * are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to + * 1:TEP,when bit2 is set to 1:sync,when bit3 is set to 1:disable the update + */ + uint32_t gen_cfg_upmethod: 4; + /** gen_t0_sel : R/W; bitpos: [6:4]; default: 0; + * Source selection for PWM generator event_t0, take effect immediately, 0: + * fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none + */ + uint32_t gen_t0_sel: 3; + /** gen_t1_sel : R/W; bitpos: [9:7]; default: 0; + * Source selection for PWM generator event_t1, take effect immediately, 0: + * fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none + */ + uint32_t gen_t1_sel: 3; + uint32_t reserved_10: 22; + }; + uint32_t val; +} mcpwm_gen_cfg0_reg_t; + +/** Type of gen_force register + * Permissives to force PWM0A and PWM0B outputs by software + */ +typedef union { + struct { + /** gen_cntuforce_upmethod : R/W; bitpos: [5:0]; default: 32; + * Updating method for continuous software force of PWM generator0. When all bits are + * set to 0: immediately, when bit0 is set to 1: TEZ,,when bit1 is set to 1: TEP, when + * bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync, + * when bit5 is set to 1: disable update. (TEA/B here and below means an event + * generated when the timer's value equals to that of register A/B.) + */ + uint32_t gen_cntuforce_upmethod: 6; + /** gen_a_cntuforce_mode : R/W; bitpos: [7:6]; default: 0; + * Continuous software force mode for PWM0A. 0: disabled, 1: low, 2: high, 3: disabled + */ + uint32_t gen_a_cntuforce_mode: 2; + /** gen_b_cntuforce_mode : R/W; bitpos: [9:8]; default: 0; + * Continuous software force mode for PWM0B. 0: disabled, 1: low, 2: high, 3: disabled + */ + uint32_t gen_b_cntuforce_mode: 2; + /** gen_a_nciforce : R/W; bitpos: [10]; default: 0; + * Trigger of non-continuous immediate software-force event for PWM0A, a toggle will + * trigger a force event. + */ + uint32_t gen_a_nciforce: 1; + /** gen_a_nciforce_mode : R/W; bitpos: [12:11]; default: 0; + * non-continuous immediate software force mode for PWM0A, 0: disabled, 1: low, 2: + * high, 3: disabled + */ + uint32_t gen_a_nciforce_mode: 2; + /** gen_b_nciforce : R/W; bitpos: [13]; default: 0; + * Trigger of non-continuous immediate software-force event for PWM0B, a toggle will + * trigger a force event. + */ + uint32_t gen_b_nciforce: 1; + /** gen_b_nciforce_mode : R/W; bitpos: [15:14]; default: 0; + * non-continuous immediate software force mode for PWM0B, 0: disabled, 1: low, 2: + * high, 3: disabled + */ + uint32_t gen_b_nciforce_mode: 2; + uint32_t reserved_16: 16; + }; + uint32_t val; +} mcpwm_gen_force_reg_t; + +/** Type of generator register + * Actions triggered by events on PWM0A + */ +typedef union { + struct { + /** gen_utez : R/W; bitpos: [1:0]; default: 0; + * Action on PWM0A triggered by event TEZ when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ + uint32_t gen_utez: 2; + /** gen_utep : R/W; bitpos: [3:2]; default: 0; + * Action on PWM0A triggered by event TEP when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ + uint32_t gen_utep: 2; + /** gen_utea : R/W; bitpos: [5:4]; default: 0; + * Action on PWM0A triggered by event TEA when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ + uint32_t gen_utea: 2; + /** gen_uteb : R/W; bitpos: [7:6]; default: 0; + * Action on PWM0A triggered by event TEB when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ + uint32_t gen_uteb: 2; + /** gen_ut0 : R/W; bitpos: [9:8]; default: 0; + * Action on PWM0A triggered by event_t0 when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ + uint32_t gen_ut0: 2; + /** gen_ut1 : R/W; bitpos: [11:10]; default: 0; + * Action on PWM0A triggered by event_t1 when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ + uint32_t gen_ut1: 2; + /** gen_dtez : R/W; bitpos: [13:12]; default: 0; + * Action on PWM0A triggered by event TEZ when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ + uint32_t gen_dtez: 2; + /** gen_dtep : R/W; bitpos: [15:14]; default: 0; + * Action on PWM0A triggered by event TEP when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ + uint32_t gen_dtep: 2; + /** gen_dtea : R/W; bitpos: [17:16]; default: 0; + * Action on PWM0A triggered by event TEA when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ + uint32_t gen_dtea: 2; + /** gen_dteb : R/W; bitpos: [19:18]; default: 0; + * Action on PWM0A triggered by event TEB when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ + uint32_t gen_dteb: 2; + /** gen_dt0 : R/W; bitpos: [21:20]; default: 0; + * Action on PWM0A triggered by event_t0 when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ + uint32_t gen_dt0: 2; + /** gen_dt1 : R/W; bitpos: [23:22]; default: 0; + * Action on PWM0A triggered by event_t1 when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ + uint32_t gen_dt1: 2; + uint32_t reserved_24: 8; + }; + uint32_t val; +} mcpwm_gen_reg_t; + +/** Type of dt_cfg register + * PWM generator dead time type selection and configuration + */ +typedef union { + struct { + /** dt_fed_upmethod : R/W; bitpos: [3:0]; default: 0; + * Update method for FED (rising edge delay) active register. 0: immediate, when bit0 + * is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when + * bit3 is set to 1: disable the update + */ + uint32_t dt_fed_upmethod: 4; + /** dt_red_upmethod : R/W; bitpos: [7:4]; default: 0; + * Update method for RED (rising edge delay) active register. 0: immediate, when bit0 + * is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when + * bit3 is set to 1: disable the update + */ + uint32_t dt_red_upmethod: 4; + /** dt_deb_mode : R/W; bitpos: [8]; default: 0; + * S8 in table, dual-edge B mode, 0: fed/red take effect on different path separately, + * 1: fed/red take effect on B path, A out is in bypass or dulpB mode + */ + uint32_t dt_deb_mode: 1; + /** dt_a_outswap : R/W; bitpos: [9]; default: 0; + * S6 in table + */ + uint32_t dt_a_outswap: 1; + /** dt_b_outswap : R/W; bitpos: [10]; default: 0; + * S7 in table + */ + uint32_t dt_b_outswap: 1; + /** dt_red_insel : R/W; bitpos: [11]; default: 0; + * S4 in table + */ + uint32_t dt_red_insel: 1; + /** dt_fed_insel : R/W; bitpos: [12]; default: 0; + * S5 in table + */ + uint32_t dt_fed_insel: 1; + /** dt_red_outinvert : R/W; bitpos: [13]; default: 0; + * S2 in table + */ + uint32_t dt_red_outinvert: 1; + /** dt_fed_outinvert : R/W; bitpos: [14]; default: 0; + * S3 in table + */ + uint32_t dt_fed_outinvert: 1; + /** dt_a_outbypass : R/W; bitpos: [15]; default: 1; + * S1 in table + */ + uint32_t dt_a_outbypass: 1; + /** dt_b_outbypass : R/W; bitpos: [16]; default: 1; + * S0 in table + */ + uint32_t dt_b_outbypass: 1; + /** dt_clk_sel : R/W; bitpos: [17]; default: 0; + * Dead time clock selection. 0: PWM_clk, 1: PT_clk + */ + uint32_t dt_clk_sel: 1; + uint32_t reserved_18: 14; + }; + uint32_t val; +} mcpwm_dt_cfg_reg_t; + +/** Type of dt_fed_cfg register + * PWM generator shadow register for falling edge delay (FED). + */ +typedef union { + struct { + /** dt_fed : R/W; bitpos: [15:0]; default: 0; + * Shadow register for FED + */ + uint32_t dt_fed: 16; + uint32_t reserved_16: 16; + }; + uint32_t val; +} mcpwm_dt_fed_cfg_reg_t; + +/** Type of dt_red_cfg register + * PWM generator shadow register for rising edge delay (RED). + */ +typedef union { + struct { + /** dt_red : R/W; bitpos: [15:0]; default: 0; + * Shadow register for RED + */ + uint32_t dt_red: 16; + uint32_t reserved_16: 16; + }; + uint32_t val; +} mcpwm_dt_red_cfg_reg_t; + +/** Type of carrier_cfg register + * PWM generator carrier enable and configuratoin + */ +typedef union { + struct { + /** carrier_en : R/W; bitpos: [0]; default: 0; + * When set, carrier function is enabled. When cleared, carrier is bypassed + */ + uint32_t carrier_en: 1; + /** carrier_prescale : R/W; bitpos: [4:1]; default: 0; + * PWM carrier clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk * + * (PWM_CARRIER_PRESCALE + 1) + */ + uint32_t carrier_prescale: 4; + /** carrier_duty : R/W; bitpos: [7:5]; default: 0; + * carrier duty selection. Duty = PWM_CARRIER_DUTY / 8 + */ + uint32_t carrier_duty: 3; + /** carrier_oshtwth : R/W; bitpos: [11:8]; default: 0; + * width of the first pulse in number of periods of the carrier + */ + uint32_t carrier_oshtwth: 4; + /** carrier_out_invert : R/W; bitpos: [12]; default: 0; + * when set, invert the output of PWM0A and PWM0B for this submodule + */ + uint32_t carrier_out_invert: 1; + /** carrier_in_invert : R/W; bitpos: [13]; default: 0; + * when set, invert the input of PWM0A and PWM0B for this submodule + */ + uint32_t carrier_in_invert: 1; + uint32_t reserved_14: 18; + }; + uint32_t val; +} mcpwm_carrier_cfg_reg_t; + +/** Type of fh_cfg0 register + * Actions on PWM0A and PWM0B trip events + */ +typedef union { + struct { + /** fh_sw_cbc : R/W; bitpos: [0]; default: 0; + * Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable + */ + uint32_t fh_sw_cbc: 1; + /** fh_f2_cbc : R/W; bitpos: [1]; default: 0; + * fault_event2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + */ + uint32_t fh_f2_cbc: 1; + /** fh_f1_cbc : R/W; bitpos: [2]; default: 0; + * fault_event1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + */ + uint32_t fh_f1_cbc: 1; + /** fh_f0_cbc : R/W; bitpos: [3]; default: 0; + * fault_event0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + */ + uint32_t fh_f0_cbc: 1; + /** fh_sw_ost : R/W; bitpos: [4]; default: 0; + * Enable register for software force one-shot mode action. 0: disable, 1: enable + */ + uint32_t fh_sw_ost: 1; + /** fh_f2_ost : R/W; bitpos: [5]; default: 0; + * fault_event2 will trigger one-shot mode action. 0: disable, 1: enable + */ + uint32_t fh_f2_ost: 1; + /** fh_f1_ost : R/W; bitpos: [6]; default: 0; + * fault_event1 will trigger one-shot mode action. 0: disable, 1: enable + */ + uint32_t fh_f1_ost: 1; + /** fh_f0_ost : R/W; bitpos: [7]; default: 0; + * fault_event0 will trigger one-shot mode action. 0: disable, 1: enable + */ + uint32_t fh_f0_ost: 1; + /** fh_a_cbc_d : R/W; bitpos: [9:8]; default: 0; + * Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is + * decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + */ + uint32_t fh_a_cbc_d: 2; + /** fh_a_cbc_u : R/W; bitpos: [11:10]; default: 0; + * Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is + * increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + */ + uint32_t fh_a_cbc_u: 2; + /** fh_a_ost_d : R/W; bitpos: [13:12]; default: 0; + * One-shot mode action on PWM0A when fault event occurs and timer is decreasing. 0: + * do nothing, 1: force low, 2: force high, 3: toggle + */ + uint32_t fh_a_ost_d: 2; + /** fh_a_ost_u : R/W; bitpos: [15:14]; default: 0; + * One-shot mode action on PWM0A when fault event occurs and timer is increasing. 0: + * do nothing, 1: force low, 2: force high, 3: toggle + */ + uint32_t fh_a_ost_u: 2; + /** fh_b_cbc_d : R/W; bitpos: [17:16]; default: 0; + * Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is + * decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + */ + uint32_t fh_b_cbc_d: 2; + /** fh_b_cbc_u : R/W; bitpos: [19:18]; default: 0; + * Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is + * increasing. 0: do nothing,1: force low, 2: force high, 3: toggle + */ + uint32_t fh_b_cbc_u: 2; + /** fh_b_ost_d : R/W; bitpos: [21:20]; default: 0; + * One-shot mode action on PWM0B when fault event occurs and timer is decreasing. 0: + * do nothing, 1: force low, 2: force high, 3: toggle + */ + uint32_t fh_b_ost_d: 2; + /** fh_b_ost_u : R/W; bitpos: [23:22]; default: 0; + * One-shot mode action on PWM0B when fault event occurs and timer is increasing. 0: + * do nothing, 1: force low, 2: force high, 3: toggle + */ + uint32_t fh_b_ost_u: 2; + uint32_t reserved_24: 8; + }; + uint32_t val; +} mcpwm_fh_cfg0_reg_t; + +/** Type of fh_cfg1 register + * Software triggers for fault handler actions + */ +typedef union { + struct { + /** fh_clr_ost : R/W; bitpos: [0]; default: 0; + * a rising edge will clear on going one-shot mode action + */ + uint32_t fh_clr_ost: 1; + /** fh_cbcpulse : R/W; bitpos: [2:1]; default: 0; + * cycle-by-cycle mode action refresh moment selection. When bit0 is set to 1: TEZ, + * when bit1 is set to 1:TEP, when bit0 and bit1 both set to 0: stop refresh, when + * bit0 and bit1 both set to 1: refresh at TEP/TEZ + */ + uint32_t fh_cbcpulse: 2; + /** fh_force_cbc : R/W; bitpos: [3]; default: 0; + * a toggle trigger a cycle-by-cycle mode action + */ + uint32_t fh_force_cbc: 1; + /** fh_force_ost : R/W; bitpos: [4]; default: 0; + * a toggle (software negate its value) triggers a one-shot mode action + */ + uint32_t fh_force_ost: 1; + uint32_t reserved_5: 27; + }; + uint32_t val; +} mcpwm_fh_cfg1_reg_t; + +/** Type of fh_status register + * Status of fault events. + */ +typedef union { + struct { + /** fh_cbc_on : RO; bitpos: [0]; default: 0; + * Set and reset by hardware. If set, a cycle-by-cycle mode action is on going + */ + uint32_t fh_cbc_on: 1; + /** fh_ost_on : RO; bitpos: [1]; default: 0; + * Set and reset by hardware. If set, an one-shot mode action is on going + */ + uint32_t fh_ost_on: 1; + uint32_t reserved_2: 30; + }; + uint32_t val; +} mcpwm_fh_status_reg_t; + +/** Group: Fault Detection Configuration and Status */ +/** Type of fault_detect register + * Fault detection configuration and status + */ +typedef union { + struct { + /** f0_en : R/W; bitpos: [0]; default: 0; + * When set, fault_event0 generation is enabled + */ + uint32_t f0_en: 1; + /** f1_en : R/W; bitpos: [1]; default: 0; + * When set, fault_event1 generation is enabled + */ + uint32_t f1_en: 1; + /** f2_en : R/W; bitpos: [2]; default: 0; + * When set, fault_event2 generation is enabled + */ + uint32_t f2_en: 1; + /** f0_pole : R/W; bitpos: [3]; default: 0; + * Set fault_event0 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, + * 1: level high + */ + uint32_t f0_pole: 1; + /** f1_pole : R/W; bitpos: [4]; default: 0; + * Set fault_event1 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, + * 1: level high + */ + uint32_t f1_pole: 1; + /** f2_pole : R/W; bitpos: [5]; default: 0; + * Set fault_event2 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, + * 1: level high + */ + uint32_t f2_pole: 1; + /** event_f0 : RO; bitpos: [6]; default: 0; + * Set and reset by hardware. If set, fault_event0 is on going + */ + uint32_t event_f0: 1; + /** event_f1 : RO; bitpos: [7]; default: 0; + * Set and reset by hardware. If set, fault_event1 is on going + */ + uint32_t event_f1: 1; + /** event_f2 : RO; bitpos: [8]; default: 0; + * Set and reset by hardware. If set, fault_event2 is on going + */ + uint32_t event_f2: 1; + uint32_t reserved_9: 23; + }; + uint32_t val; +} mcpwm_fault_detect_reg_t; + + +/** Group: Capture Configuration and Status */ +/** Type of cap_timer_cfg register + * Configure capture timer + */ +typedef union { + struct { + /** cap_timer_en : R/W; bitpos: [0]; default: 0; + * When set, capture timer incrementing under APB_clk is enabled. + */ + uint32_t cap_timer_en: 1; + /** cap_synci_en : R/W; bitpos: [1]; default: 0; + * When set, capture timer sync is enabled. + */ + uint32_t cap_synci_en: 1; + /** cap_synci_sel : R/W; bitpos: [4:2]; default: 0; + * capture module sync input selection. 0: none, 1: timer0 sync_out, 2: timer1 + * sync_out, 3: timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, + * 6: SYNC2 from GPIO matrix + */ + uint32_t cap_synci_sel: 3; + /** cap_sync_sw : WT; bitpos: [5]; default: 0; + * When reg_cap_synci_en is 1, write 1 will trigger a capture timer sync, capture + * timer is loaded with value in phase register. + */ + uint32_t cap_sync_sw: 1; + uint32_t reserved_6: 26; + }; + uint32_t val; +} mcpwm_cap_timer_cfg_reg_t; + +/** Type of cap_timer_phase register + * Phase for capture timer sync + */ +typedef union { + struct { + /** cap_timer_phase : R/W; bitpos: [31:0]; default: 0; + * Phase value for capture timer sync operation. + */ + uint32_t cap_timer_phase: 32; + }; + uint32_t val; +} mcpwm_cap_timer_phase_reg_t; + +/** Type of cap_chn_cfg register + * Capture channel 0 configuration and enable + */ +typedef union { + struct { + /** capn_en : R/W; bitpos: [0]; default: 0; + * When set, capture on channel 0 is enabled + */ + uint32_t capn_en: 1; + /** capn_mode : R/W; bitpos: [2:1]; default: 0; + * Edge of capture on channel 0 after prescaling. When bit0 is set to 1: enable + * capture on the negative edge, When bit1 is set to 1: enable capture on the positive + * edge. + */ + uint32_t capn_mode: 2; + /** capn_prescale : R/W; bitpos: [10:3]; default: 0; + * Value of prescaling on possitive edge of CAPn. Prescale value = PWM_CAPn_PRESCALE + + * 1 + */ + uint32_t capn_prescale: 8; + /** capn_in_invert : R/W; bitpos: [11]; default: 0; + * when set, CAPn form GPIO matrix is inverted before prescale + */ + uint32_t capn_in_invert: 1; + /** capn_sw : WT; bitpos: [12]; default: 0; + * Write 1 will trigger a software forced capture on channel 0 + */ + uint32_t capn_sw: 1; + uint32_t reserved_13: 19; + }; + uint32_t val; +} mcpwm_cap_chn_cfg_reg_t; + +/** Type of cap_chn register + * chn capture value status register + */ +typedef union { + struct { + /** capn_value : RO; bitpos: [31:0]; default: 0; + * Value of last capture on channel n + */ + uint32_t capn_value: 32; + }; + uint32_t val; +} mcpwm_cap_chn_reg_t; + +/** Type of cap_status register + * Edge of last capture trigger + */ +typedef union { + struct { + /** cap0_edge : RO; bitpos: [0]; default: 0; + * Edge of last capture trigger on channel 0, 0: posedge, 1: negedge + */ + uint32_t cap0_edge: 1; + /** cap1_edge : RO; bitpos: [1]; default: 0; + * Edge of last capture trigger on channel 1, 0: posedge, 1: negedge + */ + uint32_t cap1_edge: 1; + /** cap2_edge : RO; bitpos: [2]; default: 0; + * Edge of last capture trigger on channel 2, 0: posedge, 1: negedge + */ + uint32_t cap2_edge: 1; + uint32_t reserved_3: 29; + }; + uint32_t val; +} mcpwm_cap_status_reg_t; + + +/** Group: Enable update of active registers */ +/** Type of update_cfg register + * Enable update. + */ +typedef union { + struct { + /** global_up_en : R/W; bitpos: [0]; default: 1; + * The global enable of update of all active registers in MCPWM module + */ + uint32_t global_up_en: 1; + /** global_force_up : R/W; bitpos: [1]; default: 0; + * a toggle (software invert its value) will trigger a forced update of all active + * registers in MCPWM module + */ + uint32_t global_force_up: 1; + /** op0_up_en : R/W; bitpos: [2]; default: 1; + * When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 0 + * are enabled + */ + uint32_t op0_up_en: 1; + /** op0_force_up : R/W; bitpos: [3]; default: 0; + * a toggle (software invert its value) will trigger a forced update of active + * registers in PWM operator 0 + */ + uint32_t op0_force_up: 1; + /** op1_up_en : R/W; bitpos: [4]; default: 1; + * When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 1 + * are enabled + */ + uint32_t op1_up_en: 1; + /** op1_force_up : R/W; bitpos: [5]; default: 0; + * a toggle (software invert its value) will trigger a forced update of active + * registers in PWM operator 1 + */ + uint32_t op1_force_up: 1; + /** op2_up_en : R/W; bitpos: [6]; default: 1; + * When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 2 + * are enabled + */ + uint32_t op2_up_en: 1; + /** op2_force_up : R/W; bitpos: [7]; default: 0; + * a toggle (software invert its value) will trigger a forced update of active + * registers in PWM operator 2 + */ + uint32_t op2_force_up: 1; + uint32_t reserved_8: 24; + }; + uint32_t val; +} mcpwm_update_cfg_reg_t; + + +/** Group: Manage Interrupts */ +/** Type of int_ena register + * Interrupt enable bits + */ +typedef union { + struct { + /** timer0_stop_int_ena : R/W; bitpos: [0]; default: 0; + * The enable bit for the interrupt triggered when the timer 0 stops. + */ + uint32_t timer0_stop_int_ena: 1; + /** timer1_stop_int_ena : R/W; bitpos: [1]; default: 0; + * The enable bit for the interrupt triggered when the timer 1 stops. + */ + uint32_t timer1_stop_int_ena: 1; + /** timer2_stop_int_ena : R/W; bitpos: [2]; default: 0; + * The enable bit for the interrupt triggered when the timer 2 stops. + */ + uint32_t timer2_stop_int_ena: 1; + /** timer0_tez_int_ena : R/W; bitpos: [3]; default: 0; + * The enable bit for the interrupt triggered by a PWM timer 0 TEZ event. + */ + uint32_t timer0_tez_int_ena: 1; + /** timer1_tez_int_ena : R/W; bitpos: [4]; default: 0; + * The enable bit for the interrupt triggered by a PWM timer 1 TEZ event. + */ + uint32_t timer1_tez_int_ena: 1; + /** timer2_tez_int_ena : R/W; bitpos: [5]; default: 0; + * The enable bit for the interrupt triggered by a PWM timer 2 TEZ event. + */ + uint32_t timer2_tez_int_ena: 1; + /** timer0_tep_int_ena : R/W; bitpos: [6]; default: 0; + * The enable bit for the interrupt triggered by a PWM timer 0 TEP event. + */ + uint32_t timer0_tep_int_ena: 1; + /** timer1_tep_int_ena : R/W; bitpos: [7]; default: 0; + * The enable bit for the interrupt triggered by a PWM timer 1 TEP event. + */ + uint32_t timer1_tep_int_ena: 1; + /** timer2_tep_int_ena : R/W; bitpos: [8]; default: 0; + * The enable bit for the interrupt triggered by a PWM timer 2 TEP event. + */ + uint32_t timer2_tep_int_ena: 1; + /** fault0_int_ena : R/W; bitpos: [9]; default: 0; + * The enable bit for the interrupt triggered when fault_event0 starts. + */ + uint32_t fault0_int_ena: 1; + /** fault1_int_ena : R/W; bitpos: [10]; default: 0; + * The enable bit for the interrupt triggered when fault_event1 starts. + */ + uint32_t fault1_int_ena: 1; + /** fault2_int_ena : R/W; bitpos: [11]; default: 0; + * The enable bit for the interrupt triggered when fault_event2 starts. + */ + uint32_t fault2_int_ena: 1; + /** fault0_clr_int_ena : R/W; bitpos: [12]; default: 0; + * The enable bit for the interrupt triggered when fault_event0 ends. + */ + uint32_t fault0_clr_int_ena: 1; + /** fault1_clr_int_ena : R/W; bitpos: [13]; default: 0; + * The enable bit for the interrupt triggered when fault_event1 ends. + */ + uint32_t fault1_clr_int_ena: 1; + /** fault2_clr_int_ena : R/W; bitpos: [14]; default: 0; + * The enable bit for the interrupt triggered when fault_event2 ends. + */ + uint32_t fault2_clr_int_ena: 1; + /** op0_tea_int_ena : R/W; bitpos: [15]; default: 0; + * The enable bit for the interrupt triggered by a PWM operator 0 TEA event + */ + uint32_t op0_tea_int_ena: 1; + /** op1_tea_int_ena : R/W; bitpos: [16]; default: 0; + * The enable bit for the interrupt triggered by a PWM operator 1 TEA event + */ + uint32_t op1_tea_int_ena: 1; + /** op2_tea_int_ena : R/W; bitpos: [17]; default: 0; + * The enable bit for the interrupt triggered by a PWM operator 2 TEA event + */ + uint32_t op2_tea_int_ena: 1; + /** op0_teb_int_ena : R/W; bitpos: [18]; default: 0; + * The enable bit for the interrupt triggered by a PWM operator 0 TEB event + */ + uint32_t op0_teb_int_ena: 1; + /** op1_teb_int_ena : R/W; bitpos: [19]; default: 0; + * The enable bit for the interrupt triggered by a PWM operator 1 TEB event + */ + uint32_t op1_teb_int_ena: 1; + /** op2_teb_int_ena : R/W; bitpos: [20]; default: 0; + * The enable bit for the interrupt triggered by a PWM operator 2 TEB event + */ + uint32_t op2_teb_int_ena: 1; + /** fh0_cbc_int_ena : R/W; bitpos: [21]; default: 0; + * The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0. + */ + uint32_t fh0_cbc_int_ena: 1; + /** fh1_cbc_int_ena : R/W; bitpos: [22]; default: 0; + * The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1. + */ + uint32_t fh1_cbc_int_ena: 1; + /** fh2_cbc_int_ena : R/W; bitpos: [23]; default: 0; + * The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2. + */ + uint32_t fh2_cbc_int_ena: 1; + /** fh0_ost_int_ena : R/W; bitpos: [24]; default: 0; + * The enable bit for the interrupt triggered by a one-shot mode action on PWM0. + */ + uint32_t fh0_ost_int_ena: 1; + /** fh1_ost_int_ena : R/W; bitpos: [25]; default: 0; + * The enable bit for the interrupt triggered by a one-shot mode action on PWM1. + */ + uint32_t fh1_ost_int_ena: 1; + /** fh2_ost_int_ena : R/W; bitpos: [26]; default: 0; + * The enable bit for the interrupt triggered by a one-shot mode action on PWM2. + */ + uint32_t fh2_ost_int_ena: 1; + /** cap0_int_ena : R/W; bitpos: [27]; default: 0; + * The enable bit for the interrupt triggered by capture on channel 0. + */ + uint32_t cap0_int_ena: 1; + /** cap1_int_ena : R/W; bitpos: [28]; default: 0; + * The enable bit for the interrupt triggered by capture on channel 1. + */ + uint32_t cap1_int_ena: 1; + /** cap2_int_ena : R/W; bitpos: [29]; default: 0; + * The enable bit for the interrupt triggered by capture on channel 2. + */ + uint32_t cap2_int_ena: 1; + uint32_t reserved_30: 2; + }; + uint32_t val; +} mcpwm_int_ena_reg_t; + +/** Type of int_raw register + * Raw interrupt status + */ +typedef union { + struct { + /** timer0_stop_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * The raw status bit for the interrupt triggered when the timer 0 stops. + */ + uint32_t timer0_stop_int_raw: 1; + /** timer1_stop_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * The raw status bit for the interrupt triggered when the timer 1 stops. + */ + uint32_t timer1_stop_int_raw: 1; + /** timer2_stop_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The raw status bit for the interrupt triggered when the timer 2 stops. + */ + uint32_t timer2_stop_int_raw: 1; + /** timer0_tez_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * The raw status bit for the interrupt triggered by a PWM timer 0 TEZ event. + */ + uint32_t timer0_tez_int_raw: 1; + /** timer1_tez_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * The raw status bit for the interrupt triggered by a PWM timer 1 TEZ event. + */ + uint32_t timer1_tez_int_raw: 1; + /** timer2_tez_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * The raw status bit for the interrupt triggered by a PWM timer 2 TEZ event. + */ + uint32_t timer2_tez_int_raw: 1; + /** timer0_tep_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * The raw status bit for the interrupt triggered by a PWM timer 0 TEP event. + */ + uint32_t timer0_tep_int_raw: 1; + /** timer1_tep_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + * The raw status bit for the interrupt triggered by a PWM timer 1 TEP event. + */ + uint32_t timer1_tep_int_raw: 1; + /** timer2_tep_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * The raw status bit for the interrupt triggered by a PWM timer 2 TEP event. + */ + uint32_t timer2_tep_int_raw: 1; + /** fault0_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * The raw status bit for the interrupt triggered when fault_event0 starts. + */ + uint32_t fault0_int_raw: 1; + /** fault1_int_raw : R/WTC/SS; bitpos: [10]; default: 0; + * The raw status bit for the interrupt triggered when fault_event1 starts. + */ + uint32_t fault1_int_raw: 1; + /** fault2_int_raw : R/WTC/SS; bitpos: [11]; default: 0; + * The raw status bit for the interrupt triggered when fault_event2 starts. + */ + uint32_t fault2_int_raw: 1; + /** fault0_clr_int_raw : R/WTC/SS; bitpos: [12]; default: 0; + * The raw status bit for the interrupt triggered when fault_event0 ends. + */ + uint32_t fault0_clr_int_raw: 1; + /** fault1_clr_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + * The raw status bit for the interrupt triggered when fault_event1 ends. + */ + uint32_t fault1_clr_int_raw: 1; + /** fault2_clr_int_raw : R/WTC/SS; bitpos: [14]; default: 0; + * The raw status bit for the interrupt triggered when fault_event2 ends. + */ + uint32_t fault2_clr_int_raw: 1; + /** op0_tea_int_raw : R/WTC/SS; bitpos: [15]; default: 0; + * The raw status bit for the interrupt triggered by a PWM operator 0 TEA event + */ + uint32_t op0_tea_int_raw: 1; + /** op1_tea_int_raw : R/WTC/SS; bitpos: [16]; default: 0; + * The raw status bit for the interrupt triggered by a PWM operator 1 TEA event + */ + uint32_t op1_tea_int_raw: 1; + /** op2_tea_int_raw : R/WTC/SS; bitpos: [17]; default: 0; + * The raw status bit for the interrupt triggered by a PWM operator 2 TEA event + */ + uint32_t op2_tea_int_raw: 1; + /** op0_teb_int_raw : R/WTC/SS; bitpos: [18]; default: 0; + * The raw status bit for the interrupt triggered by a PWM operator 0 TEB event + */ + uint32_t op0_teb_int_raw: 1; + /** op1_teb_int_raw : R/WTC/SS; bitpos: [19]; default: 0; + * The raw status bit for the interrupt triggered by a PWM operator 1 TEB event + */ + uint32_t op1_teb_int_raw: 1; + /** op2_teb_int_raw : R/WTC/SS; bitpos: [20]; default: 0; + * The raw status bit for the interrupt triggered by a PWM operator 2 TEB event + */ + uint32_t op2_teb_int_raw: 1; + /** fh0_cbc_int_raw : R/WTC/SS; bitpos: [21]; default: 0; + * The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on + * PWM0. + */ + uint32_t fh0_cbc_int_raw: 1; + /** fh1_cbc_int_raw : R/WTC/SS; bitpos: [22]; default: 0; + * The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on + * PWM1. + */ + uint32_t fh1_cbc_int_raw: 1; + /** fh2_cbc_int_raw : R/WTC/SS; bitpos: [23]; default: 0; + * The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on + * PWM2. + */ + uint32_t fh2_cbc_int_raw: 1; + /** fh0_ost_int_raw : R/WTC/SS; bitpos: [24]; default: 0; + * The raw status bit for the interrupt triggered by a one-shot mode action on PWM0. + */ + uint32_t fh0_ost_int_raw: 1; + /** fh1_ost_int_raw : R/WTC/SS; bitpos: [25]; default: 0; + * The raw status bit for the interrupt triggered by a one-shot mode action on PWM1. + */ + uint32_t fh1_ost_int_raw: 1; + /** fh2_ost_int_raw : R/WTC/SS; bitpos: [26]; default: 0; + * The raw status bit for the interrupt triggered by a one-shot mode action on PWM2. + */ + uint32_t fh2_ost_int_raw: 1; + /** cap0_int_raw : R/WTC/SS; bitpos: [27]; default: 0; + * The raw status bit for the interrupt triggered by capture on channel 0. + */ + uint32_t cap0_int_raw: 1; + /** cap1_int_raw : R/WTC/SS; bitpos: [28]; default: 0; + * The raw status bit for the interrupt triggered by capture on channel 1. + */ + uint32_t cap1_int_raw: 1; + /** cap2_int_raw : R/WTC/SS; bitpos: [29]; default: 0; + * The raw status bit for the interrupt triggered by capture on channel 2. + */ + uint32_t cap2_int_raw: 1; + uint32_t reserved_30: 2; + }; + uint32_t val; +} mcpwm_int_raw_reg_t; + +/** Type of int_st register + * Masked interrupt status + */ +typedef union { + struct { + /** timer0_stop_int_st : RO; bitpos: [0]; default: 0; + * The masked status bit for the interrupt triggered when the timer 0 stops. + */ + uint32_t timer0_stop_int_st: 1; + /** timer1_stop_int_st : RO; bitpos: [1]; default: 0; + * The masked status bit for the interrupt triggered when the timer 1 stops. + */ + uint32_t timer1_stop_int_st: 1; + /** timer2_stop_int_st : RO; bitpos: [2]; default: 0; + * The masked status bit for the interrupt triggered when the timer 2 stops. + */ + uint32_t timer2_stop_int_st: 1; + /** timer0_tez_int_st : RO; bitpos: [3]; default: 0; + * The masked status bit for the interrupt triggered by a PWM timer 0 TEZ event. + */ + uint32_t timer0_tez_int_st: 1; + /** timer1_tez_int_st : RO; bitpos: [4]; default: 0; + * The masked status bit for the interrupt triggered by a PWM timer 1 TEZ event. + */ + uint32_t timer1_tez_int_st: 1; + /** timer2_tez_int_st : RO; bitpos: [5]; default: 0; + * The masked status bit for the interrupt triggered by a PWM timer 2 TEZ event. + */ + uint32_t timer2_tez_int_st: 1; + /** timer0_tep_int_st : RO; bitpos: [6]; default: 0; + * The masked status bit for the interrupt triggered by a PWM timer 0 TEP event. + */ + uint32_t timer0_tep_int_st: 1; + /** timer1_tep_int_st : RO; bitpos: [7]; default: 0; + * The masked status bit for the interrupt triggered by a PWM timer 1 TEP event. + */ + uint32_t timer1_tep_int_st: 1; + /** timer2_tep_int_st : RO; bitpos: [8]; default: 0; + * The masked status bit for the interrupt triggered by a PWM timer 2 TEP event. + */ + uint32_t timer2_tep_int_st: 1; + /** fault0_int_st : RO; bitpos: [9]; default: 0; + * The masked status bit for the interrupt triggered when fault_event0 starts. + */ + uint32_t fault0_int_st: 1; + /** fault1_int_st : RO; bitpos: [10]; default: 0; + * The masked status bit for the interrupt triggered when fault_event1 starts. + */ + uint32_t fault1_int_st: 1; + /** fault2_int_st : RO; bitpos: [11]; default: 0; + * The masked status bit for the interrupt triggered when fault_event2 starts. + */ + uint32_t fault2_int_st: 1; + /** fault0_clr_int_st : RO; bitpos: [12]; default: 0; + * The masked status bit for the interrupt triggered when fault_event0 ends. + */ + uint32_t fault0_clr_int_st: 1; + /** fault1_clr_int_st : RO; bitpos: [13]; default: 0; + * The masked status bit for the interrupt triggered when fault_event1 ends. + */ + uint32_t fault1_clr_int_st: 1; + /** fault2_clr_int_st : RO; bitpos: [14]; default: 0; + * The masked status bit for the interrupt triggered when fault_event2 ends. + */ + uint32_t fault2_clr_int_st: 1; + /** op0_tea_int_st : RO; bitpos: [15]; default: 0; + * The masked status bit for the interrupt triggered by a PWM operator 0 TEA event + */ + uint32_t op0_tea_int_st: 1; + /** op1_tea_int_st : RO; bitpos: [16]; default: 0; + * The masked status bit for the interrupt triggered by a PWM operator 1 TEA event + */ + uint32_t op1_tea_int_st: 1; + /** op2_tea_int_st : RO; bitpos: [17]; default: 0; + * The masked status bit for the interrupt triggered by a PWM operator 2 TEA event + */ + uint32_t op2_tea_int_st: 1; + /** op0_teb_int_st : RO; bitpos: [18]; default: 0; + * The masked status bit for the interrupt triggered by a PWM operator 0 TEB event + */ + uint32_t op0_teb_int_st: 1; + /** op1_teb_int_st : RO; bitpos: [19]; default: 0; + * The masked status bit for the interrupt triggered by a PWM operator 1 TEB event + */ + uint32_t op1_teb_int_st: 1; + /** op2_teb_int_st : RO; bitpos: [20]; default: 0; + * The masked status bit for the interrupt triggered by a PWM operator 2 TEB event + */ + uint32_t op2_teb_int_st: 1; + /** fh0_cbc_int_st : RO; bitpos: [21]; default: 0; + * The masked status bit for the interrupt triggered by a cycle-by-cycle mode action + * on PWM0. + */ + uint32_t fh0_cbc_int_st: 1; + /** fh1_cbc_int_st : RO; bitpos: [22]; default: 0; + * The masked status bit for the interrupt triggered by a cycle-by-cycle mode action + * on PWM1. + */ + uint32_t fh1_cbc_int_st: 1; + /** fh2_cbc_int_st : RO; bitpos: [23]; default: 0; + * The masked status bit for the interrupt triggered by a cycle-by-cycle mode action + * on PWM2. + */ + uint32_t fh2_cbc_int_st: 1; + /** fh0_ost_int_st : RO; bitpos: [24]; default: 0; + * The masked status bit for the interrupt triggered by a one-shot mode action on PWM0. + */ + uint32_t fh0_ost_int_st: 1; + /** fh1_ost_int_st : RO; bitpos: [25]; default: 0; + * The masked status bit for the interrupt triggered by a one-shot mode action on PWM1. + */ + uint32_t fh1_ost_int_st: 1; + /** fh2_ost_int_st : RO; bitpos: [26]; default: 0; + * The masked status bit for the interrupt triggered by a one-shot mode action on PWM2. + */ + uint32_t fh2_ost_int_st: 1; + /** cap0_int_st : RO; bitpos: [27]; default: 0; + * The masked status bit for the interrupt triggered by capture on channel 0. + */ + uint32_t cap0_int_st: 1; + /** cap1_int_st : RO; bitpos: [28]; default: 0; + * The masked status bit for the interrupt triggered by capture on channel 1. + */ + uint32_t cap1_int_st: 1; + /** cap2_int_st : RO; bitpos: [29]; default: 0; + * The masked status bit for the interrupt triggered by capture on channel 2. + */ + uint32_t cap2_int_st: 1; + uint32_t reserved_30: 2; + }; + uint32_t val; +} mcpwm_int_st_reg_t; + +/** Type of int_clr register + * Interrupt clear bits + */ +typedef union { + struct { + /** timer0_stop_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear the interrupt triggered when the timer 0 stops. + */ + uint32_t timer0_stop_int_clr: 1; + /** timer1_stop_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear the interrupt triggered when the timer 1 stops. + */ + uint32_t timer1_stop_int_clr: 1; + /** timer2_stop_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear the interrupt triggered when the timer 2 stops. + */ + uint32_t timer2_stop_int_clr: 1; + /** timer0_tez_int_clr : WT; bitpos: [3]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM timer 0 TEZ event. + */ + uint32_t timer0_tez_int_clr: 1; + /** timer1_tez_int_clr : WT; bitpos: [4]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM timer 1 TEZ event. + */ + uint32_t timer1_tez_int_clr: 1; + /** timer2_tez_int_clr : WT; bitpos: [5]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM timer 2 TEZ event. + */ + uint32_t timer2_tez_int_clr: 1; + /** timer0_tep_int_clr : WT; bitpos: [6]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM timer 0 TEP event. + */ + uint32_t timer0_tep_int_clr: 1; + /** timer1_tep_int_clr : WT; bitpos: [7]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM timer 1 TEP event. + */ + uint32_t timer1_tep_int_clr: 1; + /** timer2_tep_int_clr : WT; bitpos: [8]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM timer 2 TEP event. + */ + uint32_t timer2_tep_int_clr: 1; + /** fault0_int_clr : WT; bitpos: [9]; default: 0; + * Set this bit to clear the interrupt triggered when fault_event0 starts. + */ + uint32_t fault0_int_clr: 1; + /** fault1_int_clr : WT; bitpos: [10]; default: 0; + * Set this bit to clear the interrupt triggered when fault_event1 starts. + */ + uint32_t fault1_int_clr: 1; + /** fault2_int_clr : WT; bitpos: [11]; default: 0; + * Set this bit to clear the interrupt triggered when fault_event2 starts. + */ + uint32_t fault2_int_clr: 1; + /** fault0_clr_int_clr : WT; bitpos: [12]; default: 0; + * Set this bit to clear the interrupt triggered when fault_event0 ends. + */ + uint32_t fault0_clr_int_clr: 1; + /** fault1_clr_int_clr : WT; bitpos: [13]; default: 0; + * Set this bit to clear the interrupt triggered when fault_event1 ends. + */ + uint32_t fault1_clr_int_clr: 1; + /** fault2_clr_int_clr : WT; bitpos: [14]; default: 0; + * Set this bit to clear the interrupt triggered when fault_event2 ends. + */ + uint32_t fault2_clr_int_clr: 1; + /** op0_tea_int_clr : WT; bitpos: [15]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM operator 0 TEA event + */ + uint32_t op0_tea_int_clr: 1; + /** op1_tea_int_clr : WT; bitpos: [16]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM operator 1 TEA event + */ + uint32_t op1_tea_int_clr: 1; + /** op2_tea_int_clr : WT; bitpos: [17]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM operator 2 TEA event + */ + uint32_t op2_tea_int_clr: 1; + /** op0_teb_int_clr : WT; bitpos: [18]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM operator 0 TEB event + */ + uint32_t op0_teb_int_clr: 1; + /** op1_teb_int_clr : WT; bitpos: [19]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM operator 1 TEB event + */ + uint32_t op1_teb_int_clr: 1; + /** op2_teb_int_clr : WT; bitpos: [20]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM operator 2 TEB event + */ + uint32_t op2_teb_int_clr: 1; + /** fh0_cbc_int_clr : WT; bitpos: [21]; default: 0; + * Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on + * PWM0. + */ + uint32_t fh0_cbc_int_clr: 1; + /** fh1_cbc_int_clr : WT; bitpos: [22]; default: 0; + * Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on + * PWM1. + */ + uint32_t fh1_cbc_int_clr: 1; + /** fh2_cbc_int_clr : WT; bitpos: [23]; default: 0; + * Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on + * PWM2. + */ + uint32_t fh2_cbc_int_clr: 1; + /** fh0_ost_int_clr : WT; bitpos: [24]; default: 0; + * Set this bit to clear the interrupt triggered by a one-shot mode action on PWM0. + */ + uint32_t fh0_ost_int_clr: 1; + /** fh1_ost_int_clr : WT; bitpos: [25]; default: 0; + * Set this bit to clear the interrupt triggered by a one-shot mode action on PWM1. + */ + uint32_t fh1_ost_int_clr: 1; + /** fh2_ost_int_clr : WT; bitpos: [26]; default: 0; + * Set this bit to clear the interrupt triggered by a one-shot mode action on PWM2. + */ + uint32_t fh2_ost_int_clr: 1; + /** cap0_int_clr : WT; bitpos: [27]; default: 0; + * Set this bit to clear the interrupt triggered by capture on channel 0. + */ + uint32_t cap0_int_clr: 1; + /** cap1_int_clr : WT; bitpos: [28]; default: 0; + * Set this bit to clear the interrupt triggered by capture on channel 1. + */ + uint32_t cap1_int_clr: 1; + /** cap2_int_clr : WT; bitpos: [29]; default: 0; + * Set this bit to clear the interrupt triggered by capture on channel 2. + */ + uint32_t cap2_int_clr: 1; + uint32_t reserved_30: 2; + }; + uint32_t val; +} mcpwm_int_clr_reg_t; + + +/** Group: MCMCPWM APB configuration register */ +/** Type of clk register + * MCPWM APB configuration register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 0; + * Force clock on for this register file + */ + uint32_t clk_en: 1; + uint32_t reserved_1: 31; + }; + uint32_t val; +} mcpwm_clk_reg_t; + + +/** Group: Version Register */ +/** Type of version register + * Version register. + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 34632240; + * Version of this register file + */ + uint32_t date: 28; + uint32_t reserved_28: 4; + }; + uint32_t val; +} mcpwm_version_reg_t; + + +typedef struct { + mcpwm_timer_cfg0_reg_t timer_cfg0; + mcpwm_timer_cfg1_reg_t timer_cfg1; + mcpwm_timer_sync_reg_t timer_sync; + mcpwm_timer_status_reg_t timer_status; +} mcpwm_timer_regs_t; + +typedef struct { + mcpwm_gen_stmp_cfg_reg_t gen_stmp_cfg; + mcpwm_gen_tstmp_reg_t timestamp[2]; + mcpwm_gen_cfg0_reg_t gen_cfg0; + mcpwm_gen_force_reg_t gen_force; + mcpwm_gen_reg_t generator[2]; + mcpwm_dt_cfg_reg_t dt_cfg; + mcpwm_dt_fed_cfg_reg_t dt_fed_cfg; + mcpwm_dt_red_cfg_reg_t dt_red_cfg; + mcpwm_carrier_cfg_reg_t carrier_cfg; + mcpwm_fh_cfg0_reg_t fh_cfg0; + mcpwm_fh_cfg1_reg_t fh_cfg1; + mcpwm_fh_status_reg_t fh_status; +} mcpwm_operator_reg_t; + +typedef struct { + volatile mcpwm_clk_cfg_reg_t clk_cfg; + volatile mcpwm_timer_regs_t timer[3]; + volatile mcpwm_timer_synci_cfg_reg_t timer_synci_cfg; + volatile mcpwm_operator_timersel_reg_t operator_timersel; + volatile mcpwm_operator_reg_t operator[3]; + volatile mcpwm_fault_detect_reg_t fault_detect; + volatile mcpwm_cap_timer_cfg_reg_t cap_timer_cfg; + volatile mcpwm_cap_timer_phase_reg_t cap_timer_phase; + volatile mcpwm_cap_chn_cfg_reg_t cap_chn_cfg[3]; + volatile mcpwm_cap_chn_reg_t cap_chn[3]; + volatile mcpwm_cap_status_reg_t cap_status; + volatile mcpwm_update_cfg_reg_t update_cfg; + volatile mcpwm_int_ena_reg_t int_ena; + volatile mcpwm_int_raw_reg_t int_raw; + volatile mcpwm_int_st_reg_t int_st; + volatile mcpwm_int_clr_reg_t int_clr; + volatile mcpwm_clk_reg_t clk; + volatile mcpwm_version_reg_t version; } mcpwm_dev_t; extern mcpwm_dev_t MCPWM0; extern mcpwm_dev_t MCPWM1; +#ifndef __cplusplus +_Static_assert(sizeof(mcpwm_dev_t) == 0x128, "Invalid size of mcpwm_dev_t structure"); +#endif + #ifdef __cplusplus } #endif diff --git a/components/soc/esp32s3/include/soc/mcpwm_reg.h b/components/soc/esp32s3/include/soc/mcpwm_reg.h index 5ca6eadd7fc..6a370aa6910 100644 --- a/components/soc/esp32s3/include/soc/mcpwm_reg.h +++ b/components/soc/esp32s3/include/soc/mcpwm_reg.h @@ -1,2910 +1,3829 @@ -// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -#ifndef _SOC_MCPWM_REG_H_ -#define _SOC_MCPWM_REG_H_ - - -#include "soc.h" +/** + * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" #ifdef __cplusplus extern "C" { #endif -#define REG_MCPWM_BASE(i) (DR_REG_PWM0_BASE + i * (0xE000)) - -#define MCPWM_CLK_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x0) -/* MCPWM_CLK_PRESCALE : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ -/*description: .*/ -#define MCPWM_CLK_PRESCALE 0x000000FF -#define MCPWM_CLK_PRESCALE_M ((MCPWM_CLK_PRESCALE_V)<<(MCPWM_CLK_PRESCALE_S)) -#define MCPWM_CLK_PRESCALE_V 0xFF +#define DR_REG_MCPWM_BASE(i) (DR_REG_PWM0_BASE + i * (0xE000)) + +/** MCPWM_CLK_CFG_REG register + * PWM clock prescaler register. + */ +#define MCPWM_CLK_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0x0) +/** MCPWM_CLK_PRESCALE : R/W; bitpos: [7:0]; default: 0; + * Period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1) + */ +#define MCPWM_CLK_PRESCALE 0x000000FFU +#define MCPWM_CLK_PRESCALE_M (MCPWM_CLK_PRESCALE_V << MCPWM_CLK_PRESCALE_S) +#define MCPWM_CLK_PRESCALE_V 0x000000FFU #define MCPWM_CLK_PRESCALE_S 0 -#define MCPWM_TIMER0_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x4) -/* MCPWM_TIMER0_PERIOD_UPMETHOD : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ -/*description: 0: immediate, 1: eqz, 2: sync, 3: eqz | sync.*/ -#define MCPWM_TIMER0_PERIOD_UPMETHOD 0x00000003 -#define MCPWM_TIMER0_PERIOD_UPMETHOD_M ((MCPWM_TIMER0_PERIOD_UPMETHOD_V)<<(MCPWM_TIMER0_PERIOD_UPMETHOD_S)) -#define MCPWM_TIMER0_PERIOD_UPMETHOD_V 0x3 -#define MCPWM_TIMER0_PERIOD_UPMETHOD_S 24 -/* MCPWM_TIMER0_PERIOD : R/W ;bitpos:[23:8] ;default: 16'h00ff ; */ -/*description: .*/ -#define MCPWM_TIMER0_PERIOD 0x0000FFFF -#define MCPWM_TIMER0_PERIOD_M ((MCPWM_TIMER0_PERIOD_V)<<(MCPWM_TIMER0_PERIOD_S)) -#define MCPWM_TIMER0_PERIOD_V 0xFFFF -#define MCPWM_TIMER0_PERIOD_S 8 -/* MCPWM_TIMER0_PRESCALE : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ -/*description: .*/ -#define MCPWM_TIMER0_PRESCALE 0x000000FF -#define MCPWM_TIMER0_PRESCALE_M ((MCPWM_TIMER0_PRESCALE_V)<<(MCPWM_TIMER0_PRESCALE_S)) -#define MCPWM_TIMER0_PRESCALE_V 0xFF +/** MCPWM_TIMER0_CFG0_REG register + * PWM timer0 period and update method configuration register. + */ +#define MCPWM_TIMER0_CFG0_REG(i) (DR_REG_MCPWM_BASE(i) + 0x4) +/** MCPWM_TIMER0_PRESCALE : R/W; bitpos: [7:0]; default: 0; + * Configure the divisor of PT0_clk, takes effect when PWM timer0 stops and starts + * agsin. period of PT0_clk = Period of PWM_clk * (PWM_TIMER0_PRESCALE + 1) + */ +#define MCPWM_TIMER0_PRESCALE 0x000000FFU +#define MCPWM_TIMER0_PRESCALE_M (MCPWM_TIMER0_PRESCALE_V << MCPWM_TIMER0_PRESCALE_S) +#define MCPWM_TIMER0_PRESCALE_V 0x000000FFU #define MCPWM_TIMER0_PRESCALE_S 0 +/** MCPWM_TIMER0_PERIOD : R/W; bitpos: [23:8]; default: 255; + * period shadow register of PWM timer0 + */ +#define MCPWM_TIMER0_PERIOD 0x0000FFFFU +#define MCPWM_TIMER0_PERIOD_M (MCPWM_TIMER0_PERIOD_V << MCPWM_TIMER0_PERIOD_S) +#define MCPWM_TIMER0_PERIOD_V 0x0000FFFFU +#define MCPWM_TIMER0_PERIOD_S 8 +/** MCPWM_TIMER0_PERIOD_UPMETHOD : R/W; bitpos: [25:24]; default: 0; + * Update method for active register of PWM timer0 period, 0: immediate, 1: TEZ, 2: + * sync, 3: TEZ or sync. TEZ here and below means timer equal zero event + */ +#define MCPWM_TIMER0_PERIOD_UPMETHOD 0x00000003U +#define MCPWM_TIMER0_PERIOD_UPMETHOD_M (MCPWM_TIMER0_PERIOD_UPMETHOD_V << MCPWM_TIMER0_PERIOD_UPMETHOD_S) +#define MCPWM_TIMER0_PERIOD_UPMETHOD_V 0x00000003U +#define MCPWM_TIMER0_PERIOD_UPMETHOD_S 24 -#define MCPWM_TIMER0_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0x8) -/* MCPWM_TIMER0_MOD : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: 0: freeze, 1: inc, 2: dec, 3: up-down.*/ -#define MCPWM_TIMER0_MOD 0x00000003 -#define MCPWM_TIMER0_MOD_M ((MCPWM_TIMER0_MOD_V)<<(MCPWM_TIMER0_MOD_S)) -#define MCPWM_TIMER0_MOD_V 0x3 -#define MCPWM_TIMER0_MOD_S 3 -/* MCPWM_TIMER0_START : R/W ;bitpos:[2:0] ;default: 3'h0 ; */ -/*description: 0: stop @ eqz, 1: stop @ eqp, 2: free run, 3: start and stop @ next eqz, 4: star -t and stop @ next eqp,.*/ -#define MCPWM_TIMER0_START 0x00000007 -#define MCPWM_TIMER0_START_M ((MCPWM_TIMER0_START_V)<<(MCPWM_TIMER0_START_S)) -#define MCPWM_TIMER0_START_V 0x7 +/** MCPWM_TIMER0_CFG1_REG register + * PWM timer0 working mode and start/stop control configuration register. + */ +#define MCPWM_TIMER0_CFG1_REG(i) (DR_REG_MCPWM_BASE(i) + 0x8) +/** MCPWM_TIMER0_START : R/W/SC; bitpos: [2:0]; default: 0; + * PWM timer0 start and stop control. 0: if PWM timer0 starts, then stops at TEZ, 1: + * if timer0 starts, then stops at TEP, 2: PWM timer0 starts and runs on, 3: timer0 + * starts and stops at the next TEZ, 4: timer0 starts and stops at the next TEP. TEP + * here and below means the event that happens when the timer equals to period + */ +#define MCPWM_TIMER0_START 0x00000007U +#define MCPWM_TIMER0_START_M (MCPWM_TIMER0_START_V << MCPWM_TIMER0_START_S) +#define MCPWM_TIMER0_START_V 0x00000007U #define MCPWM_TIMER0_START_S 0 +/** MCPWM_TIMER0_MOD : R/W; bitpos: [4:3]; default: 0; + * PWM timer0 working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down + * mode + */ +#define MCPWM_TIMER0_MOD 0x00000003U +#define MCPWM_TIMER0_MOD_M (MCPWM_TIMER0_MOD_V << MCPWM_TIMER0_MOD_S) +#define MCPWM_TIMER0_MOD_V 0x00000003U +#define MCPWM_TIMER0_MOD_S 3 -#define MCPWM_TIMER0_SYNC_REG(i) (REG_MCPWM_BASE(i) + 0xC) -/* MCPWM_TIMER0_PHASE : R/W ;bitpos:[20:4] ;default: 17'd0 ; */ -/*description: .*/ -#define MCPWM_TIMER0_PHASE 0x0001FFFF -#define MCPWM_TIMER0_PHASE_M ((MCPWM_TIMER0_PHASE_V)<<(MCPWM_TIMER0_PHASE_S)) -#define MCPWM_TIMER0_PHASE_V 0x1FFFF -#define MCPWM_TIMER0_PHASE_S 4 -/* MCPWM_TIMER0_SYNCO_SEL : R/W ;bitpos:[3:2] ;default: 2'd0 ; */ -/*description: .*/ -#define MCPWM_TIMER0_SYNCO_SEL 0x00000003 -#define MCPWM_TIMER0_SYNCO_SEL_M ((MCPWM_TIMER0_SYNCO_SEL_V)<<(MCPWM_TIMER0_SYNCO_SEL_S)) -#define MCPWM_TIMER0_SYNCO_SEL_V 0x3 -#define MCPWM_TIMER0_SYNCO_SEL_S 2 -/* MCPWM_TIMER0_SYNC_SW : R/W ;bitpos:[1] ;default: 1'h0 ; */ -/*description: write the negate value will trigger a sw sync.*/ -#define MCPWM_TIMER0_SYNC_SW (BIT(1)) -#define MCPWM_TIMER0_SYNC_SW_M (BIT(1)) -#define MCPWM_TIMER0_SYNC_SW_V 0x1 -#define MCPWM_TIMER0_SYNC_SW_S 1 -/* MCPWM_TIMER0_SYNCI_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: .*/ +/** MCPWM_TIMER0_SYNC_REG register + * PWM timer0 sync function configuration register. + */ +#define MCPWM_TIMER0_SYNC_REG(i) (DR_REG_MCPWM_BASE(i) + 0xc) +/** MCPWM_TIMER0_SYNCI_EN : R/W; bitpos: [0]; default: 0; + * When set, timer reloading with phase on sync input event is enabled. + */ #define MCPWM_TIMER0_SYNCI_EN (BIT(0)) -#define MCPWM_TIMER0_SYNCI_EN_M (BIT(0)) -#define MCPWM_TIMER0_SYNCI_EN_V 0x1 +#define MCPWM_TIMER0_SYNCI_EN_M (MCPWM_TIMER0_SYNCI_EN_V << MCPWM_TIMER0_SYNCI_EN_S) +#define MCPWM_TIMER0_SYNCI_EN_V 0x00000001U #define MCPWM_TIMER0_SYNCI_EN_S 0 - -#define MCPWM_TIMER0_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x10) -/* MCPWM_TIMER0_DIRECTION : RO ;bitpos:[16] ;default: 1'd0 ; */ -/*description: .*/ +/** MCPWM_TIMER0_SYNC_SW : R/W; bitpos: [1]; default: 0; + * Toggling this bit will trigger a software sync. + */ +#define MCPWM_TIMER0_SYNC_SW (BIT(1)) +#define MCPWM_TIMER0_SYNC_SW_M (MCPWM_TIMER0_SYNC_SW_V << MCPWM_TIMER0_SYNC_SW_S) +#define MCPWM_TIMER0_SYNC_SW_V 0x00000001U +#define MCPWM_TIMER0_SYNC_SW_S 1 +/** MCPWM_TIMER0_SYNCO_SEL : R/W; bitpos: [3:2]; default: 0; + * PWM timer0 sync_out selection, 0: sync_in, 1: TEZ, 2: TEP, and sync out will always + * generate when toggling the reg_timer0_sync_sw bit + */ +#define MCPWM_TIMER0_SYNCO_SEL 0x00000003U +#define MCPWM_TIMER0_SYNCO_SEL_M (MCPWM_TIMER0_SYNCO_SEL_V << MCPWM_TIMER0_SYNCO_SEL_S) +#define MCPWM_TIMER0_SYNCO_SEL_V 0x00000003U +#define MCPWM_TIMER0_SYNCO_SEL_S 2 +/** MCPWM_TIMER0_PHASE : R/W; bitpos: [19:4]; default: 0; + * phase for timer reload on sync event + */ +#define MCPWM_TIMER0_PHASE 0x0000FFFFU +#define MCPWM_TIMER0_PHASE_M (MCPWM_TIMER0_PHASE_V << MCPWM_TIMER0_PHASE_S) +#define MCPWM_TIMER0_PHASE_V 0x0000FFFFU +#define MCPWM_TIMER0_PHASE_S 4 +/** MCPWM_TIMER0_PHASE_DIRECTION : R/W; bitpos: [20]; default: 0; + * Configure the PWM timer0's direction at the time sync event occurs when timer0 mode + * is up-down mode: 0-increase,1-decrease + */ +#define MCPWM_TIMER0_PHASE_DIRECTION (BIT(20)) +#define MCPWM_TIMER0_PHASE_DIRECTION_M (MCPWM_TIMER0_PHASE_DIRECTION_V << MCPWM_TIMER0_PHASE_DIRECTION_S) +#define MCPWM_TIMER0_PHASE_DIRECTION_V 0x00000001U +#define MCPWM_TIMER0_PHASE_DIRECTION_S 20 + +/** MCPWM_TIMER0_STATUS_REG register + * PWM timer0 status register. + */ +#define MCPWM_TIMER0_STATUS_REG(i) (DR_REG_MCPWM_BASE(i) + 0x10) +/** MCPWM_TIMER0_VALUE : RO; bitpos: [15:0]; default: 0; + * current PWM timer0 counter value + */ +#define MCPWM_TIMER0_VALUE 0x0000FFFFU +#define MCPWM_TIMER0_VALUE_M (MCPWM_TIMER0_VALUE_V << MCPWM_TIMER0_VALUE_S) +#define MCPWM_TIMER0_VALUE_V 0x0000FFFFU +#define MCPWM_TIMER0_VALUE_S 0 +/** MCPWM_TIMER0_DIRECTION : RO; bitpos: [16]; default: 0; + * current PWM timer0 counter direction, 0: increment 1: decrement + */ #define MCPWM_TIMER0_DIRECTION (BIT(16)) -#define MCPWM_TIMER0_DIRECTION_M (BIT(16)) -#define MCPWM_TIMER0_DIRECTION_V 0x1 +#define MCPWM_TIMER0_DIRECTION_M (MCPWM_TIMER0_DIRECTION_V << MCPWM_TIMER0_DIRECTION_S) +#define MCPWM_TIMER0_DIRECTION_V 0x00000001U #define MCPWM_TIMER0_DIRECTION_S 16 -/* MCPWM_TIMER0_VALUE : RO ;bitpos:[15:0] ;default: 16'd0 ; */ -/*description: .*/ -#define MCPWM_TIMER0_VALUE 0x0000FFFF -#define MCPWM_TIMER0_VALUE_M ((MCPWM_TIMER0_VALUE_V)<<(MCPWM_TIMER0_VALUE_S)) -#define MCPWM_TIMER0_VALUE_V 0xFFFF -#define MCPWM_TIMER0_VALUE_S 0 -#define MCPWM_TIMER1_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x14) -/* MCPWM_TIMER1_PERIOD_UPMETHOD : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ -/*description: .*/ -#define MCPWM_TIMER1_PERIOD_UPMETHOD 0x00000003 -#define MCPWM_TIMER1_PERIOD_UPMETHOD_M ((MCPWM_TIMER1_PERIOD_UPMETHOD_V)<<(MCPWM_TIMER1_PERIOD_UPMETHOD_S)) -#define MCPWM_TIMER1_PERIOD_UPMETHOD_V 0x3 -#define MCPWM_TIMER1_PERIOD_UPMETHOD_S 24 -/* MCPWM_TIMER1_PERIOD : R/W ;bitpos:[23:8] ;default: 16'h00ff ; */ -/*description: .*/ -#define MCPWM_TIMER1_PERIOD 0x0000FFFF -#define MCPWM_TIMER1_PERIOD_M ((MCPWM_TIMER1_PERIOD_V)<<(MCPWM_TIMER1_PERIOD_S)) -#define MCPWM_TIMER1_PERIOD_V 0xFFFF -#define MCPWM_TIMER1_PERIOD_S 8 -/* MCPWM_TIMER1_PRESCALE : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ -/*description: .*/ -#define MCPWM_TIMER1_PRESCALE 0x000000FF -#define MCPWM_TIMER1_PRESCALE_M ((MCPWM_TIMER1_PRESCALE_V)<<(MCPWM_TIMER1_PRESCALE_S)) -#define MCPWM_TIMER1_PRESCALE_V 0xFF +/** MCPWM_TIMER1_CFG0_REG register + * PWM timer1 period and update method configuration register. + */ +#define MCPWM_TIMER1_CFG0_REG(i) (DR_REG_MCPWM_BASE(i) + 0x14) +/** MCPWM_TIMER1_PRESCALE : R/W; bitpos: [7:0]; default: 0; + * Configure the divisor of PT1_clk, takes effect when PWM timer1 stops and starts + * agsin. period of PT1_clk = Period of PWM_clk * (PWM_TIMER1_PRESCALE + 1) + */ +#define MCPWM_TIMER1_PRESCALE 0x000000FFU +#define MCPWM_TIMER1_PRESCALE_M (MCPWM_TIMER1_PRESCALE_V << MCPWM_TIMER1_PRESCALE_S) +#define MCPWM_TIMER1_PRESCALE_V 0x000000FFU #define MCPWM_TIMER1_PRESCALE_S 0 +/** MCPWM_TIMER1_PERIOD : R/W; bitpos: [23:8]; default: 255; + * period shadow register of PWM timer1 + */ +#define MCPWM_TIMER1_PERIOD 0x0000FFFFU +#define MCPWM_TIMER1_PERIOD_M (MCPWM_TIMER1_PERIOD_V << MCPWM_TIMER1_PERIOD_S) +#define MCPWM_TIMER1_PERIOD_V 0x0000FFFFU +#define MCPWM_TIMER1_PERIOD_S 8 +/** MCPWM_TIMER1_PERIOD_UPMETHOD : R/W; bitpos: [25:24]; default: 0; + * Update method for active register of PWM timer1 period, 0: immediate, 1: TEZ, 2: + * sync, 3: TEZ | sync. TEZ here and below means timer equal zero event + */ +#define MCPWM_TIMER1_PERIOD_UPMETHOD 0x00000003U +#define MCPWM_TIMER1_PERIOD_UPMETHOD_M (MCPWM_TIMER1_PERIOD_UPMETHOD_V << MCPWM_TIMER1_PERIOD_UPMETHOD_S) +#define MCPWM_TIMER1_PERIOD_UPMETHOD_V 0x00000003U +#define MCPWM_TIMER1_PERIOD_UPMETHOD_S 24 -#define MCPWM_TIMER1_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0x18) -/* MCPWM_TIMER1_MOD : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: 0: freeze, 1: inc, 2: dec, 3: up-down.*/ -#define MCPWM_TIMER1_MOD 0x00000003 -#define MCPWM_TIMER1_MOD_M ((MCPWM_TIMER1_MOD_V)<<(MCPWM_TIMER1_MOD_S)) -#define MCPWM_TIMER1_MOD_V 0x3 -#define MCPWM_TIMER1_MOD_S 3 -/* MCPWM_TIMER1_START : R/W ;bitpos:[2:0] ;default: 3'h0 ; */ -/*description: .*/ -#define MCPWM_TIMER1_START 0x00000007 -#define MCPWM_TIMER1_START_M ((MCPWM_TIMER1_START_V)<<(MCPWM_TIMER1_START_S)) -#define MCPWM_TIMER1_START_V 0x7 +/** MCPWM_TIMER1_CFG1_REG register + * PWM timer1 working mode and start/stop control configuration register. + */ +#define MCPWM_TIMER1_CFG1_REG(i) (DR_REG_MCPWM_BASE(i) + 0x18) +/** MCPWM_TIMER1_START : R/W/SC; bitpos: [2:0]; default: 0; + * PWM timer1 start and stop control. 0: if PWM timer1 starts, then stops at TEZ, 1: + * if timer1 starts, then stops at TEP, 2: PWM timer1 starts and runs on, 3: timer1 + * starts and stops at the next TEZ, 4: timer1 starts and stops at the next TEP. TEP + * here and below means the event that happens when the timer equals to period + */ +#define MCPWM_TIMER1_START 0x00000007U +#define MCPWM_TIMER1_START_M (MCPWM_TIMER1_START_V << MCPWM_TIMER1_START_S) +#define MCPWM_TIMER1_START_V 0x00000007U #define MCPWM_TIMER1_START_S 0 +/** MCPWM_TIMER1_MOD : R/W; bitpos: [4:3]; default: 0; + * PWM timer1 working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down + * mode + */ +#define MCPWM_TIMER1_MOD 0x00000003U +#define MCPWM_TIMER1_MOD_M (MCPWM_TIMER1_MOD_V << MCPWM_TIMER1_MOD_S) +#define MCPWM_TIMER1_MOD_V 0x00000003U +#define MCPWM_TIMER1_MOD_S 3 -#define MCPWM_TIMER1_SYNC_REG(i) (REG_MCPWM_BASE(i) + 0x1C) -/* MCPWM_TIMER1_PHASE : R/W ;bitpos:[20:4] ;default: 17'd0 ; */ -/*description: .*/ -#define MCPWM_TIMER1_PHASE 0x0001FFFF -#define MCPWM_TIMER1_PHASE_M ((MCPWM_TIMER1_PHASE_V)<<(MCPWM_TIMER1_PHASE_S)) -#define MCPWM_TIMER1_PHASE_V 0x1FFFF -#define MCPWM_TIMER1_PHASE_S 4 -/* MCPWM_TIMER1_SYNCO_SEL : R/W ;bitpos:[3:2] ;default: 2'd0 ; */ -/*description: 0: synci, 1: tez, 2: tep, else 0.*/ -#define MCPWM_TIMER1_SYNCO_SEL 0x00000003 -#define MCPWM_TIMER1_SYNCO_SEL_M ((MCPWM_TIMER1_SYNCO_SEL_V)<<(MCPWM_TIMER1_SYNCO_SEL_S)) -#define MCPWM_TIMER1_SYNCO_SEL_V 0x3 -#define MCPWM_TIMER1_SYNCO_SEL_S 2 -/* MCPWM_TIMER1_SYNC_SW : R/W ;bitpos:[1] ;default: 1'h0 ; */ -/*description: write the negate value will trigger a sw sync.*/ -#define MCPWM_TIMER1_SYNC_SW (BIT(1)) -#define MCPWM_TIMER1_SYNC_SW_M (BIT(1)) -#define MCPWM_TIMER1_SYNC_SW_V 0x1 -#define MCPWM_TIMER1_SYNC_SW_S 1 -/* MCPWM_TIMER1_SYNCI_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: .*/ +/** MCPWM_TIMER1_SYNC_REG register + * PWM timer1 sync function configuration register. + */ +#define MCPWM_TIMER1_SYNC_REG(i) (DR_REG_MCPWM_BASE(i) + 0x1c) +/** MCPWM_TIMER1_SYNCI_EN : R/W; bitpos: [0]; default: 0; + * When set, timer reloading with phase on sync input event is enabled. + */ #define MCPWM_TIMER1_SYNCI_EN (BIT(0)) -#define MCPWM_TIMER1_SYNCI_EN_M (BIT(0)) -#define MCPWM_TIMER1_SYNCI_EN_V 0x1 +#define MCPWM_TIMER1_SYNCI_EN_M (MCPWM_TIMER1_SYNCI_EN_V << MCPWM_TIMER1_SYNCI_EN_S) +#define MCPWM_TIMER1_SYNCI_EN_V 0x00000001U #define MCPWM_TIMER1_SYNCI_EN_S 0 - -#define MCPWM_TIMER1_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x20) -/* MCPWM_TIMER1_DIRECTION : RO ;bitpos:[16] ;default: 1'd0 ; */ -/*description: .*/ +/** MCPWM_TIMER1_SYNC_SW : R/W; bitpos: [1]; default: 0; + * Toggling this bit will trigger a software sync. + */ +#define MCPWM_TIMER1_SYNC_SW (BIT(1)) +#define MCPWM_TIMER1_SYNC_SW_M (MCPWM_TIMER1_SYNC_SW_V << MCPWM_TIMER1_SYNC_SW_S) +#define MCPWM_TIMER1_SYNC_SW_V 0x00000001U +#define MCPWM_TIMER1_SYNC_SW_S 1 +/** MCPWM_TIMER1_SYNCO_SEL : R/W; bitpos: [3:2]; default: 0; + * PWM timer1 sync_out selection, 0: sync_in, 1: TEZ, 2: TEP, and sync out will always + * generate when toggling the reg_timer1_sync_sw bit + */ +#define MCPWM_TIMER1_SYNCO_SEL 0x00000003U +#define MCPWM_TIMER1_SYNCO_SEL_M (MCPWM_TIMER1_SYNCO_SEL_V << MCPWM_TIMER1_SYNCO_SEL_S) +#define MCPWM_TIMER1_SYNCO_SEL_V 0x00000003U +#define MCPWM_TIMER1_SYNCO_SEL_S 2 +/** MCPWM_TIMER1_PHASE : R/W; bitpos: [19:4]; default: 0; + * phase for timer reload on sync event + */ +#define MCPWM_TIMER1_PHASE 0x0000FFFFU +#define MCPWM_TIMER1_PHASE_M (MCPWM_TIMER1_PHASE_V << MCPWM_TIMER1_PHASE_S) +#define MCPWM_TIMER1_PHASE_V 0x0000FFFFU +#define MCPWM_TIMER1_PHASE_S 4 +/** MCPWM_TIMER1_PHASE_DIRECTION : R/W; bitpos: [20]; default: 0; + * Configure the PWM timer1's direction at the time sync event occurs when timer1 mode + * is up-down mode: 0-increase,1-decrease + */ +#define MCPWM_TIMER1_PHASE_DIRECTION (BIT(20)) +#define MCPWM_TIMER1_PHASE_DIRECTION_M (MCPWM_TIMER1_PHASE_DIRECTION_V << MCPWM_TIMER1_PHASE_DIRECTION_S) +#define MCPWM_TIMER1_PHASE_DIRECTION_V 0x00000001U +#define MCPWM_TIMER1_PHASE_DIRECTION_S 20 + +/** MCPWM_TIMER1_STATUS_REG register + * PWM timer1 status register. + */ +#define MCPWM_TIMER1_STATUS_REG(i) (DR_REG_MCPWM_BASE(i) + 0x20) +/** MCPWM_TIMER1_VALUE : RO; bitpos: [15:0]; default: 0; + * current PWM timer1 counter value + */ +#define MCPWM_TIMER1_VALUE 0x0000FFFFU +#define MCPWM_TIMER1_VALUE_M (MCPWM_TIMER1_VALUE_V << MCPWM_TIMER1_VALUE_S) +#define MCPWM_TIMER1_VALUE_V 0x0000FFFFU +#define MCPWM_TIMER1_VALUE_S 0 +/** MCPWM_TIMER1_DIRECTION : RO; bitpos: [16]; default: 0; + * current PWM timer1 counter direction, 0: increment 1: decrement + */ #define MCPWM_TIMER1_DIRECTION (BIT(16)) -#define MCPWM_TIMER1_DIRECTION_M (BIT(16)) -#define MCPWM_TIMER1_DIRECTION_V 0x1 +#define MCPWM_TIMER1_DIRECTION_M (MCPWM_TIMER1_DIRECTION_V << MCPWM_TIMER1_DIRECTION_S) +#define MCPWM_TIMER1_DIRECTION_V 0x00000001U #define MCPWM_TIMER1_DIRECTION_S 16 -/* MCPWM_TIMER1_VALUE : RO ;bitpos:[15:0] ;default: 16'd0 ; */ -/*description: .*/ -#define MCPWM_TIMER1_VALUE 0x0000FFFF -#define MCPWM_TIMER1_VALUE_M ((MCPWM_TIMER1_VALUE_V)<<(MCPWM_TIMER1_VALUE_S)) -#define MCPWM_TIMER1_VALUE_V 0xFFFF -#define MCPWM_TIMER1_VALUE_S 0 -#define MCPWM_TIMER2_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x24) -/* MCPWM_TIMER2_PERIOD_UPMETHOD : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ -/*description: .*/ -#define MCPWM_TIMER2_PERIOD_UPMETHOD 0x00000003 -#define MCPWM_TIMER2_PERIOD_UPMETHOD_M ((MCPWM_TIMER2_PERIOD_UPMETHOD_V)<<(MCPWM_TIMER2_PERIOD_UPMETHOD_S)) -#define MCPWM_TIMER2_PERIOD_UPMETHOD_V 0x3 -#define MCPWM_TIMER2_PERIOD_UPMETHOD_S 24 -/* MCPWM_TIMER2_PERIOD : R/W ;bitpos:[23:8] ;default: 16'h00ff ; */ -/*description: .*/ -#define MCPWM_TIMER2_PERIOD 0x0000FFFF -#define MCPWM_TIMER2_PERIOD_M ((MCPWM_TIMER2_PERIOD_V)<<(MCPWM_TIMER2_PERIOD_S)) -#define MCPWM_TIMER2_PERIOD_V 0xFFFF -#define MCPWM_TIMER2_PERIOD_S 8 -/* MCPWM_TIMER2_PRESCALE : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ -/*description: .*/ -#define MCPWM_TIMER2_PRESCALE 0x000000FF -#define MCPWM_TIMER2_PRESCALE_M ((MCPWM_TIMER2_PRESCALE_V)<<(MCPWM_TIMER2_PRESCALE_S)) -#define MCPWM_TIMER2_PRESCALE_V 0xFF +/** MCPWM_TIMER2_CFG0_REG register + * PWM timer2 period and update method configuration register. + */ +#define MCPWM_TIMER2_CFG0_REG(i) (DR_REG_MCPWM_BASE(i) + 0x24) +/** MCPWM_TIMER2_PRESCALE : R/W; bitpos: [7:0]; default: 0; + * Configure the divisor of PT2_clk, takes effect when PWM timer2 stops and starts + * agsin. period of PT2_clk = Period of PWM_clk * (PWM_TIMER2_PRESCALE + 1) + */ +#define MCPWM_TIMER2_PRESCALE 0x000000FFU +#define MCPWM_TIMER2_PRESCALE_M (MCPWM_TIMER2_PRESCALE_V << MCPWM_TIMER2_PRESCALE_S) +#define MCPWM_TIMER2_PRESCALE_V 0x000000FFU #define MCPWM_TIMER2_PRESCALE_S 0 +/** MCPWM_TIMER2_PERIOD : R/W; bitpos: [23:8]; default: 255; + * period shadow register of PWM timer2 + */ +#define MCPWM_TIMER2_PERIOD 0x0000FFFFU +#define MCPWM_TIMER2_PERIOD_M (MCPWM_TIMER2_PERIOD_V << MCPWM_TIMER2_PERIOD_S) +#define MCPWM_TIMER2_PERIOD_V 0x0000FFFFU +#define MCPWM_TIMER2_PERIOD_S 8 +/** MCPWM_TIMER2_PERIOD_UPMETHOD : R/W; bitpos: [25:24]; default: 0; + * Update method for active register of PWM timer2 period, 0: immediate, 1: TEZ, 2: + * sync, 3: TEZ | sync. TEZ here and below means timer equal zero event + */ +#define MCPWM_TIMER2_PERIOD_UPMETHOD 0x00000003U +#define MCPWM_TIMER2_PERIOD_UPMETHOD_M (MCPWM_TIMER2_PERIOD_UPMETHOD_V << MCPWM_TIMER2_PERIOD_UPMETHOD_S) +#define MCPWM_TIMER2_PERIOD_UPMETHOD_V 0x00000003U +#define MCPWM_TIMER2_PERIOD_UPMETHOD_S 24 -#define MCPWM_TIMER2_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0x28) -/* MCPWM_TIMER2_MOD : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: .*/ -#define MCPWM_TIMER2_MOD 0x00000003 -#define MCPWM_TIMER2_MOD_M ((MCPWM_TIMER2_MOD_V)<<(MCPWM_TIMER2_MOD_S)) -#define MCPWM_TIMER2_MOD_V 0x3 -#define MCPWM_TIMER2_MOD_S 3 -/* MCPWM_TIMER2_START : R/W ;bitpos:[2:0] ;default: 3'h0 ; */ -/*description: .*/ -#define MCPWM_TIMER2_START 0x00000007 -#define MCPWM_TIMER2_START_M ((MCPWM_TIMER2_START_V)<<(MCPWM_TIMER2_START_S)) -#define MCPWM_TIMER2_START_V 0x7 +/** MCPWM_TIMER2_CFG1_REG register + * PWM timer2 working mode and start/stop control configuration register. + */ +#define MCPWM_TIMER2_CFG1_REG(i) (DR_REG_MCPWM_BASE(i) + 0x28) +/** MCPWM_TIMER2_START : R/W/SC; bitpos: [2:0]; default: 0; + * PWM timer2 start and stop control. 0: if PWM timer2 starts, then stops at TEZ, 1: + * if timer2 starts, then stops at TEP, 2: PWM timer2 starts and runs on, 3: timer2 + * starts and stops at the next TEZ, 4: timer2 starts and stops at the next TEP. TEP + * here and below means the event that happens when the timer equals to period + */ +#define MCPWM_TIMER2_START 0x00000007U +#define MCPWM_TIMER2_START_M (MCPWM_TIMER2_START_V << MCPWM_TIMER2_START_S) +#define MCPWM_TIMER2_START_V 0x00000007U #define MCPWM_TIMER2_START_S 0 +/** MCPWM_TIMER2_MOD : R/W; bitpos: [4:3]; default: 0; + * PWM timer2 working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down + * mode + */ +#define MCPWM_TIMER2_MOD 0x00000003U +#define MCPWM_TIMER2_MOD_M (MCPWM_TIMER2_MOD_V << MCPWM_TIMER2_MOD_S) +#define MCPWM_TIMER2_MOD_V 0x00000003U +#define MCPWM_TIMER2_MOD_S 3 -#define MCPWM_TIMER2_SYNC_REG(i) (REG_MCPWM_BASE(i) + 0x2C) -/* MCPWM_TIMER2_PHASE : R/W ;bitpos:[20:4] ;default: 17'd0 ; */ -/*description: .*/ -#define MCPWM_TIMER2_PHASE 0x0001FFFF -#define MCPWM_TIMER2_PHASE_M ((MCPWM_TIMER2_PHASE_V)<<(MCPWM_TIMER2_PHASE_S)) -#define MCPWM_TIMER2_PHASE_V 0x1FFFF -#define MCPWM_TIMER2_PHASE_S 4 -/* MCPWM_TIMER2_SYNCO_SEL : R/W ;bitpos:[3:2] ;default: 2'd0 ; */ -/*description: .*/ -#define MCPWM_TIMER2_SYNCO_SEL 0x00000003 -#define MCPWM_TIMER2_SYNCO_SEL_M ((MCPWM_TIMER2_SYNCO_SEL_V)<<(MCPWM_TIMER2_SYNCO_SEL_S)) -#define MCPWM_TIMER2_SYNCO_SEL_V 0x3 -#define MCPWM_TIMER2_SYNCO_SEL_S 2 -/* MCPWM_TIMER2_SYNC_SW : R/W ;bitpos:[1] ;default: 1'h0 ; */ -/*description: write the negate value will trigger a sw sync.*/ -#define MCPWM_TIMER2_SYNC_SW (BIT(1)) -#define MCPWM_TIMER2_SYNC_SW_M (BIT(1)) -#define MCPWM_TIMER2_SYNC_SW_V 0x1 -#define MCPWM_TIMER2_SYNC_SW_S 1 -/* MCPWM_TIMER2_SYNCI_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: .*/ +/** MCPWM_TIMER2_SYNC_REG register + * PWM timer2 sync function configuration register. + */ +#define MCPWM_TIMER2_SYNC_REG(i) (DR_REG_MCPWM_BASE(i) + 0x2c) +/** MCPWM_TIMER2_SYNCI_EN : R/W; bitpos: [0]; default: 0; + * When set, timer reloading with phase on sync input event is enabled. + */ #define MCPWM_TIMER2_SYNCI_EN (BIT(0)) -#define MCPWM_TIMER2_SYNCI_EN_M (BIT(0)) -#define MCPWM_TIMER2_SYNCI_EN_V 0x1 +#define MCPWM_TIMER2_SYNCI_EN_M (MCPWM_TIMER2_SYNCI_EN_V << MCPWM_TIMER2_SYNCI_EN_S) +#define MCPWM_TIMER2_SYNCI_EN_V 0x00000001U #define MCPWM_TIMER2_SYNCI_EN_S 0 - -#define MCPWM_TIMER2_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x30) -/* MCPWM_TIMER2_DIRECTION : RO ;bitpos:[16] ;default: 1'd0 ; */ -/*description: .*/ +/** MCPWM_TIMER2_SYNC_SW : R/W; bitpos: [1]; default: 0; + * Toggling this bit will trigger a software sync. + */ +#define MCPWM_TIMER2_SYNC_SW (BIT(1)) +#define MCPWM_TIMER2_SYNC_SW_M (MCPWM_TIMER2_SYNC_SW_V << MCPWM_TIMER2_SYNC_SW_S) +#define MCPWM_TIMER2_SYNC_SW_V 0x00000001U +#define MCPWM_TIMER2_SYNC_SW_S 1 +/** MCPWM_TIMER2_SYNCO_SEL : R/W; bitpos: [3:2]; default: 0; + * PWM timer2 sync_out selection, 0: sync_in, 1: TEZ, 2: TEP, and sync out will always + * generate when toggling the reg_timer0_sync_sw bit + */ +#define MCPWM_TIMER2_SYNCO_SEL 0x00000003U +#define MCPWM_TIMER2_SYNCO_SEL_M (MCPWM_TIMER2_SYNCO_SEL_V << MCPWM_TIMER2_SYNCO_SEL_S) +#define MCPWM_TIMER2_SYNCO_SEL_V 0x00000003U +#define MCPWM_TIMER2_SYNCO_SEL_S 2 +/** MCPWM_TIMER2_PHASE : R/W; bitpos: [19:4]; default: 0; + * phase for timer reload on sync event + */ +#define MCPWM_TIMER2_PHASE 0x0000FFFFU +#define MCPWM_TIMER2_PHASE_M (MCPWM_TIMER2_PHASE_V << MCPWM_TIMER2_PHASE_S) +#define MCPWM_TIMER2_PHASE_V 0x0000FFFFU +#define MCPWM_TIMER2_PHASE_S 4 +/** MCPWM_TIMER2_PHASE_DIRECTION : R/W; bitpos: [20]; default: 0; + * Configure the PWM timer2's direction at the time sync event occurs when timer2 mode + * is up-down mode: 0-increase,1-decrease + */ +#define MCPWM_TIMER2_PHASE_DIRECTION (BIT(20)) +#define MCPWM_TIMER2_PHASE_DIRECTION_M (MCPWM_TIMER2_PHASE_DIRECTION_V << MCPWM_TIMER2_PHASE_DIRECTION_S) +#define MCPWM_TIMER2_PHASE_DIRECTION_V 0x00000001U +#define MCPWM_TIMER2_PHASE_DIRECTION_S 20 + +/** MCPWM_TIMER2_STATUS_REG register + * PWM timer2 status register. + */ +#define MCPWM_TIMER2_STATUS_REG(i) (DR_REG_MCPWM_BASE(i) + 0x30) +/** MCPWM_TIMER2_VALUE : RO; bitpos: [15:0]; default: 0; + * current PWM timer2 counter value + */ +#define MCPWM_TIMER2_VALUE 0x0000FFFFU +#define MCPWM_TIMER2_VALUE_M (MCPWM_TIMER2_VALUE_V << MCPWM_TIMER2_VALUE_S) +#define MCPWM_TIMER2_VALUE_V 0x0000FFFFU +#define MCPWM_TIMER2_VALUE_S 0 +/** MCPWM_TIMER2_DIRECTION : RO; bitpos: [16]; default: 0; + * current PWM timer2 counter direction, 0: increment 1: decrement + */ #define MCPWM_TIMER2_DIRECTION (BIT(16)) -#define MCPWM_TIMER2_DIRECTION_M (BIT(16)) -#define MCPWM_TIMER2_DIRECTION_V 0x1 +#define MCPWM_TIMER2_DIRECTION_M (MCPWM_TIMER2_DIRECTION_V << MCPWM_TIMER2_DIRECTION_S) +#define MCPWM_TIMER2_DIRECTION_V 0x00000001U #define MCPWM_TIMER2_DIRECTION_S 16 -/* MCPWM_TIMER2_VALUE : RO ;bitpos:[15:0] ;default: 16'd0 ; */ -/*description: .*/ -#define MCPWM_TIMER2_VALUE 0x0000FFFF -#define MCPWM_TIMER2_VALUE_M ((MCPWM_TIMER2_VALUE_V)<<(MCPWM_TIMER2_VALUE_S)) -#define MCPWM_TIMER2_VALUE_V 0xFFFF -#define MCPWM_TIMER2_VALUE_S 0 -#define MCPWM_TIMER_SYNCI_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x34) -/* MCPWM_EXTERNAL_SYNCI2_INVERT : R/W ;bitpos:[11] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_EXTERNAL_SYNCI2_INVERT (BIT(11)) -#define MCPWM_EXTERNAL_SYNCI2_INVERT_M (BIT(11)) -#define MCPWM_EXTERNAL_SYNCI2_INVERT_V 0x1 -#define MCPWM_EXTERNAL_SYNCI2_INVERT_S 11 -/* MCPWM_EXTERNAL_SYNCI1_INVERT : R/W ;bitpos:[10] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_EXTERNAL_SYNCI1_INVERT (BIT(10)) -#define MCPWM_EXTERNAL_SYNCI1_INVERT_M (BIT(10)) -#define MCPWM_EXTERNAL_SYNCI1_INVERT_V 0x1 -#define MCPWM_EXTERNAL_SYNCI1_INVERT_S 10 -/* MCPWM_EXTERNAL_SYNCI0_INVERT : R/W ;bitpos:[9] ;default: 1'd0 ; */ -/*description: .*/ +/** MCPWM_TIMER_SYNCI_CFG_REG register + * Synchronization input selection for three PWM timers. + */ +#define MCPWM_TIMER_SYNCI_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0x34) +/** MCPWM_TIMER0_SYNCISEL : R/W; bitpos: [2:0]; default: 0; + * select sync input for PWM timer0, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, + * 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: + * SYNC2 from GPIO matrix, other values: no sync input selected + */ +#define MCPWM_TIMER0_SYNCISEL 0x00000007U +#define MCPWM_TIMER0_SYNCISEL_M (MCPWM_TIMER0_SYNCISEL_V << MCPWM_TIMER0_SYNCISEL_S) +#define MCPWM_TIMER0_SYNCISEL_V 0x00000007U +#define MCPWM_TIMER0_SYNCISEL_S 0 +/** MCPWM_TIMER1_SYNCISEL : R/W; bitpos: [5:3]; default: 0; + * select sync input for PWM timer1, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, + * 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: + * SYNC2 from GPIO matrix, other values: no sync input selected + */ +#define MCPWM_TIMER1_SYNCISEL 0x00000007U +#define MCPWM_TIMER1_SYNCISEL_M (MCPWM_TIMER1_SYNCISEL_V << MCPWM_TIMER1_SYNCISEL_S) +#define MCPWM_TIMER1_SYNCISEL_V 0x00000007U +#define MCPWM_TIMER1_SYNCISEL_S 3 +/** MCPWM_TIMER2_SYNCISEL : R/W; bitpos: [8:6]; default: 0; + * select sync input for PWM timer2, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, + * 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: + * SYNC2 from GPIO matrix, other values: no sync input selected + */ +#define MCPWM_TIMER2_SYNCISEL 0x00000007U +#define MCPWM_TIMER2_SYNCISEL_M (MCPWM_TIMER2_SYNCISEL_V << MCPWM_TIMER2_SYNCISEL_S) +#define MCPWM_TIMER2_SYNCISEL_V 0x00000007U +#define MCPWM_TIMER2_SYNCISEL_S 6 +/** MCPWM_EXTERNAL_SYNCI0_INVERT : R/W; bitpos: [9]; default: 0; + * invert SYNC0 from GPIO matrix + */ #define MCPWM_EXTERNAL_SYNCI0_INVERT (BIT(9)) -#define MCPWM_EXTERNAL_SYNCI0_INVERT_M (BIT(9)) -#define MCPWM_EXTERNAL_SYNCI0_INVERT_V 0x1 +#define MCPWM_EXTERNAL_SYNCI0_INVERT_M (MCPWM_EXTERNAL_SYNCI0_INVERT_V << MCPWM_EXTERNAL_SYNCI0_INVERT_S) +#define MCPWM_EXTERNAL_SYNCI0_INVERT_V 0x00000001U #define MCPWM_EXTERNAL_SYNCI0_INVERT_S 9 -/* MCPWM_TIMER2_SYNCISEL : R/W ;bitpos:[8:6] ;default: 3'd0 ; */ -/*description: .*/ -#define MCPWM_TIMER2_SYNCISEL 0x00000007 -#define MCPWM_TIMER2_SYNCISEL_M ((MCPWM_TIMER2_SYNCISEL_V)<<(MCPWM_TIMER2_SYNCISEL_S)) -#define MCPWM_TIMER2_SYNCISEL_V 0x7 -#define MCPWM_TIMER2_SYNCISEL_S 6 -/* MCPWM_TIMER1_SYNCISEL : R/W ;bitpos:[5:3] ;default: 3'd0 ; */ -/*description: .*/ -#define MCPWM_TIMER1_SYNCISEL 0x00000007 -#define MCPWM_TIMER1_SYNCISEL_M ((MCPWM_TIMER1_SYNCISEL_V)<<(MCPWM_TIMER1_SYNCISEL_S)) -#define MCPWM_TIMER1_SYNCISEL_V 0x7 -#define MCPWM_TIMER1_SYNCISEL_S 3 -/* MCPWM_TIMER0_SYNCISEL : R/W ;bitpos:[2:0] ;default: 3'd0 ; */ -/*description: .*/ -#define MCPWM_TIMER0_SYNCISEL 0x00000007 -#define MCPWM_TIMER0_SYNCISEL_M ((MCPWM_TIMER0_SYNCISEL_V)<<(MCPWM_TIMER0_SYNCISEL_S)) -#define MCPWM_TIMER0_SYNCISEL_V 0x7 -#define MCPWM_TIMER0_SYNCISEL_S 0 +/** MCPWM_EXTERNAL_SYNCI1_INVERT : R/W; bitpos: [10]; default: 0; + * invert SYNC1 from GPIO matrix + */ +#define MCPWM_EXTERNAL_SYNCI1_INVERT (BIT(10)) +#define MCPWM_EXTERNAL_SYNCI1_INVERT_M (MCPWM_EXTERNAL_SYNCI1_INVERT_V << MCPWM_EXTERNAL_SYNCI1_INVERT_S) +#define MCPWM_EXTERNAL_SYNCI1_INVERT_V 0x00000001U +#define MCPWM_EXTERNAL_SYNCI1_INVERT_S 10 +/** MCPWM_EXTERNAL_SYNCI2_INVERT : R/W; bitpos: [11]; default: 0; + * invert SYNC2 from GPIO matrix + */ +#define MCPWM_EXTERNAL_SYNCI2_INVERT (BIT(11)) +#define MCPWM_EXTERNAL_SYNCI2_INVERT_M (MCPWM_EXTERNAL_SYNCI2_INVERT_V << MCPWM_EXTERNAL_SYNCI2_INVERT_S) +#define MCPWM_EXTERNAL_SYNCI2_INVERT_V 0x00000001U +#define MCPWM_EXTERNAL_SYNCI2_INVERT_S 11 -#define MCPWM_OPERATOR_TIMERSEL_REG(i) (REG_MCPWM_BASE(i) + 0x38) -/* MCPWM_OPERATOR2_TIMERSEL : R/W ;bitpos:[5:4] ;default: 2'd0 ; */ -/*description: 0: timer0, 1: timer1, 2: timer2.*/ -#define MCPWM_OPERATOR2_TIMERSEL 0x00000003 -#define MCPWM_OPERATOR2_TIMERSEL_M ((MCPWM_OPERATOR2_TIMERSEL_V)<<(MCPWM_OPERATOR2_TIMERSEL_S)) -#define MCPWM_OPERATOR2_TIMERSEL_V 0x3 -#define MCPWM_OPERATOR2_TIMERSEL_S 4 -/* MCPWM_OPERATOR1_TIMERSEL : R/W ;bitpos:[3:2] ;default: 2'd0 ; */ -/*description: 0: timer0, 1: timer1, 2: timer2.*/ -#define MCPWM_OPERATOR1_TIMERSEL 0x00000003 -#define MCPWM_OPERATOR1_TIMERSEL_M ((MCPWM_OPERATOR1_TIMERSEL_V)<<(MCPWM_OPERATOR1_TIMERSEL_S)) -#define MCPWM_OPERATOR1_TIMERSEL_V 0x3 -#define MCPWM_OPERATOR1_TIMERSEL_S 2 -/* MCPWM_OPERATOR0_TIMERSEL : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: 0: timer0, 1: timer1, 2: timer2.*/ -#define MCPWM_OPERATOR0_TIMERSEL 0x00000003 -#define MCPWM_OPERATOR0_TIMERSEL_M ((MCPWM_OPERATOR0_TIMERSEL_V)<<(MCPWM_OPERATOR0_TIMERSEL_S)) -#define MCPWM_OPERATOR0_TIMERSEL_V 0x3 +/** MCPWM_OPERATOR_TIMERSEL_REG register + * Select specific timer for PWM operators. + */ +#define MCPWM_OPERATOR_TIMERSEL_REG(i) (DR_REG_MCPWM_BASE(i) + 0x38) +/** MCPWM_OPERATOR0_TIMERSEL : R/W; bitpos: [1:0]; default: 0; + * Select which PWM timer is the timing reference for PWM operator0, 0: timer0, 1: + * timer1, 2: timer2 + */ +#define MCPWM_OPERATOR0_TIMERSEL 0x00000003U +#define MCPWM_OPERATOR0_TIMERSEL_M (MCPWM_OPERATOR0_TIMERSEL_V << MCPWM_OPERATOR0_TIMERSEL_S) +#define MCPWM_OPERATOR0_TIMERSEL_V 0x00000003U #define MCPWM_OPERATOR0_TIMERSEL_S 0 +/** MCPWM_OPERATOR1_TIMERSEL : R/W; bitpos: [3:2]; default: 0; + * Select which PWM timer is the timing reference for PWM operator1, 0: timer0, 1: + * timer1, 2: timer2 + */ +#define MCPWM_OPERATOR1_TIMERSEL 0x00000003U +#define MCPWM_OPERATOR1_TIMERSEL_M (MCPWM_OPERATOR1_TIMERSEL_V << MCPWM_OPERATOR1_TIMERSEL_S) +#define MCPWM_OPERATOR1_TIMERSEL_V 0x00000003U +#define MCPWM_OPERATOR1_TIMERSEL_S 2 +/** MCPWM_OPERATOR2_TIMERSEL : R/W; bitpos: [5:4]; default: 0; + * Select which PWM timer is the timing reference for PWM operator2, 0: timer0, 1: + * timer1, 2: timer2 + */ +#define MCPWM_OPERATOR2_TIMERSEL 0x00000003U +#define MCPWM_OPERATOR2_TIMERSEL_M (MCPWM_OPERATOR2_TIMERSEL_V << MCPWM_OPERATOR2_TIMERSEL_S) +#define MCPWM_OPERATOR2_TIMERSEL_V 0x00000003U +#define MCPWM_OPERATOR2_TIMERSEL_S 4 -#define MCPWM_CMPR0_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x3C) -/* MCPWM_CMPR0_B_SHDW_FULL : R/W ;bitpos:[9] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_CMPR0_B_SHDW_FULL (BIT(9)) -#define MCPWM_CMPR0_B_SHDW_FULL_M (BIT(9)) -#define MCPWM_CMPR0_B_SHDW_FULL_V 0x1 -#define MCPWM_CMPR0_B_SHDW_FULL_S 9 -/* MCPWM_CMPR0_A_SHDW_FULL : R/W ;bitpos:[8] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_CMPR0_A_SHDW_FULL (BIT(8)) -#define MCPWM_CMPR0_A_SHDW_FULL_M (BIT(8)) -#define MCPWM_CMPR0_A_SHDW_FULL_V 0x1 -#define MCPWM_CMPR0_A_SHDW_FULL_S 8 -/* MCPWM_CMPR0_B_UPMETHOD : R/W ;bitpos:[7:4] ;default: 4'd0 ; */ -/*description: 0: immediate, bit0: tez, bit1: tep, bit2: sync, bit3: freeze.*/ -#define MCPWM_CMPR0_B_UPMETHOD 0x0000000F -#define MCPWM_CMPR0_B_UPMETHOD_M ((MCPWM_CMPR0_B_UPMETHOD_V)<<(MCPWM_CMPR0_B_UPMETHOD_S)) -#define MCPWM_CMPR0_B_UPMETHOD_V 0xF -#define MCPWM_CMPR0_B_UPMETHOD_S 4 -/* MCPWM_CMPR0_A_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: 0: immediate, bit0: tez, bit1: tep, bit2: sync, bit3: freeze.*/ -#define MCPWM_CMPR0_A_UPMETHOD 0x0000000F -#define MCPWM_CMPR0_A_UPMETHOD_M ((MCPWM_CMPR0_A_UPMETHOD_V)<<(MCPWM_CMPR0_A_UPMETHOD_S)) -#define MCPWM_CMPR0_A_UPMETHOD_V 0xF -#define MCPWM_CMPR0_A_UPMETHOD_S 0 - -#define MCPWM_CMPR0_VALUE0_REG(i) (REG_MCPWM_BASE(i) + 0x40) -/* MCPWM_CMPR0_A : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ -/*description: .*/ -#define MCPWM_CMPR0_A 0x0000FFFF -#define MCPWM_CMPR0_A_M ((MCPWM_CMPR0_A_V)<<(MCPWM_CMPR0_A_S)) -#define MCPWM_CMPR0_A_V 0xFFFF -#define MCPWM_CMPR0_A_S 0 - -#define MCPWM_CMPR0_VALUE1_REG(i) (REG_MCPWM_BASE(i) + 0x44) -/* MCPWM_CMPR0_B : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ -/*description: .*/ -#define MCPWM_CMPR0_B 0x0000FFFF -#define MCPWM_CMPR0_B_M ((MCPWM_CMPR0_B_V)<<(MCPWM_CMPR0_B_S)) -#define MCPWM_CMPR0_B_V 0xFFFF -#define MCPWM_CMPR0_B_S 0 - -#define MCPWM_GEN0_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x48) -/* MCPWM_GEN0_T1_SEL : R/W ;bitpos:[9:7] ;default: 3'd0 ; */ -/*description: take effect immediately, 0: extra0, 1: extra1, 2: extra2, 3: sync_taken, 4: none.*/ -#define MCPWM_GEN0_T1_SEL 0x00000007 -#define MCPWM_GEN0_T1_SEL_M ((MCPWM_GEN0_T1_SEL_V)<<(MCPWM_GEN0_T1_SEL_S)) -#define MCPWM_GEN0_T1_SEL_V 0x7 -#define MCPWM_GEN0_T1_SEL_S 7 -/* MCPWM_GEN0_T0_SEL : R/W ;bitpos:[6:4] ;default: 3'd0 ; */ -/*description: take effect immediately, 0: extra0, 1: extra1, 2: extra2, 3: sync_taken, 4: none.*/ -#define MCPWM_GEN0_T0_SEL 0x00000007 -#define MCPWM_GEN0_T0_SEL_M ((MCPWM_GEN0_T0_SEL_V)<<(MCPWM_GEN0_T0_SEL_S)) -#define MCPWM_GEN0_T0_SEL_V 0x7 -#define MCPWM_GEN0_T0_SEL_S 4 -/* MCPWM_GEN0_CFG_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: 0: immediate, bit0: tez, bit1: tep, bit2: sync. bit3: freeze.*/ -#define MCPWM_GEN0_CFG_UPMETHOD 0x0000000F -#define MCPWM_GEN0_CFG_UPMETHOD_M ((MCPWM_GEN0_CFG_UPMETHOD_V)<<(MCPWM_GEN0_CFG_UPMETHOD_S)) -#define MCPWM_GEN0_CFG_UPMETHOD_V 0xF +/** MCPWM_GEN0_STMP_CFG_REG register + * Transfer status and update method for time stamp registers A and B + */ +#define MCPWM_GEN0_STMP_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0x3c) +/** MCPWM_GEN0_A_UPMETHOD : R/W; bitpos: [3:0]; default: 0; + * Update method for PWM generator 0 time stamp A's active register. When all bits are + * set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when + * bit2 is set to 1: sync, when bit3 is set to 1: disable the update. + */ +#define MCPWM_GEN0_A_UPMETHOD 0x0000000FU +#define MCPWM_GEN0_A_UPMETHOD_M (MCPWM_GEN0_A_UPMETHOD_V << MCPWM_GEN0_A_UPMETHOD_S) +#define MCPWM_GEN0_A_UPMETHOD_V 0x0000000FU +#define MCPWM_GEN0_A_UPMETHOD_S 0 +/** MCPWM_GEN0_B_UPMETHOD : R/W; bitpos: [7:4]; default: 0; + * Update method for PWM generator 0 time stamp B's active register. When all bits are + * set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when + * bit2 is set to 1: sync, when bit3 is set to 1: disable the update. + */ +#define MCPWM_GEN0_B_UPMETHOD 0x0000000FU +#define MCPWM_GEN0_B_UPMETHOD_M (MCPWM_GEN0_B_UPMETHOD_V << MCPWM_GEN0_B_UPMETHOD_S) +#define MCPWM_GEN0_B_UPMETHOD_V 0x0000000FU +#define MCPWM_GEN0_B_UPMETHOD_S 4 +/** MCPWM_GEN0_A_SHDW_FULL : R/W/WTC/SC; bitpos: [8]; default: 0; + * Set and reset by hardware. If set, PWM generator 0 time stamp A's shadow reg is + * filled and waiting to be transferred to A's active reg. If cleared, A's active reg + * has been updated with shadow register latest value + */ +#define MCPWM_GEN0_A_SHDW_FULL (BIT(8)) +#define MCPWM_GEN0_A_SHDW_FULL_M (MCPWM_GEN0_A_SHDW_FULL_V << MCPWM_GEN0_A_SHDW_FULL_S) +#define MCPWM_GEN0_A_SHDW_FULL_V 0x00000001U +#define MCPWM_GEN0_A_SHDW_FULL_S 8 +/** MCPWM_GEN0_B_SHDW_FULL : R/W/WTC/SC; bitpos: [9]; default: 0; + * Set and reset by hardware. If set, PWM generator 0 time stamp B's shadow reg is + * filled and waiting to be transferred to B's active reg. If cleared, B's active reg + * has been updated with shadow register latest value + */ +#define MCPWM_GEN0_B_SHDW_FULL (BIT(9)) +#define MCPWM_GEN0_B_SHDW_FULL_M (MCPWM_GEN0_B_SHDW_FULL_V << MCPWM_GEN0_B_SHDW_FULL_S) +#define MCPWM_GEN0_B_SHDW_FULL_V 0x00000001U +#define MCPWM_GEN0_B_SHDW_FULL_S 9 + +/** MCPWM_GEN0_TSTMP_A_REG register + * PWM generator 0 shadow register for timer stamp A. + */ +#define MCPWM_GEN0_TSTMP_A_REG(i) (DR_REG_MCPWM_BASE(i) + 0x40) +/** MCPWM_GEN0_A : R/W; bitpos: [15:0]; default: 0; + * PWM generator 0 time stamp A's shadow register + */ +#define MCPWM_GEN0_A 0x0000FFFFU +#define MCPWM_GEN0_A_M (MCPWM_GEN0_A_V << MCPWM_GEN0_A_S) +#define MCPWM_GEN0_A_V 0x0000FFFFU +#define MCPWM_GEN0_A_S 0 + +/** MCPWM_GEN0_TSTMP_B_REG register + * PWM generator 0 shadow register for timer stamp B. + */ +#define MCPWM_GEN0_TSTMP_B_REG(i) (DR_REG_MCPWM_BASE(i) + 0x44) +/** MCPWM_GEN0_B : R/W; bitpos: [15:0]; default: 0; + * PWM generator 0 time stamp B's shadow register + */ +#define MCPWM_GEN0_B 0x0000FFFFU +#define MCPWM_GEN0_B_M (MCPWM_GEN0_B_V << MCPWM_GEN0_B_S) +#define MCPWM_GEN0_B_V 0x0000FFFFU +#define MCPWM_GEN0_B_S 0 + +/** MCPWM_GEN0_CFG0_REG register + * PWM generator 0 event T0 and T1 handling + */ +#define MCPWM_GEN0_CFG0_REG(i) (DR_REG_MCPWM_BASE(i) + 0x48) +/** MCPWM_GEN0_CFG_UPMETHOD : R/W; bitpos: [3:0]; default: 0; + * Update method for PWM generator 0's active register of configuration. When all bits + * are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to + * 1:TEP,when bit2 is set to 1:sync,when bit3 is set to 1:disable the update + */ +#define MCPWM_GEN0_CFG_UPMETHOD 0x0000000FU +#define MCPWM_GEN0_CFG_UPMETHOD_M (MCPWM_GEN0_CFG_UPMETHOD_V << MCPWM_GEN0_CFG_UPMETHOD_S) +#define MCPWM_GEN0_CFG_UPMETHOD_V 0x0000000FU #define MCPWM_GEN0_CFG_UPMETHOD_S 0 +/** MCPWM_GEN0_T0_SEL : R/W; bitpos: [6:4]; default: 0; + * Source selection for PWM generator 0 event_t0, take effect immediately, 0: + * fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none + */ +#define MCPWM_GEN0_T0_SEL 0x00000007U +#define MCPWM_GEN0_T0_SEL_M (MCPWM_GEN0_T0_SEL_V << MCPWM_GEN0_T0_SEL_S) +#define MCPWM_GEN0_T0_SEL_V 0x00000007U +#define MCPWM_GEN0_T0_SEL_S 4 +/** MCPWM_GEN0_T1_SEL : R/W; bitpos: [9:7]; default: 0; + * Source selection for PWM generator 0 event_t1, take effect immediately, 0: + * fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none + */ +#define MCPWM_GEN0_T1_SEL 0x00000007U +#define MCPWM_GEN0_T1_SEL_M (MCPWM_GEN0_T1_SEL_V << MCPWM_GEN0_T1_SEL_S) +#define MCPWM_GEN0_T1_SEL_V 0x00000007U +#define MCPWM_GEN0_T1_SEL_S 7 -#define MCPWM_GEN0_FORCE_REG(i) (REG_MCPWM_BASE(i) + 0x4C) -/* MCPWM_GEN0_B_NCIFORCE_MODE : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ -/*description: 0: disabled, 1: low, 2: high, 3: disabled.*/ -#define MCPWM_GEN0_B_NCIFORCE_MODE 0x00000003 -#define MCPWM_GEN0_B_NCIFORCE_MODE_M ((MCPWM_GEN0_B_NCIFORCE_MODE_V)<<(MCPWM_GEN0_B_NCIFORCE_MODE_S)) -#define MCPWM_GEN0_B_NCIFORCE_MODE_V 0x3 -#define MCPWM_GEN0_B_NCIFORCE_MODE_S 14 -/* MCPWM_GEN0_B_NCIFORCE : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: non-continuous immediate sw force, a toggle will trigger a force event.*/ -#define MCPWM_GEN0_B_NCIFORCE (BIT(13)) -#define MCPWM_GEN0_B_NCIFORCE_M (BIT(13)) -#define MCPWM_GEN0_B_NCIFORCE_V 0x1 -#define MCPWM_GEN0_B_NCIFORCE_S 13 -/* MCPWM_GEN0_A_NCIFORCE_MODE : R/W ;bitpos:[12:11] ;default: 2'd0 ; */ -/*description: 0: disabled, 1: low, 2: high, 3: disabled.*/ -#define MCPWM_GEN0_A_NCIFORCE_MODE 0x00000003 -#define MCPWM_GEN0_A_NCIFORCE_MODE_M ((MCPWM_GEN0_A_NCIFORCE_MODE_V)<<(MCPWM_GEN0_A_NCIFORCE_MODE_S)) -#define MCPWM_GEN0_A_NCIFORCE_MODE_V 0x3 -#define MCPWM_GEN0_A_NCIFORCE_MODE_S 11 -/* MCPWM_GEN0_A_NCIFORCE : R/W ;bitpos:[10] ;default: 1'd0 ; */ -/*description: non-continuous immediate sw force, a toggle will trigger a force event.*/ +/** MCPWM_GEN0_FORCE_REG register + * Permissives to force PWM0A and PWM0B outputs by software + */ +#define MCPWM_GEN0_FORCE_REG(i) (DR_REG_MCPWM_BASE(i) + 0x4c) +/** MCPWM_GEN0_CNTUFORCE_UPMETHOD : R/W; bitpos: [5:0]; default: 32; + * Updating method for continuous software force of PWM generator0. When all bits are + * set to 0: immediately, when bit0 is set to 1: TEZ,,when bit1 is set to 1: TEP, when + * bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync, + * when bit5 is set to 1: disable update. (TEA/B here and below means an event + * generated when the timer's value equals to that of register A/B.) + */ +#define MCPWM_GEN0_CNTUFORCE_UPMETHOD 0x0000003FU +#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_M (MCPWM_GEN0_CNTUFORCE_UPMETHOD_V << MCPWM_GEN0_CNTUFORCE_UPMETHOD_S) +#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_V 0x0000003FU +#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_S 0 +/** MCPWM_GEN0_A_CNTUFORCE_MODE : R/W; bitpos: [7:6]; default: 0; + * Continuous software force mode for PWM0A. 0: disabled, 1: low, 2: high, 3: disabled + */ +#define MCPWM_GEN0_A_CNTUFORCE_MODE 0x00000003U +#define MCPWM_GEN0_A_CNTUFORCE_MODE_M (MCPWM_GEN0_A_CNTUFORCE_MODE_V << MCPWM_GEN0_A_CNTUFORCE_MODE_S) +#define MCPWM_GEN0_A_CNTUFORCE_MODE_V 0x00000003U +#define MCPWM_GEN0_A_CNTUFORCE_MODE_S 6 +/** MCPWM_GEN0_B_CNTUFORCE_MODE : R/W; bitpos: [9:8]; default: 0; + * Continuous software force mode for PWM0B. 0: disabled, 1: low, 2: high, 3: disabled + */ +#define MCPWM_GEN0_B_CNTUFORCE_MODE 0x00000003U +#define MCPWM_GEN0_B_CNTUFORCE_MODE_M (MCPWM_GEN0_B_CNTUFORCE_MODE_V << MCPWM_GEN0_B_CNTUFORCE_MODE_S) +#define MCPWM_GEN0_B_CNTUFORCE_MODE_V 0x00000003U +#define MCPWM_GEN0_B_CNTUFORCE_MODE_S 8 +/** MCPWM_GEN0_A_NCIFORCE : R/W; bitpos: [10]; default: 0; + * Trigger of non-continuous immediate software-force event for PWM0A, a toggle will + * trigger a force event. + */ #define MCPWM_GEN0_A_NCIFORCE (BIT(10)) -#define MCPWM_GEN0_A_NCIFORCE_M (BIT(10)) -#define MCPWM_GEN0_A_NCIFORCE_V 0x1 +#define MCPWM_GEN0_A_NCIFORCE_M (MCPWM_GEN0_A_NCIFORCE_V << MCPWM_GEN0_A_NCIFORCE_S) +#define MCPWM_GEN0_A_NCIFORCE_V 0x00000001U #define MCPWM_GEN0_A_NCIFORCE_S 10 -/* MCPWM_GEN0_B_CNTUFORCE_MODE : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ -/*description: 0: disabled, 1: low, 2: high, 3: disabled.*/ -#define MCPWM_GEN0_B_CNTUFORCE_MODE 0x00000003 -#define MCPWM_GEN0_B_CNTUFORCE_MODE_M ((MCPWM_GEN0_B_CNTUFORCE_MODE_V)<<(MCPWM_GEN0_B_CNTUFORCE_MODE_S)) -#define MCPWM_GEN0_B_CNTUFORCE_MODE_V 0x3 -#define MCPWM_GEN0_B_CNTUFORCE_MODE_S 8 -/* MCPWM_GEN0_A_CNTUFORCE_MODE : R/W ;bitpos:[7:6] ;default: 2'd0 ; */ -/*description: 0: disabled, 1: low, 2: high, 3: disabled.*/ -#define MCPWM_GEN0_A_CNTUFORCE_MODE 0x00000003 -#define MCPWM_GEN0_A_CNTUFORCE_MODE_M ((MCPWM_GEN0_A_CNTUFORCE_MODE_V)<<(MCPWM_GEN0_A_CNTUFORCE_MODE_S)) -#define MCPWM_GEN0_A_CNTUFORCE_MODE_V 0x3 -#define MCPWM_GEN0_A_CNTUFORCE_MODE_S 6 -/* MCPWM_GEN0_CNTUFORCE_UPMETHOD : R/W ;bitpos:[5:0] ;default: 6'h20 ; */ -/*description: 0: immediate, bit0: tez, bit1: tep, bit2: tea, bit3: teb, bit4: sync, bit5: free -ze.*/ -#define MCPWM_GEN0_CNTUFORCE_UPMETHOD 0x0000003F -#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_M ((MCPWM_GEN0_CNTUFORCE_UPMETHOD_V)<<(MCPWM_GEN0_CNTUFORCE_UPMETHOD_S)) -#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_V 0x3F -#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_S 0 +/** MCPWM_GEN0_A_NCIFORCE_MODE : R/W; bitpos: [12:11]; default: 0; + * non-continuous immediate software force mode for PWM0A, 0: disabled, 1: low, 2: + * high, 3: disabled + */ +#define MCPWM_GEN0_A_NCIFORCE_MODE 0x00000003U +#define MCPWM_GEN0_A_NCIFORCE_MODE_M (MCPWM_GEN0_A_NCIFORCE_MODE_V << MCPWM_GEN0_A_NCIFORCE_MODE_S) +#define MCPWM_GEN0_A_NCIFORCE_MODE_V 0x00000003U +#define MCPWM_GEN0_A_NCIFORCE_MODE_S 11 +/** MCPWM_GEN0_B_NCIFORCE : R/W; bitpos: [13]; default: 0; + * Trigger of non-continuous immediate software-force event for PWM0B, a toggle will + * trigger a force event. + */ +#define MCPWM_GEN0_B_NCIFORCE (BIT(13)) +#define MCPWM_GEN0_B_NCIFORCE_M (MCPWM_GEN0_B_NCIFORCE_V << MCPWM_GEN0_B_NCIFORCE_S) +#define MCPWM_GEN0_B_NCIFORCE_V 0x00000001U +#define MCPWM_GEN0_B_NCIFORCE_S 13 +/** MCPWM_GEN0_B_NCIFORCE_MODE : R/W; bitpos: [15:14]; default: 0; + * non-continuous immediate software force mode for PWM0B, 0: disabled, 1: low, 2: + * high, 3: disabled + */ +#define MCPWM_GEN0_B_NCIFORCE_MODE 0x00000003U +#define MCPWM_GEN0_B_NCIFORCE_MODE_M (MCPWM_GEN0_B_NCIFORCE_MODE_V << MCPWM_GEN0_B_NCIFORCE_MODE_S) +#define MCPWM_GEN0_B_NCIFORCE_MODE_V 0x00000003U +#define MCPWM_GEN0_B_NCIFORCE_MODE_S 14 -#define MCPWM_GEN0_A_REG(i) (REG_MCPWM_BASE(i) + 0x50) -/* MCPWM_GEN0_A_DT1 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ -/*description: 0: no change, 1: low, 2: high, 3: toggle.*/ -#define MCPWM_GEN0_A_DT1 0x00000003 -#define MCPWM_GEN0_A_DT1_M ((MCPWM_GEN0_A_DT1_V)<<(MCPWM_GEN0_A_DT1_S)) -#define MCPWM_GEN0_A_DT1_V 0x3 -#define MCPWM_GEN0_A_DT1_S 22 -/* MCPWM_GEN0_A_DT0 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ -/*description: .*/ -#define MCPWM_GEN0_A_DT0 0x00000003 -#define MCPWM_GEN0_A_DT0_M ((MCPWM_GEN0_A_DT0_V)<<(MCPWM_GEN0_A_DT0_S)) -#define MCPWM_GEN0_A_DT0_V 0x3 -#define MCPWM_GEN0_A_DT0_S 20 -/* MCPWM_GEN0_A_DTEB : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ -/*description: .*/ -#define MCPWM_GEN0_A_DTEB 0x00000003 -#define MCPWM_GEN0_A_DTEB_M ((MCPWM_GEN0_A_DTEB_V)<<(MCPWM_GEN0_A_DTEB_S)) -#define MCPWM_GEN0_A_DTEB_V 0x3 -#define MCPWM_GEN0_A_DTEB_S 18 -/* MCPWM_GEN0_A_DTEA : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ -/*description: .*/ -#define MCPWM_GEN0_A_DTEA 0x00000003 -#define MCPWM_GEN0_A_DTEA_M ((MCPWM_GEN0_A_DTEA_V)<<(MCPWM_GEN0_A_DTEA_S)) -#define MCPWM_GEN0_A_DTEA_V 0x3 -#define MCPWM_GEN0_A_DTEA_S 16 -/* MCPWM_GEN0_A_DTEP : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ -/*description: .*/ -#define MCPWM_GEN0_A_DTEP 0x00000003 -#define MCPWM_GEN0_A_DTEP_M ((MCPWM_GEN0_A_DTEP_V)<<(MCPWM_GEN0_A_DTEP_S)) -#define MCPWM_GEN0_A_DTEP_V 0x3 -#define MCPWM_GEN0_A_DTEP_S 14 -/* MCPWM_GEN0_A_DTEZ : R/W ;bitpos:[13:12] ;default: 2'd0 ; */ -/*description: .*/ -#define MCPWM_GEN0_A_DTEZ 0x00000003 -#define MCPWM_GEN0_A_DTEZ_M ((MCPWM_GEN0_A_DTEZ_V)<<(MCPWM_GEN0_A_DTEZ_S)) -#define MCPWM_GEN0_A_DTEZ_V 0x3 -#define MCPWM_GEN0_A_DTEZ_S 12 -/* MCPWM_GEN0_A_UT1 : R/W ;bitpos:[11:10] ;default: 2'd0 ; */ -/*description: .*/ -#define MCPWM_GEN0_A_UT1 0x00000003 -#define MCPWM_GEN0_A_UT1_M ((MCPWM_GEN0_A_UT1_V)<<(MCPWM_GEN0_A_UT1_S)) -#define MCPWM_GEN0_A_UT1_V 0x3 -#define MCPWM_GEN0_A_UT1_S 10 -/* MCPWM_GEN0_A_UT0 : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ -/*description: .*/ -#define MCPWM_GEN0_A_UT0 0x00000003 -#define MCPWM_GEN0_A_UT0_M ((MCPWM_GEN0_A_UT0_V)<<(MCPWM_GEN0_A_UT0_S)) -#define MCPWM_GEN0_A_UT0_V 0x3 -#define MCPWM_GEN0_A_UT0_S 8 -/* MCPWM_GEN0_A_UTEB : R/W ;bitpos:[7:6] ;default: 2'd0 ; */ -/*description: .*/ -#define MCPWM_GEN0_A_UTEB 0x00000003 -#define MCPWM_GEN0_A_UTEB_M ((MCPWM_GEN0_A_UTEB_V)<<(MCPWM_GEN0_A_UTEB_S)) -#define MCPWM_GEN0_A_UTEB_V 0x3 -#define MCPWM_GEN0_A_UTEB_S 6 -/* MCPWM_GEN0_A_UTEA : R/W ;bitpos:[5:4] ;default: 2'd0 ; */ -/*description: .*/ -#define MCPWM_GEN0_A_UTEA 0x00000003 -#define MCPWM_GEN0_A_UTEA_M ((MCPWM_GEN0_A_UTEA_V)<<(MCPWM_GEN0_A_UTEA_S)) -#define MCPWM_GEN0_A_UTEA_V 0x3 -#define MCPWM_GEN0_A_UTEA_S 4 -/* MCPWM_GEN0_A_UTEP : R/W ;bitpos:[3:2] ;default: 2'd0 ; */ -/*description: .*/ -#define MCPWM_GEN0_A_UTEP 0x00000003 -#define MCPWM_GEN0_A_UTEP_M ((MCPWM_GEN0_A_UTEP_V)<<(MCPWM_GEN0_A_UTEP_S)) -#define MCPWM_GEN0_A_UTEP_V 0x3 -#define MCPWM_GEN0_A_UTEP_S 2 -/* MCPWM_GEN0_A_UTEZ : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: .*/ -#define MCPWM_GEN0_A_UTEZ 0x00000003 -#define MCPWM_GEN0_A_UTEZ_M ((MCPWM_GEN0_A_UTEZ_V)<<(MCPWM_GEN0_A_UTEZ_S)) -#define MCPWM_GEN0_A_UTEZ_V 0x3 +/** MCPWM_GEN0_A_REG register + * Actions triggered by events on PWM0A + */ +#define MCPWM_GEN0_A_REG(i) (DR_REG_MCPWM_BASE(i) + 0x50) +/** MCPWM_GEN0_A_UTEZ : R/W; bitpos: [1:0]; default: 0; + * Action on PWM0A triggered by event TEZ when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN0_A_UTEZ 0x00000003U +#define MCPWM_GEN0_A_UTEZ_M (MCPWM_GEN0_A_UTEZ_V << MCPWM_GEN0_A_UTEZ_S) +#define MCPWM_GEN0_A_UTEZ_V 0x00000003U #define MCPWM_GEN0_A_UTEZ_S 0 +/** MCPWM_GEN0_A_UTEP : R/W; bitpos: [3:2]; default: 0; + * Action on PWM0A triggered by event TEP when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN0_A_UTEP 0x00000003U +#define MCPWM_GEN0_A_UTEP_M (MCPWM_GEN0_A_UTEP_V << MCPWM_GEN0_A_UTEP_S) +#define MCPWM_GEN0_A_UTEP_V 0x00000003U +#define MCPWM_GEN0_A_UTEP_S 2 +/** MCPWM_GEN0_A_UTEA : R/W; bitpos: [5:4]; default: 0; + * Action on PWM0A triggered by event TEA when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN0_A_UTEA 0x00000003U +#define MCPWM_GEN0_A_UTEA_M (MCPWM_GEN0_A_UTEA_V << MCPWM_GEN0_A_UTEA_S) +#define MCPWM_GEN0_A_UTEA_V 0x00000003U +#define MCPWM_GEN0_A_UTEA_S 4 +/** MCPWM_GEN0_A_UTEB : R/W; bitpos: [7:6]; default: 0; + * Action on PWM0A triggered by event TEB when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN0_A_UTEB 0x00000003U +#define MCPWM_GEN0_A_UTEB_M (MCPWM_GEN0_A_UTEB_V << MCPWM_GEN0_A_UTEB_S) +#define MCPWM_GEN0_A_UTEB_V 0x00000003U +#define MCPWM_GEN0_A_UTEB_S 6 +/** MCPWM_GEN0_A_UT0 : R/W; bitpos: [9:8]; default: 0; + * Action on PWM0A triggered by event_t0 when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN0_A_UT0 0x00000003U +#define MCPWM_GEN0_A_UT0_M (MCPWM_GEN0_A_UT0_V << MCPWM_GEN0_A_UT0_S) +#define MCPWM_GEN0_A_UT0_V 0x00000003U +#define MCPWM_GEN0_A_UT0_S 8 +/** MCPWM_GEN0_A_UT1 : R/W; bitpos: [11:10]; default: 0; + * Action on PWM0A triggered by event_t1 when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN0_A_UT1 0x00000003U +#define MCPWM_GEN0_A_UT1_M (MCPWM_GEN0_A_UT1_V << MCPWM_GEN0_A_UT1_S) +#define MCPWM_GEN0_A_UT1_V 0x00000003U +#define MCPWM_GEN0_A_UT1_S 10 +/** MCPWM_GEN0_A_DTEZ : R/W; bitpos: [13:12]; default: 0; + * Action on PWM0A triggered by event TEZ when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN0_A_DTEZ 0x00000003U +#define MCPWM_GEN0_A_DTEZ_M (MCPWM_GEN0_A_DTEZ_V << MCPWM_GEN0_A_DTEZ_S) +#define MCPWM_GEN0_A_DTEZ_V 0x00000003U +#define MCPWM_GEN0_A_DTEZ_S 12 +/** MCPWM_GEN0_A_DTEP : R/W; bitpos: [15:14]; default: 0; + * Action on PWM0A triggered by event TEP when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN0_A_DTEP 0x00000003U +#define MCPWM_GEN0_A_DTEP_M (MCPWM_GEN0_A_DTEP_V << MCPWM_GEN0_A_DTEP_S) +#define MCPWM_GEN0_A_DTEP_V 0x00000003U +#define MCPWM_GEN0_A_DTEP_S 14 +/** MCPWM_GEN0_A_DTEA : R/W; bitpos: [17:16]; default: 0; + * Action on PWM0A triggered by event TEA when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN0_A_DTEA 0x00000003U +#define MCPWM_GEN0_A_DTEA_M (MCPWM_GEN0_A_DTEA_V << MCPWM_GEN0_A_DTEA_S) +#define MCPWM_GEN0_A_DTEA_V 0x00000003U +#define MCPWM_GEN0_A_DTEA_S 16 +/** MCPWM_GEN0_A_DTEB : R/W; bitpos: [19:18]; default: 0; + * Action on PWM0A triggered by event TEB when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN0_A_DTEB 0x00000003U +#define MCPWM_GEN0_A_DTEB_M (MCPWM_GEN0_A_DTEB_V << MCPWM_GEN0_A_DTEB_S) +#define MCPWM_GEN0_A_DTEB_V 0x00000003U +#define MCPWM_GEN0_A_DTEB_S 18 +/** MCPWM_GEN0_A_DT0 : R/W; bitpos: [21:20]; default: 0; + * Action on PWM0A triggered by event_t0 when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN0_A_DT0 0x00000003U +#define MCPWM_GEN0_A_DT0_M (MCPWM_GEN0_A_DT0_V << MCPWM_GEN0_A_DT0_S) +#define MCPWM_GEN0_A_DT0_V 0x00000003U +#define MCPWM_GEN0_A_DT0_S 20 +/** MCPWM_GEN0_A_DT1 : R/W; bitpos: [23:22]; default: 0; + * Action on PWM0A triggered by event_t1 when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN0_A_DT1 0x00000003U +#define MCPWM_GEN0_A_DT1_M (MCPWM_GEN0_A_DT1_V << MCPWM_GEN0_A_DT1_S) +#define MCPWM_GEN0_A_DT1_V 0x00000003U +#define MCPWM_GEN0_A_DT1_S 22 -#define MCPWM_GEN0_B_REG(i) (REG_MCPWM_BASE(i) + 0x54) -/* MCPWM_GEN0_B_DT1 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ -/*description: .*/ -#define MCPWM_GEN0_B_DT1 0x00000003 -#define MCPWM_GEN0_B_DT1_M ((MCPWM_GEN0_B_DT1_V)<<(MCPWM_GEN0_B_DT1_S)) -#define MCPWM_GEN0_B_DT1_V 0x3 -#define MCPWM_GEN0_B_DT1_S 22 -/* MCPWM_GEN0_B_DT0 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ -/*description: .*/ -#define MCPWM_GEN0_B_DT0 0x00000003 -#define MCPWM_GEN0_B_DT0_M ((MCPWM_GEN0_B_DT0_V)<<(MCPWM_GEN0_B_DT0_S)) -#define MCPWM_GEN0_B_DT0_V 0x3 -#define MCPWM_GEN0_B_DT0_S 20 -/* MCPWM_GEN0_B_DTEB : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ -/*description: .*/ -#define MCPWM_GEN0_B_DTEB 0x00000003 -#define MCPWM_GEN0_B_DTEB_M ((MCPWM_GEN0_B_DTEB_V)<<(MCPWM_GEN0_B_DTEB_S)) -#define MCPWM_GEN0_B_DTEB_V 0x3 -#define MCPWM_GEN0_B_DTEB_S 18 -/* MCPWM_GEN0_B_DTEA : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ -/*description: .*/ -#define MCPWM_GEN0_B_DTEA 0x00000003 -#define MCPWM_GEN0_B_DTEA_M ((MCPWM_GEN0_B_DTEA_V)<<(MCPWM_GEN0_B_DTEA_S)) -#define MCPWM_GEN0_B_DTEA_V 0x3 -#define MCPWM_GEN0_B_DTEA_S 16 -/* MCPWM_GEN0_B_DTEP : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ -/*description: .*/ -#define MCPWM_GEN0_B_DTEP 0x00000003 -#define MCPWM_GEN0_B_DTEP_M ((MCPWM_GEN0_B_DTEP_V)<<(MCPWM_GEN0_B_DTEP_S)) -#define MCPWM_GEN0_B_DTEP_V 0x3 -#define MCPWM_GEN0_B_DTEP_S 14 -/* MCPWM_GEN0_B_DTEZ : R/W ;bitpos:[13:12] ;default: 2'd0 ; */ -/*description: .*/ -#define MCPWM_GEN0_B_DTEZ 0x00000003 -#define MCPWM_GEN0_B_DTEZ_M ((MCPWM_GEN0_B_DTEZ_V)<<(MCPWM_GEN0_B_DTEZ_S)) -#define MCPWM_GEN0_B_DTEZ_V 0x3 -#define MCPWM_GEN0_B_DTEZ_S 12 -/* MCPWM_GEN0_B_UT1 : R/W ;bitpos:[11:10] ;default: 2'd0 ; */ -/*description: .*/ -#define MCPWM_GEN0_B_UT1 0x00000003 -#define MCPWM_GEN0_B_UT1_M ((MCPWM_GEN0_B_UT1_V)<<(MCPWM_GEN0_B_UT1_S)) -#define MCPWM_GEN0_B_UT1_V 0x3 -#define MCPWM_GEN0_B_UT1_S 10 -/* MCPWM_GEN0_B_UT0 : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ -/*description: .*/ -#define MCPWM_GEN0_B_UT0 0x00000003 -#define MCPWM_GEN0_B_UT0_M ((MCPWM_GEN0_B_UT0_V)<<(MCPWM_GEN0_B_UT0_S)) -#define MCPWM_GEN0_B_UT0_V 0x3 -#define MCPWM_GEN0_B_UT0_S 8 -/* MCPWM_GEN0_B_UTEB : R/W ;bitpos:[7:6] ;default: 2'd0 ; */ -/*description: .*/ -#define MCPWM_GEN0_B_UTEB 0x00000003 -#define MCPWM_GEN0_B_UTEB_M ((MCPWM_GEN0_B_UTEB_V)<<(MCPWM_GEN0_B_UTEB_S)) -#define MCPWM_GEN0_B_UTEB_V 0x3 -#define MCPWM_GEN0_B_UTEB_S 6 -/* MCPWM_GEN0_B_UTEA : R/W ;bitpos:[5:4] ;default: 2'd0 ; */ -/*description: .*/ -#define MCPWM_GEN0_B_UTEA 0x00000003 -#define MCPWM_GEN0_B_UTEA_M ((MCPWM_GEN0_B_UTEA_V)<<(MCPWM_GEN0_B_UTEA_S)) -#define MCPWM_GEN0_B_UTEA_V 0x3 -#define MCPWM_GEN0_B_UTEA_S 4 -/* MCPWM_GEN0_B_UTEP : R/W ;bitpos:[3:2] ;default: 2'd0 ; */ -/*description: .*/ -#define MCPWM_GEN0_B_UTEP 0x00000003 -#define MCPWM_GEN0_B_UTEP_M ((MCPWM_GEN0_B_UTEP_V)<<(MCPWM_GEN0_B_UTEP_S)) -#define MCPWM_GEN0_B_UTEP_V 0x3 -#define MCPWM_GEN0_B_UTEP_S 2 -/* MCPWM_GEN0_B_UTEZ : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: .*/ -#define MCPWM_GEN0_B_UTEZ 0x00000003 -#define MCPWM_GEN0_B_UTEZ_M ((MCPWM_GEN0_B_UTEZ_V)<<(MCPWM_GEN0_B_UTEZ_S)) -#define MCPWM_GEN0_B_UTEZ_V 0x3 +/** MCPWM_GEN0_B_REG register + * Actions triggered by events on PWM0B + */ +#define MCPWM_GEN0_B_REG(i) (DR_REG_MCPWM_BASE(i) + 0x54) +/** MCPWM_GEN0_B_UTEZ : R/W; bitpos: [1:0]; default: 0; + * Action on PWM0B triggered by event TEZ when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN0_B_UTEZ 0x00000003U +#define MCPWM_GEN0_B_UTEZ_M (MCPWM_GEN0_B_UTEZ_V << MCPWM_GEN0_B_UTEZ_S) +#define MCPWM_GEN0_B_UTEZ_V 0x00000003U #define MCPWM_GEN0_B_UTEZ_S 0 +/** MCPWM_GEN0_B_UTEP : R/W; bitpos: [3:2]; default: 0; + * Action on PWM0B triggered by event TEP when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN0_B_UTEP 0x00000003U +#define MCPWM_GEN0_B_UTEP_M (MCPWM_GEN0_B_UTEP_V << MCPWM_GEN0_B_UTEP_S) +#define MCPWM_GEN0_B_UTEP_V 0x00000003U +#define MCPWM_GEN0_B_UTEP_S 2 +/** MCPWM_GEN0_B_UTEA : R/W; bitpos: [5:4]; default: 0; + * Action on PWM0B triggered by event TEA when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN0_B_UTEA 0x00000003U +#define MCPWM_GEN0_B_UTEA_M (MCPWM_GEN0_B_UTEA_V << MCPWM_GEN0_B_UTEA_S) +#define MCPWM_GEN0_B_UTEA_V 0x00000003U +#define MCPWM_GEN0_B_UTEA_S 4 +/** MCPWM_GEN0_B_UTEB : R/W; bitpos: [7:6]; default: 0; + * Action on PWM0B triggered by event TEB when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN0_B_UTEB 0x00000003U +#define MCPWM_GEN0_B_UTEB_M (MCPWM_GEN0_B_UTEB_V << MCPWM_GEN0_B_UTEB_S) +#define MCPWM_GEN0_B_UTEB_V 0x00000003U +#define MCPWM_GEN0_B_UTEB_S 6 +/** MCPWM_GEN0_B_UT0 : R/W; bitpos: [9:8]; default: 0; + * Action on PWM0B triggered by event_t0 when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN0_B_UT0 0x00000003U +#define MCPWM_GEN0_B_UT0_M (MCPWM_GEN0_B_UT0_V << MCPWM_GEN0_B_UT0_S) +#define MCPWM_GEN0_B_UT0_V 0x00000003U +#define MCPWM_GEN0_B_UT0_S 8 +/** MCPWM_GEN0_B_UT1 : R/W; bitpos: [11:10]; default: 0; + * Action on PWM0B triggered by event_t1 when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN0_B_UT1 0x00000003U +#define MCPWM_GEN0_B_UT1_M (MCPWM_GEN0_B_UT1_V << MCPWM_GEN0_B_UT1_S) +#define MCPWM_GEN0_B_UT1_V 0x00000003U +#define MCPWM_GEN0_B_UT1_S 10 +/** MCPWM_GEN0_B_DTEZ : R/W; bitpos: [13:12]; default: 0; + * Action on PWM0B triggered by event TEZ when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN0_B_DTEZ 0x00000003U +#define MCPWM_GEN0_B_DTEZ_M (MCPWM_GEN0_B_DTEZ_V << MCPWM_GEN0_B_DTEZ_S) +#define MCPWM_GEN0_B_DTEZ_V 0x00000003U +#define MCPWM_GEN0_B_DTEZ_S 12 +/** MCPWM_GEN0_B_DTEP : R/W; bitpos: [15:14]; default: 0; + * Action on PWM0B triggered by event TEP when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN0_B_DTEP 0x00000003U +#define MCPWM_GEN0_B_DTEP_M (MCPWM_GEN0_B_DTEP_V << MCPWM_GEN0_B_DTEP_S) +#define MCPWM_GEN0_B_DTEP_V 0x00000003U +#define MCPWM_GEN0_B_DTEP_S 14 +/** MCPWM_GEN0_B_DTEA : R/W; bitpos: [17:16]; default: 0; + * Action on PWM0B triggered by event TEA when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN0_B_DTEA 0x00000003U +#define MCPWM_GEN0_B_DTEA_M (MCPWM_GEN0_B_DTEA_V << MCPWM_GEN0_B_DTEA_S) +#define MCPWM_GEN0_B_DTEA_V 0x00000003U +#define MCPWM_GEN0_B_DTEA_S 16 +/** MCPWM_GEN0_B_DTEB : R/W; bitpos: [19:18]; default: 0; + * Action on PWM0B triggered by event TEB when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN0_B_DTEB 0x00000003U +#define MCPWM_GEN0_B_DTEB_M (MCPWM_GEN0_B_DTEB_V << MCPWM_GEN0_B_DTEB_S) +#define MCPWM_GEN0_B_DTEB_V 0x00000003U +#define MCPWM_GEN0_B_DTEB_S 18 +/** MCPWM_GEN0_B_DT0 : R/W; bitpos: [21:20]; default: 0; + * Action on PWM0B triggered by event_t0 when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN0_B_DT0 0x00000003U +#define MCPWM_GEN0_B_DT0_M (MCPWM_GEN0_B_DT0_V << MCPWM_GEN0_B_DT0_S) +#define MCPWM_GEN0_B_DT0_V 0x00000003U +#define MCPWM_GEN0_B_DT0_S 20 +/** MCPWM_GEN0_B_DT1 : R/W; bitpos: [23:22]; default: 0; + * Action on PWM0B triggered by event_t1 when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN0_B_DT1 0x00000003U +#define MCPWM_GEN0_B_DT1_M (MCPWM_GEN0_B_DT1_V << MCPWM_GEN0_B_DT1_S) +#define MCPWM_GEN0_B_DT1_V 0x00000003U +#define MCPWM_GEN0_B_DT1_S 22 -#define MCPWM_DB0_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x58) -/* MCPWM_DB0_CLK_SEL : R/W ;bitpos:[17] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_DB0_CLK_SEL (BIT(17)) -#define MCPWM_DB0_CLK_SEL_M (BIT(17)) -#define MCPWM_DB0_CLK_SEL_V 0x1 -#define MCPWM_DB0_CLK_SEL_S 17 -/* MCPWM_DB0_B_OUTBYPASS : R/W ;bitpos:[16] ;default: 1'd1 ; */ -/*description: .*/ -#define MCPWM_DB0_B_OUTBYPASS (BIT(16)) -#define MCPWM_DB0_B_OUTBYPASS_M (BIT(16)) -#define MCPWM_DB0_B_OUTBYPASS_V 0x1 -#define MCPWM_DB0_B_OUTBYPASS_S 16 -/* MCPWM_DB0_A_OUTBYPASS : R/W ;bitpos:[15] ;default: 1'd1 ; */ -/*description: .*/ -#define MCPWM_DB0_A_OUTBYPASS (BIT(15)) -#define MCPWM_DB0_A_OUTBYPASS_M (BIT(15)) -#define MCPWM_DB0_A_OUTBYPASS_V 0x1 -#define MCPWM_DB0_A_OUTBYPASS_S 15 -/* MCPWM_DB0_FED_OUTINVERT : R/W ;bitpos:[14] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_DB0_FED_OUTINVERT (BIT(14)) -#define MCPWM_DB0_FED_OUTINVERT_M (BIT(14)) -#define MCPWM_DB0_FED_OUTINVERT_V 0x1 -#define MCPWM_DB0_FED_OUTINVERT_S 14 -/* MCPWM_DB0_RED_OUTINVERT : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_DB0_RED_OUTINVERT (BIT(13)) -#define MCPWM_DB0_RED_OUTINVERT_M (BIT(13)) -#define MCPWM_DB0_RED_OUTINVERT_V 0x1 -#define MCPWM_DB0_RED_OUTINVERT_S 13 -/* MCPWM_DB0_FED_INSEL : R/W ;bitpos:[12] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_DB0_FED_INSEL (BIT(12)) -#define MCPWM_DB0_FED_INSEL_M (BIT(12)) -#define MCPWM_DB0_FED_INSEL_V 0x1 -#define MCPWM_DB0_FED_INSEL_S 12 -/* MCPWM_DB0_RED_INSEL : R/W ;bitpos:[11] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_DB0_RED_INSEL (BIT(11)) -#define MCPWM_DB0_RED_INSEL_M (BIT(11)) -#define MCPWM_DB0_RED_INSEL_V 0x1 -#define MCPWM_DB0_RED_INSEL_S 11 -/* MCPWM_DB0_B_OUTSWAP : R/W ;bitpos:[10] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_DB0_B_OUTSWAP (BIT(10)) -#define MCPWM_DB0_B_OUTSWAP_M (BIT(10)) -#define MCPWM_DB0_B_OUTSWAP_V 0x1 -#define MCPWM_DB0_B_OUTSWAP_S 10 -/* MCPWM_DB0_A_OUTSWAP : R/W ;bitpos:[9] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_DB0_A_OUTSWAP (BIT(9)) -#define MCPWM_DB0_A_OUTSWAP_M (BIT(9)) -#define MCPWM_DB0_A_OUTSWAP_V 0x1 -#define MCPWM_DB0_A_OUTSWAP_S 9 -/* MCPWM_DB0_DEB_MODE : R/W ;bitpos:[8] ;default: 1'd0 ; */ -/*description: immediate, dual-edge B mode, 0: fed/red take effect on different path separately -, 1: fed/red take effect on B path, A out is in bypass or dulpB mode.*/ -#define MCPWM_DB0_DEB_MODE (BIT(8)) -#define MCPWM_DB0_DEB_MODE_M (BIT(8)) -#define MCPWM_DB0_DEB_MODE_V 0x1 -#define MCPWM_DB0_DEB_MODE_S 8 -/* MCPWM_DB0_RED_UPMETHOD : R/W ;bitpos:[7:4] ;default: 4'd0 ; */ -/*description: 0: immediate, bit0: tez, bit1: tep, bit2: sync, bit3: freeze.*/ -#define MCPWM_DB0_RED_UPMETHOD 0x0000000F -#define MCPWM_DB0_RED_UPMETHOD_M ((MCPWM_DB0_RED_UPMETHOD_V)<<(MCPWM_DB0_RED_UPMETHOD_S)) -#define MCPWM_DB0_RED_UPMETHOD_V 0xF -#define MCPWM_DB0_RED_UPMETHOD_S 4 -/* MCPWM_DB0_FED_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: 0: immediate, bit0: tez, bit1: tep, bit2: sync, bit3: freeze.*/ -#define MCPWM_DB0_FED_UPMETHOD 0x0000000F -#define MCPWM_DB0_FED_UPMETHOD_M ((MCPWM_DB0_FED_UPMETHOD_V)<<(MCPWM_DB0_FED_UPMETHOD_S)) -#define MCPWM_DB0_FED_UPMETHOD_V 0xF -#define MCPWM_DB0_FED_UPMETHOD_S 0 - -#define MCPWM_DB0_FED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x5C) -/* MCPWM_DB0_FED : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ -/*description: .*/ -#define MCPWM_DB0_FED 0x0000FFFF -#define MCPWM_DB0_FED_M ((MCPWM_DB0_FED_V)<<(MCPWM_DB0_FED_S)) -#define MCPWM_DB0_FED_V 0xFFFF -#define MCPWM_DB0_FED_S 0 - -#define MCPWM_DB0_RED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x60) -/* MCPWM_DB0_RED : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ -/*description: .*/ -#define MCPWM_DB0_RED 0x0000FFFF -#define MCPWM_DB0_RED_M ((MCPWM_DB0_RED_V)<<(MCPWM_DB0_RED_S)) -#define MCPWM_DB0_RED_V 0xFFFF -#define MCPWM_DB0_RED_S 0 - -#define MCPWM_CHOPPER0_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x64) -/* MCPWM_CHOPPER0_IN_INVERT : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_CHOPPER0_IN_INVERT (BIT(13)) -#define MCPWM_CHOPPER0_IN_INVERT_M (BIT(13)) -#define MCPWM_CHOPPER0_IN_INVERT_V 0x1 -#define MCPWM_CHOPPER0_IN_INVERT_S 13 -/* MCPWM_CHOPPER0_OUT_INVERT : R/W ;bitpos:[12] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_CHOPPER0_OUT_INVERT (BIT(12)) -#define MCPWM_CHOPPER0_OUT_INVERT_M (BIT(12)) -#define MCPWM_CHOPPER0_OUT_INVERT_V 0x1 -#define MCPWM_CHOPPER0_OUT_INVERT_S 12 -/* MCPWM_CHOPPER0_OSHTWTH : R/W ;bitpos:[11:8] ;default: 4'd0 ; */ -/*description: .*/ -#define MCPWM_CHOPPER0_OSHTWTH 0x0000000F -#define MCPWM_CHOPPER0_OSHTWTH_M ((MCPWM_CHOPPER0_OSHTWTH_V)<<(MCPWM_CHOPPER0_OSHTWTH_S)) -#define MCPWM_CHOPPER0_OSHTWTH_V 0xF -#define MCPWM_CHOPPER0_OSHTWTH_S 8 -/* MCPWM_CHOPPER0_DUTY : R/W ;bitpos:[7:5] ;default: 3'd0 ; */ -/*description: .*/ -#define MCPWM_CHOPPER0_DUTY 0x00000007 -#define MCPWM_CHOPPER0_DUTY_M ((MCPWM_CHOPPER0_DUTY_V)<<(MCPWM_CHOPPER0_DUTY_S)) -#define MCPWM_CHOPPER0_DUTY_V 0x7 -#define MCPWM_CHOPPER0_DUTY_S 5 -/* MCPWM_CHOPPER0_PRESCALE : R/W ;bitpos:[4:1] ;default: 4'd0 ; */ -/*description: .*/ -#define MCPWM_CHOPPER0_PRESCALE 0x0000000F -#define MCPWM_CHOPPER0_PRESCALE_M ((MCPWM_CHOPPER0_PRESCALE_V)<<(MCPWM_CHOPPER0_PRESCALE_S)) -#define MCPWM_CHOPPER0_PRESCALE_V 0xF -#define MCPWM_CHOPPER0_PRESCALE_S 1 -/* MCPWM_CHOPPER0_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_CHOPPER0_EN (BIT(0)) -#define MCPWM_CHOPPER0_EN_M (BIT(0)) -#define MCPWM_CHOPPER0_EN_V 0x1 -#define MCPWM_CHOPPER0_EN_S 0 - -#define MCPWM_TZ0_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x68) -/* MCPWM_TZ0_B_OST_U : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ -/*description: 0: do nothing, 1: force lo, 2: force hi, 3: toggle.*/ -#define MCPWM_TZ0_B_OST_U 0x00000003 -#define MCPWM_TZ0_B_OST_U_M ((MCPWM_TZ0_B_OST_U_V)<<(MCPWM_TZ0_B_OST_U_S)) -#define MCPWM_TZ0_B_OST_U_V 0x3 -#define MCPWM_TZ0_B_OST_U_S 22 -/* MCPWM_TZ0_B_OST_D : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ -/*description: 0: do nothing, 1: force lo, 2: force hi, 3: toggle.*/ -#define MCPWM_TZ0_B_OST_D 0x00000003 -#define MCPWM_TZ0_B_OST_D_M ((MCPWM_TZ0_B_OST_D_V)<<(MCPWM_TZ0_B_OST_D_S)) -#define MCPWM_TZ0_B_OST_D_V 0x3 -#define MCPWM_TZ0_B_OST_D_S 20 -/* MCPWM_TZ0_B_CBC_U : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ -/*description: 0: do nothing, 1: force lo, 2: force hi, 3: toggle.*/ -#define MCPWM_TZ0_B_CBC_U 0x00000003 -#define MCPWM_TZ0_B_CBC_U_M ((MCPWM_TZ0_B_CBC_U_V)<<(MCPWM_TZ0_B_CBC_U_S)) -#define MCPWM_TZ0_B_CBC_U_V 0x3 -#define MCPWM_TZ0_B_CBC_U_S 18 -/* MCPWM_TZ0_B_CBC_D : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ -/*description: 0: do nothing, 1: force lo, 2: force hi, 3: toggle.*/ -#define MCPWM_TZ0_B_CBC_D 0x00000003 -#define MCPWM_TZ0_B_CBC_D_M ((MCPWM_TZ0_B_CBC_D_V)<<(MCPWM_TZ0_B_CBC_D_S)) -#define MCPWM_TZ0_B_CBC_D_V 0x3 -#define MCPWM_TZ0_B_CBC_D_S 16 -/* MCPWM_TZ0_A_OST_U : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ -/*description: 0: do nothing, 1: force lo, 2: force hi, 3: toggle.*/ -#define MCPWM_TZ0_A_OST_U 0x00000003 -#define MCPWM_TZ0_A_OST_U_M ((MCPWM_TZ0_A_OST_U_V)<<(MCPWM_TZ0_A_OST_U_S)) -#define MCPWM_TZ0_A_OST_U_V 0x3 -#define MCPWM_TZ0_A_OST_U_S 14 -/* MCPWM_TZ0_A_OST_D : R/W ;bitpos:[13:12] ;default: 2'd0 ; */ -/*description: 0: do nothing, 1: force lo, 2: force hi, 3: toggle.*/ -#define MCPWM_TZ0_A_OST_D 0x00000003 -#define MCPWM_TZ0_A_OST_D_M ((MCPWM_TZ0_A_OST_D_V)<<(MCPWM_TZ0_A_OST_D_S)) -#define MCPWM_TZ0_A_OST_D_V 0x3 -#define MCPWM_TZ0_A_OST_D_S 12 -/* MCPWM_TZ0_A_CBC_U : R/W ;bitpos:[11:10] ;default: 2'd0 ; */ -/*description: 0: do nothing, 1: force lo, 2: force hi, 3: toggle.*/ -#define MCPWM_TZ0_A_CBC_U 0x00000003 -#define MCPWM_TZ0_A_CBC_U_M ((MCPWM_TZ0_A_CBC_U_V)<<(MCPWM_TZ0_A_CBC_U_S)) -#define MCPWM_TZ0_A_CBC_U_V 0x3 -#define MCPWM_TZ0_A_CBC_U_S 10 -/* MCPWM_TZ0_A_CBC_D : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ -/*description: 0: do nothing, 1: force lo, 2: force hi, 3: toggle.*/ -#define MCPWM_TZ0_A_CBC_D 0x00000003 -#define MCPWM_TZ0_A_CBC_D_M ((MCPWM_TZ0_A_CBC_D_V)<<(MCPWM_TZ0_A_CBC_D_S)) -#define MCPWM_TZ0_A_CBC_D_V 0x3 -#define MCPWM_TZ0_A_CBC_D_S 8 -/* MCPWM_TZ0_F0_OST : R/W ;bitpos:[7] ;default: 1'd0 ; */ -/*description: 0: disable, 1: enable.*/ -#define MCPWM_TZ0_F0_OST (BIT(7)) -#define MCPWM_TZ0_F0_OST_M (BIT(7)) -#define MCPWM_TZ0_F0_OST_V 0x1 -#define MCPWM_TZ0_F0_OST_S 7 -/* MCPWM_TZ0_F1_OST : R/W ;bitpos:[6] ;default: 1'd0 ; */ -/*description: 0: disable, 1: enable.*/ -#define MCPWM_TZ0_F1_OST (BIT(6)) -#define MCPWM_TZ0_F1_OST_M (BIT(6)) -#define MCPWM_TZ0_F1_OST_V 0x1 -#define MCPWM_TZ0_F1_OST_S 6 -/* MCPWM_TZ0_F2_OST : R/W ;bitpos:[5] ;default: 1'd0 ; */ -/*description: 0: disable, 1: enable.*/ -#define MCPWM_TZ0_F2_OST (BIT(5)) -#define MCPWM_TZ0_F2_OST_M (BIT(5)) -#define MCPWM_TZ0_F2_OST_V 0x1 -#define MCPWM_TZ0_F2_OST_S 5 -/* MCPWM_TZ0_SW_OST : R/W ;bitpos:[4] ;default: 1'd0 ; */ -/*description: 0: disable, 1: enable.*/ -#define MCPWM_TZ0_SW_OST (BIT(4)) -#define MCPWM_TZ0_SW_OST_M (BIT(4)) -#define MCPWM_TZ0_SW_OST_V 0x1 -#define MCPWM_TZ0_SW_OST_S 4 -/* MCPWM_TZ0_F0_CBC : R/W ;bitpos:[3] ;default: 1'd0 ; */ -/*description: 0: disable, 1: enable.*/ -#define MCPWM_TZ0_F0_CBC (BIT(3)) -#define MCPWM_TZ0_F0_CBC_M (BIT(3)) -#define MCPWM_TZ0_F0_CBC_V 0x1 -#define MCPWM_TZ0_F0_CBC_S 3 -/* MCPWM_TZ0_F1_CBC : R/W ;bitpos:[2] ;default: 1'd0 ; */ -/*description: 0: disable, 1: enable.*/ -#define MCPWM_TZ0_F1_CBC (BIT(2)) -#define MCPWM_TZ0_F1_CBC_M (BIT(2)) -#define MCPWM_TZ0_F1_CBC_V 0x1 -#define MCPWM_TZ0_F1_CBC_S 2 -/* MCPWM_TZ0_F2_CBC : R/W ;bitpos:[1] ;default: 1'd0 ; */ -/*description: 0: disable, 1: enable.*/ -#define MCPWM_TZ0_F2_CBC (BIT(1)) -#define MCPWM_TZ0_F2_CBC_M (BIT(1)) -#define MCPWM_TZ0_F2_CBC_V 0x1 -#define MCPWM_TZ0_F2_CBC_S 1 -/* MCPWM_TZ0_SW_CBC : R/W ;bitpos:[0] ;default: 1'd0 ; */ -/*description: 0: disable, 1: enable.*/ -#define MCPWM_TZ0_SW_CBC (BIT(0)) -#define MCPWM_TZ0_SW_CBC_M (BIT(0)) -#define MCPWM_TZ0_SW_CBC_V 0x1 -#define MCPWM_TZ0_SW_CBC_S 0 - -#define MCPWM_TZ0_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0x6C) -/* MCPWM_TZ0_FORCE_OST : R/W ;bitpos:[4] ;default: 1'd0 ; */ -/*description: a toggle trigger a oneshot tripping.*/ -#define MCPWM_TZ0_FORCE_OST (BIT(4)) -#define MCPWM_TZ0_FORCE_OST_M (BIT(4)) -#define MCPWM_TZ0_FORCE_OST_V 0x1 -#define MCPWM_TZ0_FORCE_OST_S 4 -/* MCPWM_TZ0_FORCE_CBC : R/W ;bitpos:[3] ;default: 1'd0 ; */ -/*description: a toggle trigger a cycle-by-cycle tripping.*/ -#define MCPWM_TZ0_FORCE_CBC (BIT(3)) -#define MCPWM_TZ0_FORCE_CBC_M (BIT(3)) -#define MCPWM_TZ0_FORCE_CBC_V 0x1 -#define MCPWM_TZ0_FORCE_CBC_S 3 -/* MCPWM_TZ0_CBCPULSE : R/W ;bitpos:[2:1] ;default: 2'd0 ; */ -/*description: bit0: tez, bit1: tep.*/ -#define MCPWM_TZ0_CBCPULSE 0x00000003 -#define MCPWM_TZ0_CBCPULSE_M ((MCPWM_TZ0_CBCPULSE_V)<<(MCPWM_TZ0_CBCPULSE_S)) -#define MCPWM_TZ0_CBCPULSE_V 0x3 -#define MCPWM_TZ0_CBCPULSE_S 1 -/* MCPWM_TZ0_CLR_OST : R/W ;bitpos:[0] ;default: 1'd0 ; */ -/*description: a toggle will clear oneshot tripping.*/ -#define MCPWM_TZ0_CLR_OST (BIT(0)) -#define MCPWM_TZ0_CLR_OST_M (BIT(0)) -#define MCPWM_TZ0_CLR_OST_V 0x1 -#define MCPWM_TZ0_CLR_OST_S 0 - -#define MCPWM_TZ0_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x70) -/* MCPWM_TZ0_OST_ON : RO ;bitpos:[1] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_TZ0_OST_ON (BIT(1)) -#define MCPWM_TZ0_OST_ON_M (BIT(1)) -#define MCPWM_TZ0_OST_ON_V 0x1 -#define MCPWM_TZ0_OST_ON_S 1 -/* MCPWM_TZ0_CBC_ON : RO ;bitpos:[0] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_TZ0_CBC_ON (BIT(0)) -#define MCPWM_TZ0_CBC_ON_M (BIT(0)) -#define MCPWM_TZ0_CBC_ON_V 0x1 -#define MCPWM_TZ0_CBC_ON_S 0 - -#define MCPWM_CMPR1_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x74) -/* MCPWM_CMPR1_B_SHDW_FULL : R/W ;bitpos:[9] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_CMPR1_B_SHDW_FULL (BIT(9)) -#define MCPWM_CMPR1_B_SHDW_FULL_M (BIT(9)) -#define MCPWM_CMPR1_B_SHDW_FULL_V 0x1 -#define MCPWM_CMPR1_B_SHDW_FULL_S 9 -/* MCPWM_CMPR1_A_SHDW_FULL : R/W ;bitpos:[8] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_CMPR1_A_SHDW_FULL (BIT(8)) -#define MCPWM_CMPR1_A_SHDW_FULL_M (BIT(8)) -#define MCPWM_CMPR1_A_SHDW_FULL_V 0x1 -#define MCPWM_CMPR1_A_SHDW_FULL_S 8 -/* MCPWM_CMPR1_B_UPMETHOD : R/W ;bitpos:[7:4] ;default: 4'd0 ; */ -/*description: 0: immediate, bit0: tez, bit1: tep, bit2: sync, bit3: freeze.*/ -#define MCPWM_CMPR1_B_UPMETHOD 0x0000000F -#define MCPWM_CMPR1_B_UPMETHOD_M ((MCPWM_CMPR1_B_UPMETHOD_V)<<(MCPWM_CMPR1_B_UPMETHOD_S)) -#define MCPWM_CMPR1_B_UPMETHOD_V 0xF -#define MCPWM_CMPR1_B_UPMETHOD_S 4 -/* MCPWM_CMPR1_A_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: 0: immediate, bit0: tez, bit1: tep, bit2: sync, bit3: freeze.*/ -#define MCPWM_CMPR1_A_UPMETHOD 0x0000000F -#define MCPWM_CMPR1_A_UPMETHOD_M ((MCPWM_CMPR1_A_UPMETHOD_V)<<(MCPWM_CMPR1_A_UPMETHOD_S)) -#define MCPWM_CMPR1_A_UPMETHOD_V 0xF -#define MCPWM_CMPR1_A_UPMETHOD_S 0 - -#define MCPWM_CMPR1_VALUE0_REG(i) (REG_MCPWM_BASE(i) + 0x78) -/* MCPWM_CMPR1_A : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ -/*description: .*/ -#define MCPWM_CMPR1_A 0x0000FFFF -#define MCPWM_CMPR1_A_M ((MCPWM_CMPR1_A_V)<<(MCPWM_CMPR1_A_S)) -#define MCPWM_CMPR1_A_V 0xFFFF -#define MCPWM_CMPR1_A_S 0 - -#define MCPWM_CMPR1_VALUE1_REG(i) (REG_MCPWM_BASE(i) + 0x7C) -/* MCPWM_CMPR1_B : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ -/*description: .*/ -#define MCPWM_CMPR1_B 0x0000FFFF -#define MCPWM_CMPR1_B_M ((MCPWM_CMPR1_B_V)<<(MCPWM_CMPR1_B_S)) -#define MCPWM_CMPR1_B_V 0xFFFF -#define MCPWM_CMPR1_B_S 0 - -#define MCPWM_GEN1_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x80) -/* MCPWM_GEN1_T1_SEL : R/W ;bitpos:[9:7] ;default: 3'd0 ; */ -/*description: take effect immediately, 0: extra0, 1: extra1, 2: extra2, 3: sync_taken, 4: none.*/ -#define MCPWM_GEN1_T1_SEL 0x00000007 -#define MCPWM_GEN1_T1_SEL_M ((MCPWM_GEN1_T1_SEL_V)<<(MCPWM_GEN1_T1_SEL_S)) -#define MCPWM_GEN1_T1_SEL_V 0x7 -#define MCPWM_GEN1_T1_SEL_S 7 -/* MCPWM_GEN1_T0_SEL : R/W ;bitpos:[6:4] ;default: 3'd0 ; */ -/*description: take effect immediately, 0: extra0, 1: extra1, 2: extra2, 3: sync_taken, 4: none.*/ -#define MCPWM_GEN1_T0_SEL 0x00000007 -#define MCPWM_GEN1_T0_SEL_M ((MCPWM_GEN1_T0_SEL_V)<<(MCPWM_GEN1_T0_SEL_S)) -#define MCPWM_GEN1_T0_SEL_V 0x7 -#define MCPWM_GEN1_T0_SEL_S 4 -/* MCPWM_GEN1_CFG_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: 0: immediate, bit0: tez, bit1: tep, bit2: sync. bit3: freeze.*/ -#define MCPWM_GEN1_CFG_UPMETHOD 0x0000000F -#define MCPWM_GEN1_CFG_UPMETHOD_M ((MCPWM_GEN1_CFG_UPMETHOD_V)<<(MCPWM_GEN1_CFG_UPMETHOD_S)) -#define MCPWM_GEN1_CFG_UPMETHOD_V 0xF +/** MCPWM_DT0_CFG_REG register + * PWM generator 0 dead time type selection and configuration + */ +#define MCPWM_DT0_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0x58) +/** MCPWM_DT0_FED_UPMETHOD : R/W; bitpos: [3:0]; default: 0; + * Update method for FED (rising edge delay) active register. 0: immediate, when bit0 + * is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when + * bit3 is set to 1: disable the update + */ +#define MCPWM_DT0_FED_UPMETHOD 0x0000000FU +#define MCPWM_DT0_FED_UPMETHOD_M (MCPWM_DT0_FED_UPMETHOD_V << MCPWM_DT0_FED_UPMETHOD_S) +#define MCPWM_DT0_FED_UPMETHOD_V 0x0000000FU +#define MCPWM_DT0_FED_UPMETHOD_S 0 +/** MCPWM_DT0_RED_UPMETHOD : R/W; bitpos: [7:4]; default: 0; + * Update method for RED (rising edge delay) active register. 0: immediate, when bit0 + * is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when + * bit3 is set to 1: disable the update + */ +#define MCPWM_DT0_RED_UPMETHOD 0x0000000FU +#define MCPWM_DT0_RED_UPMETHOD_M (MCPWM_DT0_RED_UPMETHOD_V << MCPWM_DT0_RED_UPMETHOD_S) +#define MCPWM_DT0_RED_UPMETHOD_V 0x0000000FU +#define MCPWM_DT0_RED_UPMETHOD_S 4 +/** MCPWM_DT0_DEB_MODE : R/W; bitpos: [8]; default: 0; + * S8 in table, dual-edge B mode, 0: fed/red take effect on different path separately, + * 1: fed/red take effect on B path, A out is in bypass or dulpB mode + */ +#define MCPWM_DT0_DEB_MODE (BIT(8)) +#define MCPWM_DT0_DEB_MODE_M (MCPWM_DT0_DEB_MODE_V << MCPWM_DT0_DEB_MODE_S) +#define MCPWM_DT0_DEB_MODE_V 0x00000001U +#define MCPWM_DT0_DEB_MODE_S 8 +/** MCPWM_DT0_A_OUTSWAP : R/W; bitpos: [9]; default: 0; + * S6 in table + */ +#define MCPWM_DT0_A_OUTSWAP (BIT(9)) +#define MCPWM_DT0_A_OUTSWAP_M (MCPWM_DT0_A_OUTSWAP_V << MCPWM_DT0_A_OUTSWAP_S) +#define MCPWM_DT0_A_OUTSWAP_V 0x00000001U +#define MCPWM_DT0_A_OUTSWAP_S 9 +/** MCPWM_DT0_B_OUTSWAP : R/W; bitpos: [10]; default: 0; + * S7 in table + */ +#define MCPWM_DT0_B_OUTSWAP (BIT(10)) +#define MCPWM_DT0_B_OUTSWAP_M (MCPWM_DT0_B_OUTSWAP_V << MCPWM_DT0_B_OUTSWAP_S) +#define MCPWM_DT0_B_OUTSWAP_V 0x00000001U +#define MCPWM_DT0_B_OUTSWAP_S 10 +/** MCPWM_DT0_RED_INSEL : R/W; bitpos: [11]; default: 0; + * S4 in table + */ +#define MCPWM_DT0_RED_INSEL (BIT(11)) +#define MCPWM_DT0_RED_INSEL_M (MCPWM_DT0_RED_INSEL_V << MCPWM_DT0_RED_INSEL_S) +#define MCPWM_DT0_RED_INSEL_V 0x00000001U +#define MCPWM_DT0_RED_INSEL_S 11 +/** MCPWM_DT0_FED_INSEL : R/W; bitpos: [12]; default: 0; + * S5 in table + */ +#define MCPWM_DT0_FED_INSEL (BIT(12)) +#define MCPWM_DT0_FED_INSEL_M (MCPWM_DT0_FED_INSEL_V << MCPWM_DT0_FED_INSEL_S) +#define MCPWM_DT0_FED_INSEL_V 0x00000001U +#define MCPWM_DT0_FED_INSEL_S 12 +/** MCPWM_DT0_RED_OUTINVERT : R/W; bitpos: [13]; default: 0; + * S2 in table + */ +#define MCPWM_DT0_RED_OUTINVERT (BIT(13)) +#define MCPWM_DT0_RED_OUTINVERT_M (MCPWM_DT0_RED_OUTINVERT_V << MCPWM_DT0_RED_OUTINVERT_S) +#define MCPWM_DT0_RED_OUTINVERT_V 0x00000001U +#define MCPWM_DT0_RED_OUTINVERT_S 13 +/** MCPWM_DT0_FED_OUTINVERT : R/W; bitpos: [14]; default: 0; + * S3 in table + */ +#define MCPWM_DT0_FED_OUTINVERT (BIT(14)) +#define MCPWM_DT0_FED_OUTINVERT_M (MCPWM_DT0_FED_OUTINVERT_V << MCPWM_DT0_FED_OUTINVERT_S) +#define MCPWM_DT0_FED_OUTINVERT_V 0x00000001U +#define MCPWM_DT0_FED_OUTINVERT_S 14 +/** MCPWM_DT0_A_OUTBYPASS : R/W; bitpos: [15]; default: 1; + * S1 in table + */ +#define MCPWM_DT0_A_OUTBYPASS (BIT(15)) +#define MCPWM_DT0_A_OUTBYPASS_M (MCPWM_DT0_A_OUTBYPASS_V << MCPWM_DT0_A_OUTBYPASS_S) +#define MCPWM_DT0_A_OUTBYPASS_V 0x00000001U +#define MCPWM_DT0_A_OUTBYPASS_S 15 +/** MCPWM_DT0_B_OUTBYPASS : R/W; bitpos: [16]; default: 1; + * S0 in table + */ +#define MCPWM_DT0_B_OUTBYPASS (BIT(16)) +#define MCPWM_DT0_B_OUTBYPASS_M (MCPWM_DT0_B_OUTBYPASS_V << MCPWM_DT0_B_OUTBYPASS_S) +#define MCPWM_DT0_B_OUTBYPASS_V 0x00000001U +#define MCPWM_DT0_B_OUTBYPASS_S 16 +/** MCPWM_DT0_CLK_SEL : R/W; bitpos: [17]; default: 0; + * Dead time clock selection. 0: PWM_clk, 1: PT_clk + */ +#define MCPWM_DT0_CLK_SEL (BIT(17)) +#define MCPWM_DT0_CLK_SEL_M (MCPWM_DT0_CLK_SEL_V << MCPWM_DT0_CLK_SEL_S) +#define MCPWM_DT0_CLK_SEL_V 0x00000001U +#define MCPWM_DT0_CLK_SEL_S 17 + +/** MCPWM_DT0_FED_CFG_REG register + * PWM generator 0 shadow register for falling edge delay (FED). + */ +#define MCPWM_DT0_FED_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0x5c) +/** MCPWM_DT0_FED : R/W; bitpos: [15:0]; default: 0; + * Shadow register for FED + */ +#define MCPWM_DT0_FED 0x0000FFFFU +#define MCPWM_DT0_FED_M (MCPWM_DT0_FED_V << MCPWM_DT0_FED_S) +#define MCPWM_DT0_FED_V 0x0000FFFFU +#define MCPWM_DT0_FED_S 0 + +/** MCPWM_DT0_RED_CFG_REG register + * PWM generator 0 shadow register for rising edge delay (RED). + */ +#define MCPWM_DT0_RED_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0x60) +/** MCPWM_DT0_RED : R/W; bitpos: [15:0]; default: 0; + * Shadow register for RED + */ +#define MCPWM_DT0_RED 0x0000FFFFU +#define MCPWM_DT0_RED_M (MCPWM_DT0_RED_V << MCPWM_DT0_RED_S) +#define MCPWM_DT0_RED_V 0x0000FFFFU +#define MCPWM_DT0_RED_S 0 + +/** MCPWM_CARRIER0_CFG_REG register + * PWM generator 0 carrier enable and configuratoin + */ +#define MCPWM_CARRIER0_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0x64) +/** MCPWM_CARRIER0_EN : R/W; bitpos: [0]; default: 0; + * When set, carrier0 function is enabled. When cleared, carrier0 is bypassed + */ +#define MCPWM_CARRIER0_EN (BIT(0)) +#define MCPWM_CARRIER0_EN_M (MCPWM_CARRIER0_EN_V << MCPWM_CARRIER0_EN_S) +#define MCPWM_CARRIER0_EN_V 0x00000001U +#define MCPWM_CARRIER0_EN_S 0 +/** MCPWM_CARRIER0_PRESCALE : R/W; bitpos: [4:1]; default: 0; + * PWM carrier0 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk * + * (PWM_CARRIER0_PRESCALE + 1) + */ +#define MCPWM_CARRIER0_PRESCALE 0x0000000FU +#define MCPWM_CARRIER0_PRESCALE_M (MCPWM_CARRIER0_PRESCALE_V << MCPWM_CARRIER0_PRESCALE_S) +#define MCPWM_CARRIER0_PRESCALE_V 0x0000000FU +#define MCPWM_CARRIER0_PRESCALE_S 1 +/** MCPWM_CARRIER0_DUTY : R/W; bitpos: [7:5]; default: 0; + * carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8 + */ +#define MCPWM_CARRIER0_DUTY 0x00000007U +#define MCPWM_CARRIER0_DUTY_M (MCPWM_CARRIER0_DUTY_V << MCPWM_CARRIER0_DUTY_S) +#define MCPWM_CARRIER0_DUTY_V 0x00000007U +#define MCPWM_CARRIER0_DUTY_S 5 +/** MCPWM_CARRIER0_OSHTWTH : R/W; bitpos: [11:8]; default: 0; + * width of the first pulse in number of periods of the carrier + */ +#define MCPWM_CARRIER0_OSHTWTH 0x0000000FU +#define MCPWM_CARRIER0_OSHTWTH_M (MCPWM_CARRIER0_OSHTWTH_V << MCPWM_CARRIER0_OSHTWTH_S) +#define MCPWM_CARRIER0_OSHTWTH_V 0x0000000FU +#define MCPWM_CARRIER0_OSHTWTH_S 8 +/** MCPWM_CARRIER0_OUT_INVERT : R/W; bitpos: [12]; default: 0; + * when set, invert the output of PWM0A and PWM0B for this submodule + */ +#define MCPWM_CARRIER0_OUT_INVERT (BIT(12)) +#define MCPWM_CARRIER0_OUT_INVERT_M (MCPWM_CARRIER0_OUT_INVERT_V << MCPWM_CARRIER0_OUT_INVERT_S) +#define MCPWM_CARRIER0_OUT_INVERT_V 0x00000001U +#define MCPWM_CARRIER0_OUT_INVERT_S 12 +/** MCPWM_CARRIER0_IN_INVERT : R/W; bitpos: [13]; default: 0; + * when set, invert the input of PWM0A and PWM0B for this submodule + */ +#define MCPWM_CARRIER0_IN_INVERT (BIT(13)) +#define MCPWM_CARRIER0_IN_INVERT_M (MCPWM_CARRIER0_IN_INVERT_V << MCPWM_CARRIER0_IN_INVERT_S) +#define MCPWM_CARRIER0_IN_INVERT_V 0x00000001U +#define MCPWM_CARRIER0_IN_INVERT_S 13 + +/** MCPWM_FH0_CFG0_REG register + * Actions on PWM0A and PWM0B trip events + */ +#define MCPWM_FH0_CFG0_REG(i) (DR_REG_MCPWM_BASE(i) + 0x68) +/** MCPWM_FH0_SW_CBC : R/W; bitpos: [0]; default: 0; + * Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable + */ +#define MCPWM_FH0_SW_CBC (BIT(0)) +#define MCPWM_FH0_SW_CBC_M (MCPWM_FH0_SW_CBC_V << MCPWM_FH0_SW_CBC_S) +#define MCPWM_FH0_SW_CBC_V 0x00000001U +#define MCPWM_FH0_SW_CBC_S 0 +/** MCPWM_FH0_F2_CBC : R/W; bitpos: [1]; default: 0; + * fault_event2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + */ +#define MCPWM_FH0_F2_CBC (BIT(1)) +#define MCPWM_FH0_F2_CBC_M (MCPWM_FH0_F2_CBC_V << MCPWM_FH0_F2_CBC_S) +#define MCPWM_FH0_F2_CBC_V 0x00000001U +#define MCPWM_FH0_F2_CBC_S 1 +/** MCPWM_FH0_F1_CBC : R/W; bitpos: [2]; default: 0; + * fault_event1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + */ +#define MCPWM_FH0_F1_CBC (BIT(2)) +#define MCPWM_FH0_F1_CBC_M (MCPWM_FH0_F1_CBC_V << MCPWM_FH0_F1_CBC_S) +#define MCPWM_FH0_F1_CBC_V 0x00000001U +#define MCPWM_FH0_F1_CBC_S 2 +/** MCPWM_FH0_F0_CBC : R/W; bitpos: [3]; default: 0; + * fault_event0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + */ +#define MCPWM_FH0_F0_CBC (BIT(3)) +#define MCPWM_FH0_F0_CBC_M (MCPWM_FH0_F0_CBC_V << MCPWM_FH0_F0_CBC_S) +#define MCPWM_FH0_F0_CBC_V 0x00000001U +#define MCPWM_FH0_F0_CBC_S 3 +/** MCPWM_FH0_SW_OST : R/W; bitpos: [4]; default: 0; + * Enable register for software force one-shot mode action. 0: disable, 1: enable + */ +#define MCPWM_FH0_SW_OST (BIT(4)) +#define MCPWM_FH0_SW_OST_M (MCPWM_FH0_SW_OST_V << MCPWM_FH0_SW_OST_S) +#define MCPWM_FH0_SW_OST_V 0x00000001U +#define MCPWM_FH0_SW_OST_S 4 +/** MCPWM_FH0_F2_OST : R/W; bitpos: [5]; default: 0; + * fault_event2 will trigger one-shot mode action. 0: disable, 1: enable + */ +#define MCPWM_FH0_F2_OST (BIT(5)) +#define MCPWM_FH0_F2_OST_M (MCPWM_FH0_F2_OST_V << MCPWM_FH0_F2_OST_S) +#define MCPWM_FH0_F2_OST_V 0x00000001U +#define MCPWM_FH0_F2_OST_S 5 +/** MCPWM_FH0_F1_OST : R/W; bitpos: [6]; default: 0; + * fault_event1 will trigger one-shot mode action. 0: disable, 1: enable + */ +#define MCPWM_FH0_F1_OST (BIT(6)) +#define MCPWM_FH0_F1_OST_M (MCPWM_FH0_F1_OST_V << MCPWM_FH0_F1_OST_S) +#define MCPWM_FH0_F1_OST_V 0x00000001U +#define MCPWM_FH0_F1_OST_S 6 +/** MCPWM_FH0_F0_OST : R/W; bitpos: [7]; default: 0; + * fault_event0 will trigger one-shot mode action. 0: disable, 1: enable + */ +#define MCPWM_FH0_F0_OST (BIT(7)) +#define MCPWM_FH0_F0_OST_M (MCPWM_FH0_F0_OST_V << MCPWM_FH0_F0_OST_S) +#define MCPWM_FH0_F0_OST_V 0x00000001U +#define MCPWM_FH0_F0_OST_S 7 +/** MCPWM_FH0_A_CBC_D : R/W; bitpos: [9:8]; default: 0; + * Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is + * decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_FH0_A_CBC_D 0x00000003U +#define MCPWM_FH0_A_CBC_D_M (MCPWM_FH0_A_CBC_D_V << MCPWM_FH0_A_CBC_D_S) +#define MCPWM_FH0_A_CBC_D_V 0x00000003U +#define MCPWM_FH0_A_CBC_D_S 8 +/** MCPWM_FH0_A_CBC_U : R/W; bitpos: [11:10]; default: 0; + * Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is + * increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_FH0_A_CBC_U 0x00000003U +#define MCPWM_FH0_A_CBC_U_M (MCPWM_FH0_A_CBC_U_V << MCPWM_FH0_A_CBC_U_S) +#define MCPWM_FH0_A_CBC_U_V 0x00000003U +#define MCPWM_FH0_A_CBC_U_S 10 +/** MCPWM_FH0_A_OST_D : R/W; bitpos: [13:12]; default: 0; + * One-shot mode action on PWM0A when fault event occurs and timer is decreasing. 0: + * do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_FH0_A_OST_D 0x00000003U +#define MCPWM_FH0_A_OST_D_M (MCPWM_FH0_A_OST_D_V << MCPWM_FH0_A_OST_D_S) +#define MCPWM_FH0_A_OST_D_V 0x00000003U +#define MCPWM_FH0_A_OST_D_S 12 +/** MCPWM_FH0_A_OST_U : R/W; bitpos: [15:14]; default: 0; + * One-shot mode action on PWM0A when fault event occurs and timer is increasing. 0: + * do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_FH0_A_OST_U 0x00000003U +#define MCPWM_FH0_A_OST_U_M (MCPWM_FH0_A_OST_U_V << MCPWM_FH0_A_OST_U_S) +#define MCPWM_FH0_A_OST_U_V 0x00000003U +#define MCPWM_FH0_A_OST_U_S 14 +/** MCPWM_FH0_B_CBC_D : R/W; bitpos: [17:16]; default: 0; + * Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is + * decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_FH0_B_CBC_D 0x00000003U +#define MCPWM_FH0_B_CBC_D_M (MCPWM_FH0_B_CBC_D_V << MCPWM_FH0_B_CBC_D_S) +#define MCPWM_FH0_B_CBC_D_V 0x00000003U +#define MCPWM_FH0_B_CBC_D_S 16 +/** MCPWM_FH0_B_CBC_U : R/W; bitpos: [19:18]; default: 0; + * Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is + * increasing. 0: do nothing,1: force low, 2: force high, 3: toggle + */ +#define MCPWM_FH0_B_CBC_U 0x00000003U +#define MCPWM_FH0_B_CBC_U_M (MCPWM_FH0_B_CBC_U_V << MCPWM_FH0_B_CBC_U_S) +#define MCPWM_FH0_B_CBC_U_V 0x00000003U +#define MCPWM_FH0_B_CBC_U_S 18 +/** MCPWM_FH0_B_OST_D : R/W; bitpos: [21:20]; default: 0; + * One-shot mode action on PWM0B when fault event occurs and timer is decreasing. 0: + * do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_FH0_B_OST_D 0x00000003U +#define MCPWM_FH0_B_OST_D_M (MCPWM_FH0_B_OST_D_V << MCPWM_FH0_B_OST_D_S) +#define MCPWM_FH0_B_OST_D_V 0x00000003U +#define MCPWM_FH0_B_OST_D_S 20 +/** MCPWM_FH0_B_OST_U : R/W; bitpos: [23:22]; default: 0; + * One-shot mode action on PWM0B when fault event occurs and timer is increasing. 0: + * do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_FH0_B_OST_U 0x00000003U +#define MCPWM_FH0_B_OST_U_M (MCPWM_FH0_B_OST_U_V << MCPWM_FH0_B_OST_U_S) +#define MCPWM_FH0_B_OST_U_V 0x00000003U +#define MCPWM_FH0_B_OST_U_S 22 + +/** MCPWM_FH0_CFG1_REG register + * Software triggers for fault handler actions + */ +#define MCPWM_FH0_CFG1_REG(i) (DR_REG_MCPWM_BASE(i) + 0x6c) +/** MCPWM_FH0_CLR_OST : R/W; bitpos: [0]; default: 0; + * a rising edge will clear on going one-shot mode action + */ +#define MCPWM_FH0_CLR_OST (BIT(0)) +#define MCPWM_FH0_CLR_OST_M (MCPWM_FH0_CLR_OST_V << MCPWM_FH0_CLR_OST_S) +#define MCPWM_FH0_CLR_OST_V 0x00000001U +#define MCPWM_FH0_CLR_OST_S 0 +/** MCPWM_FH0_CBCPULSE : R/W; bitpos: [2:1]; default: 0; + * cycle-by-cycle mode action refresh moment selection. When bit0 is set to 1: TEZ, + * when bit1 is set to 1:TEP, when bit0 and bit1 both set to 0: stop refresh, when + * bit0 and bit1 both set to 1: refresh at TEP/TEZ + */ +#define MCPWM_FH0_CBCPULSE 0x00000003U +#define MCPWM_FH0_CBCPULSE_M (MCPWM_FH0_CBCPULSE_V << MCPWM_FH0_CBCPULSE_S) +#define MCPWM_FH0_CBCPULSE_V 0x00000003U +#define MCPWM_FH0_CBCPULSE_S 1 +/** MCPWM_FH0_FORCE_CBC : R/W; bitpos: [3]; default: 0; + * a toggle trigger a cycle-by-cycle mode action + */ +#define MCPWM_FH0_FORCE_CBC (BIT(3)) +#define MCPWM_FH0_FORCE_CBC_M (MCPWM_FH0_FORCE_CBC_V << MCPWM_FH0_FORCE_CBC_S) +#define MCPWM_FH0_FORCE_CBC_V 0x00000001U +#define MCPWM_FH0_FORCE_CBC_S 3 +/** MCPWM_FH0_FORCE_OST : R/W; bitpos: [4]; default: 0; + * a toggle (software negate its value) triggers a one-shot mode action + */ +#define MCPWM_FH0_FORCE_OST (BIT(4)) +#define MCPWM_FH0_FORCE_OST_M (MCPWM_FH0_FORCE_OST_V << MCPWM_FH0_FORCE_OST_S) +#define MCPWM_FH0_FORCE_OST_V 0x00000001U +#define MCPWM_FH0_FORCE_OST_S 4 + +/** MCPWM_FH0_STATUS_REG register + * Status of fault events. + */ +#define MCPWM_FH0_STATUS_REG(i) (DR_REG_MCPWM_BASE(i) + 0x70) +/** MCPWM_FH0_CBC_ON : RO; bitpos: [0]; default: 0; + * Set and reset by hardware. If set, a cycle-by-cycle mode action is on going + */ +#define MCPWM_FH0_CBC_ON (BIT(0)) +#define MCPWM_FH0_CBC_ON_M (MCPWM_FH0_CBC_ON_V << MCPWM_FH0_CBC_ON_S) +#define MCPWM_FH0_CBC_ON_V 0x00000001U +#define MCPWM_FH0_CBC_ON_S 0 +/** MCPWM_FH0_OST_ON : RO; bitpos: [1]; default: 0; + * Set and reset by hardware. If set, an one-shot mode action is on going + */ +#define MCPWM_FH0_OST_ON (BIT(1)) +#define MCPWM_FH0_OST_ON_M (MCPWM_FH0_OST_ON_V << MCPWM_FH0_OST_ON_S) +#define MCPWM_FH0_OST_ON_V 0x00000001U +#define MCPWM_FH0_OST_ON_S 1 + +/** MCPWM_GEN1_STMP_CFG_REG register + * Transfer status and update method for time stamp registers A and B + */ +#define MCPWM_GEN1_STMP_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0x74) +/** MCPWM_GEN1_A_UPMETHOD : R/W; bitpos: [3:0]; default: 0; + * Update method for PWM generator 1 time stamp A's active register. When all bits are + * set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when + * bit2 is set to 1: sync, when bit3 is set to 1: disable the update. + */ +#define MCPWM_GEN1_A_UPMETHOD 0x0000000FU +#define MCPWM_GEN1_A_UPMETHOD_M (MCPWM_GEN1_A_UPMETHOD_V << MCPWM_GEN1_A_UPMETHOD_S) +#define MCPWM_GEN1_A_UPMETHOD_V 0x0000000FU +#define MCPWM_GEN1_A_UPMETHOD_S 0 +/** MCPWM_GEN1_B_UPMETHOD : R/W; bitpos: [7:4]; default: 0; + * Update method for PWM generator 1 time stamp B's active register. When all bits are + * set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when + * bit2 is set to 1: sync, when bit3 is set to 1: disable the update. + */ +#define MCPWM_GEN1_B_UPMETHOD 0x0000000FU +#define MCPWM_GEN1_B_UPMETHOD_M (MCPWM_GEN1_B_UPMETHOD_V << MCPWM_GEN1_B_UPMETHOD_S) +#define MCPWM_GEN1_B_UPMETHOD_V 0x0000000FU +#define MCPWM_GEN1_B_UPMETHOD_S 4 +/** MCPWM_GEN1_A_SHDW_FULL : R/W/WTC/SC; bitpos: [8]; default: 0; + * Set and reset by hardware. If set, PWM generator 1 time stamp A's shadow reg is + * filled and waiting to be transferred to A's active reg. If cleared, A's active reg + * has been updated with shadow register latest value + */ +#define MCPWM_GEN1_A_SHDW_FULL (BIT(8)) +#define MCPWM_GEN1_A_SHDW_FULL_M (MCPWM_GEN1_A_SHDW_FULL_V << MCPWM_GEN1_A_SHDW_FULL_S) +#define MCPWM_GEN1_A_SHDW_FULL_V 0x00000001U +#define MCPWM_GEN1_A_SHDW_FULL_S 8 +/** MCPWM_GEN1_B_SHDW_FULL : R/W/WTC/SC; bitpos: [9]; default: 0; + * Set and reset by hardware. If set, PWM generator 1 time stamp B's shadow reg is + * filled and waiting to be transferred to B's active reg. If cleared, B's active reg + * has been updated with shadow register latest value + */ +#define MCPWM_GEN1_B_SHDW_FULL (BIT(9)) +#define MCPWM_GEN1_B_SHDW_FULL_M (MCPWM_GEN1_B_SHDW_FULL_V << MCPWM_GEN1_B_SHDW_FULL_S) +#define MCPWM_GEN1_B_SHDW_FULL_V 0x00000001U +#define MCPWM_GEN1_B_SHDW_FULL_S 9 + +/** MCPWM_GEN1_TSTMP_A_REG register + * PWM generator 1 shadow register for timer stamp A. + */ +#define MCPWM_GEN1_TSTMP_A_REG(i) (DR_REG_MCPWM_BASE(i) + 0x78) +/** MCPWM_GEN1_A : R/W; bitpos: [15:0]; default: 0; + * PWM generator 1 time stamp A's shadow register + */ +#define MCPWM_GEN1_A 0x0000FFFFU +#define MCPWM_GEN1_A_M (MCPWM_GEN1_A_V << MCPWM_GEN1_A_S) +#define MCPWM_GEN1_A_V 0x0000FFFFU +#define MCPWM_GEN1_A_S 0 + +/** MCPWM_GEN1_TSTMP_B_REG register + * PWM generator 1 shadow register for timer stamp B. + */ +#define MCPWM_GEN1_TSTMP_B_REG(i) (DR_REG_MCPWM_BASE(i) + 0x7c) +/** MCPWM_GEN1_B : R/W; bitpos: [15:0]; default: 0; + * PWM generator 1 time stamp B's shadow register + */ +#define MCPWM_GEN1_B 0x0000FFFFU +#define MCPWM_GEN1_B_M (MCPWM_GEN1_B_V << MCPWM_GEN1_B_S) +#define MCPWM_GEN1_B_V 0x0000FFFFU +#define MCPWM_GEN1_B_S 0 + +/** MCPWM_GEN1_CFG0_REG register + * PWM generator 1 event T0 and T1 handling + */ +#define MCPWM_GEN1_CFG0_REG(i) (DR_REG_MCPWM_BASE(i) + 0x80) +/** MCPWM_GEN1_CFG_UPMETHOD : R/W; bitpos: [3:0]; default: 0; + * Update method for PWM generator 1's active register of configuration. When all bits + * are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to + * 1:sync;when bit3 is set to 1:disable the update. + */ +#define MCPWM_GEN1_CFG_UPMETHOD 0x0000000FU +#define MCPWM_GEN1_CFG_UPMETHOD_M (MCPWM_GEN1_CFG_UPMETHOD_V << MCPWM_GEN1_CFG_UPMETHOD_S) +#define MCPWM_GEN1_CFG_UPMETHOD_V 0x0000000FU #define MCPWM_GEN1_CFG_UPMETHOD_S 0 +/** MCPWM_GEN1_T0_SEL : R/W; bitpos: [6:4]; default: 0; + * Source selection for PWM generator 1 event_t0, take effect immediately, 0: + * fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none + */ +#define MCPWM_GEN1_T0_SEL 0x00000007U +#define MCPWM_GEN1_T0_SEL_M (MCPWM_GEN1_T0_SEL_V << MCPWM_GEN1_T0_SEL_S) +#define MCPWM_GEN1_T0_SEL_V 0x00000007U +#define MCPWM_GEN1_T0_SEL_S 4 +/** MCPWM_GEN1_T1_SEL : R/W; bitpos: [9:7]; default: 0; + * Source selection for PWM generator 1 event_t1, take effect immediately, 0: + * fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none + */ +#define MCPWM_GEN1_T1_SEL 0x00000007U +#define MCPWM_GEN1_T1_SEL_M (MCPWM_GEN1_T1_SEL_V << MCPWM_GEN1_T1_SEL_S) +#define MCPWM_GEN1_T1_SEL_V 0x00000007U +#define MCPWM_GEN1_T1_SEL_S 7 -#define MCPWM_GEN1_FORCE_REG(i) (REG_MCPWM_BASE(i) + 0x84) -/* MCPWM_GEN1_B_NCIFORCE_MODE : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ -/*description: 0: disabled, 1: low, 2: high, 3: disabled.*/ -#define MCPWM_GEN1_B_NCIFORCE_MODE 0x00000003 -#define MCPWM_GEN1_B_NCIFORCE_MODE_M ((MCPWM_GEN1_B_NCIFORCE_MODE_V)<<(MCPWM_GEN1_B_NCIFORCE_MODE_S)) -#define MCPWM_GEN1_B_NCIFORCE_MODE_V 0x3 -#define MCPWM_GEN1_B_NCIFORCE_MODE_S 14 -/* MCPWM_GEN1_B_NCIFORCE : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: non-continuous immediate sw force, a toggle will trigger a force event.*/ -#define MCPWM_GEN1_B_NCIFORCE (BIT(13)) -#define MCPWM_GEN1_B_NCIFORCE_M (BIT(13)) -#define MCPWM_GEN1_B_NCIFORCE_V 0x1 -#define MCPWM_GEN1_B_NCIFORCE_S 13 -/* MCPWM_GEN1_A_NCIFORCE_MODE : R/W ;bitpos:[12:11] ;default: 2'd0 ; */ -/*description: 0: disabled, 1: low, 2: high, 3: disabled.*/ -#define MCPWM_GEN1_A_NCIFORCE_MODE 0x00000003 -#define MCPWM_GEN1_A_NCIFORCE_MODE_M ((MCPWM_GEN1_A_NCIFORCE_MODE_V)<<(MCPWM_GEN1_A_NCIFORCE_MODE_S)) -#define MCPWM_GEN1_A_NCIFORCE_MODE_V 0x3 -#define MCPWM_GEN1_A_NCIFORCE_MODE_S 11 -/* MCPWM_GEN1_A_NCIFORCE : R/W ;bitpos:[10] ;default: 1'd0 ; */ -/*description: non-continuous immediate sw force, a toggle will trigger a force event.*/ +/** MCPWM_GEN1_FORCE_REG register + * Permissives to force PWM1A and PWM1B outputs by software + */ +#define MCPWM_GEN1_FORCE_REG(i) (DR_REG_MCPWM_BASE(i) + 0x84) +/** MCPWM_GEN1_CNTUFORCE_UPMETHOD : R/W; bitpos: [5:0]; default: 32; + * Updating method for continuous software force of PWM generator 1. When all bits are + * set to 0: immediately, when bit0 is set to 1: TEZ,when bit1 is set to 1: TEP, when + * bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync, + * when bit5 is set to 1: disable update. (TEA/B here and below means an event + * generated when the timer's value equals to that of register A/B.) + */ +#define MCPWM_GEN1_CNTUFORCE_UPMETHOD 0x0000003FU +#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_M (MCPWM_GEN1_CNTUFORCE_UPMETHOD_V << MCPWM_GEN1_CNTUFORCE_UPMETHOD_S) +#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_V 0x0000003FU +#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_S 0 +/** MCPWM_GEN1_A_CNTUFORCE_MODE : R/W; bitpos: [7:6]; default: 0; + * Continuous software force mode for PWM1A. 0: disabled, 1: low, 2: high, 3: disabled + */ +#define MCPWM_GEN1_A_CNTUFORCE_MODE 0x00000003U +#define MCPWM_GEN1_A_CNTUFORCE_MODE_M (MCPWM_GEN1_A_CNTUFORCE_MODE_V << MCPWM_GEN1_A_CNTUFORCE_MODE_S) +#define MCPWM_GEN1_A_CNTUFORCE_MODE_V 0x00000003U +#define MCPWM_GEN1_A_CNTUFORCE_MODE_S 6 +/** MCPWM_GEN1_B_CNTUFORCE_MODE : R/W; bitpos: [9:8]; default: 0; + * Continuous software force mode for PWM1B. 0: disabled, 1: low, 2: high, 3: disabled + */ +#define MCPWM_GEN1_B_CNTUFORCE_MODE 0x00000003U +#define MCPWM_GEN1_B_CNTUFORCE_MODE_M (MCPWM_GEN1_B_CNTUFORCE_MODE_V << MCPWM_GEN1_B_CNTUFORCE_MODE_S) +#define MCPWM_GEN1_B_CNTUFORCE_MODE_V 0x00000003U +#define MCPWM_GEN1_B_CNTUFORCE_MODE_S 8 +/** MCPWM_GEN1_A_NCIFORCE : R/W; bitpos: [10]; default: 0; + * Trigger of non-continuous immediate software-force event for PWM1A, a toggle will + * trigger a force event. + */ #define MCPWM_GEN1_A_NCIFORCE (BIT(10)) -#define MCPWM_GEN1_A_NCIFORCE_M (BIT(10)) -#define MCPWM_GEN1_A_NCIFORCE_V 0x1 +#define MCPWM_GEN1_A_NCIFORCE_M (MCPWM_GEN1_A_NCIFORCE_V << MCPWM_GEN1_A_NCIFORCE_S) +#define MCPWM_GEN1_A_NCIFORCE_V 0x00000001U #define MCPWM_GEN1_A_NCIFORCE_S 10 -/* MCPWM_GEN1_B_CNTUFORCE_MODE : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ -/*description: 0: disabled, 1: low, 2: high, 3: disabled.*/ -#define MCPWM_GEN1_B_CNTUFORCE_MODE 0x00000003 -#define MCPWM_GEN1_B_CNTUFORCE_MODE_M ((MCPWM_GEN1_B_CNTUFORCE_MODE_V)<<(MCPWM_GEN1_B_CNTUFORCE_MODE_S)) -#define MCPWM_GEN1_B_CNTUFORCE_MODE_V 0x3 -#define MCPWM_GEN1_B_CNTUFORCE_MODE_S 8 -/* MCPWM_GEN1_A_CNTUFORCE_MODE : R/W ;bitpos:[7:6] ;default: 2'd0 ; */ -/*description: 0: disabled, 1: low, 2: high, 3: disabled.*/ -#define MCPWM_GEN1_A_CNTUFORCE_MODE 0x00000003 -#define MCPWM_GEN1_A_CNTUFORCE_MODE_M ((MCPWM_GEN1_A_CNTUFORCE_MODE_V)<<(MCPWM_GEN1_A_CNTUFORCE_MODE_S)) -#define MCPWM_GEN1_A_CNTUFORCE_MODE_V 0x3 -#define MCPWM_GEN1_A_CNTUFORCE_MODE_S 6 -/* MCPWM_GEN1_CNTUFORCE_UPMETHOD : R/W ;bitpos:[5:0] ;default: 6'h20 ; */ -/*description: 0: immediate, bit0: tez, bit1: tep, bit2: tea, bit3: teb, bit4: sync, bit5: free -ze.*/ -#define MCPWM_GEN1_CNTUFORCE_UPMETHOD 0x0000003F -#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_M ((MCPWM_GEN1_CNTUFORCE_UPMETHOD_V)<<(MCPWM_GEN1_CNTUFORCE_UPMETHOD_S)) -#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_V 0x3F -#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_S 0 +/** MCPWM_GEN1_A_NCIFORCE_MODE : R/W; bitpos: [12:11]; default: 0; + * non-continuous immediate software force mode for PWM1A, 0: disabled, 1: low, 2: + * high, 3: disabled + */ +#define MCPWM_GEN1_A_NCIFORCE_MODE 0x00000003U +#define MCPWM_GEN1_A_NCIFORCE_MODE_M (MCPWM_GEN1_A_NCIFORCE_MODE_V << MCPWM_GEN1_A_NCIFORCE_MODE_S) +#define MCPWM_GEN1_A_NCIFORCE_MODE_V 0x00000003U +#define MCPWM_GEN1_A_NCIFORCE_MODE_S 11 +/** MCPWM_GEN1_B_NCIFORCE : R/W; bitpos: [13]; default: 0; + * Trigger of non-continuous immediate software-force event for PWM1B, a toggle will + * trigger a force event. + */ +#define MCPWM_GEN1_B_NCIFORCE (BIT(13)) +#define MCPWM_GEN1_B_NCIFORCE_M (MCPWM_GEN1_B_NCIFORCE_V << MCPWM_GEN1_B_NCIFORCE_S) +#define MCPWM_GEN1_B_NCIFORCE_V 0x00000001U +#define MCPWM_GEN1_B_NCIFORCE_S 13 +/** MCPWM_GEN1_B_NCIFORCE_MODE : R/W; bitpos: [15:14]; default: 0; + * non-continuous immediate software force mode for PWM1B, 0: disabled, 1: low, 2: + * high, 3: disabled + */ +#define MCPWM_GEN1_B_NCIFORCE_MODE 0x00000003U +#define MCPWM_GEN1_B_NCIFORCE_MODE_M (MCPWM_GEN1_B_NCIFORCE_MODE_V << MCPWM_GEN1_B_NCIFORCE_MODE_S) +#define MCPWM_GEN1_B_NCIFORCE_MODE_V 0x00000003U +#define MCPWM_GEN1_B_NCIFORCE_MODE_S 14 -#define MCPWM_GEN1_A_REG(i) (REG_MCPWM_BASE(i) + 0x88) -/* MCPWM_GEN1_A_DT1 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ -/*description: 0: no change, 1: low, 2: high, 3: toggle.*/ -#define MCPWM_GEN1_A_DT1 0x00000003 -#define MCPWM_GEN1_A_DT1_M ((MCPWM_GEN1_A_DT1_V)<<(MCPWM_GEN1_A_DT1_S)) -#define MCPWM_GEN1_A_DT1_V 0x3 -#define MCPWM_GEN1_A_DT1_S 22 -/* MCPWM_GEN1_A_DT0 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ -/*description: .*/ -#define MCPWM_GEN1_A_DT0 0x00000003 -#define MCPWM_GEN1_A_DT0_M ((MCPWM_GEN1_A_DT0_V)<<(MCPWM_GEN1_A_DT0_S)) -#define MCPWM_GEN1_A_DT0_V 0x3 -#define MCPWM_GEN1_A_DT0_S 20 -/* MCPWM_GEN1_A_DTEB : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ -/*description: .*/ -#define MCPWM_GEN1_A_DTEB 0x00000003 -#define MCPWM_GEN1_A_DTEB_M ((MCPWM_GEN1_A_DTEB_V)<<(MCPWM_GEN1_A_DTEB_S)) -#define MCPWM_GEN1_A_DTEB_V 0x3 -#define MCPWM_GEN1_A_DTEB_S 18 -/* MCPWM_GEN1_A_DTEA : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ -/*description: .*/ -#define MCPWM_GEN1_A_DTEA 0x00000003 -#define MCPWM_GEN1_A_DTEA_M ((MCPWM_GEN1_A_DTEA_V)<<(MCPWM_GEN1_A_DTEA_S)) -#define MCPWM_GEN1_A_DTEA_V 0x3 -#define MCPWM_GEN1_A_DTEA_S 16 -/* MCPWM_GEN1_A_DTEP : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ -/*description: .*/ -#define MCPWM_GEN1_A_DTEP 0x00000003 -#define MCPWM_GEN1_A_DTEP_M ((MCPWM_GEN1_A_DTEP_V)<<(MCPWM_GEN1_A_DTEP_S)) -#define MCPWM_GEN1_A_DTEP_V 0x3 -#define MCPWM_GEN1_A_DTEP_S 14 -/* MCPWM_GEN1_A_DTEZ : R/W ;bitpos:[13:12] ;default: 2'd0 ; */ -/*description: .*/ -#define MCPWM_GEN1_A_DTEZ 0x00000003 -#define MCPWM_GEN1_A_DTEZ_M ((MCPWM_GEN1_A_DTEZ_V)<<(MCPWM_GEN1_A_DTEZ_S)) -#define MCPWM_GEN1_A_DTEZ_V 0x3 -#define MCPWM_GEN1_A_DTEZ_S 12 -/* MCPWM_GEN1_A_UT1 : R/W ;bitpos:[11:10] ;default: 2'd0 ; */ -/*description: .*/ -#define MCPWM_GEN1_A_UT1 0x00000003 -#define MCPWM_GEN1_A_UT1_M ((MCPWM_GEN1_A_UT1_V)<<(MCPWM_GEN1_A_UT1_S)) -#define MCPWM_GEN1_A_UT1_V 0x3 -#define MCPWM_GEN1_A_UT1_S 10 -/* MCPWM_GEN1_A_UT0 : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ -/*description: .*/ -#define MCPWM_GEN1_A_UT0 0x00000003 -#define MCPWM_GEN1_A_UT0_M ((MCPWM_GEN1_A_UT0_V)<<(MCPWM_GEN1_A_UT0_S)) -#define MCPWM_GEN1_A_UT0_V 0x3 -#define MCPWM_GEN1_A_UT0_S 8 -/* MCPWM_GEN1_A_UTEB : R/W ;bitpos:[7:6] ;default: 2'd0 ; */ -/*description: .*/ -#define MCPWM_GEN1_A_UTEB 0x00000003 -#define MCPWM_GEN1_A_UTEB_M ((MCPWM_GEN1_A_UTEB_V)<<(MCPWM_GEN1_A_UTEB_S)) -#define MCPWM_GEN1_A_UTEB_V 0x3 -#define MCPWM_GEN1_A_UTEB_S 6 -/* MCPWM_GEN1_A_UTEA : R/W ;bitpos:[5:4] ;default: 2'd0 ; */ -/*description: .*/ -#define MCPWM_GEN1_A_UTEA 0x00000003 -#define MCPWM_GEN1_A_UTEA_M ((MCPWM_GEN1_A_UTEA_V)<<(MCPWM_GEN1_A_UTEA_S)) -#define MCPWM_GEN1_A_UTEA_V 0x3 -#define MCPWM_GEN1_A_UTEA_S 4 -/* MCPWM_GEN1_A_UTEP : R/W ;bitpos:[3:2] ;default: 2'd0 ; */ -/*description: .*/ -#define MCPWM_GEN1_A_UTEP 0x00000003 -#define MCPWM_GEN1_A_UTEP_M ((MCPWM_GEN1_A_UTEP_V)<<(MCPWM_GEN1_A_UTEP_S)) -#define MCPWM_GEN1_A_UTEP_V 0x3 -#define MCPWM_GEN1_A_UTEP_S 2 -/* MCPWM_GEN1_A_UTEZ : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: .*/ -#define MCPWM_GEN1_A_UTEZ 0x00000003 -#define MCPWM_GEN1_A_UTEZ_M ((MCPWM_GEN1_A_UTEZ_V)<<(MCPWM_GEN1_A_UTEZ_S)) -#define MCPWM_GEN1_A_UTEZ_V 0x3 +/** MCPWM_GEN1_A_REG register + * Actions triggered by events on PWM1A + */ +#define MCPWM_GEN1_A_REG(i) (DR_REG_MCPWM_BASE(i) + 0x88) +/** MCPWM_GEN1_A_UTEZ : R/W; bitpos: [1:0]; default: 0; + * Action on PWM1A triggered by event TEZ when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN1_A_UTEZ 0x00000003U +#define MCPWM_GEN1_A_UTEZ_M (MCPWM_GEN1_A_UTEZ_V << MCPWM_GEN1_A_UTEZ_S) +#define MCPWM_GEN1_A_UTEZ_V 0x00000003U #define MCPWM_GEN1_A_UTEZ_S 0 +/** MCPWM_GEN1_A_UTEP : R/W; bitpos: [3:2]; default: 0; + * Action on PWM1A triggered by event TEP when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN1_A_UTEP 0x00000003U +#define MCPWM_GEN1_A_UTEP_M (MCPWM_GEN1_A_UTEP_V << MCPWM_GEN1_A_UTEP_S) +#define MCPWM_GEN1_A_UTEP_V 0x00000003U +#define MCPWM_GEN1_A_UTEP_S 2 +/** MCPWM_GEN1_A_UTEA : R/W; bitpos: [5:4]; default: 0; + * Action on PWM1A triggered by event TEA when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN1_A_UTEA 0x00000003U +#define MCPWM_GEN1_A_UTEA_M (MCPWM_GEN1_A_UTEA_V << MCPWM_GEN1_A_UTEA_S) +#define MCPWM_GEN1_A_UTEA_V 0x00000003U +#define MCPWM_GEN1_A_UTEA_S 4 +/** MCPWM_GEN1_A_UTEB : R/W; bitpos: [7:6]; default: 0; + * Action on PWM1A triggered by event TEB when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN1_A_UTEB 0x00000003U +#define MCPWM_GEN1_A_UTEB_M (MCPWM_GEN1_A_UTEB_V << MCPWM_GEN1_A_UTEB_S) +#define MCPWM_GEN1_A_UTEB_V 0x00000003U +#define MCPWM_GEN1_A_UTEB_S 6 +/** MCPWM_GEN1_A_UT0 : R/W; bitpos: [9:8]; default: 0; + * Action on PWM1A triggered by event_t0 when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN1_A_UT0 0x00000003U +#define MCPWM_GEN1_A_UT0_M (MCPWM_GEN1_A_UT0_V << MCPWM_GEN1_A_UT0_S) +#define MCPWM_GEN1_A_UT0_V 0x00000003U +#define MCPWM_GEN1_A_UT0_S 8 +/** MCPWM_GEN1_A_UT1 : R/W; bitpos: [11:10]; default: 0; + * Action on PWM1A triggered by event_t1 when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN1_A_UT1 0x00000003U +#define MCPWM_GEN1_A_UT1_M (MCPWM_GEN1_A_UT1_V << MCPWM_GEN1_A_UT1_S) +#define MCPWM_GEN1_A_UT1_V 0x00000003U +#define MCPWM_GEN1_A_UT1_S 10 +/** MCPWM_GEN1_A_DTEZ : R/W; bitpos: [13:12]; default: 0; + * Action on PWM1A triggered by event TEZ when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN1_A_DTEZ 0x00000003U +#define MCPWM_GEN1_A_DTEZ_M (MCPWM_GEN1_A_DTEZ_V << MCPWM_GEN1_A_DTEZ_S) +#define MCPWM_GEN1_A_DTEZ_V 0x00000003U +#define MCPWM_GEN1_A_DTEZ_S 12 +/** MCPWM_GEN1_A_DTEP : R/W; bitpos: [15:14]; default: 0; + * Action on PWM1A triggered by event TEP when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN1_A_DTEP 0x00000003U +#define MCPWM_GEN1_A_DTEP_M (MCPWM_GEN1_A_DTEP_V << MCPWM_GEN1_A_DTEP_S) +#define MCPWM_GEN1_A_DTEP_V 0x00000003U +#define MCPWM_GEN1_A_DTEP_S 14 +/** MCPWM_GEN1_A_DTEA : R/W; bitpos: [17:16]; default: 0; + * Action on PWM1A triggered by event TEA when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN1_A_DTEA 0x00000003U +#define MCPWM_GEN1_A_DTEA_M (MCPWM_GEN1_A_DTEA_V << MCPWM_GEN1_A_DTEA_S) +#define MCPWM_GEN1_A_DTEA_V 0x00000003U +#define MCPWM_GEN1_A_DTEA_S 16 +/** MCPWM_GEN1_A_DTEB : R/W; bitpos: [19:18]; default: 0; + * Action on PWM1A triggered by event TEB when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN1_A_DTEB 0x00000003U +#define MCPWM_GEN1_A_DTEB_M (MCPWM_GEN1_A_DTEB_V << MCPWM_GEN1_A_DTEB_S) +#define MCPWM_GEN1_A_DTEB_V 0x00000003U +#define MCPWM_GEN1_A_DTEB_S 18 +/** MCPWM_GEN1_A_DT0 : R/W; bitpos: [21:20]; default: 0; + * Action on PWM1A triggered by event_t0 when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN1_A_DT0 0x00000003U +#define MCPWM_GEN1_A_DT0_M (MCPWM_GEN1_A_DT0_V << MCPWM_GEN1_A_DT0_S) +#define MCPWM_GEN1_A_DT0_V 0x00000003U +#define MCPWM_GEN1_A_DT0_S 20 +/** MCPWM_GEN1_A_DT1 : R/W; bitpos: [23:22]; default: 0; + * Action on PWM1A triggered by event_t1 when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN1_A_DT1 0x00000003U +#define MCPWM_GEN1_A_DT1_M (MCPWM_GEN1_A_DT1_V << MCPWM_GEN1_A_DT1_S) +#define MCPWM_GEN1_A_DT1_V 0x00000003U +#define MCPWM_GEN1_A_DT1_S 22 -#define MCPWM_GEN1_B_REG(i) (REG_MCPWM_BASE(i) + 0x8C) -/* MCPWM_GEN1_B_DT1 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ -/*description: .*/ -#define MCPWM_GEN1_B_DT1 0x00000003 -#define MCPWM_GEN1_B_DT1_M ((MCPWM_GEN1_B_DT1_V)<<(MCPWM_GEN1_B_DT1_S)) -#define MCPWM_GEN1_B_DT1_V 0x3 -#define MCPWM_GEN1_B_DT1_S 22 -/* MCPWM_GEN1_B_DT0 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ -/*description: .*/ -#define MCPWM_GEN1_B_DT0 0x00000003 -#define MCPWM_GEN1_B_DT0_M ((MCPWM_GEN1_B_DT0_V)<<(MCPWM_GEN1_B_DT0_S)) -#define MCPWM_GEN1_B_DT0_V 0x3 -#define MCPWM_GEN1_B_DT0_S 20 -/* MCPWM_GEN1_B_DTEB : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ -/*description: .*/ -#define MCPWM_GEN1_B_DTEB 0x00000003 -#define MCPWM_GEN1_B_DTEB_M ((MCPWM_GEN1_B_DTEB_V)<<(MCPWM_GEN1_B_DTEB_S)) -#define MCPWM_GEN1_B_DTEB_V 0x3 -#define MCPWM_GEN1_B_DTEB_S 18 -/* MCPWM_GEN1_B_DTEA : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ -/*description: .*/ -#define MCPWM_GEN1_B_DTEA 0x00000003 -#define MCPWM_GEN1_B_DTEA_M ((MCPWM_GEN1_B_DTEA_V)<<(MCPWM_GEN1_B_DTEA_S)) -#define MCPWM_GEN1_B_DTEA_V 0x3 -#define MCPWM_GEN1_B_DTEA_S 16 -/* MCPWM_GEN1_B_DTEP : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ -/*description: .*/ -#define MCPWM_GEN1_B_DTEP 0x00000003 -#define MCPWM_GEN1_B_DTEP_M ((MCPWM_GEN1_B_DTEP_V)<<(MCPWM_GEN1_B_DTEP_S)) -#define MCPWM_GEN1_B_DTEP_V 0x3 -#define MCPWM_GEN1_B_DTEP_S 14 -/* MCPWM_GEN1_B_DTEZ : R/W ;bitpos:[13:12] ;default: 2'd0 ; */ -/*description: .*/ -#define MCPWM_GEN1_B_DTEZ 0x00000003 -#define MCPWM_GEN1_B_DTEZ_M ((MCPWM_GEN1_B_DTEZ_V)<<(MCPWM_GEN1_B_DTEZ_S)) -#define MCPWM_GEN1_B_DTEZ_V 0x3 -#define MCPWM_GEN1_B_DTEZ_S 12 -/* MCPWM_GEN1_B_UT1 : R/W ;bitpos:[11:10] ;default: 2'd0 ; */ -/*description: .*/ -#define MCPWM_GEN1_B_UT1 0x00000003 -#define MCPWM_GEN1_B_UT1_M ((MCPWM_GEN1_B_UT1_V)<<(MCPWM_GEN1_B_UT1_S)) -#define MCPWM_GEN1_B_UT1_V 0x3 -#define MCPWM_GEN1_B_UT1_S 10 -/* MCPWM_GEN1_B_UT0 : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ -/*description: .*/ -#define MCPWM_GEN1_B_UT0 0x00000003 -#define MCPWM_GEN1_B_UT0_M ((MCPWM_GEN1_B_UT0_V)<<(MCPWM_GEN1_B_UT0_S)) -#define MCPWM_GEN1_B_UT0_V 0x3 -#define MCPWM_GEN1_B_UT0_S 8 -/* MCPWM_GEN1_B_UTEB : R/W ;bitpos:[7:6] ;default: 2'd0 ; */ -/*description: .*/ -#define MCPWM_GEN1_B_UTEB 0x00000003 -#define MCPWM_GEN1_B_UTEB_M ((MCPWM_GEN1_B_UTEB_V)<<(MCPWM_GEN1_B_UTEB_S)) -#define MCPWM_GEN1_B_UTEB_V 0x3 -#define MCPWM_GEN1_B_UTEB_S 6 -/* MCPWM_GEN1_B_UTEA : R/W ;bitpos:[5:4] ;default: 2'd0 ; */ -/*description: .*/ -#define MCPWM_GEN1_B_UTEA 0x00000003 -#define MCPWM_GEN1_B_UTEA_M ((MCPWM_GEN1_B_UTEA_V)<<(MCPWM_GEN1_B_UTEA_S)) -#define MCPWM_GEN1_B_UTEA_V 0x3 -#define MCPWM_GEN1_B_UTEA_S 4 -/* MCPWM_GEN1_B_UTEP : R/W ;bitpos:[3:2] ;default: 2'd0 ; */ -/*description: .*/ -#define MCPWM_GEN1_B_UTEP 0x00000003 -#define MCPWM_GEN1_B_UTEP_M ((MCPWM_GEN1_B_UTEP_V)<<(MCPWM_GEN1_B_UTEP_S)) -#define MCPWM_GEN1_B_UTEP_V 0x3 -#define MCPWM_GEN1_B_UTEP_S 2 -/* MCPWM_GEN1_B_UTEZ : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: .*/ -#define MCPWM_GEN1_B_UTEZ 0x00000003 -#define MCPWM_GEN1_B_UTEZ_M ((MCPWM_GEN1_B_UTEZ_V)<<(MCPWM_GEN1_B_UTEZ_S)) -#define MCPWM_GEN1_B_UTEZ_V 0x3 +/** MCPWM_GEN1_B_REG register + * Actions triggered by events on PWM1B + */ +#define MCPWM_GEN1_B_REG(i) (DR_REG_MCPWM_BASE(i) + 0x8c) +/** MCPWM_GEN1_B_UTEZ : R/W; bitpos: [1:0]; default: 0; + * Action on PWM1B triggered by event TEZ when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN1_B_UTEZ 0x00000003U +#define MCPWM_GEN1_B_UTEZ_M (MCPWM_GEN1_B_UTEZ_V << MCPWM_GEN1_B_UTEZ_S) +#define MCPWM_GEN1_B_UTEZ_V 0x00000003U #define MCPWM_GEN1_B_UTEZ_S 0 +/** MCPWM_GEN1_B_UTEP : R/W; bitpos: [3:2]; default: 0; + * Action on PWM1B triggered by event TEP when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN1_B_UTEP 0x00000003U +#define MCPWM_GEN1_B_UTEP_M (MCPWM_GEN1_B_UTEP_V << MCPWM_GEN1_B_UTEP_S) +#define MCPWM_GEN1_B_UTEP_V 0x00000003U +#define MCPWM_GEN1_B_UTEP_S 2 +/** MCPWM_GEN1_B_UTEA : R/W; bitpos: [5:4]; default: 0; + * Action on PWM1B triggered by event TEA when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN1_B_UTEA 0x00000003U +#define MCPWM_GEN1_B_UTEA_M (MCPWM_GEN1_B_UTEA_V << MCPWM_GEN1_B_UTEA_S) +#define MCPWM_GEN1_B_UTEA_V 0x00000003U +#define MCPWM_GEN1_B_UTEA_S 4 +/** MCPWM_GEN1_B_UTEB : R/W; bitpos: [7:6]; default: 0; + * Action on PWM1B triggered by event TEB when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN1_B_UTEB 0x00000003U +#define MCPWM_GEN1_B_UTEB_M (MCPWM_GEN1_B_UTEB_V << MCPWM_GEN1_B_UTEB_S) +#define MCPWM_GEN1_B_UTEB_V 0x00000003U +#define MCPWM_GEN1_B_UTEB_S 6 +/** MCPWM_GEN1_B_UT0 : R/W; bitpos: [9:8]; default: 0; + * Action on PWM1B triggered by event_t0 when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN1_B_UT0 0x00000003U +#define MCPWM_GEN1_B_UT0_M (MCPWM_GEN1_B_UT0_V << MCPWM_GEN1_B_UT0_S) +#define MCPWM_GEN1_B_UT0_V 0x00000003U +#define MCPWM_GEN1_B_UT0_S 8 +/** MCPWM_GEN1_B_UT1 : R/W; bitpos: [11:10]; default: 0; + * Action on PWM1B triggered by event_t1 when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN1_B_UT1 0x00000003U +#define MCPWM_GEN1_B_UT1_M (MCPWM_GEN1_B_UT1_V << MCPWM_GEN1_B_UT1_S) +#define MCPWM_GEN1_B_UT1_V 0x00000003U +#define MCPWM_GEN1_B_UT1_S 10 +/** MCPWM_GEN1_B_DTEZ : R/W; bitpos: [13:12]; default: 0; + * Action on PWM1B triggered by event TEZ when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN1_B_DTEZ 0x00000003U +#define MCPWM_GEN1_B_DTEZ_M (MCPWM_GEN1_B_DTEZ_V << MCPWM_GEN1_B_DTEZ_S) +#define MCPWM_GEN1_B_DTEZ_V 0x00000003U +#define MCPWM_GEN1_B_DTEZ_S 12 +/** MCPWM_GEN1_B_DTEP : R/W; bitpos: [15:14]; default: 0; + * Action on PWM1B triggered by event TEP when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN1_B_DTEP 0x00000003U +#define MCPWM_GEN1_B_DTEP_M (MCPWM_GEN1_B_DTEP_V << MCPWM_GEN1_B_DTEP_S) +#define MCPWM_GEN1_B_DTEP_V 0x00000003U +#define MCPWM_GEN1_B_DTEP_S 14 +/** MCPWM_GEN1_B_DTEA : R/W; bitpos: [17:16]; default: 0; + * Action on PWM1B triggered by event TEA when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN1_B_DTEA 0x00000003U +#define MCPWM_GEN1_B_DTEA_M (MCPWM_GEN1_B_DTEA_V << MCPWM_GEN1_B_DTEA_S) +#define MCPWM_GEN1_B_DTEA_V 0x00000003U +#define MCPWM_GEN1_B_DTEA_S 16 +/** MCPWM_GEN1_B_DTEB : R/W; bitpos: [19:18]; default: 0; + * Action on PWM1B triggered by event TEB when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN1_B_DTEB 0x00000003U +#define MCPWM_GEN1_B_DTEB_M (MCPWM_GEN1_B_DTEB_V << MCPWM_GEN1_B_DTEB_S) +#define MCPWM_GEN1_B_DTEB_V 0x00000003U +#define MCPWM_GEN1_B_DTEB_S 18 +/** MCPWM_GEN1_B_DT0 : R/W; bitpos: [21:20]; default: 0; + * Action on PWM1B triggered by event_t0 when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN1_B_DT0 0x00000003U +#define MCPWM_GEN1_B_DT0_M (MCPWM_GEN1_B_DT0_V << MCPWM_GEN1_B_DT0_S) +#define MCPWM_GEN1_B_DT0_V 0x00000003U +#define MCPWM_GEN1_B_DT0_S 20 +/** MCPWM_GEN1_B_DT1 : R/W; bitpos: [23:22]; default: 0; + * Action on PWM1B triggered by event_t1 when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN1_B_DT1 0x00000003U +#define MCPWM_GEN1_B_DT1_M (MCPWM_GEN1_B_DT1_V << MCPWM_GEN1_B_DT1_S) +#define MCPWM_GEN1_B_DT1_V 0x00000003U +#define MCPWM_GEN1_B_DT1_S 22 -#define MCPWM_DB1_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x90) -/* MCPWM_DB1_CLK_SEL : R/W ;bitpos:[17] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_DB1_CLK_SEL (BIT(17)) -#define MCPWM_DB1_CLK_SEL_M (BIT(17)) -#define MCPWM_DB1_CLK_SEL_V 0x1 -#define MCPWM_DB1_CLK_SEL_S 17 -/* MCPWM_DB1_B_OUTBYPASS : R/W ;bitpos:[16] ;default: 1'd1 ; */ -/*description: .*/ -#define MCPWM_DB1_B_OUTBYPASS (BIT(16)) -#define MCPWM_DB1_B_OUTBYPASS_M (BIT(16)) -#define MCPWM_DB1_B_OUTBYPASS_V 0x1 -#define MCPWM_DB1_B_OUTBYPASS_S 16 -/* MCPWM_DB1_A_OUTBYPASS : R/W ;bitpos:[15] ;default: 1'd1 ; */ -/*description: .*/ -#define MCPWM_DB1_A_OUTBYPASS (BIT(15)) -#define MCPWM_DB1_A_OUTBYPASS_M (BIT(15)) -#define MCPWM_DB1_A_OUTBYPASS_V 0x1 -#define MCPWM_DB1_A_OUTBYPASS_S 15 -/* MCPWM_DB1_FED_OUTINVERT : R/W ;bitpos:[14] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_DB1_FED_OUTINVERT (BIT(14)) -#define MCPWM_DB1_FED_OUTINVERT_M (BIT(14)) -#define MCPWM_DB1_FED_OUTINVERT_V 0x1 -#define MCPWM_DB1_FED_OUTINVERT_S 14 -/* MCPWM_DB1_RED_OUTINVERT : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_DB1_RED_OUTINVERT (BIT(13)) -#define MCPWM_DB1_RED_OUTINVERT_M (BIT(13)) -#define MCPWM_DB1_RED_OUTINVERT_V 0x1 -#define MCPWM_DB1_RED_OUTINVERT_S 13 -/* MCPWM_DB1_FED_INSEL : R/W ;bitpos:[12] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_DB1_FED_INSEL (BIT(12)) -#define MCPWM_DB1_FED_INSEL_M (BIT(12)) -#define MCPWM_DB1_FED_INSEL_V 0x1 -#define MCPWM_DB1_FED_INSEL_S 12 -/* MCPWM_DB1_RED_INSEL : R/W ;bitpos:[11] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_DB1_RED_INSEL (BIT(11)) -#define MCPWM_DB1_RED_INSEL_M (BIT(11)) -#define MCPWM_DB1_RED_INSEL_V 0x1 -#define MCPWM_DB1_RED_INSEL_S 11 -/* MCPWM_DB1_B_OUTSWAP : R/W ;bitpos:[10] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_DB1_B_OUTSWAP (BIT(10)) -#define MCPWM_DB1_B_OUTSWAP_M (BIT(10)) -#define MCPWM_DB1_B_OUTSWAP_V 0x1 -#define MCPWM_DB1_B_OUTSWAP_S 10 -/* MCPWM_DB1_A_OUTSWAP : R/W ;bitpos:[9] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_DB1_A_OUTSWAP (BIT(9)) -#define MCPWM_DB1_A_OUTSWAP_M (BIT(9)) -#define MCPWM_DB1_A_OUTSWAP_V 0x1 -#define MCPWM_DB1_A_OUTSWAP_S 9 -/* MCPWM_DB1_DEB_MODE : R/W ;bitpos:[8] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_DB1_DEB_MODE (BIT(8)) -#define MCPWM_DB1_DEB_MODE_M (BIT(8)) -#define MCPWM_DB1_DEB_MODE_V 0x1 -#define MCPWM_DB1_DEB_MODE_S 8 -/* MCPWM_DB1_RED_UPMETHOD : R/W ;bitpos:[7:4] ;default: 4'd0 ; */ -/*description: .*/ -#define MCPWM_DB1_RED_UPMETHOD 0x0000000F -#define MCPWM_DB1_RED_UPMETHOD_M ((MCPWM_DB1_RED_UPMETHOD_V)<<(MCPWM_DB1_RED_UPMETHOD_S)) -#define MCPWM_DB1_RED_UPMETHOD_V 0xF -#define MCPWM_DB1_RED_UPMETHOD_S 4 -/* MCPWM_DB1_FED_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: .*/ -#define MCPWM_DB1_FED_UPMETHOD 0x0000000F -#define MCPWM_DB1_FED_UPMETHOD_M ((MCPWM_DB1_FED_UPMETHOD_V)<<(MCPWM_DB1_FED_UPMETHOD_S)) -#define MCPWM_DB1_FED_UPMETHOD_V 0xF -#define MCPWM_DB1_FED_UPMETHOD_S 0 - -#define MCPWM_DB1_FED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x94) -/* MCPWM_DB1_FED : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ -/*description: .*/ -#define MCPWM_DB1_FED 0x0000FFFF -#define MCPWM_DB1_FED_M ((MCPWM_DB1_FED_V)<<(MCPWM_DB1_FED_S)) -#define MCPWM_DB1_FED_V 0xFFFF -#define MCPWM_DB1_FED_S 0 - -#define MCPWM_DB1_RED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x98) -/* MCPWM_DB1_RED : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ -/*description: .*/ -#define MCPWM_DB1_RED 0x0000FFFF -#define MCPWM_DB1_RED_M ((MCPWM_DB1_RED_V)<<(MCPWM_DB1_RED_S)) -#define MCPWM_DB1_RED_V 0xFFFF -#define MCPWM_DB1_RED_S 0 - -#define MCPWM_CHOPPER1_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x9C) -/* MCPWM_CHOPPER1_IN_INVERT : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_CHOPPER1_IN_INVERT (BIT(13)) -#define MCPWM_CHOPPER1_IN_INVERT_M (BIT(13)) -#define MCPWM_CHOPPER1_IN_INVERT_V 0x1 -#define MCPWM_CHOPPER1_IN_INVERT_S 13 -/* MCPWM_CHOPPER1_OUT_INVERT : R/W ;bitpos:[12] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_CHOPPER1_OUT_INVERT (BIT(12)) -#define MCPWM_CHOPPER1_OUT_INVERT_M (BIT(12)) -#define MCPWM_CHOPPER1_OUT_INVERT_V 0x1 -#define MCPWM_CHOPPER1_OUT_INVERT_S 12 -/* MCPWM_CHOPPER1_OSHTWTH : R/W ;bitpos:[11:8] ;default: 4'd0 ; */ -/*description: .*/ -#define MCPWM_CHOPPER1_OSHTWTH 0x0000000F -#define MCPWM_CHOPPER1_OSHTWTH_M ((MCPWM_CHOPPER1_OSHTWTH_V)<<(MCPWM_CHOPPER1_OSHTWTH_S)) -#define MCPWM_CHOPPER1_OSHTWTH_V 0xF -#define MCPWM_CHOPPER1_OSHTWTH_S 8 -/* MCPWM_CHOPPER1_DUTY : R/W ;bitpos:[7:5] ;default: 3'd0 ; */ -/*description: .*/ -#define MCPWM_CHOPPER1_DUTY 0x00000007 -#define MCPWM_CHOPPER1_DUTY_M ((MCPWM_CHOPPER1_DUTY_V)<<(MCPWM_CHOPPER1_DUTY_S)) -#define MCPWM_CHOPPER1_DUTY_V 0x7 -#define MCPWM_CHOPPER1_DUTY_S 5 -/* MCPWM_CHOPPER1_PRESCALE : R/W ;bitpos:[4:1] ;default: 4'd0 ; */ -/*description: .*/ -#define MCPWM_CHOPPER1_PRESCALE 0x0000000F -#define MCPWM_CHOPPER1_PRESCALE_M ((MCPWM_CHOPPER1_PRESCALE_V)<<(MCPWM_CHOPPER1_PRESCALE_S)) -#define MCPWM_CHOPPER1_PRESCALE_V 0xF -#define MCPWM_CHOPPER1_PRESCALE_S 1 -/* MCPWM_CHOPPER1_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_CHOPPER1_EN (BIT(0)) -#define MCPWM_CHOPPER1_EN_M (BIT(0)) -#define MCPWM_CHOPPER1_EN_V 0x1 -#define MCPWM_CHOPPER1_EN_S 0 - -#define MCPWM_TZ1_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0xA0) -/* MCPWM_TZ1_B_OST_U : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ -/*description: 0: do nothing, 1: force lo, 2: force hi, 3: toggle.*/ -#define MCPWM_TZ1_B_OST_U 0x00000003 -#define MCPWM_TZ1_B_OST_U_M ((MCPWM_TZ1_B_OST_U_V)<<(MCPWM_TZ1_B_OST_U_S)) -#define MCPWM_TZ1_B_OST_U_V 0x3 -#define MCPWM_TZ1_B_OST_U_S 22 -/* MCPWM_TZ1_B_OST_D : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ -/*description: 0: do nothing, 1: force lo, 2: force hi, 3: toggle.*/ -#define MCPWM_TZ1_B_OST_D 0x00000003 -#define MCPWM_TZ1_B_OST_D_M ((MCPWM_TZ1_B_OST_D_V)<<(MCPWM_TZ1_B_OST_D_S)) -#define MCPWM_TZ1_B_OST_D_V 0x3 -#define MCPWM_TZ1_B_OST_D_S 20 -/* MCPWM_TZ1_B_CBC_U : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ -/*description: 0: do nothing, 1: force lo, 2: force hi, 3: toggle.*/ -#define MCPWM_TZ1_B_CBC_U 0x00000003 -#define MCPWM_TZ1_B_CBC_U_M ((MCPWM_TZ1_B_CBC_U_V)<<(MCPWM_TZ1_B_CBC_U_S)) -#define MCPWM_TZ1_B_CBC_U_V 0x3 -#define MCPWM_TZ1_B_CBC_U_S 18 -/* MCPWM_TZ1_B_CBC_D : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ -/*description: 0: do nothing, 1: force lo, 2: force hi, 3: toggle.*/ -#define MCPWM_TZ1_B_CBC_D 0x00000003 -#define MCPWM_TZ1_B_CBC_D_M ((MCPWM_TZ1_B_CBC_D_V)<<(MCPWM_TZ1_B_CBC_D_S)) -#define MCPWM_TZ1_B_CBC_D_V 0x3 -#define MCPWM_TZ1_B_CBC_D_S 16 -/* MCPWM_TZ1_A_OST_U : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ -/*description: 0: do nothing, 1: force lo, 2: force hi, 3: toggle.*/ -#define MCPWM_TZ1_A_OST_U 0x00000003 -#define MCPWM_TZ1_A_OST_U_M ((MCPWM_TZ1_A_OST_U_V)<<(MCPWM_TZ1_A_OST_U_S)) -#define MCPWM_TZ1_A_OST_U_V 0x3 -#define MCPWM_TZ1_A_OST_U_S 14 -/* MCPWM_TZ1_A_OST_D : R/W ;bitpos:[13:12] ;default: 2'd0 ; */ -/*description: 0: do nothing, 1: force lo, 2: force hi, 3: toggle.*/ -#define MCPWM_TZ1_A_OST_D 0x00000003 -#define MCPWM_TZ1_A_OST_D_M ((MCPWM_TZ1_A_OST_D_V)<<(MCPWM_TZ1_A_OST_D_S)) -#define MCPWM_TZ1_A_OST_D_V 0x3 -#define MCPWM_TZ1_A_OST_D_S 12 -/* MCPWM_TZ1_A_CBC_U : R/W ;bitpos:[11:10] ;default: 2'd0 ; */ -/*description: 0: do nothing, 1: force lo, 2: force hi, 3: toggle.*/ -#define MCPWM_TZ1_A_CBC_U 0x00000003 -#define MCPWM_TZ1_A_CBC_U_M ((MCPWM_TZ1_A_CBC_U_V)<<(MCPWM_TZ1_A_CBC_U_S)) -#define MCPWM_TZ1_A_CBC_U_V 0x3 -#define MCPWM_TZ1_A_CBC_U_S 10 -/* MCPWM_TZ1_A_CBC_D : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ -/*description: 0: do nothing, 1: force lo, 2: force hi, 3: toggle.*/ -#define MCPWM_TZ1_A_CBC_D 0x00000003 -#define MCPWM_TZ1_A_CBC_D_M ((MCPWM_TZ1_A_CBC_D_V)<<(MCPWM_TZ1_A_CBC_D_S)) -#define MCPWM_TZ1_A_CBC_D_V 0x3 -#define MCPWM_TZ1_A_CBC_D_S 8 -/* MCPWM_TZ1_F0_OST : R/W ;bitpos:[7] ;default: 1'd0 ; */ -/*description: 0: disable, 1: enable.*/ -#define MCPWM_TZ1_F0_OST (BIT(7)) -#define MCPWM_TZ1_F0_OST_M (BIT(7)) -#define MCPWM_TZ1_F0_OST_V 0x1 -#define MCPWM_TZ1_F0_OST_S 7 -/* MCPWM_TZ1_F1_OST : R/W ;bitpos:[6] ;default: 1'd0 ; */ -/*description: 0: disable, 1: enable.*/ -#define MCPWM_TZ1_F1_OST (BIT(6)) -#define MCPWM_TZ1_F1_OST_M (BIT(6)) -#define MCPWM_TZ1_F1_OST_V 0x1 -#define MCPWM_TZ1_F1_OST_S 6 -/* MCPWM_TZ1_F2_OST : R/W ;bitpos:[5] ;default: 1'd0 ; */ -/*description: 0: disable, 1: enable.*/ -#define MCPWM_TZ1_F2_OST (BIT(5)) -#define MCPWM_TZ1_F2_OST_M (BIT(5)) -#define MCPWM_TZ1_F2_OST_V 0x1 -#define MCPWM_TZ1_F2_OST_S 5 -/* MCPWM_TZ1_SW_OST : R/W ;bitpos:[4] ;default: 1'd0 ; */ -/*description: 0: disable, 1: enable.*/ -#define MCPWM_TZ1_SW_OST (BIT(4)) -#define MCPWM_TZ1_SW_OST_M (BIT(4)) -#define MCPWM_TZ1_SW_OST_V 0x1 -#define MCPWM_TZ1_SW_OST_S 4 -/* MCPWM_TZ1_F0_CBC : R/W ;bitpos:[3] ;default: 1'd0 ; */ -/*description: 0: disable, 1: enable.*/ -#define MCPWM_TZ1_F0_CBC (BIT(3)) -#define MCPWM_TZ1_F0_CBC_M (BIT(3)) -#define MCPWM_TZ1_F0_CBC_V 0x1 -#define MCPWM_TZ1_F0_CBC_S 3 -/* MCPWM_TZ1_F1_CBC : R/W ;bitpos:[2] ;default: 1'd0 ; */ -/*description: 0: disable, 1: enable.*/ -#define MCPWM_TZ1_F1_CBC (BIT(2)) -#define MCPWM_TZ1_F1_CBC_M (BIT(2)) -#define MCPWM_TZ1_F1_CBC_V 0x1 -#define MCPWM_TZ1_F1_CBC_S 2 -/* MCPWM_TZ1_F2_CBC : R/W ;bitpos:[1] ;default: 1'd0 ; */ -/*description: 0: disable, 1: enable.*/ -#define MCPWM_TZ1_F2_CBC (BIT(1)) -#define MCPWM_TZ1_F2_CBC_M (BIT(1)) -#define MCPWM_TZ1_F2_CBC_V 0x1 -#define MCPWM_TZ1_F2_CBC_S 1 -/* MCPWM_TZ1_SW_CBC : R/W ;bitpos:[0] ;default: 1'd0 ; */ -/*description: 0: disable, 1: enable.*/ -#define MCPWM_TZ1_SW_CBC (BIT(0)) -#define MCPWM_TZ1_SW_CBC_M (BIT(0)) -#define MCPWM_TZ1_SW_CBC_V 0x1 -#define MCPWM_TZ1_SW_CBC_S 0 - -#define MCPWM_TZ1_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0xA4) -/* MCPWM_TZ1_FORCE_OST : R/W ;bitpos:[4] ;default: 1'd0 ; */ -/*description: a toggle trigger a oneshot tripping.*/ -#define MCPWM_TZ1_FORCE_OST (BIT(4)) -#define MCPWM_TZ1_FORCE_OST_M (BIT(4)) -#define MCPWM_TZ1_FORCE_OST_V 0x1 -#define MCPWM_TZ1_FORCE_OST_S 4 -/* MCPWM_TZ1_FORCE_CBC : R/W ;bitpos:[3] ;default: 1'd0 ; */ -/*description: a toggle trigger a cycle-by-cycle tripping.*/ -#define MCPWM_TZ1_FORCE_CBC (BIT(3)) -#define MCPWM_TZ1_FORCE_CBC_M (BIT(3)) -#define MCPWM_TZ1_FORCE_CBC_V 0x1 -#define MCPWM_TZ1_FORCE_CBC_S 3 -/* MCPWM_TZ1_CBCPULSE : R/W ;bitpos:[2:1] ;default: 2'd0 ; */ -/*description: bit0: tez, bit1: tep.*/ -#define MCPWM_TZ1_CBCPULSE 0x00000003 -#define MCPWM_TZ1_CBCPULSE_M ((MCPWM_TZ1_CBCPULSE_V)<<(MCPWM_TZ1_CBCPULSE_S)) -#define MCPWM_TZ1_CBCPULSE_V 0x3 -#define MCPWM_TZ1_CBCPULSE_S 1 -/* MCPWM_TZ1_CLR_OST : R/W ;bitpos:[0] ;default: 1'd0 ; */ -/*description: a toggle will clear oneshot tripping.*/ -#define MCPWM_TZ1_CLR_OST (BIT(0)) -#define MCPWM_TZ1_CLR_OST_M (BIT(0)) -#define MCPWM_TZ1_CLR_OST_V 0x1 -#define MCPWM_TZ1_CLR_OST_S 0 - -#define MCPWM_TZ1_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0xA8) -/* MCPWM_TZ1_OST_ON : RO ;bitpos:[1] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_TZ1_OST_ON (BIT(1)) -#define MCPWM_TZ1_OST_ON_M (BIT(1)) -#define MCPWM_TZ1_OST_ON_V 0x1 -#define MCPWM_TZ1_OST_ON_S 1 -/* MCPWM_TZ1_CBC_ON : RO ;bitpos:[0] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_TZ1_CBC_ON (BIT(0)) -#define MCPWM_TZ1_CBC_ON_M (BIT(0)) -#define MCPWM_TZ1_CBC_ON_V 0x1 -#define MCPWM_TZ1_CBC_ON_S 0 - -#define MCPWM_CMPR2_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xAC) -/* MCPWM_CMPR2_B_SHDW_FULL : R/W ;bitpos:[9] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_CMPR2_B_SHDW_FULL (BIT(9)) -#define MCPWM_CMPR2_B_SHDW_FULL_M (BIT(9)) -#define MCPWM_CMPR2_B_SHDW_FULL_V 0x1 -#define MCPWM_CMPR2_B_SHDW_FULL_S 9 -/* MCPWM_CMPR2_A_SHDW_FULL : R/W ;bitpos:[8] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_CMPR2_A_SHDW_FULL (BIT(8)) -#define MCPWM_CMPR2_A_SHDW_FULL_M (BIT(8)) -#define MCPWM_CMPR2_A_SHDW_FULL_V 0x1 -#define MCPWM_CMPR2_A_SHDW_FULL_S 8 -/* MCPWM_CMPR2_B_UPMETHOD : R/W ;bitpos:[7:4] ;default: 4'd0 ; */ -/*description: 0: immediate, bit0: tez, bit1: tep, bit2: sync, bit3: freeze.*/ -#define MCPWM_CMPR2_B_UPMETHOD 0x0000000F -#define MCPWM_CMPR2_B_UPMETHOD_M ((MCPWM_CMPR2_B_UPMETHOD_V)<<(MCPWM_CMPR2_B_UPMETHOD_S)) -#define MCPWM_CMPR2_B_UPMETHOD_V 0xF -#define MCPWM_CMPR2_B_UPMETHOD_S 4 -/* MCPWM_CMPR2_A_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: 0: immediate, bit0: tez, bit1: tep, bit2: sync, bit3: freeze.*/ -#define MCPWM_CMPR2_A_UPMETHOD 0x0000000F -#define MCPWM_CMPR2_A_UPMETHOD_M ((MCPWM_CMPR2_A_UPMETHOD_V)<<(MCPWM_CMPR2_A_UPMETHOD_S)) -#define MCPWM_CMPR2_A_UPMETHOD_V 0xF -#define MCPWM_CMPR2_A_UPMETHOD_S 0 - -#define MCPWM_CMPR2_VALUE0_REG(i) (REG_MCPWM_BASE(i) + 0xB0) -/* MCPWM_CMPR2_A : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ -/*description: .*/ -#define MCPWM_CMPR2_A 0x0000FFFF -#define MCPWM_CMPR2_A_M ((MCPWM_CMPR2_A_V)<<(MCPWM_CMPR2_A_S)) -#define MCPWM_CMPR2_A_V 0xFFFF -#define MCPWM_CMPR2_A_S 0 - -#define MCPWM_CMPR2_VALUE1_REG(i) (REG_MCPWM_BASE(i) + 0xB4) -/* MCPWM_CMPR2_B : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ -/*description: .*/ -#define MCPWM_CMPR2_B 0x0000FFFF -#define MCPWM_CMPR2_B_M ((MCPWM_CMPR2_B_V)<<(MCPWM_CMPR2_B_S)) -#define MCPWM_CMPR2_B_V 0xFFFF -#define MCPWM_CMPR2_B_S 0 - -#define MCPWM_GEN2_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0xB8) -/* MCPWM_GEN2_T1_SEL : R/W ;bitpos:[9:7] ;default: 3'd0 ; */ -/*description: take effect immediately, 0: extra0, 1: extra1, 2: extra2, 3: sync_taken, 4: none.*/ -#define MCPWM_GEN2_T1_SEL 0x00000007 -#define MCPWM_GEN2_T1_SEL_M ((MCPWM_GEN2_T1_SEL_V)<<(MCPWM_GEN2_T1_SEL_S)) -#define MCPWM_GEN2_T1_SEL_V 0x7 -#define MCPWM_GEN2_T1_SEL_S 7 -/* MCPWM_GEN2_T0_SEL : R/W ;bitpos:[6:4] ;default: 3'd0 ; */ -/*description: take effect immediately, 0: extra0, 1: extra1, 2: extra2, 3: sync_taken, 4: none.*/ -#define MCPWM_GEN2_T0_SEL 0x00000007 -#define MCPWM_GEN2_T0_SEL_M ((MCPWM_GEN2_T0_SEL_V)<<(MCPWM_GEN2_T0_SEL_S)) -#define MCPWM_GEN2_T0_SEL_V 0x7 -#define MCPWM_GEN2_T0_SEL_S 4 -/* MCPWM_GEN2_CFG_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: 0: immediate, bit0: tez, bit1: tep, bit2: sync. bit3: freeze.*/ -#define MCPWM_GEN2_CFG_UPMETHOD 0x0000000F -#define MCPWM_GEN2_CFG_UPMETHOD_M ((MCPWM_GEN2_CFG_UPMETHOD_V)<<(MCPWM_GEN2_CFG_UPMETHOD_S)) -#define MCPWM_GEN2_CFG_UPMETHOD_V 0xF +/** MCPWM_DT1_CFG_REG register + * PWM generator 1 dead time type selection and configuration + */ +#define MCPWM_DT1_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0x90) +/** MCPWM_DT1_FED_UPMETHOD : R/W; bitpos: [3:0]; default: 0; + * Update method for FED (falling edge delay) active register. 0: immediate, when bit0 + * is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when + * bit3 is set to 1: disable the update + */ +#define MCPWM_DT1_FED_UPMETHOD 0x0000000FU +#define MCPWM_DT1_FED_UPMETHOD_M (MCPWM_DT1_FED_UPMETHOD_V << MCPWM_DT1_FED_UPMETHOD_S) +#define MCPWM_DT1_FED_UPMETHOD_V 0x0000000FU +#define MCPWM_DT1_FED_UPMETHOD_S 0 +/** MCPWM_DT1_RED_UPMETHOD : R/W; bitpos: [7:4]; default: 0; + * Update method for RED (rising edge delay) active register. 0: immediate,when bit0 + * is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when + * bit3 is set to 1: disable the update + */ +#define MCPWM_DT1_RED_UPMETHOD 0x0000000FU +#define MCPWM_DT1_RED_UPMETHOD_M (MCPWM_DT1_RED_UPMETHOD_V << MCPWM_DT1_RED_UPMETHOD_S) +#define MCPWM_DT1_RED_UPMETHOD_V 0x0000000FU +#define MCPWM_DT1_RED_UPMETHOD_S 4 +/** MCPWM_DT1_DEB_MODE : R/W; bitpos: [8]; default: 0; + * S8 in table, dual-edge B mode, 0: fed/red take effect on different path separately, + * 1: fed/red take effect on B path, A out is in bypass or dulpB mode + */ +#define MCPWM_DT1_DEB_MODE (BIT(8)) +#define MCPWM_DT1_DEB_MODE_M (MCPWM_DT1_DEB_MODE_V << MCPWM_DT1_DEB_MODE_S) +#define MCPWM_DT1_DEB_MODE_V 0x00000001U +#define MCPWM_DT1_DEB_MODE_S 8 +/** MCPWM_DT1_A_OUTSWAP : R/W; bitpos: [9]; default: 0; + * S6 in table + */ +#define MCPWM_DT1_A_OUTSWAP (BIT(9)) +#define MCPWM_DT1_A_OUTSWAP_M (MCPWM_DT1_A_OUTSWAP_V << MCPWM_DT1_A_OUTSWAP_S) +#define MCPWM_DT1_A_OUTSWAP_V 0x00000001U +#define MCPWM_DT1_A_OUTSWAP_S 9 +/** MCPWM_DT1_B_OUTSWAP : R/W; bitpos: [10]; default: 0; + * S7 in table + */ +#define MCPWM_DT1_B_OUTSWAP (BIT(10)) +#define MCPWM_DT1_B_OUTSWAP_M (MCPWM_DT1_B_OUTSWAP_V << MCPWM_DT1_B_OUTSWAP_S) +#define MCPWM_DT1_B_OUTSWAP_V 0x00000001U +#define MCPWM_DT1_B_OUTSWAP_S 10 +/** MCPWM_DT1_RED_INSEL : R/W; bitpos: [11]; default: 0; + * S4 in table + */ +#define MCPWM_DT1_RED_INSEL (BIT(11)) +#define MCPWM_DT1_RED_INSEL_M (MCPWM_DT1_RED_INSEL_V << MCPWM_DT1_RED_INSEL_S) +#define MCPWM_DT1_RED_INSEL_V 0x00000001U +#define MCPWM_DT1_RED_INSEL_S 11 +/** MCPWM_DT1_FED_INSEL : R/W; bitpos: [12]; default: 0; + * S5 in table + */ +#define MCPWM_DT1_FED_INSEL (BIT(12)) +#define MCPWM_DT1_FED_INSEL_M (MCPWM_DT1_FED_INSEL_V << MCPWM_DT1_FED_INSEL_S) +#define MCPWM_DT1_FED_INSEL_V 0x00000001U +#define MCPWM_DT1_FED_INSEL_S 12 +/** MCPWM_DT1_RED_OUTINVERT : R/W; bitpos: [13]; default: 0; + * S2 in table + */ +#define MCPWM_DT1_RED_OUTINVERT (BIT(13)) +#define MCPWM_DT1_RED_OUTINVERT_M (MCPWM_DT1_RED_OUTINVERT_V << MCPWM_DT1_RED_OUTINVERT_S) +#define MCPWM_DT1_RED_OUTINVERT_V 0x00000001U +#define MCPWM_DT1_RED_OUTINVERT_S 13 +/** MCPWM_DT1_FED_OUTINVERT : R/W; bitpos: [14]; default: 0; + * S3 in table + */ +#define MCPWM_DT1_FED_OUTINVERT (BIT(14)) +#define MCPWM_DT1_FED_OUTINVERT_M (MCPWM_DT1_FED_OUTINVERT_V << MCPWM_DT1_FED_OUTINVERT_S) +#define MCPWM_DT1_FED_OUTINVERT_V 0x00000001U +#define MCPWM_DT1_FED_OUTINVERT_S 14 +/** MCPWM_DT1_A_OUTBYPASS : R/W; bitpos: [15]; default: 1; + * S1 in table + */ +#define MCPWM_DT1_A_OUTBYPASS (BIT(15)) +#define MCPWM_DT1_A_OUTBYPASS_M (MCPWM_DT1_A_OUTBYPASS_V << MCPWM_DT1_A_OUTBYPASS_S) +#define MCPWM_DT1_A_OUTBYPASS_V 0x00000001U +#define MCPWM_DT1_A_OUTBYPASS_S 15 +/** MCPWM_DT1_B_OUTBYPASS : R/W; bitpos: [16]; default: 1; + * S0 in table + */ +#define MCPWM_DT1_B_OUTBYPASS (BIT(16)) +#define MCPWM_DT1_B_OUTBYPASS_M (MCPWM_DT1_B_OUTBYPASS_V << MCPWM_DT1_B_OUTBYPASS_S) +#define MCPWM_DT1_B_OUTBYPASS_V 0x00000001U +#define MCPWM_DT1_B_OUTBYPASS_S 16 +/** MCPWM_DT1_CLK_SEL : R/W; bitpos: [17]; default: 0; + * Dead time clock selection. 0: PWM_clk, 1: PT_clk + */ +#define MCPWM_DT1_CLK_SEL (BIT(17)) +#define MCPWM_DT1_CLK_SEL_M (MCPWM_DT1_CLK_SEL_V << MCPWM_DT1_CLK_SEL_S) +#define MCPWM_DT1_CLK_SEL_V 0x00000001U +#define MCPWM_DT1_CLK_SEL_S 17 + +/** MCPWM_DT1_FED_CFG_REG register + * PWM generator 1 shadow register for falling edge delay (FED). + */ +#define MCPWM_DT1_FED_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0x94) +/** MCPWM_DT1_FED : R/W; bitpos: [15:0]; default: 0; + * Shadow register for FED + */ +#define MCPWM_DT1_FED 0x0000FFFFU +#define MCPWM_DT1_FED_M (MCPWM_DT1_FED_V << MCPWM_DT1_FED_S) +#define MCPWM_DT1_FED_V 0x0000FFFFU +#define MCPWM_DT1_FED_S 0 + +/** MCPWM_DT1_RED_CFG_REG register + * PWM generator 1 shadow register for rising edge delay (RED). + */ +#define MCPWM_DT1_RED_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0x98) +/** MCPWM_DT1_RED : R/W; bitpos: [15:0]; default: 0; + * Shadow register for RED + */ +#define MCPWM_DT1_RED 0x0000FFFFU +#define MCPWM_DT1_RED_M (MCPWM_DT1_RED_V << MCPWM_DT1_RED_S) +#define MCPWM_DT1_RED_V 0x0000FFFFU +#define MCPWM_DT1_RED_S 0 + +/** MCPWM_CARRIER1_CFG_REG register + * PWM generator 1 carrier enable and configuratoin + */ +#define MCPWM_CARRIER1_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0x9c) +/** MCPWM_CARRIER1_EN : R/W; bitpos: [0]; default: 0; + * When set, carrier1 function is enabled. When cleared, carrier1 is bypassed + */ +#define MCPWM_CARRIER1_EN (BIT(0)) +#define MCPWM_CARRIER1_EN_M (MCPWM_CARRIER1_EN_V << MCPWM_CARRIER1_EN_S) +#define MCPWM_CARRIER1_EN_V 0x00000001U +#define MCPWM_CARRIER1_EN_S 0 +/** MCPWM_CARRIER1_PRESCALE : R/W; bitpos: [4:1]; default: 0; + * PWM carrier1 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk * + * (PWM_CARRIER0_PRESCALE + 1) + */ +#define MCPWM_CARRIER1_PRESCALE 0x0000000FU +#define MCPWM_CARRIER1_PRESCALE_M (MCPWM_CARRIER1_PRESCALE_V << MCPWM_CARRIER1_PRESCALE_S) +#define MCPWM_CARRIER1_PRESCALE_V 0x0000000FU +#define MCPWM_CARRIER1_PRESCALE_S 1 +/** MCPWM_CARRIER1_DUTY : R/W; bitpos: [7:5]; default: 0; + * carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8 + */ +#define MCPWM_CARRIER1_DUTY 0x00000007U +#define MCPWM_CARRIER1_DUTY_M (MCPWM_CARRIER1_DUTY_V << MCPWM_CARRIER1_DUTY_S) +#define MCPWM_CARRIER1_DUTY_V 0x00000007U +#define MCPWM_CARRIER1_DUTY_S 5 +/** MCPWM_CARRIER1_OSHTWTH : R/W; bitpos: [11:8]; default: 0; + * width of the first pulse in number of periods of the carrier + */ +#define MCPWM_CARRIER1_OSHTWTH 0x0000000FU +#define MCPWM_CARRIER1_OSHTWTH_M (MCPWM_CARRIER1_OSHTWTH_V << MCPWM_CARRIER1_OSHTWTH_S) +#define MCPWM_CARRIER1_OSHTWTH_V 0x0000000FU +#define MCPWM_CARRIER1_OSHTWTH_S 8 +/** MCPWM_CARRIER1_OUT_INVERT : R/W; bitpos: [12]; default: 0; + * when set, invert the output of PWM1A and PWM1B for this submodule + */ +#define MCPWM_CARRIER1_OUT_INVERT (BIT(12)) +#define MCPWM_CARRIER1_OUT_INVERT_M (MCPWM_CARRIER1_OUT_INVERT_V << MCPWM_CARRIER1_OUT_INVERT_S) +#define MCPWM_CARRIER1_OUT_INVERT_V 0x00000001U +#define MCPWM_CARRIER1_OUT_INVERT_S 12 +/** MCPWM_CARRIER1_IN_INVERT : R/W; bitpos: [13]; default: 0; + * when set, invert the input of PWM1A and PWM1B for this submodule + */ +#define MCPWM_CARRIER1_IN_INVERT (BIT(13)) +#define MCPWM_CARRIER1_IN_INVERT_M (MCPWM_CARRIER1_IN_INVERT_V << MCPWM_CARRIER1_IN_INVERT_S) +#define MCPWM_CARRIER1_IN_INVERT_V 0x00000001U +#define MCPWM_CARRIER1_IN_INVERT_S 13 + +/** MCPWM_FH1_CFG0_REG register + * Actions on PWM1A and PWM1B trip events + */ +#define MCPWM_FH1_CFG0_REG(i) (DR_REG_MCPWM_BASE(i) + 0xa0) +/** MCPWM_FH1_SW_CBC : R/W; bitpos: [0]; default: 0; + * Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable + */ +#define MCPWM_FH1_SW_CBC (BIT(0)) +#define MCPWM_FH1_SW_CBC_M (MCPWM_FH1_SW_CBC_V << MCPWM_FH1_SW_CBC_S) +#define MCPWM_FH1_SW_CBC_V 0x00000001U +#define MCPWM_FH1_SW_CBC_S 0 +/** MCPWM_FH1_F2_CBC : R/W; bitpos: [1]; default: 0; + * fault_event2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + */ +#define MCPWM_FH1_F2_CBC (BIT(1)) +#define MCPWM_FH1_F2_CBC_M (MCPWM_FH1_F2_CBC_V << MCPWM_FH1_F2_CBC_S) +#define MCPWM_FH1_F2_CBC_V 0x00000001U +#define MCPWM_FH1_F2_CBC_S 1 +/** MCPWM_FH1_F1_CBC : R/W; bitpos: [2]; default: 0; + * fault_event1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + */ +#define MCPWM_FH1_F1_CBC (BIT(2)) +#define MCPWM_FH1_F1_CBC_M (MCPWM_FH1_F1_CBC_V << MCPWM_FH1_F1_CBC_S) +#define MCPWM_FH1_F1_CBC_V 0x00000001U +#define MCPWM_FH1_F1_CBC_S 2 +/** MCPWM_FH1_F0_CBC : R/W; bitpos: [3]; default: 0; + * fault_event0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + */ +#define MCPWM_FH1_F0_CBC (BIT(3)) +#define MCPWM_FH1_F0_CBC_M (MCPWM_FH1_F0_CBC_V << MCPWM_FH1_F0_CBC_S) +#define MCPWM_FH1_F0_CBC_V 0x00000001U +#define MCPWM_FH1_F0_CBC_S 3 +/** MCPWM_FH1_SW_OST : R/W; bitpos: [4]; default: 0; + * Enable register for software force one-shot mode action. 0: disable, 1: enable + */ +#define MCPWM_FH1_SW_OST (BIT(4)) +#define MCPWM_FH1_SW_OST_M (MCPWM_FH1_SW_OST_V << MCPWM_FH1_SW_OST_S) +#define MCPWM_FH1_SW_OST_V 0x00000001U +#define MCPWM_FH1_SW_OST_S 4 +/** MCPWM_FH1_F2_OST : R/W; bitpos: [5]; default: 0; + * fault_event2 will trigger one-shot mode action. 0: disable, 1: enable + */ +#define MCPWM_FH1_F2_OST (BIT(5)) +#define MCPWM_FH1_F2_OST_M (MCPWM_FH1_F2_OST_V << MCPWM_FH1_F2_OST_S) +#define MCPWM_FH1_F2_OST_V 0x00000001U +#define MCPWM_FH1_F2_OST_S 5 +/** MCPWM_FH1_F1_OST : R/W; bitpos: [6]; default: 0; + * fault_event1 will trigger one-shot mode action. 0: disable, 1: enable + */ +#define MCPWM_FH1_F1_OST (BIT(6)) +#define MCPWM_FH1_F1_OST_M (MCPWM_FH1_F1_OST_V << MCPWM_FH1_F1_OST_S) +#define MCPWM_FH1_F1_OST_V 0x00000001U +#define MCPWM_FH1_F1_OST_S 6 +/** MCPWM_FH1_F0_OST : R/W; bitpos: [7]; default: 0; + * fault_event0 will trigger one-shot mode action. 0: disable, 1: enable + */ +#define MCPWM_FH1_F0_OST (BIT(7)) +#define MCPWM_FH1_F0_OST_M (MCPWM_FH1_F0_OST_V << MCPWM_FH1_F0_OST_S) +#define MCPWM_FH1_F0_OST_V 0x00000001U +#define MCPWM_FH1_F0_OST_S 7 +/** MCPWM_FH1_A_CBC_D : R/W; bitpos: [9:8]; default: 0; + * Cycle-by-cycle mode action on PWM1A when fault event occurs and timer is + * decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_FH1_A_CBC_D 0x00000003U +#define MCPWM_FH1_A_CBC_D_M (MCPWM_FH1_A_CBC_D_V << MCPWM_FH1_A_CBC_D_S) +#define MCPWM_FH1_A_CBC_D_V 0x00000003U +#define MCPWM_FH1_A_CBC_D_S 8 +/** MCPWM_FH1_A_CBC_U : R/W; bitpos: [11:10]; default: 0; + * Cycle-by-cycle mode action on PWM1A when fault event occurs and timer is + * increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_FH1_A_CBC_U 0x00000003U +#define MCPWM_FH1_A_CBC_U_M (MCPWM_FH1_A_CBC_U_V << MCPWM_FH1_A_CBC_U_S) +#define MCPWM_FH1_A_CBC_U_V 0x00000003U +#define MCPWM_FH1_A_CBC_U_S 10 +/** MCPWM_FH1_A_OST_D : R/W; bitpos: [13:12]; default: 0; + * One-shot mode action on PWM1A when fault event occurs and timer is decreasing. 0: + * do nothing,1: force low, 2: force high, 3: toggle + */ +#define MCPWM_FH1_A_OST_D 0x00000003U +#define MCPWM_FH1_A_OST_D_M (MCPWM_FH1_A_OST_D_V << MCPWM_FH1_A_OST_D_S) +#define MCPWM_FH1_A_OST_D_V 0x00000003U +#define MCPWM_FH1_A_OST_D_S 12 +/** MCPWM_FH1_A_OST_U : R/W; bitpos: [15:14]; default: 0; + * One-shot mode action on PWM1A when fault event occurs and timer is increasing. 0: + * do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_FH1_A_OST_U 0x00000003U +#define MCPWM_FH1_A_OST_U_M (MCPWM_FH1_A_OST_U_V << MCPWM_FH1_A_OST_U_S) +#define MCPWM_FH1_A_OST_U_V 0x00000003U +#define MCPWM_FH1_A_OST_U_S 14 +/** MCPWM_FH1_B_CBC_D : R/W; bitpos: [17:16]; default: 0; + * Cycle-by-cycle mode action on PWM1B when fault event occurs and timer is + * decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_FH1_B_CBC_D 0x00000003U +#define MCPWM_FH1_B_CBC_D_M (MCPWM_FH1_B_CBC_D_V << MCPWM_FH1_B_CBC_D_S) +#define MCPWM_FH1_B_CBC_D_V 0x00000003U +#define MCPWM_FH1_B_CBC_D_S 16 +/** MCPWM_FH1_B_CBC_U : R/W; bitpos: [19:18]; default: 0; + * Cycle-by-cycle mode action on PWM1B when fault event occurs and timer is + * increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_FH1_B_CBC_U 0x00000003U +#define MCPWM_FH1_B_CBC_U_M (MCPWM_FH1_B_CBC_U_V << MCPWM_FH1_B_CBC_U_S) +#define MCPWM_FH1_B_CBC_U_V 0x00000003U +#define MCPWM_FH1_B_CBC_U_S 18 +/** MCPWM_FH1_B_OST_D : R/W; bitpos: [21:20]; default: 0; + * One-shot mode action on PWM1B when fault event occurs and timer is decreasing. 0: + * do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_FH1_B_OST_D 0x00000003U +#define MCPWM_FH1_B_OST_D_M (MCPWM_FH1_B_OST_D_V << MCPWM_FH1_B_OST_D_S) +#define MCPWM_FH1_B_OST_D_V 0x00000003U +#define MCPWM_FH1_B_OST_D_S 20 +/** MCPWM_FH1_B_OST_U : R/W; bitpos: [23:22]; default: 0; + * One-shot mode action on PWM1B when fault event occurs and timer is increasing. 0: + * do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_FH1_B_OST_U 0x00000003U +#define MCPWM_FH1_B_OST_U_M (MCPWM_FH1_B_OST_U_V << MCPWM_FH1_B_OST_U_S) +#define MCPWM_FH1_B_OST_U_V 0x00000003U +#define MCPWM_FH1_B_OST_U_S 22 + +/** MCPWM_FH1_CFG1_REG register + * Software triggers for fault handler actions + */ +#define MCPWM_FH1_CFG1_REG(i) (DR_REG_MCPWM_BASE(i) + 0xa4) +/** MCPWM_FH1_CLR_OST : R/W; bitpos: [0]; default: 0; + * a rising edge will clear on going one-shot mode action + */ +#define MCPWM_FH1_CLR_OST (BIT(0)) +#define MCPWM_FH1_CLR_OST_M (MCPWM_FH1_CLR_OST_V << MCPWM_FH1_CLR_OST_S) +#define MCPWM_FH1_CLR_OST_V 0x00000001U +#define MCPWM_FH1_CLR_OST_S 0 +/** MCPWM_FH1_CBCPULSE : R/W; bitpos: [2:1]; default: 0; + * cycle-by-cycle mode action refresh moment selection. When bit0 is set to 1: TEZ, + * when bit1 is set to 1:TEP + */ +#define MCPWM_FH1_CBCPULSE 0x00000003U +#define MCPWM_FH1_CBCPULSE_M (MCPWM_FH1_CBCPULSE_V << MCPWM_FH1_CBCPULSE_S) +#define MCPWM_FH1_CBCPULSE_V 0x00000003U +#define MCPWM_FH1_CBCPULSE_S 1 +/** MCPWM_FH1_FORCE_CBC : R/W; bitpos: [3]; default: 0; + * a toggle trigger a cycle-by-cycle mode action + */ +#define MCPWM_FH1_FORCE_CBC (BIT(3)) +#define MCPWM_FH1_FORCE_CBC_M (MCPWM_FH1_FORCE_CBC_V << MCPWM_FH1_FORCE_CBC_S) +#define MCPWM_FH1_FORCE_CBC_V 0x00000001U +#define MCPWM_FH1_FORCE_CBC_S 3 +/** MCPWM_FH1_FORCE_OST : R/W; bitpos: [4]; default: 0; + * a toggle (software negate its value) triggers a one-shot mode action + */ +#define MCPWM_FH1_FORCE_OST (BIT(4)) +#define MCPWM_FH1_FORCE_OST_M (MCPWM_FH1_FORCE_OST_V << MCPWM_FH1_FORCE_OST_S) +#define MCPWM_FH1_FORCE_OST_V 0x00000001U +#define MCPWM_FH1_FORCE_OST_S 4 + +/** MCPWM_FH1_STATUS_REG register + * Status of fault events. + */ +#define MCPWM_FH1_STATUS_REG(i) (DR_REG_MCPWM_BASE(i) + 0xa8) +/** MCPWM_FH1_CBC_ON : RO; bitpos: [0]; default: 0; + * Set and reset by hardware. If set, a cycle-by-cycle mode action is on going + */ +#define MCPWM_FH1_CBC_ON (BIT(0)) +#define MCPWM_FH1_CBC_ON_M (MCPWM_FH1_CBC_ON_V << MCPWM_FH1_CBC_ON_S) +#define MCPWM_FH1_CBC_ON_V 0x00000001U +#define MCPWM_FH1_CBC_ON_S 0 +/** MCPWM_FH1_OST_ON : RO; bitpos: [1]; default: 0; + * Set and reset by hardware. If set, an one-shot mode action is on going + */ +#define MCPWM_FH1_OST_ON (BIT(1)) +#define MCPWM_FH1_OST_ON_M (MCPWM_FH1_OST_ON_V << MCPWM_FH1_OST_ON_S) +#define MCPWM_FH1_OST_ON_V 0x00000001U +#define MCPWM_FH1_OST_ON_S 1 + +/** MCPWM_GEN2_STMP_CFG_REG register + * Transfer status and update method for time stamp registers A and B + */ +#define MCPWM_GEN2_STMP_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0xac) +/** MCPWM_GEN2_A_UPMETHOD : R/W; bitpos: [3:0]; default: 0; + * Update method for PWM generator 2 time stamp A's active register. When all bits are + * set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when + * bit2 is set to 1: sync, when bit3 is set to 1: disable the update. + */ +#define MCPWM_GEN2_A_UPMETHOD 0x0000000FU +#define MCPWM_GEN2_A_UPMETHOD_M (MCPWM_GEN2_A_UPMETHOD_V << MCPWM_GEN2_A_UPMETHOD_S) +#define MCPWM_GEN2_A_UPMETHOD_V 0x0000000FU +#define MCPWM_GEN2_A_UPMETHOD_S 0 +/** MCPWM_GEN2_B_UPMETHOD : R/W; bitpos: [7:4]; default: 0; + * Update method for PWM generator 2 time stamp B's active register. When all bits are + * set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when + * bit2 is set to 1: sync, when bit3 is set to 1: disable the update. + */ +#define MCPWM_GEN2_B_UPMETHOD 0x0000000FU +#define MCPWM_GEN2_B_UPMETHOD_M (MCPWM_GEN2_B_UPMETHOD_V << MCPWM_GEN2_B_UPMETHOD_S) +#define MCPWM_GEN2_B_UPMETHOD_V 0x0000000FU +#define MCPWM_GEN2_B_UPMETHOD_S 4 +/** MCPWM_GEN2_A_SHDW_FULL : R/W/WTC/SC; bitpos: [8]; default: 0; + * Set and reset by hardware. If set, PWM generator 2 time stamp A's shadow reg is + * filled and waiting to be transferred to A's active reg. If cleared, A's active reg + * has been updated with shadow register latest value + */ +#define MCPWM_GEN2_A_SHDW_FULL (BIT(8)) +#define MCPWM_GEN2_A_SHDW_FULL_M (MCPWM_GEN2_A_SHDW_FULL_V << MCPWM_GEN2_A_SHDW_FULL_S) +#define MCPWM_GEN2_A_SHDW_FULL_V 0x00000001U +#define MCPWM_GEN2_A_SHDW_FULL_S 8 +/** MCPWM_GEN2_B_SHDW_FULL : R/W/WTC/SC; bitpos: [9]; default: 0; + * Set and reset by hardware. If set, PWM generator 2 time stamp B's shadow reg is + * filled and waiting to be transferred to B's active reg. If cleared, B's active reg + * has been updated with shadow register latest value + */ +#define MCPWM_GEN2_B_SHDW_FULL (BIT(9)) +#define MCPWM_GEN2_B_SHDW_FULL_M (MCPWM_GEN2_B_SHDW_FULL_V << MCPWM_GEN2_B_SHDW_FULL_S) +#define MCPWM_GEN2_B_SHDW_FULL_V 0x00000001U +#define MCPWM_GEN2_B_SHDW_FULL_S 9 + +/** MCPWM_GEN2_TSTMP_A_REG register + * PWM generator 2 shadow register for timer stamp A. + */ +#define MCPWM_GEN2_TSTMP_A_REG(i) (DR_REG_MCPWM_BASE(i) + 0xb0) +/** MCPWM_GEN2_A : R/W; bitpos: [15:0]; default: 0; + * PWM generator 2 time stamp A's shadow register + */ +#define MCPWM_GEN2_A 0x0000FFFFU +#define MCPWM_GEN2_A_M (MCPWM_GEN2_A_V << MCPWM_GEN2_A_S) +#define MCPWM_GEN2_A_V 0x0000FFFFU +#define MCPWM_GEN2_A_S 0 + +/** MCPWM_GEN2_TSTMP_B_REG register + * PWM generator 2 shadow register for timer stamp A. + */ +#define MCPWM_GEN2_TSTMP_B_REG(i) (DR_REG_MCPWM_BASE(i) + 0xb4) +/** MCPWM_GEN2_B : R/W; bitpos: [15:0]; default: 0; + * PWM generator 2 time stamp B's shadow register + */ +#define MCPWM_GEN2_B 0x0000FFFFU +#define MCPWM_GEN2_B_M (MCPWM_GEN2_B_V << MCPWM_GEN2_B_S) +#define MCPWM_GEN2_B_V 0x0000FFFFU +#define MCPWM_GEN2_B_S 0 + +/** MCPWM_GEN2_CFG0_REG register + * PWM generator 2 event T0 and T1 handling + */ +#define MCPWM_GEN2_CFG0_REG(i) (DR_REG_MCPWM_BASE(i) + 0xb8) +/** MCPWM_GEN2_CFG_UPMETHOD : R/W; bitpos: [3:0]; default: 0; + * Update method for PWM generator 2's active register of configuration. 0: + * immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1:sync;when bit3 is + * set to 1:disable the update. + */ +#define MCPWM_GEN2_CFG_UPMETHOD 0x0000000FU +#define MCPWM_GEN2_CFG_UPMETHOD_M (MCPWM_GEN2_CFG_UPMETHOD_V << MCPWM_GEN2_CFG_UPMETHOD_S) +#define MCPWM_GEN2_CFG_UPMETHOD_V 0x0000000FU #define MCPWM_GEN2_CFG_UPMETHOD_S 0 +/** MCPWM_GEN2_T0_SEL : R/W; bitpos: [6:4]; default: 0; + * Source selection for PWM generator 2 event_t0, take effect immediately, 0: + * fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none + */ +#define MCPWM_GEN2_T0_SEL 0x00000007U +#define MCPWM_GEN2_T0_SEL_M (MCPWM_GEN2_T0_SEL_V << MCPWM_GEN2_T0_SEL_S) +#define MCPWM_GEN2_T0_SEL_V 0x00000007U +#define MCPWM_GEN2_T0_SEL_S 4 +/** MCPWM_GEN2_T1_SEL : R/W; bitpos: [9:7]; default: 0; + * Source selection for PWM generator 2 event_t1, take effect immediately, 0: + * fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none + */ +#define MCPWM_GEN2_T1_SEL 0x00000007U +#define MCPWM_GEN2_T1_SEL_M (MCPWM_GEN2_T1_SEL_V << MCPWM_GEN2_T1_SEL_S) +#define MCPWM_GEN2_T1_SEL_V 0x00000007U +#define MCPWM_GEN2_T1_SEL_S 7 -#define MCPWM_GEN2_FORCE_REG(i) (REG_MCPWM_BASE(i) + 0xBC) -/* MCPWM_GEN2_B_NCIFORCE_MODE : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ -/*description: 0: disabled, 1: low, 2: high, 3: disabled.*/ -#define MCPWM_GEN2_B_NCIFORCE_MODE 0x00000003 -#define MCPWM_GEN2_B_NCIFORCE_MODE_M ((MCPWM_GEN2_B_NCIFORCE_MODE_V)<<(MCPWM_GEN2_B_NCIFORCE_MODE_S)) -#define MCPWM_GEN2_B_NCIFORCE_MODE_V 0x3 -#define MCPWM_GEN2_B_NCIFORCE_MODE_S 14 -/* MCPWM_GEN2_B_NCIFORCE : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: non-continuous immediate sw force, a toggle will trigger a force event.*/ -#define MCPWM_GEN2_B_NCIFORCE (BIT(13)) -#define MCPWM_GEN2_B_NCIFORCE_M (BIT(13)) -#define MCPWM_GEN2_B_NCIFORCE_V 0x1 -#define MCPWM_GEN2_B_NCIFORCE_S 13 -/* MCPWM_GEN2_A_NCIFORCE_MODE : R/W ;bitpos:[12:11] ;default: 2'd0 ; */ -/*description: 0: disabled, 1: low, 2: high, 3: disabled.*/ -#define MCPWM_GEN2_A_NCIFORCE_MODE 0x00000003 -#define MCPWM_GEN2_A_NCIFORCE_MODE_M ((MCPWM_GEN2_A_NCIFORCE_MODE_V)<<(MCPWM_GEN2_A_NCIFORCE_MODE_S)) -#define MCPWM_GEN2_A_NCIFORCE_MODE_V 0x3 -#define MCPWM_GEN2_A_NCIFORCE_MODE_S 11 -/* MCPWM_GEN2_A_NCIFORCE : R/W ;bitpos:[10] ;default: 1'd0 ; */ -/*description: non-continuous immediate sw force, a toggle will trigger a force event.*/ +/** MCPWM_GEN2_FORCE_REG register + * Permissives to force PWM2A and PWM2B outputs by software + */ +#define MCPWM_GEN2_FORCE_REG(i) (DR_REG_MCPWM_BASE(i) + 0xbc) +/** MCPWM_GEN2_CNTUFORCE_UPMETHOD : R/W; bitpos: [5:0]; default: 32; + * Updating method for continuous software force of PWM generator 2. When all bits are + * set to 0: immediately, when bit0 is set to 1: TEZ,when bit1 is set to 1: TEP, when + * bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync, + * when bit5 is set to 1: disable update. (TEA/B here and below means an event + * generated when the timer's value equals to that of register A/B.) + */ +#define MCPWM_GEN2_CNTUFORCE_UPMETHOD 0x0000003FU +#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_M (MCPWM_GEN2_CNTUFORCE_UPMETHOD_V << MCPWM_GEN2_CNTUFORCE_UPMETHOD_S) +#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_V 0x0000003FU +#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_S 0 +/** MCPWM_GEN2_A_CNTUFORCE_MODE : R/W; bitpos: [7:6]; default: 0; + * Continuous software force mode for PWM2A. 0: disabled, 1: low, 2: high, 3: disabled + */ +#define MCPWM_GEN2_A_CNTUFORCE_MODE 0x00000003U +#define MCPWM_GEN2_A_CNTUFORCE_MODE_M (MCPWM_GEN2_A_CNTUFORCE_MODE_V << MCPWM_GEN2_A_CNTUFORCE_MODE_S) +#define MCPWM_GEN2_A_CNTUFORCE_MODE_V 0x00000003U +#define MCPWM_GEN2_A_CNTUFORCE_MODE_S 6 +/** MCPWM_GEN2_B_CNTUFORCE_MODE : R/W; bitpos: [9:8]; default: 0; + * Continuous software force mode for PWM2B. 0: disabled, 1: low, 2: high, 3: disabled + */ +#define MCPWM_GEN2_B_CNTUFORCE_MODE 0x00000003U +#define MCPWM_GEN2_B_CNTUFORCE_MODE_M (MCPWM_GEN2_B_CNTUFORCE_MODE_V << MCPWM_GEN2_B_CNTUFORCE_MODE_S) +#define MCPWM_GEN2_B_CNTUFORCE_MODE_V 0x00000003U +#define MCPWM_GEN2_B_CNTUFORCE_MODE_S 8 +/** MCPWM_GEN2_A_NCIFORCE : R/W; bitpos: [10]; default: 0; + * Trigger of non-continuous immediate software-force event for PWM2A, a toggle will + * trigger a force event. + */ #define MCPWM_GEN2_A_NCIFORCE (BIT(10)) -#define MCPWM_GEN2_A_NCIFORCE_M (BIT(10)) -#define MCPWM_GEN2_A_NCIFORCE_V 0x1 +#define MCPWM_GEN2_A_NCIFORCE_M (MCPWM_GEN2_A_NCIFORCE_V << MCPWM_GEN2_A_NCIFORCE_S) +#define MCPWM_GEN2_A_NCIFORCE_V 0x00000001U #define MCPWM_GEN2_A_NCIFORCE_S 10 -/* MCPWM_GEN2_B_CNTUFORCE_MODE : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ -/*description: 0: disabled, 1: low, 2: high, 3: disabled.*/ -#define MCPWM_GEN2_B_CNTUFORCE_MODE 0x00000003 -#define MCPWM_GEN2_B_CNTUFORCE_MODE_M ((MCPWM_GEN2_B_CNTUFORCE_MODE_V)<<(MCPWM_GEN2_B_CNTUFORCE_MODE_S)) -#define MCPWM_GEN2_B_CNTUFORCE_MODE_V 0x3 -#define MCPWM_GEN2_B_CNTUFORCE_MODE_S 8 -/* MCPWM_GEN2_A_CNTUFORCE_MODE : R/W ;bitpos:[7:6] ;default: 2'd0 ; */ -/*description: 0: disabled, 1: low, 2: high, 3: disabled.*/ -#define MCPWM_GEN2_A_CNTUFORCE_MODE 0x00000003 -#define MCPWM_GEN2_A_CNTUFORCE_MODE_M ((MCPWM_GEN2_A_CNTUFORCE_MODE_V)<<(MCPWM_GEN2_A_CNTUFORCE_MODE_S)) -#define MCPWM_GEN2_A_CNTUFORCE_MODE_V 0x3 -#define MCPWM_GEN2_A_CNTUFORCE_MODE_S 6 -/* MCPWM_GEN2_CNTUFORCE_UPMETHOD : R/W ;bitpos:[5:0] ;default: 6'h20 ; */ -/*description: 0: immediate, bit0: tez, bit1: tep, bit2: tea, bit3: teb, bit4: sync, bit5: free -ze.*/ -#define MCPWM_GEN2_CNTUFORCE_UPMETHOD 0x0000003F -#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_M ((MCPWM_GEN2_CNTUFORCE_UPMETHOD_V)<<(MCPWM_GEN2_CNTUFORCE_UPMETHOD_S)) -#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_V 0x3F -#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_S 0 +/** MCPWM_GEN2_A_NCIFORCE_MODE : R/W; bitpos: [12:11]; default: 0; + * non-continuous immediate software force mode for PWM2A, 0: disabled, 1: low, 2: + * high, 3: disabled + */ +#define MCPWM_GEN2_A_NCIFORCE_MODE 0x00000003U +#define MCPWM_GEN2_A_NCIFORCE_MODE_M (MCPWM_GEN2_A_NCIFORCE_MODE_V << MCPWM_GEN2_A_NCIFORCE_MODE_S) +#define MCPWM_GEN2_A_NCIFORCE_MODE_V 0x00000003U +#define MCPWM_GEN2_A_NCIFORCE_MODE_S 11 +/** MCPWM_GEN2_B_NCIFORCE : R/W; bitpos: [13]; default: 0; + * Trigger of non-continuous immediate software-force event for PWM2B, a toggle will + * trigger a force event. + */ +#define MCPWM_GEN2_B_NCIFORCE (BIT(13)) +#define MCPWM_GEN2_B_NCIFORCE_M (MCPWM_GEN2_B_NCIFORCE_V << MCPWM_GEN2_B_NCIFORCE_S) +#define MCPWM_GEN2_B_NCIFORCE_V 0x00000001U +#define MCPWM_GEN2_B_NCIFORCE_S 13 +/** MCPWM_GEN2_B_NCIFORCE_MODE : R/W; bitpos: [15:14]; default: 0; + * non-continuous immediate software force mode for PWM2B, 0: disabled, 1: low, 2: + * high, 3: disabled + */ +#define MCPWM_GEN2_B_NCIFORCE_MODE 0x00000003U +#define MCPWM_GEN2_B_NCIFORCE_MODE_M (MCPWM_GEN2_B_NCIFORCE_MODE_V << MCPWM_GEN2_B_NCIFORCE_MODE_S) +#define MCPWM_GEN2_B_NCIFORCE_MODE_V 0x00000003U +#define MCPWM_GEN2_B_NCIFORCE_MODE_S 14 -#define MCPWM_GEN2_A_REG(i) (REG_MCPWM_BASE(i) + 0xC0) -/* MCPWM_GEN2_A_DT1 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ -/*description: 0: no change, 1: low, 2: high, 3: toggle.*/ -#define MCPWM_GEN2_A_DT1 0x00000003 -#define MCPWM_GEN2_A_DT1_M ((MCPWM_GEN2_A_DT1_V)<<(MCPWM_GEN2_A_DT1_S)) -#define MCPWM_GEN2_A_DT1_V 0x3 -#define MCPWM_GEN2_A_DT1_S 22 -/* MCPWM_GEN2_A_DT0 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ -/*description: .*/ -#define MCPWM_GEN2_A_DT0 0x00000003 -#define MCPWM_GEN2_A_DT0_M ((MCPWM_GEN2_A_DT0_V)<<(MCPWM_GEN2_A_DT0_S)) -#define MCPWM_GEN2_A_DT0_V 0x3 -#define MCPWM_GEN2_A_DT0_S 20 -/* MCPWM_GEN2_A_DTEB : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ -/*description: .*/ -#define MCPWM_GEN2_A_DTEB 0x00000003 -#define MCPWM_GEN2_A_DTEB_M ((MCPWM_GEN2_A_DTEB_V)<<(MCPWM_GEN2_A_DTEB_S)) -#define MCPWM_GEN2_A_DTEB_V 0x3 -#define MCPWM_GEN2_A_DTEB_S 18 -/* MCPWM_GEN2_A_DTEA : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ -/*description: .*/ -#define MCPWM_GEN2_A_DTEA 0x00000003 -#define MCPWM_GEN2_A_DTEA_M ((MCPWM_GEN2_A_DTEA_V)<<(MCPWM_GEN2_A_DTEA_S)) -#define MCPWM_GEN2_A_DTEA_V 0x3 -#define MCPWM_GEN2_A_DTEA_S 16 -/* MCPWM_GEN2_A_DTEP : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ -/*description: .*/ -#define MCPWM_GEN2_A_DTEP 0x00000003 -#define MCPWM_GEN2_A_DTEP_M ((MCPWM_GEN2_A_DTEP_V)<<(MCPWM_GEN2_A_DTEP_S)) -#define MCPWM_GEN2_A_DTEP_V 0x3 -#define MCPWM_GEN2_A_DTEP_S 14 -/* MCPWM_GEN2_A_DTEZ : R/W ;bitpos:[13:12] ;default: 2'd0 ; */ -/*description: .*/ -#define MCPWM_GEN2_A_DTEZ 0x00000003 -#define MCPWM_GEN2_A_DTEZ_M ((MCPWM_GEN2_A_DTEZ_V)<<(MCPWM_GEN2_A_DTEZ_S)) -#define MCPWM_GEN2_A_DTEZ_V 0x3 -#define MCPWM_GEN2_A_DTEZ_S 12 -/* MCPWM_GEN2_A_UT1 : R/W ;bitpos:[11:10] ;default: 2'd0 ; */ -/*description: .*/ -#define MCPWM_GEN2_A_UT1 0x00000003 -#define MCPWM_GEN2_A_UT1_M ((MCPWM_GEN2_A_UT1_V)<<(MCPWM_GEN2_A_UT1_S)) -#define MCPWM_GEN2_A_UT1_V 0x3 -#define MCPWM_GEN2_A_UT1_S 10 -/* MCPWM_GEN2_A_UT0 : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ -/*description: .*/ -#define MCPWM_GEN2_A_UT0 0x00000003 -#define MCPWM_GEN2_A_UT0_M ((MCPWM_GEN2_A_UT0_V)<<(MCPWM_GEN2_A_UT0_S)) -#define MCPWM_GEN2_A_UT0_V 0x3 -#define MCPWM_GEN2_A_UT0_S 8 -/* MCPWM_GEN2_A_UTEB : R/W ;bitpos:[7:6] ;default: 2'd0 ; */ -/*description: .*/ -#define MCPWM_GEN2_A_UTEB 0x00000003 -#define MCPWM_GEN2_A_UTEB_M ((MCPWM_GEN2_A_UTEB_V)<<(MCPWM_GEN2_A_UTEB_S)) -#define MCPWM_GEN2_A_UTEB_V 0x3 -#define MCPWM_GEN2_A_UTEB_S 6 -/* MCPWM_GEN2_A_UTEA : R/W ;bitpos:[5:4] ;default: 2'd0 ; */ -/*description: .*/ -#define MCPWM_GEN2_A_UTEA 0x00000003 -#define MCPWM_GEN2_A_UTEA_M ((MCPWM_GEN2_A_UTEA_V)<<(MCPWM_GEN2_A_UTEA_S)) -#define MCPWM_GEN2_A_UTEA_V 0x3 -#define MCPWM_GEN2_A_UTEA_S 4 -/* MCPWM_GEN2_A_UTEP : R/W ;bitpos:[3:2] ;default: 2'd0 ; */ -/*description: .*/ -#define MCPWM_GEN2_A_UTEP 0x00000003 -#define MCPWM_GEN2_A_UTEP_M ((MCPWM_GEN2_A_UTEP_V)<<(MCPWM_GEN2_A_UTEP_S)) -#define MCPWM_GEN2_A_UTEP_V 0x3 -#define MCPWM_GEN2_A_UTEP_S 2 -/* MCPWM_GEN2_A_UTEZ : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: .*/ -#define MCPWM_GEN2_A_UTEZ 0x00000003 -#define MCPWM_GEN2_A_UTEZ_M ((MCPWM_GEN2_A_UTEZ_V)<<(MCPWM_GEN2_A_UTEZ_S)) -#define MCPWM_GEN2_A_UTEZ_V 0x3 +/** MCPWM_GEN2_A_REG register + * Actions triggered by events on PWM2A + */ +#define MCPWM_GEN2_A_REG(i) (DR_REG_MCPWM_BASE(i) + 0xc0) +/** MCPWM_GEN2_A_UTEZ : R/W; bitpos: [1:0]; default: 0; + * Action on PWM2A triggered by event TEZ when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN2_A_UTEZ 0x00000003U +#define MCPWM_GEN2_A_UTEZ_M (MCPWM_GEN2_A_UTEZ_V << MCPWM_GEN2_A_UTEZ_S) +#define MCPWM_GEN2_A_UTEZ_V 0x00000003U #define MCPWM_GEN2_A_UTEZ_S 0 +/** MCPWM_GEN2_A_UTEP : R/W; bitpos: [3:2]; default: 0; + * Action on PWM2A triggered by event TEP when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN2_A_UTEP 0x00000003U +#define MCPWM_GEN2_A_UTEP_M (MCPWM_GEN2_A_UTEP_V << MCPWM_GEN2_A_UTEP_S) +#define MCPWM_GEN2_A_UTEP_V 0x00000003U +#define MCPWM_GEN2_A_UTEP_S 2 +/** MCPWM_GEN2_A_UTEA : R/W; bitpos: [5:4]; default: 0; + * Action on PWM2A triggered by event TEA when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN2_A_UTEA 0x00000003U +#define MCPWM_GEN2_A_UTEA_M (MCPWM_GEN2_A_UTEA_V << MCPWM_GEN2_A_UTEA_S) +#define MCPWM_GEN2_A_UTEA_V 0x00000003U +#define MCPWM_GEN2_A_UTEA_S 4 +/** MCPWM_GEN2_A_UTEB : R/W; bitpos: [7:6]; default: 0; + * Action on PWM2A triggered by event TEB when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN2_A_UTEB 0x00000003U +#define MCPWM_GEN2_A_UTEB_M (MCPWM_GEN2_A_UTEB_V << MCPWM_GEN2_A_UTEB_S) +#define MCPWM_GEN2_A_UTEB_V 0x00000003U +#define MCPWM_GEN2_A_UTEB_S 6 +/** MCPWM_GEN2_A_UT0 : R/W; bitpos: [9:8]; default: 0; + * Action on PWM2A triggered by event_t0 when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN2_A_UT0 0x00000003U +#define MCPWM_GEN2_A_UT0_M (MCPWM_GEN2_A_UT0_V << MCPWM_GEN2_A_UT0_S) +#define MCPWM_GEN2_A_UT0_V 0x00000003U +#define MCPWM_GEN2_A_UT0_S 8 +/** MCPWM_GEN2_A_UT1 : R/W; bitpos: [11:10]; default: 0; + * Action on PWM2A triggered by event_t1 when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN2_A_UT1 0x00000003U +#define MCPWM_GEN2_A_UT1_M (MCPWM_GEN2_A_UT1_V << MCPWM_GEN2_A_UT1_S) +#define MCPWM_GEN2_A_UT1_V 0x00000003U +#define MCPWM_GEN2_A_UT1_S 10 +/** MCPWM_GEN2_A_DTEZ : R/W; bitpos: [13:12]; default: 0; + * Action on PWM2A triggered by event TEZ when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN2_A_DTEZ 0x00000003U +#define MCPWM_GEN2_A_DTEZ_M (MCPWM_GEN2_A_DTEZ_V << MCPWM_GEN2_A_DTEZ_S) +#define MCPWM_GEN2_A_DTEZ_V 0x00000003U +#define MCPWM_GEN2_A_DTEZ_S 12 +/** MCPWM_GEN2_A_DTEP : R/W; bitpos: [15:14]; default: 0; + * Action on PWM2A triggered by event TEP when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN2_A_DTEP 0x00000003U +#define MCPWM_GEN2_A_DTEP_M (MCPWM_GEN2_A_DTEP_V << MCPWM_GEN2_A_DTEP_S) +#define MCPWM_GEN2_A_DTEP_V 0x00000003U +#define MCPWM_GEN2_A_DTEP_S 14 +/** MCPWM_GEN2_A_DTEA : R/W; bitpos: [17:16]; default: 0; + * Action on PWM2A triggered by event TEA when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN2_A_DTEA 0x00000003U +#define MCPWM_GEN2_A_DTEA_M (MCPWM_GEN2_A_DTEA_V << MCPWM_GEN2_A_DTEA_S) +#define MCPWM_GEN2_A_DTEA_V 0x00000003U +#define MCPWM_GEN2_A_DTEA_S 16 +/** MCPWM_GEN2_A_DTEB : R/W; bitpos: [19:18]; default: 0; + * Action on PWM2A triggered by event TEB when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN2_A_DTEB 0x00000003U +#define MCPWM_GEN2_A_DTEB_M (MCPWM_GEN2_A_DTEB_V << MCPWM_GEN2_A_DTEB_S) +#define MCPWM_GEN2_A_DTEB_V 0x00000003U +#define MCPWM_GEN2_A_DTEB_S 18 +/** MCPWM_GEN2_A_DT0 : R/W; bitpos: [21:20]; default: 0; + * Action on PWM2A triggered by event_t0 when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN2_A_DT0 0x00000003U +#define MCPWM_GEN2_A_DT0_M (MCPWM_GEN2_A_DT0_V << MCPWM_GEN2_A_DT0_S) +#define MCPWM_GEN2_A_DT0_V 0x00000003U +#define MCPWM_GEN2_A_DT0_S 20 +/** MCPWM_GEN2_A_DT1 : R/W; bitpos: [23:22]; default: 0; + * Action on PWM2A triggered by event_t1 when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN2_A_DT1 0x00000003U +#define MCPWM_GEN2_A_DT1_M (MCPWM_GEN2_A_DT1_V << MCPWM_GEN2_A_DT1_S) +#define MCPWM_GEN2_A_DT1_V 0x00000003U +#define MCPWM_GEN2_A_DT1_S 22 -#define MCPWM_GEN2_B_REG(i) (REG_MCPWM_BASE(i) + 0xC4) -/* MCPWM_GEN2_B_DT1 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ -/*description: .*/ -#define MCPWM_GEN2_B_DT1 0x00000003 -#define MCPWM_GEN2_B_DT1_M ((MCPWM_GEN2_B_DT1_V)<<(MCPWM_GEN2_B_DT1_S)) -#define MCPWM_GEN2_B_DT1_V 0x3 -#define MCPWM_GEN2_B_DT1_S 22 -/* MCPWM_GEN2_B_DT0 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ -/*description: .*/ -#define MCPWM_GEN2_B_DT0 0x00000003 -#define MCPWM_GEN2_B_DT0_M ((MCPWM_GEN2_B_DT0_V)<<(MCPWM_GEN2_B_DT0_S)) -#define MCPWM_GEN2_B_DT0_V 0x3 -#define MCPWM_GEN2_B_DT0_S 20 -/* MCPWM_GEN2_B_DTEB : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ -/*description: .*/ -#define MCPWM_GEN2_B_DTEB 0x00000003 -#define MCPWM_GEN2_B_DTEB_M ((MCPWM_GEN2_B_DTEB_V)<<(MCPWM_GEN2_B_DTEB_S)) -#define MCPWM_GEN2_B_DTEB_V 0x3 -#define MCPWM_GEN2_B_DTEB_S 18 -/* MCPWM_GEN2_B_DTEA : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ -/*description: .*/ -#define MCPWM_GEN2_B_DTEA 0x00000003 -#define MCPWM_GEN2_B_DTEA_M ((MCPWM_GEN2_B_DTEA_V)<<(MCPWM_GEN2_B_DTEA_S)) -#define MCPWM_GEN2_B_DTEA_V 0x3 -#define MCPWM_GEN2_B_DTEA_S 16 -/* MCPWM_GEN2_B_DTEP : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ -/*description: .*/ -#define MCPWM_GEN2_B_DTEP 0x00000003 -#define MCPWM_GEN2_B_DTEP_M ((MCPWM_GEN2_B_DTEP_V)<<(MCPWM_GEN2_B_DTEP_S)) -#define MCPWM_GEN2_B_DTEP_V 0x3 -#define MCPWM_GEN2_B_DTEP_S 14 -/* MCPWM_GEN2_B_DTEZ : R/W ;bitpos:[13:12] ;default: 2'd0 ; */ -/*description: .*/ -#define MCPWM_GEN2_B_DTEZ 0x00000003 -#define MCPWM_GEN2_B_DTEZ_M ((MCPWM_GEN2_B_DTEZ_V)<<(MCPWM_GEN2_B_DTEZ_S)) -#define MCPWM_GEN2_B_DTEZ_V 0x3 -#define MCPWM_GEN2_B_DTEZ_S 12 -/* MCPWM_GEN2_B_UT1 : R/W ;bitpos:[11:10] ;default: 2'd0 ; */ -/*description: .*/ -#define MCPWM_GEN2_B_UT1 0x00000003 -#define MCPWM_GEN2_B_UT1_M ((MCPWM_GEN2_B_UT1_V)<<(MCPWM_GEN2_B_UT1_S)) -#define MCPWM_GEN2_B_UT1_V 0x3 -#define MCPWM_GEN2_B_UT1_S 10 -/* MCPWM_GEN2_B_UT0 : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ -/*description: .*/ -#define MCPWM_GEN2_B_UT0 0x00000003 -#define MCPWM_GEN2_B_UT0_M ((MCPWM_GEN2_B_UT0_V)<<(MCPWM_GEN2_B_UT0_S)) -#define MCPWM_GEN2_B_UT0_V 0x3 -#define MCPWM_GEN2_B_UT0_S 8 -/* MCPWM_GEN2_B_UTEB : R/W ;bitpos:[7:6] ;default: 2'd0 ; */ -/*description: .*/ -#define MCPWM_GEN2_B_UTEB 0x00000003 -#define MCPWM_GEN2_B_UTEB_M ((MCPWM_GEN2_B_UTEB_V)<<(MCPWM_GEN2_B_UTEB_S)) -#define MCPWM_GEN2_B_UTEB_V 0x3 -#define MCPWM_GEN2_B_UTEB_S 6 -/* MCPWM_GEN2_B_UTEA : R/W ;bitpos:[5:4] ;default: 2'd0 ; */ -/*description: .*/ -#define MCPWM_GEN2_B_UTEA 0x00000003 -#define MCPWM_GEN2_B_UTEA_M ((MCPWM_GEN2_B_UTEA_V)<<(MCPWM_GEN2_B_UTEA_S)) -#define MCPWM_GEN2_B_UTEA_V 0x3 -#define MCPWM_GEN2_B_UTEA_S 4 -/* MCPWM_GEN2_B_UTEP : R/W ;bitpos:[3:2] ;default: 2'd0 ; */ -/*description: .*/ -#define MCPWM_GEN2_B_UTEP 0x00000003 -#define MCPWM_GEN2_B_UTEP_M ((MCPWM_GEN2_B_UTEP_V)<<(MCPWM_GEN2_B_UTEP_S)) -#define MCPWM_GEN2_B_UTEP_V 0x3 -#define MCPWM_GEN2_B_UTEP_S 2 -/* MCPWM_GEN2_B_UTEZ : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: .*/ -#define MCPWM_GEN2_B_UTEZ 0x00000003 -#define MCPWM_GEN2_B_UTEZ_M ((MCPWM_GEN2_B_UTEZ_V)<<(MCPWM_GEN2_B_UTEZ_S)) -#define MCPWM_GEN2_B_UTEZ_V 0x3 +/** MCPWM_GEN2_B_REG register + * Actions triggered by events on PWM2B + */ +#define MCPWM_GEN2_B_REG(i) (DR_REG_MCPWM_BASE(i) + 0xc4) +/** MCPWM_GEN2_B_UTEZ : R/W; bitpos: [1:0]; default: 0; + * Action on PWM2B triggered by event TEZ when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN2_B_UTEZ 0x00000003U +#define MCPWM_GEN2_B_UTEZ_M (MCPWM_GEN2_B_UTEZ_V << MCPWM_GEN2_B_UTEZ_S) +#define MCPWM_GEN2_B_UTEZ_V 0x00000003U #define MCPWM_GEN2_B_UTEZ_S 0 +/** MCPWM_GEN2_B_UTEP : R/W; bitpos: [3:2]; default: 0; + * Action on PWM2B triggered by event TEP when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN2_B_UTEP 0x00000003U +#define MCPWM_GEN2_B_UTEP_M (MCPWM_GEN2_B_UTEP_V << MCPWM_GEN2_B_UTEP_S) +#define MCPWM_GEN2_B_UTEP_V 0x00000003U +#define MCPWM_GEN2_B_UTEP_S 2 +/** MCPWM_GEN2_B_UTEA : R/W; bitpos: [5:4]; default: 0; + * Action on PWM2B triggered by event TEA when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN2_B_UTEA 0x00000003U +#define MCPWM_GEN2_B_UTEA_M (MCPWM_GEN2_B_UTEA_V << MCPWM_GEN2_B_UTEA_S) +#define MCPWM_GEN2_B_UTEA_V 0x00000003U +#define MCPWM_GEN2_B_UTEA_S 4 +/** MCPWM_GEN2_B_UTEB : R/W; bitpos: [7:6]; default: 0; + * Action on PWM2B triggered by event TEB when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN2_B_UTEB 0x00000003U +#define MCPWM_GEN2_B_UTEB_M (MCPWM_GEN2_B_UTEB_V << MCPWM_GEN2_B_UTEB_S) +#define MCPWM_GEN2_B_UTEB_V 0x00000003U +#define MCPWM_GEN2_B_UTEB_S 6 +/** MCPWM_GEN2_B_UT0 : R/W; bitpos: [9:8]; default: 0; + * Action on PWM2B triggered by event_t0 when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN2_B_UT0 0x00000003U +#define MCPWM_GEN2_B_UT0_M (MCPWM_GEN2_B_UT0_V << MCPWM_GEN2_B_UT0_S) +#define MCPWM_GEN2_B_UT0_V 0x00000003U +#define MCPWM_GEN2_B_UT0_S 8 +/** MCPWM_GEN2_B_UT1 : R/W; bitpos: [11:10]; default: 0; + * Action on PWM2B triggered by event_t1 when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN2_B_UT1 0x00000003U +#define MCPWM_GEN2_B_UT1_M (MCPWM_GEN2_B_UT1_V << MCPWM_GEN2_B_UT1_S) +#define MCPWM_GEN2_B_UT1_V 0x00000003U +#define MCPWM_GEN2_B_UT1_S 10 +/** MCPWM_GEN2_B_DTEZ : R/W; bitpos: [13:12]; default: 0; + * Action on PWM2B triggered by event TEZ when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN2_B_DTEZ 0x00000003U +#define MCPWM_GEN2_B_DTEZ_M (MCPWM_GEN2_B_DTEZ_V << MCPWM_GEN2_B_DTEZ_S) +#define MCPWM_GEN2_B_DTEZ_V 0x00000003U +#define MCPWM_GEN2_B_DTEZ_S 12 +/** MCPWM_GEN2_B_DTEP : R/W; bitpos: [15:14]; default: 0; + * Action on PWM2B triggered by event TEP when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN2_B_DTEP 0x00000003U +#define MCPWM_GEN2_B_DTEP_M (MCPWM_GEN2_B_DTEP_V << MCPWM_GEN2_B_DTEP_S) +#define MCPWM_GEN2_B_DTEP_V 0x00000003U +#define MCPWM_GEN2_B_DTEP_S 14 +/** MCPWM_GEN2_B_DTEA : R/W; bitpos: [17:16]; default: 0; + * Action on PWM2B triggered by event TEA when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN2_B_DTEA 0x00000003U +#define MCPWM_GEN2_B_DTEA_M (MCPWM_GEN2_B_DTEA_V << MCPWM_GEN2_B_DTEA_S) +#define MCPWM_GEN2_B_DTEA_V 0x00000003U +#define MCPWM_GEN2_B_DTEA_S 16 +/** MCPWM_GEN2_B_DTEB : R/W; bitpos: [19:18]; default: 0; + * Action on PWM2B triggered by event TEB when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN2_B_DTEB 0x00000003U +#define MCPWM_GEN2_B_DTEB_M (MCPWM_GEN2_B_DTEB_V << MCPWM_GEN2_B_DTEB_S) +#define MCPWM_GEN2_B_DTEB_V 0x00000003U +#define MCPWM_GEN2_B_DTEB_S 18 +/** MCPWM_GEN2_B_DT0 : R/W; bitpos: [21:20]; default: 0; + * Action on PWM2B triggered by event_t0 when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN2_B_DT0 0x00000003U +#define MCPWM_GEN2_B_DT0_M (MCPWM_GEN2_B_DT0_V << MCPWM_GEN2_B_DT0_S) +#define MCPWM_GEN2_B_DT0_V 0x00000003U +#define MCPWM_GEN2_B_DT0_S 20 +/** MCPWM_GEN2_B_DT1 : R/W; bitpos: [23:22]; default: 0; + * Action on PWM2B triggered by event_t1 when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN2_B_DT1 0x00000003U +#define MCPWM_GEN2_B_DT1_M (MCPWM_GEN2_B_DT1_V << MCPWM_GEN2_B_DT1_S) +#define MCPWM_GEN2_B_DT1_V 0x00000003U +#define MCPWM_GEN2_B_DT1_S 22 -#define MCPWM_DB2_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xC8) -/* MCPWM_DB2_CLK_SEL : R/W ;bitpos:[17] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_DB2_CLK_SEL (BIT(17)) -#define MCPWM_DB2_CLK_SEL_M (BIT(17)) -#define MCPWM_DB2_CLK_SEL_V 0x1 -#define MCPWM_DB2_CLK_SEL_S 17 -/* MCPWM_DB2_B_OUTBYPASS : R/W ;bitpos:[16] ;default: 1'd1 ; */ -/*description: .*/ -#define MCPWM_DB2_B_OUTBYPASS (BIT(16)) -#define MCPWM_DB2_B_OUTBYPASS_M (BIT(16)) -#define MCPWM_DB2_B_OUTBYPASS_V 0x1 -#define MCPWM_DB2_B_OUTBYPASS_S 16 -/* MCPWM_DB2_A_OUTBYPASS : R/W ;bitpos:[15] ;default: 1'd1 ; */ -/*description: .*/ -#define MCPWM_DB2_A_OUTBYPASS (BIT(15)) -#define MCPWM_DB2_A_OUTBYPASS_M (BIT(15)) -#define MCPWM_DB2_A_OUTBYPASS_V 0x1 -#define MCPWM_DB2_A_OUTBYPASS_S 15 -/* MCPWM_DB2_FED_OUTINVERT : R/W ;bitpos:[14] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_DB2_FED_OUTINVERT (BIT(14)) -#define MCPWM_DB2_FED_OUTINVERT_M (BIT(14)) -#define MCPWM_DB2_FED_OUTINVERT_V 0x1 -#define MCPWM_DB2_FED_OUTINVERT_S 14 -/* MCPWM_DB2_RED_OUTINVERT : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_DB2_RED_OUTINVERT (BIT(13)) -#define MCPWM_DB2_RED_OUTINVERT_M (BIT(13)) -#define MCPWM_DB2_RED_OUTINVERT_V 0x1 -#define MCPWM_DB2_RED_OUTINVERT_S 13 -/* MCPWM_DB2_FED_INSEL : R/W ;bitpos:[12] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_DB2_FED_INSEL (BIT(12)) -#define MCPWM_DB2_FED_INSEL_M (BIT(12)) -#define MCPWM_DB2_FED_INSEL_V 0x1 -#define MCPWM_DB2_FED_INSEL_S 12 -/* MCPWM_DB2_RED_INSEL : R/W ;bitpos:[11] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_DB2_RED_INSEL (BIT(11)) -#define MCPWM_DB2_RED_INSEL_M (BIT(11)) -#define MCPWM_DB2_RED_INSEL_V 0x1 -#define MCPWM_DB2_RED_INSEL_S 11 -/* MCPWM_DB2_B_OUTSWAP : R/W ;bitpos:[10] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_DB2_B_OUTSWAP (BIT(10)) -#define MCPWM_DB2_B_OUTSWAP_M (BIT(10)) -#define MCPWM_DB2_B_OUTSWAP_V 0x1 -#define MCPWM_DB2_B_OUTSWAP_S 10 -/* MCPWM_DB2_A_OUTSWAP : R/W ;bitpos:[9] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_DB2_A_OUTSWAP (BIT(9)) -#define MCPWM_DB2_A_OUTSWAP_M (BIT(9)) -#define MCPWM_DB2_A_OUTSWAP_V 0x1 -#define MCPWM_DB2_A_OUTSWAP_S 9 -/* MCPWM_DB2_DEB_MODE : R/W ;bitpos:[8] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_DB2_DEB_MODE (BIT(8)) -#define MCPWM_DB2_DEB_MODE_M (BIT(8)) -#define MCPWM_DB2_DEB_MODE_V 0x1 -#define MCPWM_DB2_DEB_MODE_S 8 -/* MCPWM_DB2_RED_UPMETHOD : R/W ;bitpos:[7:4] ;default: 4'd0 ; */ -/*description: .*/ -#define MCPWM_DB2_RED_UPMETHOD 0x0000000F -#define MCPWM_DB2_RED_UPMETHOD_M ((MCPWM_DB2_RED_UPMETHOD_V)<<(MCPWM_DB2_RED_UPMETHOD_S)) -#define MCPWM_DB2_RED_UPMETHOD_V 0xF -#define MCPWM_DB2_RED_UPMETHOD_S 4 -/* MCPWM_DB2_FED_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: .*/ -#define MCPWM_DB2_FED_UPMETHOD 0x0000000F -#define MCPWM_DB2_FED_UPMETHOD_M ((MCPWM_DB2_FED_UPMETHOD_V)<<(MCPWM_DB2_FED_UPMETHOD_S)) -#define MCPWM_DB2_FED_UPMETHOD_V 0xF -#define MCPWM_DB2_FED_UPMETHOD_S 0 - -#define MCPWM_DB2_FED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xCC) -/* MCPWM_DB2_FED : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ -/*description: .*/ -#define MCPWM_DB2_FED 0x0000FFFF -#define MCPWM_DB2_FED_M ((MCPWM_DB2_FED_V)<<(MCPWM_DB2_FED_S)) -#define MCPWM_DB2_FED_V 0xFFFF -#define MCPWM_DB2_FED_S 0 - -#define MCPWM_DB2_RED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xD0) -/* MCPWM_DB2_RED : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ -/*description: .*/ -#define MCPWM_DB2_RED 0x0000FFFF -#define MCPWM_DB2_RED_M ((MCPWM_DB2_RED_V)<<(MCPWM_DB2_RED_S)) -#define MCPWM_DB2_RED_V 0xFFFF -#define MCPWM_DB2_RED_S 0 - -#define MCPWM_CHOPPER2_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xD4) -/* MCPWM_CHOPPER2_IN_INVERT : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_CHOPPER2_IN_INVERT (BIT(13)) -#define MCPWM_CHOPPER2_IN_INVERT_M (BIT(13)) -#define MCPWM_CHOPPER2_IN_INVERT_V 0x1 -#define MCPWM_CHOPPER2_IN_INVERT_S 13 -/* MCPWM_CHOPPER2_OUT_INVERT : R/W ;bitpos:[12] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_CHOPPER2_OUT_INVERT (BIT(12)) -#define MCPWM_CHOPPER2_OUT_INVERT_M (BIT(12)) -#define MCPWM_CHOPPER2_OUT_INVERT_V 0x1 -#define MCPWM_CHOPPER2_OUT_INVERT_S 12 -/* MCPWM_CHOPPER2_OSHTWTH : R/W ;bitpos:[11:8] ;default: 4'd0 ; */ -/*description: .*/ -#define MCPWM_CHOPPER2_OSHTWTH 0x0000000F -#define MCPWM_CHOPPER2_OSHTWTH_M ((MCPWM_CHOPPER2_OSHTWTH_V)<<(MCPWM_CHOPPER2_OSHTWTH_S)) -#define MCPWM_CHOPPER2_OSHTWTH_V 0xF -#define MCPWM_CHOPPER2_OSHTWTH_S 8 -/* MCPWM_CHOPPER2_DUTY : R/W ;bitpos:[7:5] ;default: 3'd0 ; */ -/*description: .*/ -#define MCPWM_CHOPPER2_DUTY 0x00000007 -#define MCPWM_CHOPPER2_DUTY_M ((MCPWM_CHOPPER2_DUTY_V)<<(MCPWM_CHOPPER2_DUTY_S)) -#define MCPWM_CHOPPER2_DUTY_V 0x7 -#define MCPWM_CHOPPER2_DUTY_S 5 -/* MCPWM_CHOPPER2_PRESCALE : R/W ;bitpos:[4:1] ;default: 4'd0 ; */ -/*description: .*/ -#define MCPWM_CHOPPER2_PRESCALE 0x0000000F -#define MCPWM_CHOPPER2_PRESCALE_M ((MCPWM_CHOPPER2_PRESCALE_V)<<(MCPWM_CHOPPER2_PRESCALE_S)) -#define MCPWM_CHOPPER2_PRESCALE_V 0xF -#define MCPWM_CHOPPER2_PRESCALE_S 1 -/* MCPWM_CHOPPER2_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_CHOPPER2_EN (BIT(0)) -#define MCPWM_CHOPPER2_EN_M (BIT(0)) -#define MCPWM_CHOPPER2_EN_V 0x1 -#define MCPWM_CHOPPER2_EN_S 0 - -#define MCPWM_TZ2_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0xD8) -/* MCPWM_TZ2_B_OST_U : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ -/*description: 0: do nothing, 1: force lo, 2: force hi, 3: toggle.*/ -#define MCPWM_TZ2_B_OST_U 0x00000003 -#define MCPWM_TZ2_B_OST_U_M ((MCPWM_TZ2_B_OST_U_V)<<(MCPWM_TZ2_B_OST_U_S)) -#define MCPWM_TZ2_B_OST_U_V 0x3 -#define MCPWM_TZ2_B_OST_U_S 22 -/* MCPWM_TZ2_B_OST_D : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ -/*description: 0: do nothing, 1: force lo, 2: force hi, 3: toggle.*/ -#define MCPWM_TZ2_B_OST_D 0x00000003 -#define MCPWM_TZ2_B_OST_D_M ((MCPWM_TZ2_B_OST_D_V)<<(MCPWM_TZ2_B_OST_D_S)) -#define MCPWM_TZ2_B_OST_D_V 0x3 -#define MCPWM_TZ2_B_OST_D_S 20 -/* MCPWM_TZ2_B_CBC_U : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ -/*description: 0: do nothing, 1: force lo, 2: force hi, 3: toggle.*/ -#define MCPWM_TZ2_B_CBC_U 0x00000003 -#define MCPWM_TZ2_B_CBC_U_M ((MCPWM_TZ2_B_CBC_U_V)<<(MCPWM_TZ2_B_CBC_U_S)) -#define MCPWM_TZ2_B_CBC_U_V 0x3 -#define MCPWM_TZ2_B_CBC_U_S 18 -/* MCPWM_TZ2_B_CBC_D : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ -/*description: 0: do nothing, 1: force lo, 2: force hi, 3: toggle.*/ -#define MCPWM_TZ2_B_CBC_D 0x00000003 -#define MCPWM_TZ2_B_CBC_D_M ((MCPWM_TZ2_B_CBC_D_V)<<(MCPWM_TZ2_B_CBC_D_S)) -#define MCPWM_TZ2_B_CBC_D_V 0x3 -#define MCPWM_TZ2_B_CBC_D_S 16 -/* MCPWM_TZ2_A_OST_U : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ -/*description: 0: do nothing, 1: force lo, 2: force hi, 3: toggle.*/ -#define MCPWM_TZ2_A_OST_U 0x00000003 -#define MCPWM_TZ2_A_OST_U_M ((MCPWM_TZ2_A_OST_U_V)<<(MCPWM_TZ2_A_OST_U_S)) -#define MCPWM_TZ2_A_OST_U_V 0x3 -#define MCPWM_TZ2_A_OST_U_S 14 -/* MCPWM_TZ2_A_OST_D : R/W ;bitpos:[13:12] ;default: 2'd0 ; */ -/*description: 0: do nothing, 1: force lo, 2: force hi, 3: toggle.*/ -#define MCPWM_TZ2_A_OST_D 0x00000003 -#define MCPWM_TZ2_A_OST_D_M ((MCPWM_TZ2_A_OST_D_V)<<(MCPWM_TZ2_A_OST_D_S)) -#define MCPWM_TZ2_A_OST_D_V 0x3 -#define MCPWM_TZ2_A_OST_D_S 12 -/* MCPWM_TZ2_A_CBC_U : R/W ;bitpos:[11:10] ;default: 2'd0 ; */ -/*description: 0: do nothing, 1: force lo, 2: force hi, 3: toggle.*/ -#define MCPWM_TZ2_A_CBC_U 0x00000003 -#define MCPWM_TZ2_A_CBC_U_M ((MCPWM_TZ2_A_CBC_U_V)<<(MCPWM_TZ2_A_CBC_U_S)) -#define MCPWM_TZ2_A_CBC_U_V 0x3 -#define MCPWM_TZ2_A_CBC_U_S 10 -/* MCPWM_TZ2_A_CBC_D : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ -/*description: 0: do nothing, 1: force lo, 2: force hi, 3: toggle.*/ -#define MCPWM_TZ2_A_CBC_D 0x00000003 -#define MCPWM_TZ2_A_CBC_D_M ((MCPWM_TZ2_A_CBC_D_V)<<(MCPWM_TZ2_A_CBC_D_S)) -#define MCPWM_TZ2_A_CBC_D_V 0x3 -#define MCPWM_TZ2_A_CBC_D_S 8 -/* MCPWM_TZ2_F0_OST : R/W ;bitpos:[7] ;default: 1'd0 ; */ -/*description: 0: disable, 1: enable.*/ -#define MCPWM_TZ2_F0_OST (BIT(7)) -#define MCPWM_TZ2_F0_OST_M (BIT(7)) -#define MCPWM_TZ2_F0_OST_V 0x1 -#define MCPWM_TZ2_F0_OST_S 7 -/* MCPWM_TZ2_F1_OST : R/W ;bitpos:[6] ;default: 1'd0 ; */ -/*description: 0: disable, 1: enable.*/ -#define MCPWM_TZ2_F1_OST (BIT(6)) -#define MCPWM_TZ2_F1_OST_M (BIT(6)) -#define MCPWM_TZ2_F1_OST_V 0x1 -#define MCPWM_TZ2_F1_OST_S 6 -/* MCPWM_TZ2_F2_OST : R/W ;bitpos:[5] ;default: 1'd0 ; */ -/*description: 0: disable, 1: enable.*/ -#define MCPWM_TZ2_F2_OST (BIT(5)) -#define MCPWM_TZ2_F2_OST_M (BIT(5)) -#define MCPWM_TZ2_F2_OST_V 0x1 -#define MCPWM_TZ2_F2_OST_S 5 -/* MCPWM_TZ2_SW_OST : R/W ;bitpos:[4] ;default: 1'd0 ; */ -/*description: 0: disable, 1: enable.*/ -#define MCPWM_TZ2_SW_OST (BIT(4)) -#define MCPWM_TZ2_SW_OST_M (BIT(4)) -#define MCPWM_TZ2_SW_OST_V 0x1 -#define MCPWM_TZ2_SW_OST_S 4 -/* MCPWM_TZ2_F0_CBC : R/W ;bitpos:[3] ;default: 1'd0 ; */ -/*description: 0: disable, 1: enable.*/ -#define MCPWM_TZ2_F0_CBC (BIT(3)) -#define MCPWM_TZ2_F0_CBC_M (BIT(3)) -#define MCPWM_TZ2_F0_CBC_V 0x1 -#define MCPWM_TZ2_F0_CBC_S 3 -/* MCPWM_TZ2_F1_CBC : R/W ;bitpos:[2] ;default: 1'd0 ; */ -/*description: 0: disable, 1: enable.*/ -#define MCPWM_TZ2_F1_CBC (BIT(2)) -#define MCPWM_TZ2_F1_CBC_M (BIT(2)) -#define MCPWM_TZ2_F1_CBC_V 0x1 -#define MCPWM_TZ2_F1_CBC_S 2 -/* MCPWM_TZ2_F2_CBC : R/W ;bitpos:[1] ;default: 1'd0 ; */ -/*description: 0: disable, 1: enable.*/ -#define MCPWM_TZ2_F2_CBC (BIT(1)) -#define MCPWM_TZ2_F2_CBC_M (BIT(1)) -#define MCPWM_TZ2_F2_CBC_V 0x1 -#define MCPWM_TZ2_F2_CBC_S 1 -/* MCPWM_TZ2_SW_CBC : R/W ;bitpos:[0] ;default: 1'd0 ; */ -/*description: 0: disable, 1: enable.*/ -#define MCPWM_TZ2_SW_CBC (BIT(0)) -#define MCPWM_TZ2_SW_CBC_M (BIT(0)) -#define MCPWM_TZ2_SW_CBC_V 0x1 -#define MCPWM_TZ2_SW_CBC_S 0 - -#define MCPWM_TZ2_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0xDC) -/* MCPWM_TZ2_FORCE_OST : R/W ;bitpos:[4] ;default: 1'd0 ; */ -/*description: a toggle trigger a oneshot tripping.*/ -#define MCPWM_TZ2_FORCE_OST (BIT(4)) -#define MCPWM_TZ2_FORCE_OST_M (BIT(4)) -#define MCPWM_TZ2_FORCE_OST_V 0x1 -#define MCPWM_TZ2_FORCE_OST_S 4 -/* MCPWM_TZ2_FORCE_CBC : R/W ;bitpos:[3] ;default: 1'd0 ; */ -/*description: a toggle trigger a cycle-by-cycle tripping.*/ -#define MCPWM_TZ2_FORCE_CBC (BIT(3)) -#define MCPWM_TZ2_FORCE_CBC_M (BIT(3)) -#define MCPWM_TZ2_FORCE_CBC_V 0x1 -#define MCPWM_TZ2_FORCE_CBC_S 3 -/* MCPWM_TZ2_CBCPULSE : R/W ;bitpos:[2:1] ;default: 2'd0 ; */ -/*description: bit0: tez, bit1: tep.*/ -#define MCPWM_TZ2_CBCPULSE 0x00000003 -#define MCPWM_TZ2_CBCPULSE_M ((MCPWM_TZ2_CBCPULSE_V)<<(MCPWM_TZ2_CBCPULSE_S)) -#define MCPWM_TZ2_CBCPULSE_V 0x3 -#define MCPWM_TZ2_CBCPULSE_S 1 -/* MCPWM_TZ2_CLR_OST : R/W ;bitpos:[0] ;default: 1'd0 ; */ -/*description: a toggle will clear oneshot tripping.*/ -#define MCPWM_TZ2_CLR_OST (BIT(0)) -#define MCPWM_TZ2_CLR_OST_M (BIT(0)) -#define MCPWM_TZ2_CLR_OST_V 0x1 -#define MCPWM_TZ2_CLR_OST_S 0 - -#define MCPWM_TZ2_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0xE0) -/* MCPWM_TZ2_OST_ON : RO ;bitpos:[1] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_TZ2_OST_ON (BIT(1)) -#define MCPWM_TZ2_OST_ON_M (BIT(1)) -#define MCPWM_TZ2_OST_ON_V 0x1 -#define MCPWM_TZ2_OST_ON_S 1 -/* MCPWM_TZ2_CBC_ON : RO ;bitpos:[0] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_TZ2_CBC_ON (BIT(0)) -#define MCPWM_TZ2_CBC_ON_M (BIT(0)) -#define MCPWM_TZ2_CBC_ON_V 0x1 -#define MCPWM_TZ2_CBC_ON_S 0 - -#define MCPWM_FAULT_DETECT_REG(i) (REG_MCPWM_BASE(i) + 0xE4) -/* MCPWM_EVENT_F2 : RO ;bitpos:[8] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_EVENT_F2 (BIT(8)) -#define MCPWM_EVENT_F2_M (BIT(8)) -#define MCPWM_EVENT_F2_V 0x1 -#define MCPWM_EVENT_F2_S 8 -/* MCPWM_EVENT_F1 : RO ;bitpos:[7] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_EVENT_F1 (BIT(7)) -#define MCPWM_EVENT_F1_M (BIT(7)) -#define MCPWM_EVENT_F1_V 0x1 -#define MCPWM_EVENT_F1_S 7 -/* MCPWM_EVENT_F0 : RO ;bitpos:[6] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_EVENT_F0 (BIT(6)) -#define MCPWM_EVENT_F0_M (BIT(6)) -#define MCPWM_EVENT_F0_V 0x1 -#define MCPWM_EVENT_F0_S 6 -/* MCPWM_F2_POLE : R/W ;bitpos:[5] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_F2_POLE (BIT(5)) -#define MCPWM_F2_POLE_M (BIT(5)) -#define MCPWM_F2_POLE_V 0x1 -#define MCPWM_F2_POLE_S 5 -/* MCPWM_F1_POLE : R/W ;bitpos:[4] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_F1_POLE (BIT(4)) -#define MCPWM_F1_POLE_M (BIT(4)) -#define MCPWM_F1_POLE_V 0x1 -#define MCPWM_F1_POLE_S 4 -/* MCPWM_F0_POLE : R/W ;bitpos:[3] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_F0_POLE (BIT(3)) -#define MCPWM_F0_POLE_M (BIT(3)) -#define MCPWM_F0_POLE_V 0x1 -#define MCPWM_F0_POLE_S 3 -/* MCPWM_F2_EN : R/W ;bitpos:[2] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_F2_EN (BIT(2)) -#define MCPWM_F2_EN_M (BIT(2)) -#define MCPWM_F2_EN_V 0x1 -#define MCPWM_F2_EN_S 2 -/* MCPWM_F1_EN : R/W ;bitpos:[1] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_F1_EN (BIT(1)) -#define MCPWM_F1_EN_M (BIT(1)) -#define MCPWM_F1_EN_V 0x1 -#define MCPWM_F1_EN_S 1 -/* MCPWM_F0_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */ -/*description: .*/ +/** MCPWM_DT2_CFG_REG register + * PWM generator 2 dead time type selection and configuration + */ +#define MCPWM_DT2_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0xc8) +/** MCPWM_DT2_FED_UPMETHOD : R/W; bitpos: [3:0]; default: 0; + * Update method for FED (falling edge delay) active register. 0: immediate,when bit0 + * is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when + * bit3 is set to 1: disable the update + */ +#define MCPWM_DT2_FED_UPMETHOD 0x0000000FU +#define MCPWM_DT2_FED_UPMETHOD_M (MCPWM_DT2_FED_UPMETHOD_V << MCPWM_DT2_FED_UPMETHOD_S) +#define MCPWM_DT2_FED_UPMETHOD_V 0x0000000FU +#define MCPWM_DT2_FED_UPMETHOD_S 0 +/** MCPWM_DT2_RED_UPMETHOD : R/W; bitpos: [7:4]; default: 0; + * Update method for RED (rising edge delay) active register. 0: immediate,when bit0 + * is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when + * bit3 is set to 1: disable the update + */ +#define MCPWM_DT2_RED_UPMETHOD 0x0000000FU +#define MCPWM_DT2_RED_UPMETHOD_M (MCPWM_DT2_RED_UPMETHOD_V << MCPWM_DT2_RED_UPMETHOD_S) +#define MCPWM_DT2_RED_UPMETHOD_V 0x0000000FU +#define MCPWM_DT2_RED_UPMETHOD_S 4 +/** MCPWM_DT2_DEB_MODE : R/W; bitpos: [8]; default: 0; + * S8 in table, dual-edge B mode, 0: fed/red take effect on different path separately, + * 1: fed/red take effect on B path, A out is in bypass or dulpB mode + */ +#define MCPWM_DT2_DEB_MODE (BIT(8)) +#define MCPWM_DT2_DEB_MODE_M (MCPWM_DT2_DEB_MODE_V << MCPWM_DT2_DEB_MODE_S) +#define MCPWM_DT2_DEB_MODE_V 0x00000001U +#define MCPWM_DT2_DEB_MODE_S 8 +/** MCPWM_DT2_A_OUTSWAP : R/W; bitpos: [9]; default: 0; + * S6 in table + */ +#define MCPWM_DT2_A_OUTSWAP (BIT(9)) +#define MCPWM_DT2_A_OUTSWAP_M (MCPWM_DT2_A_OUTSWAP_V << MCPWM_DT2_A_OUTSWAP_S) +#define MCPWM_DT2_A_OUTSWAP_V 0x00000001U +#define MCPWM_DT2_A_OUTSWAP_S 9 +/** MCPWM_DT2_B_OUTSWAP : R/W; bitpos: [10]; default: 0; + * S7 in table + */ +#define MCPWM_DT2_B_OUTSWAP (BIT(10)) +#define MCPWM_DT2_B_OUTSWAP_M (MCPWM_DT2_B_OUTSWAP_V << MCPWM_DT2_B_OUTSWAP_S) +#define MCPWM_DT2_B_OUTSWAP_V 0x00000001U +#define MCPWM_DT2_B_OUTSWAP_S 10 +/** MCPWM_DT2_RED_INSEL : R/W; bitpos: [11]; default: 0; + * S4 in table + */ +#define MCPWM_DT2_RED_INSEL (BIT(11)) +#define MCPWM_DT2_RED_INSEL_M (MCPWM_DT2_RED_INSEL_V << MCPWM_DT2_RED_INSEL_S) +#define MCPWM_DT2_RED_INSEL_V 0x00000001U +#define MCPWM_DT2_RED_INSEL_S 11 +/** MCPWM_DT2_FED_INSEL : R/W; bitpos: [12]; default: 0; + * S5 in table + */ +#define MCPWM_DT2_FED_INSEL (BIT(12)) +#define MCPWM_DT2_FED_INSEL_M (MCPWM_DT2_FED_INSEL_V << MCPWM_DT2_FED_INSEL_S) +#define MCPWM_DT2_FED_INSEL_V 0x00000001U +#define MCPWM_DT2_FED_INSEL_S 12 +/** MCPWM_DT2_RED_OUTINVERT : R/W; bitpos: [13]; default: 0; + * S2 in table + */ +#define MCPWM_DT2_RED_OUTINVERT (BIT(13)) +#define MCPWM_DT2_RED_OUTINVERT_M (MCPWM_DT2_RED_OUTINVERT_V << MCPWM_DT2_RED_OUTINVERT_S) +#define MCPWM_DT2_RED_OUTINVERT_V 0x00000001U +#define MCPWM_DT2_RED_OUTINVERT_S 13 +/** MCPWM_DT2_FED_OUTINVERT : R/W; bitpos: [14]; default: 0; + * S3 in table + */ +#define MCPWM_DT2_FED_OUTINVERT (BIT(14)) +#define MCPWM_DT2_FED_OUTINVERT_M (MCPWM_DT2_FED_OUTINVERT_V << MCPWM_DT2_FED_OUTINVERT_S) +#define MCPWM_DT2_FED_OUTINVERT_V 0x00000001U +#define MCPWM_DT2_FED_OUTINVERT_S 14 +/** MCPWM_DT2_A_OUTBYPASS : R/W; bitpos: [15]; default: 1; + * S1 in table + */ +#define MCPWM_DT2_A_OUTBYPASS (BIT(15)) +#define MCPWM_DT2_A_OUTBYPASS_M (MCPWM_DT2_A_OUTBYPASS_V << MCPWM_DT2_A_OUTBYPASS_S) +#define MCPWM_DT2_A_OUTBYPASS_V 0x00000001U +#define MCPWM_DT2_A_OUTBYPASS_S 15 +/** MCPWM_DT2_B_OUTBYPASS : R/W; bitpos: [16]; default: 1; + * S0 in table + */ +#define MCPWM_DT2_B_OUTBYPASS (BIT(16)) +#define MCPWM_DT2_B_OUTBYPASS_M (MCPWM_DT2_B_OUTBYPASS_V << MCPWM_DT2_B_OUTBYPASS_S) +#define MCPWM_DT2_B_OUTBYPASS_V 0x00000001U +#define MCPWM_DT2_B_OUTBYPASS_S 16 +/** MCPWM_DT2_CLK_SEL : R/W; bitpos: [17]; default: 0; + * Dead time clock selection. 0: PWM_clk, 1: PT_clk + */ +#define MCPWM_DT2_CLK_SEL (BIT(17)) +#define MCPWM_DT2_CLK_SEL_M (MCPWM_DT2_CLK_SEL_V << MCPWM_DT2_CLK_SEL_S) +#define MCPWM_DT2_CLK_SEL_V 0x00000001U +#define MCPWM_DT2_CLK_SEL_S 17 + +/** MCPWM_DT2_FED_CFG_REG register + * PWM generator 2 shadow register for falling edge delay (FED). + */ +#define MCPWM_DT2_FED_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0xcc) +/** MCPWM_DT2_FED : R/W; bitpos: [15:0]; default: 0; + * Shadow register for FED + */ +#define MCPWM_DT2_FED 0x0000FFFFU +#define MCPWM_DT2_FED_M (MCPWM_DT2_FED_V << MCPWM_DT2_FED_S) +#define MCPWM_DT2_FED_V 0x0000FFFFU +#define MCPWM_DT2_FED_S 0 + +/** MCPWM_DT2_RED_CFG_REG register + * PWM generator 2 shadow register for rising edge delay (RED). + */ +#define MCPWM_DT2_RED_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0xd0) +/** MCPWM_DT2_RED : R/W; bitpos: [15:0]; default: 0; + * Shadow register for RED + */ +#define MCPWM_DT2_RED 0x0000FFFFU +#define MCPWM_DT2_RED_M (MCPWM_DT2_RED_V << MCPWM_DT2_RED_S) +#define MCPWM_DT2_RED_V 0x0000FFFFU +#define MCPWM_DT2_RED_S 0 + +/** MCPWM_CARRIER2_CFG_REG register + * PWM generator 2 carrier enable and configuratoin + */ +#define MCPWM_CARRIER2_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0xd4) +/** MCPWM_CARRIER2_EN : R/W; bitpos: [0]; default: 0; + * When set, carrier2 function is enabled. When cleared, carrier2 is bypassed + */ +#define MCPWM_CARRIER2_EN (BIT(0)) +#define MCPWM_CARRIER2_EN_M (MCPWM_CARRIER2_EN_V << MCPWM_CARRIER2_EN_S) +#define MCPWM_CARRIER2_EN_V 0x00000001U +#define MCPWM_CARRIER2_EN_S 0 +/** MCPWM_CARRIER2_PRESCALE : R/W; bitpos: [4:1]; default: 0; + * PWM carrier2 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk * + * (PWM_CARRIER0_PRESCALE + 1) + */ +#define MCPWM_CARRIER2_PRESCALE 0x0000000FU +#define MCPWM_CARRIER2_PRESCALE_M (MCPWM_CARRIER2_PRESCALE_V << MCPWM_CARRIER2_PRESCALE_S) +#define MCPWM_CARRIER2_PRESCALE_V 0x0000000FU +#define MCPWM_CARRIER2_PRESCALE_S 1 +/** MCPWM_CARRIER2_DUTY : R/W; bitpos: [7:5]; default: 0; + * carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8 + */ +#define MCPWM_CARRIER2_DUTY 0x00000007U +#define MCPWM_CARRIER2_DUTY_M (MCPWM_CARRIER2_DUTY_V << MCPWM_CARRIER2_DUTY_S) +#define MCPWM_CARRIER2_DUTY_V 0x00000007U +#define MCPWM_CARRIER2_DUTY_S 5 +/** MCPWM_CARRIER2_OSHTWTH : R/W; bitpos: [11:8]; default: 0; + * width of the first pulse in number of periods of the carrier + */ +#define MCPWM_CARRIER2_OSHTWTH 0x0000000FU +#define MCPWM_CARRIER2_OSHTWTH_M (MCPWM_CARRIER2_OSHTWTH_V << MCPWM_CARRIER2_OSHTWTH_S) +#define MCPWM_CARRIER2_OSHTWTH_V 0x0000000FU +#define MCPWM_CARRIER2_OSHTWTH_S 8 +/** MCPWM_CARRIER2_OUT_INVERT : R/W; bitpos: [12]; default: 0; + * when set, invert the output of PWM2A and PWM2B for this submodule + */ +#define MCPWM_CARRIER2_OUT_INVERT (BIT(12)) +#define MCPWM_CARRIER2_OUT_INVERT_M (MCPWM_CARRIER2_OUT_INVERT_V << MCPWM_CARRIER2_OUT_INVERT_S) +#define MCPWM_CARRIER2_OUT_INVERT_V 0x00000001U +#define MCPWM_CARRIER2_OUT_INVERT_S 12 +/** MCPWM_CARRIER2_IN_INVERT : R/W; bitpos: [13]; default: 0; + * when set, invert the input of PWM2A and PWM2B for this submodule + */ +#define MCPWM_CARRIER2_IN_INVERT (BIT(13)) +#define MCPWM_CARRIER2_IN_INVERT_M (MCPWM_CARRIER2_IN_INVERT_V << MCPWM_CARRIER2_IN_INVERT_S) +#define MCPWM_CARRIER2_IN_INVERT_V 0x00000001U +#define MCPWM_CARRIER2_IN_INVERT_S 13 + +/** MCPWM_FH2_CFG0_REG register + * Actions on PWM2A and PWM2B trip events + */ +#define MCPWM_FH2_CFG0_REG(i) (DR_REG_MCPWM_BASE(i) + 0xd8) +/** MCPWM_FH2_SW_CBC : R/W; bitpos: [0]; default: 0; + * Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable + */ +#define MCPWM_FH2_SW_CBC (BIT(0)) +#define MCPWM_FH2_SW_CBC_M (MCPWM_FH2_SW_CBC_V << MCPWM_FH2_SW_CBC_S) +#define MCPWM_FH2_SW_CBC_V 0x00000001U +#define MCPWM_FH2_SW_CBC_S 0 +/** MCPWM_FH2_F2_CBC : R/W; bitpos: [1]; default: 0; + * fault_event2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + */ +#define MCPWM_FH2_F2_CBC (BIT(1)) +#define MCPWM_FH2_F2_CBC_M (MCPWM_FH2_F2_CBC_V << MCPWM_FH2_F2_CBC_S) +#define MCPWM_FH2_F2_CBC_V 0x00000001U +#define MCPWM_FH2_F2_CBC_S 1 +/** MCPWM_FH2_F1_CBC : R/W; bitpos: [2]; default: 0; + * fault_event1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + */ +#define MCPWM_FH2_F1_CBC (BIT(2)) +#define MCPWM_FH2_F1_CBC_M (MCPWM_FH2_F1_CBC_V << MCPWM_FH2_F1_CBC_S) +#define MCPWM_FH2_F1_CBC_V 0x00000001U +#define MCPWM_FH2_F1_CBC_S 2 +/** MCPWM_FH2_F0_CBC : R/W; bitpos: [3]; default: 0; + * fault_event0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + */ +#define MCPWM_FH2_F0_CBC (BIT(3)) +#define MCPWM_FH2_F0_CBC_M (MCPWM_FH2_F0_CBC_V << MCPWM_FH2_F0_CBC_S) +#define MCPWM_FH2_F0_CBC_V 0x00000001U +#define MCPWM_FH2_F0_CBC_S 3 +/** MCPWM_FH2_SW_OST : R/W; bitpos: [4]; default: 0; + * Enable register for software force one-shot mode action. 0: disable, 1: enable + */ +#define MCPWM_FH2_SW_OST (BIT(4)) +#define MCPWM_FH2_SW_OST_M (MCPWM_FH2_SW_OST_V << MCPWM_FH2_SW_OST_S) +#define MCPWM_FH2_SW_OST_V 0x00000001U +#define MCPWM_FH2_SW_OST_S 4 +/** MCPWM_FH2_F2_OST : R/W; bitpos: [5]; default: 0; + * fault_event2 will trigger one-shot mode action. 0: disable, 1: enable + */ +#define MCPWM_FH2_F2_OST (BIT(5)) +#define MCPWM_FH2_F2_OST_M (MCPWM_FH2_F2_OST_V << MCPWM_FH2_F2_OST_S) +#define MCPWM_FH2_F2_OST_V 0x00000001U +#define MCPWM_FH2_F2_OST_S 5 +/** MCPWM_FH2_F1_OST : R/W; bitpos: [6]; default: 0; + * fault_event1 will trigger one-shot mode action. 0: disable, 1: enable + */ +#define MCPWM_FH2_F1_OST (BIT(6)) +#define MCPWM_FH2_F1_OST_M (MCPWM_FH2_F1_OST_V << MCPWM_FH2_F1_OST_S) +#define MCPWM_FH2_F1_OST_V 0x00000001U +#define MCPWM_FH2_F1_OST_S 6 +/** MCPWM_FH2_F0_OST : R/W; bitpos: [7]; default: 0; + * fault_event0 will trigger one-shot mode action. 0: disable, 1: enable + */ +#define MCPWM_FH2_F0_OST (BIT(7)) +#define MCPWM_FH2_F0_OST_M (MCPWM_FH2_F0_OST_V << MCPWM_FH2_F0_OST_S) +#define MCPWM_FH2_F0_OST_V 0x00000001U +#define MCPWM_FH2_F0_OST_S 7 +/** MCPWM_FH2_A_CBC_D : R/W; bitpos: [9:8]; default: 0; + * Cycle-by-cycle mode action on PWM2A when fault event occurs and timer is + * decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_FH2_A_CBC_D 0x00000003U +#define MCPWM_FH2_A_CBC_D_M (MCPWM_FH2_A_CBC_D_V << MCPWM_FH2_A_CBC_D_S) +#define MCPWM_FH2_A_CBC_D_V 0x00000003U +#define MCPWM_FH2_A_CBC_D_S 8 +/** MCPWM_FH2_A_CBC_U : R/W; bitpos: [11:10]; default: 0; + * Cycle-by-cycle mode action on PWM2A when fault event occurs and timer is + * increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_FH2_A_CBC_U 0x00000003U +#define MCPWM_FH2_A_CBC_U_M (MCPWM_FH2_A_CBC_U_V << MCPWM_FH2_A_CBC_U_S) +#define MCPWM_FH2_A_CBC_U_V 0x00000003U +#define MCPWM_FH2_A_CBC_U_S 10 +/** MCPWM_FH2_A_OST_D : R/W; bitpos: [13:12]; default: 0; + * One-shot mode action on PWM2A when fault event occurs and timer is decreasing. 0: + * do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_FH2_A_OST_D 0x00000003U +#define MCPWM_FH2_A_OST_D_M (MCPWM_FH2_A_OST_D_V << MCPWM_FH2_A_OST_D_S) +#define MCPWM_FH2_A_OST_D_V 0x00000003U +#define MCPWM_FH2_A_OST_D_S 12 +/** MCPWM_FH2_A_OST_U : R/W; bitpos: [15:14]; default: 0; + * One-shot mode action on PWM2A when fault event occurs and timer is increasing. 0: + * do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_FH2_A_OST_U 0x00000003U +#define MCPWM_FH2_A_OST_U_M (MCPWM_FH2_A_OST_U_V << MCPWM_FH2_A_OST_U_S) +#define MCPWM_FH2_A_OST_U_V 0x00000003U +#define MCPWM_FH2_A_OST_U_S 14 +/** MCPWM_FH2_B_CBC_D : R/W; bitpos: [17:16]; default: 0; + * Cycle-by-cycle mode action on PWM2B when fault event occurs and timer is + * decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_FH2_B_CBC_D 0x00000003U +#define MCPWM_FH2_B_CBC_D_M (MCPWM_FH2_B_CBC_D_V << MCPWM_FH2_B_CBC_D_S) +#define MCPWM_FH2_B_CBC_D_V 0x00000003U +#define MCPWM_FH2_B_CBC_D_S 16 +/** MCPWM_FH2_B_CBC_U : R/W; bitpos: [19:18]; default: 0; + * Cycle-by-cycle mode action on PWM2B when fault event occurs and timer is + * increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_FH2_B_CBC_U 0x00000003U +#define MCPWM_FH2_B_CBC_U_M (MCPWM_FH2_B_CBC_U_V << MCPWM_FH2_B_CBC_U_S) +#define MCPWM_FH2_B_CBC_U_V 0x00000003U +#define MCPWM_FH2_B_CBC_U_S 18 +/** MCPWM_FH2_B_OST_D : R/W; bitpos: [21:20]; default: 0; + * One-shot mode action on PWM2B when fault event occurs and timer is decreasing. 0: + * do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_FH2_B_OST_D 0x00000003U +#define MCPWM_FH2_B_OST_D_M (MCPWM_FH2_B_OST_D_V << MCPWM_FH2_B_OST_D_S) +#define MCPWM_FH2_B_OST_D_V 0x00000003U +#define MCPWM_FH2_B_OST_D_S 20 +/** MCPWM_FH2_B_OST_U : R/W; bitpos: [23:22]; default: 0; + * One-shot mode action on PWM2B when fault event occurs and timer is increasing. 0: + * do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_FH2_B_OST_U 0x00000003U +#define MCPWM_FH2_B_OST_U_M (MCPWM_FH2_B_OST_U_V << MCPWM_FH2_B_OST_U_S) +#define MCPWM_FH2_B_OST_U_V 0x00000003U +#define MCPWM_FH2_B_OST_U_S 22 + +/** MCPWM_FH2_CFG1_REG register + * Software triggers for fault handler actions + */ +#define MCPWM_FH2_CFG1_REG(i) (DR_REG_MCPWM_BASE(i) + 0xdc) +/** MCPWM_FH2_CLR_OST : R/W; bitpos: [0]; default: 0; + * a rising edge will clear on going one-shot mode action + */ +#define MCPWM_FH2_CLR_OST (BIT(0)) +#define MCPWM_FH2_CLR_OST_M (MCPWM_FH2_CLR_OST_V << MCPWM_FH2_CLR_OST_S) +#define MCPWM_FH2_CLR_OST_V 0x00000001U +#define MCPWM_FH2_CLR_OST_S 0 +/** MCPWM_FH2_CBCPULSE : R/W; bitpos: [2:1]; default: 0; + * cycle-by-cycle mode action refresh moment selection. When bit0 is set to 1: TEZ, + * when bit1 is set to 1:TEP + */ +#define MCPWM_FH2_CBCPULSE 0x00000003U +#define MCPWM_FH2_CBCPULSE_M (MCPWM_FH2_CBCPULSE_V << MCPWM_FH2_CBCPULSE_S) +#define MCPWM_FH2_CBCPULSE_V 0x00000003U +#define MCPWM_FH2_CBCPULSE_S 1 +/** MCPWM_FH2_FORCE_CBC : R/W; bitpos: [3]; default: 0; + * a toggle trigger a cycle-by-cycle mode action + */ +#define MCPWM_FH2_FORCE_CBC (BIT(3)) +#define MCPWM_FH2_FORCE_CBC_M (MCPWM_FH2_FORCE_CBC_V << MCPWM_FH2_FORCE_CBC_S) +#define MCPWM_FH2_FORCE_CBC_V 0x00000001U +#define MCPWM_FH2_FORCE_CBC_S 3 +/** MCPWM_FH2_FORCE_OST : R/W; bitpos: [4]; default: 0; + * a toggle (software negate its value) triggers a one-shot mode action + */ +#define MCPWM_FH2_FORCE_OST (BIT(4)) +#define MCPWM_FH2_FORCE_OST_M (MCPWM_FH2_FORCE_OST_V << MCPWM_FH2_FORCE_OST_S) +#define MCPWM_FH2_FORCE_OST_V 0x00000001U +#define MCPWM_FH2_FORCE_OST_S 4 + +/** MCPWM_FH2_STATUS_REG register + * Status of fault events. + */ +#define MCPWM_FH2_STATUS_REG(i) (DR_REG_MCPWM_BASE(i) + 0xe0) +/** MCPWM_FH2_CBC_ON : RO; bitpos: [0]; default: 0; + * Set and reset by hardware. If set, a cycle-by-cycle mode action is on going + */ +#define MCPWM_FH2_CBC_ON (BIT(0)) +#define MCPWM_FH2_CBC_ON_M (MCPWM_FH2_CBC_ON_V << MCPWM_FH2_CBC_ON_S) +#define MCPWM_FH2_CBC_ON_V 0x00000001U +#define MCPWM_FH2_CBC_ON_S 0 +/** MCPWM_FH2_OST_ON : RO; bitpos: [1]; default: 0; + * Set and reset by hardware. If set, an one-shot mode action is on going + */ +#define MCPWM_FH2_OST_ON (BIT(1)) +#define MCPWM_FH2_OST_ON_M (MCPWM_FH2_OST_ON_V << MCPWM_FH2_OST_ON_S) +#define MCPWM_FH2_OST_ON_V 0x00000001U +#define MCPWM_FH2_OST_ON_S 1 + +/** MCPWM_FAULT_DETECT_REG register + * Fault detection configuration and status + */ +#define MCPWM_FAULT_DETECT_REG(i) (DR_REG_MCPWM_BASE(i) + 0xe4) +/** MCPWM_F0_EN : R/W; bitpos: [0]; default: 0; + * When set, fault_event0 generation is enabled + */ #define MCPWM_F0_EN (BIT(0)) -#define MCPWM_F0_EN_M (BIT(0)) -#define MCPWM_F0_EN_V 0x1 +#define MCPWM_F0_EN_M (MCPWM_F0_EN_V << MCPWM_F0_EN_S) +#define MCPWM_F0_EN_V 0x00000001U #define MCPWM_F0_EN_S 0 +/** MCPWM_F1_EN : R/W; bitpos: [1]; default: 0; + * When set, fault_event1 generation is enabled + */ +#define MCPWM_F1_EN (BIT(1)) +#define MCPWM_F1_EN_M (MCPWM_F1_EN_V << MCPWM_F1_EN_S) +#define MCPWM_F1_EN_V 0x00000001U +#define MCPWM_F1_EN_S 1 +/** MCPWM_F2_EN : R/W; bitpos: [2]; default: 0; + * When set, fault_event2 generation is enabled + */ +#define MCPWM_F2_EN (BIT(2)) +#define MCPWM_F2_EN_M (MCPWM_F2_EN_V << MCPWM_F2_EN_S) +#define MCPWM_F2_EN_V 0x00000001U +#define MCPWM_F2_EN_S 2 +/** MCPWM_F0_POLE : R/W; bitpos: [3]; default: 0; + * Set fault_event0 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, + * 1: level high + */ +#define MCPWM_F0_POLE (BIT(3)) +#define MCPWM_F0_POLE_M (MCPWM_F0_POLE_V << MCPWM_F0_POLE_S) +#define MCPWM_F0_POLE_V 0x00000001U +#define MCPWM_F0_POLE_S 3 +/** MCPWM_F1_POLE : R/W; bitpos: [4]; default: 0; + * Set fault_event1 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, + * 1: level high + */ +#define MCPWM_F1_POLE (BIT(4)) +#define MCPWM_F1_POLE_M (MCPWM_F1_POLE_V << MCPWM_F1_POLE_S) +#define MCPWM_F1_POLE_V 0x00000001U +#define MCPWM_F1_POLE_S 4 +/** MCPWM_F2_POLE : R/W; bitpos: [5]; default: 0; + * Set fault_event2 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, + * 1: level high + */ +#define MCPWM_F2_POLE (BIT(5)) +#define MCPWM_F2_POLE_M (MCPWM_F2_POLE_V << MCPWM_F2_POLE_S) +#define MCPWM_F2_POLE_V 0x00000001U +#define MCPWM_F2_POLE_S 5 +/** MCPWM_EVENT_F0 : RO; bitpos: [6]; default: 0; + * Set and reset by hardware. If set, fault_event0 is on going + */ +#define MCPWM_EVENT_F0 (BIT(6)) +#define MCPWM_EVENT_F0_M (MCPWM_EVENT_F0_V << MCPWM_EVENT_F0_S) +#define MCPWM_EVENT_F0_V 0x00000001U +#define MCPWM_EVENT_F0_S 6 +/** MCPWM_EVENT_F1 : RO; bitpos: [7]; default: 0; + * Set and reset by hardware. If set, fault_event1 is on going + */ +#define MCPWM_EVENT_F1 (BIT(7)) +#define MCPWM_EVENT_F1_M (MCPWM_EVENT_F1_V << MCPWM_EVENT_F1_S) +#define MCPWM_EVENT_F1_V 0x00000001U +#define MCPWM_EVENT_F1_S 7 +/** MCPWM_EVENT_F2 : RO; bitpos: [8]; default: 0; + * Set and reset by hardware. If set, fault_event2 is on going + */ +#define MCPWM_EVENT_F2 (BIT(8)) +#define MCPWM_EVENT_F2_M (MCPWM_EVENT_F2_V << MCPWM_EVENT_F2_S) +#define MCPWM_EVENT_F2_V 0x00000001U +#define MCPWM_EVENT_F2_S 8 -#define MCPWM_CAP_TIMER_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xE8) -/* MCPWM_CAP_SYNC_SW : WO ;bitpos:[5] ;default: 1'd0 ; */ -/*description: Write 1 will force a timer sync.*/ -#define MCPWM_CAP_SYNC_SW (BIT(5)) -#define MCPWM_CAP_SYNC_SW_M (BIT(5)) -#define MCPWM_CAP_SYNC_SW_V 0x1 -#define MCPWM_CAP_SYNC_SW_S 5 -/* MCPWM_CAP_SYNCI_SEL : R/W ;bitpos:[4:2] ;default: 3'd0 ; */ -/*description: .*/ -#define MCPWM_CAP_SYNCI_SEL 0x00000007 -#define MCPWM_CAP_SYNCI_SEL_M ((MCPWM_CAP_SYNCI_SEL_V)<<(MCPWM_CAP_SYNCI_SEL_S)) -#define MCPWM_CAP_SYNCI_SEL_V 0x7 -#define MCPWM_CAP_SYNCI_SEL_S 2 -/* MCPWM_CAP_SYNCI_EN : R/W ;bitpos:[1] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_CAP_SYNCI_EN (BIT(1)) -#define MCPWM_CAP_SYNCI_EN_M (BIT(1)) -#define MCPWM_CAP_SYNCI_EN_V 0x1 -#define MCPWM_CAP_SYNCI_EN_S 1 -/* MCPWM_CAP_TIMER_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */ -/*description: .*/ +/** MCPWM_CAP_TIMER_CFG_REG register + * Configure capture timer + */ +#define MCPWM_CAP_TIMER_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0xe8) +/** MCPWM_CAP_TIMER_EN : R/W; bitpos: [0]; default: 0; + * When set, capture timer incrementing under APB_clk is enabled. + */ #define MCPWM_CAP_TIMER_EN (BIT(0)) -#define MCPWM_CAP_TIMER_EN_M (BIT(0)) -#define MCPWM_CAP_TIMER_EN_V 0x1 +#define MCPWM_CAP_TIMER_EN_M (MCPWM_CAP_TIMER_EN_V << MCPWM_CAP_TIMER_EN_S) +#define MCPWM_CAP_TIMER_EN_V 0x00000001U #define MCPWM_CAP_TIMER_EN_S 0 +/** MCPWM_CAP_SYNCI_EN : R/W; bitpos: [1]; default: 0; + * When set, capture timer sync is enabled. + */ +#define MCPWM_CAP_SYNCI_EN (BIT(1)) +#define MCPWM_CAP_SYNCI_EN_M (MCPWM_CAP_SYNCI_EN_V << MCPWM_CAP_SYNCI_EN_S) +#define MCPWM_CAP_SYNCI_EN_V 0x00000001U +#define MCPWM_CAP_SYNCI_EN_S 1 +/** MCPWM_CAP_SYNCI_SEL : R/W; bitpos: [4:2]; default: 0; + * capture module sync input selection. 0: none, 1: timer0 sync_out, 2: timer1 + * sync_out, 3: timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, + * 6: SYNC2 from GPIO matrix + */ +#define MCPWM_CAP_SYNCI_SEL 0x00000007U +#define MCPWM_CAP_SYNCI_SEL_M (MCPWM_CAP_SYNCI_SEL_V << MCPWM_CAP_SYNCI_SEL_S) +#define MCPWM_CAP_SYNCI_SEL_V 0x00000007U +#define MCPWM_CAP_SYNCI_SEL_S 2 +/** MCPWM_CAP_SYNC_SW : WT; bitpos: [5]; default: 0; + * When reg_cap_synci_en is 1, write 1 will trigger a capture timer sync, capture + * timer is loaded with value in phase register. + */ +#define MCPWM_CAP_SYNC_SW (BIT(5)) +#define MCPWM_CAP_SYNC_SW_M (MCPWM_CAP_SYNC_SW_V << MCPWM_CAP_SYNC_SW_S) +#define MCPWM_CAP_SYNC_SW_V 0x00000001U +#define MCPWM_CAP_SYNC_SW_S 5 -#define MCPWM_CAP_TIMER_PHASE_REG(i) (REG_MCPWM_BASE(i) + 0xEC) -/* MCPWM_CAP_PHASE : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: .*/ -#define MCPWM_CAP_PHASE 0xFFFFFFFF -#define MCPWM_CAP_PHASE_M ((MCPWM_CAP_PHASE_V)<<(MCPWM_CAP_PHASE_S)) -#define MCPWM_CAP_PHASE_V 0xFFFFFFFF -#define MCPWM_CAP_PHASE_S 0 - -#define MCPWM_CAP_CH0_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xF0) -/* MCPWM_CAP0_SW : WO ;bitpos:[12] ;default: 1'd0 ; */ -/*description: Write 1 will trigger a sw capture.*/ -#define MCPWM_CAP0_SW (BIT(12)) -#define MCPWM_CAP0_SW_M (BIT(12)) -#define MCPWM_CAP0_SW_V 0x1 -#define MCPWM_CAP0_SW_S 12 -/* MCPWM_CAP0_IN_INVERT : R/W ;bitpos:[11] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_CAP0_IN_INVERT (BIT(11)) -#define MCPWM_CAP0_IN_INVERT_M (BIT(11)) -#define MCPWM_CAP0_IN_INVERT_V 0x1 -#define MCPWM_CAP0_IN_INVERT_S 11 -/* MCPWM_CAP0_PRESCALE : R/W ;bitpos:[10:3] ;default: 8'd0 ; */ -/*description: .*/ -#define MCPWM_CAP0_PRESCALE 0x000000FF -#define MCPWM_CAP0_PRESCALE_M ((MCPWM_CAP0_PRESCALE_V)<<(MCPWM_CAP0_PRESCALE_S)) -#define MCPWM_CAP0_PRESCALE_V 0xFF -#define MCPWM_CAP0_PRESCALE_S 3 -/* MCPWM_CAP0_MODE : R/W ;bitpos:[2:1] ;default: 2'd0 ; */ -/*description: bit0: negedge cap en, bit1: posedge cap en.*/ -#define MCPWM_CAP0_MODE 0x00000003 -#define MCPWM_CAP0_MODE_M ((MCPWM_CAP0_MODE_V)<<(MCPWM_CAP0_MODE_S)) -#define MCPWM_CAP0_MODE_V 0x3 -#define MCPWM_CAP0_MODE_S 1 -/* MCPWM_CAP0_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */ -/*description: .*/ +/** MCPWM_CAP_TIMER_PHASE_REG register + * Phase for capture timer sync + */ +#define MCPWM_CAP_TIMER_PHASE_REG(i) (DR_REG_MCPWM_BASE(i) + 0xec) +/** MCPWM_CAP_TIMER_PHASE : R/W; bitpos: [31:0]; default: 0; + * Phase value for capture timer sync operation. + */ +#define MCPWM_CAP_TIMER_PHASE 0xFFFFFFFFU +#define MCPWM_CAP_TIMER_PHASE_M (MCPWM_CAP_TIMER_PHASE_V << MCPWM_CAP_TIMER_PHASE_S) +#define MCPWM_CAP_TIMER_PHASE_V 0xFFFFFFFFU +#define MCPWM_CAP_TIMER_PHASE_S 0 + +/** MCPWM_CAP_CH0_CFG_REG register + * Capture channel 0 configuration and enable + */ +#define MCPWM_CAP_CH0_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0xf0) +/** MCPWM_CAP0_EN : R/W; bitpos: [0]; default: 0; + * When set, capture on channel 0 is enabled + */ #define MCPWM_CAP0_EN (BIT(0)) -#define MCPWM_CAP0_EN_M (BIT(0)) -#define MCPWM_CAP0_EN_V 0x1 +#define MCPWM_CAP0_EN_M (MCPWM_CAP0_EN_V << MCPWM_CAP0_EN_S) +#define MCPWM_CAP0_EN_V 0x00000001U #define MCPWM_CAP0_EN_S 0 +/** MCPWM_CAP0_MODE : R/W; bitpos: [2:1]; default: 0; + * Edge of capture on channel 0 after prescaling. When bit0 is set to 1: enable + * capture on the negative edge, When bit1 is set to 1: enable capture on the positive + * edge. + */ +#define MCPWM_CAP0_MODE 0x00000003U +#define MCPWM_CAP0_MODE_M (MCPWM_CAP0_MODE_V << MCPWM_CAP0_MODE_S) +#define MCPWM_CAP0_MODE_V 0x00000003U +#define MCPWM_CAP0_MODE_S 1 +/** MCPWM_CAP0_PRESCALE : R/W; bitpos: [10:3]; default: 0; + * Value of prescaling on possitive edge of CAP0. Prescale value = PWM_CAP0_PRESCALE + + * 1 + */ +#define MCPWM_CAP0_PRESCALE 0x000000FFU +#define MCPWM_CAP0_PRESCALE_M (MCPWM_CAP0_PRESCALE_V << MCPWM_CAP0_PRESCALE_S) +#define MCPWM_CAP0_PRESCALE_V 0x000000FFU +#define MCPWM_CAP0_PRESCALE_S 3 +/** MCPWM_CAP0_IN_INVERT : R/W; bitpos: [11]; default: 0; + * when set, CAP0 form GPIO matrix is inverted before prescale + */ +#define MCPWM_CAP0_IN_INVERT (BIT(11)) +#define MCPWM_CAP0_IN_INVERT_M (MCPWM_CAP0_IN_INVERT_V << MCPWM_CAP0_IN_INVERT_S) +#define MCPWM_CAP0_IN_INVERT_V 0x00000001U +#define MCPWM_CAP0_IN_INVERT_S 11 +/** MCPWM_CAP0_SW : WT; bitpos: [12]; default: 0; + * Write 1 will trigger a software forced capture on channel 0 + */ +#define MCPWM_CAP0_SW (BIT(12)) +#define MCPWM_CAP0_SW_M (MCPWM_CAP0_SW_V << MCPWM_CAP0_SW_S) +#define MCPWM_CAP0_SW_V 0x00000001U +#define MCPWM_CAP0_SW_S 12 -#define MCPWM_CAP_CH1_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xF4) -/* MCPWM_CAP1_SW : WO ;bitpos:[12] ;default: 1'd0 ; */ -/*description: Write 1 will trigger a sw capture.*/ -#define MCPWM_CAP1_SW (BIT(12)) -#define MCPWM_CAP1_SW_M (BIT(12)) -#define MCPWM_CAP1_SW_V 0x1 -#define MCPWM_CAP1_SW_S 12 -/* MCPWM_CAP1_IN_INVERT : R/W ;bitpos:[11] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_CAP1_IN_INVERT (BIT(11)) -#define MCPWM_CAP1_IN_INVERT_M (BIT(11)) -#define MCPWM_CAP1_IN_INVERT_V 0x1 -#define MCPWM_CAP1_IN_INVERT_S 11 -/* MCPWM_CAP1_PRESCALE : R/W ;bitpos:[10:3] ;default: 8'd0 ; */ -/*description: .*/ -#define MCPWM_CAP1_PRESCALE 0x000000FF -#define MCPWM_CAP1_PRESCALE_M ((MCPWM_CAP1_PRESCALE_V)<<(MCPWM_CAP1_PRESCALE_S)) -#define MCPWM_CAP1_PRESCALE_V 0xFF -#define MCPWM_CAP1_PRESCALE_S 3 -/* MCPWM_CAP1_MODE : R/W ;bitpos:[2:1] ;default: 2'd0 ; */ -/*description: .*/ -#define MCPWM_CAP1_MODE 0x00000003 -#define MCPWM_CAP1_MODE_M ((MCPWM_CAP1_MODE_V)<<(MCPWM_CAP1_MODE_S)) -#define MCPWM_CAP1_MODE_V 0x3 -#define MCPWM_CAP1_MODE_S 1 -/* MCPWM_CAP1_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */ -/*description: .*/ +/** MCPWM_CAP_CH1_CFG_REG register + * Capture channel 1 configuration and enable + */ +#define MCPWM_CAP_CH1_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0xf4) +/** MCPWM_CAP1_EN : R/W; bitpos: [0]; default: 0; + * When set, capture on channel 2 is enabled + */ #define MCPWM_CAP1_EN (BIT(0)) -#define MCPWM_CAP1_EN_M (BIT(0)) -#define MCPWM_CAP1_EN_V 0x1 +#define MCPWM_CAP1_EN_M (MCPWM_CAP1_EN_V << MCPWM_CAP1_EN_S) +#define MCPWM_CAP1_EN_V 0x00000001U #define MCPWM_CAP1_EN_S 0 +/** MCPWM_CAP1_MODE : R/W; bitpos: [2:1]; default: 0; + * Edge of capture on channel 1 after prescaling. When bit0 is set to 1: enable + * capture on the negative edge, When bit1 is set to 1: enable capture on the positive + * edge. + */ +#define MCPWM_CAP1_MODE 0x00000003U +#define MCPWM_CAP1_MODE_M (MCPWM_CAP1_MODE_V << MCPWM_CAP1_MODE_S) +#define MCPWM_CAP1_MODE_V 0x00000003U +#define MCPWM_CAP1_MODE_S 1 +/** MCPWM_CAP1_PRESCALE : R/W; bitpos: [10:3]; default: 0; + * Value of prescaling on possitive edge of CAP1. Prescale value = PWM_CAP1_PRESCALE + + * 1 + */ +#define MCPWM_CAP1_PRESCALE 0x000000FFU +#define MCPWM_CAP1_PRESCALE_M (MCPWM_CAP1_PRESCALE_V << MCPWM_CAP1_PRESCALE_S) +#define MCPWM_CAP1_PRESCALE_V 0x000000FFU +#define MCPWM_CAP1_PRESCALE_S 3 +/** MCPWM_CAP1_IN_INVERT : R/W; bitpos: [11]; default: 0; + * when set, CAP1 form GPIO matrix is inverted before prescale + */ +#define MCPWM_CAP1_IN_INVERT (BIT(11)) +#define MCPWM_CAP1_IN_INVERT_M (MCPWM_CAP1_IN_INVERT_V << MCPWM_CAP1_IN_INVERT_S) +#define MCPWM_CAP1_IN_INVERT_V 0x00000001U +#define MCPWM_CAP1_IN_INVERT_S 11 +/** MCPWM_CAP1_SW : WT; bitpos: [12]; default: 0; + * Write 1 will trigger a software forced capture on channel 1 + */ +#define MCPWM_CAP1_SW (BIT(12)) +#define MCPWM_CAP1_SW_M (MCPWM_CAP1_SW_V << MCPWM_CAP1_SW_S) +#define MCPWM_CAP1_SW_V 0x00000001U +#define MCPWM_CAP1_SW_S 12 -#define MCPWM_CAP_CH2_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xF8) -/* MCPWM_CAP2_SW : WO ;bitpos:[12] ;default: 1'd0 ; */ -/*description: Write 1 will trigger a sw capture.*/ -#define MCPWM_CAP2_SW (BIT(12)) -#define MCPWM_CAP2_SW_M (BIT(12)) -#define MCPWM_CAP2_SW_V 0x1 -#define MCPWM_CAP2_SW_S 12 -/* MCPWM_CAP2_IN_INVERT : R/W ;bitpos:[11] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_CAP2_IN_INVERT (BIT(11)) -#define MCPWM_CAP2_IN_INVERT_M (BIT(11)) -#define MCPWM_CAP2_IN_INVERT_V 0x1 -#define MCPWM_CAP2_IN_INVERT_S 11 -/* MCPWM_CAP2_PRESCALE : R/W ;bitpos:[10:3] ;default: 8'd0 ; */ -/*description: .*/ -#define MCPWM_CAP2_PRESCALE 0x000000FF -#define MCPWM_CAP2_PRESCALE_M ((MCPWM_CAP2_PRESCALE_V)<<(MCPWM_CAP2_PRESCALE_S)) -#define MCPWM_CAP2_PRESCALE_V 0xFF -#define MCPWM_CAP2_PRESCALE_S 3 -/* MCPWM_CAP2_MODE : R/W ;bitpos:[2:1] ;default: 2'd0 ; */ -/*description: .*/ -#define MCPWM_CAP2_MODE 0x00000003 -#define MCPWM_CAP2_MODE_M ((MCPWM_CAP2_MODE_V)<<(MCPWM_CAP2_MODE_S)) -#define MCPWM_CAP2_MODE_V 0x3 -#define MCPWM_CAP2_MODE_S 1 -/* MCPWM_CAP2_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */ -/*description: .*/ +/** MCPWM_CAP_CH2_CFG_REG register + * Capture channel 2 configuration and enable + */ +#define MCPWM_CAP_CH2_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0xf8) +/** MCPWM_CAP2_EN : R/W; bitpos: [0]; default: 0; + * When set, capture on channel 2 is enabled + */ #define MCPWM_CAP2_EN (BIT(0)) -#define MCPWM_CAP2_EN_M (BIT(0)) -#define MCPWM_CAP2_EN_V 0x1 +#define MCPWM_CAP2_EN_M (MCPWM_CAP2_EN_V << MCPWM_CAP2_EN_S) +#define MCPWM_CAP2_EN_V 0x00000001U #define MCPWM_CAP2_EN_S 0 +/** MCPWM_CAP2_MODE : R/W; bitpos: [2:1]; default: 0; + * Edge of capture on channel 2 after prescaling. When bit0 is set to 1: enable + * capture on the negative edge, When bit1 is set to 1: enable capture on the positive + * edge. + */ +#define MCPWM_CAP2_MODE 0x00000003U +#define MCPWM_CAP2_MODE_M (MCPWM_CAP2_MODE_V << MCPWM_CAP2_MODE_S) +#define MCPWM_CAP2_MODE_V 0x00000003U +#define MCPWM_CAP2_MODE_S 1 +/** MCPWM_CAP2_PRESCALE : R/W; bitpos: [10:3]; default: 0; + * Value of prescaling on possitive edge of CAP2. Prescale value = PWM_CAP2_PRESCALE + + * 1 + */ +#define MCPWM_CAP2_PRESCALE 0x000000FFU +#define MCPWM_CAP2_PRESCALE_M (MCPWM_CAP2_PRESCALE_V << MCPWM_CAP2_PRESCALE_S) +#define MCPWM_CAP2_PRESCALE_V 0x000000FFU +#define MCPWM_CAP2_PRESCALE_S 3 +/** MCPWM_CAP2_IN_INVERT : R/W; bitpos: [11]; default: 0; + * when set, CAP2 form GPIO matrix is inverted before prescale + */ +#define MCPWM_CAP2_IN_INVERT (BIT(11)) +#define MCPWM_CAP2_IN_INVERT_M (MCPWM_CAP2_IN_INVERT_V << MCPWM_CAP2_IN_INVERT_S) +#define MCPWM_CAP2_IN_INVERT_V 0x00000001U +#define MCPWM_CAP2_IN_INVERT_S 11 +/** MCPWM_CAP2_SW : WT; bitpos: [12]; default: 0; + * Write 1 will trigger a software forced capture on channel 2 + */ +#define MCPWM_CAP2_SW (BIT(12)) +#define MCPWM_CAP2_SW_M (MCPWM_CAP2_SW_V << MCPWM_CAP2_SW_S) +#define MCPWM_CAP2_SW_V 0x00000001U +#define MCPWM_CAP2_SW_S 12 -#define MCPWM_CAP_CH0_REG(i) (REG_MCPWM_BASE(i) + 0xFC) -/* MCPWM_CAP0_VALUE : RO ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: .*/ -#define MCPWM_CAP0_VALUE 0xFFFFFFFF -#define MCPWM_CAP0_VALUE_M ((MCPWM_CAP0_VALUE_V)<<(MCPWM_CAP0_VALUE_S)) -#define MCPWM_CAP0_VALUE_V 0xFFFFFFFF +/** MCPWM_CAP_CH0_REG register + * ch0 capture value status register + */ +#define MCPWM_CAP_CH0_REG(i) (DR_REG_MCPWM_BASE(i) + 0xfc) +/** MCPWM_CAP0_VALUE : RO; bitpos: [31:0]; default: 0; + * Value of last capture on channel 0 + */ +#define MCPWM_CAP0_VALUE 0xFFFFFFFFU +#define MCPWM_CAP0_VALUE_M (MCPWM_CAP0_VALUE_V << MCPWM_CAP0_VALUE_S) +#define MCPWM_CAP0_VALUE_V 0xFFFFFFFFU #define MCPWM_CAP0_VALUE_S 0 -#define MCPWM_CAP_CH1_REG(i) (REG_MCPWM_BASE(i) + 0x100) -/* MCPWM_CAP1_VALUE : RO ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: .*/ -#define MCPWM_CAP1_VALUE 0xFFFFFFFF -#define MCPWM_CAP1_VALUE_M ((MCPWM_CAP1_VALUE_V)<<(MCPWM_CAP1_VALUE_S)) -#define MCPWM_CAP1_VALUE_V 0xFFFFFFFF +/** MCPWM_CAP_CH1_REG register + * ch1 capture value status register + */ +#define MCPWM_CAP_CH1_REG(i) (DR_REG_MCPWM_BASE(i) + 0x100) +/** MCPWM_CAP1_VALUE : RO; bitpos: [31:0]; default: 0; + * Value of last capture on channel 1 + */ +#define MCPWM_CAP1_VALUE 0xFFFFFFFFU +#define MCPWM_CAP1_VALUE_M (MCPWM_CAP1_VALUE_V << MCPWM_CAP1_VALUE_S) +#define MCPWM_CAP1_VALUE_V 0xFFFFFFFFU #define MCPWM_CAP1_VALUE_S 0 -#define MCPWM_CAP_CH2_REG(i) (REG_MCPWM_BASE(i) + 0x104) -/* MCPWM_CAP2_VALUE : RO ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: .*/ -#define MCPWM_CAP2_VALUE 0xFFFFFFFF -#define MCPWM_CAP2_VALUE_M ((MCPWM_CAP2_VALUE_V)<<(MCPWM_CAP2_VALUE_S)) -#define MCPWM_CAP2_VALUE_V 0xFFFFFFFF +/** MCPWM_CAP_CH2_REG register + * ch2 capture value status register + */ +#define MCPWM_CAP_CH2_REG(i) (DR_REG_MCPWM_BASE(i) + 0x104) +/** MCPWM_CAP2_VALUE : RO; bitpos: [31:0]; default: 0; + * Value of last capture on channel 2 + */ +#define MCPWM_CAP2_VALUE 0xFFFFFFFFU +#define MCPWM_CAP2_VALUE_M (MCPWM_CAP2_VALUE_V << MCPWM_CAP2_VALUE_S) +#define MCPWM_CAP2_VALUE_V 0xFFFFFFFFU #define MCPWM_CAP2_VALUE_S 0 -#define MCPWM_CAP_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x108) -/* MCPWM_CAP2_EDGE : RO ;bitpos:[2] ;default: 1'd0 ; */ -/*description: cap trigger's edge, 0: posedge, 1: negedge.*/ -#define MCPWM_CAP2_EDGE (BIT(2)) -#define MCPWM_CAP2_EDGE_M (BIT(2)) -#define MCPWM_CAP2_EDGE_V 0x1 -#define MCPWM_CAP2_EDGE_S 2 -/* MCPWM_CAP1_EDGE : RO ;bitpos:[1] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_CAP1_EDGE (BIT(1)) -#define MCPWM_CAP1_EDGE_M (BIT(1)) -#define MCPWM_CAP1_EDGE_V 0x1 -#define MCPWM_CAP1_EDGE_S 1 -/* MCPWM_CAP0_EDGE : RO ;bitpos:[0] ;default: 1'd0 ; */ -/*description: .*/ +/** MCPWM_CAP_STATUS_REG register + * Edge of last capture trigger + */ +#define MCPWM_CAP_STATUS_REG(i) (DR_REG_MCPWM_BASE(i) + 0x108) +/** MCPWM_CAP0_EDGE : RO; bitpos: [0]; default: 0; + * Edge of last capture trigger on channel 0, 0: posedge, 1: negedge + */ #define MCPWM_CAP0_EDGE (BIT(0)) -#define MCPWM_CAP0_EDGE_M (BIT(0)) -#define MCPWM_CAP0_EDGE_V 0x1 +#define MCPWM_CAP0_EDGE_M (MCPWM_CAP0_EDGE_V << MCPWM_CAP0_EDGE_S) +#define MCPWM_CAP0_EDGE_V 0x00000001U #define MCPWM_CAP0_EDGE_S 0 +/** MCPWM_CAP1_EDGE : RO; bitpos: [1]; default: 0; + * Edge of last capture trigger on channel 1, 0: posedge, 1: negedge + */ +#define MCPWM_CAP1_EDGE (BIT(1)) +#define MCPWM_CAP1_EDGE_M (MCPWM_CAP1_EDGE_V << MCPWM_CAP1_EDGE_S) +#define MCPWM_CAP1_EDGE_V 0x00000001U +#define MCPWM_CAP1_EDGE_S 1 +/** MCPWM_CAP2_EDGE : RO; bitpos: [2]; default: 0; + * Edge of last capture trigger on channel 2, 0: posedge, 1: negedge + */ +#define MCPWM_CAP2_EDGE (BIT(2)) +#define MCPWM_CAP2_EDGE_M (MCPWM_CAP2_EDGE_V << MCPWM_CAP2_EDGE_S) +#define MCPWM_CAP2_EDGE_V 0x00000001U +#define MCPWM_CAP2_EDGE_S 2 -#define MCPWM_UPDATE_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x10C) -/* MCPWM_OP2_FORCE_UP : R/W ;bitpos:[7] ;default: 1'd0 ; */ -/*description: a toggle will trigger a force update.*/ -#define MCPWM_OP2_FORCE_UP (BIT(7)) -#define MCPWM_OP2_FORCE_UP_M (BIT(7)) -#define MCPWM_OP2_FORCE_UP_V 0x1 -#define MCPWM_OP2_FORCE_UP_S 7 -/* MCPWM_OP2_UP_EN : R/W ;bitpos:[6] ;default: 1'd1 ; */ -/*description: reg update local enable.*/ -#define MCPWM_OP2_UP_EN (BIT(6)) -#define MCPWM_OP2_UP_EN_M (BIT(6)) -#define MCPWM_OP2_UP_EN_V 0x1 -#define MCPWM_OP2_UP_EN_S 6 -/* MCPWM_OP1_FORCE_UP : R/W ;bitpos:[5] ;default: 1'd0 ; */ -/*description: a toggle will trigger a force update.*/ -#define MCPWM_OP1_FORCE_UP (BIT(5)) -#define MCPWM_OP1_FORCE_UP_M (BIT(5)) -#define MCPWM_OP1_FORCE_UP_V 0x1 -#define MCPWM_OP1_FORCE_UP_S 5 -/* MCPWM_OP1_UP_EN : R/W ;bitpos:[4] ;default: 1'd1 ; */ -/*description: .*/ -#define MCPWM_OP1_UP_EN (BIT(4)) -#define MCPWM_OP1_UP_EN_M (BIT(4)) -#define MCPWM_OP1_UP_EN_V 0x1 -#define MCPWM_OP1_UP_EN_S 4 -/* MCPWM_OP0_FORCE_UP : R/W ;bitpos:[3] ;default: 1'd0 ; */ -/*description: a toggle will trigger a force update.*/ -#define MCPWM_OP0_FORCE_UP (BIT(3)) -#define MCPWM_OP0_FORCE_UP_M (BIT(3)) -#define MCPWM_OP0_FORCE_UP_V 0x1 -#define MCPWM_OP0_FORCE_UP_S 3 -/* MCPWM_OP0_UP_EN : R/W ;bitpos:[2] ;default: 1'd1 ; */ -/*description: .*/ -#define MCPWM_OP0_UP_EN (BIT(2)) -#define MCPWM_OP0_UP_EN_M (BIT(2)) -#define MCPWM_OP0_UP_EN_V 0x1 -#define MCPWM_OP0_UP_EN_S 2 -/* MCPWM_GLOBAL_FORCE_UP : R/W ;bitpos:[1] ;default: 1'd0 ; */ -/*description: a toggle will trigger a force update, all timers and operators will update their - active regs.*/ -#define MCPWM_GLOBAL_FORCE_UP (BIT(1)) -#define MCPWM_GLOBAL_FORCE_UP_M (BIT(1)) -#define MCPWM_GLOBAL_FORCE_UP_V 0x1 -#define MCPWM_GLOBAL_FORCE_UP_S 1 -/* MCPWM_GLOBAL_UP_EN : R/W ;bitpos:[0] ;default: 1'd1 ; */ -/*description: .*/ +/** MCPWM_UPDATE_CFG_REG register + * Enable update. + */ +#define MCPWM_UPDATE_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0x10c) +/** MCPWM_GLOBAL_UP_EN : R/W; bitpos: [0]; default: 1; + * The global enable of update of all active registers in MCPWM module + */ #define MCPWM_GLOBAL_UP_EN (BIT(0)) -#define MCPWM_GLOBAL_UP_EN_M (BIT(0)) -#define MCPWM_GLOBAL_UP_EN_V 0x1 +#define MCPWM_GLOBAL_UP_EN_M (MCPWM_GLOBAL_UP_EN_V << MCPWM_GLOBAL_UP_EN_S) +#define MCPWM_GLOBAL_UP_EN_V 0x00000001U #define MCPWM_GLOBAL_UP_EN_S 0 +/** MCPWM_GLOBAL_FORCE_UP : R/W; bitpos: [1]; default: 0; + * a toggle (software invert its value) will trigger a forced update of all active + * registers in MCPWM module + */ +#define MCPWM_GLOBAL_FORCE_UP (BIT(1)) +#define MCPWM_GLOBAL_FORCE_UP_M (MCPWM_GLOBAL_FORCE_UP_V << MCPWM_GLOBAL_FORCE_UP_S) +#define MCPWM_GLOBAL_FORCE_UP_V 0x00000001U +#define MCPWM_GLOBAL_FORCE_UP_S 1 +/** MCPWM_OP0_UP_EN : R/W; bitpos: [2]; default: 1; + * When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 0 + * are enabled + */ +#define MCPWM_OP0_UP_EN (BIT(2)) +#define MCPWM_OP0_UP_EN_M (MCPWM_OP0_UP_EN_V << MCPWM_OP0_UP_EN_S) +#define MCPWM_OP0_UP_EN_V 0x00000001U +#define MCPWM_OP0_UP_EN_S 2 +/** MCPWM_OP0_FORCE_UP : R/W; bitpos: [3]; default: 0; + * a toggle (software invert its value) will trigger a forced update of active + * registers in PWM operator 0 + */ +#define MCPWM_OP0_FORCE_UP (BIT(3)) +#define MCPWM_OP0_FORCE_UP_M (MCPWM_OP0_FORCE_UP_V << MCPWM_OP0_FORCE_UP_S) +#define MCPWM_OP0_FORCE_UP_V 0x00000001U +#define MCPWM_OP0_FORCE_UP_S 3 +/** MCPWM_OP1_UP_EN : R/W; bitpos: [4]; default: 1; + * When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 1 + * are enabled + */ +#define MCPWM_OP1_UP_EN (BIT(4)) +#define MCPWM_OP1_UP_EN_M (MCPWM_OP1_UP_EN_V << MCPWM_OP1_UP_EN_S) +#define MCPWM_OP1_UP_EN_V 0x00000001U +#define MCPWM_OP1_UP_EN_S 4 +/** MCPWM_OP1_FORCE_UP : R/W; bitpos: [5]; default: 0; + * a toggle (software invert its value) will trigger a forced update of active + * registers in PWM operator 1 + */ +#define MCPWM_OP1_FORCE_UP (BIT(5)) +#define MCPWM_OP1_FORCE_UP_M (MCPWM_OP1_FORCE_UP_V << MCPWM_OP1_FORCE_UP_S) +#define MCPWM_OP1_FORCE_UP_V 0x00000001U +#define MCPWM_OP1_FORCE_UP_S 5 +/** MCPWM_OP2_UP_EN : R/W; bitpos: [6]; default: 1; + * When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 2 + * are enabled + */ +#define MCPWM_OP2_UP_EN (BIT(6)) +#define MCPWM_OP2_UP_EN_M (MCPWM_OP2_UP_EN_V << MCPWM_OP2_UP_EN_S) +#define MCPWM_OP2_UP_EN_V 0x00000001U +#define MCPWM_OP2_UP_EN_S 6 +/** MCPWM_OP2_FORCE_UP : R/W; bitpos: [7]; default: 0; + * a toggle (software invert its value) will trigger a forced update of active + * registers in PWM operator 2 + */ +#define MCPWM_OP2_FORCE_UP (BIT(7)) +#define MCPWM_OP2_FORCE_UP_M (MCPWM_OP2_FORCE_UP_V << MCPWM_OP2_FORCE_UP_S) +#define MCPWM_OP2_FORCE_UP_V 0x00000001U +#define MCPWM_OP2_FORCE_UP_S 7 -#define MCPWM_INT_ENA_PWM_REG(i) (REG_MCPWM_BASE(i) + 0x110) -/* MCPWM_CAP2_INT_ENA : R/W ;bitpos:[29] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_CAP2_INT_ENA (BIT(29)) -#define MCPWM_CAP2_INT_ENA_M (BIT(29)) -#define MCPWM_CAP2_INT_ENA_V 0x1 -#define MCPWM_CAP2_INT_ENA_S 29 -/* MCPWM_CAP1_INT_ENA : R/W ;bitpos:[28] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_CAP1_INT_ENA (BIT(28)) -#define MCPWM_CAP1_INT_ENA_M (BIT(28)) -#define MCPWM_CAP1_INT_ENA_V 0x1 -#define MCPWM_CAP1_INT_ENA_S 28 -/* MCPWM_CAP0_INT_ENA : R/W ;bitpos:[27] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_CAP0_INT_ENA (BIT(27)) -#define MCPWM_CAP0_INT_ENA_M (BIT(27)) -#define MCPWM_CAP0_INT_ENA_V 0x1 -#define MCPWM_CAP0_INT_ENA_S 27 -/* MCPWM_TZ2_OST_INT_ENA : R/W ;bitpos:[26] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_TZ2_OST_INT_ENA (BIT(26)) -#define MCPWM_TZ2_OST_INT_ENA_M (BIT(26)) -#define MCPWM_TZ2_OST_INT_ENA_V 0x1 -#define MCPWM_TZ2_OST_INT_ENA_S 26 -/* MCPWM_TZ1_OST_INT_ENA : R/W ;bitpos:[25] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_TZ1_OST_INT_ENA (BIT(25)) -#define MCPWM_TZ1_OST_INT_ENA_M (BIT(25)) -#define MCPWM_TZ1_OST_INT_ENA_V 0x1 -#define MCPWM_TZ1_OST_INT_ENA_S 25 -/* MCPWM_TZ0_OST_INT_ENA : R/W ;bitpos:[24] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_TZ0_OST_INT_ENA (BIT(24)) -#define MCPWM_TZ0_OST_INT_ENA_M (BIT(24)) -#define MCPWM_TZ0_OST_INT_ENA_V 0x1 -#define MCPWM_TZ0_OST_INT_ENA_S 24 -/* MCPWM_TZ2_CBC_INT_ENA : R/W ;bitpos:[23] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_TZ2_CBC_INT_ENA (BIT(23)) -#define MCPWM_TZ2_CBC_INT_ENA_M (BIT(23)) -#define MCPWM_TZ2_CBC_INT_ENA_V 0x1 -#define MCPWM_TZ2_CBC_INT_ENA_S 23 -/* MCPWM_TZ1_CBC_INT_ENA : R/W ;bitpos:[22] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_TZ1_CBC_INT_ENA (BIT(22)) -#define MCPWM_TZ1_CBC_INT_ENA_M (BIT(22)) -#define MCPWM_TZ1_CBC_INT_ENA_V 0x1 -#define MCPWM_TZ1_CBC_INT_ENA_S 22 -/* MCPWM_TZ0_CBC_INT_ENA : R/W ;bitpos:[21] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_TZ0_CBC_INT_ENA (BIT(21)) -#define MCPWM_TZ0_CBC_INT_ENA_M (BIT(21)) -#define MCPWM_TZ0_CBC_INT_ENA_V 0x1 -#define MCPWM_TZ0_CBC_INT_ENA_S 21 -/* MCPWM_CMPR2_TEB_INT_ENA : R/W ;bitpos:[20] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_CMPR2_TEB_INT_ENA (BIT(20)) -#define MCPWM_CMPR2_TEB_INT_ENA_M (BIT(20)) -#define MCPWM_CMPR2_TEB_INT_ENA_V 0x1 -#define MCPWM_CMPR2_TEB_INT_ENA_S 20 -/* MCPWM_CMPR1_TEB_INT_ENA : R/W ;bitpos:[19] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_CMPR1_TEB_INT_ENA (BIT(19)) -#define MCPWM_CMPR1_TEB_INT_ENA_M (BIT(19)) -#define MCPWM_CMPR1_TEB_INT_ENA_V 0x1 -#define MCPWM_CMPR1_TEB_INT_ENA_S 19 -/* MCPWM_CMPR0_TEB_INT_ENA : R/W ;bitpos:[18] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_CMPR0_TEB_INT_ENA (BIT(18)) -#define MCPWM_CMPR0_TEB_INT_ENA_M (BIT(18)) -#define MCPWM_CMPR0_TEB_INT_ENA_V 0x1 -#define MCPWM_CMPR0_TEB_INT_ENA_S 18 -/* MCPWM_CMPR2_TEA_INT_ENA : R/W ;bitpos:[17] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_CMPR2_TEA_INT_ENA (BIT(17)) -#define MCPWM_CMPR2_TEA_INT_ENA_M (BIT(17)) -#define MCPWM_CMPR2_TEA_INT_ENA_V 0x1 -#define MCPWM_CMPR2_TEA_INT_ENA_S 17 -/* MCPWM_CMPR1_TEA_INT_ENA : R/W ;bitpos:[16] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_CMPR1_TEA_INT_ENA (BIT(16)) -#define MCPWM_CMPR1_TEA_INT_ENA_M (BIT(16)) -#define MCPWM_CMPR1_TEA_INT_ENA_V 0x1 -#define MCPWM_CMPR1_TEA_INT_ENA_S 16 -/* MCPWM_CMPR0_TEA_INT_ENA : R/W ;bitpos:[15] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_CMPR0_TEA_INT_ENA (BIT(15)) -#define MCPWM_CMPR0_TEA_INT_ENA_M (BIT(15)) -#define MCPWM_CMPR0_TEA_INT_ENA_V 0x1 -#define MCPWM_CMPR0_TEA_INT_ENA_S 15 -/* MCPWM_FAULT2_CLR_INT_ENA : R/W ;bitpos:[14] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_FAULT2_CLR_INT_ENA (BIT(14)) -#define MCPWM_FAULT2_CLR_INT_ENA_M (BIT(14)) -#define MCPWM_FAULT2_CLR_INT_ENA_V 0x1 -#define MCPWM_FAULT2_CLR_INT_ENA_S 14 -/* MCPWM_FAULT1_CLR_INT_ENA : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_FAULT1_CLR_INT_ENA (BIT(13)) -#define MCPWM_FAULT1_CLR_INT_ENA_M (BIT(13)) -#define MCPWM_FAULT1_CLR_INT_ENA_V 0x1 -#define MCPWM_FAULT1_CLR_INT_ENA_S 13 -/* MCPWM_FAULT0_CLR_INT_ENA : R/W ;bitpos:[12] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_FAULT0_CLR_INT_ENA (BIT(12)) -#define MCPWM_FAULT0_CLR_INT_ENA_M (BIT(12)) -#define MCPWM_FAULT0_CLR_INT_ENA_V 0x1 -#define MCPWM_FAULT0_CLR_INT_ENA_S 12 -/* MCPWM_FAULT2_INT_ENA : R/W ;bitpos:[11] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_FAULT2_INT_ENA (BIT(11)) -#define MCPWM_FAULT2_INT_ENA_M (BIT(11)) -#define MCPWM_FAULT2_INT_ENA_V 0x1 -#define MCPWM_FAULT2_INT_ENA_S 11 -/* MCPWM_FAULT1_INT_ENA : R/W ;bitpos:[10] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_FAULT1_INT_ENA (BIT(10)) -#define MCPWM_FAULT1_INT_ENA_M (BIT(10)) -#define MCPWM_FAULT1_INT_ENA_V 0x1 -#define MCPWM_FAULT1_INT_ENA_S 10 -/* MCPWM_FAULT0_INT_ENA : R/W ;bitpos:[9] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_FAULT0_INT_ENA (BIT(9)) -#define MCPWM_FAULT0_INT_ENA_M (BIT(9)) -#define MCPWM_FAULT0_INT_ENA_V 0x1 -#define MCPWM_FAULT0_INT_ENA_S 9 -/* MCPWM_TIMER2_TEP_INT_ENA : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: .*/ -#define MCPWM_TIMER2_TEP_INT_ENA (BIT(8)) -#define MCPWM_TIMER2_TEP_INT_ENA_M (BIT(8)) -#define MCPWM_TIMER2_TEP_INT_ENA_V 0x1 -#define MCPWM_TIMER2_TEP_INT_ENA_S 8 -/* MCPWM_TIMER1_TEP_INT_ENA : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: .*/ -#define MCPWM_TIMER1_TEP_INT_ENA (BIT(7)) -#define MCPWM_TIMER1_TEP_INT_ENA_M (BIT(7)) -#define MCPWM_TIMER1_TEP_INT_ENA_V 0x1 -#define MCPWM_TIMER1_TEP_INT_ENA_S 7 -/* MCPWM_TIMER0_TEP_INT_ENA : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define MCPWM_TIMER0_TEP_INT_ENA (BIT(6)) -#define MCPWM_TIMER0_TEP_INT_ENA_M (BIT(6)) -#define MCPWM_TIMER0_TEP_INT_ENA_V 0x1 -#define MCPWM_TIMER0_TEP_INT_ENA_S 6 -/* MCPWM_TIMER2_TEZ_INT_ENA : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define MCPWM_TIMER2_TEZ_INT_ENA (BIT(5)) -#define MCPWM_TIMER2_TEZ_INT_ENA_M (BIT(5)) -#define MCPWM_TIMER2_TEZ_INT_ENA_V 0x1 -#define MCPWM_TIMER2_TEZ_INT_ENA_S 5 -/* MCPWM_TIMER1_TEZ_INT_ENA : R/W ;bitpos:[4] ;default: 1'h0 ; */ -/*description: .*/ -#define MCPWM_TIMER1_TEZ_INT_ENA (BIT(4)) -#define MCPWM_TIMER1_TEZ_INT_ENA_M (BIT(4)) -#define MCPWM_TIMER1_TEZ_INT_ENA_V 0x1 -#define MCPWM_TIMER1_TEZ_INT_ENA_S 4 -/* MCPWM_TIMER0_TEZ_INT_ENA : R/W ;bitpos:[3] ;default: 1'h0 ; */ -/*description: .*/ -#define MCPWM_TIMER0_TEZ_INT_ENA (BIT(3)) -#define MCPWM_TIMER0_TEZ_INT_ENA_M (BIT(3)) -#define MCPWM_TIMER0_TEZ_INT_ENA_V 0x1 -#define MCPWM_TIMER0_TEZ_INT_ENA_S 3 -/* MCPWM_TIMER2_STOP_INT_ENA : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: .*/ -#define MCPWM_TIMER2_STOP_INT_ENA (BIT(2)) -#define MCPWM_TIMER2_STOP_INT_ENA_M (BIT(2)) -#define MCPWM_TIMER2_STOP_INT_ENA_V 0x1 -#define MCPWM_TIMER2_STOP_INT_ENA_S 2 -/* MCPWM_TIMER1_STOP_INT_ENA : R/W ;bitpos:[1] ;default: 1'h0 ; */ -/*description: .*/ -#define MCPWM_TIMER1_STOP_INT_ENA (BIT(1)) -#define MCPWM_TIMER1_STOP_INT_ENA_M (BIT(1)) -#define MCPWM_TIMER1_STOP_INT_ENA_V 0x1 -#define MCPWM_TIMER1_STOP_INT_ENA_S 1 -/* MCPWM_TIMER0_STOP_INT_ENA : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: .*/ +/** MCPWM_INT_ENA_REG register + * Interrupt enable bits + */ +#define MCPWM_INT_ENA_REG(i) (DR_REG_MCPWM_BASE(i) + 0x110) +/** MCPWM_TIMER0_STOP_INT_ENA : R/W; bitpos: [0]; default: 0; + * The enable bit for the interrupt triggered when the timer 0 stops. + */ #define MCPWM_TIMER0_STOP_INT_ENA (BIT(0)) -#define MCPWM_TIMER0_STOP_INT_ENA_M (BIT(0)) -#define MCPWM_TIMER0_STOP_INT_ENA_V 0x1 +#define MCPWM_TIMER0_STOP_INT_ENA_M (MCPWM_TIMER0_STOP_INT_ENA_V << MCPWM_TIMER0_STOP_INT_ENA_S) +#define MCPWM_TIMER0_STOP_INT_ENA_V 0x00000001U #define MCPWM_TIMER0_STOP_INT_ENA_S 0 +/** MCPWM_TIMER1_STOP_INT_ENA : R/W; bitpos: [1]; default: 0; + * The enable bit for the interrupt triggered when the timer 1 stops. + */ +#define MCPWM_TIMER1_STOP_INT_ENA (BIT(1)) +#define MCPWM_TIMER1_STOP_INT_ENA_M (MCPWM_TIMER1_STOP_INT_ENA_V << MCPWM_TIMER1_STOP_INT_ENA_S) +#define MCPWM_TIMER1_STOP_INT_ENA_V 0x00000001U +#define MCPWM_TIMER1_STOP_INT_ENA_S 1 +/** MCPWM_TIMER2_STOP_INT_ENA : R/W; bitpos: [2]; default: 0; + * The enable bit for the interrupt triggered when the timer 2 stops. + */ +#define MCPWM_TIMER2_STOP_INT_ENA (BIT(2)) +#define MCPWM_TIMER2_STOP_INT_ENA_M (MCPWM_TIMER2_STOP_INT_ENA_V << MCPWM_TIMER2_STOP_INT_ENA_S) +#define MCPWM_TIMER2_STOP_INT_ENA_V 0x00000001U +#define MCPWM_TIMER2_STOP_INT_ENA_S 2 +/** MCPWM_TIMER0_TEZ_INT_ENA : R/W; bitpos: [3]; default: 0; + * The enable bit for the interrupt triggered by a PWM timer 0 TEZ event. + */ +#define MCPWM_TIMER0_TEZ_INT_ENA (BIT(3)) +#define MCPWM_TIMER0_TEZ_INT_ENA_M (MCPWM_TIMER0_TEZ_INT_ENA_V << MCPWM_TIMER0_TEZ_INT_ENA_S) +#define MCPWM_TIMER0_TEZ_INT_ENA_V 0x00000001U +#define MCPWM_TIMER0_TEZ_INT_ENA_S 3 +/** MCPWM_TIMER1_TEZ_INT_ENA : R/W; bitpos: [4]; default: 0; + * The enable bit for the interrupt triggered by a PWM timer 1 TEZ event. + */ +#define MCPWM_TIMER1_TEZ_INT_ENA (BIT(4)) +#define MCPWM_TIMER1_TEZ_INT_ENA_M (MCPWM_TIMER1_TEZ_INT_ENA_V << MCPWM_TIMER1_TEZ_INT_ENA_S) +#define MCPWM_TIMER1_TEZ_INT_ENA_V 0x00000001U +#define MCPWM_TIMER1_TEZ_INT_ENA_S 4 +/** MCPWM_TIMER2_TEZ_INT_ENA : R/W; bitpos: [5]; default: 0; + * The enable bit for the interrupt triggered by a PWM timer 2 TEZ event. + */ +#define MCPWM_TIMER2_TEZ_INT_ENA (BIT(5)) +#define MCPWM_TIMER2_TEZ_INT_ENA_M (MCPWM_TIMER2_TEZ_INT_ENA_V << MCPWM_TIMER2_TEZ_INT_ENA_S) +#define MCPWM_TIMER2_TEZ_INT_ENA_V 0x00000001U +#define MCPWM_TIMER2_TEZ_INT_ENA_S 5 +/** MCPWM_TIMER0_TEP_INT_ENA : R/W; bitpos: [6]; default: 0; + * The enable bit for the interrupt triggered by a PWM timer 0 TEP event. + */ +#define MCPWM_TIMER0_TEP_INT_ENA (BIT(6)) +#define MCPWM_TIMER0_TEP_INT_ENA_M (MCPWM_TIMER0_TEP_INT_ENA_V << MCPWM_TIMER0_TEP_INT_ENA_S) +#define MCPWM_TIMER0_TEP_INT_ENA_V 0x00000001U +#define MCPWM_TIMER0_TEP_INT_ENA_S 6 +/** MCPWM_TIMER1_TEP_INT_ENA : R/W; bitpos: [7]; default: 0; + * The enable bit for the interrupt triggered by a PWM timer 1 TEP event. + */ +#define MCPWM_TIMER1_TEP_INT_ENA (BIT(7)) +#define MCPWM_TIMER1_TEP_INT_ENA_M (MCPWM_TIMER1_TEP_INT_ENA_V << MCPWM_TIMER1_TEP_INT_ENA_S) +#define MCPWM_TIMER1_TEP_INT_ENA_V 0x00000001U +#define MCPWM_TIMER1_TEP_INT_ENA_S 7 +/** MCPWM_TIMER2_TEP_INT_ENA : R/W; bitpos: [8]; default: 0; + * The enable bit for the interrupt triggered by a PWM timer 2 TEP event. + */ +#define MCPWM_TIMER2_TEP_INT_ENA (BIT(8)) +#define MCPWM_TIMER2_TEP_INT_ENA_M (MCPWM_TIMER2_TEP_INT_ENA_V << MCPWM_TIMER2_TEP_INT_ENA_S) +#define MCPWM_TIMER2_TEP_INT_ENA_V 0x00000001U +#define MCPWM_TIMER2_TEP_INT_ENA_S 8 +/** MCPWM_FAULT0_INT_ENA : R/W; bitpos: [9]; default: 0; + * The enable bit for the interrupt triggered when fault_event0 starts. + */ +#define MCPWM_FAULT0_INT_ENA (BIT(9)) +#define MCPWM_FAULT0_INT_ENA_M (MCPWM_FAULT0_INT_ENA_V << MCPWM_FAULT0_INT_ENA_S) +#define MCPWM_FAULT0_INT_ENA_V 0x00000001U +#define MCPWM_FAULT0_INT_ENA_S 9 +/** MCPWM_FAULT1_INT_ENA : R/W; bitpos: [10]; default: 0; + * The enable bit for the interrupt triggered when fault_event1 starts. + */ +#define MCPWM_FAULT1_INT_ENA (BIT(10)) +#define MCPWM_FAULT1_INT_ENA_M (MCPWM_FAULT1_INT_ENA_V << MCPWM_FAULT1_INT_ENA_S) +#define MCPWM_FAULT1_INT_ENA_V 0x00000001U +#define MCPWM_FAULT1_INT_ENA_S 10 +/** MCPWM_FAULT2_INT_ENA : R/W; bitpos: [11]; default: 0; + * The enable bit for the interrupt triggered when fault_event2 starts. + */ +#define MCPWM_FAULT2_INT_ENA (BIT(11)) +#define MCPWM_FAULT2_INT_ENA_M (MCPWM_FAULT2_INT_ENA_V << MCPWM_FAULT2_INT_ENA_S) +#define MCPWM_FAULT2_INT_ENA_V 0x00000001U +#define MCPWM_FAULT2_INT_ENA_S 11 +/** MCPWM_FAULT0_CLR_INT_ENA : R/W; bitpos: [12]; default: 0; + * The enable bit for the interrupt triggered when fault_event0 ends. + */ +#define MCPWM_FAULT0_CLR_INT_ENA (BIT(12)) +#define MCPWM_FAULT0_CLR_INT_ENA_M (MCPWM_FAULT0_CLR_INT_ENA_V << MCPWM_FAULT0_CLR_INT_ENA_S) +#define MCPWM_FAULT0_CLR_INT_ENA_V 0x00000001U +#define MCPWM_FAULT0_CLR_INT_ENA_S 12 +/** MCPWM_FAULT1_CLR_INT_ENA : R/W; bitpos: [13]; default: 0; + * The enable bit for the interrupt triggered when fault_event1 ends. + */ +#define MCPWM_FAULT1_CLR_INT_ENA (BIT(13)) +#define MCPWM_FAULT1_CLR_INT_ENA_M (MCPWM_FAULT1_CLR_INT_ENA_V << MCPWM_FAULT1_CLR_INT_ENA_S) +#define MCPWM_FAULT1_CLR_INT_ENA_V 0x00000001U +#define MCPWM_FAULT1_CLR_INT_ENA_S 13 +/** MCPWM_FAULT2_CLR_INT_ENA : R/W; bitpos: [14]; default: 0; + * The enable bit for the interrupt triggered when fault_event2 ends. + */ +#define MCPWM_FAULT2_CLR_INT_ENA (BIT(14)) +#define MCPWM_FAULT2_CLR_INT_ENA_M (MCPWM_FAULT2_CLR_INT_ENA_V << MCPWM_FAULT2_CLR_INT_ENA_S) +#define MCPWM_FAULT2_CLR_INT_ENA_V 0x00000001U +#define MCPWM_FAULT2_CLR_INT_ENA_S 14 +/** MCPWM_OP0_TEA_INT_ENA : R/W; bitpos: [15]; default: 0; + * The enable bit for the interrupt triggered by a PWM operator 0 TEA event + */ +#define MCPWM_OP0_TEA_INT_ENA (BIT(15)) +#define MCPWM_OP0_TEA_INT_ENA_M (MCPWM_OP0_TEA_INT_ENA_V << MCPWM_OP0_TEA_INT_ENA_S) +#define MCPWM_OP0_TEA_INT_ENA_V 0x00000001U +#define MCPWM_OP0_TEA_INT_ENA_S 15 +/** MCPWM_OP1_TEA_INT_ENA : R/W; bitpos: [16]; default: 0; + * The enable bit for the interrupt triggered by a PWM operator 1 TEA event + */ +#define MCPWM_OP1_TEA_INT_ENA (BIT(16)) +#define MCPWM_OP1_TEA_INT_ENA_M (MCPWM_OP1_TEA_INT_ENA_V << MCPWM_OP1_TEA_INT_ENA_S) +#define MCPWM_OP1_TEA_INT_ENA_V 0x00000001U +#define MCPWM_OP1_TEA_INT_ENA_S 16 +/** MCPWM_OP2_TEA_INT_ENA : R/W; bitpos: [17]; default: 0; + * The enable bit for the interrupt triggered by a PWM operator 2 TEA event + */ +#define MCPWM_OP2_TEA_INT_ENA (BIT(17)) +#define MCPWM_OP2_TEA_INT_ENA_M (MCPWM_OP2_TEA_INT_ENA_V << MCPWM_OP2_TEA_INT_ENA_S) +#define MCPWM_OP2_TEA_INT_ENA_V 0x00000001U +#define MCPWM_OP2_TEA_INT_ENA_S 17 +/** MCPWM_OP0_TEB_INT_ENA : R/W; bitpos: [18]; default: 0; + * The enable bit for the interrupt triggered by a PWM operator 0 TEB event + */ +#define MCPWM_OP0_TEB_INT_ENA (BIT(18)) +#define MCPWM_OP0_TEB_INT_ENA_M (MCPWM_OP0_TEB_INT_ENA_V << MCPWM_OP0_TEB_INT_ENA_S) +#define MCPWM_OP0_TEB_INT_ENA_V 0x00000001U +#define MCPWM_OP0_TEB_INT_ENA_S 18 +/** MCPWM_OP1_TEB_INT_ENA : R/W; bitpos: [19]; default: 0; + * The enable bit for the interrupt triggered by a PWM operator 1 TEB event + */ +#define MCPWM_OP1_TEB_INT_ENA (BIT(19)) +#define MCPWM_OP1_TEB_INT_ENA_M (MCPWM_OP1_TEB_INT_ENA_V << MCPWM_OP1_TEB_INT_ENA_S) +#define MCPWM_OP1_TEB_INT_ENA_V 0x00000001U +#define MCPWM_OP1_TEB_INT_ENA_S 19 +/** MCPWM_OP2_TEB_INT_ENA : R/W; bitpos: [20]; default: 0; + * The enable bit for the interrupt triggered by a PWM operator 2 TEB event + */ +#define MCPWM_OP2_TEB_INT_ENA (BIT(20)) +#define MCPWM_OP2_TEB_INT_ENA_M (MCPWM_OP2_TEB_INT_ENA_V << MCPWM_OP2_TEB_INT_ENA_S) +#define MCPWM_OP2_TEB_INT_ENA_V 0x00000001U +#define MCPWM_OP2_TEB_INT_ENA_S 20 +/** MCPWM_FH0_CBC_INT_ENA : R/W; bitpos: [21]; default: 0; + * The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0. + */ +#define MCPWM_FH0_CBC_INT_ENA (BIT(21)) +#define MCPWM_FH0_CBC_INT_ENA_M (MCPWM_FH0_CBC_INT_ENA_V << MCPWM_FH0_CBC_INT_ENA_S) +#define MCPWM_FH0_CBC_INT_ENA_V 0x00000001U +#define MCPWM_FH0_CBC_INT_ENA_S 21 +/** MCPWM_FH1_CBC_INT_ENA : R/W; bitpos: [22]; default: 0; + * The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1. + */ +#define MCPWM_FH1_CBC_INT_ENA (BIT(22)) +#define MCPWM_FH1_CBC_INT_ENA_M (MCPWM_FH1_CBC_INT_ENA_V << MCPWM_FH1_CBC_INT_ENA_S) +#define MCPWM_FH1_CBC_INT_ENA_V 0x00000001U +#define MCPWM_FH1_CBC_INT_ENA_S 22 +/** MCPWM_FH2_CBC_INT_ENA : R/W; bitpos: [23]; default: 0; + * The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2. + */ +#define MCPWM_FH2_CBC_INT_ENA (BIT(23)) +#define MCPWM_FH2_CBC_INT_ENA_M (MCPWM_FH2_CBC_INT_ENA_V << MCPWM_FH2_CBC_INT_ENA_S) +#define MCPWM_FH2_CBC_INT_ENA_V 0x00000001U +#define MCPWM_FH2_CBC_INT_ENA_S 23 +/** MCPWM_FH0_OST_INT_ENA : R/W; bitpos: [24]; default: 0; + * The enable bit for the interrupt triggered by a one-shot mode action on PWM0. + */ +#define MCPWM_FH0_OST_INT_ENA (BIT(24)) +#define MCPWM_FH0_OST_INT_ENA_M (MCPWM_FH0_OST_INT_ENA_V << MCPWM_FH0_OST_INT_ENA_S) +#define MCPWM_FH0_OST_INT_ENA_V 0x00000001U +#define MCPWM_FH0_OST_INT_ENA_S 24 +/** MCPWM_FH1_OST_INT_ENA : R/W; bitpos: [25]; default: 0; + * The enable bit for the interrupt triggered by a one-shot mode action on PWM1. + */ +#define MCPWM_FH1_OST_INT_ENA (BIT(25)) +#define MCPWM_FH1_OST_INT_ENA_M (MCPWM_FH1_OST_INT_ENA_V << MCPWM_FH1_OST_INT_ENA_S) +#define MCPWM_FH1_OST_INT_ENA_V 0x00000001U +#define MCPWM_FH1_OST_INT_ENA_S 25 +/** MCPWM_FH2_OST_INT_ENA : R/W; bitpos: [26]; default: 0; + * The enable bit for the interrupt triggered by a one-shot mode action on PWM2. + */ +#define MCPWM_FH2_OST_INT_ENA (BIT(26)) +#define MCPWM_FH2_OST_INT_ENA_M (MCPWM_FH2_OST_INT_ENA_V << MCPWM_FH2_OST_INT_ENA_S) +#define MCPWM_FH2_OST_INT_ENA_V 0x00000001U +#define MCPWM_FH2_OST_INT_ENA_S 26 +/** MCPWM_CAP0_INT_ENA : R/W; bitpos: [27]; default: 0; + * The enable bit for the interrupt triggered by capture on channel 0. + */ +#define MCPWM_CAP0_INT_ENA (BIT(27)) +#define MCPWM_CAP0_INT_ENA_M (MCPWM_CAP0_INT_ENA_V << MCPWM_CAP0_INT_ENA_S) +#define MCPWM_CAP0_INT_ENA_V 0x00000001U +#define MCPWM_CAP0_INT_ENA_S 27 +/** MCPWM_CAP1_INT_ENA : R/W; bitpos: [28]; default: 0; + * The enable bit for the interrupt triggered by capture on channel 1. + */ +#define MCPWM_CAP1_INT_ENA (BIT(28)) +#define MCPWM_CAP1_INT_ENA_M (MCPWM_CAP1_INT_ENA_V << MCPWM_CAP1_INT_ENA_S) +#define MCPWM_CAP1_INT_ENA_V 0x00000001U +#define MCPWM_CAP1_INT_ENA_S 28 +/** MCPWM_CAP2_INT_ENA : R/W; bitpos: [29]; default: 0; + * The enable bit for the interrupt triggered by capture on channel 2. + */ +#define MCPWM_CAP2_INT_ENA (BIT(29)) +#define MCPWM_CAP2_INT_ENA_M (MCPWM_CAP2_INT_ENA_V << MCPWM_CAP2_INT_ENA_S) +#define MCPWM_CAP2_INT_ENA_V 0x00000001U +#define MCPWM_CAP2_INT_ENA_S 29 -#define MCPWM_INT_RAW_PWM_REG(i) (REG_MCPWM_BASE(i) + 0x114) -/* MCPWM_CAP2_INT_RAW : RO ;bitpos:[29] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_CAP2_INT_RAW (BIT(29)) -#define MCPWM_CAP2_INT_RAW_M (BIT(29)) -#define MCPWM_CAP2_INT_RAW_V 0x1 -#define MCPWM_CAP2_INT_RAW_S 29 -/* MCPWM_CAP1_INT_RAW : RO ;bitpos:[28] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_CAP1_INT_RAW (BIT(28)) -#define MCPWM_CAP1_INT_RAW_M (BIT(28)) -#define MCPWM_CAP1_INT_RAW_V 0x1 -#define MCPWM_CAP1_INT_RAW_S 28 -/* MCPWM_CAP0_INT_RAW : RO ;bitpos:[27] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_CAP0_INT_RAW (BIT(27)) -#define MCPWM_CAP0_INT_RAW_M (BIT(27)) -#define MCPWM_CAP0_INT_RAW_V 0x1 -#define MCPWM_CAP0_INT_RAW_S 27 -/* MCPWM_TZ2_OST_INT_RAW : RO ;bitpos:[26] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_TZ2_OST_INT_RAW (BIT(26)) -#define MCPWM_TZ2_OST_INT_RAW_M (BIT(26)) -#define MCPWM_TZ2_OST_INT_RAW_V 0x1 -#define MCPWM_TZ2_OST_INT_RAW_S 26 -/* MCPWM_TZ1_OST_INT_RAW : RO ;bitpos:[25] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_TZ1_OST_INT_RAW (BIT(25)) -#define MCPWM_TZ1_OST_INT_RAW_M (BIT(25)) -#define MCPWM_TZ1_OST_INT_RAW_V 0x1 -#define MCPWM_TZ1_OST_INT_RAW_S 25 -/* MCPWM_TZ0_OST_INT_RAW : RO ;bitpos:[24] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_TZ0_OST_INT_RAW (BIT(24)) -#define MCPWM_TZ0_OST_INT_RAW_M (BIT(24)) -#define MCPWM_TZ0_OST_INT_RAW_V 0x1 -#define MCPWM_TZ0_OST_INT_RAW_S 24 -/* MCPWM_TZ2_CBC_INT_RAW : RO ;bitpos:[23] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_TZ2_CBC_INT_RAW (BIT(23)) -#define MCPWM_TZ2_CBC_INT_RAW_M (BIT(23)) -#define MCPWM_TZ2_CBC_INT_RAW_V 0x1 -#define MCPWM_TZ2_CBC_INT_RAW_S 23 -/* MCPWM_TZ1_CBC_INT_RAW : RO ;bitpos:[22] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_TZ1_CBC_INT_RAW (BIT(22)) -#define MCPWM_TZ1_CBC_INT_RAW_M (BIT(22)) -#define MCPWM_TZ1_CBC_INT_RAW_V 0x1 -#define MCPWM_TZ1_CBC_INT_RAW_S 22 -/* MCPWM_TZ0_CBC_INT_RAW : RO ;bitpos:[21] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_TZ0_CBC_INT_RAW (BIT(21)) -#define MCPWM_TZ0_CBC_INT_RAW_M (BIT(21)) -#define MCPWM_TZ0_CBC_INT_RAW_V 0x1 -#define MCPWM_TZ0_CBC_INT_RAW_S 21 -/* MCPWM_CMPR2_TEB_INT_RAW : RO ;bitpos:[20] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_CMPR2_TEB_INT_RAW (BIT(20)) -#define MCPWM_CMPR2_TEB_INT_RAW_M (BIT(20)) -#define MCPWM_CMPR2_TEB_INT_RAW_V 0x1 -#define MCPWM_CMPR2_TEB_INT_RAW_S 20 -/* MCPWM_CMPR1_TEB_INT_RAW : RO ;bitpos:[19] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_CMPR1_TEB_INT_RAW (BIT(19)) -#define MCPWM_CMPR1_TEB_INT_RAW_M (BIT(19)) -#define MCPWM_CMPR1_TEB_INT_RAW_V 0x1 -#define MCPWM_CMPR1_TEB_INT_RAW_S 19 -/* MCPWM_CMPR0_TEB_INT_RAW : RO ;bitpos:[18] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_CMPR0_TEB_INT_RAW (BIT(18)) -#define MCPWM_CMPR0_TEB_INT_RAW_M (BIT(18)) -#define MCPWM_CMPR0_TEB_INT_RAW_V 0x1 -#define MCPWM_CMPR0_TEB_INT_RAW_S 18 -/* MCPWM_CMPR2_TEA_INT_RAW : RO ;bitpos:[17] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_CMPR2_TEA_INT_RAW (BIT(17)) -#define MCPWM_CMPR2_TEA_INT_RAW_M (BIT(17)) -#define MCPWM_CMPR2_TEA_INT_RAW_V 0x1 -#define MCPWM_CMPR2_TEA_INT_RAW_S 17 -/* MCPWM_CMPR1_TEA_INT_RAW : RO ;bitpos:[16] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_CMPR1_TEA_INT_RAW (BIT(16)) -#define MCPWM_CMPR1_TEA_INT_RAW_M (BIT(16)) -#define MCPWM_CMPR1_TEA_INT_RAW_V 0x1 -#define MCPWM_CMPR1_TEA_INT_RAW_S 16 -/* MCPWM_CMPR0_TEA_INT_RAW : RO ;bitpos:[15] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_CMPR0_TEA_INT_RAW (BIT(15)) -#define MCPWM_CMPR0_TEA_INT_RAW_M (BIT(15)) -#define MCPWM_CMPR0_TEA_INT_RAW_V 0x1 -#define MCPWM_CMPR0_TEA_INT_RAW_S 15 -/* MCPWM_FAULT2_CLR_INT_RAW : RO ;bitpos:[14] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_FAULT2_CLR_INT_RAW (BIT(14)) -#define MCPWM_FAULT2_CLR_INT_RAW_M (BIT(14)) -#define MCPWM_FAULT2_CLR_INT_RAW_V 0x1 -#define MCPWM_FAULT2_CLR_INT_RAW_S 14 -/* MCPWM_FAULT1_CLR_INT_RAW : RO ;bitpos:[13] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_FAULT1_CLR_INT_RAW (BIT(13)) -#define MCPWM_FAULT1_CLR_INT_RAW_M (BIT(13)) -#define MCPWM_FAULT1_CLR_INT_RAW_V 0x1 -#define MCPWM_FAULT1_CLR_INT_RAW_S 13 -/* MCPWM_FAULT0_CLR_INT_RAW : RO ;bitpos:[12] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_FAULT0_CLR_INT_RAW (BIT(12)) -#define MCPWM_FAULT0_CLR_INT_RAW_M (BIT(12)) -#define MCPWM_FAULT0_CLR_INT_RAW_V 0x1 -#define MCPWM_FAULT0_CLR_INT_RAW_S 12 -/* MCPWM_FAULT2_INT_RAW : RO ;bitpos:[11] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_FAULT2_INT_RAW (BIT(11)) -#define MCPWM_FAULT2_INT_RAW_M (BIT(11)) -#define MCPWM_FAULT2_INT_RAW_V 0x1 -#define MCPWM_FAULT2_INT_RAW_S 11 -/* MCPWM_FAULT1_INT_RAW : RO ;bitpos:[10] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_FAULT1_INT_RAW (BIT(10)) -#define MCPWM_FAULT1_INT_RAW_M (BIT(10)) -#define MCPWM_FAULT1_INT_RAW_V 0x1 -#define MCPWM_FAULT1_INT_RAW_S 10 -/* MCPWM_FAULT0_INT_RAW : RO ;bitpos:[9] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_FAULT0_INT_RAW (BIT(9)) -#define MCPWM_FAULT0_INT_RAW_M (BIT(9)) -#define MCPWM_FAULT0_INT_RAW_V 0x1 -#define MCPWM_FAULT0_INT_RAW_S 9 -/* MCPWM_TIMER2_TEP_INT_RAW : RO ;bitpos:[8] ;default: 1'h0 ; */ -/*description: .*/ -#define MCPWM_TIMER2_TEP_INT_RAW (BIT(8)) -#define MCPWM_TIMER2_TEP_INT_RAW_M (BIT(8)) -#define MCPWM_TIMER2_TEP_INT_RAW_V 0x1 -#define MCPWM_TIMER2_TEP_INT_RAW_S 8 -/* MCPWM_TIMER1_TEP_INT_RAW : RO ;bitpos:[7] ;default: 1'h0 ; */ -/*description: .*/ -#define MCPWM_TIMER1_TEP_INT_RAW (BIT(7)) -#define MCPWM_TIMER1_TEP_INT_RAW_M (BIT(7)) -#define MCPWM_TIMER1_TEP_INT_RAW_V 0x1 -#define MCPWM_TIMER1_TEP_INT_RAW_S 7 -/* MCPWM_TIMER0_TEP_INT_RAW : RO ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define MCPWM_TIMER0_TEP_INT_RAW (BIT(6)) -#define MCPWM_TIMER0_TEP_INT_RAW_M (BIT(6)) -#define MCPWM_TIMER0_TEP_INT_RAW_V 0x1 -#define MCPWM_TIMER0_TEP_INT_RAW_S 6 -/* MCPWM_TIMER2_TEZ_INT_RAW : RO ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define MCPWM_TIMER2_TEZ_INT_RAW (BIT(5)) -#define MCPWM_TIMER2_TEZ_INT_RAW_M (BIT(5)) -#define MCPWM_TIMER2_TEZ_INT_RAW_V 0x1 -#define MCPWM_TIMER2_TEZ_INT_RAW_S 5 -/* MCPWM_TIMER1_TEZ_INT_RAW : RO ;bitpos:[4] ;default: 1'h0 ; */ -/*description: .*/ -#define MCPWM_TIMER1_TEZ_INT_RAW (BIT(4)) -#define MCPWM_TIMER1_TEZ_INT_RAW_M (BIT(4)) -#define MCPWM_TIMER1_TEZ_INT_RAW_V 0x1 -#define MCPWM_TIMER1_TEZ_INT_RAW_S 4 -/* MCPWM_TIMER0_TEZ_INT_RAW : RO ;bitpos:[3] ;default: 1'h0 ; */ -/*description: .*/ -#define MCPWM_TIMER0_TEZ_INT_RAW (BIT(3)) -#define MCPWM_TIMER0_TEZ_INT_RAW_M (BIT(3)) -#define MCPWM_TIMER0_TEZ_INT_RAW_V 0x1 -#define MCPWM_TIMER0_TEZ_INT_RAW_S 3 -/* MCPWM_TIMER2_STOP_INT_RAW : RO ;bitpos:[2] ;default: 1'h0 ; */ -/*description: .*/ -#define MCPWM_TIMER2_STOP_INT_RAW (BIT(2)) -#define MCPWM_TIMER2_STOP_INT_RAW_M (BIT(2)) -#define MCPWM_TIMER2_STOP_INT_RAW_V 0x1 -#define MCPWM_TIMER2_STOP_INT_RAW_S 2 -/* MCPWM_TIMER1_STOP_INT_RAW : RO ;bitpos:[1] ;default: 1'h0 ; */ -/*description: .*/ -#define MCPWM_TIMER1_STOP_INT_RAW (BIT(1)) -#define MCPWM_TIMER1_STOP_INT_RAW_M (BIT(1)) -#define MCPWM_TIMER1_STOP_INT_RAW_V 0x1 -#define MCPWM_TIMER1_STOP_INT_RAW_S 1 -/* MCPWM_TIMER0_STOP_INT_RAW : RO ;bitpos:[0] ;default: 1'h0 ; */ -/*description: .*/ +/** MCPWM_INT_RAW_REG register + * Raw interrupt status + */ +#define MCPWM_INT_RAW_REG(i) (DR_REG_MCPWM_BASE(i) + 0x114) +/** MCPWM_TIMER0_STOP_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw status bit for the interrupt triggered when the timer 0 stops. + */ #define MCPWM_TIMER0_STOP_INT_RAW (BIT(0)) -#define MCPWM_TIMER0_STOP_INT_RAW_M (BIT(0)) -#define MCPWM_TIMER0_STOP_INT_RAW_V 0x1 +#define MCPWM_TIMER0_STOP_INT_RAW_M (MCPWM_TIMER0_STOP_INT_RAW_V << MCPWM_TIMER0_STOP_INT_RAW_S) +#define MCPWM_TIMER0_STOP_INT_RAW_V 0x00000001U #define MCPWM_TIMER0_STOP_INT_RAW_S 0 +/** MCPWM_TIMER1_STOP_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw status bit for the interrupt triggered when the timer 1 stops. + */ +#define MCPWM_TIMER1_STOP_INT_RAW (BIT(1)) +#define MCPWM_TIMER1_STOP_INT_RAW_M (MCPWM_TIMER1_STOP_INT_RAW_V << MCPWM_TIMER1_STOP_INT_RAW_S) +#define MCPWM_TIMER1_STOP_INT_RAW_V 0x00000001U +#define MCPWM_TIMER1_STOP_INT_RAW_S 1 +/** MCPWM_TIMER2_STOP_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw status bit for the interrupt triggered when the timer 2 stops. + */ +#define MCPWM_TIMER2_STOP_INT_RAW (BIT(2)) +#define MCPWM_TIMER2_STOP_INT_RAW_M (MCPWM_TIMER2_STOP_INT_RAW_V << MCPWM_TIMER2_STOP_INT_RAW_S) +#define MCPWM_TIMER2_STOP_INT_RAW_V 0x00000001U +#define MCPWM_TIMER2_STOP_INT_RAW_S 2 +/** MCPWM_TIMER0_TEZ_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw status bit for the interrupt triggered by a PWM timer 0 TEZ event. + */ +#define MCPWM_TIMER0_TEZ_INT_RAW (BIT(3)) +#define MCPWM_TIMER0_TEZ_INT_RAW_M (MCPWM_TIMER0_TEZ_INT_RAW_V << MCPWM_TIMER0_TEZ_INT_RAW_S) +#define MCPWM_TIMER0_TEZ_INT_RAW_V 0x00000001U +#define MCPWM_TIMER0_TEZ_INT_RAW_S 3 +/** MCPWM_TIMER1_TEZ_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw status bit for the interrupt triggered by a PWM timer 1 TEZ event. + */ +#define MCPWM_TIMER1_TEZ_INT_RAW (BIT(4)) +#define MCPWM_TIMER1_TEZ_INT_RAW_M (MCPWM_TIMER1_TEZ_INT_RAW_V << MCPWM_TIMER1_TEZ_INT_RAW_S) +#define MCPWM_TIMER1_TEZ_INT_RAW_V 0x00000001U +#define MCPWM_TIMER1_TEZ_INT_RAW_S 4 +/** MCPWM_TIMER2_TEZ_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * The raw status bit for the interrupt triggered by a PWM timer 2 TEZ event. + */ +#define MCPWM_TIMER2_TEZ_INT_RAW (BIT(5)) +#define MCPWM_TIMER2_TEZ_INT_RAW_M (MCPWM_TIMER2_TEZ_INT_RAW_V << MCPWM_TIMER2_TEZ_INT_RAW_S) +#define MCPWM_TIMER2_TEZ_INT_RAW_V 0x00000001U +#define MCPWM_TIMER2_TEZ_INT_RAW_S 5 +/** MCPWM_TIMER0_TEP_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * The raw status bit for the interrupt triggered by a PWM timer 0 TEP event. + */ +#define MCPWM_TIMER0_TEP_INT_RAW (BIT(6)) +#define MCPWM_TIMER0_TEP_INT_RAW_M (MCPWM_TIMER0_TEP_INT_RAW_V << MCPWM_TIMER0_TEP_INT_RAW_S) +#define MCPWM_TIMER0_TEP_INT_RAW_V 0x00000001U +#define MCPWM_TIMER0_TEP_INT_RAW_S 6 +/** MCPWM_TIMER1_TEP_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * The raw status bit for the interrupt triggered by a PWM timer 1 TEP event. + */ +#define MCPWM_TIMER1_TEP_INT_RAW (BIT(7)) +#define MCPWM_TIMER1_TEP_INT_RAW_M (MCPWM_TIMER1_TEP_INT_RAW_V << MCPWM_TIMER1_TEP_INT_RAW_S) +#define MCPWM_TIMER1_TEP_INT_RAW_V 0x00000001U +#define MCPWM_TIMER1_TEP_INT_RAW_S 7 +/** MCPWM_TIMER2_TEP_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * The raw status bit for the interrupt triggered by a PWM timer 2 TEP event. + */ +#define MCPWM_TIMER2_TEP_INT_RAW (BIT(8)) +#define MCPWM_TIMER2_TEP_INT_RAW_M (MCPWM_TIMER2_TEP_INT_RAW_V << MCPWM_TIMER2_TEP_INT_RAW_S) +#define MCPWM_TIMER2_TEP_INT_RAW_V 0x00000001U +#define MCPWM_TIMER2_TEP_INT_RAW_S 8 +/** MCPWM_FAULT0_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * The raw status bit for the interrupt triggered when fault_event0 starts. + */ +#define MCPWM_FAULT0_INT_RAW (BIT(9)) +#define MCPWM_FAULT0_INT_RAW_M (MCPWM_FAULT0_INT_RAW_V << MCPWM_FAULT0_INT_RAW_S) +#define MCPWM_FAULT0_INT_RAW_V 0x00000001U +#define MCPWM_FAULT0_INT_RAW_S 9 +/** MCPWM_FAULT1_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * The raw status bit for the interrupt triggered when fault_event1 starts. + */ +#define MCPWM_FAULT1_INT_RAW (BIT(10)) +#define MCPWM_FAULT1_INT_RAW_M (MCPWM_FAULT1_INT_RAW_V << MCPWM_FAULT1_INT_RAW_S) +#define MCPWM_FAULT1_INT_RAW_V 0x00000001U +#define MCPWM_FAULT1_INT_RAW_S 10 +/** MCPWM_FAULT2_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; + * The raw status bit for the interrupt triggered when fault_event2 starts. + */ +#define MCPWM_FAULT2_INT_RAW (BIT(11)) +#define MCPWM_FAULT2_INT_RAW_M (MCPWM_FAULT2_INT_RAW_V << MCPWM_FAULT2_INT_RAW_S) +#define MCPWM_FAULT2_INT_RAW_V 0x00000001U +#define MCPWM_FAULT2_INT_RAW_S 11 +/** MCPWM_FAULT0_CLR_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * The raw status bit for the interrupt triggered when fault_event0 ends. + */ +#define MCPWM_FAULT0_CLR_INT_RAW (BIT(12)) +#define MCPWM_FAULT0_CLR_INT_RAW_M (MCPWM_FAULT0_CLR_INT_RAW_V << MCPWM_FAULT0_CLR_INT_RAW_S) +#define MCPWM_FAULT0_CLR_INT_RAW_V 0x00000001U +#define MCPWM_FAULT0_CLR_INT_RAW_S 12 +/** MCPWM_FAULT1_CLR_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; + * The raw status bit for the interrupt triggered when fault_event1 ends. + */ +#define MCPWM_FAULT1_CLR_INT_RAW (BIT(13)) +#define MCPWM_FAULT1_CLR_INT_RAW_M (MCPWM_FAULT1_CLR_INT_RAW_V << MCPWM_FAULT1_CLR_INT_RAW_S) +#define MCPWM_FAULT1_CLR_INT_RAW_V 0x00000001U +#define MCPWM_FAULT1_CLR_INT_RAW_S 13 +/** MCPWM_FAULT2_CLR_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; + * The raw status bit for the interrupt triggered when fault_event2 ends. + */ +#define MCPWM_FAULT2_CLR_INT_RAW (BIT(14)) +#define MCPWM_FAULT2_CLR_INT_RAW_M (MCPWM_FAULT2_CLR_INT_RAW_V << MCPWM_FAULT2_CLR_INT_RAW_S) +#define MCPWM_FAULT2_CLR_INT_RAW_V 0x00000001U +#define MCPWM_FAULT2_CLR_INT_RAW_S 14 +/** MCPWM_OP0_TEA_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; + * The raw status bit for the interrupt triggered by a PWM operator 0 TEA event + */ +#define MCPWM_OP0_TEA_INT_RAW (BIT(15)) +#define MCPWM_OP0_TEA_INT_RAW_M (MCPWM_OP0_TEA_INT_RAW_V << MCPWM_OP0_TEA_INT_RAW_S) +#define MCPWM_OP0_TEA_INT_RAW_V 0x00000001U +#define MCPWM_OP0_TEA_INT_RAW_S 15 +/** MCPWM_OP1_TEA_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0; + * The raw status bit for the interrupt triggered by a PWM operator 1 TEA event + */ +#define MCPWM_OP1_TEA_INT_RAW (BIT(16)) +#define MCPWM_OP1_TEA_INT_RAW_M (MCPWM_OP1_TEA_INT_RAW_V << MCPWM_OP1_TEA_INT_RAW_S) +#define MCPWM_OP1_TEA_INT_RAW_V 0x00000001U +#define MCPWM_OP1_TEA_INT_RAW_S 16 +/** MCPWM_OP2_TEA_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0; + * The raw status bit for the interrupt triggered by a PWM operator 2 TEA event + */ +#define MCPWM_OP2_TEA_INT_RAW (BIT(17)) +#define MCPWM_OP2_TEA_INT_RAW_M (MCPWM_OP2_TEA_INT_RAW_V << MCPWM_OP2_TEA_INT_RAW_S) +#define MCPWM_OP2_TEA_INT_RAW_V 0x00000001U +#define MCPWM_OP2_TEA_INT_RAW_S 17 +/** MCPWM_OP0_TEB_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0; + * The raw status bit for the interrupt triggered by a PWM operator 0 TEB event + */ +#define MCPWM_OP0_TEB_INT_RAW (BIT(18)) +#define MCPWM_OP0_TEB_INT_RAW_M (MCPWM_OP0_TEB_INT_RAW_V << MCPWM_OP0_TEB_INT_RAW_S) +#define MCPWM_OP0_TEB_INT_RAW_V 0x00000001U +#define MCPWM_OP0_TEB_INT_RAW_S 18 +/** MCPWM_OP1_TEB_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0; + * The raw status bit for the interrupt triggered by a PWM operator 1 TEB event + */ +#define MCPWM_OP1_TEB_INT_RAW (BIT(19)) +#define MCPWM_OP1_TEB_INT_RAW_M (MCPWM_OP1_TEB_INT_RAW_V << MCPWM_OP1_TEB_INT_RAW_S) +#define MCPWM_OP1_TEB_INT_RAW_V 0x00000001U +#define MCPWM_OP1_TEB_INT_RAW_S 19 +/** MCPWM_OP2_TEB_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0; + * The raw status bit for the interrupt triggered by a PWM operator 2 TEB event + */ +#define MCPWM_OP2_TEB_INT_RAW (BIT(20)) +#define MCPWM_OP2_TEB_INT_RAW_M (MCPWM_OP2_TEB_INT_RAW_V << MCPWM_OP2_TEB_INT_RAW_S) +#define MCPWM_OP2_TEB_INT_RAW_V 0x00000001U +#define MCPWM_OP2_TEB_INT_RAW_S 20 +/** MCPWM_FH0_CBC_INT_RAW : R/WTC/SS; bitpos: [21]; default: 0; + * The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on + * PWM0. + */ +#define MCPWM_FH0_CBC_INT_RAW (BIT(21)) +#define MCPWM_FH0_CBC_INT_RAW_M (MCPWM_FH0_CBC_INT_RAW_V << MCPWM_FH0_CBC_INT_RAW_S) +#define MCPWM_FH0_CBC_INT_RAW_V 0x00000001U +#define MCPWM_FH0_CBC_INT_RAW_S 21 +/** MCPWM_FH1_CBC_INT_RAW : R/WTC/SS; bitpos: [22]; default: 0; + * The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on + * PWM1. + */ +#define MCPWM_FH1_CBC_INT_RAW (BIT(22)) +#define MCPWM_FH1_CBC_INT_RAW_M (MCPWM_FH1_CBC_INT_RAW_V << MCPWM_FH1_CBC_INT_RAW_S) +#define MCPWM_FH1_CBC_INT_RAW_V 0x00000001U +#define MCPWM_FH1_CBC_INT_RAW_S 22 +/** MCPWM_FH2_CBC_INT_RAW : R/WTC/SS; bitpos: [23]; default: 0; + * The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on + * PWM2. + */ +#define MCPWM_FH2_CBC_INT_RAW (BIT(23)) +#define MCPWM_FH2_CBC_INT_RAW_M (MCPWM_FH2_CBC_INT_RAW_V << MCPWM_FH2_CBC_INT_RAW_S) +#define MCPWM_FH2_CBC_INT_RAW_V 0x00000001U +#define MCPWM_FH2_CBC_INT_RAW_S 23 +/** MCPWM_FH0_OST_INT_RAW : R/WTC/SS; bitpos: [24]; default: 0; + * The raw status bit for the interrupt triggered by a one-shot mode action on PWM0. + */ +#define MCPWM_FH0_OST_INT_RAW (BIT(24)) +#define MCPWM_FH0_OST_INT_RAW_M (MCPWM_FH0_OST_INT_RAW_V << MCPWM_FH0_OST_INT_RAW_S) +#define MCPWM_FH0_OST_INT_RAW_V 0x00000001U +#define MCPWM_FH0_OST_INT_RAW_S 24 +/** MCPWM_FH1_OST_INT_RAW : R/WTC/SS; bitpos: [25]; default: 0; + * The raw status bit for the interrupt triggered by a one-shot mode action on PWM1. + */ +#define MCPWM_FH1_OST_INT_RAW (BIT(25)) +#define MCPWM_FH1_OST_INT_RAW_M (MCPWM_FH1_OST_INT_RAW_V << MCPWM_FH1_OST_INT_RAW_S) +#define MCPWM_FH1_OST_INT_RAW_V 0x00000001U +#define MCPWM_FH1_OST_INT_RAW_S 25 +/** MCPWM_FH2_OST_INT_RAW : R/WTC/SS; bitpos: [26]; default: 0; + * The raw status bit for the interrupt triggered by a one-shot mode action on PWM2. + */ +#define MCPWM_FH2_OST_INT_RAW (BIT(26)) +#define MCPWM_FH2_OST_INT_RAW_M (MCPWM_FH2_OST_INT_RAW_V << MCPWM_FH2_OST_INT_RAW_S) +#define MCPWM_FH2_OST_INT_RAW_V 0x00000001U +#define MCPWM_FH2_OST_INT_RAW_S 26 +/** MCPWM_CAP0_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0; + * The raw status bit for the interrupt triggered by capture on channel 0. + */ +#define MCPWM_CAP0_INT_RAW (BIT(27)) +#define MCPWM_CAP0_INT_RAW_M (MCPWM_CAP0_INT_RAW_V << MCPWM_CAP0_INT_RAW_S) +#define MCPWM_CAP0_INT_RAW_V 0x00000001U +#define MCPWM_CAP0_INT_RAW_S 27 +/** MCPWM_CAP1_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0; + * The raw status bit for the interrupt triggered by capture on channel 1. + */ +#define MCPWM_CAP1_INT_RAW (BIT(28)) +#define MCPWM_CAP1_INT_RAW_M (MCPWM_CAP1_INT_RAW_V << MCPWM_CAP1_INT_RAW_S) +#define MCPWM_CAP1_INT_RAW_V 0x00000001U +#define MCPWM_CAP1_INT_RAW_S 28 +/** MCPWM_CAP2_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0; + * The raw status bit for the interrupt triggered by capture on channel 2. + */ +#define MCPWM_CAP2_INT_RAW (BIT(29)) +#define MCPWM_CAP2_INT_RAW_M (MCPWM_CAP2_INT_RAW_V << MCPWM_CAP2_INT_RAW_S) +#define MCPWM_CAP2_INT_RAW_V 0x00000001U +#define MCPWM_CAP2_INT_RAW_S 29 -#define MCPWM_INT_ST_PWM_REG(i) (REG_MCPWM_BASE(i) + 0x118) -/* MCPWM_CAP2_INT_ST : RO ;bitpos:[29] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_CAP2_INT_ST (BIT(29)) -#define MCPWM_CAP2_INT_ST_M (BIT(29)) -#define MCPWM_CAP2_INT_ST_V 0x1 -#define MCPWM_CAP2_INT_ST_S 29 -/* MCPWM_CAP1_INT_ST : RO ;bitpos:[28] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_CAP1_INT_ST (BIT(28)) -#define MCPWM_CAP1_INT_ST_M (BIT(28)) -#define MCPWM_CAP1_INT_ST_V 0x1 -#define MCPWM_CAP1_INT_ST_S 28 -/* MCPWM_CAP0_INT_ST : RO ;bitpos:[27] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_CAP0_INT_ST (BIT(27)) -#define MCPWM_CAP0_INT_ST_M (BIT(27)) -#define MCPWM_CAP0_INT_ST_V 0x1 -#define MCPWM_CAP0_INT_ST_S 27 -/* MCPWM_TZ2_OST_INT_ST : RO ;bitpos:[26] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_TZ2_OST_INT_ST (BIT(26)) -#define MCPWM_TZ2_OST_INT_ST_M (BIT(26)) -#define MCPWM_TZ2_OST_INT_ST_V 0x1 -#define MCPWM_TZ2_OST_INT_ST_S 26 -/* MCPWM_TZ1_OST_INT_ST : RO ;bitpos:[25] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_TZ1_OST_INT_ST (BIT(25)) -#define MCPWM_TZ1_OST_INT_ST_M (BIT(25)) -#define MCPWM_TZ1_OST_INT_ST_V 0x1 -#define MCPWM_TZ1_OST_INT_ST_S 25 -/* MCPWM_TZ0_OST_INT_ST : RO ;bitpos:[24] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_TZ0_OST_INT_ST (BIT(24)) -#define MCPWM_TZ0_OST_INT_ST_M (BIT(24)) -#define MCPWM_TZ0_OST_INT_ST_V 0x1 -#define MCPWM_TZ0_OST_INT_ST_S 24 -/* MCPWM_TZ2_CBC_INT_ST : RO ;bitpos:[23] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_TZ2_CBC_INT_ST (BIT(23)) -#define MCPWM_TZ2_CBC_INT_ST_M (BIT(23)) -#define MCPWM_TZ2_CBC_INT_ST_V 0x1 -#define MCPWM_TZ2_CBC_INT_ST_S 23 -/* MCPWM_TZ1_CBC_INT_ST : RO ;bitpos:[22] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_TZ1_CBC_INT_ST (BIT(22)) -#define MCPWM_TZ1_CBC_INT_ST_M (BIT(22)) -#define MCPWM_TZ1_CBC_INT_ST_V 0x1 -#define MCPWM_TZ1_CBC_INT_ST_S 22 -/* MCPWM_TZ0_CBC_INT_ST : RO ;bitpos:[21] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_TZ0_CBC_INT_ST (BIT(21)) -#define MCPWM_TZ0_CBC_INT_ST_M (BIT(21)) -#define MCPWM_TZ0_CBC_INT_ST_V 0x1 -#define MCPWM_TZ0_CBC_INT_ST_S 21 -/* MCPWM_CMPR2_TEB_INT_ST : RO ;bitpos:[20] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_CMPR2_TEB_INT_ST (BIT(20)) -#define MCPWM_CMPR2_TEB_INT_ST_M (BIT(20)) -#define MCPWM_CMPR2_TEB_INT_ST_V 0x1 -#define MCPWM_CMPR2_TEB_INT_ST_S 20 -/* MCPWM_CMPR1_TEB_INT_ST : RO ;bitpos:[19] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_CMPR1_TEB_INT_ST (BIT(19)) -#define MCPWM_CMPR1_TEB_INT_ST_M (BIT(19)) -#define MCPWM_CMPR1_TEB_INT_ST_V 0x1 -#define MCPWM_CMPR1_TEB_INT_ST_S 19 -/* MCPWM_CMPR0_TEB_INT_ST : RO ;bitpos:[18] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_CMPR0_TEB_INT_ST (BIT(18)) -#define MCPWM_CMPR0_TEB_INT_ST_M (BIT(18)) -#define MCPWM_CMPR0_TEB_INT_ST_V 0x1 -#define MCPWM_CMPR0_TEB_INT_ST_S 18 -/* MCPWM_CMPR2_TEA_INT_ST : RO ;bitpos:[17] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_CMPR2_TEA_INT_ST (BIT(17)) -#define MCPWM_CMPR2_TEA_INT_ST_M (BIT(17)) -#define MCPWM_CMPR2_TEA_INT_ST_V 0x1 -#define MCPWM_CMPR2_TEA_INT_ST_S 17 -/* MCPWM_CMPR1_TEA_INT_ST : RO ;bitpos:[16] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_CMPR1_TEA_INT_ST (BIT(16)) -#define MCPWM_CMPR1_TEA_INT_ST_M (BIT(16)) -#define MCPWM_CMPR1_TEA_INT_ST_V 0x1 -#define MCPWM_CMPR1_TEA_INT_ST_S 16 -/* MCPWM_CMPR0_TEA_INT_ST : RO ;bitpos:[15] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_CMPR0_TEA_INT_ST (BIT(15)) -#define MCPWM_CMPR0_TEA_INT_ST_M (BIT(15)) -#define MCPWM_CMPR0_TEA_INT_ST_V 0x1 -#define MCPWM_CMPR0_TEA_INT_ST_S 15 -/* MCPWM_FAULT2_CLR_INT_ST : RO ;bitpos:[14] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_FAULT2_CLR_INT_ST (BIT(14)) -#define MCPWM_FAULT2_CLR_INT_ST_M (BIT(14)) -#define MCPWM_FAULT2_CLR_INT_ST_V 0x1 -#define MCPWM_FAULT2_CLR_INT_ST_S 14 -/* MCPWM_FAULT1_CLR_INT_ST : RO ;bitpos:[13] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_FAULT1_CLR_INT_ST (BIT(13)) -#define MCPWM_FAULT1_CLR_INT_ST_M (BIT(13)) -#define MCPWM_FAULT1_CLR_INT_ST_V 0x1 -#define MCPWM_FAULT1_CLR_INT_ST_S 13 -/* MCPWM_FAULT0_CLR_INT_ST : RO ;bitpos:[12] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_FAULT0_CLR_INT_ST (BIT(12)) -#define MCPWM_FAULT0_CLR_INT_ST_M (BIT(12)) -#define MCPWM_FAULT0_CLR_INT_ST_V 0x1 -#define MCPWM_FAULT0_CLR_INT_ST_S 12 -/* MCPWM_FAULT2_INT_ST : RO ;bitpos:[11] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_FAULT2_INT_ST (BIT(11)) -#define MCPWM_FAULT2_INT_ST_M (BIT(11)) -#define MCPWM_FAULT2_INT_ST_V 0x1 -#define MCPWM_FAULT2_INT_ST_S 11 -/* MCPWM_FAULT1_INT_ST : RO ;bitpos:[10] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_FAULT1_INT_ST (BIT(10)) -#define MCPWM_FAULT1_INT_ST_M (BIT(10)) -#define MCPWM_FAULT1_INT_ST_V 0x1 -#define MCPWM_FAULT1_INT_ST_S 10 -/* MCPWM_FAULT0_INT_ST : RO ;bitpos:[9] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_FAULT0_INT_ST (BIT(9)) -#define MCPWM_FAULT0_INT_ST_M (BIT(9)) -#define MCPWM_FAULT0_INT_ST_V 0x1 -#define MCPWM_FAULT0_INT_ST_S 9 -/* MCPWM_TIMER2_TEP_INT_ST : RO ;bitpos:[8] ;default: 1'h0 ; */ -/*description: .*/ -#define MCPWM_TIMER2_TEP_INT_ST (BIT(8)) -#define MCPWM_TIMER2_TEP_INT_ST_M (BIT(8)) -#define MCPWM_TIMER2_TEP_INT_ST_V 0x1 -#define MCPWM_TIMER2_TEP_INT_ST_S 8 -/* MCPWM_TIMER1_TEP_INT_ST : RO ;bitpos:[7] ;default: 1'h0 ; */ -/*description: .*/ -#define MCPWM_TIMER1_TEP_INT_ST (BIT(7)) -#define MCPWM_TIMER1_TEP_INT_ST_M (BIT(7)) -#define MCPWM_TIMER1_TEP_INT_ST_V 0x1 -#define MCPWM_TIMER1_TEP_INT_ST_S 7 -/* MCPWM_TIMER0_TEP_INT_ST : RO ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define MCPWM_TIMER0_TEP_INT_ST (BIT(6)) -#define MCPWM_TIMER0_TEP_INT_ST_M (BIT(6)) -#define MCPWM_TIMER0_TEP_INT_ST_V 0x1 -#define MCPWM_TIMER0_TEP_INT_ST_S 6 -/* MCPWM_TIMER2_TEZ_INT_ST : RO ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define MCPWM_TIMER2_TEZ_INT_ST (BIT(5)) -#define MCPWM_TIMER2_TEZ_INT_ST_M (BIT(5)) -#define MCPWM_TIMER2_TEZ_INT_ST_V 0x1 -#define MCPWM_TIMER2_TEZ_INT_ST_S 5 -/* MCPWM_TIMER1_TEZ_INT_ST : RO ;bitpos:[4] ;default: 1'h0 ; */ -/*description: .*/ -#define MCPWM_TIMER1_TEZ_INT_ST (BIT(4)) -#define MCPWM_TIMER1_TEZ_INT_ST_M (BIT(4)) -#define MCPWM_TIMER1_TEZ_INT_ST_V 0x1 -#define MCPWM_TIMER1_TEZ_INT_ST_S 4 -/* MCPWM_TIMER0_TEZ_INT_ST : RO ;bitpos:[3] ;default: 1'h0 ; */ -/*description: .*/ -#define MCPWM_TIMER0_TEZ_INT_ST (BIT(3)) -#define MCPWM_TIMER0_TEZ_INT_ST_M (BIT(3)) -#define MCPWM_TIMER0_TEZ_INT_ST_V 0x1 -#define MCPWM_TIMER0_TEZ_INT_ST_S 3 -/* MCPWM_TIMER2_STOP_INT_ST : RO ;bitpos:[2] ;default: 1'h0 ; */ -/*description: .*/ -#define MCPWM_TIMER2_STOP_INT_ST (BIT(2)) -#define MCPWM_TIMER2_STOP_INT_ST_M (BIT(2)) -#define MCPWM_TIMER2_STOP_INT_ST_V 0x1 -#define MCPWM_TIMER2_STOP_INT_ST_S 2 -/* MCPWM_TIMER1_STOP_INT_ST : RO ;bitpos:[1] ;default: 1'h0 ; */ -/*description: .*/ -#define MCPWM_TIMER1_STOP_INT_ST (BIT(1)) -#define MCPWM_TIMER1_STOP_INT_ST_M (BIT(1)) -#define MCPWM_TIMER1_STOP_INT_ST_V 0x1 -#define MCPWM_TIMER1_STOP_INT_ST_S 1 -/* MCPWM_TIMER0_STOP_INT_ST : RO ;bitpos:[0] ;default: 1'h0 ; */ -/*description: .*/ +/** MCPWM_INT_ST_REG register + * Masked interrupt status + */ +#define MCPWM_INT_ST_REG(i) (DR_REG_MCPWM_BASE(i) + 0x118) +/** MCPWM_TIMER0_STOP_INT_ST : RO; bitpos: [0]; default: 0; + * The masked status bit for the interrupt triggered when the timer 0 stops. + */ #define MCPWM_TIMER0_STOP_INT_ST (BIT(0)) -#define MCPWM_TIMER0_STOP_INT_ST_M (BIT(0)) -#define MCPWM_TIMER0_STOP_INT_ST_V 0x1 +#define MCPWM_TIMER0_STOP_INT_ST_M (MCPWM_TIMER0_STOP_INT_ST_V << MCPWM_TIMER0_STOP_INT_ST_S) +#define MCPWM_TIMER0_STOP_INT_ST_V 0x00000001U #define MCPWM_TIMER0_STOP_INT_ST_S 0 +/** MCPWM_TIMER1_STOP_INT_ST : RO; bitpos: [1]; default: 0; + * The masked status bit for the interrupt triggered when the timer 1 stops. + */ +#define MCPWM_TIMER1_STOP_INT_ST (BIT(1)) +#define MCPWM_TIMER1_STOP_INT_ST_M (MCPWM_TIMER1_STOP_INT_ST_V << MCPWM_TIMER1_STOP_INT_ST_S) +#define MCPWM_TIMER1_STOP_INT_ST_V 0x00000001U +#define MCPWM_TIMER1_STOP_INT_ST_S 1 +/** MCPWM_TIMER2_STOP_INT_ST : RO; bitpos: [2]; default: 0; + * The masked status bit for the interrupt triggered when the timer 2 stops. + */ +#define MCPWM_TIMER2_STOP_INT_ST (BIT(2)) +#define MCPWM_TIMER2_STOP_INT_ST_M (MCPWM_TIMER2_STOP_INT_ST_V << MCPWM_TIMER2_STOP_INT_ST_S) +#define MCPWM_TIMER2_STOP_INT_ST_V 0x00000001U +#define MCPWM_TIMER2_STOP_INT_ST_S 2 +/** MCPWM_TIMER0_TEZ_INT_ST : RO; bitpos: [3]; default: 0; + * The masked status bit for the interrupt triggered by a PWM timer 0 TEZ event. + */ +#define MCPWM_TIMER0_TEZ_INT_ST (BIT(3)) +#define MCPWM_TIMER0_TEZ_INT_ST_M (MCPWM_TIMER0_TEZ_INT_ST_V << MCPWM_TIMER0_TEZ_INT_ST_S) +#define MCPWM_TIMER0_TEZ_INT_ST_V 0x00000001U +#define MCPWM_TIMER0_TEZ_INT_ST_S 3 +/** MCPWM_TIMER1_TEZ_INT_ST : RO; bitpos: [4]; default: 0; + * The masked status bit for the interrupt triggered by a PWM timer 1 TEZ event. + */ +#define MCPWM_TIMER1_TEZ_INT_ST (BIT(4)) +#define MCPWM_TIMER1_TEZ_INT_ST_M (MCPWM_TIMER1_TEZ_INT_ST_V << MCPWM_TIMER1_TEZ_INT_ST_S) +#define MCPWM_TIMER1_TEZ_INT_ST_V 0x00000001U +#define MCPWM_TIMER1_TEZ_INT_ST_S 4 +/** MCPWM_TIMER2_TEZ_INT_ST : RO; bitpos: [5]; default: 0; + * The masked status bit for the interrupt triggered by a PWM timer 2 TEZ event. + */ +#define MCPWM_TIMER2_TEZ_INT_ST (BIT(5)) +#define MCPWM_TIMER2_TEZ_INT_ST_M (MCPWM_TIMER2_TEZ_INT_ST_V << MCPWM_TIMER2_TEZ_INT_ST_S) +#define MCPWM_TIMER2_TEZ_INT_ST_V 0x00000001U +#define MCPWM_TIMER2_TEZ_INT_ST_S 5 +/** MCPWM_TIMER0_TEP_INT_ST : RO; bitpos: [6]; default: 0; + * The masked status bit for the interrupt triggered by a PWM timer 0 TEP event. + */ +#define MCPWM_TIMER0_TEP_INT_ST (BIT(6)) +#define MCPWM_TIMER0_TEP_INT_ST_M (MCPWM_TIMER0_TEP_INT_ST_V << MCPWM_TIMER0_TEP_INT_ST_S) +#define MCPWM_TIMER0_TEP_INT_ST_V 0x00000001U +#define MCPWM_TIMER0_TEP_INT_ST_S 6 +/** MCPWM_TIMER1_TEP_INT_ST : RO; bitpos: [7]; default: 0; + * The masked status bit for the interrupt triggered by a PWM timer 1 TEP event. + */ +#define MCPWM_TIMER1_TEP_INT_ST (BIT(7)) +#define MCPWM_TIMER1_TEP_INT_ST_M (MCPWM_TIMER1_TEP_INT_ST_V << MCPWM_TIMER1_TEP_INT_ST_S) +#define MCPWM_TIMER1_TEP_INT_ST_V 0x00000001U +#define MCPWM_TIMER1_TEP_INT_ST_S 7 +/** MCPWM_TIMER2_TEP_INT_ST : RO; bitpos: [8]; default: 0; + * The masked status bit for the interrupt triggered by a PWM timer 2 TEP event. + */ +#define MCPWM_TIMER2_TEP_INT_ST (BIT(8)) +#define MCPWM_TIMER2_TEP_INT_ST_M (MCPWM_TIMER2_TEP_INT_ST_V << MCPWM_TIMER2_TEP_INT_ST_S) +#define MCPWM_TIMER2_TEP_INT_ST_V 0x00000001U +#define MCPWM_TIMER2_TEP_INT_ST_S 8 +/** MCPWM_FAULT0_INT_ST : RO; bitpos: [9]; default: 0; + * The masked status bit for the interrupt triggered when fault_event0 starts. + */ +#define MCPWM_FAULT0_INT_ST (BIT(9)) +#define MCPWM_FAULT0_INT_ST_M (MCPWM_FAULT0_INT_ST_V << MCPWM_FAULT0_INT_ST_S) +#define MCPWM_FAULT0_INT_ST_V 0x00000001U +#define MCPWM_FAULT0_INT_ST_S 9 +/** MCPWM_FAULT1_INT_ST : RO; bitpos: [10]; default: 0; + * The masked status bit for the interrupt triggered when fault_event1 starts. + */ +#define MCPWM_FAULT1_INT_ST (BIT(10)) +#define MCPWM_FAULT1_INT_ST_M (MCPWM_FAULT1_INT_ST_V << MCPWM_FAULT1_INT_ST_S) +#define MCPWM_FAULT1_INT_ST_V 0x00000001U +#define MCPWM_FAULT1_INT_ST_S 10 +/** MCPWM_FAULT2_INT_ST : RO; bitpos: [11]; default: 0; + * The masked status bit for the interrupt triggered when fault_event2 starts. + */ +#define MCPWM_FAULT2_INT_ST (BIT(11)) +#define MCPWM_FAULT2_INT_ST_M (MCPWM_FAULT2_INT_ST_V << MCPWM_FAULT2_INT_ST_S) +#define MCPWM_FAULT2_INT_ST_V 0x00000001U +#define MCPWM_FAULT2_INT_ST_S 11 +/** MCPWM_FAULT0_CLR_INT_ST : RO; bitpos: [12]; default: 0; + * The masked status bit for the interrupt triggered when fault_event0 ends. + */ +#define MCPWM_FAULT0_CLR_INT_ST (BIT(12)) +#define MCPWM_FAULT0_CLR_INT_ST_M (MCPWM_FAULT0_CLR_INT_ST_V << MCPWM_FAULT0_CLR_INT_ST_S) +#define MCPWM_FAULT0_CLR_INT_ST_V 0x00000001U +#define MCPWM_FAULT0_CLR_INT_ST_S 12 +/** MCPWM_FAULT1_CLR_INT_ST : RO; bitpos: [13]; default: 0; + * The masked status bit for the interrupt triggered when fault_event1 ends. + */ +#define MCPWM_FAULT1_CLR_INT_ST (BIT(13)) +#define MCPWM_FAULT1_CLR_INT_ST_M (MCPWM_FAULT1_CLR_INT_ST_V << MCPWM_FAULT1_CLR_INT_ST_S) +#define MCPWM_FAULT1_CLR_INT_ST_V 0x00000001U +#define MCPWM_FAULT1_CLR_INT_ST_S 13 +/** MCPWM_FAULT2_CLR_INT_ST : RO; bitpos: [14]; default: 0; + * The masked status bit for the interrupt triggered when fault_event2 ends. + */ +#define MCPWM_FAULT2_CLR_INT_ST (BIT(14)) +#define MCPWM_FAULT2_CLR_INT_ST_M (MCPWM_FAULT2_CLR_INT_ST_V << MCPWM_FAULT2_CLR_INT_ST_S) +#define MCPWM_FAULT2_CLR_INT_ST_V 0x00000001U +#define MCPWM_FAULT2_CLR_INT_ST_S 14 +/** MCPWM_OP0_TEA_INT_ST : RO; bitpos: [15]; default: 0; + * The masked status bit for the interrupt triggered by a PWM operator 0 TEA event + */ +#define MCPWM_OP0_TEA_INT_ST (BIT(15)) +#define MCPWM_OP0_TEA_INT_ST_M (MCPWM_OP0_TEA_INT_ST_V << MCPWM_OP0_TEA_INT_ST_S) +#define MCPWM_OP0_TEA_INT_ST_V 0x00000001U +#define MCPWM_OP0_TEA_INT_ST_S 15 +/** MCPWM_OP1_TEA_INT_ST : RO; bitpos: [16]; default: 0; + * The masked status bit for the interrupt triggered by a PWM operator 1 TEA event + */ +#define MCPWM_OP1_TEA_INT_ST (BIT(16)) +#define MCPWM_OP1_TEA_INT_ST_M (MCPWM_OP1_TEA_INT_ST_V << MCPWM_OP1_TEA_INT_ST_S) +#define MCPWM_OP1_TEA_INT_ST_V 0x00000001U +#define MCPWM_OP1_TEA_INT_ST_S 16 +/** MCPWM_OP2_TEA_INT_ST : RO; bitpos: [17]; default: 0; + * The masked status bit for the interrupt triggered by a PWM operator 2 TEA event + */ +#define MCPWM_OP2_TEA_INT_ST (BIT(17)) +#define MCPWM_OP2_TEA_INT_ST_M (MCPWM_OP2_TEA_INT_ST_V << MCPWM_OP2_TEA_INT_ST_S) +#define MCPWM_OP2_TEA_INT_ST_V 0x00000001U +#define MCPWM_OP2_TEA_INT_ST_S 17 +/** MCPWM_OP0_TEB_INT_ST : RO; bitpos: [18]; default: 0; + * The masked status bit for the interrupt triggered by a PWM operator 0 TEB event + */ +#define MCPWM_OP0_TEB_INT_ST (BIT(18)) +#define MCPWM_OP0_TEB_INT_ST_M (MCPWM_OP0_TEB_INT_ST_V << MCPWM_OP0_TEB_INT_ST_S) +#define MCPWM_OP0_TEB_INT_ST_V 0x00000001U +#define MCPWM_OP0_TEB_INT_ST_S 18 +/** MCPWM_OP1_TEB_INT_ST : RO; bitpos: [19]; default: 0; + * The masked status bit for the interrupt triggered by a PWM operator 1 TEB event + */ +#define MCPWM_OP1_TEB_INT_ST (BIT(19)) +#define MCPWM_OP1_TEB_INT_ST_M (MCPWM_OP1_TEB_INT_ST_V << MCPWM_OP1_TEB_INT_ST_S) +#define MCPWM_OP1_TEB_INT_ST_V 0x00000001U +#define MCPWM_OP1_TEB_INT_ST_S 19 +/** MCPWM_OP2_TEB_INT_ST : RO; bitpos: [20]; default: 0; + * The masked status bit for the interrupt triggered by a PWM operator 2 TEB event + */ +#define MCPWM_OP2_TEB_INT_ST (BIT(20)) +#define MCPWM_OP2_TEB_INT_ST_M (MCPWM_OP2_TEB_INT_ST_V << MCPWM_OP2_TEB_INT_ST_S) +#define MCPWM_OP2_TEB_INT_ST_V 0x00000001U +#define MCPWM_OP2_TEB_INT_ST_S 20 +/** MCPWM_FH0_CBC_INT_ST : RO; bitpos: [21]; default: 0; + * The masked status bit for the interrupt triggered by a cycle-by-cycle mode action + * on PWM0. + */ +#define MCPWM_FH0_CBC_INT_ST (BIT(21)) +#define MCPWM_FH0_CBC_INT_ST_M (MCPWM_FH0_CBC_INT_ST_V << MCPWM_FH0_CBC_INT_ST_S) +#define MCPWM_FH0_CBC_INT_ST_V 0x00000001U +#define MCPWM_FH0_CBC_INT_ST_S 21 +/** MCPWM_FH1_CBC_INT_ST : RO; bitpos: [22]; default: 0; + * The masked status bit for the interrupt triggered by a cycle-by-cycle mode action + * on PWM1. + */ +#define MCPWM_FH1_CBC_INT_ST (BIT(22)) +#define MCPWM_FH1_CBC_INT_ST_M (MCPWM_FH1_CBC_INT_ST_V << MCPWM_FH1_CBC_INT_ST_S) +#define MCPWM_FH1_CBC_INT_ST_V 0x00000001U +#define MCPWM_FH1_CBC_INT_ST_S 22 +/** MCPWM_FH2_CBC_INT_ST : RO; bitpos: [23]; default: 0; + * The masked status bit for the interrupt triggered by a cycle-by-cycle mode action + * on PWM2. + */ +#define MCPWM_FH2_CBC_INT_ST (BIT(23)) +#define MCPWM_FH2_CBC_INT_ST_M (MCPWM_FH2_CBC_INT_ST_V << MCPWM_FH2_CBC_INT_ST_S) +#define MCPWM_FH2_CBC_INT_ST_V 0x00000001U +#define MCPWM_FH2_CBC_INT_ST_S 23 +/** MCPWM_FH0_OST_INT_ST : RO; bitpos: [24]; default: 0; + * The masked status bit for the interrupt triggered by a one-shot mode action on PWM0. + */ +#define MCPWM_FH0_OST_INT_ST (BIT(24)) +#define MCPWM_FH0_OST_INT_ST_M (MCPWM_FH0_OST_INT_ST_V << MCPWM_FH0_OST_INT_ST_S) +#define MCPWM_FH0_OST_INT_ST_V 0x00000001U +#define MCPWM_FH0_OST_INT_ST_S 24 +/** MCPWM_FH1_OST_INT_ST : RO; bitpos: [25]; default: 0; + * The masked status bit for the interrupt triggered by a one-shot mode action on PWM1. + */ +#define MCPWM_FH1_OST_INT_ST (BIT(25)) +#define MCPWM_FH1_OST_INT_ST_M (MCPWM_FH1_OST_INT_ST_V << MCPWM_FH1_OST_INT_ST_S) +#define MCPWM_FH1_OST_INT_ST_V 0x00000001U +#define MCPWM_FH1_OST_INT_ST_S 25 +/** MCPWM_FH2_OST_INT_ST : RO; bitpos: [26]; default: 0; + * The masked status bit for the interrupt triggered by a one-shot mode action on PWM2. + */ +#define MCPWM_FH2_OST_INT_ST (BIT(26)) +#define MCPWM_FH2_OST_INT_ST_M (MCPWM_FH2_OST_INT_ST_V << MCPWM_FH2_OST_INT_ST_S) +#define MCPWM_FH2_OST_INT_ST_V 0x00000001U +#define MCPWM_FH2_OST_INT_ST_S 26 +/** MCPWM_CAP0_INT_ST : RO; bitpos: [27]; default: 0; + * The masked status bit for the interrupt triggered by capture on channel 0. + */ +#define MCPWM_CAP0_INT_ST (BIT(27)) +#define MCPWM_CAP0_INT_ST_M (MCPWM_CAP0_INT_ST_V << MCPWM_CAP0_INT_ST_S) +#define MCPWM_CAP0_INT_ST_V 0x00000001U +#define MCPWM_CAP0_INT_ST_S 27 +/** MCPWM_CAP1_INT_ST : RO; bitpos: [28]; default: 0; + * The masked status bit for the interrupt triggered by capture on channel 1. + */ +#define MCPWM_CAP1_INT_ST (BIT(28)) +#define MCPWM_CAP1_INT_ST_M (MCPWM_CAP1_INT_ST_V << MCPWM_CAP1_INT_ST_S) +#define MCPWM_CAP1_INT_ST_V 0x00000001U +#define MCPWM_CAP1_INT_ST_S 28 +/** MCPWM_CAP2_INT_ST : RO; bitpos: [29]; default: 0; + * The masked status bit for the interrupt triggered by capture on channel 2. + */ +#define MCPWM_CAP2_INT_ST (BIT(29)) +#define MCPWM_CAP2_INT_ST_M (MCPWM_CAP2_INT_ST_V << MCPWM_CAP2_INT_ST_S) +#define MCPWM_CAP2_INT_ST_V 0x00000001U +#define MCPWM_CAP2_INT_ST_S 29 -#define MCPWM_INT_CLR_PWM_REG(i) (REG_MCPWM_BASE(i) + 0x11C) -/* MCPWM_CAP2_INT_CLR : WO ;bitpos:[29] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_CAP2_INT_CLR (BIT(29)) -#define MCPWM_CAP2_INT_CLR_M (BIT(29)) -#define MCPWM_CAP2_INT_CLR_V 0x1 -#define MCPWM_CAP2_INT_CLR_S 29 -/* MCPWM_CAP1_INT_CLR : WO ;bitpos:[28] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_CAP1_INT_CLR (BIT(28)) -#define MCPWM_CAP1_INT_CLR_M (BIT(28)) -#define MCPWM_CAP1_INT_CLR_V 0x1 -#define MCPWM_CAP1_INT_CLR_S 28 -/* MCPWM_CAP0_INT_CLR : WO ;bitpos:[27] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_CAP0_INT_CLR (BIT(27)) -#define MCPWM_CAP0_INT_CLR_M (BIT(27)) -#define MCPWM_CAP0_INT_CLR_V 0x1 -#define MCPWM_CAP0_INT_CLR_S 27 -/* MCPWM_TZ2_OST_INT_CLR : WO ;bitpos:[26] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_TZ2_OST_INT_CLR (BIT(26)) -#define MCPWM_TZ2_OST_INT_CLR_M (BIT(26)) -#define MCPWM_TZ2_OST_INT_CLR_V 0x1 -#define MCPWM_TZ2_OST_INT_CLR_S 26 -/* MCPWM_TZ1_OST_INT_CLR : WO ;bitpos:[25] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_TZ1_OST_INT_CLR (BIT(25)) -#define MCPWM_TZ1_OST_INT_CLR_M (BIT(25)) -#define MCPWM_TZ1_OST_INT_CLR_V 0x1 -#define MCPWM_TZ1_OST_INT_CLR_S 25 -/* MCPWM_TZ0_OST_INT_CLR : WO ;bitpos:[24] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_TZ0_OST_INT_CLR (BIT(24)) -#define MCPWM_TZ0_OST_INT_CLR_M (BIT(24)) -#define MCPWM_TZ0_OST_INT_CLR_V 0x1 -#define MCPWM_TZ0_OST_INT_CLR_S 24 -/* MCPWM_TZ2_CBC_INT_CLR : WO ;bitpos:[23] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_TZ2_CBC_INT_CLR (BIT(23)) -#define MCPWM_TZ2_CBC_INT_CLR_M (BIT(23)) -#define MCPWM_TZ2_CBC_INT_CLR_V 0x1 -#define MCPWM_TZ2_CBC_INT_CLR_S 23 -/* MCPWM_TZ1_CBC_INT_CLR : WO ;bitpos:[22] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_TZ1_CBC_INT_CLR (BIT(22)) -#define MCPWM_TZ1_CBC_INT_CLR_M (BIT(22)) -#define MCPWM_TZ1_CBC_INT_CLR_V 0x1 -#define MCPWM_TZ1_CBC_INT_CLR_S 22 -/* MCPWM_TZ0_CBC_INT_CLR : WO ;bitpos:[21] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_TZ0_CBC_INT_CLR (BIT(21)) -#define MCPWM_TZ0_CBC_INT_CLR_M (BIT(21)) -#define MCPWM_TZ0_CBC_INT_CLR_V 0x1 -#define MCPWM_TZ0_CBC_INT_CLR_S 21 -/* MCPWM_CMPR2_TEB_INT_CLR : WO ;bitpos:[20] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_CMPR2_TEB_INT_CLR (BIT(20)) -#define MCPWM_CMPR2_TEB_INT_CLR_M (BIT(20)) -#define MCPWM_CMPR2_TEB_INT_CLR_V 0x1 -#define MCPWM_CMPR2_TEB_INT_CLR_S 20 -/* MCPWM_CMPR1_TEB_INT_CLR : WO ;bitpos:[19] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_CMPR1_TEB_INT_CLR (BIT(19)) -#define MCPWM_CMPR1_TEB_INT_CLR_M (BIT(19)) -#define MCPWM_CMPR1_TEB_INT_CLR_V 0x1 -#define MCPWM_CMPR1_TEB_INT_CLR_S 19 -/* MCPWM_CMPR0_TEB_INT_CLR : WO ;bitpos:[18] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_CMPR0_TEB_INT_CLR (BIT(18)) -#define MCPWM_CMPR0_TEB_INT_CLR_M (BIT(18)) -#define MCPWM_CMPR0_TEB_INT_CLR_V 0x1 -#define MCPWM_CMPR0_TEB_INT_CLR_S 18 -/* MCPWM_CMPR2_TEA_INT_CLR : WO ;bitpos:[17] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_CMPR2_TEA_INT_CLR (BIT(17)) -#define MCPWM_CMPR2_TEA_INT_CLR_M (BIT(17)) -#define MCPWM_CMPR2_TEA_INT_CLR_V 0x1 -#define MCPWM_CMPR2_TEA_INT_CLR_S 17 -/* MCPWM_CMPR1_TEA_INT_CLR : WO ;bitpos:[16] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_CMPR1_TEA_INT_CLR (BIT(16)) -#define MCPWM_CMPR1_TEA_INT_CLR_M (BIT(16)) -#define MCPWM_CMPR1_TEA_INT_CLR_V 0x1 -#define MCPWM_CMPR1_TEA_INT_CLR_S 16 -/* MCPWM_CMPR0_TEA_INT_CLR : WO ;bitpos:[15] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_CMPR0_TEA_INT_CLR (BIT(15)) -#define MCPWM_CMPR0_TEA_INT_CLR_M (BIT(15)) -#define MCPWM_CMPR0_TEA_INT_CLR_V 0x1 -#define MCPWM_CMPR0_TEA_INT_CLR_S 15 -/* MCPWM_FAULT2_CLR_INT_CLR : WO ;bitpos:[14] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_FAULT2_CLR_INT_CLR (BIT(14)) -#define MCPWM_FAULT2_CLR_INT_CLR_M (BIT(14)) -#define MCPWM_FAULT2_CLR_INT_CLR_V 0x1 -#define MCPWM_FAULT2_CLR_INT_CLR_S 14 -/* MCPWM_FAULT1_CLR_INT_CLR : WO ;bitpos:[13] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_FAULT1_CLR_INT_CLR (BIT(13)) -#define MCPWM_FAULT1_CLR_INT_CLR_M (BIT(13)) -#define MCPWM_FAULT1_CLR_INT_CLR_V 0x1 -#define MCPWM_FAULT1_CLR_INT_CLR_S 13 -/* MCPWM_FAULT0_CLR_INT_CLR : WO ;bitpos:[12] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_FAULT0_CLR_INT_CLR (BIT(12)) -#define MCPWM_FAULT0_CLR_INT_CLR_M (BIT(12)) -#define MCPWM_FAULT0_CLR_INT_CLR_V 0x1 -#define MCPWM_FAULT0_CLR_INT_CLR_S 12 -/* MCPWM_FAULT2_INT_CLR : WO ;bitpos:[11] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_FAULT2_INT_CLR (BIT(11)) -#define MCPWM_FAULT2_INT_CLR_M (BIT(11)) -#define MCPWM_FAULT2_INT_CLR_V 0x1 -#define MCPWM_FAULT2_INT_CLR_S 11 -/* MCPWM_FAULT1_INT_CLR : WO ;bitpos:[10] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_FAULT1_INT_CLR (BIT(10)) -#define MCPWM_FAULT1_INT_CLR_M (BIT(10)) -#define MCPWM_FAULT1_INT_CLR_V 0x1 -#define MCPWM_FAULT1_INT_CLR_S 10 -/* MCPWM_FAULT0_INT_CLR : WO ;bitpos:[9] ;default: 1'd0 ; */ -/*description: .*/ -#define MCPWM_FAULT0_INT_CLR (BIT(9)) -#define MCPWM_FAULT0_INT_CLR_M (BIT(9)) -#define MCPWM_FAULT0_INT_CLR_V 0x1 -#define MCPWM_FAULT0_INT_CLR_S 9 -/* MCPWM_TIMER2_TEP_INT_CLR : WO ;bitpos:[8] ;default: 1'h0 ; */ -/*description: .*/ -#define MCPWM_TIMER2_TEP_INT_CLR (BIT(8)) -#define MCPWM_TIMER2_TEP_INT_CLR_M (BIT(8)) -#define MCPWM_TIMER2_TEP_INT_CLR_V 0x1 -#define MCPWM_TIMER2_TEP_INT_CLR_S 8 -/* MCPWM_TIMER1_TEP_INT_CLR : WO ;bitpos:[7] ;default: 1'h0 ; */ -/*description: .*/ -#define MCPWM_TIMER1_TEP_INT_CLR (BIT(7)) -#define MCPWM_TIMER1_TEP_INT_CLR_M (BIT(7)) -#define MCPWM_TIMER1_TEP_INT_CLR_V 0x1 -#define MCPWM_TIMER1_TEP_INT_CLR_S 7 -/* MCPWM_TIMER0_TEP_INT_CLR : WO ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define MCPWM_TIMER0_TEP_INT_CLR (BIT(6)) -#define MCPWM_TIMER0_TEP_INT_CLR_M (BIT(6)) -#define MCPWM_TIMER0_TEP_INT_CLR_V 0x1 -#define MCPWM_TIMER0_TEP_INT_CLR_S 6 -/* MCPWM_TIMER2_TEZ_INT_CLR : WO ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define MCPWM_TIMER2_TEZ_INT_CLR (BIT(5)) -#define MCPWM_TIMER2_TEZ_INT_CLR_M (BIT(5)) -#define MCPWM_TIMER2_TEZ_INT_CLR_V 0x1 -#define MCPWM_TIMER2_TEZ_INT_CLR_S 5 -/* MCPWM_TIMER1_TEZ_INT_CLR : WO ;bitpos:[4] ;default: 1'h0 ; */ -/*description: .*/ -#define MCPWM_TIMER1_TEZ_INT_CLR (BIT(4)) -#define MCPWM_TIMER1_TEZ_INT_CLR_M (BIT(4)) -#define MCPWM_TIMER1_TEZ_INT_CLR_V 0x1 -#define MCPWM_TIMER1_TEZ_INT_CLR_S 4 -/* MCPWM_TIMER0_TEZ_INT_CLR : WO ;bitpos:[3] ;default: 1'h0 ; */ -/*description: .*/ -#define MCPWM_TIMER0_TEZ_INT_CLR (BIT(3)) -#define MCPWM_TIMER0_TEZ_INT_CLR_M (BIT(3)) -#define MCPWM_TIMER0_TEZ_INT_CLR_V 0x1 -#define MCPWM_TIMER0_TEZ_INT_CLR_S 3 -/* MCPWM_TIMER2_STOP_INT_CLR : WO ;bitpos:[2] ;default: 1'h0 ; */ -/*description: .*/ -#define MCPWM_TIMER2_STOP_INT_CLR (BIT(2)) -#define MCPWM_TIMER2_STOP_INT_CLR_M (BIT(2)) -#define MCPWM_TIMER2_STOP_INT_CLR_V 0x1 -#define MCPWM_TIMER2_STOP_INT_CLR_S 2 -/* MCPWM_TIMER1_STOP_INT_CLR : WO ;bitpos:[1] ;default: 1'h0 ; */ -/*description: .*/ -#define MCPWM_TIMER1_STOP_INT_CLR (BIT(1)) -#define MCPWM_TIMER1_STOP_INT_CLR_M (BIT(1)) -#define MCPWM_TIMER1_STOP_INT_CLR_V 0x1 -#define MCPWM_TIMER1_STOP_INT_CLR_S 1 -/* MCPWM_TIMER0_STOP_INT_CLR : WO ;bitpos:[0] ;default: 1'h0 ; */ -/*description: .*/ +/** MCPWM_INT_CLR_REG register + * Interrupt clear bits + */ +#define MCPWM_INT_CLR_REG(i) (DR_REG_MCPWM_BASE(i) + 0x11c) +/** MCPWM_TIMER0_STOP_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the interrupt triggered when the timer 0 stops. + */ #define MCPWM_TIMER0_STOP_INT_CLR (BIT(0)) -#define MCPWM_TIMER0_STOP_INT_CLR_M (BIT(0)) -#define MCPWM_TIMER0_STOP_INT_CLR_V 0x1 +#define MCPWM_TIMER0_STOP_INT_CLR_M (MCPWM_TIMER0_STOP_INT_CLR_V << MCPWM_TIMER0_STOP_INT_CLR_S) +#define MCPWM_TIMER0_STOP_INT_CLR_V 0x00000001U #define MCPWM_TIMER0_STOP_INT_CLR_S 0 +/** MCPWM_TIMER1_STOP_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the interrupt triggered when the timer 1 stops. + */ +#define MCPWM_TIMER1_STOP_INT_CLR (BIT(1)) +#define MCPWM_TIMER1_STOP_INT_CLR_M (MCPWM_TIMER1_STOP_INT_CLR_V << MCPWM_TIMER1_STOP_INT_CLR_S) +#define MCPWM_TIMER1_STOP_INT_CLR_V 0x00000001U +#define MCPWM_TIMER1_STOP_INT_CLR_S 1 +/** MCPWM_TIMER2_STOP_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the interrupt triggered when the timer 2 stops. + */ +#define MCPWM_TIMER2_STOP_INT_CLR (BIT(2)) +#define MCPWM_TIMER2_STOP_INT_CLR_M (MCPWM_TIMER2_STOP_INT_CLR_V << MCPWM_TIMER2_STOP_INT_CLR_S) +#define MCPWM_TIMER2_STOP_INT_CLR_V 0x00000001U +#define MCPWM_TIMER2_STOP_INT_CLR_S 2 +/** MCPWM_TIMER0_TEZ_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM timer 0 TEZ event. + */ +#define MCPWM_TIMER0_TEZ_INT_CLR (BIT(3)) +#define MCPWM_TIMER0_TEZ_INT_CLR_M (MCPWM_TIMER0_TEZ_INT_CLR_V << MCPWM_TIMER0_TEZ_INT_CLR_S) +#define MCPWM_TIMER0_TEZ_INT_CLR_V 0x00000001U +#define MCPWM_TIMER0_TEZ_INT_CLR_S 3 +/** MCPWM_TIMER1_TEZ_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM timer 1 TEZ event. + */ +#define MCPWM_TIMER1_TEZ_INT_CLR (BIT(4)) +#define MCPWM_TIMER1_TEZ_INT_CLR_M (MCPWM_TIMER1_TEZ_INT_CLR_V << MCPWM_TIMER1_TEZ_INT_CLR_S) +#define MCPWM_TIMER1_TEZ_INT_CLR_V 0x00000001U +#define MCPWM_TIMER1_TEZ_INT_CLR_S 4 +/** MCPWM_TIMER2_TEZ_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM timer 2 TEZ event. + */ +#define MCPWM_TIMER2_TEZ_INT_CLR (BIT(5)) +#define MCPWM_TIMER2_TEZ_INT_CLR_M (MCPWM_TIMER2_TEZ_INT_CLR_V << MCPWM_TIMER2_TEZ_INT_CLR_S) +#define MCPWM_TIMER2_TEZ_INT_CLR_V 0x00000001U +#define MCPWM_TIMER2_TEZ_INT_CLR_S 5 +/** MCPWM_TIMER0_TEP_INT_CLR : WT; bitpos: [6]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM timer 0 TEP event. + */ +#define MCPWM_TIMER0_TEP_INT_CLR (BIT(6)) +#define MCPWM_TIMER0_TEP_INT_CLR_M (MCPWM_TIMER0_TEP_INT_CLR_V << MCPWM_TIMER0_TEP_INT_CLR_S) +#define MCPWM_TIMER0_TEP_INT_CLR_V 0x00000001U +#define MCPWM_TIMER0_TEP_INT_CLR_S 6 +/** MCPWM_TIMER1_TEP_INT_CLR : WT; bitpos: [7]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM timer 1 TEP event. + */ +#define MCPWM_TIMER1_TEP_INT_CLR (BIT(7)) +#define MCPWM_TIMER1_TEP_INT_CLR_M (MCPWM_TIMER1_TEP_INT_CLR_V << MCPWM_TIMER1_TEP_INT_CLR_S) +#define MCPWM_TIMER1_TEP_INT_CLR_V 0x00000001U +#define MCPWM_TIMER1_TEP_INT_CLR_S 7 +/** MCPWM_TIMER2_TEP_INT_CLR : WT; bitpos: [8]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM timer 2 TEP event. + */ +#define MCPWM_TIMER2_TEP_INT_CLR (BIT(8)) +#define MCPWM_TIMER2_TEP_INT_CLR_M (MCPWM_TIMER2_TEP_INT_CLR_V << MCPWM_TIMER2_TEP_INT_CLR_S) +#define MCPWM_TIMER2_TEP_INT_CLR_V 0x00000001U +#define MCPWM_TIMER2_TEP_INT_CLR_S 8 +/** MCPWM_FAULT0_INT_CLR : WT; bitpos: [9]; default: 0; + * Set this bit to clear the interrupt triggered when fault_event0 starts. + */ +#define MCPWM_FAULT0_INT_CLR (BIT(9)) +#define MCPWM_FAULT0_INT_CLR_M (MCPWM_FAULT0_INT_CLR_V << MCPWM_FAULT0_INT_CLR_S) +#define MCPWM_FAULT0_INT_CLR_V 0x00000001U +#define MCPWM_FAULT0_INT_CLR_S 9 +/** MCPWM_FAULT1_INT_CLR : WT; bitpos: [10]; default: 0; + * Set this bit to clear the interrupt triggered when fault_event1 starts. + */ +#define MCPWM_FAULT1_INT_CLR (BIT(10)) +#define MCPWM_FAULT1_INT_CLR_M (MCPWM_FAULT1_INT_CLR_V << MCPWM_FAULT1_INT_CLR_S) +#define MCPWM_FAULT1_INT_CLR_V 0x00000001U +#define MCPWM_FAULT1_INT_CLR_S 10 +/** MCPWM_FAULT2_INT_CLR : WT; bitpos: [11]; default: 0; + * Set this bit to clear the interrupt triggered when fault_event2 starts. + */ +#define MCPWM_FAULT2_INT_CLR (BIT(11)) +#define MCPWM_FAULT2_INT_CLR_M (MCPWM_FAULT2_INT_CLR_V << MCPWM_FAULT2_INT_CLR_S) +#define MCPWM_FAULT2_INT_CLR_V 0x00000001U +#define MCPWM_FAULT2_INT_CLR_S 11 +/** MCPWM_FAULT0_CLR_INT_CLR : WT; bitpos: [12]; default: 0; + * Set this bit to clear the interrupt triggered when fault_event0 ends. + */ +#define MCPWM_FAULT0_CLR_INT_CLR (BIT(12)) +#define MCPWM_FAULT0_CLR_INT_CLR_M (MCPWM_FAULT0_CLR_INT_CLR_V << MCPWM_FAULT0_CLR_INT_CLR_S) +#define MCPWM_FAULT0_CLR_INT_CLR_V 0x00000001U +#define MCPWM_FAULT0_CLR_INT_CLR_S 12 +/** MCPWM_FAULT1_CLR_INT_CLR : WT; bitpos: [13]; default: 0; + * Set this bit to clear the interrupt triggered when fault_event1 ends. + */ +#define MCPWM_FAULT1_CLR_INT_CLR (BIT(13)) +#define MCPWM_FAULT1_CLR_INT_CLR_M (MCPWM_FAULT1_CLR_INT_CLR_V << MCPWM_FAULT1_CLR_INT_CLR_S) +#define MCPWM_FAULT1_CLR_INT_CLR_V 0x00000001U +#define MCPWM_FAULT1_CLR_INT_CLR_S 13 +/** MCPWM_FAULT2_CLR_INT_CLR : WT; bitpos: [14]; default: 0; + * Set this bit to clear the interrupt triggered when fault_event2 ends. + */ +#define MCPWM_FAULT2_CLR_INT_CLR (BIT(14)) +#define MCPWM_FAULT2_CLR_INT_CLR_M (MCPWM_FAULT2_CLR_INT_CLR_V << MCPWM_FAULT2_CLR_INT_CLR_S) +#define MCPWM_FAULT2_CLR_INT_CLR_V 0x00000001U +#define MCPWM_FAULT2_CLR_INT_CLR_S 14 +/** MCPWM_OP0_TEA_INT_CLR : WT; bitpos: [15]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM operator 0 TEA event + */ +#define MCPWM_OP0_TEA_INT_CLR (BIT(15)) +#define MCPWM_OP0_TEA_INT_CLR_M (MCPWM_OP0_TEA_INT_CLR_V << MCPWM_OP0_TEA_INT_CLR_S) +#define MCPWM_OP0_TEA_INT_CLR_V 0x00000001U +#define MCPWM_OP0_TEA_INT_CLR_S 15 +/** MCPWM_OP1_TEA_INT_CLR : WT; bitpos: [16]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM operator 1 TEA event + */ +#define MCPWM_OP1_TEA_INT_CLR (BIT(16)) +#define MCPWM_OP1_TEA_INT_CLR_M (MCPWM_OP1_TEA_INT_CLR_V << MCPWM_OP1_TEA_INT_CLR_S) +#define MCPWM_OP1_TEA_INT_CLR_V 0x00000001U +#define MCPWM_OP1_TEA_INT_CLR_S 16 +/** MCPWM_OP2_TEA_INT_CLR : WT; bitpos: [17]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM operator 2 TEA event + */ +#define MCPWM_OP2_TEA_INT_CLR (BIT(17)) +#define MCPWM_OP2_TEA_INT_CLR_M (MCPWM_OP2_TEA_INT_CLR_V << MCPWM_OP2_TEA_INT_CLR_S) +#define MCPWM_OP2_TEA_INT_CLR_V 0x00000001U +#define MCPWM_OP2_TEA_INT_CLR_S 17 +/** MCPWM_OP0_TEB_INT_CLR : WT; bitpos: [18]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM operator 0 TEB event + */ +#define MCPWM_OP0_TEB_INT_CLR (BIT(18)) +#define MCPWM_OP0_TEB_INT_CLR_M (MCPWM_OP0_TEB_INT_CLR_V << MCPWM_OP0_TEB_INT_CLR_S) +#define MCPWM_OP0_TEB_INT_CLR_V 0x00000001U +#define MCPWM_OP0_TEB_INT_CLR_S 18 +/** MCPWM_OP1_TEB_INT_CLR : WT; bitpos: [19]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM operator 1 TEB event + */ +#define MCPWM_OP1_TEB_INT_CLR (BIT(19)) +#define MCPWM_OP1_TEB_INT_CLR_M (MCPWM_OP1_TEB_INT_CLR_V << MCPWM_OP1_TEB_INT_CLR_S) +#define MCPWM_OP1_TEB_INT_CLR_V 0x00000001U +#define MCPWM_OP1_TEB_INT_CLR_S 19 +/** MCPWM_OP2_TEB_INT_CLR : WT; bitpos: [20]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM operator 2 TEB event + */ +#define MCPWM_OP2_TEB_INT_CLR (BIT(20)) +#define MCPWM_OP2_TEB_INT_CLR_M (MCPWM_OP2_TEB_INT_CLR_V << MCPWM_OP2_TEB_INT_CLR_S) +#define MCPWM_OP2_TEB_INT_CLR_V 0x00000001U +#define MCPWM_OP2_TEB_INT_CLR_S 20 +/** MCPWM_FH0_CBC_INT_CLR : WT; bitpos: [21]; default: 0; + * Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on + * PWM0. + */ +#define MCPWM_FH0_CBC_INT_CLR (BIT(21)) +#define MCPWM_FH0_CBC_INT_CLR_M (MCPWM_FH0_CBC_INT_CLR_V << MCPWM_FH0_CBC_INT_CLR_S) +#define MCPWM_FH0_CBC_INT_CLR_V 0x00000001U +#define MCPWM_FH0_CBC_INT_CLR_S 21 +/** MCPWM_FH1_CBC_INT_CLR : WT; bitpos: [22]; default: 0; + * Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on + * PWM1. + */ +#define MCPWM_FH1_CBC_INT_CLR (BIT(22)) +#define MCPWM_FH1_CBC_INT_CLR_M (MCPWM_FH1_CBC_INT_CLR_V << MCPWM_FH1_CBC_INT_CLR_S) +#define MCPWM_FH1_CBC_INT_CLR_V 0x00000001U +#define MCPWM_FH1_CBC_INT_CLR_S 22 +/** MCPWM_FH2_CBC_INT_CLR : WT; bitpos: [23]; default: 0; + * Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on + * PWM2. + */ +#define MCPWM_FH2_CBC_INT_CLR (BIT(23)) +#define MCPWM_FH2_CBC_INT_CLR_M (MCPWM_FH2_CBC_INT_CLR_V << MCPWM_FH2_CBC_INT_CLR_S) +#define MCPWM_FH2_CBC_INT_CLR_V 0x00000001U +#define MCPWM_FH2_CBC_INT_CLR_S 23 +/** MCPWM_FH0_OST_INT_CLR : WT; bitpos: [24]; default: 0; + * Set this bit to clear the interrupt triggered by a one-shot mode action on PWM0. + */ +#define MCPWM_FH0_OST_INT_CLR (BIT(24)) +#define MCPWM_FH0_OST_INT_CLR_M (MCPWM_FH0_OST_INT_CLR_V << MCPWM_FH0_OST_INT_CLR_S) +#define MCPWM_FH0_OST_INT_CLR_V 0x00000001U +#define MCPWM_FH0_OST_INT_CLR_S 24 +/** MCPWM_FH1_OST_INT_CLR : WT; bitpos: [25]; default: 0; + * Set this bit to clear the interrupt triggered by a one-shot mode action on PWM1. + */ +#define MCPWM_FH1_OST_INT_CLR (BIT(25)) +#define MCPWM_FH1_OST_INT_CLR_M (MCPWM_FH1_OST_INT_CLR_V << MCPWM_FH1_OST_INT_CLR_S) +#define MCPWM_FH1_OST_INT_CLR_V 0x00000001U +#define MCPWM_FH1_OST_INT_CLR_S 25 +/** MCPWM_FH2_OST_INT_CLR : WT; bitpos: [26]; default: 0; + * Set this bit to clear the interrupt triggered by a one-shot mode action on PWM2. + */ +#define MCPWM_FH2_OST_INT_CLR (BIT(26)) +#define MCPWM_FH2_OST_INT_CLR_M (MCPWM_FH2_OST_INT_CLR_V << MCPWM_FH2_OST_INT_CLR_S) +#define MCPWM_FH2_OST_INT_CLR_V 0x00000001U +#define MCPWM_FH2_OST_INT_CLR_S 26 +/** MCPWM_CAP0_INT_CLR : WT; bitpos: [27]; default: 0; + * Set this bit to clear the interrupt triggered by capture on channel 0. + */ +#define MCPWM_CAP0_INT_CLR (BIT(27)) +#define MCPWM_CAP0_INT_CLR_M (MCPWM_CAP0_INT_CLR_V << MCPWM_CAP0_INT_CLR_S) +#define MCPWM_CAP0_INT_CLR_V 0x00000001U +#define MCPWM_CAP0_INT_CLR_S 27 +/** MCPWM_CAP1_INT_CLR : WT; bitpos: [28]; default: 0; + * Set this bit to clear the interrupt triggered by capture on channel 1. + */ +#define MCPWM_CAP1_INT_CLR (BIT(28)) +#define MCPWM_CAP1_INT_CLR_M (MCPWM_CAP1_INT_CLR_V << MCPWM_CAP1_INT_CLR_S) +#define MCPWM_CAP1_INT_CLR_V 0x00000001U +#define MCPWM_CAP1_INT_CLR_S 28 +/** MCPWM_CAP2_INT_CLR : WT; bitpos: [29]; default: 0; + * Set this bit to clear the interrupt triggered by capture on channel 2. + */ +#define MCPWM_CAP2_INT_CLR (BIT(29)) +#define MCPWM_CAP2_INT_CLR_M (MCPWM_CAP2_INT_CLR_V << MCPWM_CAP2_INT_CLR_S) +#define MCPWM_CAP2_INT_CLR_V 0x00000001U +#define MCPWM_CAP2_INT_CLR_S 29 -#define MCPWM_CLK_REG(i) (REG_MCPWM_BASE(i) + 0x120) -/* MCPWM_CLK_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */ -/*description: .*/ +/** MCPWM_CLK_REG register + * MCPWM APB configuration register + */ +#define MCPWM_CLK_REG(i) (DR_REG_MCPWM_BASE(i) + 0x120) +/** MCPWM_CLK_EN : R/W; bitpos: [0]; default: 0; + * Force clock on for this register file + */ #define MCPWM_CLK_EN (BIT(0)) -#define MCPWM_CLK_EN_M (BIT(0)) -#define MCPWM_CLK_EN_V 0x1 +#define MCPWM_CLK_EN_M (MCPWM_CLK_EN_V << MCPWM_CLK_EN_S) +#define MCPWM_CLK_EN_V 0x00000001U #define MCPWM_CLK_EN_S 0 -#define MCPWM_VERSION_REG(i) (REG_MCPWM_BASE(i) + 0x124) -/* MCPWM_DATE : R/W ;bitpos:[27:0] ;default: 28'h1509110 ; */ -/*description: .*/ -#define MCPWM_DATE 0x0FFFFFFF -#define MCPWM_DATE_M ((MCPWM_DATE_V)<<(MCPWM_DATE_S)) -#define MCPWM_DATE_V 0xFFFFFFF +/** MCPWM_VERSION_REG register + * Version register. + */ +#define MCPWM_VERSION_REG(i) (DR_REG_MCPWM_BASE(i) + 0x124) +/** MCPWM_DATE : R/W; bitpos: [27:0]; default: 34632240; + * Version of this register file + */ +#define MCPWM_DATE 0x0FFFFFFFU +#define MCPWM_DATE_M (MCPWM_DATE_V << MCPWM_DATE_S) +#define MCPWM_DATE_V 0x0FFFFFFFU #define MCPWM_DATE_S 0 - #ifdef __cplusplus } #endif - - - -#endif /*_SOC_MCPWM_REG_H_ */ diff --git a/components/soc/esp32s3/include/soc/mcpwm_struct.h b/components/soc/esp32s3/include/soc/mcpwm_struct.h index 565e0a98865..afd2a5633c4 100644 --- a/components/soc/esp32s3/include/soc/mcpwm_struct.h +++ b/components/soc/esp32s3/include/soc/mcpwm_struct.h @@ -1,461 +1,1468 @@ -// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -#ifndef _SOC_MCPWM_STRUCT_H_ -#define _SOC_MCPWM_STRUCT_H_ - +/** + * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once #include #ifdef __cplusplus extern "C" { #endif -typedef volatile struct { - union { - struct { - uint32_t prescale : 8; - uint32_t reserved8 : 24; - }; - uint32_t val; - } clk_cfg; - struct { - union { - struct { - uint32_t prescale : 8; - uint32_t period : 16; - uint32_t upmethod : 2; /*0: immediate, 1: eqz, 2: sync, 3: eqz | sync*/ - uint32_t reserved26 : 6; - }; - uint32_t val; - } period; - union { - struct { - uint32_t start : 3; /*0: stop @ eqz, 1: stop @ eqp, 2: free run, 3: start and stop @ next eqz, 4: start and stop @ next eqp,*/ - uint32_t mode : 2; /* 0: freeze, 1: inc, 2: dec, 3: up-down*/ - uint32_t reserved5 : 27; - }; - uint32_t val; - } mode; - union { - struct { - uint32_t in_en : 1; - uint32_t sync_sw : 1; /*write the negate value will trigger a sw sync*/ - uint32_t out_sel : 2; - uint32_t timer_phase : 16; /*phase for timer reload on sync event*/ - uint32_t phase_direct : 1; /*counter direction to apply on sync event*/ - uint32_t reserved21 : 11; - }; - uint32_t val; - } sync; - union { - struct { - uint32_t value : 16; - uint32_t direction : 1; - uint32_t reserved17 : 15; - }; - uint32_t val; - } status; - } timer[3]; - union { - struct { - uint32_t t0_in_sel : 3; - uint32_t t1_in_sel : 3; - uint32_t t2_in_sel : 3; - uint32_t ext_in0_inv : 1; - uint32_t ext_in1_inv : 1; - uint32_t ext_in2_inv : 1; - uint32_t reserved12 : 20; - }; - uint32_t val; - } timer_synci_cfg; - union { - struct { - uint32_t operator0_sel : 2; /*0: timer0, 1: timer1, 2: timer2*/ - uint32_t operator1_sel : 2; /*0: timer0, 1: timer1, 2: timer2*/ - uint32_t operator2_sel : 2; /*0: timer0, 1: timer1, 2: timer2*/ - uint32_t reserved6 : 26; - }; - uint32_t val; - } timer_sel; - struct { - union { - struct { - uint32_t a_upmethod : 4; /*0: immediate, bit0: tez, bit1: tep, bit2: sync, bit3: freeze*/ - uint32_t b_upmethod : 4; /*0: immediate, bit0: tez, bit1: tep, bit2: sync, bit3: freeze*/ - uint32_t a_shdw_full : 1; - uint32_t b_shdw_full : 1; - uint32_t reserved10 : 22; - }; - uint32_t val; - } cmpr_cfg; - union { - struct { - uint32_t cmpr_val : 16; - uint32_t reserved16 : 16; - }; - uint32_t val; - } cmpr_value[2]; - union { - struct { - uint32_t upmethod : 4; /*0: immediate, bit0: tez, bit1: tep, bit2: sync. bit3: freeze*/ - uint32_t t0_sel : 3; /*take effect immediately, 0: extra0, 1: extra1, 2: extra2, 3: sync_taken, 4: none*/ - uint32_t t1_sel : 3; /*take effect immediately, 0: extra0, 1: extra1, 2: extra2, 3: sync_taken, 4: none*/ - uint32_t reserved10 : 22; - }; - uint32_t val; - } gen_cfg0; - union { - struct { - uint32_t cntu_force_upmethod : 6; /*0: immediate, bit0: tez, bit1: tep, bit2: tea, bit3: teb, bit4: sync, bit5: freeze*/ - uint32_t a_cntuforce_mode : 2; /*0: disabled, 1: low, 2: high, 3: disabled*/ - uint32_t b_cntuforce_mode : 2; /*0: disabled, 1: low, 2: high, 3: disabled*/ - uint32_t a_nciforce : 1; /*non-continuous immediate sw force, a toggle will trigger a force event*/ - uint32_t a_nciforce_mode : 2; /*0: disabled, 1: low, 2: high, 3: disabled*/ - uint32_t b_nciforce : 1; /*non-continuous immediate sw force, a toggle will trigger a force event*/ - uint32_t b_nciforce_mode : 2; /*0: disabled, 1: low, 2: high, 3: disabled*/ - uint32_t reserved16 : 16; - }; - uint32_t val; - } gen_force; - union { - struct { - uint32_t utez : 2; - uint32_t utep : 2; - uint32_t utea : 2; - uint32_t uteb : 2; - uint32_t ut0 : 2; - uint32_t ut1 : 2; - uint32_t dtez : 2; - uint32_t dtep : 2; - uint32_t dtea : 2; - uint32_t dteb : 2; - uint32_t dt0 : 2; - uint32_t dt1 : 2; /*0: no change, 1: low, 2: high, 3: toggle*/ - uint32_t reserved24 : 8; - }; - uint32_t val; - } generator[2]; - union { - struct { - uint32_t fed_upmethod : 4; /*0: immediate, bit0: tez, bit1: tep, bit2: sync, bit3: freeze*/ - uint32_t red_upmethod : 4; /*0: immediate, bit0: tez, bit1: tep, bit2: sync, bit3: freeze*/ - uint32_t deb_mode : 1; /*immediate, dual-edge B mode, 0: fed/red take effect on different path separately, 1: fed/red take effect on B path, A out is in bypass or dulpB mode*/ - uint32_t a_outswap : 1; - uint32_t b_outswap : 1; - uint32_t red_insel : 1; - uint32_t fed_insel : 1; - uint32_t red_outinvert : 1; - uint32_t fed_outinvert : 1; - uint32_t a_outbypass : 1; - uint32_t b_outbypass : 1; - uint32_t clk_sel : 1; - uint32_t reserved18 : 14; - }; - uint32_t val; - } db_cfg; - union { - struct { - uint32_t fed : 16; - uint32_t reserved16 : 16; - }; - uint32_t val; - } db_fed_cfg; - union { - struct { - uint32_t red : 16; - uint32_t reserved16 : 16; - }; - uint32_t val; - } db_red_cfg; - union { - struct { - uint32_t en : 1; - uint32_t prescale : 4; - uint32_t duty : 3; - uint32_t oshtwth : 4; - uint32_t out_invert : 1; - uint32_t in_invert : 1; - uint32_t reserved14 : 18; - }; - uint32_t val; - } carrier_cfg; - union { - struct { - uint32_t sw_cbc : 1; /*0: disable, 1: enable*/ - uint32_t f2_cbc : 1; /*0: disable, 1: enable*/ - uint32_t f1_cbc : 1; /*0: disable, 1: enable*/ - uint32_t f0_cbc : 1; /*0: disable, 1: enable*/ - uint32_t sw_ost : 1; /*0: disable, 1: enable*/ - uint32_t f2_ost : 1; /*0: disable, 1: enable*/ - uint32_t f1_ost : 1; /*0: disable, 1: enable*/ - uint32_t f0_ost : 1; /*0: disable, 1: enable*/ - uint32_t a_cbc_d : 2; /*0: do nothing, 1: force lo, 2: force hi, 3: toggle*/ - uint32_t a_cbc_u : 2; /*0: do nothing, 1: force lo, 2: force hi, 3: toggle*/ - uint32_t a_ost_d : 2; /*0: do nothing, 1: force lo, 2: force hi, 3: toggle*/ - uint32_t a_ost_u : 2; /*0: do nothing, 1: force lo, 2: force hi, 3: toggle*/ - uint32_t b_cbc_d : 2; /*0: do nothing, 1: force lo, 2: force hi, 3: toggle*/ - uint32_t b_cbc_u : 2; /*0: do nothing, 1: force lo, 2: force hi, 3: toggle*/ - uint32_t b_ost_d : 2; /*0: do nothing, 1: force lo, 2: force hi, 3: toggle*/ - uint32_t b_ost_u : 2; /*0: do nothing, 1: force lo, 2: force hi, 3: toggle*/ - uint32_t reserved24 : 8; - }; - uint32_t val; - } tz_cfg0; - union { - struct { - uint32_t clr_ost : 1; /*a toggle will clear oneshot tripping*/ - uint32_t cbcpulse : 2; /*bit0: tez, bit1: tep*/ - uint32_t force_cbc : 1; /*a toggle trigger a cycle-by-cycle tripping*/ - uint32_t force_ost : 1; /*a toggle trigger a oneshot tripping*/ - uint32_t reserved5 : 27; - }; - uint32_t val; - } tz_cfg1; - union { - struct { - uint32_t cbc_on : 1; - uint32_t ost_on : 1; - uint32_t reserved2 : 30; - }; - uint32_t val; - } tz_status; - } channel[3]; - union { - struct { - uint32_t f0_en : 1; - uint32_t f1_en : 1; - uint32_t f2_en : 1; - uint32_t f0_pole : 1; - uint32_t f1_pole : 1; - uint32_t f2_pole : 1; - uint32_t event_f0 : 1; - uint32_t event_f1 : 1; - uint32_t event_f2 : 1; - uint32_t reserved9 : 23; - }; - uint32_t val; - } fault_detect; - union { - struct { - uint32_t timer_en : 1; - uint32_t synci_en : 1; - uint32_t synci_sel : 3; - uint32_t sync_sw : 1; /*Write 1 will force a timer sync*/ - uint32_t reserved6 : 26; - }; - uint32_t val; - } cap_timer_cfg; - uint32_t cap_timer_phase; - union { - struct { - uint32_t en : 1; - uint32_t mode : 2; /*bit0: negedge cap en, bit1: posedge cap en*/ - uint32_t prescale : 8; - uint32_t in_invert : 1; - uint32_t sw : 1; /*Write 1 will trigger a sw capture*/ - uint32_t reserved13 : 19; - }; - uint32_t val; - } cap_cfg_ch[3]; - uint32_t cap_val_ch[3]; - union { - struct { - uint32_t cap0_edge : 1; - uint32_t cap1_edge : 1; - uint32_t cap2_edge : 1; /*cap trigger's edge, 0: posedge, 1: negedge*/ - uint32_t reserved3 : 29; - }; - uint32_t val; - } cap_status; - union { - struct { - uint32_t global_up_en : 1; - uint32_t global_force_up : 1; /*a toggle will trigger a force update, all timers and operators will update their active regs*/ - uint32_t op0_up_en : 1; - uint32_t op0_force_up : 1; /*a toggle will trigger a force update*/ - uint32_t op1_up_en : 1; - uint32_t op1_force_up : 1; /*a toggle will trigger a force update*/ - uint32_t op2_up_en : 1; /*reg update local enable*/ - uint32_t op2_force_up : 1; /*a toggle will trigger a force update*/ - uint32_t reserved8 : 24; - }; - uint32_t val; - } update_cfg; - union { - struct { - uint32_t timer0_stop : 1; - uint32_t timer1_stop : 1; - uint32_t timer2_stop : 1; - uint32_t timer0_tez : 1; - uint32_t timer1_tez : 1; - uint32_t timer2_tez : 1; - uint32_t timer0_tep : 1; - uint32_t timer1_tep : 1; - uint32_t timer2_tep : 1; - uint32_t fault0 : 1; - uint32_t fault1 : 1; - uint32_t fault2 : 1; - uint32_t fault0_clr : 1; - uint32_t fault1_clr : 1; - uint32_t fault2_clr : 1; - uint32_t cmpr0_tea : 1; - uint32_t cmpr1_tea : 1; - uint32_t cmpr2_tea : 1; - uint32_t cmpr0_teb : 1; - uint32_t cmpr1_teb : 1; - uint32_t cmpr2_teb : 1; - uint32_t tz0_cbc : 1; - uint32_t tz1_cbc : 1; - uint32_t tz2_cbc : 1; - uint32_t tz0_ost : 1; - uint32_t tz1_ost : 1; - uint32_t tz2_ost : 1; - uint32_t cap0 : 1; - uint32_t cap1 : 1; - uint32_t cap2 : 1; - uint32_t reserved30 : 2; - }; - uint32_t val; - } int_ena; - union { - struct { - uint32_t timer0_stop : 1; - uint32_t timer1_stop : 1; - uint32_t timer2_stop : 1; - uint32_t timer0_tez : 1; - uint32_t timer1_tez : 1; - uint32_t timer2_tez : 1; - uint32_t timer0_tep : 1; - uint32_t timer1_tep : 1; - uint32_t timer2_tep : 1; - uint32_t fault0 : 1; - uint32_t fault1 : 1; - uint32_t fault2 : 1; - uint32_t fault0_clr : 1; - uint32_t fault1_clr : 1; - uint32_t fault2_clr : 1; - uint32_t cmpr0_tea : 1; - uint32_t cmpr1_tea : 1; - uint32_t cmpr2_tea : 1; - uint32_t cmpr0_teb : 1; - uint32_t cmpr1_teb : 1; - uint32_t cmpr2_teb : 1; - uint32_t tz0_cbc : 1; - uint32_t tz1_cbc : 1; - uint32_t tz2_cbc : 1; - uint32_t tz0_ost : 1; - uint32_t tz1_ost : 1; - uint32_t tz2_ost : 1; - uint32_t cap0 : 1; - uint32_t cap1 : 1; - uint32_t cap2 : 1; - uint32_t reserved30 : 2; - }; - uint32_t val; - } int_raw; - union { - struct { - uint32_t timer0_stop : 1; - uint32_t timer1_stop : 1; - uint32_t timer2_stop : 1; - uint32_t timer0_tez : 1; - uint32_t timer1_tez : 1; - uint32_t timer2_tez : 1; - uint32_t timer0_tep : 1; - uint32_t timer1_tep : 1; - uint32_t timer2_tep : 1; - uint32_t fault0 : 1; - uint32_t fault1 : 1; - uint32_t fault2 : 1; - uint32_t fault0_clr : 1; - uint32_t fault1_clr : 1; - uint32_t fault2_clr : 1; - uint32_t cmpr0_tea : 1; - uint32_t cmpr1_tea : 1; - uint32_t cmpr2_tea : 1; - uint32_t cmpr0_teb : 1; - uint32_t cmpr1_teb : 1; - uint32_t cmpr2_teb : 1; - uint32_t tz0_cbc : 1; - uint32_t tz1_cbc : 1; - uint32_t tz2_cbc : 1; - uint32_t tz0_ost : 1; - uint32_t tz1_ost : 1; - uint32_t tz2_ost : 1; - uint32_t cap0 : 1; - uint32_t cap1 : 1; - uint32_t cap2 : 1; - uint32_t reserved30 : 2; - }; - uint32_t val; - } int_st; - union { - struct { - uint32_t timer0_stop : 1; - uint32_t timer1_stop : 1; - uint32_t timer2_stop : 1; - uint32_t timer0_tez : 1; - uint32_t timer1_tez : 1; - uint32_t timer2_tez : 1; - uint32_t timer0_tep : 1; - uint32_t timer1_tep : 1; - uint32_t timer2_tep : 1; - uint32_t fault0 : 1; - uint32_t fault1 : 1; - uint32_t fault2 : 1; - uint32_t fault0_clr : 1; - uint32_t fault1_clr : 1; - uint32_t fault2_clr : 1; - uint32_t cmpr0_tea : 1; - uint32_t cmpr1_tea : 1; - uint32_t cmpr2_tea : 1; - uint32_t cmpr0_teb : 1; - uint32_t cmpr1_teb : 1; - uint32_t cmpr2_teb : 1; - uint32_t tz0_cbc : 1; - uint32_t tz1_cbc : 1; - uint32_t tz2_cbc : 1; - uint32_t tz0_ost : 1; - uint32_t tz1_ost : 1; - uint32_t tz2_ost : 1; - uint32_t cap0 : 1; - uint32_t cap1 : 1; - uint32_t cap2 : 1; - uint32_t reserved30 : 2; - }; - uint32_t val; - } int_clr; - union { - struct { - uint32_t en : 1; - uint32_t reserved1 : 31; - }; - uint32_t val; - } reg_clk; - union { - struct { - uint32_t date : 28; - uint32_t reserved28 : 4; - }; - uint32_t val; - } version; +/** Group: Prescaler configuration */ +/** Type of clk_cfg register + * PWM clock prescaler register. + */ +typedef union { + struct { + /** clk_prescale : R/W; bitpos: [7:0]; default: 0; + * Period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1) + */ + uint32_t clk_prescale: 8; + uint32_t reserved_8: 24; + }; + uint32_t val; +} mcpwm_clk_cfg_reg_t; + + +/** Group: MCPWM Timer Configuration and status */ +/** Type of timer_cfg0 register + * PWM timer period and update method configuration register. + */ +typedef union { + struct { + /** timer_prescale : R/W; bitpos: [7:0]; default: 0; + * Configure the divisor of PT0_clk, takes effect when PWM timer stops and starts + * agsin. period of PT0_clk = Period of PWM_clk * (PWM_TIMER_PRESCALE + 1) + */ + uint32_t timer_prescale: 8; + /** timer_period : R/W; bitpos: [23:8]; default: 255; + * period shadow register of PWM timer + */ + uint32_t timer_period: 16; + /** timer_period_upmethod : R/W; bitpos: [25:24]; default: 0; + * Update method for active register of PWM timer period, 0: immediate, 1: TEZ, 2: + * sync, 3: TEZ or sync. TEZ here and below means timer equal zero event + */ + uint32_t timer_period_upmethod: 2; + uint32_t reserved_26: 6; + }; + uint32_t val; +} mcpwm_timer_cfg0_reg_t; + +/** Type of timer_cfg1 register + * PWM timer working mode and start/stop control configuration register. + */ +typedef union { + struct { + /** timer_start : R/W/SC; bitpos: [2:0]; default: 0; + * PWM timer start and stop control. 0: if PWM timer starts, then stops at TEZ, 1: + * if timer starts, then stops at TEP, 2: PWM timer starts and runs on, 3: timer + * starts and stops at the next TEZ, 4: timer starts and stops at the next TEP. TEP + * here and below means the event that happens when the timer equals to period + */ + uint32_t timer_start: 3; + /** timer_mod : R/W; bitpos: [4:3]; default: 0; + * PWM timer working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down + * mode + */ + uint32_t timer_mod: 2; + uint32_t reserved_5: 27; + }; + uint32_t val; +} mcpwm_timer_cfg1_reg_t; + +/** Type of timer_sync register + * PWM timer sync function configuration register. + */ +typedef union { + struct { + /** timer_synci_en : R/W; bitpos: [0]; default: 0; + * When set, timer reloading with phase on sync input event is enabled. + */ + uint32_t timer_synci_en: 1; + /** timer_sync_sw : R/W; bitpos: [1]; default: 0; + * Toggling this bit will trigger a software sync. + */ + uint32_t timer_sync_sw: 1; + /** timer_synco_sel : R/W; bitpos: [3:2]; default: 0; + * PWM timer sync_out selection, 0: sync_in, 1: TEZ, 2: TEP, and sync out will always + * generate when toggling the reg_timer_sync_sw bit + */ + uint32_t timer_synco_sel: 2; + /** timer_phase : R/W; bitpos: [19:4]; default: 0; + * phase for timer reload on sync event + */ + uint32_t timer_phase: 16; + /** timer_phase_direction : R/W; bitpos: [20]; default: 0; + * Configure the PWM timer's direction at the time sync event occurs when timer mode + * is up-down mode: 0-increase,1-decrease + */ + uint32_t timer_phase_direction: 1; + uint32_t reserved_21: 11; + }; + uint32_t val; +} mcpwm_timer_sync_reg_t; + +/** Type of timer_status register + * PWM timer status register. + */ +typedef union { + struct { + /** timer_value : RO; bitpos: [15:0]; default: 0; + * current PWM timer counter value + */ + uint32_t timer_value: 16; + /** timer_direction : RO; bitpos: [16]; default: 0; + * current PWM timer counter direction, 0: increment 1: decrement + */ + uint32_t timer_direction: 1; + uint32_t reserved_17: 15; + }; + uint32_t val; +} mcpwm_timer_status_reg_t; + + +/** Group: Common configuration for MCPWM timers */ +/** Type of timer_synci_cfg register + * Synchronization input selection for three PWM timers. + */ +typedef union { + struct { + /** timer0_syncisel : R/W; bitpos: [2:0]; default: 0; + * select sync input for PWM timer0, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, + * 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: + * SYNC2 from GPIO matrix, other values: no sync input selected + */ + uint32_t timer0_syncisel: 3; + /** timer1_syncisel : R/W; bitpos: [5:3]; default: 0; + * select sync input for PWM timer1, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, + * 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: + * SYNC2 from GPIO matrix, other values: no sync input selected + */ + uint32_t timer1_syncisel: 3; + /** timer2_syncisel : R/W; bitpos: [8:6]; default: 0; + * select sync input for PWM timer2, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, + * 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: + * SYNC2 from GPIO matrix, other values: no sync input selected + */ + uint32_t timer2_syncisel: 3; + /** external_synci0_invert : R/W; bitpos: [9]; default: 0; + * invert SYNC0 from GPIO matrix + */ + uint32_t external_synci0_invert: 1; + /** external_synci1_invert : R/W; bitpos: [10]; default: 0; + * invert SYNC1 from GPIO matrix + */ + uint32_t external_synci1_invert: 1; + /** external_synci2_invert : R/W; bitpos: [11]; default: 0; + * invert SYNC2 from GPIO matrix + */ + uint32_t external_synci2_invert: 1; + uint32_t reserved_12: 20; + }; + uint32_t val; +} mcpwm_timer_synci_cfg_reg_t; + +/** Type of operator_timersel register + * Select specific timer for PWM operators. + */ +typedef union { + struct { + /** operator0_timersel : R/W; bitpos: [1:0]; default: 0; + * Select which PWM timer is the timing reference for PWM operator0, 0: timer0, 1: + * timer1, 2: timer2 + */ + uint32_t operator0_timersel: 2; + /** operator1_timersel : R/W; bitpos: [3:2]; default: 0; + * Select which PWM timer is the timing reference for PWM operator1, 0: timer0, 1: + * timer1, 2: timer2 + */ + uint32_t operator1_timersel: 2; + /** operator2_timersel : R/W; bitpos: [5:4]; default: 0; + * Select which PWM timer is the timing reference for PWM operator2, 0: timer0, 1: + * timer1, 2: timer2 + */ + uint32_t operator2_timersel: 2; + uint32_t reserved_6: 26; + }; + uint32_t val; +} mcpwm_operator_timersel_reg_t; + + +/** Group: MCPWM Operator Configuration and Status */ +/** Type of gen_stmp_cfg register + * Transfer status and update method for time stamp registers A and B + */ +typedef union { + struct { + /** gen_a_upmethod : R/W; bitpos: [3:0]; default: 0; + * Update method for PWM generator time stamp A's active register. When all bits are + * set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when + * bit2 is set to 1: sync, when bit3 is set to 1: disable the update. + */ + uint32_t gen_a_upmethod: 4; + /** gen_b_upmethod : R/W; bitpos: [7:4]; default: 0; + * Update method for PWM generator time stamp B's active register. When all bits are + * set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when + * bit2 is set to 1: sync, when bit3 is set to 1: disable the update. + */ + uint32_t gen_b_upmethod: 4; + /** gen_a_shdw_full : R/W/WTC/SC; bitpos: [8]; default: 0; + * Set and reset by hardware. If set, PWM generator time stamp A's shadow reg is + * filled and waiting to be transferred to A's active reg. If cleared, A's active reg + * has been updated with shadow register latest value + */ + uint32_t gen_a_shdw_full: 1; + /** gen_b_shdw_full : R/W/WTC/SC; bitpos: [9]; default: 0; + * Set and reset by hardware. If set, PWM generator time stamp B's shadow reg is + * filled and waiting to be transferred to B's active reg. If cleared, B's active reg + * has been updated with shadow register latest value + */ + uint32_t gen_b_shdw_full: 1; + uint32_t reserved_10: 22; + }; + uint32_t val; +} mcpwm_gen_stmp_cfg_reg_t; + +/** Type of gen_tstmp register + * PWM generator shadow register for timer stamp + */ +typedef union { + struct { + /** gen : R/W; bitpos: [15:0]; default: 0; + * PWM generator time stamp's shadow register + */ + uint32_t gen: 16; + uint32_t reserved_16: 16; + }; + uint32_t val; +} mcpwm_gen_tstmp_reg_t; + +/** Type of gen_cfg0 register + * PWM generator event T0 and T1 handling + */ +typedef union { + struct { + /** gen_cfg_upmethod : R/W; bitpos: [3:0]; default: 0; + * Update method for PWM generator's active register of configuration. When all bits + * are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to + * 1:TEP,when bit2 is set to 1:sync,when bit3 is set to 1:disable the update + */ + uint32_t gen_cfg_upmethod: 4; + /** gen_t0_sel : R/W; bitpos: [6:4]; default: 0; + * Source selection for PWM generator event_t0, take effect immediately, 0: + * fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none + */ + uint32_t gen_t0_sel: 3; + /** gen_t1_sel : R/W; bitpos: [9:7]; default: 0; + * Source selection for PWM generator event_t1, take effect immediately, 0: + * fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none + */ + uint32_t gen_t1_sel: 3; + uint32_t reserved_10: 22; + }; + uint32_t val; +} mcpwm_gen_cfg0_reg_t; + +/** Type of gen_force register + * Permissives to force PWM0A and PWM0B outputs by software + */ +typedef union { + struct { + /** gen_cntuforce_upmethod : R/W; bitpos: [5:0]; default: 32; + * Updating method for continuous software force of PWM generator0. When all bits are + * set to 0: immediately, when bit0 is set to 1: TEZ,,when bit1 is set to 1: TEP, when + * bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync, + * when bit5 is set to 1: disable update. (TEA/B here and below means an event + * generated when the timer's value equals to that of register A/B.) + */ + uint32_t gen_cntuforce_upmethod: 6; + /** gen_a_cntuforce_mode : R/W; bitpos: [7:6]; default: 0; + * Continuous software force mode for PWM0A. 0: disabled, 1: low, 2: high, 3: disabled + */ + uint32_t gen_a_cntuforce_mode: 2; + /** gen_b_cntuforce_mode : R/W; bitpos: [9:8]; default: 0; + * Continuous software force mode for PWM0B. 0: disabled, 1: low, 2: high, 3: disabled + */ + uint32_t gen_b_cntuforce_mode: 2; + /** gen_a_nciforce : R/W; bitpos: [10]; default: 0; + * Trigger of non-continuous immediate software-force event for PWM0A, a toggle will + * trigger a force event. + */ + uint32_t gen_a_nciforce: 1; + /** gen_a_nciforce_mode : R/W; bitpos: [12:11]; default: 0; + * non-continuous immediate software force mode for PWM0A, 0: disabled, 1: low, 2: + * high, 3: disabled + */ + uint32_t gen_a_nciforce_mode: 2; + /** gen_b_nciforce : R/W; bitpos: [13]; default: 0; + * Trigger of non-continuous immediate software-force event for PWM0B, a toggle will + * trigger a force event. + */ + uint32_t gen_b_nciforce: 1; + /** gen_b_nciforce_mode : R/W; bitpos: [15:14]; default: 0; + * non-continuous immediate software force mode for PWM0B, 0: disabled, 1: low, 2: + * high, 3: disabled + */ + uint32_t gen_b_nciforce_mode: 2; + uint32_t reserved_16: 16; + }; + uint32_t val; +} mcpwm_gen_force_reg_t; + +/** Type of generator register + * Actions triggered by events on PWM0A + */ +typedef union { + struct { + /** gen_utez : R/W; bitpos: [1:0]; default: 0; + * Action on PWM0A triggered by event TEZ when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ + uint32_t gen_utez: 2; + /** gen_utep : R/W; bitpos: [3:2]; default: 0; + * Action on PWM0A triggered by event TEP when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ + uint32_t gen_utep: 2; + /** gen_utea : R/W; bitpos: [5:4]; default: 0; + * Action on PWM0A triggered by event TEA when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ + uint32_t gen_utea: 2; + /** gen_uteb : R/W; bitpos: [7:6]; default: 0; + * Action on PWM0A triggered by event TEB when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ + uint32_t gen_uteb: 2; + /** gen_ut0 : R/W; bitpos: [9:8]; default: 0; + * Action on PWM0A triggered by event_t0 when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ + uint32_t gen_ut0: 2; + /** gen_ut1 : R/W; bitpos: [11:10]; default: 0; + * Action on PWM0A triggered by event_t1 when timer increasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ + uint32_t gen_ut1: 2; + /** gen_dtez : R/W; bitpos: [13:12]; default: 0; + * Action on PWM0A triggered by event TEZ when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ + uint32_t gen_dtez: 2; + /** gen_dtep : R/W; bitpos: [15:14]; default: 0; + * Action on PWM0A triggered by event TEP when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ + uint32_t gen_dtep: 2; + /** gen_dtea : R/W; bitpos: [17:16]; default: 0; + * Action on PWM0A triggered by event TEA when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ + uint32_t gen_dtea: 2; + /** gen_dteb : R/W; bitpos: [19:18]; default: 0; + * Action on PWM0A triggered by event TEB when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ + uint32_t gen_dteb: 2; + /** gen_dt0 : R/W; bitpos: [21:20]; default: 0; + * Action on PWM0A triggered by event_t0 when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ + uint32_t gen_dt0: 2; + /** gen_dt1 : R/W; bitpos: [23:22]; default: 0; + * Action on PWM0A triggered by event_t1 when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ + uint32_t gen_dt1: 2; + uint32_t reserved_24: 8; + }; + uint32_t val; +} mcpwm_gen_reg_t; + +/** Type of dt_cfg register + * PWM generator dead time type selection and configuration + */ +typedef union { + struct { + /** dt_fed_upmethod : R/W; bitpos: [3:0]; default: 0; + * Update method for FED (rising edge delay) active register. 0: immediate, when bit0 + * is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when + * bit3 is set to 1: disable the update + */ + uint32_t dt_fed_upmethod: 4; + /** dt_red_upmethod : R/W; bitpos: [7:4]; default: 0; + * Update method for RED (rising edge delay) active register. 0: immediate, when bit0 + * is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when + * bit3 is set to 1: disable the update + */ + uint32_t dt_red_upmethod: 4; + /** dt_deb_mode : R/W; bitpos: [8]; default: 0; + * S8 in table, dual-edge B mode, 0: fed/red take effect on different path separately, + * 1: fed/red take effect on B path, A out is in bypass or dulpB mode + */ + uint32_t dt_deb_mode: 1; + /** dt_a_outswap : R/W; bitpos: [9]; default: 0; + * S6 in table + */ + uint32_t dt_a_outswap: 1; + /** dt_b_outswap : R/W; bitpos: [10]; default: 0; + * S7 in table + */ + uint32_t dt_b_outswap: 1; + /** dt_red_insel : R/W; bitpos: [11]; default: 0; + * S4 in table + */ + uint32_t dt_red_insel: 1; + /** dt_fed_insel : R/W; bitpos: [12]; default: 0; + * S5 in table + */ + uint32_t dt_fed_insel: 1; + /** dt_red_outinvert : R/W; bitpos: [13]; default: 0; + * S2 in table + */ + uint32_t dt_red_outinvert: 1; + /** dt_fed_outinvert : R/W; bitpos: [14]; default: 0; + * S3 in table + */ + uint32_t dt_fed_outinvert: 1; + /** dt_a_outbypass : R/W; bitpos: [15]; default: 1; + * S1 in table + */ + uint32_t dt_a_outbypass: 1; + /** dt_b_outbypass : R/W; bitpos: [16]; default: 1; + * S0 in table + */ + uint32_t dt_b_outbypass: 1; + /** dt_clk_sel : R/W; bitpos: [17]; default: 0; + * Dead time clock selection. 0: PWM_clk, 1: PT_clk + */ + uint32_t dt_clk_sel: 1; + uint32_t reserved_18: 14; + }; + uint32_t val; +} mcpwm_dt_cfg_reg_t; + +/** Type of dt_fed_cfg register + * PWM generator shadow register for falling edge delay (FED). + */ +typedef union { + struct { + /** dt_fed : R/W; bitpos: [15:0]; default: 0; + * Shadow register for FED + */ + uint32_t dt_fed: 16; + uint32_t reserved_16: 16; + }; + uint32_t val; +} mcpwm_dt_fed_cfg_reg_t; + +/** Type of dt_red_cfg register + * PWM generator shadow register for rising edge delay (RED). + */ +typedef union { + struct { + /** dt_red : R/W; bitpos: [15:0]; default: 0; + * Shadow register for RED + */ + uint32_t dt_red: 16; + uint32_t reserved_16: 16; + }; + uint32_t val; +} mcpwm_dt_red_cfg_reg_t; + +/** Type of carrier_cfg register + * PWM generator carrier enable and configuratoin + */ +typedef union { + struct { + /** carrier_en : R/W; bitpos: [0]; default: 0; + * When set, carrier function is enabled. When cleared, carrier is bypassed + */ + uint32_t carrier_en: 1; + /** carrier_prescale : R/W; bitpos: [4:1]; default: 0; + * PWM carrier clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk * + * (PWM_CARRIER_PRESCALE + 1) + */ + uint32_t carrier_prescale: 4; + /** carrier_duty : R/W; bitpos: [7:5]; default: 0; + * carrier duty selection. Duty = PWM_CARRIER_DUTY / 8 + */ + uint32_t carrier_duty: 3; + /** carrier_oshtwth : R/W; bitpos: [11:8]; default: 0; + * width of the first pulse in number of periods of the carrier + */ + uint32_t carrier_oshtwth: 4; + /** carrier_out_invert : R/W; bitpos: [12]; default: 0; + * when set, invert the output of PWM0A and PWM0B for this submodule + */ + uint32_t carrier_out_invert: 1; + /** carrier_in_invert : R/W; bitpos: [13]; default: 0; + * when set, invert the input of PWM0A and PWM0B for this submodule + */ + uint32_t carrier_in_invert: 1; + uint32_t reserved_14: 18; + }; + uint32_t val; +} mcpwm_carrier_cfg_reg_t; + +/** Type of fh_cfg0 register + * Actions on PWM0A and PWM0B trip events + */ +typedef union { + struct { + /** fh_sw_cbc : R/W; bitpos: [0]; default: 0; + * Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable + */ + uint32_t fh_sw_cbc: 1; + /** fh_f2_cbc : R/W; bitpos: [1]; default: 0; + * fault_event2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + */ + uint32_t fh_f2_cbc: 1; + /** fh_f1_cbc : R/W; bitpos: [2]; default: 0; + * fault_event1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + */ + uint32_t fh_f1_cbc: 1; + /** fh_f0_cbc : R/W; bitpos: [3]; default: 0; + * fault_event0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + */ + uint32_t fh_f0_cbc: 1; + /** fh_sw_ost : R/W; bitpos: [4]; default: 0; + * Enable register for software force one-shot mode action. 0: disable, 1: enable + */ + uint32_t fh_sw_ost: 1; + /** fh_f2_ost : R/W; bitpos: [5]; default: 0; + * fault_event2 will trigger one-shot mode action. 0: disable, 1: enable + */ + uint32_t fh_f2_ost: 1; + /** fh_f1_ost : R/W; bitpos: [6]; default: 0; + * fault_event1 will trigger one-shot mode action. 0: disable, 1: enable + */ + uint32_t fh_f1_ost: 1; + /** fh_f0_ost : R/W; bitpos: [7]; default: 0; + * fault_event0 will trigger one-shot mode action. 0: disable, 1: enable + */ + uint32_t fh_f0_ost: 1; + /** fh_a_cbc_d : R/W; bitpos: [9:8]; default: 0; + * Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is + * decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + */ + uint32_t fh_a_cbc_d: 2; + /** fh_a_cbc_u : R/W; bitpos: [11:10]; default: 0; + * Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is + * increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + */ + uint32_t fh_a_cbc_u: 2; + /** fh_a_ost_d : R/W; bitpos: [13:12]; default: 0; + * One-shot mode action on PWM0A when fault event occurs and timer is decreasing. 0: + * do nothing, 1: force low, 2: force high, 3: toggle + */ + uint32_t fh_a_ost_d: 2; + /** fh_a_ost_u : R/W; bitpos: [15:14]; default: 0; + * One-shot mode action on PWM0A when fault event occurs and timer is increasing. 0: + * do nothing, 1: force low, 2: force high, 3: toggle + */ + uint32_t fh_a_ost_u: 2; + /** fh_b_cbc_d : R/W; bitpos: [17:16]; default: 0; + * Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is + * decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + */ + uint32_t fh_b_cbc_d: 2; + /** fh_b_cbc_u : R/W; bitpos: [19:18]; default: 0; + * Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is + * increasing. 0: do nothing,1: force low, 2: force high, 3: toggle + */ + uint32_t fh_b_cbc_u: 2; + /** fh_b_ost_d : R/W; bitpos: [21:20]; default: 0; + * One-shot mode action on PWM0B when fault event occurs and timer is decreasing. 0: + * do nothing, 1: force low, 2: force high, 3: toggle + */ + uint32_t fh_b_ost_d: 2; + /** fh_b_ost_u : R/W; bitpos: [23:22]; default: 0; + * One-shot mode action on PWM0B when fault event occurs and timer is increasing. 0: + * do nothing, 1: force low, 2: force high, 3: toggle + */ + uint32_t fh_b_ost_u: 2; + uint32_t reserved_24: 8; + }; + uint32_t val; +} mcpwm_fh_cfg0_reg_t; + +/** Type of fh_cfg1 register + * Software triggers for fault handler actions + */ +typedef union { + struct { + /** fh_clr_ost : R/W; bitpos: [0]; default: 0; + * a rising edge will clear on going one-shot mode action + */ + uint32_t fh_clr_ost: 1; + /** fh_cbcpulse : R/W; bitpos: [2:1]; default: 0; + * cycle-by-cycle mode action refresh moment selection. When bit0 is set to 1: TEZ, + * when bit1 is set to 1:TEP, when bit0 and bit1 both set to 0: stop refresh, when + * bit0 and bit1 both set to 1: refresh at TEP/TEZ + */ + uint32_t fh_cbcpulse: 2; + /** fh_force_cbc : R/W; bitpos: [3]; default: 0; + * a toggle trigger a cycle-by-cycle mode action + */ + uint32_t fh_force_cbc: 1; + /** fh_force_ost : R/W; bitpos: [4]; default: 0; + * a toggle (software negate its value) triggers a one-shot mode action + */ + uint32_t fh_force_ost: 1; + uint32_t reserved_5: 27; + }; + uint32_t val; +} mcpwm_fh_cfg1_reg_t; + +/** Type of fh_status register + * Status of fault events. + */ +typedef union { + struct { + /** fh_cbc_on : RO; bitpos: [0]; default: 0; + * Set and reset by hardware. If set, a cycle-by-cycle mode action is on going + */ + uint32_t fh_cbc_on: 1; + /** fh_ost_on : RO; bitpos: [1]; default: 0; + * Set and reset by hardware. If set, an one-shot mode action is on going + */ + uint32_t fh_ost_on: 1; + uint32_t reserved_2: 30; + }; + uint32_t val; +} mcpwm_fh_status_reg_t; + +/** Group: Fault Detection Configuration and Status */ +/** Type of fault_detect register + * Fault detection configuration and status + */ +typedef union { + struct { + /** f0_en : R/W; bitpos: [0]; default: 0; + * When set, fault_event0 generation is enabled + */ + uint32_t f0_en: 1; + /** f1_en : R/W; bitpos: [1]; default: 0; + * When set, fault_event1 generation is enabled + */ + uint32_t f1_en: 1; + /** f2_en : R/W; bitpos: [2]; default: 0; + * When set, fault_event2 generation is enabled + */ + uint32_t f2_en: 1; + /** f0_pole : R/W; bitpos: [3]; default: 0; + * Set fault_event0 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, + * 1: level high + */ + uint32_t f0_pole: 1; + /** f1_pole : R/W; bitpos: [4]; default: 0; + * Set fault_event1 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, + * 1: level high + */ + uint32_t f1_pole: 1; + /** f2_pole : R/W; bitpos: [5]; default: 0; + * Set fault_event2 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, + * 1: level high + */ + uint32_t f2_pole: 1; + /** event_f0 : RO; bitpos: [6]; default: 0; + * Set and reset by hardware. If set, fault_event0 is on going + */ + uint32_t event_f0: 1; + /** event_f1 : RO; bitpos: [7]; default: 0; + * Set and reset by hardware. If set, fault_event1 is on going + */ + uint32_t event_f1: 1; + /** event_f2 : RO; bitpos: [8]; default: 0; + * Set and reset by hardware. If set, fault_event2 is on going + */ + uint32_t event_f2: 1; + uint32_t reserved_9: 23; + }; + uint32_t val; +} mcpwm_fault_detect_reg_t; + + +/** Group: Capture Configuration and Status */ +/** Type of cap_timer_cfg register + * Configure capture timer + */ +typedef union { + struct { + /** cap_timer_en : R/W; bitpos: [0]; default: 0; + * When set, capture timer incrementing under APB_clk is enabled. + */ + uint32_t cap_timer_en: 1; + /** cap_synci_en : R/W; bitpos: [1]; default: 0; + * When set, capture timer sync is enabled. + */ + uint32_t cap_synci_en: 1; + /** cap_synci_sel : R/W; bitpos: [4:2]; default: 0; + * capture module sync input selection. 0: none, 1: timer0 sync_out, 2: timer1 + * sync_out, 3: timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, + * 6: SYNC2 from GPIO matrix + */ + uint32_t cap_synci_sel: 3; + /** cap_sync_sw : WT; bitpos: [5]; default: 0; + * When reg_cap_synci_en is 1, write 1 will trigger a capture timer sync, capture + * timer is loaded with value in phase register. + */ + uint32_t cap_sync_sw: 1; + uint32_t reserved_6: 26; + }; + uint32_t val; +} mcpwm_cap_timer_cfg_reg_t; + +/** Type of cap_timer_phase register + * Phase for capture timer sync + */ +typedef union { + struct { + /** cap_timer_phase : R/W; bitpos: [31:0]; default: 0; + * Phase value for capture timer sync operation. + */ + uint32_t cap_timer_phase: 32; + }; + uint32_t val; +} mcpwm_cap_timer_phase_reg_t; + +/** Type of cap_chn_cfg register + * Capture channel 0 configuration and enable + */ +typedef union { + struct { + /** capn_en : R/W; bitpos: [0]; default: 0; + * When set, capture on channel 0 is enabled + */ + uint32_t capn_en: 1; + /** capn_mode : R/W; bitpos: [2:1]; default: 0; + * Edge of capture on channel 0 after prescaling. When bit0 is set to 1: enable + * capture on the negative edge, When bit1 is set to 1: enable capture on the positive + * edge. + */ + uint32_t capn_mode: 2; + /** capn_prescale : R/W; bitpos: [10:3]; default: 0; + * Value of prescaling on possitive edge of CAPn. Prescale value = PWM_CAPn_PRESCALE + + * 1 + */ + uint32_t capn_prescale: 8; + /** capn_in_invert : R/W; bitpos: [11]; default: 0; + * when set, CAPn form GPIO matrix is inverted before prescale + */ + uint32_t capn_in_invert: 1; + /** capn_sw : WT; bitpos: [12]; default: 0; + * Write 1 will trigger a software forced capture on channel 0 + */ + uint32_t capn_sw: 1; + uint32_t reserved_13: 19; + }; + uint32_t val; +} mcpwm_cap_chn_cfg_reg_t; + +/** Type of cap_chn register + * chn capture value status register + */ +typedef union { + struct { + /** capn_value : RO; bitpos: [31:0]; default: 0; + * Value of last capture on channel n + */ + uint32_t capn_value: 32; + }; + uint32_t val; +} mcpwm_cap_chn_reg_t; + +/** Type of cap_status register + * Edge of last capture trigger + */ +typedef union { + struct { + /** cap0_edge : RO; bitpos: [0]; default: 0; + * Edge of last capture trigger on channel 0, 0: posedge, 1: negedge + */ + uint32_t cap0_edge: 1; + /** cap1_edge : RO; bitpos: [1]; default: 0; + * Edge of last capture trigger on channel 1, 0: posedge, 1: negedge + */ + uint32_t cap1_edge: 1; + /** cap2_edge : RO; bitpos: [2]; default: 0; + * Edge of last capture trigger on channel 2, 0: posedge, 1: negedge + */ + uint32_t cap2_edge: 1; + uint32_t reserved_3: 29; + }; + uint32_t val; +} mcpwm_cap_status_reg_t; + + +/** Group: Enable update of active registers */ +/** Type of update_cfg register + * Enable update. + */ +typedef union { + struct { + /** global_up_en : R/W; bitpos: [0]; default: 1; + * The global enable of update of all active registers in MCPWM module + */ + uint32_t global_up_en: 1; + /** global_force_up : R/W; bitpos: [1]; default: 0; + * a toggle (software invert its value) will trigger a forced update of all active + * registers in MCPWM module + */ + uint32_t global_force_up: 1; + /** op0_up_en : R/W; bitpos: [2]; default: 1; + * When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 0 + * are enabled + */ + uint32_t op0_up_en: 1; + /** op0_force_up : R/W; bitpos: [3]; default: 0; + * a toggle (software invert its value) will trigger a forced update of active + * registers in PWM operator 0 + */ + uint32_t op0_force_up: 1; + /** op1_up_en : R/W; bitpos: [4]; default: 1; + * When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 1 + * are enabled + */ + uint32_t op1_up_en: 1; + /** op1_force_up : R/W; bitpos: [5]; default: 0; + * a toggle (software invert its value) will trigger a forced update of active + * registers in PWM operator 1 + */ + uint32_t op1_force_up: 1; + /** op2_up_en : R/W; bitpos: [6]; default: 1; + * When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 2 + * are enabled + */ + uint32_t op2_up_en: 1; + /** op2_force_up : R/W; bitpos: [7]; default: 0; + * a toggle (software invert its value) will trigger a forced update of active + * registers in PWM operator 2 + */ + uint32_t op2_force_up: 1; + uint32_t reserved_8: 24; + }; + uint32_t val; +} mcpwm_update_cfg_reg_t; + + +/** Group: Manage Interrupts */ +/** Type of int_ena register + * Interrupt enable bits + */ +typedef union { + struct { + /** timer0_stop_int_ena : R/W; bitpos: [0]; default: 0; + * The enable bit for the interrupt triggered when the timer 0 stops. + */ + uint32_t timer0_stop_int_ena: 1; + /** timer1_stop_int_ena : R/W; bitpos: [1]; default: 0; + * The enable bit for the interrupt triggered when the timer 1 stops. + */ + uint32_t timer1_stop_int_ena: 1; + /** timer2_stop_int_ena : R/W; bitpos: [2]; default: 0; + * The enable bit for the interrupt triggered when the timer 2 stops. + */ + uint32_t timer2_stop_int_ena: 1; + /** timer0_tez_int_ena : R/W; bitpos: [3]; default: 0; + * The enable bit for the interrupt triggered by a PWM timer 0 TEZ event. + */ + uint32_t timer0_tez_int_ena: 1; + /** timer1_tez_int_ena : R/W; bitpos: [4]; default: 0; + * The enable bit for the interrupt triggered by a PWM timer 1 TEZ event. + */ + uint32_t timer1_tez_int_ena: 1; + /** timer2_tez_int_ena : R/W; bitpos: [5]; default: 0; + * The enable bit for the interrupt triggered by a PWM timer 2 TEZ event. + */ + uint32_t timer2_tez_int_ena: 1; + /** timer0_tep_int_ena : R/W; bitpos: [6]; default: 0; + * The enable bit for the interrupt triggered by a PWM timer 0 TEP event. + */ + uint32_t timer0_tep_int_ena: 1; + /** timer1_tep_int_ena : R/W; bitpos: [7]; default: 0; + * The enable bit for the interrupt triggered by a PWM timer 1 TEP event. + */ + uint32_t timer1_tep_int_ena: 1; + /** timer2_tep_int_ena : R/W; bitpos: [8]; default: 0; + * The enable bit for the interrupt triggered by a PWM timer 2 TEP event. + */ + uint32_t timer2_tep_int_ena: 1; + /** fault0_int_ena : R/W; bitpos: [9]; default: 0; + * The enable bit for the interrupt triggered when fault_event0 starts. + */ + uint32_t fault0_int_ena: 1; + /** fault1_int_ena : R/W; bitpos: [10]; default: 0; + * The enable bit for the interrupt triggered when fault_event1 starts. + */ + uint32_t fault1_int_ena: 1; + /** fault2_int_ena : R/W; bitpos: [11]; default: 0; + * The enable bit for the interrupt triggered when fault_event2 starts. + */ + uint32_t fault2_int_ena: 1; + /** fault0_clr_int_ena : R/W; bitpos: [12]; default: 0; + * The enable bit for the interrupt triggered when fault_event0 ends. + */ + uint32_t fault0_clr_int_ena: 1; + /** fault1_clr_int_ena : R/W; bitpos: [13]; default: 0; + * The enable bit for the interrupt triggered when fault_event1 ends. + */ + uint32_t fault1_clr_int_ena: 1; + /** fault2_clr_int_ena : R/W; bitpos: [14]; default: 0; + * The enable bit for the interrupt triggered when fault_event2 ends. + */ + uint32_t fault2_clr_int_ena: 1; + /** op0_tea_int_ena : R/W; bitpos: [15]; default: 0; + * The enable bit for the interrupt triggered by a PWM operator 0 TEA event + */ + uint32_t op0_tea_int_ena: 1; + /** op1_tea_int_ena : R/W; bitpos: [16]; default: 0; + * The enable bit for the interrupt triggered by a PWM operator 1 TEA event + */ + uint32_t op1_tea_int_ena: 1; + /** op2_tea_int_ena : R/W; bitpos: [17]; default: 0; + * The enable bit for the interrupt triggered by a PWM operator 2 TEA event + */ + uint32_t op2_tea_int_ena: 1; + /** op0_teb_int_ena : R/W; bitpos: [18]; default: 0; + * The enable bit for the interrupt triggered by a PWM operator 0 TEB event + */ + uint32_t op0_teb_int_ena: 1; + /** op1_teb_int_ena : R/W; bitpos: [19]; default: 0; + * The enable bit for the interrupt triggered by a PWM operator 1 TEB event + */ + uint32_t op1_teb_int_ena: 1; + /** op2_teb_int_ena : R/W; bitpos: [20]; default: 0; + * The enable bit for the interrupt triggered by a PWM operator 2 TEB event + */ + uint32_t op2_teb_int_ena: 1; + /** fh0_cbc_int_ena : R/W; bitpos: [21]; default: 0; + * The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0. + */ + uint32_t fh0_cbc_int_ena: 1; + /** fh1_cbc_int_ena : R/W; bitpos: [22]; default: 0; + * The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1. + */ + uint32_t fh1_cbc_int_ena: 1; + /** fh2_cbc_int_ena : R/W; bitpos: [23]; default: 0; + * The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2. + */ + uint32_t fh2_cbc_int_ena: 1; + /** fh0_ost_int_ena : R/W; bitpos: [24]; default: 0; + * The enable bit for the interrupt triggered by a one-shot mode action on PWM0. + */ + uint32_t fh0_ost_int_ena: 1; + /** fh1_ost_int_ena : R/W; bitpos: [25]; default: 0; + * The enable bit for the interrupt triggered by a one-shot mode action on PWM1. + */ + uint32_t fh1_ost_int_ena: 1; + /** fh2_ost_int_ena : R/W; bitpos: [26]; default: 0; + * The enable bit for the interrupt triggered by a one-shot mode action on PWM2. + */ + uint32_t fh2_ost_int_ena: 1; + /** cap0_int_ena : R/W; bitpos: [27]; default: 0; + * The enable bit for the interrupt triggered by capture on channel 0. + */ + uint32_t cap0_int_ena: 1; + /** cap1_int_ena : R/W; bitpos: [28]; default: 0; + * The enable bit for the interrupt triggered by capture on channel 1. + */ + uint32_t cap1_int_ena: 1; + /** cap2_int_ena : R/W; bitpos: [29]; default: 0; + * The enable bit for the interrupt triggered by capture on channel 2. + */ + uint32_t cap2_int_ena: 1; + uint32_t reserved_30: 2; + }; + uint32_t val; +} mcpwm_int_ena_reg_t; + +/** Type of int_raw register + * Raw interrupt status + */ +typedef union { + struct { + /** timer0_stop_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * The raw status bit for the interrupt triggered when the timer 0 stops. + */ + uint32_t timer0_stop_int_raw: 1; + /** timer1_stop_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * The raw status bit for the interrupt triggered when the timer 1 stops. + */ + uint32_t timer1_stop_int_raw: 1; + /** timer2_stop_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The raw status bit for the interrupt triggered when the timer 2 stops. + */ + uint32_t timer2_stop_int_raw: 1; + /** timer0_tez_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * The raw status bit for the interrupt triggered by a PWM timer 0 TEZ event. + */ + uint32_t timer0_tez_int_raw: 1; + /** timer1_tez_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * The raw status bit for the interrupt triggered by a PWM timer 1 TEZ event. + */ + uint32_t timer1_tez_int_raw: 1; + /** timer2_tez_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * The raw status bit for the interrupt triggered by a PWM timer 2 TEZ event. + */ + uint32_t timer2_tez_int_raw: 1; + /** timer0_tep_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * The raw status bit for the interrupt triggered by a PWM timer 0 TEP event. + */ + uint32_t timer0_tep_int_raw: 1; + /** timer1_tep_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + * The raw status bit for the interrupt triggered by a PWM timer 1 TEP event. + */ + uint32_t timer1_tep_int_raw: 1; + /** timer2_tep_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * The raw status bit for the interrupt triggered by a PWM timer 2 TEP event. + */ + uint32_t timer2_tep_int_raw: 1; + /** fault0_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * The raw status bit for the interrupt triggered when fault_event0 starts. + */ + uint32_t fault0_int_raw: 1; + /** fault1_int_raw : R/WTC/SS; bitpos: [10]; default: 0; + * The raw status bit for the interrupt triggered when fault_event1 starts. + */ + uint32_t fault1_int_raw: 1; + /** fault2_int_raw : R/WTC/SS; bitpos: [11]; default: 0; + * The raw status bit for the interrupt triggered when fault_event2 starts. + */ + uint32_t fault2_int_raw: 1; + /** fault0_clr_int_raw : R/WTC/SS; bitpos: [12]; default: 0; + * The raw status bit for the interrupt triggered when fault_event0 ends. + */ + uint32_t fault0_clr_int_raw: 1; + /** fault1_clr_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + * The raw status bit for the interrupt triggered when fault_event1 ends. + */ + uint32_t fault1_clr_int_raw: 1; + /** fault2_clr_int_raw : R/WTC/SS; bitpos: [14]; default: 0; + * The raw status bit for the interrupt triggered when fault_event2 ends. + */ + uint32_t fault2_clr_int_raw: 1; + /** op0_tea_int_raw : R/WTC/SS; bitpos: [15]; default: 0; + * The raw status bit for the interrupt triggered by a PWM operator 0 TEA event + */ + uint32_t op0_tea_int_raw: 1; + /** op1_tea_int_raw : R/WTC/SS; bitpos: [16]; default: 0; + * The raw status bit for the interrupt triggered by a PWM operator 1 TEA event + */ + uint32_t op1_tea_int_raw: 1; + /** op2_tea_int_raw : R/WTC/SS; bitpos: [17]; default: 0; + * The raw status bit for the interrupt triggered by a PWM operator 2 TEA event + */ + uint32_t op2_tea_int_raw: 1; + /** op0_teb_int_raw : R/WTC/SS; bitpos: [18]; default: 0; + * The raw status bit for the interrupt triggered by a PWM operator 0 TEB event + */ + uint32_t op0_teb_int_raw: 1; + /** op1_teb_int_raw : R/WTC/SS; bitpos: [19]; default: 0; + * The raw status bit for the interrupt triggered by a PWM operator 1 TEB event + */ + uint32_t op1_teb_int_raw: 1; + /** op2_teb_int_raw : R/WTC/SS; bitpos: [20]; default: 0; + * The raw status bit for the interrupt triggered by a PWM operator 2 TEB event + */ + uint32_t op2_teb_int_raw: 1; + /** fh0_cbc_int_raw : R/WTC/SS; bitpos: [21]; default: 0; + * The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on + * PWM0. + */ + uint32_t fh0_cbc_int_raw: 1; + /** fh1_cbc_int_raw : R/WTC/SS; bitpos: [22]; default: 0; + * The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on + * PWM1. + */ + uint32_t fh1_cbc_int_raw: 1; + /** fh2_cbc_int_raw : R/WTC/SS; bitpos: [23]; default: 0; + * The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on + * PWM2. + */ + uint32_t fh2_cbc_int_raw: 1; + /** fh0_ost_int_raw : R/WTC/SS; bitpos: [24]; default: 0; + * The raw status bit for the interrupt triggered by a one-shot mode action on PWM0. + */ + uint32_t fh0_ost_int_raw: 1; + /** fh1_ost_int_raw : R/WTC/SS; bitpos: [25]; default: 0; + * The raw status bit for the interrupt triggered by a one-shot mode action on PWM1. + */ + uint32_t fh1_ost_int_raw: 1; + /** fh2_ost_int_raw : R/WTC/SS; bitpos: [26]; default: 0; + * The raw status bit for the interrupt triggered by a one-shot mode action on PWM2. + */ + uint32_t fh2_ost_int_raw: 1; + /** cap0_int_raw : R/WTC/SS; bitpos: [27]; default: 0; + * The raw status bit for the interrupt triggered by capture on channel 0. + */ + uint32_t cap0_int_raw: 1; + /** cap1_int_raw : R/WTC/SS; bitpos: [28]; default: 0; + * The raw status bit for the interrupt triggered by capture on channel 1. + */ + uint32_t cap1_int_raw: 1; + /** cap2_int_raw : R/WTC/SS; bitpos: [29]; default: 0; + * The raw status bit for the interrupt triggered by capture on channel 2. + */ + uint32_t cap2_int_raw: 1; + uint32_t reserved_30: 2; + }; + uint32_t val; +} mcpwm_int_raw_reg_t; + +/** Type of int_st register + * Masked interrupt status + */ +typedef union { + struct { + /** timer0_stop_int_st : RO; bitpos: [0]; default: 0; + * The masked status bit for the interrupt triggered when the timer 0 stops. + */ + uint32_t timer0_stop_int_st: 1; + /** timer1_stop_int_st : RO; bitpos: [1]; default: 0; + * The masked status bit for the interrupt triggered when the timer 1 stops. + */ + uint32_t timer1_stop_int_st: 1; + /** timer2_stop_int_st : RO; bitpos: [2]; default: 0; + * The masked status bit for the interrupt triggered when the timer 2 stops. + */ + uint32_t timer2_stop_int_st: 1; + /** timer0_tez_int_st : RO; bitpos: [3]; default: 0; + * The masked status bit for the interrupt triggered by a PWM timer 0 TEZ event. + */ + uint32_t timer0_tez_int_st: 1; + /** timer1_tez_int_st : RO; bitpos: [4]; default: 0; + * The masked status bit for the interrupt triggered by a PWM timer 1 TEZ event. + */ + uint32_t timer1_tez_int_st: 1; + /** timer2_tez_int_st : RO; bitpos: [5]; default: 0; + * The masked status bit for the interrupt triggered by a PWM timer 2 TEZ event. + */ + uint32_t timer2_tez_int_st: 1; + /** timer0_tep_int_st : RO; bitpos: [6]; default: 0; + * The masked status bit for the interrupt triggered by a PWM timer 0 TEP event. + */ + uint32_t timer0_tep_int_st: 1; + /** timer1_tep_int_st : RO; bitpos: [7]; default: 0; + * The masked status bit for the interrupt triggered by a PWM timer 1 TEP event. + */ + uint32_t timer1_tep_int_st: 1; + /** timer2_tep_int_st : RO; bitpos: [8]; default: 0; + * The masked status bit for the interrupt triggered by a PWM timer 2 TEP event. + */ + uint32_t timer2_tep_int_st: 1; + /** fault0_int_st : RO; bitpos: [9]; default: 0; + * The masked status bit for the interrupt triggered when fault_event0 starts. + */ + uint32_t fault0_int_st: 1; + /** fault1_int_st : RO; bitpos: [10]; default: 0; + * The masked status bit for the interrupt triggered when fault_event1 starts. + */ + uint32_t fault1_int_st: 1; + /** fault2_int_st : RO; bitpos: [11]; default: 0; + * The masked status bit for the interrupt triggered when fault_event2 starts. + */ + uint32_t fault2_int_st: 1; + /** fault0_clr_int_st : RO; bitpos: [12]; default: 0; + * The masked status bit for the interrupt triggered when fault_event0 ends. + */ + uint32_t fault0_clr_int_st: 1; + /** fault1_clr_int_st : RO; bitpos: [13]; default: 0; + * The masked status bit for the interrupt triggered when fault_event1 ends. + */ + uint32_t fault1_clr_int_st: 1; + /** fault2_clr_int_st : RO; bitpos: [14]; default: 0; + * The masked status bit for the interrupt triggered when fault_event2 ends. + */ + uint32_t fault2_clr_int_st: 1; + /** op0_tea_int_st : RO; bitpos: [15]; default: 0; + * The masked status bit for the interrupt triggered by a PWM operator 0 TEA event + */ + uint32_t op0_tea_int_st: 1; + /** op1_tea_int_st : RO; bitpos: [16]; default: 0; + * The masked status bit for the interrupt triggered by a PWM operator 1 TEA event + */ + uint32_t op1_tea_int_st: 1; + /** op2_tea_int_st : RO; bitpos: [17]; default: 0; + * The masked status bit for the interrupt triggered by a PWM operator 2 TEA event + */ + uint32_t op2_tea_int_st: 1; + /** op0_teb_int_st : RO; bitpos: [18]; default: 0; + * The masked status bit for the interrupt triggered by a PWM operator 0 TEB event + */ + uint32_t op0_teb_int_st: 1; + /** op1_teb_int_st : RO; bitpos: [19]; default: 0; + * The masked status bit for the interrupt triggered by a PWM operator 1 TEB event + */ + uint32_t op1_teb_int_st: 1; + /** op2_teb_int_st : RO; bitpos: [20]; default: 0; + * The masked status bit for the interrupt triggered by a PWM operator 2 TEB event + */ + uint32_t op2_teb_int_st: 1; + /** fh0_cbc_int_st : RO; bitpos: [21]; default: 0; + * The masked status bit for the interrupt triggered by a cycle-by-cycle mode action + * on PWM0. + */ + uint32_t fh0_cbc_int_st: 1; + /** fh1_cbc_int_st : RO; bitpos: [22]; default: 0; + * The masked status bit for the interrupt triggered by a cycle-by-cycle mode action + * on PWM1. + */ + uint32_t fh1_cbc_int_st: 1; + /** fh2_cbc_int_st : RO; bitpos: [23]; default: 0; + * The masked status bit for the interrupt triggered by a cycle-by-cycle mode action + * on PWM2. + */ + uint32_t fh2_cbc_int_st: 1; + /** fh0_ost_int_st : RO; bitpos: [24]; default: 0; + * The masked status bit for the interrupt triggered by a one-shot mode action on PWM0. + */ + uint32_t fh0_ost_int_st: 1; + /** fh1_ost_int_st : RO; bitpos: [25]; default: 0; + * The masked status bit for the interrupt triggered by a one-shot mode action on PWM1. + */ + uint32_t fh1_ost_int_st: 1; + /** fh2_ost_int_st : RO; bitpos: [26]; default: 0; + * The masked status bit for the interrupt triggered by a one-shot mode action on PWM2. + */ + uint32_t fh2_ost_int_st: 1; + /** cap0_int_st : RO; bitpos: [27]; default: 0; + * The masked status bit for the interrupt triggered by capture on channel 0. + */ + uint32_t cap0_int_st: 1; + /** cap1_int_st : RO; bitpos: [28]; default: 0; + * The masked status bit for the interrupt triggered by capture on channel 1. + */ + uint32_t cap1_int_st: 1; + /** cap2_int_st : RO; bitpos: [29]; default: 0; + * The masked status bit for the interrupt triggered by capture on channel 2. + */ + uint32_t cap2_int_st: 1; + uint32_t reserved_30: 2; + }; + uint32_t val; +} mcpwm_int_st_reg_t; + +/** Type of int_clr register + * Interrupt clear bits + */ +typedef union { + struct { + /** timer0_stop_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear the interrupt triggered when the timer 0 stops. + */ + uint32_t timer0_stop_int_clr: 1; + /** timer1_stop_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear the interrupt triggered when the timer 1 stops. + */ + uint32_t timer1_stop_int_clr: 1; + /** timer2_stop_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear the interrupt triggered when the timer 2 stops. + */ + uint32_t timer2_stop_int_clr: 1; + /** timer0_tez_int_clr : WT; bitpos: [3]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM timer 0 TEZ event. + */ + uint32_t timer0_tez_int_clr: 1; + /** timer1_tez_int_clr : WT; bitpos: [4]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM timer 1 TEZ event. + */ + uint32_t timer1_tez_int_clr: 1; + /** timer2_tez_int_clr : WT; bitpos: [5]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM timer 2 TEZ event. + */ + uint32_t timer2_tez_int_clr: 1; + /** timer0_tep_int_clr : WT; bitpos: [6]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM timer 0 TEP event. + */ + uint32_t timer0_tep_int_clr: 1; + /** timer1_tep_int_clr : WT; bitpos: [7]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM timer 1 TEP event. + */ + uint32_t timer1_tep_int_clr: 1; + /** timer2_tep_int_clr : WT; bitpos: [8]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM timer 2 TEP event. + */ + uint32_t timer2_tep_int_clr: 1; + /** fault0_int_clr : WT; bitpos: [9]; default: 0; + * Set this bit to clear the interrupt triggered when fault_event0 starts. + */ + uint32_t fault0_int_clr: 1; + /** fault1_int_clr : WT; bitpos: [10]; default: 0; + * Set this bit to clear the interrupt triggered when fault_event1 starts. + */ + uint32_t fault1_int_clr: 1; + /** fault2_int_clr : WT; bitpos: [11]; default: 0; + * Set this bit to clear the interrupt triggered when fault_event2 starts. + */ + uint32_t fault2_int_clr: 1; + /** fault0_clr_int_clr : WT; bitpos: [12]; default: 0; + * Set this bit to clear the interrupt triggered when fault_event0 ends. + */ + uint32_t fault0_clr_int_clr: 1; + /** fault1_clr_int_clr : WT; bitpos: [13]; default: 0; + * Set this bit to clear the interrupt triggered when fault_event1 ends. + */ + uint32_t fault1_clr_int_clr: 1; + /** fault2_clr_int_clr : WT; bitpos: [14]; default: 0; + * Set this bit to clear the interrupt triggered when fault_event2 ends. + */ + uint32_t fault2_clr_int_clr: 1; + /** op0_tea_int_clr : WT; bitpos: [15]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM operator 0 TEA event + */ + uint32_t op0_tea_int_clr: 1; + /** op1_tea_int_clr : WT; bitpos: [16]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM operator 1 TEA event + */ + uint32_t op1_tea_int_clr: 1; + /** op2_tea_int_clr : WT; bitpos: [17]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM operator 2 TEA event + */ + uint32_t op2_tea_int_clr: 1; + /** op0_teb_int_clr : WT; bitpos: [18]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM operator 0 TEB event + */ + uint32_t op0_teb_int_clr: 1; + /** op1_teb_int_clr : WT; bitpos: [19]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM operator 1 TEB event + */ + uint32_t op1_teb_int_clr: 1; + /** op2_teb_int_clr : WT; bitpos: [20]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM operator 2 TEB event + */ + uint32_t op2_teb_int_clr: 1; + /** fh0_cbc_int_clr : WT; bitpos: [21]; default: 0; + * Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on + * PWM0. + */ + uint32_t fh0_cbc_int_clr: 1; + /** fh1_cbc_int_clr : WT; bitpos: [22]; default: 0; + * Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on + * PWM1. + */ + uint32_t fh1_cbc_int_clr: 1; + /** fh2_cbc_int_clr : WT; bitpos: [23]; default: 0; + * Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on + * PWM2. + */ + uint32_t fh2_cbc_int_clr: 1; + /** fh0_ost_int_clr : WT; bitpos: [24]; default: 0; + * Set this bit to clear the interrupt triggered by a one-shot mode action on PWM0. + */ + uint32_t fh0_ost_int_clr: 1; + /** fh1_ost_int_clr : WT; bitpos: [25]; default: 0; + * Set this bit to clear the interrupt triggered by a one-shot mode action on PWM1. + */ + uint32_t fh1_ost_int_clr: 1; + /** fh2_ost_int_clr : WT; bitpos: [26]; default: 0; + * Set this bit to clear the interrupt triggered by a one-shot mode action on PWM2. + */ + uint32_t fh2_ost_int_clr: 1; + /** cap0_int_clr : WT; bitpos: [27]; default: 0; + * Set this bit to clear the interrupt triggered by capture on channel 0. + */ + uint32_t cap0_int_clr: 1; + /** cap1_int_clr : WT; bitpos: [28]; default: 0; + * Set this bit to clear the interrupt triggered by capture on channel 1. + */ + uint32_t cap1_int_clr: 1; + /** cap2_int_clr : WT; bitpos: [29]; default: 0; + * Set this bit to clear the interrupt triggered by capture on channel 2. + */ + uint32_t cap2_int_clr: 1; + uint32_t reserved_30: 2; + }; + uint32_t val; +} mcpwm_int_clr_reg_t; + + +/** Group: MCMCPWM APB configuration register */ +/** Type of clk register + * MCPWM APB configuration register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 0; + * Force clock on for this register file + */ + uint32_t clk_en: 1; + uint32_t reserved_1: 31; + }; + uint32_t val; +} mcpwm_clk_reg_t; + + +/** Group: Version Register */ +/** Type of version register + * Version register. + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 34632240; + * Version of this register file + */ + uint32_t date: 28; + uint32_t reserved_28: 4; + }; + uint32_t val; +} mcpwm_version_reg_t; + + +typedef struct { + mcpwm_timer_cfg0_reg_t timer_cfg0; + mcpwm_timer_cfg1_reg_t timer_cfg1; + mcpwm_timer_sync_reg_t timer_sync; + mcpwm_timer_status_reg_t timer_status; +} mcpwm_timer_regs_t; + +typedef struct { + mcpwm_gen_stmp_cfg_reg_t gen_stmp_cfg; + mcpwm_gen_tstmp_reg_t timestamp[2]; + mcpwm_gen_cfg0_reg_t gen_cfg0; + mcpwm_gen_force_reg_t gen_force; + mcpwm_gen_reg_t generator[2]; + mcpwm_dt_cfg_reg_t dt_cfg; + mcpwm_dt_fed_cfg_reg_t dt_fed_cfg; + mcpwm_dt_red_cfg_reg_t dt_red_cfg; + mcpwm_carrier_cfg_reg_t carrier_cfg; + mcpwm_fh_cfg0_reg_t fh_cfg0; + mcpwm_fh_cfg1_reg_t fh_cfg1; + mcpwm_fh_status_reg_t fh_status; +} mcpwm_operator_reg_t; + +typedef struct { + volatile mcpwm_clk_cfg_reg_t clk_cfg; + volatile mcpwm_timer_regs_t timer[3]; + volatile mcpwm_timer_synci_cfg_reg_t timer_synci_cfg; + volatile mcpwm_operator_timersel_reg_t operator_timersel; + volatile mcpwm_operator_reg_t operator[3]; + volatile mcpwm_fault_detect_reg_t fault_detect; + volatile mcpwm_cap_timer_cfg_reg_t cap_timer_cfg; + volatile mcpwm_cap_timer_phase_reg_t cap_timer_phase; + volatile mcpwm_cap_chn_cfg_reg_t cap_chn_cfg[3]; + volatile mcpwm_cap_chn_reg_t cap_chn[3]; + volatile mcpwm_cap_status_reg_t cap_status; + volatile mcpwm_update_cfg_reg_t update_cfg; + volatile mcpwm_int_ena_reg_t int_ena; + volatile mcpwm_int_raw_reg_t int_raw; + volatile mcpwm_int_st_reg_t int_st; + volatile mcpwm_int_clr_reg_t int_clr; + volatile mcpwm_clk_reg_t clk; + volatile mcpwm_version_reg_t version; } mcpwm_dev_t; + extern mcpwm_dev_t MCPWM0; extern mcpwm_dev_t MCPWM1; + +#ifndef __cplusplus +_Static_assert(sizeof(mcpwm_dev_t) == 0x128, "Invalid size of mcpwm_dev_t structure"); +#endif + #ifdef __cplusplus } #endif - - - -#endif /*_SOC_MCPWM_STRUCT_H_ */