From 80315b77a006e0aa04d8c47be273397d8c98925e Mon Sep 17 00:00:00 2001 From: "Michael (XIAO Xufeng)" Date: Mon, 6 Mar 2023 11:46:19 +0800 Subject: [PATCH 1/5] bootloader: fix analog reset on C6 and H2 --- .../src/esp32c6/bootloader_esp32c6.c | 31 +++---------------- .../src/esp32c6/bootloader_soc.c | 21 ++++++++----- .../src/esp32h2/bootloader_esp32h2.c | 31 +++---------------- .../src/esp32h2/bootloader_soc.c | 18 +++++------ .../src/esp32h4/bootloader_esp32h4.c | 2 +- .../src/esp32h4/bootloader_soc.c | 2 +- .../esp32c6/include/soc/lp_analog_peri_reg.h | 4 +-- .../esp32h2/include/soc/lp_analog_peri_reg.h | 4 +-- .../esp32h4/include/rev1/soc/rtc_cntl_reg.h | 2 +- .../esp32h4/include/rev2/soc/rtc_cntl_reg.h | 2 +- 10 files changed, 37 insertions(+), 80 deletions(-) diff --git a/components/bootloader_support/src/esp32c6/bootloader_esp32c6.c b/components/bootloader_support/src/esp32c6/bootloader_esp32c6.c index e1eec5bcd808..1e2b4ce501f7 100644 --- a/components/bootloader_support/src/esp32c6/bootloader_esp32c6.c +++ b/components/bootloader_support/src/esp32c6/bootloader_esp32c6.c @@ -103,33 +103,10 @@ static inline void bootloader_hardware_init(void) static inline void bootloader_ana_reset_config(void) { - // TODO: IDF-5990 copied from C3, need update - // Have removed bootloader_ana_super_wdt_reset_config for now; can be evaluated later to see whether needs to add it back - /* - For origin chip & ECO1: only support swt reset; - For ECO2: fix brownout reset bug, support swt & brownout reset; - For ECO3: fix clock glitch reset bug, support all reset, include: swt & brownout & clock glitch reset. - */ - uint8_t chip_version = efuse_hal_get_minor_chip_version(); - switch (chip_version) { - case 0: - case 1: - //Disable BOR and GLITCH reset - bootloader_ana_bod_reset_config(false); - bootloader_ana_clock_glitch_reset_config(false); - break; - case 2: - //Enable BOR reset. Disable GLITCH reset - bootloader_ana_bod_reset_config(true); - bootloader_ana_clock_glitch_reset_config(false); - break; - case 3: - default: - //Enable BOR, and GLITCH reset - bootloader_ana_bod_reset_config(true); - bootloader_ana_clock_glitch_reset_config(true); - break; - } + //Enable super WDT reset. + bootloader_ana_super_wdt_reset_config(true); + //Enable BOD reset + bootloader_ana_bod_reset_config(true); } esp_err_t bootloader_init(void) diff --git a/components/bootloader_support/src/esp32c6/bootloader_soc.c b/components/bootloader_support/src/esp32c6/bootloader_soc.c index 77a8d2176a73..66358dd3fa0a 100644 --- a/components/bootloader_support/src/esp32c6/bootloader_soc.c +++ b/components/bootloader_support/src/esp32c6/bootloader_soc.c @@ -1,15 +1,24 @@ /* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ #include +#include #include "soc/soc.h" #include "soc/lp_analog_peri_reg.h" +void bootloader_ana_super_wdt_reset_config(bool enable) +{ + //C6 doesn't support bypass super WDT reset + assert(enable); + REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_SUPER_WDT_RST); +} + void bootloader_ana_bod_reset_config(bool enable) { - REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_BOR_RST); + REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_BOD_RST); + if (enable) { REG_SET_BIT(LP_ANALOG_PERI_LP_ANA_BOD_MODE1_CNTL_REG, LP_ANALOG_PERI_LP_ANA_BOD_MODE1_RESET_ENA); } else { @@ -17,12 +26,8 @@ void bootloader_ana_bod_reset_config(bool enable) } } +//Not supported but common bootloader calls the function. Do nothing void bootloader_ana_clock_glitch_reset_config(bool enable) { - REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_GLITCH_RST); - if (enable) { - REG_SET_BIT(LP_ANALOG_PERI_LP_ANA_CK_GLITCH_CNTL_REG, LP_ANALOG_PERI_LP_ANA_CK_GLITCH_RESET_ENA); - } else { - REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_CK_GLITCH_CNTL_REG, LP_ANALOG_PERI_LP_ANA_CK_GLITCH_RESET_ENA); - } + (void)enable; } diff --git a/components/bootloader_support/src/esp32h2/bootloader_esp32h2.c b/components/bootloader_support/src/esp32h2/bootloader_esp32h2.c index 5de830031f24..6fcdfcc8c46b 100644 --- a/components/bootloader_support/src/esp32h2/bootloader_esp32h2.c +++ b/components/bootloader_support/src/esp32h2/bootloader_esp32h2.c @@ -93,33 +93,10 @@ static inline void bootloader_hardware_init(void) static inline void bootloader_ana_reset_config(void) { - // TODO: IDF-5990 copied from C6, need update - // Have removed bootloader_ana_super_wdt_reset_config for now; can be evaluated later to see whether needs to add it back - /* - For origin chip & ECO1: only support swt reset; - For ECO2: fix brownout reset bug, support swt & brownout reset; - For ECO3: fix clock glitch reset bug, support all reset, include: swt & brownout & clock glitch reset. - */ - uint8_t chip_version = efuse_hal_get_minor_chip_version(); - switch (chip_version) { - case 0: - case 1: - //Disable BOR and GLITCH reset - bootloader_ana_bod_reset_config(false); - bootloader_ana_clock_glitch_reset_config(false); - break; - case 2: - //Enable BOR reset. Disable GLITCH reset - bootloader_ana_bod_reset_config(true); - bootloader_ana_clock_glitch_reset_config(false); - break; - case 3: - default: - //Enable BOR, and GLITCH reset - bootloader_ana_bod_reset_config(true); - bootloader_ana_clock_glitch_reset_config(true); - break; - } + //Enable super WDT reset. + bootloader_ana_super_wdt_reset_config(true); + //Enable BOD reset + bootloader_ana_bod_reset_config(true); } esp_err_t bootloader_init(void) diff --git a/components/bootloader_support/src/esp32h2/bootloader_soc.c b/components/bootloader_support/src/esp32h2/bootloader_soc.c index 21334dd9ecf7..508e0b6a7bff 100644 --- a/components/bootloader_support/src/esp32h2/bootloader_soc.c +++ b/components/bootloader_support/src/esp32h2/bootloader_soc.c @@ -1,20 +1,22 @@ /* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ #include -#include "soc/soc.h" #include "soc/lp_analog_peri_reg.h" void bootloader_ana_super_wdt_reset_config(bool enable) { - // ESP32H2 has removed the super wdt + //H2 doesn't support bypass super WDT reset + assert(enable); + REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_SUPER_WDT_RST); } void bootloader_ana_bod_reset_config(bool enable) { - REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_BOR_RST); + REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_BOD_RST); + if (enable) { REG_SET_BIT(LP_ANALOG_PERI_LP_ANA_BOD_MODE1_CNTL_REG, LP_ANALOG_PERI_LP_ANA_BOD_MODE1_RESET_ENA); } else { @@ -22,12 +24,8 @@ void bootloader_ana_bod_reset_config(bool enable) } } +//Not supported but common bootloader calls the function. Do nothing void bootloader_ana_clock_glitch_reset_config(bool enable) { - REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_GLITCH_RST); - if (enable) { - REG_SET_BIT(LP_ANALOG_PERI_LP_ANA_CK_GLITCH_CNTL_REG, LP_ANALOG_PERI_LP_ANA_CK_GLITCH_RESET_ENA); - } else { - REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_CK_GLITCH_CNTL_REG, LP_ANALOG_PERI_LP_ANA_CK_GLITCH_RESET_ENA); - } + (void)enable; } diff --git a/components/bootloader_support/src/esp32h4/bootloader_esp32h4.c b/components/bootloader_support/src/esp32h4/bootloader_esp32h4.c index 7b48fcc75659..50653dbd8cb0 100644 --- a/components/bootloader_support/src/esp32h4/bootloader_esp32h4.c +++ b/components/bootloader_support/src/esp32h4/bootloader_esp32h4.c @@ -85,7 +85,7 @@ static inline void bootloader_hardware_init(void) static inline void bootloader_ana_reset_config(void) { - //Enable WDT, BOR, and GLITCH reset + //Enable WDT, BOD, and GLITCH reset bootloader_ana_super_wdt_reset_config(true); bootloader_ana_bod_reset_config(true); bootloader_ana_clock_glitch_reset_config(true); diff --git a/components/bootloader_support/src/esp32h4/bootloader_soc.c b/components/bootloader_support/src/esp32h4/bootloader_soc.c index 7104528a5850..a8e6f45d9df8 100644 --- a/components/bootloader_support/src/esp32h4/bootloader_soc.c +++ b/components/bootloader_support/src/esp32h4/bootloader_soc.c @@ -20,7 +20,7 @@ void bootloader_ana_super_wdt_reset_config(bool enable) void bootloader_ana_bod_reset_config(bool enable) { - REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_BOR_RST); + REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_BOD_RST); if (enable) { REG_SET_BIT(RTC_CNTL_BROWN_OUT_REG, RTC_CNTL_BROWN_OUT_ANA_RST_EN); diff --git a/components/soc/esp32c6/include/soc/lp_analog_peri_reg.h b/components/soc/esp32c6/include/soc/lp_analog_peri_reg.h index 25848608d664..84f2f919e692 100644 --- a/components/soc/esp32c6/include/soc/lp_analog_peri_reg.h +++ b/components/soc/esp32c6/include/soc/lp_analog_peri_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -109,7 +109,7 @@ extern "C" { #define LP_ANALOG_PERI_LP_ANA_ANA_FIB_ENA_S 0 #define LP_ANALOG_PERI_LP_ANA_FIB_GLITCH_RST BIT(0) -#define LP_ANALOG_PERI_LP_ANA_FIB_BOR_RST BIT(1) +#define LP_ANALOG_PERI_LP_ANA_FIB_BOD_RST BIT(1) #define LP_ANALOG_PERI_LP_ANA_FIB_SUPER_WDT_RST BIT(2) /** LP_ANALOG_PERI_LP_ANA_INT_RAW_REG register diff --git a/components/soc/esp32h2/include/soc/lp_analog_peri_reg.h b/components/soc/esp32h2/include/soc/lp_analog_peri_reg.h index d44ae667aeef..85277c4d350c 100644 --- a/components/soc/esp32h2/include/soc/lp_analog_peri_reg.h +++ b/components/soc/esp32h2/include/soc/lp_analog_peri_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -234,7 +234,7 @@ extern "C" { #define LP_ANALOG_PERI_LP_ANA_ANA_FIB_ENA_S 0 #define LP_ANALOG_PERI_LP_ANA_FIB_GLITCH_RST BIT(0) -#define LP_ANALOG_PERI_LP_ANA_FIB_BOR_RST BIT(1) +#define LP_ANALOG_PERI_LP_ANA_FIB_BOD_RST BIT(1) #define LP_ANALOG_PERI_LP_ANA_FIB_SUPER_WDT_RST BIT(2) /** LP_ANALOG_PERI_LP_ANA_INT_RAW_REG register diff --git a/components/soc/esp32h4/include/rev1/soc/rtc_cntl_reg.h b/components/soc/esp32h4/include/rev1/soc/rtc_cntl_reg.h index 34d6c7c5d473..f079d1240cec 100644 --- a/components/soc/esp32h4/include/rev1/soc/rtc_cntl_reg.h +++ b/components/soc/esp32h4/include/rev1/soc/rtc_cntl_reg.h @@ -2727,7 +2727,7 @@ extern "C" { #define RTC_CNTL_FIB_SEL_S 0 #define RTC_CNTL_FIB_GLITCH_RST BIT(0) -#define RTC_CNTL_FIB_BOR_RST BIT(1) +#define RTC_CNTL_FIB_BOD_RST BIT(1) #define RTC_CNTL_FIB_SUPER_WDT_RST BIT(2) #define RTC_CNTL_GPIO_WAKEUP_REG (DR_REG_RTCCNTL_BASE + 0x013C) diff --git a/components/soc/esp32h4/include/rev2/soc/rtc_cntl_reg.h b/components/soc/esp32h4/include/rev2/soc/rtc_cntl_reg.h index 8226d49e4f6b..c2e6c19f9a2f 100644 --- a/components/soc/esp32h4/include/rev2/soc/rtc_cntl_reg.h +++ b/components/soc/esp32h4/include/rev2/soc/rtc_cntl_reg.h @@ -3475,7 +3475,7 @@ extern "C" { #define RTC_CNTL_FIB_SEL_S 0 #define RTC_CNTL_FIB_GLITCH_RST BIT(0) -#define RTC_CNTL_FIB_BOR_RST BIT(1) +#define RTC_CNTL_FIB_BOD_RST BIT(1) #define RTC_CNTL_FIB_SUPER_WDT_RST BIT(2) /** RTC_CNTL_GPIO_WAKEUP_REG register From 113e4dc5201909fdfd93daf7440a39b866d1920d Mon Sep 17 00:00:00 2001 From: Xiao Xufeng Date: Tue, 7 Mar 2023 11:12:10 +0800 Subject: [PATCH 2/5] bootloader: removed unavailable rtc features --- .../bootloader_support/src/esp32/bootloader_soc.c | 12 ++---------- .../bootloader_support/src/esp32s2/bootloader_soc.c | 12 ++---------- 2 files changed, 4 insertions(+), 20 deletions(-) diff --git a/components/bootloader_support/src/esp32/bootloader_soc.c b/components/bootloader_support/src/esp32/bootloader_soc.c index 242a5755086e..31525ef277cc 100644 --- a/components/bootloader_support/src/esp32/bootloader_soc.c +++ b/components/bootloader_support/src/esp32/bootloader_soc.c @@ -3,18 +3,10 @@ * * SPDX-License-Identifier: Apache-2.0 */ -#include - -void bootloader_ana_super_wdt_reset_config(bool enable) -{ - (void)enable; -} -void bootloader_ana_bod_reset_config(bool enable) -{ - (void)enable; -} +#include +//Not supported but common bootloader calls the function. Do nothing void bootloader_ana_clock_glitch_reset_config(bool enable) { (void)enable; diff --git a/components/bootloader_support/src/esp32s2/bootloader_soc.c b/components/bootloader_support/src/esp32s2/bootloader_soc.c index 242a5755086e..31525ef277cc 100644 --- a/components/bootloader_support/src/esp32s2/bootloader_soc.c +++ b/components/bootloader_support/src/esp32s2/bootloader_soc.c @@ -3,18 +3,10 @@ * * SPDX-License-Identifier: Apache-2.0 */ -#include - -void bootloader_ana_super_wdt_reset_config(bool enable) -{ - (void)enable; -} -void bootloader_ana_bod_reset_config(bool enable) -{ - (void)enable; -} +#include +//Not supported but common bootloader calls the function. Do nothing void bootloader_ana_clock_glitch_reset_config(bool enable) { (void)enable; From ca3d871a2105e66573acb7a2a96cb6c7a7ee48c3 Mon Sep 17 00:00:00 2001 From: Xiao Xufeng Date: Tue, 7 Mar 2023 11:13:18 +0800 Subject: [PATCH 3/5] bootloader: fixed super watchdog not enabled issue on C3, S3, H4 --- .../bootloader_support/src/esp32c3/bootloader_esp32c3.c | 6 +++--- components/bootloader_support/src/esp32c3/bootloader_soc.c | 6 +++--- components/bootloader_support/src/esp32h4/bootloader_soc.c | 4 ++-- .../bootloader_support/src/esp32s3/bootloader_esp32s3.c | 2 +- components/bootloader_support/src/esp32s3/bootloader_soc.c | 6 +++--- components/soc/esp32c3/include/soc/rtc_cntl_reg.h | 2 +- components/soc/esp32s3/include/soc/rtc_cntl_reg.h | 2 +- 7 files changed, 14 insertions(+), 14 deletions(-) diff --git a/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c b/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c index 97fbe9d5c1c5..f77f8b68d982 100644 --- a/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c +++ b/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c @@ -104,20 +104,20 @@ static inline void bootloader_ana_reset_config(void) switch (efuse_hal_chip_revision()) { case 0: case 1: - //Enable WDT reset. Disable BOR and GLITCH reset + //Enable WDT reset. Disable BOD and GLITCH reset bootloader_ana_super_wdt_reset_config(true); bootloader_ana_bod_reset_config(false); bootloader_ana_clock_glitch_reset_config(false); break; case 2: - //Enable WDT and BOR reset. Disable GLITCH reset + //Enable WDT and BOD reset. Disable GLITCH reset bootloader_ana_super_wdt_reset_config(true); bootloader_ana_bod_reset_config(true); bootloader_ana_clock_glitch_reset_config(false); break; case 3: default: - //Enable WDT, BOR, and GLITCH reset + //Enable WDT, BOD, and GLITCH reset bootloader_ana_super_wdt_reset_config(true); bootloader_ana_bod_reset_config(true); bootloader_ana_clock_glitch_reset_config(true); diff --git a/components/bootloader_support/src/esp32c3/bootloader_soc.c b/components/bootloader_support/src/esp32c3/bootloader_soc.c index 7104528a5850..f808b72fd535 100644 --- a/components/bootloader_support/src/esp32c3/bootloader_soc.c +++ b/components/bootloader_support/src/esp32c3/bootloader_soc.c @@ -12,15 +12,15 @@ void bootloader_ana_super_wdt_reset_config(bool enable) REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_SUPER_WDT_RST); if (enable) { - REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST); - } else { REG_CLR_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST); + } else { + REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST); } } void bootloader_ana_bod_reset_config(bool enable) { - REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_BOR_RST); + REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_BOD_RST); if (enable) { REG_SET_BIT(RTC_CNTL_BROWN_OUT_REG, RTC_CNTL_BROWN_OUT_ANA_RST_EN); diff --git a/components/bootloader_support/src/esp32h4/bootloader_soc.c b/components/bootloader_support/src/esp32h4/bootloader_soc.c index a8e6f45d9df8..f808b72fd535 100644 --- a/components/bootloader_support/src/esp32h4/bootloader_soc.c +++ b/components/bootloader_support/src/esp32h4/bootloader_soc.c @@ -12,9 +12,9 @@ void bootloader_ana_super_wdt_reset_config(bool enable) REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_SUPER_WDT_RST); if (enable) { - REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST); - } else { REG_CLR_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST); + } else { + REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST); } } diff --git a/components/bootloader_support/src/esp32s3/bootloader_esp32s3.c b/components/bootloader_support/src/esp32s3/bootloader_esp32s3.c index d09901430cef..d6f650d1f81b 100644 --- a/components/bootloader_support/src/esp32s3/bootloader_esp32s3.c +++ b/components/bootloader_support/src/esp32s3/bootloader_esp32s3.c @@ -130,7 +130,7 @@ static void bootloader_super_wdt_auto_feed(void) static inline void bootloader_ana_reset_config(void) { - //Enable WDT, BOR, and GLITCH reset + //Enable WDT, BOD, and GLITCH reset bootloader_ana_super_wdt_reset_config(true); bootloader_ana_bod_reset_config(true); bootloader_ana_clock_glitch_reset_config(true); diff --git a/components/bootloader_support/src/esp32s3/bootloader_soc.c b/components/bootloader_support/src/esp32s3/bootloader_soc.c index 7104528a5850..f808b72fd535 100644 --- a/components/bootloader_support/src/esp32s3/bootloader_soc.c +++ b/components/bootloader_support/src/esp32s3/bootloader_soc.c @@ -12,15 +12,15 @@ void bootloader_ana_super_wdt_reset_config(bool enable) REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_SUPER_WDT_RST); if (enable) { - REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST); - } else { REG_CLR_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST); + } else { + REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST); } } void bootloader_ana_bod_reset_config(bool enable) { - REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_BOR_RST); + REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_BOD_RST); if (enable) { REG_SET_BIT(RTC_CNTL_BROWN_OUT_REG, RTC_CNTL_BROWN_OUT_ANA_RST_EN); diff --git a/components/soc/esp32c3/include/soc/rtc_cntl_reg.h b/components/soc/esp32c3/include/soc/rtc_cntl_reg.h index ac7d7b03b475..55c8cc2cb588 100644 --- a/components/soc/esp32c3/include/soc/rtc_cntl_reg.h +++ b/components/soc/esp32c3/include/soc/rtc_cntl_reg.h @@ -2353,7 +2353,7 @@ extern "C" { #define RTC_CNTL_FIB_SEL_S 0 #define RTC_CNTL_FIB_GLITCH_RST BIT(0) -#define RTC_CNTL_FIB_BOR_RST BIT(1) +#define RTC_CNTL_FIB_BOD_RST BIT(1) #define RTC_CNTL_FIB_SUPER_WDT_RST BIT(2) #define RTC_CNTL_GPIO_WAKEUP_REG (DR_REG_RTCCNTL_BASE + 0x0110) diff --git a/components/soc/esp32s3/include/soc/rtc_cntl_reg.h b/components/soc/esp32s3/include/soc/rtc_cntl_reg.h index f7eca5aa481f..c66e06b38a7c 100644 --- a/components/soc/esp32s3/include/soc/rtc_cntl_reg.h +++ b/components/soc/esp32s3/include/soc/rtc_cntl_reg.h @@ -3571,7 +3571,7 @@ ork.*/ #define RTC_CNTL_FIB_SEL_S 0 #define RTC_CNTL_FIB_GLITCH_RST BIT(0) -#define RTC_CNTL_FIB_BOR_RST BIT(1) +#define RTC_CNTL_FIB_BOD_RST BIT(1) #define RTC_CNTL_FIB_SUPER_WDT_RST BIT(2) #define RTC_CNTL_TOUCH_DAC_REG (DR_REG_RTCCNTL_BASE + 0x14C) From c6559a9b6479fdc0825b3e92b0142c3045b37ab5 Mon Sep 17 00:00:00 2001 From: Xiao Xufeng Date: Tue, 7 Mar 2023 11:15:05 +0800 Subject: [PATCH 4/5] bootloader: cleanup ana reset config code --- .../src/esp32c3/bootloader_esp32c3.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c b/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c index f77f8b68d982..0a6a5925fc6b 100644 --- a/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c +++ b/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c @@ -96,29 +96,29 @@ static inline void bootloader_hardware_init(void) static inline void bootloader_ana_reset_config(void) { + //Enable super WDT reset. + bootloader_ana_super_wdt_reset_config(true); + /* - For origin chip & ECO1: only support swt reset; - For ECO2: fix brownout reset bug, support swt & brownout reset; - For ECO3: fix clock glitch reset bug, support all reset, include: swt & brownout & clock glitch reset. + For origin chip & ECO1: brownout & clock glitch reset not available + For ECO2: fix brownout reset bug + For ECO3: fix clock glitch reset bug */ switch (efuse_hal_chip_revision()) { case 0: case 1: - //Enable WDT reset. Disable BOD and GLITCH reset - bootloader_ana_super_wdt_reset_config(true); + //Disable BOD and GLITCH reset bootloader_ana_bod_reset_config(false); bootloader_ana_clock_glitch_reset_config(false); break; case 2: - //Enable WDT and BOD reset. Disable GLITCH reset - bootloader_ana_super_wdt_reset_config(true); + //Enable BOD reset. Disable GLITCH reset bootloader_ana_bod_reset_config(true); bootloader_ana_clock_glitch_reset_config(false); break; case 3: default: - //Enable WDT, BOD, and GLITCH reset - bootloader_ana_super_wdt_reset_config(true); + //Enable BOD, and GLITCH reset bootloader_ana_bod_reset_config(true); bootloader_ana_clock_glitch_reset_config(true); break; From 5c88e0d801be54fc6f1f0150f4e87556e4438552 Mon Sep 17 00:00:00 2001 From: Xiao Xufeng Date: Wed, 8 Mar 2023 14:12:34 +0800 Subject: [PATCH 5/5] bootloader: enable super WDT and BOD reset on C2 --- .../src/esp32c2/bootloader_esp32c2.c | 10 +++++++++ .../src/esp32c2/bootloader_soc.c | 21 ++++++++++++++++--- .../soc/esp32c2/include/soc/rtc_cntl_reg.h | 4 ++++ 3 files changed, 32 insertions(+), 3 deletions(-) diff --git a/components/bootloader_support/src/esp32c2/bootloader_esp32c2.c b/components/bootloader_support/src/esp32c2/bootloader_esp32c2.c index ebe7cf275797..c54da7eb7464 100644 --- a/components/bootloader_support/src/esp32c2/bootloader_esp32c2.c +++ b/components/bootloader_support/src/esp32c2/bootloader_esp32c2.c @@ -34,6 +34,7 @@ #include "bootloader_mem.h" #include "bootloader_console.h" #include "bootloader_flash_priv.h" +#include "bootloader_soc.h" #include "esp_private/bootloader_flash_internal.h" #include "esp_efuse.h" #include "hal/mmu_hal.h" @@ -78,10 +79,19 @@ static void bootloader_super_wdt_auto_feed(void) REG_WRITE(RTC_CNTL_SWD_WPROTECT_REG, 0); } +static inline void bootloader_ana_reset_config(void) +{ + //Enable super WDT reset. + bootloader_ana_super_wdt_reset_config(true); + //Enable BOD reset + bootloader_ana_bod_reset_config(true); +} + esp_err_t bootloader_init(void) { esp_err_t ret = ESP_OK; + bootloader_ana_reset_config(); bootloader_super_wdt_auto_feed(); // In RAM_APP, memory will be initialized in `call_start_cpu0` diff --git a/components/bootloader_support/src/esp32c2/bootloader_soc.c b/components/bootloader_support/src/esp32c2/bootloader_soc.c index 2b20b0415aca..2233be7529a4 100644 --- a/components/bootloader_support/src/esp32c2/bootloader_soc.c +++ b/components/bootloader_support/src/esp32c2/bootloader_soc.c @@ -3,19 +3,34 @@ * * SPDX-License-Identifier: Apache-2.0 */ + #include +#include "soc/rtc_cntl_reg.h" void bootloader_ana_super_wdt_reset_config(bool enable) { - (void)enable; // ESP32-C2 has none of these features. + REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_SUPER_WDT_RST); + + if (enable) { + REG_CLR_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST); + } else { + REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST); + } } void bootloader_ana_bod_reset_config(bool enable) { - (void)enable; // ESP32-C2 has none of these features. + REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_BOD_RST); + + if (enable) { + REG_SET_BIT(RTC_CNTL_BROWN_OUT_REG, RTC_CNTL_BROWN_OUT_ANA_RST_EN); + } else { + REG_CLR_BIT(RTC_CNTL_BROWN_OUT_REG, RTC_CNTL_BROWN_OUT_ANA_RST_EN); + } } +//Not supported but common bootloader calls the function. Do nothing void bootloader_ana_clock_glitch_reset_config(bool enable) { - (void)enable; // ESP32-C2 has none of these features. + (void)enable; } diff --git a/components/soc/esp32c2/include/soc/rtc_cntl_reg.h b/components/soc/esp32c2/include/soc/rtc_cntl_reg.h index 2ae5143b01f4..e70fb4760303 100644 --- a/components/soc/esp32c2/include/soc/rtc_cntl_reg.h +++ b/components/soc/esp32c2/include/soc/rtc_cntl_reg.h @@ -1678,6 +1678,10 @@ RO CPU.*/ #define RTC_CNTL_FIB_SEL_V 0x7 #define RTC_CNTL_FIB_SEL_S 0 +#define RTC_CNTL_FIB_GLITCH_RST BIT(0) +#define RTC_CNTL_FIB_BOD_RST BIT(1) +#define RTC_CNTL_FIB_SUPER_WDT_RST BIT(2) + #define RTC_CNTL_GPIO_WAKEUP_REG (DR_REG_RTCCNTL_BASE + 0xFC) /* RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE : ;bitpos:[31] ;default: 1'b0 ; */ /*description: Need add desc.*/