From 55db8da793293ac4343b8c63e99e642a683b5260 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?D=C3=A1niel=20Buga?= Date: Mon, 20 Jan 2025 13:59:14 +0100 Subject: [PATCH] Remove Deref to pac register block from peripheral singletons --- esp-hal/src/aes/esp32.rs | 20 +- esp-hal/src/aes/esp32cX.rs | 19 +- esp-hal/src/aes/esp32s2.rs | 22 +-- esp-hal/src/aes/esp32s3.rs | 20 +- esp-hal/src/aes/mod.rs | 23 ++- esp-hal/src/assist_debug.rs | 133 +++++++------- esp-hal/src/dma/pdma/crypto.rs | 94 ++++------ esp-hal/src/dma/pdma/i2s.rs | 101 +++++------ esp-hal/src/dma/pdma/spi.rs | 110 ++++++----- esp-hal/src/ecc.rs | 254 +++++++++++++++----------- esp-hal/src/hmac.rs | 60 +++--- esp-hal/src/i2c/lp_i2c.rs | 45 ++++- esp-hal/src/i2c/master/mod.rs | 162 ++++++----------- esp-hal/src/i2s/master.rs | 271 ++++++++++++++-------------- esp-hal/src/i2s/parallel.rs | 101 +++++------ esp-hal/src/interrupt/riscv.rs | 2 +- esp-hal/src/lcd_cam/cam.rs | 35 ++-- esp-hal/src/lcd_cam/lcd/dpi.rs | 44 ++--- esp-hal/src/lcd_cam/lcd/i8080.rs | 56 +++--- esp-hal/src/mcpwm/mod.rs | 14 +- esp-hal/src/pcnt/channel.rs | 2 +- esp-hal/src/peripheral.rs | 10 +- esp-hal/src/rsa/esp32.rs | 14 +- esp-hal/src/rsa/esp32cX.rs | 56 +++--- esp-hal/src/rsa/esp32sX.rs | 28 +-- esp-hal/src/rsa/mod.rs | 41 ++--- esp-hal/src/rtc_cntl/rtc/esp32c6.rs | 2 +- esp-hal/src/sha.rs | 65 ++++--- esp-hal/src/soc/esp32s3/psram.rs | 4 +- esp-hal/src/spi/master.rs | 142 +++++++-------- esp-hal/src/spi/slave.rs | 112 +++++------- esp-hal/src/timer/timg.rs | 10 +- esp-hal/src/trace.rs | 2 +- esp-hal/src/twai/mod.rs | 168 +++++++---------- esp-hal/src/uart.rs | 207 +++++++++++---------- esp-hal/src/usb_serial_jtag.rs | 116 ++++++------ hil-test/tests/interrupt.rs | 2 +- 37 files changed, 1261 insertions(+), 1306 deletions(-) diff --git a/esp-hal/src/aes/esp32.rs b/esp-hal/src/aes/esp32.rs index a2ca07e3ea1..fb9929cd859 100644 --- a/esp-hal/src/aes/esp32.rs +++ b/esp-hal/src/aes/esp32.rs @@ -13,22 +13,22 @@ impl Aes<'_> { } pub(super) fn write_key(&mut self, key: &[u8]) { - let key_len = self.aes.key_iter().count(); + let key_len = self.regs().key_iter().count(); debug_assert!(key.len() <= key_len * ALIGN_SIZE); debug_assert_eq!(key.len() % ALIGN_SIZE, 0); self.alignment_helper - .volatile_write_regset(self.aes.key(0).as_ptr(), key, key_len); + .volatile_write_regset(self.regs().key(0).as_ptr(), key, key_len); } pub(super) fn write_block(&mut self, block: &[u8]) { - let text_len = self.aes.text_iter().count(); + let text_len = self.regs().text_iter().count(); debug_assert_eq!(block.len(), text_len * ALIGN_SIZE); self.alignment_helper - .volatile_write_regset(self.aes.text(0).as_ptr(), block, text_len); + .volatile_write_regset(self.regs().text(0).as_ptr(), block, text_len); } pub(super) fn write_mode(&self, mode: Mode) { - self.aes.mode().write(|w| unsafe { w.bits(mode as _) }); + self.regs().mode().write(|w| unsafe { w.bits(mode as _) }); } /// Configures how the state matrix would be laid out @@ -48,22 +48,22 @@ impl Aes<'_> { to_write |= (input_text_word_endianess as u32) << 3; to_write |= (output_text_byte_endianess as u32) << 4; to_write |= (output_text_word_endianess as u32) << 5; - self.aes.endian().write(|w| unsafe { w.bits(to_write) }); + self.regs().endian().write(|w| unsafe { w.bits(to_write) }); } pub(super) fn write_start(&self) { - self.aes.start().write(|w| w.start().set_bit()); + self.regs().start().write(|w| w.start().set_bit()); } pub(super) fn read_idle(&mut self) -> bool { - self.aes.idle().read().idle().bit_is_set() + self.regs().idle().read().idle().bit_is_set() } pub(super) fn read_block(&self, block: &mut [u8]) { - let text_len = self.aes.text_iter().count(); + let text_len = self.regs().text_iter().count(); debug_assert_eq!(block.len(), text_len * ALIGN_SIZE); self.alignment_helper - .volatile_read_regset(self.aes.text(0).as_ptr(), block, text_len); + .volatile_read_regset(self.regs().text(0).as_ptr(), block, text_len); } } diff --git a/esp-hal/src/aes/esp32cX.rs b/esp-hal/src/aes/esp32cX.rs index ed5d609becf..0a035d6a559 100644 --- a/esp-hal/src/aes/esp32cX.rs +++ b/esp-hal/src/aes/esp32cX.rs @@ -6,41 +6,40 @@ impl Aes<'_> { } fn write_dma(&mut self, enable_dma: bool) { - match enable_dma { - true => self.aes.dma_enable().write(|w| w.dma_enable().set_bit()), - false => self.aes.dma_enable().write(|w| w.dma_enable().clear_bit()), - }; + self.regs() + .dma_enable() + .write(|w| w.dma_enable().bit(enable_dma)); } pub(super) fn write_key(&mut self, key: &[u8]) { debug_assert!(key.len() <= 8 * ALIGN_SIZE); debug_assert_eq!(key.len() % ALIGN_SIZE, 0); self.alignment_helper - .volatile_write_regset(self.aes.key(0).as_ptr(), key, 8); + .volatile_write_regset(self.regs().key(0).as_ptr(), key, 8); } pub(super) fn write_block(&mut self, block: &[u8]) { debug_assert_eq!(block.len(), 4 * ALIGN_SIZE); self.alignment_helper - .volatile_write_regset(self.aes.text_in(0).as_ptr(), block, 4); + .volatile_write_regset(self.regs().text_in(0).as_ptr(), block, 4); } pub(super) fn write_mode(&self, mode: Mode) { - self.aes.mode().write(|w| unsafe { w.bits(mode as _) }); + self.regs().mode().write(|w| unsafe { w.bits(mode as _) }); } pub(super) fn write_start(&self) { - self.aes.trigger().write(|w| w.trigger().set_bit()); + self.regs().trigger().write(|w| w.trigger().set_bit()); } pub(super) fn read_idle(&mut self) -> bool { - self.aes.state().read().state().bits() == 0 + self.regs().state().read().state().bits() == 0 } pub(super) fn read_block(&self, block: &mut [u8]) { debug_assert_eq!(block.len(), 4 * ALIGN_SIZE); self.alignment_helper - .volatile_read_regset(self.aes.text_out(0).as_ptr(), block, 4); + .volatile_read_regset(self.regs().text_out(0).as_ptr(), block, 4); } } diff --git a/esp-hal/src/aes/esp32s2.rs b/esp-hal/src/aes/esp32s2.rs index a9131817b09..1bed8e522c3 100644 --- a/esp-hal/src/aes/esp32s2.rs +++ b/esp-hal/src/aes/esp32s2.rs @@ -14,31 +14,31 @@ impl Aes<'_> { } fn write_dma(&mut self, enable_dma: bool) { - self.aes + self.regs() .dma_enable() .write(|w| w.dma_enable().bit(enable_dma)); } pub(super) fn write_key(&mut self, key: &[u8]) { - let key_len = self.aes.key_iter().count(); + let key_len = self.regs().key_iter().count(); debug_assert!(key.len() <= key_len * ALIGN_SIZE); debug_assert_eq!(key.len() % ALIGN_SIZE, 0); self.alignment_helper - .volatile_write_regset(self.aes.key(0).as_ptr(), key, key_len); + .volatile_write_regset(self.regs().key(0).as_ptr(), key, key_len); } pub(super) fn write_block(&mut self, block: &[u8]) { - let text_in_len = self.aes.text_in_iter().count(); + let text_in_len = self.regs().text_in_iter().count(); debug_assert_eq!(block.len(), text_in_len * ALIGN_SIZE); self.alignment_helper.volatile_write_regset( - self.aes.text_in(0).as_ptr(), + self.regs().text_in(0).as_ptr(), block, text_in_len, ); } pub(super) fn write_mode(&self, mode: Mode) { - self.aes.mode().write(|w| unsafe { w.bits(mode as _) }); + self.regs().mode().write(|w| unsafe { w.bits(mode as _) }); } /// Configures how the state matrix would be laid out. @@ -58,22 +58,22 @@ impl Aes<'_> { to_write |= (input_text_word_endianess as u32) << 3; to_write |= (output_text_byte_endianess as u32) << 4; to_write |= (output_text_word_endianess as u32) << 5; - self.aes.endian().write(|w| unsafe { w.bits(to_write) }); + self.regs().endian().write(|w| unsafe { w.bits(to_write) }); } pub(super) fn write_start(&self) { - self.aes.trigger().write(|w| w.trigger().set_bit()); + self.regs().trigger().write(|w| w.trigger().set_bit()); } pub(super) fn read_idle(&mut self) -> bool { - self.aes.state().read().state().bits() == 0 + self.regs().state().read().state().bits() == 0 } pub(super) fn read_block(&self, block: &mut [u8]) { - let text_out_len = self.aes.text_out_iter().count(); + let text_out_len = self.regs().text_out_iter().count(); debug_assert_eq!(block.len(), text_out_len * ALIGN_SIZE); self.alignment_helper.volatile_read_regset( - self.aes.text_out(0).as_ptr(), + self.regs().text_out(0).as_ptr(), block, text_out_len, ); diff --git a/esp-hal/src/aes/esp32s3.rs b/esp-hal/src/aes/esp32s3.rs index b3cf949bff9..dbc5582675a 100644 --- a/esp-hal/src/aes/esp32s3.rs +++ b/esp-hal/src/aes/esp32s3.rs @@ -6,46 +6,46 @@ impl Aes<'_> { } fn write_dma(&mut self, enable_dma: bool) { - self.aes + self.regs() .dma_enable() .write(|w| w.dma_enable().bit(enable_dma)); } pub(super) fn write_key(&mut self, key: &[u8]) { - let key_len = self.aes.key_iter().count(); + let key_len = self.regs().key_iter().count(); debug_assert!(key.len() <= key_len * ALIGN_SIZE); debug_assert_eq!(key.len() % ALIGN_SIZE, 0); self.alignment_helper - .volatile_write_regset(self.aes.key(0).as_ptr(), key, key_len); + .volatile_write_regset(self.regs().key(0).as_ptr(), key, key_len); } pub(super) fn write_block(&mut self, block: &[u8]) { - let text_in_len = self.aes.text_in_iter().count(); + let text_in_len = self.regs().text_in_iter().count(); debug_assert_eq!(block.len(), text_in_len * ALIGN_SIZE); self.alignment_helper.volatile_write_regset( - self.aes.text_in(0).as_ptr(), + self.regs().text_in(0).as_ptr(), block, text_in_len, ); } pub(super) fn write_mode(&self, mode: Mode) { - self.aes.mode().write(|w| unsafe { w.bits(mode as _) }); + self.regs().mode().write(|w| unsafe { w.bits(mode as _) }); } pub(super) fn write_start(&self) { - self.aes.trigger().write(|w| w.trigger().set_bit()); + self.regs().trigger().write(|w| w.trigger().set_bit()); } pub(super) fn read_idle(&mut self) -> bool { - self.aes.state().read().state().bits() == 0 + self.regs().state().read().state().bits() == 0 } pub(super) fn read_block(&self, block: &mut [u8]) { - let text_out_len = self.aes.text_out_iter().count(); + let text_out_len = self.regs().text_out_iter().count(); debug_assert_eq!(block.len(), text_out_len * ALIGN_SIZE); self.alignment_helper.volatile_read_regset( - self.aes.text_out(0).as_ptr(), + self.regs().text_out(0).as_ptr(), block, text_out_len, ); diff --git a/esp-hal/src/aes/mod.rs b/esp-hal/src/aes/mod.rs index 96c416fcb8b..138df44bc98 100644 --- a/esp-hal/src/aes/mod.rs +++ b/esp-hal/src/aes/mod.rs @@ -56,6 +56,7 @@ //! * AES-DMA Initialization Vector (IV) is currently not supported use crate::{ + pac, peripheral::{Peripheral, PeripheralRef}, peripherals::AES, reg_access::{AlignmentHelper, NativeEndianess}, @@ -157,6 +158,10 @@ impl<'d> Aes<'d> { ret } + fn regs(&self) -> &pac::aes::RegisterBlock { + self.aes.register_block() + } + /// Encrypts/Decrypts the given buffer based on `mode` parameter pub fn process(&mut self, block: &mut [u8; 16], mode: Mode, key: K) where @@ -314,7 +319,7 @@ pub mod dma { impl DmaSupport for AesDma<'_> { fn peripheral_wait_dma(&mut self, _is_rx: bool, _is_tx: bool) { - while self.aes.aes.state().read().state().bits() != 2 // DMA status DONE == 2 + while self.aes.regs().state().read().state().bits() != 2 // DMA status DONE == 2 && !self.channel.tx.is_done() { // wait until done @@ -456,10 +461,10 @@ pub mod dma { SYSTEM::regs() .perip_rst_en1() - .modify(|_, w| w.crypto_aes_rst().set_bit()); + .modify(|_, w| w.crypto_aes_rst().set_bit()); SYSTEM::regs() .perip_rst_en1() - .modify(|_, w| w.crypto_aes_rst().clear_bit()); + .modify(|_, w| w.crypto_aes_rst().clear_bit()); } #[cfg(any(esp32c6, esp32h2))] @@ -480,24 +485,24 @@ pub mod dma { fn enable_dma(&self, enable: bool) { self.aes - .aes + .regs() .dma_enable() .write(|w| w.dma_enable().bit(enable)); } fn enable_interrupt(&self) { - self.aes.aes.int_ena().write(|w| w.int_ena().set_bit()); + self.aes.regs().int_ena().write(|w| w.int_ena().set_bit()); } fn set_cipher_mode(&self, mode: CipherMode) { self.aes - .aes + .regs() .block_mode() .modify(|_, w| unsafe { w.block_mode().bits(mode as u8) }); if mode == CipherMode::Ctr { self.aes - .aes + .regs() .inc_sel() .modify(|_, w| w.inc_sel().clear_bit()); } @@ -508,14 +513,14 @@ pub mod dma { } fn finish_transform(&self) { - self.aes.aes.dma_exit().write(|w| w.dma_exit().set_bit()); + self.aes.regs().dma_exit().write(|w| w.dma_exit().set_bit()); self.enable_dma(false); self.reset_aes(); } fn set_num_block(&self, block: u32) { self.aes - .aes + .regs() .block_num() .modify(|_, w| unsafe { w.block_num().bits(block) }); } diff --git a/esp-hal/src/assist_debug.rs b/esp-hal/src/assist_debug.rs index 0063b4f1eae..310c2f970ca 100644 --- a/esp-hal/src/assist_debug.rs +++ b/esp-hal/src/assist_debug.rs @@ -25,6 +25,7 @@ use crate::{ interrupt::{InterruptConfigurable, InterruptHandler}, + pac, peripheral::{Peripheral, PeripheralRef}, peripherals::{Interrupt, ASSIST_DEBUG}, }; @@ -44,6 +45,10 @@ impl<'d> DebugAssist<'d> { DebugAssist { debug_assist } } + + fn regs(&self) -> &pac::assist_debug::RegisterBlock { + self.debug_assist.register_block() + } } impl crate::private::Sealed for DebugAssist<'_> {} @@ -67,15 +72,15 @@ impl DebugAssist<'_> { /// `lower_bound` or `upper_bound` threshold, the module will record the PC /// pointer and generate an interrupt. pub fn enable_sp_monitor(&mut self, lower_bound: u32, upper_bound: u32) { - self.debug_assist + self.regs() .core_0_sp_min() .write(|w| unsafe { w.core_0_sp_min().bits(lower_bound) }); - self.debug_assist + self.regs() .core_0_sp_max() .write(|w| unsafe { w.core_0_sp_max().bits(upper_bound) }); - self.debug_assist.core_0_montr_ena().modify(|_, w| { + self.regs().core_0_montr_ena().modify(|_, w| { w.core_0_sp_spill_min_ena() .set_bit() .core_0_sp_spill_max_ena() @@ -84,7 +89,7 @@ impl DebugAssist<'_> { self.clear_sp_monitor_interrupt(); - self.debug_assist.core_0_intr_ena().modify(|_, w| { + self.regs().core_0_intr_ena().modify(|_, w| { w.core_0_sp_spill_max_intr_ena() .set_bit() .core_0_sp_spill_min_intr_ena() @@ -94,14 +99,14 @@ impl DebugAssist<'_> { /// Disable SP monitoring on main core. pub fn disable_sp_monitor(&mut self) { - self.debug_assist.core_0_intr_ena().modify(|_, w| { + self.regs().core_0_intr_ena().modify(|_, w| { w.core_0_sp_spill_max_intr_ena() .clear_bit() .core_0_sp_spill_min_intr_ena() .clear_bit() }); - self.debug_assist.core_0_montr_ena().modify(|_, w| { + self.regs().core_0_montr_ena().modify(|_, w| { w.core_0_sp_spill_min_ena() .clear_bit() .core_0_sp_spill_max_ena() @@ -111,7 +116,7 @@ impl DebugAssist<'_> { /// Clear SP monitoring interrupt on main core. pub fn clear_sp_monitor_interrupt(&mut self) { - self.debug_assist.core_0_intr_clr().write(|w| { + self.regs().core_0_intr_clr().write(|w| { w.core_0_sp_spill_max_clr() .set_bit() .core_0_sp_spill_min_clr() @@ -121,13 +126,13 @@ impl DebugAssist<'_> { /// Check, if SP monitoring interrupt is set on main core. pub fn is_sp_monitor_interrupt_set(&self) -> bool { - self.debug_assist + self.regs() .core_0_intr_raw() .read() .core_0_sp_spill_max_raw() .bit_is_set() || self - .debug_assist + .regs() .core_0_intr_raw() .read() .core_0_sp_spill_min_raw() @@ -136,11 +141,7 @@ impl DebugAssist<'_> { /// Get SP monitoring PC value on main core. pub fn sp_monitor_pc(&self) -> u32 { - self.debug_assist - .core_0_sp_pc() - .read() - .core_0_sp_pc() - .bits() + self.regs().core_0_sp_pc().read().core_0_sp_pc().bits() } } @@ -150,15 +151,15 @@ impl<'d> DebugAssist<'d> { /// `lower_bound` or `upper_bound` threshold, the module will record the PC /// pointer and generate an interrupt. pub fn enable_core1_sp_monitor(&mut self, lower_bound: u32, upper_bound: u32) { - self.debug_assist + self.regs() .core_1_sp_min .write(|w| w.core_1_sp_min().bits(lower_bound)); - self.debug_assist + self.regs() .core_1_sp_max .write(|w| w.core_1_sp_max().bits(upper_bound)); - self.debug_assist.core_1_montr_ena.modify(|_, w| { + self.regs().core_1_montr_ena.modify(|_, w| { w.core_1_sp_spill_min_ena() .set_bit() .core_1_sp_spill_max_ena() @@ -167,7 +168,7 @@ impl<'d> DebugAssist<'d> { self.clear_core1_sp_monitor_interrupt(); - self.debug_assist.core_1_intr_ena.modify(|_, w| { + self.regs().core_1_intr_ena.modify(|_, w| { w.core_1_sp_spill_max_intr_ena() .set_bit() .core_1_sp_spill_min_intr_ena() @@ -177,14 +178,14 @@ impl<'d> DebugAssist<'d> { /// Disable SP monitoring on secondary core. pub fn disable_core1_sp_monitor(&mut self) { - self.debug_assist.core_1_intr_ena.modify(|_, w| { + self.regs().core_1_intr_ena.modify(|_, w| { w.core_1_sp_spill_max_intr_ena() .clear_bit() .core_1_sp_spill_min_intr_ena() .clear_bit() }); - self.debug_assist.core_1_montr_ena.modify(|_, w| { + self.regs().core_1_montr_ena.modify(|_, w| { w.core_1_sp_spill_min_ena() .clear_bit() .core_1_sp_spill_max_ena() @@ -194,7 +195,7 @@ impl<'d> DebugAssist<'d> { /// Clear SP monitoring interrupt on secondary core. pub fn clear_core1_sp_monitor_interrupt(&mut self) { - self.debug_assist.core_1_intr_clr.write(|w| { + self.regs().core_1_intr_clr.write(|w| { w.core_1_sp_spill_max_clr() .set_bit() .core_1_sp_spill_min_clr() @@ -204,13 +205,13 @@ impl<'d> DebugAssist<'d> { /// Check, if SP monitoring interrupt is set on secondary core. pub fn is_core1_sp_monitor_interrupt_set(&self) -> bool { - self.debug_assist + self.regs() .core_1_intr_raw .read() .core_1_sp_spill_max_raw() .bit_is_set() || self - .debug_assist + .regs() .core_1_intr_raw .read() .core_1_sp_spill_min_raw() @@ -219,7 +220,7 @@ impl<'d> DebugAssist<'d> { /// Get SP monitoring PC value on secondary core. pub fn core1_sp_monitor_pc(&self) -> u32 { - self.debug_assist.core_1_sp_pc.read().core_1_sp_pc().bits() + self.regs().core_1_sp_pc.read().core_1_sp_pc().bits() } } @@ -236,15 +237,15 @@ impl DebugAssist<'_> { reads: bool, writes: bool, ) { - self.debug_assist + self.regs() .core_0_area_dram0_0_min() .write(|w| unsafe { w.core_0_area_dram0_0_min().bits(lower_bound) }); - self.debug_assist + self.regs() .core_0_area_dram0_0_max() .write(|w| unsafe { w.core_0_area_dram0_0_max().bits(upper_bound) }); - self.debug_assist.core_0_montr_ena().modify(|_, w| { + self.regs().core_0_montr_ena().modify(|_, w| { w.core_0_area_dram0_0_rd_ena() .bit(reads) .core_0_area_dram0_0_wr_ena() @@ -253,7 +254,7 @@ impl DebugAssist<'_> { self.clear_region0_monitor_interrupt(); - self.debug_assist.core_0_intr_ena().modify(|_, w| { + self.regs().core_0_intr_ena().modify(|_, w| { w.core_0_area_dram0_0_rd_intr_ena() .set_bit() .core_0_area_dram0_0_wr_intr_ena() @@ -263,14 +264,14 @@ impl DebugAssist<'_> { /// Disable region0 monitoring on main core. pub fn disable_region0_monitor(&mut self) { - self.debug_assist.core_0_intr_ena().modify(|_, w| { + self.regs().core_0_intr_ena().modify(|_, w| { w.core_0_area_dram0_0_rd_intr_ena() .clear_bit() .core_0_area_dram0_0_wr_intr_ena() .clear_bit() }); - self.debug_assist.core_0_montr_ena().modify(|_, w| { + self.regs().core_0_montr_ena().modify(|_, w| { w.core_0_area_dram0_0_rd_ena() .clear_bit() .core_0_area_dram0_0_wr_ena() @@ -280,7 +281,7 @@ impl DebugAssist<'_> { /// Clear region0 monitoring interrupt on main core. pub fn clear_region0_monitor_interrupt(&mut self) { - self.debug_assist.core_0_intr_clr().write(|w| { + self.regs().core_0_intr_clr().write(|w| { w.core_0_area_dram0_0_rd_clr() .set_bit() .core_0_area_dram0_0_wr_clr() @@ -290,13 +291,13 @@ impl DebugAssist<'_> { /// Check, if region0 monitoring interrupt is set on main core. pub fn is_region0_monitor_interrupt_set(&self) -> bool { - self.debug_assist + self.regs() .core_0_intr_raw() .read() .core_0_area_dram0_0_rd_raw() .bit_is_set() || self - .debug_assist + .regs() .core_0_intr_raw() .read() .core_0_area_dram0_0_wr_raw() @@ -313,15 +314,15 @@ impl DebugAssist<'_> { reads: bool, writes: bool, ) { - self.debug_assist + self.regs() .core_0_area_dram0_1_min() .write(|w| unsafe { w.core_0_area_dram0_1_min().bits(lower_bound) }); - self.debug_assist + self.regs() .core_0_area_dram0_1_max() .write(|w| unsafe { w.core_0_area_dram0_1_max().bits(upper_bound) }); - self.debug_assist.core_0_montr_ena().modify(|_, w| { + self.regs().core_0_montr_ena().modify(|_, w| { w.core_0_area_dram0_1_rd_ena() .bit(reads) .core_0_area_dram0_1_wr_ena() @@ -330,7 +331,7 @@ impl DebugAssist<'_> { self.clear_region1_monitor_interrupt(); - self.debug_assist.core_0_intr_ena().modify(|_, w| { + self.regs().core_0_intr_ena().modify(|_, w| { w.core_0_area_dram0_1_rd_intr_ena() .set_bit() .core_0_area_dram0_1_wr_intr_ena() @@ -340,14 +341,14 @@ impl DebugAssist<'_> { /// Disable region1 monitoring on main core. pub fn disable_region1_monitor(&mut self) { - self.debug_assist.core_0_intr_ena().modify(|_, w| { + self.regs().core_0_intr_ena().modify(|_, w| { w.core_0_area_dram0_1_rd_intr_ena() .clear_bit() .core_0_area_dram0_1_wr_intr_ena() .clear_bit() }); - self.debug_assist.core_0_montr_ena().modify(|_, w| { + self.regs().core_0_montr_ena().modify(|_, w| { w.core_0_area_dram0_1_rd_ena() .clear_bit() .core_0_area_dram0_1_wr_ena() @@ -357,7 +358,7 @@ impl DebugAssist<'_> { /// Clear region1 monitoring interrupt on main core. pub fn clear_region1_monitor_interrupt(&mut self) { - self.debug_assist.core_0_intr_clr().write(|w| { + self.regs().core_0_intr_clr().write(|w| { w.core_0_area_dram0_1_rd_clr() .set_bit() .core_0_area_dram0_1_wr_clr() @@ -367,13 +368,13 @@ impl DebugAssist<'_> { /// Check, if region1 monitoring interrupt is set on main core. pub fn is_region1_monitor_interrupt_set(&self) -> bool { - self.debug_assist + self.regs() .core_0_intr_raw() .read() .core_0_area_dram0_1_rd_raw() .bit_is_set() || self - .debug_assist + .regs() .core_0_intr_raw() .read() .core_0_area_dram0_1_wr_raw() @@ -382,11 +383,7 @@ impl DebugAssist<'_> { /// Get region monitoring PC value on main core. pub fn region_monitor_pc(&self) -> u32 { - self.debug_assist - .core_0_area_pc() - .read() - .core_0_area_pc() - .bits() + self.regs().core_0_area_pc().read().core_0_area_pc().bits() } } @@ -402,15 +399,15 @@ impl DebugAssist<'_> { reads: bool, writes: bool, ) { - self.debug_assist + self.regs() .core_1_area_dram0_0_min() .write(|w| unsafe { w.core_1_area_dram0_0_min().bits(lower_bound) }); - self.debug_assist + self.regs() .core_1_area_dram0_0_max() .write(|w| unsafe { w.core_1_area_dram0_0_max().bits(upper_bound) }); - self.debug_assist.core_1_montr_ena().modify(|_, w| { + self.regs().core_1_montr_ena().modify(|_, w| { w.core_1_area_dram0_0_rd_ena() .bit(reads) .core_1_area_dram0_0_wr_ena() @@ -419,7 +416,7 @@ impl DebugAssist<'_> { self.clear_core1_region0_monitor_interrupt(); - self.debug_assist.core_1_intr_ena().modify(|_, w| { + self.regs().core_1_intr_ena().modify(|_, w| { w.core_1_area_dram0_0_rd_intr_ena() .set_bit() .core_1_area_dram0_0_wr_intr_ena() @@ -429,14 +426,14 @@ impl DebugAssist<'_> { /// Disable region0 monitoring on secondary core. pub fn disable_core1_region0_monitor(&mut self) { - self.debug_assist.core_1_intr_ena().modify(|_, w| { + self.regs().core_1_intr_ena().modify(|_, w| { w.core_1_area_dram0_0_rd_intr_ena() .clear_bit() .core_1_area_dram0_0_wr_intr_ena() .clear_bit() }); - self.debug_assist.core_1_montr_ena().modify(|_, w| { + self.regs().core_1_montr_ena().modify(|_, w| { w.core_1_area_dram0_0_rd_ena() .clear_bit() .core_1_area_dram0_0_wr_ena() @@ -446,7 +443,7 @@ impl DebugAssist<'_> { /// Clear region0 monitoring interrupt on secondary core. pub fn clear_core1_region0_monitor_interrupt(&mut self) { - self.debug_assist.core_1_intr_clr().write(|w| { + self.regs().core_1_intr_clr().write(|w| { w.core_1_area_dram0_0_rd_clr() .set_bit() .core_1_area_dram0_0_wr_clr() @@ -456,13 +453,13 @@ impl DebugAssist<'_> { /// Check, if region0 monitoring interrupt is set on secondary core. pub fn is_core1_region0_monitor_interrupt_set(&self) -> bool { - self.debug_assist + self.regs() .core_1_intr_raw() .read() .core_1_area_dram0_0_rd_raw() .bit_is_set() || self - .debug_assist + .regs() .core_1_intr_raw() .read() .core_1_area_dram0_0_wr_raw() @@ -479,15 +476,15 @@ impl DebugAssist<'_> { reads: bool, writes: bool, ) { - self.debug_assist + self.regs() .core_1_area_dram0_1_min() .write(|w| unsafe { w.core_1_area_dram0_1_min().bits(lower_bound) }); - self.debug_assist + self.regs() .core_1_area_dram0_1_max() .write(|w| unsafe { w.core_1_area_dram0_1_max().bits(upper_bound) }); - self.debug_assist.core_1_montr_ena().modify(|_, w| { + self.regs().core_1_montr_ena().modify(|_, w| { w.core_1_area_dram0_1_rd_ena() .bit(reads) .core_1_area_dram0_1_wr_ena() @@ -496,7 +493,7 @@ impl DebugAssist<'_> { self.clear_core1_region1_monitor_interrupt(); - self.debug_assist.core_1_intr_ena().modify(|_, w| { + self.regs().core_1_intr_ena().modify(|_, w| { w.core_1_area_dram0_1_rd_intr_ena() .set_bit() .core_1_area_dram0_1_wr_intr_ena() @@ -506,14 +503,14 @@ impl DebugAssist<'_> { /// Disable region1 monitoring on secondary core. pub fn disable_core1_region1_monitor(&mut self) { - self.debug_assist.core_1_intr_ena().modify(|_, w| { + self.regs().core_1_intr_ena().modify(|_, w| { w.core_1_area_dram0_1_rd_intr_ena() .clear_bit() .core_1_area_dram0_1_wr_intr_ena() .clear_bit() }); - self.debug_assist.core_1_montr_ena().modify(|_, w| { + self.regs().core_1_montr_ena().modify(|_, w| { w.core_1_area_dram0_1_rd_ena() .clear_bit() .core_1_area_dram0_1_wr_ena() @@ -523,7 +520,7 @@ impl DebugAssist<'_> { /// Clear region1 monitoring interrupt on secondary core. pub fn clear_core1_region1_monitor_interrupt(&mut self) { - self.debug_assist.core_1_intr_clr().write(|w| { + self.regs().core_1_intr_clr().write(|w| { w.core_1_area_dram0_1_rd_clr() .set_bit() .core_1_area_dram0_1_wr_clr() @@ -533,13 +530,13 @@ impl DebugAssist<'_> { /// Check, if region1 monitoring interrupt is set on secondary core. pub fn is_core1_region1_monitor_interrupt_set(&self) -> bool { - self.debug_assist + self.regs() .core_1_intr_raw() .read() .core_1_area_dram0_1_rd_raw() .bit_is_set() || self - .debug_assist + .regs() .core_1_intr_raw() .read() .core_1_area_dram0_1_wr_raw() @@ -548,10 +545,6 @@ impl DebugAssist<'_> { /// Get region monitoring PC value on secondary core. pub fn core1_region_monitor_pc(&self) -> u32 { - self.debug_assist - .core_1_area_pc() - .read() - .core_1_area_pc() - .bits() + self.regs().core_1_area_pc().read().core_1_area_pc().bits() } } diff --git a/esp-hal/src/dma/pdma/crypto.rs b/esp-hal/src/dma/pdma/crypto.rs index c4d1dab59fc..ef95472816b 100644 --- a/esp-hal/src/dma/pdma/crypto.rs +++ b/esp-hal/src/dma/pdma/crypto.rs @@ -15,6 +15,12 @@ pub(super) type CryptoRegisterBlock = crate::pac::crypto_dma::RegisterBlock; #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub struct CryptoDmaRxChannel(pub(crate) CryptoDmaChannel); +impl CryptoDmaRxChannel { + fn regs(&self) -> &CryptoRegisterBlock { + self.0.register_block() + } +} + impl crate::private::Sealed for CryptoDmaRxChannel {} impl DmaRxChannel for CryptoDmaRxChannel {} impl Peripheral for CryptoDmaRxChannel { @@ -30,6 +36,12 @@ impl Peripheral for CryptoDmaRxChannel { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub struct CryptoDmaTxChannel(pub(crate) CryptoDmaChannel); +impl CryptoDmaTxChannel { + fn regs(&self) -> &CryptoRegisterBlock { + self.0.register_block() + } +} + impl crate::private::Sealed for CryptoDmaTxChannel {} impl DmaTxChannel for CryptoDmaTxChannel {} impl Peripheral for CryptoDmaTxChannel { @@ -42,13 +54,12 @@ impl Peripheral for CryptoDmaTxChannel { impl RegisterAccess for CryptoDmaTxChannel { fn reset(&self) { - let register_block = self.0.register_block(); - register_block.conf().modify(|_, w| { + self.regs().conf().modify(|_, w| { w.out_rst().set_bit(); w.ahbm_rst().set_bit(); w.ahbm_fifo_rst().set_bit() }); - register_block.conf().modify(|_, w| { + self.regs().conf().modify(|_, w| { w.out_rst().clear_bit(); w.ahbm_rst().clear_bit(); w.ahbm_fifo_rst().clear_bit() @@ -56,15 +67,13 @@ impl RegisterAccess for CryptoDmaTxChannel { } fn set_burst_mode(&self, burst_mode: BurstConfig) { - let register_block = self.0.register_block(); - register_block + self.regs() .conf() .modify(|_, w| w.out_data_burst_en().bit(burst_mode.is_burst_enabled())); } fn set_descr_burst_mode(&self, burst_mode: bool) { - let register_block = self.0.register_block(); - register_block + self.regs() .conf() .modify(|_, w| w.outdscr_burst_en().bit(burst_mode)); } @@ -76,36 +85,31 @@ impl RegisterAccess for CryptoDmaTxChannel { p if p == DmaPeripheral::Sha as u8 => SELECT::Sha, _ => unreachable!(), }; - let register_block = self.0.register_block(); - register_block + self.regs() .aes_sha_select() .modify(|_, w| w.select().variant(peripheral)); } fn set_link_addr(&self, address: u32) { - let register_block = self.0.register_block(); - register_block + self.regs() .out_link() .modify(|_, w| unsafe { w.outlink_addr().bits(address) }); } fn start(&self) { - let register_block = self.0.register_block(); - register_block + self.regs() .out_link() .modify(|_, w| w.outlink_start().set_bit()); } fn stop(&self) { - let register_block = self.0.register_block(); - register_block + self.regs() .out_link() .modify(|_, w| w.outlink_stop().set_bit()); } fn restart(&self) { - let register_block = self.0.register_block(); - register_block + self.regs() .out_link() .modify(|_, w| w.outlink_restart().set_bit()); } @@ -122,8 +126,7 @@ impl RegisterAccess for CryptoDmaTxChannel { #[cfg(psram_dma)] fn set_ext_mem_block_size(&self, size: DmaExtMemBKSize) { - let register_block = self.0.register_block(); - register_block + self.regs() .conf1() .modify(|_, w| unsafe { w.ext_mem_bk_size().bits(size as u8) }); } @@ -141,8 +144,7 @@ impl TxRegisterAccess for CryptoDmaTxChannel { } fn last_dscr_address(&self) -> usize { - let register_block = self.0.register_block(); - register_block + self.regs() .out_eof_des_addr() .read() .out_eof_des_addr() @@ -160,8 +162,7 @@ impl TxRegisterAccess for CryptoDmaTxChannel { impl InterruptAccess for CryptoDmaTxChannel { fn enable_listen(&self, interrupts: EnumSet, enable: bool) { - let reg_block = self.0.register_block(); - reg_block.int_ena().modify(|_, w| { + self.regs().int_ena().modify(|_, w| { for interrupt in interrupts { match interrupt { DmaTxInterrupt::TotalEof => w.out_total_eof().bit(enable), @@ -177,8 +178,7 @@ impl InterruptAccess for CryptoDmaTxChannel { fn is_listening(&self) -> EnumSet { let mut result = EnumSet::new(); - let register_block = self.0.register_block(); - let int_ena = register_block.int_ena().read(); + let int_ena = self.regs().int_ena().read(); if int_ena.out_total_eof().bit_is_set() { result |= DmaTxInterrupt::TotalEof; } @@ -196,8 +196,7 @@ impl InterruptAccess for CryptoDmaTxChannel { } fn clear(&self, interrupts: impl Into>) { - let register_block = self.0.register_block(); - register_block.int_clr().write(|w| { + self.regs().int_clr().write(|w| { for interrupt in interrupts.into() { match interrupt { DmaTxInterrupt::TotalEof => w.out_total_eof().clear_bit_by_one(), @@ -213,8 +212,7 @@ impl InterruptAccess for CryptoDmaTxChannel { fn pending_interrupts(&self) -> EnumSet { let mut result = EnumSet::new(); - let register_block = self.0.register_block(); - let int_raw = register_block.int_raw().read(); + let int_raw = self.regs().int_raw().read(); if int_raw.out_total_eof().bit_is_set() { result |= DmaTxInterrupt::TotalEof; } @@ -246,13 +244,12 @@ impl InterruptAccess for CryptoDmaTxChannel { impl RegisterAccess for CryptoDmaRxChannel { fn reset(&self) { - let register_block = self.0.register_block(); - register_block.conf().modify(|_, w| { + self.regs().conf().modify(|_, w| { w.in_rst().set_bit(); w.ahbm_rst().set_bit(); w.ahbm_fifo_rst().set_bit() }); - register_block.conf().modify(|_, w| { + self.regs().conf().modify(|_, w| { w.in_rst().clear_bit(); w.ahbm_rst().clear_bit(); w.ahbm_fifo_rst().clear_bit() @@ -262,8 +259,7 @@ impl RegisterAccess for CryptoDmaRxChannel { fn set_burst_mode(&self, _burst_mode: BurstConfig) {} fn set_descr_burst_mode(&self, burst_mode: bool) { - let register_block = self.0.register_block(); - register_block + self.regs() .conf() .modify(|_, w| w.indscr_burst_en().bit(burst_mode)); } @@ -275,36 +271,31 @@ impl RegisterAccess for CryptoDmaRxChannel { p if p == DmaPeripheral::Sha as u8 => SELECT::Sha, _ => unreachable!(), }; - let register_block = self.0.register_block(); - register_block + self.regs() .aes_sha_select() .modify(|_, w| w.select().variant(peripheral)); } fn set_link_addr(&self, address: u32) { - let register_block = self.0.register_block(); - register_block + self.regs() .in_link() .modify(|_, w| unsafe { w.inlink_addr().bits(address) }); } fn start(&self) { - let register_block = self.0.register_block(); - register_block + self.regs() .in_link() .modify(|_, w| w.inlink_start().set_bit()); } fn stop(&self) { - let register_block = self.0.register_block(); - register_block + self.regs() .in_link() .modify(|_, w| w.inlink_stop().set_bit()); } fn restart(&self) { - let register_block = self.0.register_block(); - register_block + self.regs() .in_link() .modify(|_, w| w.inlink_restart().set_bit()); } @@ -321,8 +312,7 @@ impl RegisterAccess for CryptoDmaRxChannel { #[cfg(psram_dma)] fn set_ext_mem_block_size(&self, size: DmaExtMemBKSize) { - let register_block = self.0.register_block(); - register_block + self.regs() .conf1() .modify(|_, w| unsafe { w.ext_mem_bk_size().bits(size as u8) }); } @@ -347,8 +337,7 @@ impl RxRegisterAccess for CryptoDmaRxChannel { impl InterruptAccess for CryptoDmaRxChannel { fn enable_listen(&self, interrupts: EnumSet, enable: bool) { - let reg_block = self.0.register_block(); - reg_block.int_ena().modify(|_, w| { + self.regs().int_ena().modify(|_, w| { for interrupt in interrupts { match interrupt { DmaRxInterrupt::SuccessfulEof => w.in_suc_eof().bit(enable), @@ -365,8 +354,7 @@ impl InterruptAccess for CryptoDmaRxChannel { fn is_listening(&self) -> EnumSet { let mut result = EnumSet::new(); - let register_block = self.0.register_block(); - let int_ena = register_block.int_ena().read(); + let int_ena = self.regs().int_ena().read(); if int_ena.in_dscr_err().bit_is_set() { result |= DmaRxInterrupt::DescriptorError; } @@ -387,8 +375,7 @@ impl InterruptAccess for CryptoDmaRxChannel { } fn clear(&self, interrupts: impl Into>) { - let register_block = self.0.register_block(); - register_block.int_clr().write(|w| { + self.regs().int_clr().write(|w| { for interrupt in interrupts.into() { match interrupt { DmaRxInterrupt::SuccessfulEof => w.in_suc_eof().clear_bit_by_one(), @@ -405,8 +392,7 @@ impl InterruptAccess for CryptoDmaRxChannel { fn pending_interrupts(&self) -> EnumSet { let mut result = EnumSet::new(); - let register_block = self.0.register_block(); - let int_raw = register_block.int_raw().read(); + let int_raw = self.regs().int_raw().read(); if int_raw.in_dscr_err().bit_is_set() { result |= DmaRxInterrupt::DescriptorError; } diff --git a/esp-hal/src/dma/pdma/i2s.rs b/esp-hal/src/dma/pdma/i2s.rs index 41fff3d0c0c..c0b25e02443 100644 --- a/esp-hal/src/dma/pdma/i2s.rs +++ b/esp-hal/src/dma/pdma/i2s.rs @@ -9,6 +9,12 @@ pub(super) type I2sRegisterBlock = crate::pac::i2s0::RegisterBlock; #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub struct AnyI2sDmaRxChannel(pub(crate) AnyI2sDmaChannel); +impl AnyI2sDmaRxChannel { + fn regs(&self) -> &I2sRegisterBlock { + self.0.register_block() + } +} + impl crate::private::Sealed for AnyI2sDmaRxChannel {} impl DmaRxChannel for AnyI2sDmaRxChannel {} impl Peripheral for AnyI2sDmaRxChannel { @@ -24,6 +30,12 @@ impl Peripheral for AnyI2sDmaRxChannel { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub struct AnyI2sDmaTxChannel(pub(crate) AnyI2sDmaChannel); +impl AnyI2sDmaTxChannel { + fn regs(&self) -> &I2sRegisterBlock { + self.0.register_block() + } +} + impl crate::private::Sealed for AnyI2sDmaTxChannel {} impl DmaTxChannel for AnyI2sDmaTxChannel {} impl Peripheral for AnyI2sDmaTxChannel { @@ -36,28 +48,24 @@ impl Peripheral for AnyI2sDmaTxChannel { impl RegisterAccess for AnyI2sDmaTxChannel { fn reset(&self) { - let reg_block = self.0.register_block(); - reg_block.lc_conf().modify(|_, w| w.out_rst().set_bit()); - reg_block.lc_conf().modify(|_, w| w.out_rst().clear_bit()); + self.regs().lc_conf().modify(|_, w| w.out_rst().set_bit()); + self.regs().lc_conf().modify(|_, w| w.out_rst().clear_bit()); } fn set_burst_mode(&self, burst_mode: BurstConfig) { - let reg_block = self.0.register_block(); - reg_block + self.regs() .lc_conf() .modify(|_, w| w.out_data_burst_en().bit(burst_mode.is_burst_enabled())); } fn set_descr_burst_mode(&self, burst_mode: bool) { - let reg_block = self.0.register_block(); - reg_block + self.regs() .lc_conf() .modify(|_, w| w.outdscr_burst_en().bit(burst_mode)); } fn set_link_addr(&self, address: u32) { - let reg_block = self.0.register_block(); - reg_block + self.regs() .out_link() .modify(|_, w| unsafe { w.outlink_addr().bits(address) }); } @@ -67,29 +75,25 @@ impl RegisterAccess for AnyI2sDmaTxChannel { } fn start(&self) { - let reg_block = self.0.register_block(); - reg_block + self.regs() .out_link() .modify(|_, w| w.outlink_start().set_bit()); } fn stop(&self) { - let reg_block = self.0.register_block(); - reg_block + self.regs() .out_link() .modify(|_, w| w.outlink_stop().set_bit()); } fn restart(&self) { - let reg_block = self.0.register_block(); - reg_block + self.regs() .out_link() .modify(|_, w| w.outlink_restart().set_bit()); } fn set_check_owner(&self, check_owner: Option) { - let reg_block = self.0.register_block(); - reg_block + self.regs() .lc_conf() .modify(|_, w| w.check_owner().bit(check_owner.unwrap_or(true))); } @@ -100,8 +104,8 @@ impl RegisterAccess for AnyI2sDmaTxChannel { #[cfg(psram_dma)] fn set_ext_mem_block_size(&self, size: DmaExtMemBKSize) { - let spi = self.0.register_block(); - spi.lc_conf() + self.regs() + .lc_conf() .modify(|_, w| unsafe { w.ext_mem_bk_size().bits(size as u8) }); } @@ -113,15 +117,13 @@ impl RegisterAccess for AnyI2sDmaTxChannel { impl TxRegisterAccess for AnyI2sDmaTxChannel { fn set_auto_write_back(&self, enable: bool) { - let reg_block = self.0.register_block(); - reg_block + self.regs() .lc_conf() .modify(|_, w| w.out_auto_wrback().bit(enable)); } fn last_dscr_address(&self) -> usize { - let reg_block = self.0.register_block(); - reg_block + self.regs() .out_eof_des_addr() .read() .out_eof_des_addr() @@ -139,8 +141,7 @@ impl TxRegisterAccess for AnyI2sDmaTxChannel { impl InterruptAccess for AnyI2sDmaTxChannel { fn enable_listen(&self, interrupts: EnumSet, enable: bool) { - let reg_block = self.0.register_block(); - reg_block.int_ena().modify(|_, w| { + self.regs().int_ena().modify(|_, w| { for interrupt in interrupts { match interrupt { DmaTxInterrupt::TotalEof => w.out_total_eof().bit(enable), @@ -156,8 +157,7 @@ impl InterruptAccess for AnyI2sDmaTxChannel { fn is_listening(&self) -> EnumSet { let mut result = EnumSet::new(); - let reg_block = self.0.register_block(); - let int_ena = reg_block.int_ena().read(); + let int_ena = self.regs().int_ena().read(); if int_ena.out_total_eof().bit_is_set() { result |= DmaTxInterrupt::TotalEof; } @@ -177,8 +177,7 @@ impl InterruptAccess for AnyI2sDmaTxChannel { fn pending_interrupts(&self) -> EnumSet { let mut result = EnumSet::new(); - let reg_block = self.0.register_block(); - let int_raw = reg_block.int_raw().read(); + let int_raw = self.regs().int_raw().read(); if int_raw.out_total_eof().bit_is_set() { result |= DmaTxInterrupt::TotalEof; } @@ -196,8 +195,7 @@ impl InterruptAccess for AnyI2sDmaTxChannel { } fn clear(&self, interrupts: impl Into>) { - let reg_block = self.0.register_block(); - reg_block.int_clr().write(|w| { + self.regs().int_clr().write(|w| { for interrupt in interrupts.into() { match interrupt { DmaTxInterrupt::TotalEof => w.out_total_eof().clear_bit_by_one(), @@ -225,23 +223,20 @@ impl InterruptAccess for AnyI2sDmaTxChannel { impl RegisterAccess for AnyI2sDmaRxChannel { fn reset(&self) { - let reg_block = self.0.register_block(); - reg_block.lc_conf().modify(|_, w| w.in_rst().set_bit()); - reg_block.lc_conf().modify(|_, w| w.in_rst().clear_bit()); + self.regs().lc_conf().modify(|_, w| w.in_rst().set_bit()); + self.regs().lc_conf().modify(|_, w| w.in_rst().clear_bit()); } fn set_burst_mode(&self, _burst_mode: BurstConfig) {} fn set_descr_burst_mode(&self, burst_mode: bool) { - let reg_block = self.0.register_block(); - reg_block + self.regs() .lc_conf() .modify(|_, w| w.indscr_burst_en().bit(burst_mode)); } fn set_link_addr(&self, address: u32) { - let reg_block = self.0.register_block(); - reg_block + self.regs() .in_link() .modify(|_, w| unsafe { w.inlink_addr().bits(address) }); } @@ -251,27 +246,25 @@ impl RegisterAccess for AnyI2sDmaRxChannel { } fn start(&self) { - let reg_block = self.0.register_block(); - reg_block + self.regs() .in_link() .modify(|_, w| w.inlink_start().set_bit()); } fn stop(&self) { - let reg_block = self.0.register_block(); - reg_block.in_link().modify(|_, w| w.inlink_stop().set_bit()); + self.regs() + .in_link() + .modify(|_, w| w.inlink_stop().set_bit()); } fn restart(&self) { - let reg_block = self.0.register_block(); - reg_block + self.regs() .in_link() .modify(|_, w| w.inlink_restart().set_bit()); } fn set_check_owner(&self, check_owner: Option) { - let reg_block = self.0.register_block(); - reg_block + self.regs() .lc_conf() .modify(|_, w| w.check_owner().bit(check_owner.unwrap_or(true))); } @@ -282,8 +275,8 @@ impl RegisterAccess for AnyI2sDmaRxChannel { #[cfg(psram_dma)] fn set_ext_mem_block_size(&self, size: DmaExtMemBKSize) { - let spi = self.0.register_block(); - spi.lc_conf() + self.regs() + .lc_conf() .modify(|_, w| unsafe { w.ext_mem_bk_size().bits(size as u8) }); } @@ -305,8 +298,7 @@ impl RxRegisterAccess for AnyI2sDmaRxChannel { impl InterruptAccess for AnyI2sDmaRxChannel { fn enable_listen(&self, interrupts: EnumSet, enable: bool) { - let reg_block = self.0.register_block(); - reg_block.int_ena().modify(|_, w| { + self.regs().int_ena().modify(|_, w| { for interrupt in interrupts { match interrupt { DmaRxInterrupt::SuccessfulEof => w.in_suc_eof().bit(enable), @@ -323,8 +315,7 @@ impl InterruptAccess for AnyI2sDmaRxChannel { fn is_listening(&self) -> EnumSet { let mut result = EnumSet::new(); - let reg_block = self.0.register_block(); - let int_ena = reg_block.int_ena().read(); + let int_ena = self.regs().int_ena().read(); if int_ena.in_dscr_err().bit_is_set() { result |= DmaRxInterrupt::DescriptorError; } @@ -347,8 +338,7 @@ impl InterruptAccess for AnyI2sDmaRxChannel { fn pending_interrupts(&self) -> EnumSet { let mut result = EnumSet::new(); - let reg_block = self.0.register_block(); - let int_raw = reg_block.int_raw().read(); + let int_raw = self.regs().int_raw().read(); if int_raw.in_dscr_err().bit_is_set() { result |= DmaRxInterrupt::DescriptorError; } @@ -369,8 +359,7 @@ impl InterruptAccess for AnyI2sDmaRxChannel { } fn clear(&self, interrupts: impl Into>) { - let reg_block = self.0.register_block(); - reg_block.int_clr().write(|w| { + self.regs().int_clr().write(|w| { for interrupt in interrupts.into() { match interrupt { DmaRxInterrupt::SuccessfulEof => w.in_suc_eof().clear_bit_by_one(), diff --git a/esp-hal/src/dma/pdma/spi.rs b/esp-hal/src/dma/pdma/spi.rs index 8e6f8b69f48..4dea569d3c6 100644 --- a/esp-hal/src/dma/pdma/spi.rs +++ b/esp-hal/src/dma/pdma/spi.rs @@ -9,6 +9,12 @@ pub(super) type SpiRegisterBlock = crate::pac::spi2::RegisterBlock; #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub struct AnySpiDmaRxChannel(pub(crate) AnySpiDmaChannel); +impl AnySpiDmaRxChannel { + fn regs(&self) -> &SpiRegisterBlock { + self.0.register_block() + } +} + impl crate::private::Sealed for AnySpiDmaRxChannel {} impl DmaRxChannel for AnySpiDmaRxChannel {} impl Peripheral for AnySpiDmaRxChannel { @@ -24,6 +30,12 @@ impl Peripheral for AnySpiDmaRxChannel { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub struct AnySpiDmaTxChannel(pub(crate) AnySpiDmaChannel); +impl AnySpiDmaTxChannel { + fn regs(&self) -> &SpiRegisterBlock { + self.0.register_block() + } +} + impl crate::private::Sealed for AnySpiDmaTxChannel {} impl DmaTxChannel for AnySpiDmaTxChannel {} impl Peripheral for AnySpiDmaTxChannel { @@ -36,20 +48,21 @@ impl Peripheral for AnySpiDmaTxChannel { impl RegisterAccess for AnySpiDmaTxChannel { fn reset(&self) { - let spi = self.0.register_block(); - spi.dma_conf().modify(|_, w| w.out_rst().set_bit()); - spi.dma_conf().modify(|_, w| w.out_rst().clear_bit()); + self.regs().dma_conf().modify(|_, w| w.out_rst().set_bit()); + self.regs() + .dma_conf() + .modify(|_, w| w.out_rst().clear_bit()); } fn set_burst_mode(&self, burst_mode: BurstConfig) { - let spi = self.0.register_block(); - spi.dma_conf() + self.regs() + .dma_conf() .modify(|_, w| w.out_data_burst_en().bit(burst_mode.is_burst_enabled())); } fn set_descr_burst_mode(&self, burst_mode: bool) { - let spi = self.0.register_block(); - spi.dma_conf() + self.regs() + .dma_conf() .modify(|_, w| w.outdscr_burst_en().bit(burst_mode)); } @@ -58,25 +71,26 @@ impl RegisterAccess for AnySpiDmaTxChannel { } fn set_link_addr(&self, address: u32) { - let spi = self.0.register_block(); - spi.dma_out_link() + self.regs() + .dma_out_link() .modify(|_, w| unsafe { w.outlink_addr().bits(address) }); } fn start(&self) { - let spi = self.0.register_block(); - spi.dma_out_link() + self.regs() + .dma_out_link() .modify(|_, w| w.outlink_start().set_bit()); } fn stop(&self) { - let spi = self.0.register_block(); - spi.dma_out_link().modify(|_, w| w.outlink_stop().set_bit()); + self.regs() + .dma_out_link() + .modify(|_, w| w.outlink_stop().set_bit()); } fn restart(&self) { - let spi = self.0.register_block(); - spi.dma_out_link() + self.regs() + .dma_out_link() .modify(|_, w| w.outlink_restart().set_bit()); } @@ -92,8 +106,8 @@ impl RegisterAccess for AnySpiDmaTxChannel { #[cfg(psram_dma)] fn set_ext_mem_block_size(&self, size: DmaExtMemBKSize) { - let spi = self.0.register_block(); - spi.dma_conf() + self.regs() + .dma_conf() .modify(|_, w| unsafe { w.ext_mem_bk_size().bits(size as u8) }); } @@ -110,8 +124,11 @@ impl TxRegisterAccess for AnySpiDmaTxChannel { } fn last_dscr_address(&self) -> usize { - let spi = self.0.register_block(); - spi.out_eof_des_addr().read().dma_out_eof_des_addr().bits() as usize + self.regs() + .out_eof_des_addr() + .read() + .dma_out_eof_des_addr() + .bits() as usize } fn peripheral_interrupt(&self) -> Option { @@ -125,8 +142,7 @@ impl TxRegisterAccess for AnySpiDmaTxChannel { impl InterruptAccess for AnySpiDmaTxChannel { fn enable_listen(&self, interrupts: EnumSet, enable: bool) { - let reg_block = self.0.register_block(); - reg_block.dma_int_ena().modify(|_, w| { + self.regs().dma_int_ena().modify(|_, w| { for interrupt in interrupts { match interrupt { DmaTxInterrupt::TotalEof => w.out_total_eof().bit(enable), @@ -142,8 +158,7 @@ impl InterruptAccess for AnySpiDmaTxChannel { fn is_listening(&self) -> EnumSet { let mut result = EnumSet::new(); - let spi = self.0.register_block(); - let int_ena = spi.dma_int_ena().read(); + let int_ena = self.regs().dma_int_ena().read(); if int_ena.out_total_eof().bit_is_set() { result |= DmaTxInterrupt::TotalEof; } @@ -161,8 +176,7 @@ impl InterruptAccess for AnySpiDmaTxChannel { } fn clear(&self, interrupts: impl Into>) { - let spi = self.0.register_block(); - spi.dma_int_clr().write(|w| { + self.regs().dma_int_clr().write(|w| { for interrupt in interrupts.into() { match interrupt { DmaTxInterrupt::TotalEof => w.out_total_eof().clear_bit_by_one(), @@ -178,8 +192,7 @@ impl InterruptAccess for AnySpiDmaTxChannel { fn pending_interrupts(&self) -> EnumSet { let mut result = EnumSet::new(); - let spi = self.0.register_block(); - let int_raw = spi.dma_int_raw().read(); + let int_raw = self.regs().dma_int_raw().read(); if int_raw.out_total_eof().bit_is_set() { result |= DmaTxInterrupt::TotalEof; } @@ -211,16 +224,15 @@ impl InterruptAccess for AnySpiDmaTxChannel { impl RegisterAccess for AnySpiDmaRxChannel { fn reset(&self) { - let spi = self.0.register_block(); - spi.dma_conf().modify(|_, w| w.in_rst().set_bit()); - spi.dma_conf().modify(|_, w| w.in_rst().clear_bit()); + self.regs().dma_conf().modify(|_, w| w.in_rst().set_bit()); + self.regs().dma_conf().modify(|_, w| w.in_rst().clear_bit()); } fn set_burst_mode(&self, _burst_mode: BurstConfig) {} fn set_descr_burst_mode(&self, burst_mode: bool) { - let spi = self.0.register_block(); - spi.dma_conf() + self.regs() + .dma_conf() .modify(|_, w| w.indscr_burst_en().bit(burst_mode)); } @@ -229,24 +241,26 @@ impl RegisterAccess for AnySpiDmaRxChannel { } fn set_link_addr(&self, address: u32) { - let spi = self.0.register_block(); - spi.dma_in_link() + self.regs() + .dma_in_link() .modify(|_, w| unsafe { w.inlink_addr().bits(address) }); } fn start(&self) { - let spi = self.0.register_block(); - spi.dma_in_link().modify(|_, w| w.inlink_start().set_bit()); + self.regs() + .dma_in_link() + .modify(|_, w| w.inlink_start().set_bit()); } fn stop(&self) { - let spi = self.0.register_block(); - spi.dma_in_link().modify(|_, w| w.inlink_stop().set_bit()); + self.regs() + .dma_in_link() + .modify(|_, w| w.inlink_stop().set_bit()); } fn restart(&self) { - let spi = self.0.register_block(); - spi.dma_in_link() + self.regs() + .dma_in_link() .modify(|_, w| w.inlink_restart().set_bit()); } @@ -262,8 +276,8 @@ impl RegisterAccess for AnySpiDmaRxChannel { #[cfg(psram_dma)] fn set_ext_mem_block_size(&self, size: DmaExtMemBKSize) { - let spi = self.0.register_block(); - spi.dma_conf() + self.regs() + .dma_conf() .modify(|_, w| unsafe { w.ext_mem_bk_size().bits(size as u8) }); } @@ -285,8 +299,7 @@ impl RxRegisterAccess for AnySpiDmaRxChannel { impl InterruptAccess for AnySpiDmaRxChannel { fn enable_listen(&self, interrupts: EnumSet, enable: bool) { - let reg_block = self.0.register_block(); - reg_block.dma_int_ena().modify(|_, w| { + self.regs().dma_int_ena().modify(|_, w| { for interrupt in interrupts { match interrupt { DmaRxInterrupt::SuccessfulEof => w.in_suc_eof().bit(enable), @@ -303,8 +316,7 @@ impl InterruptAccess for AnySpiDmaRxChannel { fn is_listening(&self) -> EnumSet { let mut result = EnumSet::new(); - let spi = self.0.register_block(); - let int_ena = spi.dma_int_ena().read(); + let int_ena = self.regs().dma_int_ena().read(); if int_ena.inlink_dscr_error().bit_is_set() { result |= DmaRxInterrupt::DescriptorError; } @@ -325,8 +337,7 @@ impl InterruptAccess for AnySpiDmaRxChannel { } fn clear(&self, interrupts: impl Into>) { - let spi = self.0.register_block(); - spi.dma_int_clr().modify(|_, w| { + self.regs().dma_int_clr().modify(|_, w| { for interrupt in interrupts.into() { match interrupt { DmaRxInterrupt::SuccessfulEof => w.in_suc_eof().clear_bit_by_one(), @@ -343,8 +354,7 @@ impl InterruptAccess for AnySpiDmaRxChannel { fn pending_interrupts(&self) -> EnumSet { let mut result = EnumSet::new(); - let spi = self.0.register_block(); - let int_raw = spi.dma_int_raw().read(); + let int_raw = self.regs().dma_int_raw().read(); if int_raw.inlink_dscr_error().bit_is_set() { result |= DmaRxInterrupt::DescriptorError; } diff --git a/esp-hal/src/ecc.rs b/esp-hal/src/ecc.rs index e7c07cd6ac5..cd2aab5b6d9 100644 --- a/esp-hal/src/ecc.rs +++ b/esp-hal/src/ecc.rs @@ -29,14 +29,17 @@ use core::marker::PhantomData; use crate::{ interrupt::{InterruptConfigurable, InterruptHandler}, + pac, peripheral::{Peripheral, PeripheralRef}, peripherals::{Interrupt, ECC}, reg_access::{AlignmentHelper, SocDependentEndianess}, system::{self, GenericPeripheralGuard}, + Blocking, + DriverMode, }; /// The ECC Accelerator driver instance -pub struct Ecc<'d, Dm: crate::DriverMode> { +pub struct Ecc<'d, Dm: DriverMode> { ecc: PeripheralRef<'d, ECC>, alignment_helper: AlignmentHelper, phantom: PhantomData, @@ -97,8 +100,8 @@ pub enum WorkMode { ModDiv = 11, } -impl<'d> Ecc<'d, crate::Blocking> { - /// Create a new instance in [crate::Blocking] mode. +impl<'d> Ecc<'d, Blocking> { + /// Create a new instance in [Blocking] mode. pub fn new(ecc: impl Peripheral

+ 'd) -> Self { crate::into_ref!(ecc); @@ -113,9 +116,9 @@ impl<'d> Ecc<'d, crate::Blocking> { } } -impl crate::private::Sealed for Ecc<'_, crate::Blocking> {} +impl crate::private::Sealed for Ecc<'_, Blocking> {} -impl InterruptConfigurable for Ecc<'_, crate::Blocking> { +impl InterruptConfigurable for Ecc<'_, Blocking> { fn set_interrupt_handler(&mut self, handler: InterruptHandler) { for core in crate::Cpu::other() { crate::interrupt::disable(core, Interrupt::ECC); @@ -125,10 +128,14 @@ impl InterruptConfigurable for Ecc<'_, crate::Blocking> { } } -impl Ecc<'_, Dm> { +impl Ecc<'_, Dm> { + fn regs(&self) -> &pac::ecc::RegisterBlock { + self.ecc.register_block() + } + /// Resets the ECC peripheral. pub fn reset(&mut self) { - self.ecc.mult_conf().reset() + self.regs().mult_conf().reset() } /// # Base point multiplication @@ -168,15 +175,21 @@ impl Ecc<'_, Dm> { let mut tmp = [0_u8; 32]; self.reverse_words(k, &mut tmp); self.alignment_helper - .volatile_write_regset(self.ecc.k_mem(0).as_ptr(), tmp.as_ref(), 8); + .volatile_write_regset(self.regs().k_mem(0).as_ptr(), tmp.as_ref(), 8); self.reverse_words(x, &mut tmp); - self.alignment_helper - .volatile_write_regset(self.ecc.px_mem(0).as_ptr(), tmp.as_ref(), 8); + self.alignment_helper.volatile_write_regset( + self.regs().px_mem(0).as_ptr(), + tmp.as_ref(), + 8, + ); self.reverse_words(y, &mut tmp); - self.alignment_helper - .volatile_write_regset(self.ecc.py_mem(0).as_ptr(), tmp.as_ref(), 8); + self.alignment_helper.volatile_write_regset( + self.regs().py_mem(0).as_ptr(), + tmp.as_ref(), + 8, + ); - self.ecc.mult_conf().write(|w| unsafe { + self.regs().mult_conf().write(|w| unsafe { w.work_mode() .bits(mode as u8) .key_length() @@ -189,10 +202,10 @@ impl Ecc<'_, Dm> { while self.is_busy() {} self.alignment_helper - .volatile_read_regset(self.ecc.px_mem(0).as_ptr(), &mut tmp, 8); + .volatile_read_regset(self.regs().px_mem(0).as_ptr(), &mut tmp, 8); self.reverse_words(tmp.as_ref(), x); self.alignment_helper - .volatile_read_regset(self.ecc.py_mem(0).as_ptr(), &mut tmp, 8); + .volatile_read_regset(self.regs().py_mem(0).as_ptr(), &mut tmp, 8); self.reverse_words(tmp.as_ref(), y); Ok(()) @@ -235,12 +248,15 @@ impl Ecc<'_, Dm> { let mut tmp = [0_u8; 32]; self.reverse_words(k, &mut tmp); self.alignment_helper - .volatile_write_regset(self.ecc.k_mem(0).as_ptr(), tmp.as_ref(), 8); + .volatile_write_regset(self.regs().k_mem(0).as_ptr(), tmp.as_ref(), 8); self.reverse_words(y, &mut tmp); - self.alignment_helper - .volatile_write_regset(self.ecc.py_mem(0).as_ptr(), tmp.as_ref(), 8); + self.alignment_helper.volatile_write_regset( + self.regs().py_mem(0).as_ptr(), + tmp.as_ref(), + 8, + ); - self.ecc.mult_conf().write(|w| unsafe { + self.regs().mult_conf().write(|w| unsafe { w.work_mode() .bits(mode as u8) .key_length() @@ -253,7 +269,7 @@ impl Ecc<'_, Dm> { while self.is_busy() {} self.alignment_helper - .volatile_read_regset(self.ecc.py_mem(0).as_ptr(), &mut tmp, 8); + .volatile_read_regset(self.regs().py_mem(0).as_ptr(), &mut tmp, 8); self.reverse_words(tmp.as_ref(), y); Ok(()) @@ -295,13 +311,19 @@ impl Ecc<'_, Dm> { let mut tmp = [0_u8; 32]; self.reverse_words(x, &mut tmp); - self.alignment_helper - .volatile_write_regset(self.ecc.px_mem(0).as_ptr(), tmp.as_ref(), 8); + self.alignment_helper.volatile_write_regset( + self.regs().px_mem(0).as_ptr(), + tmp.as_ref(), + 8, + ); self.reverse_words(y, &mut tmp); - self.alignment_helper - .volatile_write_regset(self.ecc.py_mem(0).as_ptr(), tmp.as_ref(), 8); + self.alignment_helper.volatile_write_regset( + self.regs().py_mem(0).as_ptr(), + tmp.as_ref(), + 8, + ); - self.ecc.mult_conf().write(|w| unsafe { + self.regs().mult_conf().write(|w| unsafe { w.work_mode() .bits(mode as u8) .key_length() @@ -313,8 +335,8 @@ impl Ecc<'_, Dm> { // wait for interrupt while self.is_busy() {} - if !self.ecc.mult_conf().read().verification_result().bit() { - self.ecc.mult_conf().reset(); + if !self.regs().mult_conf().read().verification_result().bit() { + self.regs().mult_conf().reset(); return Err(Error::PointNotOnSelectedCurve); } @@ -363,15 +385,21 @@ impl Ecc<'_, Dm> { let mut tmp = [0_u8; 32]; self.reverse_words(k, &mut tmp); self.alignment_helper - .volatile_write_regset(self.ecc.k_mem(0).as_ptr(), tmp.as_ref(), 8); + .volatile_write_regset(self.regs().k_mem(0).as_ptr(), tmp.as_ref(), 8); self.reverse_words(x, &mut tmp); - self.alignment_helper - .volatile_write_regset(self.ecc.px_mem(0).as_ptr(), tmp.as_ref(), 8); + self.alignment_helper.volatile_write_regset( + self.regs().px_mem(0).as_ptr(), + tmp.as_ref(), + 8, + ); self.reverse_words(y, &mut tmp); - self.alignment_helper - .volatile_write_regset(self.ecc.py_mem(0).as_ptr(), tmp.as_ref(), 8); + self.alignment_helper.volatile_write_regset( + self.regs().py_mem(0).as_ptr(), + tmp.as_ref(), + 8, + ); - self.ecc.mult_conf().write(|w| unsafe { + self.regs().mult_conf().write(|w| unsafe { w.work_mode() .bits(mode as u8) .key_length() @@ -383,16 +411,16 @@ impl Ecc<'_, Dm> { // wait for interrupt while self.is_busy() {} - if !self.ecc.mult_conf().read().verification_result().bit() { - self.ecc.mult_conf().reset(); + if !self.regs().mult_conf().read().verification_result().bit() { + self.regs().mult_conf().reset(); return Err(Error::PointNotOnSelectedCurve); } self.alignment_helper - .volatile_read_regset(self.ecc.px_mem(0).as_ptr(), &mut tmp, 8); + .volatile_read_regset(self.regs().px_mem(0).as_ptr(), &mut tmp, 8); self.reverse_words(tmp.as_ref(), x); self.alignment_helper - .volatile_read_regset(self.ecc.py_mem(0).as_ptr(), &mut tmp, 8); + .volatile_read_regset(self.regs().py_mem(0).as_ptr(), &mut tmp, 8); self.reverse_words(tmp.as_ref(), y); Ok(()) @@ -446,15 +474,21 @@ impl Ecc<'_, Dm> { let mut tmp = [0_u8; 32]; self.reverse_words(k, &mut tmp); self.alignment_helper - .volatile_write_regset(self.ecc.k_mem(0).as_ptr(), tmp.as_ref(), 8); + .volatile_write_regset(self.regs().k_mem(0).as_ptr(), tmp.as_ref(), 8); self.reverse_words(px, &mut tmp); - self.alignment_helper - .volatile_write_regset(self.ecc.px_mem(0).as_ptr(), tmp.as_ref(), 8); + self.alignment_helper.volatile_write_regset( + self.regs().px_mem(0).as_ptr(), + tmp.as_ref(), + 8, + ); self.reverse_words(py, &mut tmp); - self.alignment_helper - .volatile_write_regset(self.ecc.py_mem(0).as_ptr(), tmp.as_ref(), 8); + self.alignment_helper.volatile_write_regset( + self.regs().py_mem(0).as_ptr(), + tmp.as_ref(), + 8, + ); - self.ecc.mult_conf().write(|w| unsafe { + self.regs().mult_conf().write(|w| unsafe { w.work_mode() .bits(mode as u8) .key_length() @@ -466,25 +500,25 @@ impl Ecc<'_, Dm> { // wait for interrupt while self.is_busy() {} - if !self.ecc.mult_conf().read().verification_result().bit() { - self.ecc.mult_conf().reset(); + if !self.regs().mult_conf().read().verification_result().bit() { + self.regs().mult_conf().reset(); return Err(Error::PointNotOnSelectedCurve); } self.alignment_helper - .volatile_read_regset(self.ecc.px_mem(0).as_ptr(), &mut tmp, 8); + .volatile_read_regset(self.regs().px_mem(0).as_ptr(), &mut tmp, 8); self.reverse_words(tmp.as_ref(), px); self.alignment_helper - .volatile_read_regset(self.ecc.py_mem(0).as_ptr(), &mut tmp, 8); + .volatile_read_regset(self.regs().py_mem(0).as_ptr(), &mut tmp, 8); self.reverse_words(tmp.as_ref(), py); self.alignment_helper - .volatile_read_regset(self.ecc.qx_mem(0).as_ptr(), &mut tmp, 8); + .volatile_read_regset(self.regs().qx_mem(0).as_ptr(), &mut tmp, 8); self.reverse_words(tmp.as_ref(), qx); self.alignment_helper - .volatile_read_regset(self.ecc.qy_mem(0).as_ptr(), &mut tmp, 8); + .volatile_read_regset(self.regs().qy_mem(0).as_ptr(), &mut tmp, 8); self.reverse_words(tmp.as_ref(), qy); self.alignment_helper - .volatile_read_regset(self.ecc.qz_mem(0).as_ptr(), &mut tmp, 8); + .volatile_read_regset(self.regs().qz_mem(0).as_ptr(), &mut tmp, 8); self.reverse_words(tmp.as_ref(), qz); Ok(()) @@ -527,15 +561,21 @@ impl Ecc<'_, Dm> { let mut tmp = [0_u8; 32]; self.reverse_words(k, &mut tmp); self.alignment_helper - .volatile_write_regset(self.ecc.k_mem(0).as_ptr(), tmp.as_ref(), 8); + .volatile_write_regset(self.regs().k_mem(0).as_ptr(), tmp.as_ref(), 8); self.reverse_words(x, &mut tmp); - self.alignment_helper - .volatile_write_regset(self.ecc.px_mem(0).as_ptr(), tmp.as_ref(), 8); + self.alignment_helper.volatile_write_regset( + self.regs().px_mem(0).as_ptr(), + tmp.as_ref(), + 8, + ); self.reverse_words(y, &mut tmp); - self.alignment_helper - .volatile_write_regset(self.ecc.py_mem(0).as_ptr(), tmp.as_ref(), 8); + self.alignment_helper.volatile_write_regset( + self.regs().py_mem(0).as_ptr(), + tmp.as_ref(), + 8, + ); - self.ecc.mult_conf().write(|w| unsafe { + self.regs().mult_conf().write(|w| unsafe { w.work_mode() .bits(mode as u8) .key_length() @@ -549,23 +589,23 @@ impl Ecc<'_, Dm> { cfg_if::cfg_if! { if #[cfg(not(esp32h2))] { self.alignment_helper - .volatile_read_regset(self.ecc.px_mem(0).as_ptr(), &mut tmp, 8); + .volatile_read_regset(self.regs().px_mem(0).as_ptr(), &mut tmp, 8); self.reverse_words(tmp.as_ref(), x); self.alignment_helper - .volatile_read_regset(self.ecc.py_mem(0).as_ptr(), &mut tmp, 8); + .volatile_read_regset(self.regs().py_mem(0).as_ptr(), &mut tmp, 8); self.reverse_words(tmp.as_ref(), y); self.alignment_helper - .volatile_read_regset(self.ecc.k_mem(0).as_ptr(), &mut tmp, 8); + .volatile_read_regset(self.regs().k_mem(0).as_ptr(), &mut tmp, 8); self.reverse_words(tmp.as_ref(), k); } else { self.alignment_helper - .volatile_read_regset(self.ecc.qx_mem(0).as_ptr(), &mut tmp, 8); + .volatile_read_regset(self.regs().qx_mem(0).as_ptr(), &mut tmp, 8); self.reverse_words(tmp.as_ref(), x); self.alignment_helper - .volatile_read_regset(self.ecc.qy_mem(0).as_ptr(), &mut tmp, 8); + .volatile_read_regset(self.regs().qy_mem(0).as_ptr(), &mut tmp, 8); self.reverse_words(tmp.as_ref(), y); self.alignment_helper - .volatile_read_regset(self.ecc.qz_mem(0).as_ptr(), &mut tmp, 8); + .volatile_read_regset(self.regs().qz_mem(0).as_ptr(), &mut tmp, 8); self.reverse_words(tmp.as_ref(), k); } } @@ -614,26 +654,26 @@ impl Ecc<'_, Dm> { cfg_if::cfg_if! { if #[cfg(not(esp32h2))] { self.alignment_helper - .volatile_write_regset(self.ecc.px_mem(0).as_ptr(), tmp.as_ref(), 8); + .volatile_write_regset(self.regs().px_mem(0).as_ptr(), tmp.as_ref(), 8); self.reverse_words(y, &mut tmp); self.alignment_helper - .volatile_write_regset(self.ecc.py_mem(0).as_ptr(), tmp.as_ref(), 8); + .volatile_write_regset(self.regs().py_mem(0).as_ptr(), tmp.as_ref(), 8); self.reverse_words(z, &mut tmp); self.alignment_helper - .volatile_write_regset(self.ecc.k_mem(0).as_ptr(), tmp.as_ref(), 8); + .volatile_write_regset(self.regs().k_mem(0).as_ptr(), tmp.as_ref(), 8); } else { self.alignment_helper - .volatile_write_regset(self.ecc.qx_mem(0).as_ptr(), tmp.as_ref(), 8); + .volatile_write_regset(self.regs().qx_mem(0).as_ptr(), tmp.as_ref(), 8); self.reverse_words(y, &mut tmp); self.alignment_helper - .volatile_write_regset(self.ecc.qy_mem(0).as_ptr(), tmp.as_ref(), 8); + .volatile_write_regset(self.regs().qy_mem(0).as_ptr(), tmp.as_ref(), 8); self.reverse_words(z, &mut tmp); self.alignment_helper - .volatile_write_regset(self.ecc.qz_mem(0).as_ptr(), tmp.as_ref(), 8); + .volatile_write_regset(self.regs().qz_mem(0).as_ptr(), tmp.as_ref(), 8); } } - self.ecc.mult_conf().write(|w| unsafe { + self.regs().mult_conf().write(|w| unsafe { w.work_mode() .bits(mode as u8) .key_length() @@ -645,8 +685,8 @@ impl Ecc<'_, Dm> { // wait for interrupt while self.is_busy() {} - if !self.ecc.mult_conf().read().verification_result().bit() { - self.ecc.mult_conf().reset(); + if !self.regs().mult_conf().read().verification_result().bit() { + self.regs().mult_conf().reset(); return Err(Error::PointNotOnSelectedCurve); } @@ -694,15 +734,21 @@ impl Ecc<'_, Dm> { let mut tmp = [0_u8; 32]; self.reverse_words(k, &mut tmp); self.alignment_helper - .volatile_write_regset(self.ecc.k_mem(0).as_ptr(), tmp.as_ref(), 8); + .volatile_write_regset(self.regs().k_mem(0).as_ptr(), tmp.as_ref(), 8); self.reverse_words(x, &mut tmp); - self.alignment_helper - .volatile_write_regset(self.ecc.px_mem(0).as_ptr(), tmp.as_ref(), 8); + self.alignment_helper.volatile_write_regset( + self.regs().px_mem(0).as_ptr(), + tmp.as_ref(), + 8, + ); self.reverse_words(y, &mut tmp); - self.alignment_helper - .volatile_write_regset(self.ecc.py_mem(0).as_ptr(), tmp.as_ref(), 8); + self.alignment_helper.volatile_write_regset( + self.regs().py_mem(0).as_ptr(), + tmp.as_ref(), + 8, + ); - self.ecc.mult_conf().write(|w| unsafe { + self.regs().mult_conf().write(|w| unsafe { w.work_mode() .bits(mode as u8) .key_length() @@ -714,36 +760,36 @@ impl Ecc<'_, Dm> { // wait for interrupt while self.is_busy() {} - if !self.ecc.mult_conf().read().verification_result().bit() { - self.ecc.mult_conf().reset(); + if !self.regs().mult_conf().read().verification_result().bit() { + self.regs().mult_conf().reset(); return Err(Error::PointNotOnSelectedCurve); } - if !self.ecc.mult_conf().read().verification_result().bit() { - self.ecc.mult_conf().reset(); + if !self.regs().mult_conf().read().verification_result().bit() { + self.regs().mult_conf().reset(); return Err(Error::PointNotOnSelectedCurve); } cfg_if::cfg_if! { if #[cfg(not(esp32h2))] { self.alignment_helper - .volatile_read_regset(self.ecc.px_mem(0).as_ptr(), &mut tmp, 8); + .volatile_read_regset(self.regs().px_mem(0).as_ptr(), &mut tmp, 8); self.reverse_words(tmp.as_ref(), x); self.alignment_helper - .volatile_read_regset(self.ecc.py_mem(0).as_ptr(), &mut tmp, 8); + .volatile_read_regset(self.regs().py_mem(0).as_ptr(), &mut tmp, 8); self.reverse_words(tmp.as_ref(), y); self.alignment_helper - .volatile_read_regset(self.ecc.k_mem(0).as_ptr(), &mut tmp, 8); + .volatile_read_regset(self.regs().k_mem(0).as_ptr(), &mut tmp, 8); self.reverse_words(tmp.as_ref(), k); } else { self.alignment_helper - .volatile_read_regset(self.ecc.qx_mem(0).as_ptr(), &mut tmp, 8); + .volatile_read_regset(self.regs().qx_mem(0).as_ptr(), &mut tmp, 8); self.reverse_words(tmp.as_ref(), x); self.alignment_helper - .volatile_read_regset(self.ecc.qy_mem(0).as_ptr(), &mut tmp, 8); + .volatile_read_regset(self.regs().qy_mem(0).as_ptr(), &mut tmp, 8); self.reverse_words(tmp.as_ref(), y); self.alignment_helper - .volatile_read_regset(self.ecc.qz_mem(0).as_ptr(), &mut tmp, 8); + .volatile_read_regset(self.regs().qz_mem(0).as_ptr(), &mut tmp, 8); self.reverse_words(tmp.as_ref(), k); } } @@ -809,21 +855,21 @@ impl Ecc<'_, Dm> { tmp[0..px.len()].copy_from_slice(px); self.alignment_helper - .volatile_write_regset(self.ecc.px_mem(0).as_ptr(), &tmp, 8); + .volatile_write_regset(self.regs().px_mem(0).as_ptr(), &tmp, 8); tmp[0..py.len()].copy_from_slice(py); self.alignment_helper - .volatile_write_regset(self.ecc.py_mem(0).as_ptr(), &tmp, 8); + .volatile_write_regset(self.regs().py_mem(0).as_ptr(), &tmp, 8); tmp[0..qx.len()].copy_from_slice(qx); self.alignment_helper - .volatile_write_regset(self.ecc.qx_mem(0).as_ptr(), &tmp, 8); + .volatile_write_regset(self.regs().qx_mem(0).as_ptr(), &tmp, 8); tmp[0..qy.len()].copy_from_slice(qy); self.alignment_helper - .volatile_write_regset(self.ecc.qy_mem(0).as_ptr(), &tmp, 8); + .volatile_write_regset(self.regs().qy_mem(0).as_ptr(), &tmp, 8); tmp[0..qz.len()].copy_from_slice(qz); self.alignment_helper - .volatile_write_regset(self.ecc.qz_mem(0).as_ptr(), &tmp, 8); + .volatile_write_regset(self.regs().qz_mem(0).as_ptr(), &tmp, 8); - self.ecc.mult_conf().write(|w| unsafe { + self.regs().mult_conf().write(|w| unsafe { w.work_mode() .bits(mode as u8) .key_length() @@ -836,23 +882,23 @@ impl Ecc<'_, Dm> { while self.is_busy() {} self.alignment_helper - .volatile_read_regset(self.ecc.px_mem(0).as_ptr(), &mut tmp, 8); + .volatile_read_regset(self.regs().px_mem(0).as_ptr(), &mut tmp, 8); let mut tmp_len = px.len(); px[..].copy_from_slice(&tmp[..tmp_len]); self.alignment_helper - .volatile_read_regset(self.ecc.py_mem(0).as_ptr(), &mut tmp, 8); + .volatile_read_regset(self.regs().py_mem(0).as_ptr(), &mut tmp, 8); tmp_len = py.len(); py[..].copy_from_slice(&tmp[..tmp_len]); self.alignment_helper - .volatile_read_regset(self.ecc.qx_mem(0).as_ptr(), &mut tmp, 8); + .volatile_read_regset(self.regs().qx_mem(0).as_ptr(), &mut tmp, 8); tmp_len = qx.len(); qx[..].copy_from_slice(&tmp[..tmp_len]); self.alignment_helper - .volatile_read_regset(self.ecc.qy_mem(0).as_ptr(), &mut tmp, 8); + .volatile_read_regset(self.regs().qy_mem(0).as_ptr(), &mut tmp, 8); tmp_len = qy.len(); qy[..].copy_from_slice(&tmp[..tmp_len]); self.alignment_helper - .volatile_read_regset(self.ecc.qz_mem(0).as_ptr(), &mut tmp, 8); + .volatile_read_regset(self.regs().qz_mem(0).as_ptr(), &mut tmp, 8); tmp_len = qz.len(); qz[..].copy_from_slice(&tmp[..tmp_len]); @@ -901,12 +947,12 @@ impl Ecc<'_, Dm> { let mut tmp = [0_u8; 32]; tmp[0..a.len()].copy_from_slice(a); self.alignment_helper - .volatile_write_regset(self.ecc.px_mem(0).as_ptr(), &tmp, 8); + .volatile_write_regset(self.regs().px_mem(0).as_ptr(), &tmp, 8); tmp[0..b.len()].copy_from_slice(b); self.alignment_helper - .volatile_write_regset(self.ecc.py_mem(0).as_ptr(), &tmp, 8); + .volatile_write_regset(self.regs().py_mem(0).as_ptr(), &tmp, 8); - self.ecc.mult_conf().write(|w| unsafe { + self.regs().mult_conf().write(|w| unsafe { w.work_mode() .bits(work_mode.clone() as u8) .key_length() @@ -921,7 +967,7 @@ impl Ecc<'_, Dm> { match work_mode { WorkMode::ModAdd | WorkMode::ModSub => { self.alignment_helper.volatile_read_regset( - self.ecc.px_mem(0).as_ptr(), + self.regs().px_mem(0).as_ptr(), &mut tmp, 8, ); @@ -930,7 +976,7 @@ impl Ecc<'_, Dm> { } WorkMode::ModMulti | WorkMode::ModDiv => { self.alignment_helper.volatile_read_regset( - self.ecc.py_mem(0).as_ptr(), + self.regs().py_mem(0).as_ptr(), &mut tmp, 8, ); @@ -944,7 +990,7 @@ impl Ecc<'_, Dm> { } fn is_busy(&self) -> bool { - self.ecc.mult_conf().read().start().bit_is_set() + self.regs().mult_conf().read().start().bit_is_set() } fn reverse_words(&self, src: &[u8], dst: &mut [u8]) { diff --git a/esp-hal/src/hmac.rs b/esp-hal/src/hmac.rs index 31a699248b6..b1ed0412c45 100644 --- a/esp-hal/src/hmac.rs +++ b/esp-hal/src/hmac.rs @@ -37,6 +37,7 @@ use core::convert::Infallible; use crate::{ + pac, peripheral::{Peripheral, PeripheralRef}, peripherals::HMAC, reg_access::{AlignmentHelper, SocDependentEndianess}, @@ -120,13 +121,17 @@ impl<'d> Hmac<'d> { } } + fn regs(&self) -> &pac::hmac::RegisterBlock { + self.hmac.register_block() + } + /// Step 1. Enable HMAC module. /// /// Before these steps, the user shall set the peripheral clocks bits for /// HMAC and SHA peripherals and clear the corresponding peripheral /// reset bits. pub fn init(&mut self) { - self.hmac.set_start().write(|w| w.set_start().set_bit()); + self.regs().set_start().write(|w| w.set_start().set_bit()); self.alignment_helper.reset(); self.byte_written = 64; self.next_command = NextCommand::None; @@ -134,17 +139,17 @@ impl<'d> Hmac<'d> { /// Step 2. Configure HMAC keys and key purposes. pub fn configure(&mut self, m: HmacPurpose, key_id: KeyId) -> nb::Result<(), Error> { - self.hmac + self.regs() .set_para_purpose() .write(|w| unsafe { w.purpose_set().bits(m as u8) }); - self.hmac + self.regs() .set_para_key() .write(|w| unsafe { w.key_set().bits(key_id as u8) }); - self.hmac + self.regs() .set_para_finish() .write(|w| w.set_para_end().set_bit()); - if self.hmac.query_error().read().query_check().bit_is_set() { + if self.regs().query_error().read().query_check().bit_is_set() { return Err(nb::Error::Other(Error::KeyPurposeMismatch)); } @@ -185,21 +190,23 @@ impl<'d> Hmac<'d> { // Checking if the message is one block including padding if msg_len < 64 + 56 { - self.hmac.one_block().write(|w| w.set_one_block().set_bit()); + self.regs() + .one_block() + .write(|w| w.set_one_block().set_bit()); while self.is_busy() {} } self.alignment_helper.volatile_read_regset( #[cfg(esp32s2)] - self.hmac.rd_result_(0).as_ptr(), + self.regs().rd_result_(0).as_ptr(), #[cfg(not(esp32s2))] - self.hmac.rd_result_mem(0).as_ptr(), + self.regs().rd_result_mem(0).as_ptr(), output, core::cmp::min(output.len(), 32) / self.alignment_helper.align_size(), ); - self.hmac + self.regs() .set_result_finish() .write(|w| w.set_result_end().set_bit()); self.byte_written = 64; @@ -208,18 +215,18 @@ impl<'d> Hmac<'d> { } fn is_busy(&mut self) -> bool { - self.hmac.query_busy().read().busy_state().bit_is_set() + self.regs().query_busy().read().busy_state().bit_is_set() } fn next_command(&mut self) { match self.next_command { NextCommand::MessageIng => { - self.hmac + self.regs() .set_message_ing() .write(|w| w.set_text_ing().set_bit()); } NextCommand::MessagePad => { - self.hmac + self.regs() .set_message_pad() .write(|w| w.set_text_pad().set_bit()); } @@ -233,9 +240,9 @@ impl<'d> Hmac<'d> { let (remaining, bound_reached) = self.alignment_helper.aligned_volatile_copy( #[cfg(esp32s2)] - self.hmac.wr_message_(0).as_ptr(), + self.regs().wr_message_(0).as_ptr(), #[cfg(not(esp32s2))] - self.hmac.wr_message_mem(0).as_ptr(), + self.regs().wr_message_mem(0).as_ptr(), incoming, 64 / self.alignment_helper.align_size(), mod_length / self.alignment_helper.align_size(), @@ -246,7 +253,7 @@ impl<'d> Hmac<'d> { .wrapping_add(incoming.len() - remaining.len()); if bound_reached { - self.hmac + self.regs() .set_message_one() .write(|w| w.set_text_one().set_bit()); @@ -267,15 +274,15 @@ impl<'d> Hmac<'d> { let flushed = self.alignment_helper.flush_to( #[cfg(esp32s2)] - self.hmac.wr_message_(0).as_ptr(), + self.regs().wr_message_(0).as_ptr(), #[cfg(not(esp32s2))] - self.hmac.wr_message_mem(0).as_ptr(), + self.regs().wr_message_mem(0).as_ptr(), (self.byte_written % 64) / self.alignment_helper.align_size(), ); self.byte_written = self.byte_written.wrapping_add(flushed); if flushed > 0 && self.byte_written % 64 == 0 { - self.hmac + self.regs() .set_message_one() .write(|w| w.set_text_one().set_bit()); while self.is_busy() {} @@ -293,14 +300,14 @@ impl<'d> Hmac<'d> { let pad_len = 64 - mod_cursor; self.alignment_helper.volatile_write_bytes( #[cfg(esp32s2)] - self.hmac.wr_message_(0).as_ptr(), + self.regs().wr_message_(0).as_ptr(), #[cfg(not(esp32s2))] - self.hmac.wr_message_mem(0).as_ptr(), + self.regs().wr_message_mem(0).as_ptr(), 0_u8, pad_len / self.alignment_helper.align_size(), mod_cursor / self.alignment_helper.align_size(), ); - self.hmac + self.regs() .set_message_one() .write(|w| w.set_text_one().set_bit()); self.byte_written = self.byte_written.wrapping_add(pad_len); @@ -315,9 +322,9 @@ impl<'d> Hmac<'d> { self.alignment_helper.volatile_write_bytes( #[cfg(esp32s2)] - self.hmac.wr_message_(0).as_ptr(), + self.regs().wr_message_(0).as_ptr(), #[cfg(not(esp32s2))] - self.hmac.wr_message_mem(0).as_ptr(), + self.regs().wr_message_mem(0).as_ptr(), 0_u8, pad_len / self.alignment_helper.align_size(), mod_cursor / self.alignment_helper.align_size(), @@ -332,15 +339,14 @@ impl<'d> Hmac<'d> { self.alignment_helper.aligned_volatile_copy( #[cfg(esp32s2)] - self.hmac.wr_message_(0).as_ptr(), + self.regs().wr_message_(0).as_ptr(), #[cfg(not(esp32s2))] - self.hmac.wr_message_mem(0).as_ptr(), + self.regs().wr_message_mem(0).as_ptr(), &len_mem, 64 / self.alignment_helper.align_size(), (64 - core::mem::size_of::()) / self.alignment_helper.align_size(), ); - - self.hmac + self.regs() .set_message_one() .write(|w| w.set_text_one().set_bit()); diff --git a/esp-hal/src/i2c/lp_i2c.rs b/esp-hal/src/i2c/lp_i2c.rs index 2b412a1f131..5add61a3de1 100644 --- a/esp-hal/src/i2c/lp_i2c.rs +++ b/esp-hal/src/i2c/lp_i2c.rs @@ -146,7 +146,10 @@ impl LpI2c { } // Initialize LP I2C HAL */ - me.i2c.clk_conf().modify(|_, w| w.sclk_active().set_bit()); + me.i2c + .register_block() + .clk_conf() + .modify(|_, w| w.sclk_active().set_bit()); // Enable LP I2C controller clock lp_peri @@ -166,7 +169,7 @@ impl LpI2c { .modify(|_, w| w.lp_i2c_clk_sel().clear_bit()); // Initialize LP I2C Master mode - me.i2c.ctr().modify(|_, w| unsafe { + me.i2c.register_block().ctr().modify(|_, w| unsafe { // Clear register w.bits(0); // Use open drain output for SDA and SCL @@ -177,9 +180,12 @@ impl LpI2c { }); // First, reset the fifo buffers - me.i2c.fifo_conf().modify(|_, w| w.nonfifo_en().clear_bit()); + me.i2c + .register_block() + .fifo_conf() + .modify(|_, w| w.nonfifo_en().clear_bit()); - me.i2c.ctr().modify(|_, w| { + me.i2c.register_block().ctr().modify(|_, w| { w.tx_lsb_first().clear_bit(); w.rx_lsb_first().clear_bit() }); @@ -245,45 +251,52 @@ impl LpI2c { // Write data to registers unsafe { - me.i2c.clk_conf().modify(|_, w| { + me.i2c.register_block().clk_conf().modify(|_, w| { w.sclk_sel().clear_bit(); w.sclk_div_num().bits((clkm_div - 1) as u8) }); // scl period me.i2c + .register_block() .scl_low_period() .write(|w| w.scl_low_period().bits(scl_low_period as u16)); - me.i2c.scl_high_period().write(|w| { + me.i2c.register_block().scl_high_period().write(|w| { w.scl_high_period().bits(scl_high_period as u16); w.scl_wait_high_period().bits(scl_wait_high_period as u8) }); // sda sample me.i2c + .register_block() .sda_hold() .write(|w| w.time().bits(sda_hold_time as u16)); me.i2c + .register_block() .sda_sample() .write(|w| w.time().bits(sda_sample_time as u16)); // setup me.i2c + .register_block() .scl_rstart_setup() .write(|w| w.time().bits(scl_rstart_setup_time as u16)); me.i2c + .register_block() .scl_stop_setup() .write(|w| w.time().bits(scl_stop_setup_time as u16)); // hold me.i2c + .register_block() .scl_start_hold() .write(|w| w.time().bits(scl_start_hold_time as u16)); me.i2c + .register_block() .scl_stop_hold() .write(|w| w.time().bits(scl_stop_hold_time as u16)); - me.i2c.to().write(|w| { + me.i2c.register_block().to().write(|w| { w.time_out_en().bit(time_out_en); w.time_out_value().bits(time_out_value.try_into().unwrap()) }); @@ -293,21 +306,28 @@ impl LpI2c { // config me.i2c + .register_block() .filter_cfg() .modify(|_, w| unsafe { w.sda_filter_thres().bits(LP_I2C_FILTER_CYC_NUM_DEF) }); me.i2c + .register_block() .filter_cfg() .modify(|_, w| unsafe { w.scl_filter_thres().bits(LP_I2C_FILTER_CYC_NUM_DEF) }); me.i2c + .register_block() .filter_cfg() .modify(|_, w| w.sda_filter_en().set_bit()); me.i2c + .register_block() .filter_cfg() .modify(|_, w| w.scl_filter_en().set_bit()); // Configure the I2C master to send a NACK when the Rx FIFO count is full - me.i2c.ctr().modify(|_, w| w.rx_full_ack_level().set_bit()); + me.i2c + .register_block() + .ctr() + .modify(|_, w| w.rx_full_ack_level().set_bit()); // Synchronize the config register values to the LP I2C peripheral clock me.lp_i2c_update(); @@ -317,24 +337,31 @@ impl LpI2c { /// Update I2C configuration fn lp_i2c_update(&self) { - self.i2c.ctr().modify(|_, w| w.conf_upgate().set_bit()); + self.i2c + .register_block() + .ctr() + .modify(|_, w| w.conf_upgate().set_bit()); } /// Resets the transmit and receive FIFO buffers. fn reset_fifo(&self) { self.i2c + .register_block() .fifo_conf() .modify(|_, w| w.tx_fifo_rst().set_bit()); self.i2c + .register_block() .fifo_conf() .modify(|_, w| w.tx_fifo_rst().clear_bit()); self.i2c + .register_block() .fifo_conf() .modify(|_, w| w.rx_fifo_rst().set_bit()); self.i2c + .register_block() .fifo_conf() .modify(|_, w| w.rx_fifo_rst().clear_bit()); } diff --git a/esp-hal/src/i2c/master/mod.rs b/esp-hal/src/i2c/master/mod.rs index be4456d03d6..912aa4be958 100644 --- a/esp-hal/src/i2c/master/mod.rs +++ b/esp-hal/src/i2c/master/mod.rs @@ -742,7 +742,7 @@ struct I2cFuture<'a> { #[cfg(not(esp32))] impl<'a> I2cFuture<'a> { pub fn new(event: Event, info: &'a Info, state: &'a State) -> Self { - info.register_block().int_ena().modify(|_, w| { + info.regs().int_ena().modify(|_, w| { let w = match event { Event::EndDetect => w.end_detect().set_bit(), Event::TxComplete => w.trans_complete().set_bit(), @@ -761,7 +761,7 @@ impl<'a> I2cFuture<'a> { } fn event_bit_is_clear(&self) -> bool { - let r = self.info.register_block().int_ena().read(); + let r = self.info.regs().int_ena().read(); match self.event { Event::EndDetect => r.end_detect().bit_is_clear(), @@ -772,7 +772,7 @@ impl<'a> I2cFuture<'a> { } fn check_error(&self) -> Result<(), Error> { - let r = self.info.register_block().int_raw().read(); + let r = self.info.regs().int_raw().read(); if r.arbitration_lost().bit_is_set() { return Err(Error::ArbitrationLost); @@ -784,19 +784,12 @@ impl<'a> I2cFuture<'a> { if r.nack().bit_is_set() { return Err(Error::AcknowledgeCheckFailed(estimate_ack_failed_reason( - self.info.register_block(), + self.info.regs(), ))); } #[cfg(not(esp32))] - if r.trans_complete().bit_is_set() - && self - .info - .register_block() - .sr() - .read() - .resp_rec() - .bit_is_clear() + if r.trans_complete().bit_is_set() && self.info.regs().sr().read().resp_rec().bit_is_clear() { return Err(Error::AcknowledgeCheckFailed( AcknowledgeCheckFailedReason::Data, @@ -982,7 +975,7 @@ impl embedded_hal_async::i2c::I2c for I2c<'_, Async> { } fn async_handler(info: &Info, state: &State) { - let regs = info.register_block(); + let regs = info.regs(); regs.int_ena().modify(|_, w| { w.end_detect().clear_bit(); w.trans_complete().clear_bit(); @@ -1152,13 +1145,13 @@ pub struct Info { impl Info { /// Returns the register block for this I2C instance. - pub fn register_block(&self) -> &RegisterBlock { + pub fn regs(&self) -> &RegisterBlock { unsafe { &*self.register_block } } /// Listen for the given interrupts fn enable_listen(&self, interrupts: EnumSet, enable: bool) { - let reg_block = self.register_block(); + let reg_block = self.regs(); reg_block.int_ena().modify(|_, w| { for interrupt in interrupts { @@ -1175,7 +1168,7 @@ impl Info { fn interrupts(&self) -> EnumSet { let mut res = EnumSet::new(); - let reg_block = self.register_block(); + let reg_block = self.regs(); let ints = reg_block.int_raw().read(); @@ -1194,7 +1187,7 @@ impl Info { } fn clear_interrupts(&self, interrupts: EnumSet) { - let reg_block = self.register_block(); + let reg_block = self.regs(); reg_block.int_clr().write(|w| { for interrupt in interrupts { @@ -1239,14 +1232,14 @@ struct Driver<'a> { } impl Driver<'_> { - fn register_block(&self) -> &RegisterBlock { - self.info.register_block() + fn regs(&self) -> &RegisterBlock { + self.info.regs() } /// Configures the I2C peripheral with the specified frequency, clocks, and /// optional timeout. fn setup(&self, config: &Config) -> Result<(), ConfigError> { - self.register_block().ctr().write(|w| { + self.regs().ctr().write(|w| { // Set I2C controller to master mode w.ms_mode().set_bit(); // Use open drain output for SDA and SCL @@ -1260,13 +1253,11 @@ impl Driver<'_> { }); #[cfg(esp32s2)] - self.register_block() - .ctr() - .modify(|_, w| w.ref_always_on().set_bit()); + self.regs().ctr().modify(|_, w| w.ref_always_on().set_bit()); // Configure filter // FIXME if we ever change this we need to adapt `set_frequency` for ESP32 - set_filter(self.register_block(), Some(7), Some(7)); + set_filter(self.regs(), Some(7), Some(7)); // Configure frequency let clocks = Clocks::get(); @@ -1295,12 +1286,10 @@ impl Driver<'_> { // (the option to reset the FSM is not available // for the ESP32) #[cfg(not(esp32))] - self.register_block() - .ctr() - .modify(|_, w| w.fsm_rst().set_bit()); + self.regs().ctr().modify(|_, w| w.fsm_rst().set_bit()); // Clear all I2C interrupts - self.register_block() + self.regs() .int_clr() .write(|w| unsafe { w.bits(I2C_LL_INTR_MASK) }); @@ -1314,7 +1303,7 @@ impl Driver<'_> { /// Resets the I2C peripheral's command registers fn reset_command_list(&self) { // Confirm that all commands that were configured were actually executed - for cmd in self.register_block().comd_iter() { + for cmd in self.regs().comd_iter() { cmd.reset(); } } @@ -1384,7 +1373,7 @@ impl Driver<'_> { let scl_stop_hold_time = hold; configure_clock( - self.register_block(), + self.regs(), 0, scl_low_period, scl_high_period, @@ -1446,7 +1435,7 @@ impl Driver<'_> { }); configure_clock( - self.register_block(), + self.regs(), 0, scl_low_period, scl_high_period, @@ -1529,7 +1518,7 @@ impl Driver<'_> { }; configure_clock( - self.register_block(), + self.regs(), clkm_div, scl_low_period, scl_high_period, @@ -1555,7 +1544,7 @@ impl Driver<'_> { self.wait_for_completion(false).await?; for byte in buffer.iter_mut() { - *byte = read_fifo(self.register_block()); + *byte = read_fifo(self.regs()); } Ok(()) @@ -1610,10 +1599,7 @@ impl Driver<'_> { // Load address and R/W bit into FIFO match addr { I2cAddress::SevenBit(addr) => { - write_fifo( - self.register_block(), - (addr << 1) | OperationType::Write as u8, - ); + write_fifo(self.regs(), (addr << 1) | OperationType::Write as u8); } } } @@ -1693,10 +1679,7 @@ impl Driver<'_> { // Load address and R/W bit into FIFO match addr { I2cAddress::SevenBit(addr) => { - write_fifo( - self.register_block(), - (addr << 1) | OperationType::Read as u8, - ); + write_fifo(self.regs(), (addr << 1) | OperationType::Read as u8); } } } @@ -1713,13 +1696,13 @@ impl Driver<'_> { loop { self.check_errors()?; - let reg = self.register_block().fifo_st().read(); + let reg = self.regs().fifo_st().read(); if reg.rxfifo_raddr().bits() != reg.rxfifo_waddr().bits() { break; } } - *byte = read_fifo(self.register_block()); + *byte = read_fifo(self.regs()); } Ok(()) @@ -1745,7 +1728,7 @@ impl Driver<'_> { // FIXME: Handle case where less data has been provided by the slave than // requested? Or is this prevented from a protocol perspective? for byte in buffer.iter_mut() { - *byte = read_fifo(self.register_block()); + *byte = read_fifo(self.regs()); } Ok(()) @@ -1753,7 +1736,7 @@ impl Driver<'_> { /// Clears all pending interrupts for the I2C peripheral. fn clear_all_interrupts(&self) { - self.register_block() + self.regs() .int_clr() .write(|w| unsafe { w.bits(I2C_LL_INTR_MASK) }); } @@ -1765,7 +1748,7 @@ impl Driver<'_> { } for b in bytes { - write_fifo(self.register_block(), *b); + write_fifo(self.regs(), *b); self.check_errors()?; } @@ -1780,7 +1763,7 @@ impl Driver<'_> { I2cFuture::new(Event::TxFifoWatermark, self.info, self.state).await?; - self.register_block() + self.regs() .int_clr() .write(|w| w.txfifo_wm().clear_bit_by_one()); @@ -1790,7 +1773,7 @@ impl Driver<'_> { break Ok(()); } - write_fifo(self.register_block(), bytes[index]); + write_fifo(self.regs(), bytes[index]); index += 1; } } @@ -1825,7 +1808,7 @@ impl Driver<'_> { let mut tout = MAX_ITERATIONS / 10; // adjust the timeout because we are yielding in the loop loop { - let interrupts = self.register_block().int_raw().read(); + let interrupts = self.regs().int_raw().read(); self.check_errors()?; @@ -1853,7 +1836,7 @@ impl Driver<'_> { fn wait_for_completion_blocking(&self, end_only: bool) -> Result<(), Error> { let mut tout = MAX_ITERATIONS; loop { - let interrupts = self.register_block().int_raw().read(); + let interrupts = self.regs().int_raw().read(); self.check_errors()?; @@ -1880,7 +1863,7 @@ impl Driver<'_> { // NOTE: on esp32 executing the end command generates the end_detect interrupt // but does not seem to clear the done bit! So we don't check the done // status of an end command - for cmd_reg in self.register_block().comd_iter() { + for cmd_reg in self.regs().comd_iter() { let cmd = cmd_reg.read(); if cmd.bits() != 0x0 && !cmd.opcode().is_end() && !cmd.command_done().bit_is_set() { @@ -1899,7 +1882,7 @@ impl Driver<'_> { /// by resetting the I2C peripheral to clear the error condition and then /// returns an appropriate error. fn check_errors(&self) -> Result<(), Error> { - let interrupts = self.register_block().int_raw().read(); + let interrupts = self.regs().int_raw().read(); // The ESP32 variant has a slightly different interrupt naming // scheme! @@ -1909,7 +1892,7 @@ impl Driver<'_> { let retval = if interrupts.time_out().bit_is_set() { Err(Error::Timeout) } else if interrupts.nack().bit_is_set() { - Err(Error::AcknowledgeCheckFailed(estimate_ack_failed_reason(self.register_block()))) + Err(Error::AcknowledgeCheckFailed(estimate_ack_failed_reason(self.regs()))) } else if interrupts.arbitration_lost().bit_is_set() { Err(Error::ArbitrationLost) } else { @@ -1920,10 +1903,10 @@ impl Driver<'_> { let retval = if interrupts.time_out().bit_is_set() { Err(Error::Timeout) } else if interrupts.nack().bit_is_set() { - Err(Error::AcknowledgeCheckFailed(estimate_ack_failed_reason(self.register_block()))) + Err(Error::AcknowledgeCheckFailed(estimate_ack_failed_reason(self.regs()))) } else if interrupts.arbitration_lost().bit_is_set() { Err(Error::ArbitrationLost) - } else if interrupts.trans_complete().bit_is_set() && self.register_block().sr().read().resp_rec().bit_is_clear() { + } else if interrupts.trans_complete().bit_is_set() && self.regs().sr().read().resp_rec().bit_is_clear() { Err(Error::AcknowledgeCheckFailed(AcknowledgeCheckFailedReason::Data)) } else { Ok(()) @@ -1951,43 +1934,26 @@ impl Driver<'_> { // Ensure that the configuration of the peripheral is correctly propagated // (only necessary for C2, C3, C6, H2 and S3 variant) #[cfg(any(esp32c2, esp32c3, esp32c6, esp32h2, esp32s3))] - self.register_block() - .ctr() - .modify(|_, w| w.conf_upgate().set_bit()); + self.regs().ctr().modify(|_, w| w.conf_upgate().set_bit()); } /// Starts an I2C transmission. fn start_transmission(&self) { // Start transmission - self.register_block() - .ctr() - .modify(|_, w| w.trans_start().set_bit()); + self.regs().ctr().modify(|_, w| w.trans_start().set_bit()); } #[cfg(not(any(esp32, esp32s2)))] /// Fills the TX FIFO with data from the provided slice. fn fill_tx_fifo(&self, bytes: &[u8]) -> Result { let mut index = 0; - while index < bytes.len() - && !self - .register_block() - .int_raw() - .read() - .txfifo_ovf() - .bit_is_set() - { - write_fifo(self.register_block(), bytes[index]); + while index < bytes.len() && !self.regs().int_raw().read().txfifo_ovf().bit_is_set() { + write_fifo(self.regs(), bytes[index]); index += 1; } - if self - .register_block() - .int_raw() - .read() - .txfifo_ovf() - .bit_is_set() - { + if self.regs().int_raw().read().txfifo_ovf().bit_is_set() { index -= 1; - self.register_block() + self.regs() .int_clr() .write(|w| w.txfifo_ovf().clear_bit_by_one()); } @@ -2006,27 +1972,15 @@ impl Driver<'_> { loop { self.check_errors()?; - while !self - .register_block() - .int_raw() - .read() - .txfifo_wm() - .bit_is_set() - { + while !self.regs().int_raw().read().txfifo_wm().bit_is_set() { self.check_errors()?; } - self.register_block() + self.regs() .int_clr() .write(|w| w.txfifo_wm().clear_bit_by_one()); - while !self - .register_block() - .int_raw() - .read() - .txfifo_wm() - .bit_is_set() - { + while !self.regs().int_raw().read().txfifo_wm().bit_is_set() { self.check_errors()?; } @@ -2034,7 +1988,7 @@ impl Driver<'_> { break Ok(()); } - write_fifo(self.register_block(), bytes[index]); + write_fifo(self.regs(), bytes[index]); index += 1; } } @@ -2051,7 +2005,7 @@ impl Driver<'_> { } for b in bytes { - write_fifo(self.register_block(), *b); + write_fifo(self.regs(), *b); } Ok(bytes.len()) @@ -2076,7 +2030,7 @@ impl Driver<'_> { // this is only possible when writing the I2C address in release mode // from [perform_write_read] for b in bytes { - write_fifo(self.register_block(), *b); + write_fifo(self.regs(), *b); self.check_errors()?; } @@ -2087,7 +2041,7 @@ impl Driver<'_> { #[cfg(not(esp32))] fn reset_fifo(&self) { // First, reset the fifo buffers - self.register_block().fifo_conf().modify(|_, w| unsafe { + self.regs().fifo_conf().modify(|_, w| unsafe { w.tx_fifo_rst().set_bit(); w.rx_fifo_rst().set_bit(); w.nonfifo_en().clear_bit(); @@ -2096,12 +2050,12 @@ impl Driver<'_> { w.txfifo_wm_thrhd().bits(8) }); - self.register_block().fifo_conf().modify(|_, w| { + self.regs().fifo_conf().modify(|_, w| { w.tx_fifo_rst().clear_bit(); w.rx_fifo_rst().clear_bit() }); - self.register_block().int_clr().write(|w| { + self.regs().int_clr().write(|w| { w.rxfifo_wm().clear_bit_by_one(); w.txfifo_wm().clear_bit_by_one() }); @@ -2113,7 +2067,7 @@ impl Driver<'_> { #[cfg(esp32)] fn reset_fifo(&self) { // First, reset the fifo buffers - self.register_block().fifo_conf().modify(|_, w| unsafe { + self.regs().fifo_conf().modify(|_, w| unsafe { w.tx_fifo_rst().set_bit(); w.rx_fifo_rst().set_bit(); w.nonfifo_en().clear_bit(); @@ -2121,12 +2075,12 @@ impl Driver<'_> { w.nonfifo_tx_thres().bits(32) }); - self.register_block().fifo_conf().modify(|_, w| { + self.regs().fifo_conf().modify(|_, w| { w.tx_fifo_rst().clear_bit(); w.rx_fifo_rst().clear_bit() }); - self.register_block() + self.regs() .int_clr() .write(|w| w.rxfifo_full().clear_bit_by_one()); } @@ -2140,7 +2094,7 @@ impl Driver<'_> { ) -> Result { self.reset_fifo(); self.reset_command_list(); - let cmd_iterator = &mut self.register_block().comd_iter(); + let cmd_iterator = &mut self.regs().comd_iter(); if start { add_cmd(cmd_iterator, Command::Start)?; @@ -2179,7 +2133,7 @@ impl Driver<'_> { self.reset_fifo(); self.reset_command_list(); - let cmd_iterator = &mut self.register_block().comd_iter(); + let cmd_iterator = &mut self.regs().comd_iter(); if start { add_cmd(cmd_iterator, Command::Start)?; diff --git a/esp-hal/src/i2s/master.rs b/esp-hal/src/i2s/master.rs index 47eb5efe75a..4629cc6d5e7 100644 --- a/esp-hal/src/i2s/master.rs +++ b/esp-hal/src/i2s/master.rs @@ -804,7 +804,7 @@ mod private { } pub trait RegBlock: Peripheral

+ DmaEligible + Into + 'static { - fn register_block(&self) -> &RegisterBlock; + fn regs(&self) -> &RegisterBlock; fn peripheral(&self) -> crate::system::Peripheral; } @@ -823,9 +823,7 @@ mod private { fn set_interrupt_handler(&self, handler: InterruptHandler); fn enable_listen(&self, interrupts: EnumSet, enable: bool) { - let reg_block = self.register_block(); - - reg_block.int_ena().modify(|_, w| { + self.regs().int_ena().modify(|_, w| { for interrupt in interrupts { match interrupt { I2sInterrupt::RxHung => w.rx_hung().bit(enable), @@ -838,8 +836,7 @@ mod private { fn interrupts(&self) -> EnumSet { let mut res = EnumSet::new(); - let reg_block = self.register_block(); - let ints = reg_block.int_st().read(); + let ints = self.regs().int_st().read(); if ints.rx_hung().bit() { res.insert(I2sInterrupt::RxHung); @@ -852,9 +849,7 @@ mod private { } fn clear_interrupts(&self, interrupts: EnumSet) { - let reg_block = self.register_block(); - - reg_block.int_clr().write(|w| { + self.regs().int_clr().write(|w| { for interrupt in interrupts { match interrupt { I2sInterrupt::RxHung => w.rx_hung().clear_bit_by_one(), @@ -866,46 +861,41 @@ mod private { } fn set_clock(&self, clock_settings: I2sClockDividers) { - let i2s = self.register_block(); - - i2s.clkm_conf().modify(|r, w| unsafe { - w.bits(r.bits() | (crate::soc::constants::I2S_DEFAULT_CLK_SRC << 21)) + self.regs().clkm_conf().modify(|r, w| unsafe { // select PLL_160M + w.bits(r.bits() | (crate::soc::constants::I2S_DEFAULT_CLK_SRC << 21)) }); #[cfg(esp32)] - i2s.clkm_conf().modify(|_, w| w.clka_ena().clear_bit()); + self.regs() + .clkm_conf() + .modify(|_, w| w.clka_ena().clear_bit()); - i2s.clkm_conf().modify(|_, w| unsafe { + self.regs().clkm_conf().modify(|_, w| unsafe { w.clk_en().set_bit(); - w.clkm_div_num().bits(clock_settings.mclk_divider as u8) - }); - - i2s.clkm_conf().modify(|_, w| unsafe { + w.clkm_div_num().bits(clock_settings.mclk_divider as u8); w.clkm_div_a().bits(clock_settings.denominator as u8); w.clkm_div_b().bits(clock_settings.numerator as u8) }); - i2s.sample_rate_conf().modify(|_, w| unsafe { + self.regs().sample_rate_conf().modify(|_, w| unsafe { w.tx_bck_div_num().bits(clock_settings.bclk_divider as u8); w.rx_bck_div_num().bits(clock_settings.bclk_divider as u8) }); } fn configure(&self, _standard: &Standard, data_format: &DataFormat) { - let i2s = self.register_block(); - let fifo_mod = match data_format { DataFormat::Data32Channel32 => 2, DataFormat::Data16Channel16 => 0, }; - i2s.sample_rate_conf() - .modify(|_, w| unsafe { w.tx_bits_mod().bits(data_format.channel_bits()) }); - i2s.sample_rate_conf() - .modify(|_, w| unsafe { w.rx_bits_mod().bits(data_format.channel_bits()) }); + self.regs().sample_rate_conf().modify(|_, w| unsafe { + w.tx_bits_mod().bits(data_format.channel_bits()); + w.rx_bits_mod().bits(data_format.channel_bits()) + }); - i2s.conf().modify(|_, w| { + self.regs().conf().modify(|_, w| { w.tx_slave_mod().clear_bit(); w.rx_slave_mod().clear_bit(); // If the I2S_RX_MSB_SHIFT bit and the I2S_TX_MSB_SHIFT bit of register @@ -930,7 +920,7 @@ mod private { w.sig_loopback().clear_bit() }); - i2s.fifo_conf().modify(|_, w| unsafe { + self.regs().fifo_conf().modify(|_, w| unsafe { w.tx_fifo_mod().bits(fifo_mod); w.tx_fifo_mod_force_en().set_bit(); w.dscr_en().set_bit(); @@ -938,32 +928,33 @@ mod private { w.rx_fifo_mod_force_en().set_bit() }); - i2s.conf_chan().modify(|_, w| unsafe { + self.regs().conf_chan().modify(|_, w| unsafe { // for now only stereo w.tx_chan_mod().bits(0); w.rx_chan_mod().bits(0) }); - i2s.conf1().modify(|_, w| { + self.regs().conf1().modify(|_, w| { w.tx_pcm_bypass().set_bit(); w.rx_pcm_bypass().set_bit() }); - i2s.pd_conf().modify(|_, w| { + self.regs().pd_conf().modify(|_, w| { w.fifo_force_pu().set_bit(); w.fifo_force_pd().clear_bit() }); - i2s.conf2().modify(|_, w| { + self.regs().conf2().modify(|_, w| { w.camera_en().clear_bit(); w.lcd_en().clear_bit() }); } fn set_master(&self) { - let i2s = self.register_block(); - i2s.conf() - .modify(|_, w| w.rx_slave_mod().clear_bit().tx_slave_mod().clear_bit()); + self.regs().conf().modify(|_, w| { + w.rx_slave_mod().clear_bit(); + w.tx_slave_mod().clear_bit() + }); } fn update(&self) { @@ -971,72 +962,67 @@ mod private { } fn reset_tx(&self) { - let i2s = self.register_block(); - i2s.conf().modify(|_, w| { + self.regs().conf().modify(|_, w| { w.tx_reset().set_bit(); w.tx_fifo_reset().set_bit() }); - i2s.conf().modify(|_, w| { + self.regs().conf().modify(|_, w| { w.tx_reset().clear_bit(); w.tx_fifo_reset().clear_bit() }); - i2s.lc_conf().modify(|_, w| w.out_rst().set_bit()); - i2s.lc_conf().modify(|_, w| w.out_rst().clear_bit()); + self.regs().lc_conf().modify(|_, w| w.out_rst().set_bit()); + self.regs().lc_conf().modify(|_, w| w.out_rst().clear_bit()); - i2s.int_clr().write(|w| { + self.regs().int_clr().write(|w| { w.out_done().clear_bit_by_one(); w.out_total_eof().clear_bit_by_one() }); } fn tx_start(&self) { - let i2s = self.register_block(); - i2s.conf().modify(|_, w| w.tx_start().set_bit()); + self.regs().conf().modify(|_, w| w.tx_start().set_bit()); - while i2s.state().read().tx_idle().bit_is_set() { + while self.regs().state().read().tx_idle().bit_is_set() { // wait } } fn tx_stop(&self) { - let i2s = self.register_block(); - i2s.conf().modify(|_, w| w.tx_start().clear_bit()); + self.regs().conf().modify(|_, w| w.tx_start().clear_bit()); } fn wait_for_tx_done(&self) { - let i2s = self.register_block(); - while i2s.state().read().tx_idle().bit_is_clear() { + while self.regs().state().read().tx_idle().bit_is_clear() { // wait } - i2s.conf().modify(|_, w| w.tx_start().clear_bit()); + self.regs().conf().modify(|_, w| w.tx_start().clear_bit()); } fn reset_rx(&self) { - let i2s = self.register_block(); - i2s.conf().modify(|_, w| { + self.regs().conf().modify(|_, w| { w.rx_reset().set_bit(); w.rx_fifo_reset().set_bit() }); - i2s.conf().modify(|_, w| { + self.regs().conf().modify(|_, w| { w.rx_reset().clear_bit(); w.rx_fifo_reset().clear_bit() }); - i2s.lc_conf().modify(|_, w| w.in_rst().set_bit()); - i2s.lc_conf().modify(|_, w| w.in_rst().clear_bit()); + self.regs().lc_conf().modify(|_, w| w.in_rst().set_bit()); + self.regs().lc_conf().modify(|_, w| w.in_rst().clear_bit()); - i2s.int_clr().write(|w| { + self.regs().int_clr().write(|w| { w.in_done().clear_bit_by_one(); w.in_suc_eof().clear_bit_by_one() }); } fn rx_start(&self, len: usize) { - let i2s = self.register_block(); - - i2s.int_clr().write(|w| w.in_suc_eof().clear_bit_by_one()); + self.regs() + .int_clr() + .write(|w| w.in_suc_eof().clear_bit_by_one()); cfg_if::cfg_if! { if #[cfg(esp32)] { @@ -1047,19 +1033,21 @@ mod private { } } - i2s.rxeof_num() + self.regs() + .rxeof_num() .modify(|_, w| unsafe { w.rx_eof_num().bits(eof_num as u32) }); - i2s.conf().modify(|_, w| w.rx_start().set_bit()); + self.regs().conf().modify(|_, w| w.rx_start().set_bit()); } fn wait_for_rx_done(&self) { - let i2s = self.register_block(); - while i2s.int_raw().read().in_suc_eof().bit_is_clear() { + while self.regs().int_raw().read().in_suc_eof().bit_is_clear() { // wait } - i2s.int_clr().write(|w| w.in_suc_eof().clear_bit_by_one()); + self.regs() + .int_clr() + .write(|w| w.in_suc_eof().clear_bit_by_one()); } } @@ -1068,9 +1056,7 @@ mod private { fn set_interrupt_handler(&self, handler: InterruptHandler); fn enable_listen(&self, interrupts: EnumSet, enable: bool) { - let reg_block = self.register_block(); - - reg_block.int_ena().modify(|_, w| { + self.regs().int_ena().modify(|_, w| { for interrupt in interrupts { match interrupt { I2sInterrupt::RxHung => w.rx_hung().bit(enable), @@ -1093,8 +1079,7 @@ mod private { fn interrupts(&self) -> EnumSet { let mut res = EnumSet::new(); - let reg_block = self.register_block(); - let ints = reg_block.int_st().read(); + let ints = self.regs().int_st().read(); if ints.rx_hung().bit() { res.insert(I2sInterrupt::RxHung); @@ -1113,9 +1098,7 @@ mod private { } fn clear_interrupts(&self, interrupts: EnumSet) { - let reg_block = self.register_block(); - - reg_block.int_clr().write(|w| { + self.regs().int_clr().write(|w| { for interrupt in interrupts { match interrupt { I2sInterrupt::RxHung => w.rx_hung().clear_bit_by_one(), @@ -1130,8 +1113,6 @@ mod private { #[cfg(any(esp32c3, esp32s3))] fn set_clock(&self, clock_settings: I2sClockDividers) { - let i2s = self.register_block(); - let clkm_div_x: u32; let clkm_div_y: u32; let clkm_div_z: u32; @@ -1171,14 +1152,14 @@ mod private { clkm_div_yn1 = 0; } - i2s.tx_clkm_div_conf().modify(|_, w| unsafe { + self.regs().tx_clkm_div_conf().modify(|_, w| unsafe { w.tx_clkm_div_x().bits(clkm_div_x as u16); w.tx_clkm_div_y().bits(clkm_div_y as u16); w.tx_clkm_div_yn1().bit(clkm_div_yn1 != 0); w.tx_clkm_div_z().bits(clkm_div_z as u16) }); - i2s.tx_clkm_conf().modify(|_, w| unsafe { + self.regs().tx_clkm_conf().modify(|_, w| unsafe { w.clk_en().set_bit(); w.tx_clk_active().set_bit(); w.tx_clk_sel() @@ -1187,19 +1168,19 @@ mod private { w.tx_clkm_div_num().bits(clock_settings.mclk_divider as u8) }); - i2s.tx_conf1().modify(|_, w| unsafe { + self.regs().tx_conf1().modify(|_, w| unsafe { w.tx_bck_div_num() .bits((clock_settings.bclk_divider - 1) as u8) }); - i2s.rx_clkm_div_conf().modify(|_, w| unsafe { + self.regs().rx_clkm_div_conf().modify(|_, w| unsafe { w.rx_clkm_div_x().bits(clkm_div_x as u16); w.rx_clkm_div_y().bits(clkm_div_y as u16); w.rx_clkm_div_yn1().bit(clkm_div_yn1 != 0); w.rx_clkm_div_z().bits(clkm_div_z as u16) }); - i2s.rx_clkm_conf().modify(|_, w| unsafe { + self.regs().rx_clkm_conf().modify(|_, w| unsafe { w.rx_clk_active().set_bit(); // for now fixed at 160MHz w.rx_clk_sel() @@ -1208,7 +1189,7 @@ mod private { w.mclk_sel().bit(true) }); - i2s.rx_conf1().modify(|_, w| unsafe { + self.regs().rx_conf1().modify(|_, w| unsafe { w.rx_bck_div_num() .bits((clock_settings.bclk_divider - 1) as u8) }); @@ -1216,8 +1197,8 @@ mod private { #[cfg(any(esp32c6, esp32h2))] fn set_clock(&self, clock_settings: I2sClockDividers) { - let i2s = self.register_block(); - let pcr = crate::peripherals::PCR::regs(); // I2S clocks are configured via PCR + // I2S clocks are configured via PCR + use crate::peripherals::PCR; let clkm_div_x: u32; let clkm_div_y: u32; @@ -1258,14 +1239,14 @@ mod private { clkm_div_yn1 = 0; } - pcr.i2s_tx_clkm_div_conf().modify(|_, w| unsafe { + PCR::regs().i2s_tx_clkm_div_conf().modify(|_, w| unsafe { w.i2s_tx_clkm_div_x().bits(clkm_div_x as u16); w.i2s_tx_clkm_div_y().bits(clkm_div_y as u16); w.i2s_tx_clkm_div_yn1().bit(clkm_div_yn1 != 0); w.i2s_tx_clkm_div_z().bits(clkm_div_z as u16) }); - pcr.i2s_tx_clkm_conf().modify(|_, w| unsafe { + PCR::regs().i2s_tx_clkm_conf().modify(|_, w| unsafe { w.i2s_tx_clkm_en().set_bit(); // for now fixed at 160MHz for C6 and 96MHz for H2 w.i2s_tx_clkm_sel() @@ -1275,24 +1256,24 @@ mod private { }); #[cfg(not(esp32h2))] - i2s.tx_conf1().modify(|_, w| unsafe { + self.regs().tx_conf1().modify(|_, w| unsafe { w.tx_bck_div_num() .bits((clock_settings.bclk_divider - 1) as u8) }); #[cfg(esp32h2)] - i2s.tx_conf().modify(|_, w| unsafe { + self.regs().tx_conf().modify(|_, w| unsafe { w.tx_bck_div_num() .bits((clock_settings.bclk_divider - 1) as u8) }); - pcr.i2s_rx_clkm_div_conf().modify(|_, w| unsafe { + PCR::regs().i2s_rx_clkm_div_conf().modify(|_, w| unsafe { w.i2s_rx_clkm_div_x().bits(clkm_div_x as u16); w.i2s_rx_clkm_div_y().bits(clkm_div_y as u16); w.i2s_rx_clkm_div_yn1().bit(clkm_div_yn1 != 0); w.i2s_rx_clkm_div_z().bits(clkm_div_z as u16) }); - pcr.i2s_rx_clkm_conf().modify(|_, w| unsafe { + PCR::regs().i2s_rx_clkm_conf().modify(|_, w| unsafe { w.i2s_rx_clkm_en().set_bit(); // for now fixed at 160MHz for C6 and 96MHz for H2 w.i2s_rx_clkm_sel() @@ -1302,22 +1283,20 @@ mod private { w.i2s_mclk_sel().bit(true) }); #[cfg(not(esp32h2))] - i2s.rx_conf1().modify(|_, w| unsafe { + self.regs().rx_conf1().modify(|_, w| unsafe { w.rx_bck_div_num() .bits((clock_settings.bclk_divider - 1) as u8) }); #[cfg(esp32h2)] - i2s.rx_conf().modify(|_, w| unsafe { + self.regs().rx_conf().modify(|_, w| unsafe { w.rx_bck_div_num() .bits((clock_settings.bclk_divider - 1) as u8) }); } fn configure(&self, _standard: &Standard, data_format: &DataFormat) { - let i2s = self.register_block(); - #[allow(clippy::useless_conversion)] - i2s.tx_conf1().modify(|_, w| unsafe { + self.regs().tx_conf1().modify(|_, w| unsafe { w.tx_tdm_ws_width() .bits((data_format.channel_bits() - 1).into()); w.tx_bits_mod().bits(data_format.data_bits() - 1); @@ -1325,10 +1304,14 @@ mod private { w.tx_half_sample_bits().bits(data_format.channel_bits() - 1) }); #[cfg(not(esp32h2))] - i2s.tx_conf1().modify(|_, w| w.tx_msb_shift().set_bit()); + self.regs() + .tx_conf1() + .modify(|_, w| w.tx_msb_shift().set_bit()); #[cfg(esp32h2)] - i2s.tx_conf().modify(|_, w| w.tx_msb_shift().set_bit()); - i2s.tx_conf().modify(|_, w| unsafe { + self.regs() + .tx_conf() + .modify(|_, w| w.tx_msb_shift().set_bit()); + self.regs().tx_conf().modify(|_, w| unsafe { w.tx_mono().clear_bit(); w.tx_mono_fst_vld().set_bit(); w.tx_stop_en().set_bit(); @@ -1341,7 +1324,7 @@ mod private { w.tx_chan_mod().bits(0) }); - i2s.tx_tdm_ctrl().modify(|_, w| unsafe { + self.regs().tx_tdm_ctrl().modify(|_, w| unsafe { w.tx_tdm_tot_chan_num().bits(1); w.tx_tdm_chan0_en().set_bit(); w.tx_tdm_chan1_en().set_bit(); @@ -1362,7 +1345,7 @@ mod private { }); #[allow(clippy::useless_conversion)] - i2s.rx_conf1().modify(|_, w| unsafe { + self.regs().rx_conf1().modify(|_, w| unsafe { w.rx_tdm_ws_width() .bits((data_format.channel_bits() - 1).into()); w.rx_bits_mod().bits(data_format.data_bits() - 1); @@ -1370,11 +1353,15 @@ mod private { w.rx_half_sample_bits().bits(data_format.channel_bits() - 1) }); #[cfg(not(esp32h2))] - i2s.rx_conf1().modify(|_, w| w.rx_msb_shift().set_bit()); + self.regs() + .rx_conf1() + .modify(|_, w| w.rx_msb_shift().set_bit()); #[cfg(esp32h2)] - i2s.rx_conf().modify(|_, w| w.rx_msb_shift().set_bit()); + self.regs() + .rx_conf() + .modify(|_, w| w.rx_msb_shift().set_bit()); - i2s.rx_conf().modify(|_, w| unsafe { + self.regs().rx_conf().modify(|_, w| unsafe { w.rx_mono().clear_bit(); w.rx_mono_fst_vld().set_bit(); w.rx_stop_mode().bits(2); @@ -1385,7 +1372,7 @@ mod private { w.rx_bit_order().clear_bit() }); - i2s.rx_tdm_ctrl().modify(|_, w| unsafe { + self.regs().rx_tdm_ctrl().modify(|_, w| unsafe { w.rx_tdm_tot_chan_num().bits(1); w.rx_tdm_pdm_chan0_en().set_bit(); w.rx_tdm_pdm_chan1_en().set_bit(); @@ -1407,71 +1394,77 @@ mod private { } fn set_master(&self) { - let i2s = self.register_block(); - i2s.tx_conf().modify(|_, w| w.tx_slave_mod().clear_bit()); - i2s.rx_conf().modify(|_, w| w.rx_slave_mod().clear_bit()); + self.regs() + .tx_conf() + .modify(|_, w| w.tx_slave_mod().clear_bit()); + self.regs() + .rx_conf() + .modify(|_, w| w.rx_slave_mod().clear_bit()); } fn update(&self) { - let i2s = self.register_block(); - i2s.tx_conf().modify(|_, w| w.tx_update().clear_bit()); - i2s.tx_conf().modify(|_, w| w.tx_update().set_bit()); + self.regs() + .tx_conf() + .modify(|_, w| w.tx_update().clear_bit()); + self.regs().tx_conf().modify(|_, w| w.tx_update().set_bit()); - i2s.rx_conf().modify(|_, w| w.rx_update().clear_bit()); - i2s.rx_conf().modify(|_, w| w.rx_update().set_bit()); + self.regs() + .rx_conf() + .modify(|_, w| w.rx_update().clear_bit()); + self.regs().rx_conf().modify(|_, w| w.rx_update().set_bit()); } fn reset_tx(&self) { - let i2s = self.register_block(); - i2s.tx_conf().modify(|_, w| { + self.regs().tx_conf().modify(|_, w| { w.tx_reset().set_bit(); w.tx_fifo_reset().set_bit() }); - i2s.tx_conf().modify(|_, w| { + self.regs().tx_conf().modify(|_, w| { w.tx_reset().clear_bit(); w.tx_fifo_reset().clear_bit() }); - i2s.int_clr().write(|w| { + self.regs().int_clr().write(|w| { w.tx_done().clear_bit_by_one(); w.tx_hung().clear_bit_by_one() }); } fn tx_start(&self) { - let i2s = self.register_block(); - i2s.tx_conf().modify(|_, w| w.tx_start().set_bit()); + self.regs().tx_conf().modify(|_, w| w.tx_start().set_bit()); } fn tx_stop(&self) { - let i2s = self.register_block(); - i2s.tx_conf().modify(|_, w| w.tx_start().clear_bit()); + self.regs() + .tx_conf() + .modify(|_, w| w.tx_start().clear_bit()); } fn wait_for_tx_done(&self) { - let i2s = self.register_block(); - while i2s.state().read().tx_idle().bit_is_clear() { + while self.regs().state().read().tx_idle().bit_is_clear() { // wait } - i2s.tx_conf().modify(|_, w| w.tx_start().clear_bit()); + self.regs() + .tx_conf() + .modify(|_, w| w.tx_start().clear_bit()); } fn reset_rx(&self) { - let i2s = self.register_block(); + self.regs() + .rx_conf() + .modify(|_, w| w.rx_start().clear_bit()); - i2s.rx_conf().modify(|_, w| w.rx_start().clear_bit()); - - i2s.rx_conf().modify(|_, w| { + self.regs().rx_conf().modify(|_, w| { w.rx_reset().set_bit(); w.rx_fifo_reset().set_bit() }); - i2s.rx_conf().modify(|_, w| { + self.regs().rx_conf().modify(|_, w| { w.rx_reset().clear_bit(); w.rx_fifo_reset().clear_bit() }); - i2s.int_clr().write(|w| { + self.regs().int_clr().write(|w| { w.rx_done().clear_bit_by_one(); w.rx_hung().clear_bit_by_one() }); @@ -1480,24 +1473,25 @@ mod private { fn rx_start(&self, len: usize) { let len = len - 1; - let i2s = self.register_block(); - i2s.rxeof_num() + self.regs() + .rxeof_num() .write(|w| unsafe { w.rx_eof_num().bits(len as u16) }); - i2s.rx_conf().modify(|_, w| w.rx_start().set_bit()); + self.regs().rx_conf().modify(|_, w| w.rx_start().set_bit()); } fn wait_for_rx_done(&self) { - let i2s = self.register_block(); - while i2s.int_raw().read().rx_done().bit_is_clear() { + while self.regs().int_raw().read().rx_done().bit_is_clear() { // wait } - i2s.int_clr().write(|w| w.rx_done().clear_bit_by_one()); + self.regs() + .int_clr() + .write(|w| w.rx_done().clear_bit_by_one()); } } impl RegBlock for I2S0 { - fn register_block(&self) -> &RegisterBlock { + fn regs(&self) -> &RegisterBlock { unsafe { &*I2S0::PTR.cast::() } } @@ -1605,7 +1599,7 @@ mod private { #[cfg(i2s1)] impl RegBlock for I2S1 { - fn register_block(&self) -> &RegisterBlock { + fn regs(&self) -> &RegisterBlock { unsafe { &*I2S1::PTR.cast::() } } @@ -1678,13 +1672,20 @@ mod private { } impl RegBlock for super::AnyI2s { + fn regs(&self) -> &RegisterBlock { + match &self.0 { + super::AnyI2sInner::I2s0(i2s) => RegBlock::regs(i2s), + #[cfg(i2s1)] + super::AnyI2sInner::I2s1(i2s) => RegBlock::regs(i2s), + } + } + delegate::delegate! { to match &self.0 { super::AnyI2sInner::I2s0(i2s) => i2s, #[cfg(i2s1)] super::AnyI2sInner::I2s1(i2s) => i2s, } { - fn register_block(&self) -> &RegisterBlock; fn peripheral(&self) -> crate::system::Peripheral; } } diff --git a/esp-hal/src/i2s/parallel.rs b/esp-hal/src/i2s/parallel.rs index cc02cefe73f..7de8045d3c5 100644 --- a/esp-hal/src/i2s/parallel.rs +++ b/esp-hal/src/i2s/parallel.rs @@ -484,121 +484,118 @@ fn calculate_clock(sample_rate: impl Into, data_bits: u8) -> I2 #[doc(hidden)] pub trait Instance: Peripheral

+ DmaEligible + Into + 'static { - fn register_block(&self) -> &RegisterBlock; + fn regs(&self) -> &RegisterBlock; fn peripheral(&self) -> crate::system::Peripheral; fn ws_signal(&self) -> OutputSignal; fn data_out_signal(&self, i: usize, bits: u8) -> OutputSignal; fn rx_reset(&self) { - let r = self.register_block(); - r.conf().modify(|_, w| w.rx_reset().set_bit()); - r.conf().modify(|_, w| w.rx_reset().clear_bit()); + self.regs().conf().modify(|_, w| w.rx_reset().set_bit()); + self.regs().conf().modify(|_, w| w.rx_reset().clear_bit()); } fn rx_dma_reset(&self) { - let r = self.register_block(); - r.lc_conf().modify(|_, w| w.in_rst().set_bit()); - r.lc_conf().modify(|_, w| w.in_rst().clear_bit()); + self.regs().lc_conf().modify(|_, w| w.in_rst().set_bit()); + self.regs().lc_conf().modify(|_, w| w.in_rst().clear_bit()); } fn rx_fifo_reset(&self) { - let r = self.register_block(); - r.conf().modify(|_, w| w.rx_fifo_reset().set_bit()); - r.conf().modify(|_, w| w.rx_fifo_reset().clear_bit()); + self.regs() + .conf() + .modify(|_, w| w.rx_fifo_reset().set_bit()); + self.regs() + .conf() + .modify(|_, w| w.rx_fifo_reset().clear_bit()); } fn tx_reset(&self) { - let r = self.register_block(); - r.conf().modify(|_, w| w.tx_reset().set_bit()); + self.regs().conf().modify(|_, w| w.tx_reset().set_bit()); // without this delay starting a subsequent transfer will hang waiting // for tx_idle to clear (the transfer does not start). // While 20 clocks works for 80MHz cpu but 100 is needed for 240MHz! xtensa_lx::timer::delay(100); - r.conf().modify(|_, w| w.tx_reset().clear_bit()); + self.regs().conf().modify(|_, w| w.tx_reset().clear_bit()); } fn tx_dma_reset(&self) { - let r = self.register_block(); - r.lc_conf().modify(|_, w| w.out_rst().set_bit()); - r.lc_conf().modify(|_, w| w.out_rst().clear_bit()); + self.regs().lc_conf().modify(|_, w| w.out_rst().set_bit()); + self.regs().lc_conf().modify(|_, w| w.out_rst().clear_bit()); } fn tx_fifo_reset(&self) { - let r = self.register_block(); - r.conf().modify(|_, w| w.tx_fifo_reset().set_bit()); - r.conf().modify(|_, w| w.tx_fifo_reset().clear_bit()); + self.regs() + .conf() + .modify(|_, w| w.tx_fifo_reset().set_bit()); + self.regs() + .conf() + .modify(|_, w| w.tx_fifo_reset().clear_bit()); } fn tx_clear_interrupts(&self) { - let r = self.register_block(); - r.int_clr().write(|w| { + self.regs().int_clr().write(|w| { w.out_done().clear_bit_by_one(); w.out_total_eof().clear_bit_by_one() }); } fn tx_start(&self) { - let r = self.register_block(); - // wait for data to show up in the fifo - while r.int_raw().read().tx_rempty().bit_is_clear() { + while self.regs().int_raw().read().tx_rempty().bit_is_clear() { // wait } // without this transfers are not reliable! xtensa_lx::timer::delay(1); - r.conf().modify(|_, w| w.tx_start().set_bit()); + self.regs().conf().modify(|_, w| w.tx_start().set_bit()); - while r.state().read().tx_idle().bit_is_set() { + while self.regs().state().read().tx_idle().bit_is_set() { // wait } } fn tx_stop(&self) { - let r = self.register_block(); - r.conf().modify(|_, w| w.tx_start().clear_bit()); + self.regs().conf().modify(|_, w| w.tx_start().clear_bit()); } fn is_tx_done(&self) -> bool { - self.register_block().state().read().tx_idle().bit_is_set() + self.regs().state().read().tx_idle().bit_is_set() } fn tx_wait_done(&self) { - let r = self.register_block(); - while r.state().read().tx_idle().bit_is_clear() { + while self.regs().state().read().tx_idle().bit_is_clear() { // wait } - r.conf().modify(|_, w| w.tx_start().clear_bit()); - r.int_clr().write(|w| { + self.regs().conf().modify(|_, w| w.tx_start().clear_bit()); + self.regs().int_clr().write(|w| { w.out_done().clear_bit_by_one(); w.out_total_eof().clear_bit_by_one() }); } fn set_clock(&self, clock_settings: I2sClockDividers) { - let r = self.register_block(); - - r.clkm_conf().modify(|r, w| unsafe { + self.regs().clkm_conf().modify(|r, w| unsafe { w.bits(r.bits() | (crate::soc::constants::I2S_DEFAULT_CLK_SRC << 21)) // select PLL_160M }); #[cfg(esp32)] - r.clkm_conf().modify(|_, w| w.clka_ena().clear_bit()); + self.regs() + .clkm_conf() + .modify(|_, w| w.clka_ena().clear_bit()); - r.clkm_conf().modify(|_, w| unsafe { + self.regs().clkm_conf().modify(|_, w| unsafe { w.clk_en().set_bit(); w.clkm_div_num().bits(clock_settings.mclk_divider as u8) }); - r.clkm_conf().modify(|_, w| unsafe { + self.regs().clkm_conf().modify(|_, w| unsafe { w.clkm_div_a().bits(clock_settings.denominator as u8); w.clkm_div_b().bits(clock_settings.numerator as u8) }); - r.sample_rate_conf().modify(|_, w| unsafe { + self.regs().sample_rate_conf().modify(|_, w| unsafe { w.tx_bck_div_num().bits(clock_settings.bclk_divider as u8); w.rx_bck_div_num().bits(clock_settings.bclk_divider as u8) }); @@ -617,21 +614,19 @@ pub trait Instance: Peripheral

+ DmaEligible + Into + 'static self.rx_dma_reset(); self.tx_dma_reset(); - let r = self.register_block(); - // clear all bits and enable lcd mode - r.conf2().write(|w| { + self.regs().conf2().write(|w| { // 8 bit mode needs this or it updates on half clocks! w.lcd_tx_wrx2_en().bit(bits == 8); w.lcd_en().set_bit() }); - r.sample_rate_conf().modify(|_, w| unsafe { + self.regs().sample_rate_conf().modify(|_, w| unsafe { w.rx_bits_mod().bits(bits); w.tx_bits_mod().bits(bits) }); - r.fifo_conf().write(|w| unsafe { + self.regs().fifo_conf().write(|w| unsafe { w.rx_fifo_mod_force_en().set_bit(); w.tx_fifo_mod_force_en().set_bit(); w.rx_fifo_mod().bits(1); @@ -641,26 +636,26 @@ pub trait Instance: Peripheral

+ DmaEligible + Into + 'static w.dscr_en().set_bit() }); - r.conf1().write(|w| { + self.regs().conf1().write(|w| { w.tx_stop_en().set_bit(); w.rx_pcm_bypass().set_bit(); w.tx_pcm_bypass().set_bit() }); - r.conf_chan().write(|w| unsafe { + self.regs().conf_chan().write(|w| unsafe { w.rx_chan_mod().bits(1); w.tx_chan_mod().bits(1) }); - r.conf().modify(|_, w| { + self.regs().conf().modify(|_, w| { w.rx_mono().set_bit(); w.tx_mono().set_bit(); w.rx_right_first().set_bit(); w.tx_right_first().set_bit() }); - r.timing().reset(); + self.regs().timing().reset(); - r.pd_conf().modify(|_, w| { + self.regs().pd_conf().modify(|_, w| { w.fifo_force_pu().set_bit(); w.fifo_force_pd().clear_bit() }); @@ -668,7 +663,7 @@ pub trait Instance: Peripheral

+ DmaEligible + Into + 'static } impl Instance for I2S0 { - fn register_block(&self) -> &RegisterBlock { + fn regs(&self) -> &RegisterBlock { unsafe { &*I2S0::PTR.cast::() } } @@ -719,7 +714,7 @@ impl Instance for I2S0 { } impl Instance for I2S1 { - fn register_block(&self) -> &RegisterBlock { + fn regs(&self) -> &RegisterBlock { unsafe { &*I2S1::PTR.cast::() } } @@ -795,7 +790,7 @@ impl Instance for AnyI2s { AnyI2sInner::I2s0(i2s) => i2s, AnyI2sInner::I2s1(i2s) => i2s, } { - fn register_block(&self) -> &RegisterBlock; + fn regs(&self) -> &RegisterBlock; fn peripheral(&self) -> crate::system::Peripheral; fn ws_signal(&self) -> OutputSignal; fn data_out_signal(&self, i: usize, bits: u8) -> OutputSignal ; diff --git a/esp-hal/src/interrupt/riscv.rs b/esp-hal/src/interrupt/riscv.rs index 37cbfc203e8..47bbe6e03d4 100644 --- a/esp-hal/src/interrupt/riscv.rs +++ b/esp-hal/src/interrupt/riscv.rs @@ -228,7 +228,7 @@ pub fn _setup_interrupts() { // at least after the 2nd stage bootloader there are some interrupts enabled // (e.g. UART) for peripheral_interrupt in 0..255 { - Interrupt::try_from(peripheral_interrupt) + crate::peripherals::Interrupt::try_from(peripheral_interrupt) .map(|intr| { #[cfg(multi_core)] disable(Cpu::AppCpu, intr); diff --git a/esp-hal/src/lcd_cam/cam.rs b/esp-hal/src/lcd_cam/cam.rs index 13382426fe7..da9251e4bea 100644 --- a/esp-hal/src/lcd_cam/cam.rs +++ b/esp-hal/src/lcd_cam/cam.rs @@ -74,6 +74,7 @@ use crate::{ Pull, }, lcd_cam::{calculate_clkm, BitOrder, ByteOrder, ClockError}, + pac, peripheral::{Peripheral, PeripheralRef}, peripherals::LCD_CAM, system::{self, GenericPeripheralGuard}, @@ -154,7 +155,7 @@ impl<'d> Camera<'d> { _guard: cam._guard, }; - this.lcd_cam + this.regs() .cam_ctrl1() .modify(|_, w| w.cam_2byte_en().bit(P::BUS_WIDTH == 2)); @@ -163,6 +164,10 @@ impl<'d> Camera<'d> { Ok(this) } + fn regs(&self) -> &pac::lcd_cam::RegisterBlock { + self.lcd_cam.register_block() + } + /// Applies the configuration to the camera interface. pub fn apply_config(&mut self, config: &Config) -> Result<(), ConfigError> { let clocks = Clocks::get(); @@ -176,7 +181,7 @@ impl<'d> Camera<'d> { ) .map_err(ConfigError::Clock)?; - self.lcd_cam.cam_ctrl().write(|w| { + self.regs().cam_ctrl().write(|w| { // Force enable the clock for all configuration registers. unsafe { w.cam_clk_sel().bits((i + 1) as _); @@ -195,7 +200,7 @@ impl<'d> Camera<'d> { w.cam_stop_en().clear_bit() } }); - self.lcd_cam.cam_ctrl1().modify(|_, w| unsafe { + self.regs().cam_ctrl1().modify(|_, w| unsafe { w.cam_vh_de_mode_en().set_bit(); w.cam_rec_data_bytelen().bits(0); w.cam_line_int_num().bits(0); @@ -207,11 +212,11 @@ impl<'d> Camera<'d> { w.cam_vsync_inv().clear_bit() }); - self.lcd_cam + self.regs() .cam_rgb_yuv() .write(|w| w.cam_conv_bypass().clear_bit()); - self.lcd_cam + self.regs() .cam_ctrl() .modify(|_, w| w.cam_update().set_bit()); @@ -260,7 +265,7 @@ impl<'d> Camera<'d> { h_enable.init_input(Pull::None); InputSignal::CAM_H_ENABLE.connect_to(h_enable); - self.lcd_cam + self.regs() .cam_ctrl1() .modify(|_, w| w.cam_vh_de_mode_en().clear_bit()); @@ -288,7 +293,7 @@ impl<'d> Camera<'d> { h_enable.init_input(Pull::None); InputSignal::CAM_H_ENABLE.connect_to(h_enable); - self.lcd_cam + self.regs() .cam_ctrl1() .modify(|_, w| w.cam_vh_de_mode_en().set_bit()); @@ -301,16 +306,16 @@ impl<'d> Camera<'d> { mut buf: BUF, ) -> Result, (DmaError, Self, BUF)> { // Reset Camera control unit and Async Rx FIFO - self.lcd_cam + self.regs() .cam_ctrl1() .modify(|_, w| w.cam_reset().set_bit()); - self.lcd_cam + self.regs() .cam_ctrl1() .modify(|_, w| w.cam_reset().clear_bit()); - self.lcd_cam + self.regs() .cam_ctrl1() .modify(|_, w| w.cam_afifo_reset().set_bit()); - self.lcd_cam + self.regs() .cam_ctrl1() .modify(|_, w| w.cam_afifo_reset().clear_bit()); @@ -326,13 +331,13 @@ impl<'d> Camera<'d> { } // Start the Camera unit to listen for incoming DVP stream. - self.lcd_cam.cam_ctrl().modify(|_, w| { + self.regs().cam_ctrl().modify(|_, w| { // Automatically stops the camera unit once the GDMA Rx FIFO is full. w.cam_stop_en().set_bit(); w.cam_update().set_bit() }); - self.lcd_cam + self.regs() .cam_ctrl1() .modify(|_, w| w.cam_start().set_bit()); @@ -370,7 +375,7 @@ impl<'d, BUF: DmaRxBuffer> CameraTransfer<'d, BUF> { // the sake of familiarity and similarity with other drivers. self.camera - .lcd_cam + .regs() .cam_ctrl1() .read() .cam_start() @@ -423,7 +428,7 @@ impl<'d, BUF: DmaRxBuffer> CameraTransfer<'d, BUF> { fn stop_peripherals(&mut self) { // Stop the LCD_CAM peripheral. self.camera - .lcd_cam + .regs() .cam_ctrl1() .modify(|_, w| w.cam_start().clear_bit()); diff --git a/esp-hal/src/lcd_cam/lcd/dpi.rs b/esp-hal/src/lcd_cam/lcd/dpi.rs index 5eed6c8568d..84d8d737200 100644 --- a/esp-hal/src/lcd_cam/lcd/dpi.rs +++ b/esp-hal/src/lcd_cam/lcd/dpi.rs @@ -113,6 +113,7 @@ use crate::{ ByteOrder, ClockError, }, + pac, peripheral::{Peripheral, PeripheralRef}, peripherals::LCD_CAM, Blocking, @@ -160,6 +161,10 @@ where Ok(this) } + fn regs(&self) -> &pac::lcd_cam::RegisterBlock { + self.lcd_cam.register_block() + } + /// Applies the configuration to the peripheral. pub fn apply_config(&mut self, config: &Config) -> Result<(), ConfigError> { let clocks = Clocks::get(); @@ -176,7 +181,7 @@ where ) .map_err(ConfigError::Clock)?; - self.lcd_cam.lcd_clock().write(|w| unsafe { + self.regs().lcd_clock().write(|w| unsafe { // Force enable the clock for all configuration registers. w.clk_en().set_bit(); w.lcd_clk_sel().bits((i + 1) as _); @@ -190,15 +195,15 @@ where w.lcd_ck_out_edge() .bit(config.clock_mode.phase == Phase::ShiftHigh) }); - self.lcd_cam + self.regs() .lcd_user() .modify(|_, w| w.lcd_reset().set_bit()); - self.lcd_cam + self.regs() .lcd_rgb_yuv() .write(|w| w.lcd_conv_bypass().clear_bit()); - self.lcd_cam.lcd_user().modify(|_, w| { + self.regs().lcd_user().modify(|_, w| { if config.format.enable_2byte_mode { w.lcd_8bits_order().bit(false); w.lcd_byte_order() @@ -221,7 +226,7 @@ where }); let timing = &config.timing; - self.lcd_cam.lcd_ctrl().modify(|_, w| unsafe { + self.regs().lcd_ctrl().modify(|_, w| unsafe { // Enable RGB mode, and input VSYNC, HSYNC, and DE signals. w.lcd_rgb_mode_en().set_bit(); @@ -232,7 +237,7 @@ where w.lcd_vt_height() .bits((timing.vertical_total_height as u16).saturating_sub(1)) }); - self.lcd_cam.lcd_ctrl1().modify(|_, w| unsafe { + self.regs().lcd_ctrl1().modify(|_, w| unsafe { w.lcd_vb_front() .bits((timing.vertical_blank_front_porch as u8).saturating_sub(1)); w.lcd_ha_width() @@ -240,7 +245,7 @@ where w.lcd_ht_width() .bits((timing.horizontal_total_width as u16).saturating_sub(1)) }); - self.lcd_cam.lcd_ctrl2().modify(|_, w| unsafe { + self.regs().lcd_ctrl2().modify(|_, w| unsafe { w.lcd_vsync_width() .bits((timing.vsync_width as u8).saturating_sub(1)); w.lcd_vsync_idle_pol().bit(config.vsync_idle_level.into()); @@ -252,7 +257,7 @@ where w.lcd_hsync_position().bits(timing.hsync_position as u8) }); - self.lcd_cam.lcd_misc().modify(|_, w| unsafe { + self.regs().lcd_misc().modify(|_, w| unsafe { // TODO: Find out what this field actually does. // Set the threshold for Async Tx FIFO full event. (5 bits) w.lcd_afifo_threshold_num().bits((1 << 5) - 1); @@ -268,13 +273,13 @@ where // Enable blank region when LCD sends data out. w.lcd_bk_en().bit(!config.disable_black_region) }); - self.lcd_cam.lcd_dly_mode().modify(|_, w| unsafe { + self.regs().lcd_dly_mode().modify(|_, w| unsafe { w.lcd_de_mode().bits(config.de_mode as u8); w.lcd_hsync_mode().bits(config.hsync_mode as u8); w.lcd_vsync_mode().bits(config.vsync_mode as u8); w }); - self.lcd_cam.lcd_data_dout_mode().modify(|_, w| unsafe { + self.regs().lcd_data_dout_mode().modify(|_, w| unsafe { w.dout0_mode().bits(config.output_bit_mode as u8); w.dout1_mode().bits(config.output_bit_mode as u8); w.dout2_mode().bits(config.output_bit_mode as u8); @@ -293,7 +298,7 @@ where w.dout15_mode().bits(config.output_bit_mode as u8) }); - self.lcd_cam + self.regs() .lcd_user() .modify(|_, w| w.lcd_update().set_bit()); @@ -559,21 +564,21 @@ where } // Reset LCD control unit and Async Tx FIFO - self.lcd_cam + self.regs() .lcd_user() .modify(|_, w| w.lcd_reset().set_bit()); - self.lcd_cam + self.regs() .lcd_misc() .modify(|_, w| w.lcd_afifo_reset().set_bit()); - self.lcd_cam.lcd_misc().modify(|_, w| { + self.regs().lcd_misc().modify(|_, w| { // 1: Send the next frame data when the current frame is sent out. // 0: LCD stops when the current frame is sent out. w.lcd_next_frame_en().bit(next_frame_en) }); // Start the transfer. - self.lcd_cam.lcd_user().modify(|_, w| { + self.regs().lcd_user().modify(|_, w| { w.lcd_update().set_bit(); w.lcd_start().set_bit() }); @@ -595,12 +600,7 @@ pub struct DpiTransfer<'d, BUF: DmaTxBuffer, Dm: DriverMode> { impl<'d, BUF: DmaTxBuffer, Dm: DriverMode> DpiTransfer<'d, BUF, Dm> { /// Returns true when [Self::wait] will not block. pub fn is_done(&self) -> bool { - self.dpi - .lcd_cam - .lcd_user() - .read() - .lcd_start() - .bit_is_clear() + self.dpi.regs().lcd_user().read().lcd_start().bit_is_clear() } /// Stops this transfer on the spot and returns the peripheral and buffer. @@ -652,7 +652,7 @@ impl<'d, BUF: DmaTxBuffer, Dm: DriverMode> DpiTransfer<'d, BUF, Dm> { fn stop_peripherals(&mut self) { // Stop the LCD_CAM peripheral. self.dpi - .lcd_cam + .regs() .lcd_user() .modify(|_, w| w.lcd_start().clear_bit()); diff --git a/esp-hal/src/lcd_cam/lcd/i8080.rs b/esp-hal/src/lcd_cam/lcd/i8080.rs index cf53cfcad67..ab37f1efcfe 100644 --- a/esp-hal/src/lcd_cam/lcd/i8080.rs +++ b/esp-hal/src/lcd_cam/lcd/i8080.rs @@ -77,6 +77,7 @@ use crate::{ Lcd, LCD_DONE_WAKER, }, + pac, peripheral::{Peripheral, PeripheralRef}, peripherals::LCD_CAM, Blocking, @@ -127,6 +128,10 @@ where Ok(this) } + fn regs(&self) -> &pac::lcd_cam::RegisterBlock { + self.lcd_cam.register_block() + } + /// Applies configuration. pub fn apply_config(&mut self, config: &Config) -> Result<(), ConfigError> { let clocks = Clocks::get(); @@ -143,7 +148,7 @@ where ) .map_err(ConfigError::Clock)?; - self.lcd_cam.lcd_clock().write(|w| unsafe { + self.regs().lcd_clock().write(|w| unsafe { // Force enable the clock for all configuration registers. w.clk_en().set_bit(); w.lcd_clk_sel().bits((i + 1) as _); @@ -158,20 +163,20 @@ where .bit(config.clock_mode.phase == Phase::ShiftHigh) }); - self.lcd_cam + self.regs() .lcd_ctrl() .write(|w| w.lcd_rgb_mode_en().clear_bit()); - self.lcd_cam + self.regs() .lcd_rgb_yuv() .write(|w| w.lcd_conv_bypass().clear_bit()); - self.lcd_cam.lcd_user().modify(|_, w| { + self.regs().lcd_user().modify(|_, w| { w.lcd_8bits_order().bit(false); w.lcd_bit_order().bit(false); w.lcd_byte_order().bit(false); w.lcd_2byte_en().bit(false) }); - self.lcd_cam.lcd_misc().write(|w| unsafe { + self.regs().lcd_misc().write(|w| unsafe { // Set the threshold for Async Tx FIFO full event. (5 bits) w.lcd_afifo_threshold_num().bits(0); // Configure the setup cycles in LCD non-RGB mode. Setup cycles @@ -202,10 +207,10 @@ where // The default value of LCD_CD w.lcd_cd_idle_edge().bit(config.cd_idle_edge) }); - self.lcd_cam + self.regs() .lcd_dly_mode() .write(|w| unsafe { w.lcd_cd_mode().bits(config.cd_mode as u8) }); - self.lcd_cam.lcd_data_dout_mode().write(|w| unsafe { + self.regs().lcd_data_dout_mode().write(|w| unsafe { w.dout0_mode().bits(config.output_bit_mode as u8); w.dout1_mode().bits(config.output_bit_mode as u8); w.dout2_mode().bits(config.output_bit_mode as u8); @@ -224,7 +229,7 @@ where w.dout15_mode().bits(config.output_bit_mode as u8) }); - self.lcd_cam + self.regs() .lcd_user() .modify(|_, w| w.lcd_update().set_bit()); @@ -236,7 +241,7 @@ where /// mode. pub fn set_byte_order(&mut self, byte_order: ByteOrder) -> &mut Self { let is_inverted = byte_order != ByteOrder::default(); - self.lcd_cam + self.regs() .lcd_user() .modify(|_, w| w.lcd_byte_order().bit(is_inverted)); self @@ -247,7 +252,7 @@ where /// mode. pub fn set_8bits_order(&mut self, byte_order: ByteOrder) -> &mut Self { let is_inverted = byte_order != ByteOrder::default(); - self.lcd_cam + self.regs() .lcd_user() .modify(|_, w| w.lcd_8bits_order().bit(is_inverted)); self @@ -255,7 +260,7 @@ where /// Configures the bit order for data transmission. pub fn set_bit_order(&mut self, bit_order: BitOrder) -> &mut Self { - self.lcd_cam + self.regs() .lcd_user() .modify(|_, w| w.lcd_bit_order().bit(bit_order != BitOrder::default())); self @@ -304,44 +309,43 @@ where let cmd = cmd.into(); // Reset LCD control unit and Async Tx FIFO - self.lcd_cam + self.regs() .lcd_user() .modify(|_, w| w.lcd_reset().set_bit()); - self.lcd_cam + self.regs() .lcd_misc() .modify(|_, w| w.lcd_afifo_reset().set_bit()); // Set cmd value match cmd { Command::None => { - self.lcd_cam + self.regs() .lcd_user() .modify(|_, w| w.lcd_cmd().clear_bit()); } Command::One(value) => { - self.lcd_cam.lcd_user().modify(|_, w| { + self.regs().lcd_user().modify(|_, w| { w.lcd_cmd().set_bit(); w.lcd_cmd_2_cycle_en().clear_bit() }); - self.lcd_cam + self.regs() .lcd_cmd_val() .write(|w| unsafe { w.lcd_cmd_value().bits(value.into() as _) }); } Command::Two(first, second) => { - self.lcd_cam.lcd_user().modify(|_, w| { + self.regs().lcd_user().modify(|_, w| { w.lcd_cmd().set_bit(); w.lcd_cmd_2_cycle_en().set_bit() }); let cmd = first.into() as u32 | (second.into() as u32) << 16; - self.lcd_cam + self.regs() .lcd_cmd_val() .write(|w| unsafe { w.lcd_cmd_value().bits(cmd) }); } } let is_2byte_mode = size_of::() == 2; - - self.lcd_cam.lcd_user().modify(|_, w| unsafe { + self.regs().lcd_user().modify(|_, w| unsafe { // Set dummy length if dummy > 0 { // Enable DUMMY phase in LCD sequence when LCD starts. @@ -362,7 +366,7 @@ where // > i. LCD_CAM_LCD_START is cleared; // > ii. or LCD_CAM_LCD_RESET is set; // > iii. or all the data in GDMA is sent out. - self.lcd_cam + self.regs() .lcd_user() .modify(|_, w| w.lcd_always_out_en().set_bit().lcd_dout().set_bit()); @@ -376,7 +380,7 @@ where } // Setup interrupts. - self.lcd_cam + self.regs() .lc_dma_int_clr() .write(|w| w.lcd_trans_done_int_clr().set_bit()); @@ -384,7 +388,7 @@ where // Otherwise, some garbage data will be sent out crate::rom::ets_delay_us(1); - self.lcd_cam.lcd_user().modify(|_, w| { + self.regs().lcd_user().modify(|_, w| { w.lcd_update().set_bit(); w.lcd_start().set_bit() }); @@ -413,7 +417,7 @@ impl<'d, BUF: DmaTxBuffer, Dm: DriverMode> I8080Transfer<'d, BUF, Dm> { /// Returns true when [Self::wait] will not block. pub fn is_done(&self) -> bool { self.i8080 - .lcd_cam + .regs() .lcd_user() .read() .lcd_start() @@ -436,7 +440,7 @@ impl<'d, BUF: DmaTxBuffer, Dm: DriverMode> I8080Transfer<'d, BUF, Dm> { // Clear "done" interrupt. self.i8080 - .lcd_cam + .regs() .lc_dma_int_clr() .write(|w| w.lcd_trans_done_int_clr().set_bit()); @@ -461,7 +465,7 @@ impl<'d, BUF: DmaTxBuffer, Dm: DriverMode> I8080Transfer<'d, BUF, Dm> { fn stop_peripherals(&mut self) { // Stop the LCD_CAM peripheral. self.i8080 - .lcd_cam + .regs() .lcd_user() .modify(|_, w| w.lcd_start().clear_bit()); diff --git a/esp-hal/src/mcpwm/mod.rs b/esp-hal/src/mcpwm/mod.rs index 2a298d33c9a..a783f0f0fb0 100644 --- a/esp-hal/src/mcpwm/mod.rs +++ b/esp-hal/src/mcpwm/mod.rs @@ -84,8 +84,6 @@ //! # } //! ``` -use core::ops::Deref; - use fugit::HertzU32; use operator::Operator; use timer::Timer; @@ -137,13 +135,15 @@ impl<'d, PWM: PwmPeripheral> McPwm<'d, PWM> { #[cfg(not(esp32c6))] { + let register_block = unsafe { &*PWM::block() }; + // set prescaler - peripheral + register_block .clk_cfg() .write(|w| unsafe { w.clk_prescale().bits(peripheral_clock.prescaler) }); // enable clock - peripheral.clk().write(|w| w.en().set_bit()); + register_block.clk().write(|w| w.en().set_bit()); } #[cfg(esp32c6)] @@ -314,7 +314,7 @@ impl PeripheralClockConfig { pub struct FrequencyError; /// A MCPWM peripheral -pub trait PwmPeripheral: Deref + crate::private::Sealed { +pub trait PwmPeripheral: crate::private::Sealed { /// Get a pointer to the peripheral RegisterBlock fn block() -> *const RegisterBlock; /// Get operator GPIO mux output signal @@ -326,7 +326,7 @@ pub trait PwmPeripheral: Deref + crate::private::Sealed #[cfg(mcpwm0)] impl PwmPeripheral for crate::peripherals::MCPWM0 { fn block() -> *const RegisterBlock { - Self::PTR + Self::regs() } fn output_signal() -> OutputSignal { @@ -349,7 +349,7 @@ impl PwmPeripheral for crate::peripherals::MCPWM0 { #[cfg(mcpwm1)] impl PwmPeripheral for crate::peripherals::MCPWM1 { fn block() -> *const RegisterBlock { - Self::PTR + Self::regs() } fn output_signal() -> OutputSignal { diff --git a/esp-hal/src/pcnt/channel.rs b/esp-hal/src/pcnt/channel.rs index 93b6d43713a..251367337b7 100644 --- a/esp-hal/src/pcnt/channel.rs +++ b/esp-hal/src/pcnt/channel.rs @@ -13,8 +13,8 @@ pub use crate::pac::pcnt::unit::conf0::{CTRL_MODE as CtrlMode, EDGE_MODE as Edge use crate::{ gpio::{interconnect::PeripheralInput, InputSignal}, peripheral::Peripheral, - system::GenericPeripheralGuard, peripherals::PCNT, + system::GenericPeripheralGuard, }; /// Represents a channel within a pulse counter unit. diff --git a/esp-hal/src/peripheral.rs b/esp-hal/src/peripheral.rs index dd70b3a23f6..6b480195a7e 100644 --- a/esp-hal/src/peripheral.rs +++ b/esp-hal/src/peripheral.rs @@ -471,13 +471,11 @@ mod peripheral_macros { pub const fn regs<'a>() -> &'a ::Target { unsafe { &*Self::PTR } } - } - - #[doc(hidden)] - impl core::ops::Deref for $name { - type Target = ::Target; - fn deref(&self) -> &Self::Target { + #[doc = r"Return a reference to the register block"] + #[inline(always)] + #[instability::unstable] + pub fn register_block(&self) -> &::Target { unsafe { &*Self::PTR } } } diff --git a/esp-hal/src/rsa/esp32.rs b/esp-hal/src/rsa/esp32.rs index 32a7490cd3a..ec0eb8d14cc 100644 --- a/esp-hal/src/rsa/esp32.rs +++ b/esp-hal/src/rsa/esp32.rs @@ -15,7 +15,7 @@ impl Rsa<'_, Dm> { /// needs to be initialized, only after that peripheral should be used. /// This function would return without an error if the memory is initialized pub fn ready(&mut self) -> nb::Result<(), Infallible> { - if self.rsa.clean().read().clean().bit_is_clear() { + if self.regs().clean().read().clean().bit_is_clear() { return Err(nb::Error::WouldBlock); } Ok(()) @@ -23,25 +23,25 @@ impl Rsa<'_, Dm> { /// Writes the multi-mode configuration to the RSA hardware. pub(super) fn write_multi_mode(&mut self, mode: u32) { - self.rsa.mult_mode().write(|w| unsafe { w.bits(mode) }); + self.regs().mult_mode().write(|w| unsafe { w.bits(mode) }); } /// Writes the modular exponentiation mode configuration to the RSA /// hardware. pub(super) fn write_modexp_mode(&mut self, mode: u32) { - self.rsa.modexp_mode().write(|w| unsafe { w.bits(mode) }); + self.regs().modexp_mode().write(|w| unsafe { w.bits(mode) }); } /// Starts the modular exponentiation operation. pub(super) fn write_modexp_start(&self) { - self.rsa + self.regs() .modexp_start() .write(|w| w.modexp_start().set_bit()); } /// Starts the multiplication operation. pub(super) fn write_multi_start(&self) { - self.rsa.mult_start().write(|w| w.mult_start().set_bit()); + self.regs().mult_start().write(|w| w.mult_start().set_bit()); } /// Starts the modular multiplication operation. @@ -51,12 +51,12 @@ impl Rsa<'_, Dm> { /// Clears the RSA interrupt flag. pub(super) fn clear_interrupt(&mut self) { - self.rsa.interrupt().write(|w| w.interrupt().set_bit()); + self.regs().interrupt().write(|w| w.interrupt().set_bit()); } /// Checks if the RSA peripheral is idle. pub(super) fn is_idle(&self) -> bool { - self.rsa.interrupt().read().interrupt().bit_is_set() + self.regs().interrupt().read().interrupt().bit_is_set() } } diff --git a/esp-hal/src/rsa/esp32cX.rs b/esp-hal/src/rsa/esp32cX.rs index 04316db36fa..5066aa81270 100644 --- a/esp-hal/src/rsa/esp32cX.rs +++ b/esp-hal/src/rsa/esp32cX.rs @@ -15,7 +15,13 @@ impl Rsa<'_, Dm> { /// needs to be initialized, only after that peripheral should be used. /// This function would return without an error if the memory is initialized pub fn ready(&mut self) -> nb::Result<(), Infallible> { - if self.rsa.query_clean().read().query_clean().bit_is_clear() { + if self + .regs() + .query_clean() + .read() + .query_clean() + .bit_is_clear() + { return Err(nb::Error::WouldBlock); } Ok(()) @@ -26,11 +32,11 @@ impl Rsa<'_, Dm> { /// When enabled rsa peripheral would generate an interrupt when a operation /// is finished. pub fn enable_disable_interrupt(&mut self, enable: bool) { - self.rsa.int_ena().write(|w| w.int_ena().bit(enable)); + self.regs().int_ena().write(|w| w.int_ena().bit(enable)); } fn write_mode(&mut self, mode: u32) { - self.rsa.mode().write(|w| unsafe { w.bits(mode) }); + self.regs().mode().write(|w| unsafe { w.bits(mode) }); } /// Enables/disables search acceleration. @@ -43,26 +49,23 @@ impl Rsa<'_, Dm> { /// /// For more information refer to 18.3.4 of pub fn enable_disable_search_acceleration(&mut self, enable: bool) { - match enable { - true => self - .rsa - .search_enable() - .write(|w| w.search_enable().set_bit()), - false => self - .rsa - .search_enable() - .write(|w| w.search_enable().clear_bit()), - }; + self.regs() + .search_enable() + .write(|w| w.search_enable().bit(enable)); } /// Checks if the search functionality is enabled in the RSA hardware. pub(super) fn is_search_enabled(&mut self) -> bool { - self.rsa.search_enable().read().search_enable().bit_is_set() + self.regs() + .search_enable() + .read() + .search_enable() + .bit_is_set() } /// Sets the search position in the RSA hardware. pub(super) fn write_search_position(&mut self, search_position: u32) { - self.rsa + self.regs() .search_pos() .write(|w| unsafe { w.bits(search_position) }); } @@ -78,47 +81,40 @@ impl Rsa<'_, Dm> { /// /// For more information refer to 18.3.4 of . pub fn enable_disable_constant_time_acceleration(&mut self, enable: bool) { - match enable { - true => self - .rsa - .constant_time() - .write(|w| w.constant_time().clear_bit()), - false => self - .rsa - .constant_time() - .write(|w| w.constant_time().set_bit()), - }; + self.regs() + .constant_time() + .write(|w| w.constant_time().bit(enable)); } /// Starts the modular exponentiation operation. pub(super) fn write_modexp_start(&self) { - self.rsa + self.regs() .set_start_modexp() .write(|w| w.set_start_modexp().set_bit()); } /// Starts the multiplication operation. pub(super) fn write_multi_start(&self) { - self.rsa + self.regs() .set_start_mult() .write(|w| w.set_start_mult().set_bit()); } /// Starts the modular multiplication operation. pub(super) fn write_modmulti_start(&self) { - self.rsa + self.regs() .set_start_modmult() .write(|w| w.set_start_modmult().set_bit()); } /// Clears the RSA interrupt flag. pub(super) fn clear_interrupt(&mut self) { - self.rsa.int_clr().write(|w| w.int_clr().set_bit()); + self.regs().int_clr().write(|w| w.int_clr().set_bit()); } /// Checks if the RSA peripheral is idle. pub(super) fn is_idle(&self) -> bool { - self.rsa.query_idle().read().query_idle().bit_is_set() + self.regs().query_idle().read().query_idle().bit_is_set() } } diff --git a/esp-hal/src/rsa/esp32sX.rs b/esp-hal/src/rsa/esp32sX.rs index ca39a295707..da637e02134 100644 --- a/esp-hal/src/rsa/esp32sX.rs +++ b/esp-hal/src/rsa/esp32sX.rs @@ -16,7 +16,7 @@ impl Rsa<'_, Dm> { /// This function would return without an error if the memory is /// initialized. pub fn ready(&mut self) -> nb::Result<(), Infallible> { - if self.rsa.clean().read().clean().bit_is_clear() { + if self.regs().clean().read().clean().bit_is_clear() { return Err(nb::Error::WouldBlock); } Ok(()) @@ -27,11 +27,11 @@ impl Rsa<'_, Dm> { /// When enabled rsa peripheral would generate an interrupt when a operation /// is finished. pub fn enable_disable_interrupt(&mut self, enable: bool) { - self.rsa.int_ena().write(|w| w.int_ena().bit(enable)); + self.regs().int_ena().write(|w| w.int_ena().bit(enable)); } fn write_mode(&mut self, mode: u32) { - self.rsa.mode().write(|w| unsafe { w.bits(mode) }); + self.regs().mode().write(|w| unsafe { w.bits(mode) }); } /// Enables/disables search acceleration. @@ -44,19 +44,23 @@ impl Rsa<'_, Dm> { /// /// For more information refer to 20.3.4 of . pub fn enable_disable_search_acceleration(&mut self, enable: bool) { - self.rsa + self.regs() .search_enable() .write(|w| w.search_enable().bit(enable)); } /// Checks if the search functionality is enabled in the RSA hardware. pub(super) fn is_search_enabled(&mut self) -> bool { - self.rsa.search_enable().read().search_enable().bit_is_set() + self.regs() + .search_enable() + .read() + .search_enable() + .bit_is_set() } /// Sets the search position in the RSA hardware. pub(super) fn write_search_position(&mut self, search_position: u32) { - self.rsa + self.regs() .search_pos() .write(|w| unsafe { w.bits(search_position) }); } @@ -72,38 +76,38 @@ impl Rsa<'_, Dm> { /// /// For more information refer to 20.3.4 of . pub fn enable_disable_constant_time_acceleration(&mut self, enable: bool) { - self.rsa + self.regs() .constant_time() .write(|w| w.constant_time().bit(!enable)); } /// Starts the modular exponentiation operation. pub(super) fn write_modexp_start(&self) { - self.rsa + self.regs() .modexp_start() .write(|w| w.modexp_start().set_bit()); } /// Starts the multiplication operation. pub(super) fn write_multi_start(&self) { - self.rsa.mult_start().write(|w| w.mult_start().set_bit()); + self.regs().mult_start().write(|w| w.mult_start().set_bit()); } /// Starts the modular multiplication operation. pub(super) fn write_modmulti_start(&self) { - self.rsa + self.regs() .modmult_start() .write(|w| w.modmult_start().set_bit()); } /// Clears the RSA interrupt flag. pub(super) fn clear_interrupt(&mut self) { - self.rsa.int_clr().write(|w| w.int_clr().set_bit()); + self.regs().int_clr().write(|w| w.int_clr().set_bit()); } /// Checks if the RSA peripheral is idle. pub(super) fn is_idle(&self) -> bool { - self.rsa.idle().read().idle().bit_is_set() + self.regs().idle().read().idle().bit_is_set() } } diff --git a/esp-hal/src/rsa/mod.rs b/esp-hal/src/rsa/mod.rs index 114bea4aa92..15531d7c3c0 100644 --- a/esp-hal/src/rsa/mod.rs +++ b/esp-hal/src/rsa/mod.rs @@ -25,6 +25,7 @@ use core::{marker::PhantomData, ptr::copy_nonoverlapping}; use crate::{ interrupt::{InterruptConfigurable, InterruptHandler}, + pac, peripheral::{Peripheral, PeripheralRef}, peripherals::{Interrupt, RSA}, system::{GenericPeripheralGuard, Peripheral as PeripheralEnable}, @@ -106,44 +107,38 @@ impl<'d, Dm: crate::DriverMode> Rsa<'d, Dm> { } } + fn regs(&self) -> &pac::rsa::RegisterBlock { + self.rsa.register_block() + } + fn write_operand_b(&mut self, operand_b: &[u32; N]) { - unsafe { - copy_nonoverlapping(operand_b.as_ptr(), self.rsa.y_mem(0).as_ptr(), N); - } + unsafe { copy_nonoverlapping(operand_b.as_ptr(), self.regs().y_mem(0).as_ptr(), N) }; } fn write_modulus(&mut self, modulus: &[u32; N]) { - unsafe { - copy_nonoverlapping(modulus.as_ptr(), self.rsa.m_mem(0).as_ptr(), N); - } + unsafe { copy_nonoverlapping(modulus.as_ptr(), self.regs().m_mem(0).as_ptr(), N) }; } fn write_mprime(&mut self, m_prime: u32) { - self.rsa.m_prime().write(|w| unsafe { w.bits(m_prime) }); + self.regs().m_prime().write(|w| unsafe { w.bits(m_prime) }); } fn write_operand_a(&mut self, operand_a: &[u32; N]) { - unsafe { - copy_nonoverlapping(operand_a.as_ptr(), self.rsa.x_mem(0).as_ptr(), N); - } + unsafe { copy_nonoverlapping(operand_a.as_ptr(), self.regs().x_mem(0).as_ptr(), N) }; } fn write_multi_operand_b(&mut self, operand_b: &[u32; N]) { - unsafe { - copy_nonoverlapping(operand_b.as_ptr(), self.rsa.z_mem(0).as_ptr().add(N), N); - } + unsafe { copy_nonoverlapping(operand_b.as_ptr(), self.regs().z_mem(0).as_ptr().add(N), N) }; } fn write_r(&mut self, r: &[u32; N]) { - unsafe { - copy_nonoverlapping(r.as_ptr(), self.rsa.z_mem(0).as_ptr(), N); - } + unsafe { copy_nonoverlapping(r.as_ptr(), self.regs().z_mem(0).as_ptr(), N) }; } fn read_out(&self, outbuf: &mut [u32; N]) { unsafe { copy_nonoverlapping( - self.rsa.z_mem(0).as_ptr() as *const u32, + self.regs().z_mem(0).as_ptr() as *const u32, outbuf.as_ptr() as *mut u32, N, ); @@ -406,17 +401,17 @@ pub(crate) mod asynch { #[must_use = "futures do nothing unless you `.await` or poll them"] struct RsaFuture<'a, 'd> { #[cfg_attr(esp32, allow(dead_code))] - instance: &'a Rsa<'d, Async>, + driver: &'a Rsa<'d, Async>, } impl<'a, 'd> RsaFuture<'a, 'd> { - fn new(instance: &'a Rsa<'d, Async>) -> Self { + fn new(driver: &'a Rsa<'d, Async>) -> Self { SIGNALED.store(false, Ordering::Relaxed); #[cfg(not(esp32))] - instance.rsa.int_ena().write(|w| w.int_ena().set_bit()); + driver.regs().int_ena().write(|w| w.int_ena().set_bit()); - Self { instance } + Self { driver } } fn is_done(&self) -> bool { @@ -427,8 +422,8 @@ pub(crate) mod asynch { impl Drop for RsaFuture<'_, '_> { fn drop(&mut self) { #[cfg(not(esp32))] - self.instance - .rsa + self.driver + .regs() .int_ena() .write(|w| w.int_ena().clear_bit()); } diff --git a/esp-hal/src/rtc_cntl/rtc/esp32c6.rs b/esp-hal/src/rtc_cntl/rtc/esp32c6.rs index 5e7dcb06087..198f9bdbdce 100644 --- a/esp-hal/src/rtc_cntl/rtc/esp32c6.rs +++ b/esp-hal/src/rtc_cntl/rtc/esp32c6.rs @@ -1361,7 +1361,7 @@ pub(crate) enum RtcFastClock { impl Clock for RtcFastClock { fn frequency(&self) -> HertzU32 { match self { - RtcFastClock::RtcFastClockXtalD2 => HertzU32::Hz(40_000_000 / 2), // TODO: Is the value correct? + RtcFastClock::RtcFastClockXtalD2 => HertzU32::Hz(40_000_000 / 2), /* TODO: Is the value correct? */ RtcFastClock::RtcFastClockRcFast => HertzU32::Hz(17_500_000), } } diff --git a/esp-hal/src/sha.rs b/esp-hal/src/sha.rs index 41fdf6dce0a..92ab1ba5a49 100644 --- a/esp-hal/src/sha.rs +++ b/esp-hal/src/sha.rs @@ -97,6 +97,11 @@ impl<'d> Sha<'d> { pub fn start_owned(self) -> ShaDigest<'d, A, Self> { ShaDigest::new(self) } + + #[cfg(not(esp32))] + fn regs(&self) -> &crate::pac::sha::RegisterBlock { + self.sha.register_block() + } } impl crate::private::Sealed for Sha<'_> {} @@ -147,7 +152,7 @@ impl<'d, A: ShaAlgorithm, S: BorrowMut>> ShaDigest<'d, A, S> { #[cfg(not(esp32))] // Setup SHA Mode. sha.borrow_mut() - .sha + .regs() .mode() .write(|w| unsafe { w.mode().bits(A::MODE_AS_BITS) }); @@ -167,7 +172,7 @@ impl<'d, A: ShaAlgorithm, S: BorrowMut>> ShaDigest<'d, A, S> { pub fn restore(mut sha: S, ctx: &mut Context) -> Self { // Setup SHA Mode. sha.borrow_mut() - .sha + .regs() .mode() .write(|w| unsafe { w.mode().bits(A::MODE_AS_BITS) }); @@ -202,7 +207,7 @@ impl<'d, A: ShaAlgorithm, S: BorrowMut>> ShaDigest<'d, A, S> { if #[cfg(esp32)] { A::is_busy(&self.sha.borrow().sha) } else { - self.sha.borrow().sha.busy().read().state().bit_is_set() + self.sha.borrow().regs().busy().read().state().bit_is_set() } } } @@ -353,30 +358,28 @@ impl<'d, A: ShaAlgorithm, S: BorrowMut>> ShaDigest<'d, A, S> { /// This method is platform-specific and differs for ESP32 and non-ESP32 /// platforms. fn process_buffer(&mut self) { - #[cfg(not(esp32))] - if self.first_run { - // Set SHA_START_REG - self.sha - .borrow_mut() - .sha - .start() - .write(|w| unsafe { w.bits(1) }); - self.first_run = false; - } else { - // SET SHA_CONTINUE_REG - self.sha - .borrow_mut() - .sha - .continue_() - .write(|w| unsafe { w.bits(1) }); - } + let sha = self.sha.borrow_mut(); - #[cfg(esp32)] - if self.first_run { - A::start(&mut self.sha.borrow_mut().sha); - self.first_run = false; - } else { - A::r#continue(&mut self.sha.borrow_mut().sha); + cfg_if::cfg_if! { + if #[cfg(esp32)] { + if self.first_run { + A::start(&mut sha.sha); + self.first_run = false; + } else { + A::r#continue(&mut sha.sha); + } + } else { + if self.first_run { + // Set SHA_START_REG + // FIXME: raw register access + sha.regs().start().write(|w| unsafe { w.bits(1) }); + self.first_run = false; + } else { + // SET SHA_CONTINUE_REG + // FIXME: raw register access + sha.regs().continue_().write(|w| unsafe { w.bits(1) }); + } + } } } @@ -586,28 +589,28 @@ macro_rules! impl_sha { #[cfg(esp32)] fn start(sha: &mut crate::peripherals::SHA) { paste::paste! { - sha.[< $name:lower _start >]().write(|w| w.[< $name:lower _start >]().set_bit()); + sha.register_block().[< $name:lower _start >]().write(|w| w.[< $name:lower _start >]().set_bit()); } } #[cfg(esp32)] fn r#continue(sha: &mut crate::peripherals::SHA) { paste::paste! { - sha.[< $name:lower _continue >]().write(|w| w.[< $name:lower _continue >]().set_bit()); + sha.register_block().[< $name:lower _continue >]().write(|w| w.[< $name:lower _continue >]().set_bit()); } } #[cfg(esp32)] fn load(sha: &mut crate::peripherals::SHA) { paste::paste! { - sha.[< $name:lower _load >]().write(|w| w.[< $name:lower _load >]().set_bit()); + sha.register_block().[< $name:lower _load >]().write(|w| w.[< $name:lower _load >]().set_bit()); } } #[cfg(esp32)] fn is_busy(sha: &crate::peripherals::SHA) -> bool { paste::paste! { - sha.[< $name:lower _busy >]().read().[< $name:lower _busy >]().bit_is_set() + sha.register_block().[< $name:lower _busy >]().read().[< $name:lower _busy >]().bit_is_set() } } } @@ -642,6 +645,7 @@ impl_sha!(Sha512_224, 5, 28, 128); impl_sha!(Sha512_256, 6, 32, 128); fn h_mem(sha: &crate::peripherals::SHA, index: usize) -> *mut u32 { + let sha = sha.register_block(); cfg_if::cfg_if! { if #[cfg(esp32)] { sha.text(index).as_ptr() @@ -652,6 +656,7 @@ fn h_mem(sha: &crate::peripherals::SHA, index: usize) -> *mut u32 { } fn m_mem(sha: &crate::peripherals::SHA, index: usize) -> *mut u32 { + let sha = sha.register_block(); cfg_if::cfg_if! { if #[cfg(esp32)] { sha.text(index).as_ptr() diff --git a/esp-hal/src/soc/esp32s3/psram.rs b/esp-hal/src/soc/esp32s3/psram.rs index 2c6574dfe37..cff314cc6a9 100644 --- a/esp-hal/src/soc/esp32s3/psram.rs +++ b/esp-hal/src/soc/esp32s3/psram.rs @@ -1092,7 +1092,9 @@ pub(crate) mod utils { unsafe { // set to variable dummy mode - SPI1::regs().ddr().modify(|_, w| w.spi_fmem_var_dummy().set_bit()); + SPI1::regs() + .ddr() + .modify(|_, w| w.spi_fmem_var_dummy().set_bit()); esp_rom_spi_set_dtr_swap_mode(1, false, false); } diff --git a/esp-hal/src/spi/master.rs b/esp-hal/src/spi/master.rs index d4a9e904688..12e7e3b641d 100644 --- a/esp-hal/src/spi/master.rs +++ b/esp-hal/src/spi/master.rs @@ -2378,6 +2378,10 @@ impl DmaDriver { self.driver.update(); } + fn regs(&self) -> &RegisterBlock { + self.driver.regs() + } + #[allow(clippy::too_many_arguments)] #[cfg_attr(place_spi_driver_in_ram, ram)] unsafe fn start_transfer_dma( @@ -2390,19 +2394,17 @@ impl DmaDriver { rx: &mut RX, tx: &mut TX, ) -> Result<(), Error> { - let reg_block = self.driver.register_block(); - #[cfg(esp32s2)] { // without this a transfer after a write will fail - reg_block.dma_out_link().write(|w| w.bits(0)); - reg_block.dma_in_link().write(|w| w.bits(0)); + self.regs().dma_out_link().write(|w| w.bits(0)); + self.regs().dma_in_link().write(|w| w.bits(0)); } self.driver.configure_datalen(rx_len, tx_len); // enable the MISO and MOSI if needed - reg_block + self.regs() .user() .modify(|_, w| w.usr_miso().bit(rx_len > 0).usr_mosi().bit(tx_len > 0)); @@ -2417,10 +2419,10 @@ impl DmaDriver { // see https://github.com/espressif/esp-idf/commit/366e4397e9dae9d93fe69ea9d389b5743295886f // see https://github.com/espressif/esp-idf/commit/0c3653b1fd7151001143451d4aa95dbf15ee8506 if _full_duplex { - reg_block + self.regs() .dma_in_link() .modify(|_, w| unsafe { w.inlink_addr().bits(0) }); - reg_block + self.regs() .dma_in_link() .modify(|_, w| w.inlink_start().set_bit()); } @@ -2441,14 +2443,12 @@ impl DmaDriver { fn enable_dma(&self) { #[cfg(gdma)] - { - // for non GDMA this is done in `assign_tx_device` / `assign_rx_device` - let reg_block = self.driver.register_block(); - reg_block.dma_conf().modify(|_, w| { - w.dma_tx_ena().set_bit(); - w.dma_rx_ena().set_bit() - }); - } + // for non GDMA this is done in `assign_tx_device` / `assign_rx_device` + self.regs().dma_conf().modify(|_, w| { + w.dma_tx_ena().set_bit(); + w.dma_rx_ena().set_bit() + }); + #[cfg(pdma)] self.reset_dma(); } @@ -2469,16 +2469,15 @@ impl DmaDriver { w.dma_afifo_rst().bit(bit) }); } - let reg_block = self.driver.register_block(); - set_reset_bit(reg_block, true); - set_reset_bit(reg_block, false); + + set_reset_bit(self.regs(), true); + set_reset_bit(self.regs(), false); self.clear_dma_interrupts(); } #[cfg(gdma)] fn clear_dma_interrupts(&self) { - let reg_block = self.driver.register_block(); - reg_block.dma_int_clr().write(|w| { + self.regs().dma_int_clr().write(|w| { w.dma_infifo_full_err().clear_bit_by_one(); w.dma_outfifo_empty_err().clear_bit_by_one(); w.trans_done().clear_bit_by_one(); @@ -2489,8 +2488,7 @@ impl DmaDriver { #[cfg(pdma)] fn clear_dma_interrupts(&self) { - let reg_block = self.driver.register_block(); - reg_block.dma_int_clr().write(|w| { + self.regs().dma_int_clr().write(|w| { w.inlink_dscr_empty().clear_bit_by_one(); w.outlink_dscr_error().clear_bit_by_one(); w.inlink_dscr_error().clear_bit_by_one(); @@ -2513,14 +2511,13 @@ struct Driver { // FIXME: split this up into peripheral versions impl Driver { /// Returns the register block for this SPI instance. - pub fn register_block(&self) -> &RegisterBlock { + pub fn regs(&self) -> &RegisterBlock { unsafe { &*self.info.register_block } } /// Initialize for full-duplex 1 bit mode fn init(&self) { - let reg_block = self.register_block(); - reg_block.user().modify(|_, w| { + self.regs().user().modify(|_, w| { w.usr_miso_highpart().clear_bit(); w.usr_mosi_highpart().clear_bit(); w.doutdin().set_bit(); @@ -2533,7 +2530,7 @@ impl Driver { }); #[cfg(gdma)] - reg_block.clk_gate().modify(|_, w| { + self.regs().clk_gate().modify(|_, w| { w.clk_en().set_bit(); w.mst_clk_active().set_bit(); w.mst_clk_sel().set_bit() @@ -2549,26 +2546,26 @@ impl Driver { } #[cfg(gdma)] - reg_block.ctrl().modify(|_, w| { + self.regs().ctrl().modify(|_, w| { w.q_pol().clear_bit(); w.d_pol().clear_bit(); w.hold_pol().clear_bit() }); #[cfg(esp32s2)] - reg_block.ctrl().modify(|_, w| { + self.regs().ctrl().modify(|_, w| { w.q_pol().clear_bit(); w.d_pol().clear_bit(); w.wp().clear_bit() }); #[cfg(esp32)] - reg_block.ctrl().modify(|_, w| w.wp().clear_bit()); + self.regs().ctrl().modify(|_, w| w.wp().clear_bit()); #[cfg(not(esp32))] - reg_block.misc().write(|w| unsafe { w.bits(0) }); + self.regs().misc().write(|w| unsafe { w.bits(0) }); - reg_block.slave().write(|w| unsafe { w.bits(0) }); + self.regs().slave().write(|w| unsafe { w.bits(0) }); } #[cfg(not(esp32))] @@ -2578,8 +2575,7 @@ impl Driver { address_mode: DataMode, data_mode: DataMode, ) -> Result<(), Error> { - let reg_block = self.register_block(); - reg_block.ctrl().modify(|_, w| { + self.regs().ctrl().modify(|_, w| { w.fcmd_dual().bit(cmd_mode == DataMode::Dual); w.fcmd_quad().bit(cmd_mode == DataMode::Quad); w.faddr_dual().bit(address_mode == DataMode::Dual); @@ -2587,7 +2583,7 @@ impl Driver { w.fread_dual().bit(data_mode == DataMode::Dual); w.fread_quad().bit(data_mode == DataMode::Quad) }); - reg_block.user().modify(|_, w| { + self.regs().user().modify(|_, w| { w.fwrite_dual().bit(data_mode == DataMode::Dual); w.fwrite_quad().bit(data_mode == DataMode::Quad) }); @@ -2601,7 +2597,6 @@ impl Driver { address_mode: DataMode, data_mode: DataMode, ) -> Result<(), Error> { - let reg_block = self.register_block(); match cmd_mode { DataMode::Single => (), DataMode::SingleTwoDataLines => (), @@ -2611,14 +2606,14 @@ impl Driver { match address_mode { DataMode::Single | DataMode::SingleTwoDataLines => { - reg_block.ctrl().modify(|_, w| { + self.regs().ctrl().modify(|_, w| { w.fread_dio().clear_bit(); w.fread_qio().clear_bit(); w.fread_dual().bit(data_mode == DataMode::Dual); w.fread_quad().bit(data_mode == DataMode::Quad) }); - reg_block.user().modify(|_, w| { + self.regs().user().modify(|_, w| { w.fwrite_dio().clear_bit(); w.fwrite_qio().clear_bit(); w.fwrite_dual().bit(data_mode == DataMode::Dual); @@ -2626,7 +2621,7 @@ impl Driver { }); } address_mode if address_mode == data_mode => { - reg_block.ctrl().modify(|_, w| { + self.regs().ctrl().modify(|_, w| { w.fastrd_mode().set_bit(); w.fread_dio().bit(address_mode == DataMode::Dual); w.fread_qio().bit(address_mode == DataMode::Quad); @@ -2634,7 +2629,7 @@ impl Driver { w.fread_quad().clear_bit() }); - reg_block.user().modify(|_, w| { + self.regs().user().modify(|_, w| { w.fwrite_dio().bit(address_mode == DataMode::Dual); w.fwrite_qio().bit(address_mode == DataMode::Quad); w.fwrite_dual().clear_bit(); @@ -2727,19 +2722,15 @@ impl Driver { | ((pre as u32 - 1) << 18); } - self.register_block() - .clock() - .write(|w| unsafe { w.bits(reg_val) }); + self.regs().clock().write(|w| unsafe { w.bits(reg_val) }); } /// Enable or disable listening for the given interrupts. #[cfg_attr(not(feature = "unstable"), allow(dead_code))] fn enable_listen(&self, interrupts: EnumSet, enable: bool) { - let reg_block = self.register_block(); - cfg_if::cfg_if! { if #[cfg(esp32)] { - reg_block.slave().modify(|_, w| { + self.regs().slave().modify(|_, w| { for interrupt in interrupts { match interrupt { SpiInterrupt::TransferDone => w.trans_inten().bit(enable), @@ -2748,7 +2739,7 @@ impl Driver { w }); } else if #[cfg(esp32s2)] { - reg_block.slave().modify(|_, w| { + self.regs().slave().modify(|_, w| { for interrupt in interrupts { match interrupt { SpiInterrupt::TransferDone => w.int_trans_done_en().bit(enable), @@ -2758,7 +2749,7 @@ impl Driver { w }); } else { - reg_block.dma_int_ena().modify(|_, w| { + self.regs().dma_int_ena().modify(|_, w| { for interrupt in interrupts { match interrupt { SpiInterrupt::TransferDone => w.trans_done().bit(enable), @@ -2777,22 +2768,21 @@ impl Driver { #[cfg_attr(not(feature = "unstable"), allow(dead_code))] fn interrupts(&self) -> EnumSet { let mut res = EnumSet::new(); - let reg_block = self.register_block(); cfg_if::cfg_if! { if #[cfg(esp32)] { - if reg_block.slave().read().trans_done().bit() { + if self.regs().slave().read().trans_done().bit() { res.insert(SpiInterrupt::TransferDone); } } else if #[cfg(esp32s2)] { - if reg_block.slave().read().trans_done().bit() { + if self.regs().slave().read().trans_done().bit() { res.insert(SpiInterrupt::TransferDone); } - if reg_block.hold().read().dma_seg_trans_done().bit() { + if self.regs().hold().read().dma_seg_trans_done().bit() { res.insert(SpiInterrupt::DmaSegmentedTransferDone); } } else { - let ints = reg_block.dma_int_raw().read(); + let ints = self.regs().dma_int_raw().read(); if ints.trans_done().bit() { res.insert(SpiInterrupt::TransferDone); @@ -2815,13 +2805,12 @@ impl Driver { /// Resets asserted interrupts #[cfg_attr(not(feature = "unstable"), allow(dead_code))] fn clear_interrupts(&self, interrupts: EnumSet) { - let reg_block = self.register_block(); cfg_if::cfg_if! { if #[cfg(esp32)] { for interrupt in interrupts { match interrupt { SpiInterrupt::TransferDone => { - reg_block.slave().modify(|_, w| w.trans_done().clear_bit()); + self.regs().slave().modify(|_, w| w.trans_done().clear_bit()); } } } @@ -2829,18 +2818,18 @@ impl Driver { for interrupt in interrupts { match interrupt { SpiInterrupt::TransferDone => { - reg_block.slave().modify(|_, w| w.trans_done().clear_bit()); + self.regs().slave().modify(|_, w| w.trans_done().clear_bit()); } SpiInterrupt::DmaSegmentedTransferDone => { - reg_block + self.regs() .hold() .modify(|_, w| w.dma_seg_trans_done().clear_bit()); } } } } else { - reg_block.dma_int_clr().write(|w| { + self.regs().dma_int_clr().write(|w| { for interrupt in interrupts { match interrupt { SpiInterrupt::TransferDone => w.trans_done().clear_bit_by_one(), @@ -2863,13 +2852,11 @@ impl Driver { } fn set_data_mode(&self, data_mode: Mode) { - let reg_block = self.register_block(); - cfg_if::cfg_if! { if #[cfg(esp32)] { - let pin_reg = reg_block.pin(); + let pin_reg = self.regs().pin(); } else { - let pin_reg = reg_block.misc(); + let pin_reg = self.regs().misc(); } }; @@ -2877,7 +2864,7 @@ impl Driver { w.ck_idle_edge() .bit(matches!(data_mode, Mode::_2 | Mode::_3)) }); - reg_block.user().modify(|_, w| { + self.regs().user().modify(|_, w| { w.ck_out_edge() .bit(matches!(data_mode, Mode::_1 | Mode::_2)) }); @@ -2893,18 +2880,16 @@ impl Driver { }); } - enable_clocks(self.register_block(), false); + enable_clocks(self.regs(), false); // Change clock frequency self.setup(frequency); - enable_clocks(self.register_block(), true); + enable_clocks(self.regs(), true); } #[cfg(not(any(esp32, esp32c3, esp32s2)))] fn set_bit_order(&self, read_order: BitOrder, write_order: BitOrder) { - let reg_block = self.register_block(); - let read_value = match read_order { BitOrder::MsbFirst => 0, BitOrder::LsbFirst => 1, @@ -2913,7 +2898,7 @@ impl Driver { BitOrder::MsbFirst => 0, BitOrder::LsbFirst => 1, }; - reg_block.ctrl().modify(|_, w| unsafe { + self.regs().ctrl().modify(|_, w| unsafe { w.rd_bit_order().bits(read_value); w.wr_bit_order().bits(write_value); w @@ -2922,8 +2907,6 @@ impl Driver { #[cfg(any(esp32, esp32c3, esp32s2))] fn set_bit_order(&self, read_order: BitOrder, write_order: BitOrder) { - let reg_block = self.register_block(); - let read_value = match read_order { BitOrder::MsbFirst => false, BitOrder::LsbFirst => true, @@ -2932,7 +2915,7 @@ impl Driver { BitOrder::MsbFirst => false, BitOrder::LsbFirst => true, }; - reg_block.ctrl().modify(|_, w| { + self.regs().ctrl().modify(|_, w| { w.rd_bit_order().bit(read_value); w.wr_bit_order().bit(write_value); w @@ -2943,7 +2926,7 @@ impl Driver { fn fill_fifo(&self, chunk: &[u8]) { // TODO: replace with `array_chunks` and `from_le_bytes` let mut c_iter = chunk.chunks_exact(4); - let mut w_iter = self.register_block().w_iter(); + let mut w_iter = self.regs().w_iter(); for c in c_iter.by_ref() { if let Some(w_reg) = w_iter.next() { let word = (c[0] as u32) @@ -3052,7 +3035,7 @@ impl Driver { /// instead. #[cfg_attr(place_spi_driver_in_ram, ram)] fn read_bytes_from_fifo(&self, words: &mut [u8]) -> Result<(), Error> { - let reg_block = self.register_block(); + let reg_block = self.regs(); for chunk in words.chunks_mut(FIFO_SIZE) { self.configure_datalen(chunk.len(), 0); @@ -3070,7 +3053,7 @@ impl Driver { } fn busy(&self) -> bool { - let reg_block = self.register_block(); + let reg_block = self.regs(); reg_block.cmd().read().usr().bit_is_set() } @@ -3104,9 +3087,8 @@ impl Driver { } fn start_operation(&self) { - let reg_block = self.register_block(); self.update(); - reg_block.cmd().modify(|_, w| w.usr().set_bit()); + self.regs().cmd().modify(|_, w| w.usr().set_bit()); } /// Starts the operation and waits for it to complete. @@ -3142,7 +3124,7 @@ impl Driver { self.init_spi_data_mode(cmd.mode(), address.mode(), data_mode)?; - let reg_block = self.register_block(); + let reg_block = self.regs(); reg_block.user().modify(|_, w| { w.usr_miso_highpart().clear_bit(); w.usr_mosi_highpart().clear_bit(); @@ -3184,7 +3166,7 @@ impl Driver { } fn set_up_common_phases(&self, cmd: Command, address: Address, dummy: u8) { - let reg_block = self.register_block(); + let reg_block = self.regs(); if !cmd.is_none() { reg_block.user2().modify(|_, w| unsafe { w.usr_command_bitlen().bits((cmd.width() - 1) as u8); @@ -3216,7 +3198,7 @@ impl Driver { fn update(&self) { cfg_if::cfg_if! { if #[cfg(gdma)] { - let reg_block = self.register_block(); + let reg_block = self.regs(); reg_block.cmd().modify(|_, w| w.update().set_bit()); @@ -3232,7 +3214,7 @@ impl Driver { } fn configure_datalen(&self, rx_len_bytes: usize, tx_len_bytes: usize) { - let reg_block = self.register_block(); + let reg_block = self.regs(); let rx_len = rx_len_bytes as u32 * 8; let tx_len = tx_len_bytes as u32 * 8; @@ -3286,7 +3268,7 @@ macro_rules! spi_instance { #[inline(always)] fn info(&self) -> &'static Info { static INFO: Info = Info { - register_block: crate::peripherals::[]::PTR, + register_block: crate::peripherals::[]::regs(), peripheral: crate::system::Peripheral::[], interrupt: crate::peripherals::Interrupt::[], sclk: OutputSignal::$sclk, diff --git a/esp-hal/src/spi/slave.rs b/esp-hal/src/spi/slave.rs index 46e25842777..6fdeb3d13ac 100644 --- a/esp-hal/src/spi/slave.rs +++ b/esp-hal/src/spi/slave.rs @@ -433,6 +433,10 @@ pub mod dma { } impl DmaDriver { + fn regs(&self) -> &RegisterBlock { + self.info.regs() + } + #[allow(clippy::too_many_arguments)] unsafe fn start_transfer_dma( &self, @@ -469,15 +473,14 @@ pub mod dma { self.reset_dma_before_usr_cmd(); - let reg_block = self.info.register_block(); #[cfg(not(esp32))] - reg_block + self.regs() .dma_conf() .modify(|_, w| w.dma_slv_seg_trans_en().clear_bit()); self.clear_dma_interrupts(); self.info.setup_for_flush(); - reg_block.cmd().modify(|_, w| w.usr().set_bit()); + self.regs().cmd().modify(|_, w| w.usr().set_bit()); if read_buffer_len > 0 { rx.start_transfer()?; @@ -491,28 +494,21 @@ pub mod dma { } fn reset_dma_before_usr_cmd(&self) { - let reg_block = self.info.register_block(); #[cfg(gdma)] - reg_block.dma_conf().modify(|_, w| { + self.regs().dma_conf().modify(|_, w| { w.rx_afifo_rst().set_bit(); w.buf_afifo_rst().set_bit(); w.dma_afifo_rst().set_bit() }); - - #[cfg(pdma)] - let _ = reg_block; } fn enable_dma(&self) { - let reg_block = self.info.register_block(); #[cfg(gdma)] - { - reg_block.dma_conf().modify(|_, w| { - w.dma_tx_ena().set_bit(); - w.dma_rx_ena().set_bit(); - w.rx_eof_en().clear_bit() - }); - } + self.regs().dma_conf().modify(|_, w| { + w.dma_tx_ena().set_bit(); + w.dma_rx_ena().set_bit(); + w.rx_eof_en().clear_bit() + }); #[cfg(pdma)] { @@ -529,16 +525,14 @@ pub mod dma { .dma_conf() .modify(|_, w| w.dma_infifo_full_clr().bit(bit)); } - set_rst_bit(reg_block, true); - set_rst_bit(reg_block, false); + set_rst_bit(self.regs(), true); + set_rst_bit(self.regs(), false); } } fn clear_dma_interrupts(&self) { - let reg_block = self.info.register_block(); - #[cfg(gdma)] - reg_block.dma_int_clr().write(|w| { + self.regs().dma_int_clr().write(|w| { w.dma_infifo_full_err().clear_bit_by_one(); w.dma_outfifo_empty_err().clear_bit_by_one(); w.trans_done().clear_bit_by_one(); @@ -547,7 +541,7 @@ pub mod dma { }); #[cfg(pdma)] - reg_block.dma_int_clr().write(|w| { + self.regs().dma_int_clr().write(|w| { w.inlink_dscr_empty().clear_bit_by_one(); w.outlink_dscr_error().clear_bit_by_one(); w.inlink_dscr_error().clear_bit_by_one(); @@ -578,7 +572,6 @@ impl InstanceDma for crate::peripherals::SPI2 {} impl InstanceDma for crate::peripherals::SPI3 {} /// Peripheral data describing a particular SPI instance. -#[doc(hidden)] #[non_exhaustive] #[doc(hidden)] pub struct Info { @@ -606,39 +599,39 @@ pub struct Info { impl Info { /// Returns the register block for this SPI instance. #[instability::unstable] - pub fn register_block(&self) -> &RegisterBlock { + pub fn regs(&self) -> &RegisterBlock { unsafe { &*self.register_block } } fn reset_spi(&self) { - let reg_block = self.register_block(); - #[cfg(esp32)] { - reg_block.slave().modify(|_, w| w.sync_reset().set_bit()); - reg_block.slave().modify(|_, w| w.sync_reset().clear_bit()); + self.regs().slave().modify(|_, w| w.sync_reset().set_bit()); + self.regs() + .slave() + .modify(|_, w| w.sync_reset().clear_bit()); } #[cfg(not(esp32))] { - reg_block.slave().modify(|_, w| w.soft_reset().set_bit()); - reg_block.slave().modify(|_, w| w.soft_reset().clear_bit()); + self.regs().slave().modify(|_, w| w.soft_reset().set_bit()); + self.regs() + .slave() + .modify(|_, w| w.soft_reset().clear_bit()); } } #[cfg(esp32)] fn prepare_length_and_lines(&self, rx_len: usize, tx_len: usize) { - let reg_block = self.register_block(); - - reg_block + self.regs() .slv_rdbuf_dlen() .write(|w| unsafe { w.bits((rx_len as u32 * 8).saturating_sub(1)) }); - reg_block + self.regs() .slv_wrbuf_dlen() .write(|w| unsafe { w.bits((tx_len as u32 * 8).saturating_sub(1)) }); // SPI Slave mode on ESP32 requires MOSI/MISO enable - reg_block.user().modify(|_, w| { + self.regs().user().modify(|_, w| { w.usr_mosi().bit(rx_len > 0); w.usr_miso().bit(tx_len > 0) }); @@ -646,13 +639,11 @@ impl Info { /// Initialize for full-duplex 1 bit mode fn init(&self) { - let reg_block = self.register_block(); - - reg_block.clock().write(|w| unsafe { w.bits(0) }); - reg_block.user().write(|w| unsafe { w.bits(0) }); - reg_block.ctrl().write(|w| unsafe { w.bits(0) }); + self.regs().clock().write(|w| unsafe { w.bits(0) }); + self.regs().user().write(|w| unsafe { w.bits(0) }); + self.regs().ctrl().write(|w| unsafe { w.bits(0) }); - reg_block.slave().write(|w| { + self.regs().slave().write(|w| { #[cfg(esp32)] w.slv_wr_rd_buf_en().set_bit(); @@ -660,27 +651,26 @@ impl Info { }); self.reset_spi(); - reg_block.user().modify(|_, w| { + self.regs().user().modify(|_, w| { w.doutdin().set_bit(); w.sio().clear_bit() }); #[cfg(not(esp32))] - reg_block.misc().write(|w| unsafe { w.bits(0) }); + self.regs().misc().write(|w| unsafe { w.bits(0) }); } fn set_data_mode(&self, data_mode: Mode, dma: bool) { - let reg_block = self.register_block(); #[cfg(esp32)] { - reg_block.pin().modify(|_, w| { + self.regs().pin().modify(|_, w| { w.ck_idle_edge() .bit(matches!(data_mode, Mode::_0 | Mode::_1)) }); - reg_block + self.regs() .user() .modify(|_, w| w.ck_i_edge().bit(matches!(data_mode, Mode::_1 | Mode::_2))); - reg_block.ctrl2().modify(|_, w| unsafe { + self.regs().ctrl2().modify(|_, w| unsafe { match data_mode { Mode::_0 => { w.miso_delay_mode().bits(0); @@ -721,19 +711,19 @@ impl Info { #[cfg(not(esp32))] { _ = dma; - cfg_if::cfg_if! { - if #[cfg(esp32s2)] { - let ctrl1_reg = reg_block.ctrl1(); - } else { - let ctrl1_reg = reg_block.slave(); - } - } - reg_block.user().modify(|_, w| { + self.regs().user().modify(|_, w| { w.tsck_i_edge() .bit(matches!(data_mode, Mode::_1 | Mode::_2)); w.rsck_i_edge() .bit(matches!(data_mode, Mode::_1 | Mode::_2)) }); + cfg_if::cfg_if! { + if #[cfg(esp32s2)] { + let ctrl1_reg = self.regs().ctrl1(); + } else { + let ctrl1_reg = self.regs().slave(); + } + } ctrl1_reg.modify(|_, w| { w.clk_mode_13() .bit(matches!(data_mode, Mode::_1 | Mode::_3)) @@ -742,15 +732,13 @@ impl Info { } fn is_bus_busy(&self) -> bool { - let reg_block = self.register_block(); - #[cfg(pdma)] { - reg_block.slave().read().trans_done().bit_is_clear() + self.regs().slave().read().trans_done().bit_is_clear() } #[cfg(gdma)] { - reg_block.dma_int_raw().read().trans_done().bit_is_clear() + self.regs().dma_int_raw().read().trans_done().bit_is_clear() } } @@ -766,11 +754,11 @@ impl Info { // used in DMA mode. fn setup_for_flush(&self) { #[cfg(pdma)] - self.register_block() + self.regs() .slave() .modify(|_, w| w.trans_done().clear_bit()); #[cfg(gdma)] - self.register_block() + self.regs() .dma_int_clr() .write(|w| w.trans_done().clear_bit_by_one()); } @@ -791,7 +779,7 @@ macro_rules! spi_instance { #[inline(always)] fn info(&self) -> &'static Info { static INFO: Info = Info { - register_block: crate::peripherals::[]::PTR, + register_block: crate::peripherals::[]::regs(), peripheral: crate::system::Peripheral::[], sclk: InputSignal::$sclk, mosi: InputSignal::$mosi, diff --git a/esp-hal/src/timer/timg.rs b/esp-hal/src/timer/timg.rs index 56b50726a18..f20c47e23e5 100644 --- a/esp-hal/src/timer/timg.rs +++ b/esp-hal/src/timer/timg.rs @@ -123,7 +123,7 @@ impl TimerGroupInstance for TIMG0 { #[inline(always)] fn register_block() -> *const RegisterBlock { - Self::PTR + Self::regs() } fn configure_src_clk() { @@ -132,7 +132,7 @@ impl TimerGroupInstance for TIMG0 { // ESP32 has only APB clock source, do nothing } else if #[cfg(any(esp32c2, esp32c3, esp32s2, esp32s3))] { unsafe { - (*Self::register_block()) + (*::register_block()) .t(0) .config() .modify(|_, w| w.use_xtal().clear_bit()); @@ -160,7 +160,7 @@ impl TimerGroupInstance for TIMG0 { // ESP32, ESP32-S2, and ESP32-S3 use only ABP, do nothing } else if #[cfg(any(esp32c2, esp32c3))] { unsafe { - (*Self::register_block()) + (*::register_block()) .wdtconfig0() .modify(|_, w| w.wdt_use_xtal().clear_bit()); } @@ -185,7 +185,7 @@ impl TimerGroupInstance for crate::peripherals::TIMG1 { #[inline(always)] fn register_block() -> *const RegisterBlock { - Self::PTR + Self::regs() } fn configure_src_clk() { @@ -199,7 +199,7 @@ impl TimerGroupInstance for crate::peripherals::TIMG1 { .modify(|_, w| unsafe { w.tg1_timer_clk_sel().bits(TIMG_DEFAULT_CLK_SRC) }); } else if #[cfg(any(esp32s2, esp32s3))] { unsafe { - (*Self::register_block()) + (*::register_block()) .t(1) .config() .modify(|_, w| w.use_xtal().clear_bit()); diff --git a/esp-hal/src/trace.rs b/esp-hal/src/trace.rs index bc01f140363..be87ba18192 100644 --- a/esp-hal/src/trace.rs +++ b/esp-hal/src/trace.rs @@ -218,7 +218,7 @@ pub trait Instance: crate::private::Sealed { impl Instance for crate::peripherals::TRACE0 { fn register_block(&self) -> &RegisterBlock { - self + self.register_block() } fn peripheral(&self) -> crate::system::Peripheral { diff --git a/esp-hal/src/twai/mod.rs b/esp-hal/src/twai/mod.rs index 8a56f1af3c8..4ff7d4a729f 100644 --- a/esp-hal/src/twai/mod.rs +++ b/esp-hal/src/twai/mod.rs @@ -701,19 +701,13 @@ where ); // Set RESET bit to 1 - this.twai - .register_block() - .mode() - .write(|w| w.reset_mode().set_bit()); + this.regs().mode().write(|w| w.reset_mode().set_bit()); + // Enable extended register layout #[cfg(esp32)] - { - // Enable extended register layout - this.twai - .register_block() - .clock_divider() - .modify(|_, w| w.ext_mode().set_bit()); - } + this.regs() + .clock_divider() + .modify(|_, w| w.ext_mode().set_bit()); // Set up the GPIO pins. let rx_pull = if no_transceiver { @@ -736,20 +730,17 @@ where this.set_mode(TwaiMode::ListenOnly); // Set TEC to 0 - this.twai - .register_block() + this.regs() .tx_err_cnt() .write(|w| unsafe { w.tx_err_cnt().bits(0) }); // Set REC to 0 - this.twai - .register_block() + this.regs() .rx_err_cnt() .write(|w| unsafe { w.rx_err_cnt().bits(0) }); // Set EWL to 96 - this.twai - .register_block() + this.regs() .err_warning_limit() .write(|w| unsafe { w.err_warning_limit().bits(96) }); @@ -757,6 +748,10 @@ where this } + fn regs(&self) -> &RegisterBlock { + self.twai.register_block() + } + fn internal_set_interrupt_handler(&mut self, handler: InterruptHandler) { for core in crate::Cpu::other() { crate::interrupt::disable(core, self.twai.interrupt()); @@ -798,17 +793,11 @@ where // Enable /2 baudrate divider by setting `brp_div`. // `brp_div` is not an interrupt, it will prescale BRP by 2. Only available on // ESP32 Revision 2 or later. Reserved otherwise. - self.twai - .register_block() - .int_ena() - .modify(|_, w| w.brp_div().set_bit()); + self.regs().int_ena().modify(|_, w| w.brp_div().set_bit()); prescaler = timing.baud_rate_prescaler / 2; } else { // Disable /2 baudrate divider by clearing brp_div. - self.twai - .register_block() - .int_ena() - .modify(|_, w| w.brp_div().clear_bit()); + self.regs().int_ena().modify(|_, w| w.brp_div().clear_bit()); } } @@ -819,27 +808,20 @@ where let triple_sample = timing.triple_sample; // Set up the prescaler and sync jump width. - self.twai - .register_block() - .bus_timing_0() - .modify(|_, w| unsafe { - w.baud_presc().bits(prescale as _); - w.sync_jump_width().bits(sjw) - }); + self.regs().bus_timing_0().modify(|_, w| unsafe { + w.baud_presc().bits(prescale as _); + w.sync_jump_width().bits(sjw) + }); // Set up the time segment 1, time segment 2, and triple sample. - self.twai - .register_block() - .bus_timing_1() - .modify(|_, w| unsafe { - w.time_seg1().bits(tseg_1); - w.time_seg2().bits(tseg_2); - w.time_samp().bit(triple_sample) - }); + self.regs().bus_timing_1().modify(|_, w| unsafe { + w.time_seg1().bits(tseg_1); + w.time_seg2().bits(tseg_2); + w.time_samp().bit(triple_sample) + }); // disable CLKOUT - self.twai - .register_block() + self.regs() .clock_divider() .modify(|_, w| w.clock_off().set_bit()); } @@ -869,15 +851,14 @@ where return; }; - let register_block = self.twai.register_block(); // Set or clear the rx filter mode bit depending on the filter type. - register_block + self.regs() .mode() .modify(|_, w| w.rx_filter_mode().bit(*filter_type == FilterType::Single)); // Copy the filter to the peripheral. unsafe { - copy_to_data_register(register_block.data_0().as_ptr(), registers); + copy_to_data_register(self.regs().data_0().as_ptr(), registers); } } @@ -888,15 +869,14 @@ where /// warning interrupt will be triggered (given the enable signal is /// valid). pub fn set_error_warning_limit(&mut self, limit: u8) { - self.twai - .register_block() + self.regs() .err_warning_limit() .write(|w| unsafe { w.err_warning_limit().bits(limit) }); } /// Set the operating mode based on provided option fn set_mode(&self, mode: TwaiMode) { - self.twai.register_block().mode().modify(|_, w| { + self.regs().mode().modify(|_, w| { // self-test mode turns off acknowledgement requirement w.self_test_mode().bit(mode == TwaiMode::SelfTest); w.listen_only_mode().bit(mode == TwaiMode::ListenOnly) @@ -910,8 +890,7 @@ where self.set_mode(self.mode); // Clear the TEC and REC - self.twai - .register_block() + self.regs() .tx_err_cnt() .write(|w| unsafe { w.tx_err_cnt().bits(0) }); @@ -926,25 +905,21 @@ where } else { 0 }; - self.twai - .register_block() + self.regs() .rx_err_cnt() .write(|w| unsafe { w.rx_err_cnt().bits(rec) }); // Clear any interrupts by reading the status register cfg_if::cfg_if! { if #[cfg(any(esp32, esp32c3, esp32s2, esp32s3))] { - let _ = self.twai.register_block().int_raw().read(); + let _ = self.regs().int_raw().read(); } else { - let _ = self.twai.register_block().interrupt().read(); + let _ = self.regs().interrupt().read(); } } // Put the peripheral into operation mode by clearing the reset mode bit. - self.twai - .register_block() - .mode() - .modify(|_, w| w.reset_mode().clear_bit()); + self.regs().mode().modify(|_, w| w.reset_mode().clear_bit()); Twai { rx: TwaiRx { @@ -1048,8 +1023,12 @@ impl<'d, Dm> Twai<'d, Dm> where Dm: DriverMode, { + fn regs(&self) -> &RegisterBlock { + self.twai.register_block() + } + fn mode(&self) -> TwaiMode { - let mode = self.twai.register_block().mode().read(); + let mode = self.regs().mode().read(); if mode.self_test_mode().bit_is_set() { TwaiMode::SelfTest @@ -1065,10 +1044,7 @@ where pub fn stop(self) -> TwaiConfiguration<'d, Dm> { // Put the peripheral into reset/configuration mode by setting the reset mode // bit. - self.twai - .register_block() - .mode() - .modify(|_, w| w.reset_mode().set_bit()); + self.regs().mode().modify(|_, w| w.reset_mode().set_bit()); let mode = self.mode(); @@ -1084,32 +1060,17 @@ where /// Returns the value of the receive error counter. pub fn receive_error_count(&self) -> u8 { - self.twai - .register_block() - .rx_err_cnt() - .read() - .rx_err_cnt() - .bits() + self.regs().rx_err_cnt().read().rx_err_cnt().bits() } /// Returns the value of the transmit error counter. pub fn transmit_error_count(&self) -> u8 { - self.twai - .register_block() - .tx_err_cnt() - .read() - .tx_err_cnt() - .bits() + self.regs().tx_err_cnt().read().tx_err_cnt().bits() } /// Check if the controller is in a bus off state. pub fn is_bus_off(&self) -> bool { - self.twai - .register_block() - .status() - .read() - .bus_off_st() - .bit_is_set() + self.regs().status().read().bus_off_st().bit_is_set() } /// Get the number of messages that the peripheral has available in the @@ -1118,8 +1079,7 @@ where /// Note that this may not be the number of valid messages in the receive /// FIFO due to fifo overflow/overrun. pub fn num_available_messages(&self) -> u8 { - self.twai - .register_block() + self.regs() .rx_message_cnt() .read() .rx_message_counter() @@ -1135,7 +1095,7 @@ where /// error states. pub fn clear_receive_fifo(&self) { while self.num_available_messages() > 0 { - release_receive_fifo(self.twai.register_block()); + release_receive_fifo(self.regs()); } } @@ -1167,6 +1127,10 @@ impl TwaiTx<'_, Dm> where Dm: DriverMode, { + fn regs(&self) -> &RegisterBlock { + self.twai.register_block() + } + /// Transmit a frame. /// /// Because of how the TWAI registers are set up, we have to do some @@ -1180,8 +1144,7 @@ where /// functionality. See notes 1 and 2 in the "Frame Identifier" section /// of the reference manual. pub fn transmit(&mut self, frame: &EspTwaiFrame) -> nb::Result<(), EspTwaiError> { - let register_block = self.twai.register_block(); - let status = register_block.status().read(); + let status = self.regs().status().read(); // Check that the peripheral is not in a bus off state. if status.bus_off_st().bit_is_set() { @@ -1192,7 +1155,7 @@ where return nb::Result::Err(nb::Error::WouldBlock); } - write_frame(register_block, frame); + write_frame(self.regs(), frame); Ok(()) } @@ -1209,10 +1172,13 @@ impl TwaiRx<'_, Dm> where Dm: DriverMode, { + fn regs(&self) -> &RegisterBlock { + self.twai.register_block() + } + /// Receive a frame pub fn receive(&mut self) -> nb::Result { - let register_block = self.twai.register_block(); - let status = register_block.status().read(); + let status = self.regs().status().read(); // Check that the peripheral is not in a bus off state. if status.bus_off_st().bit_is_set() { @@ -1231,7 +1197,7 @@ where ))); } - Ok(read_frame(register_block)?) + Ok(read_frame(self.regs())?) } } @@ -1341,11 +1307,9 @@ pub trait Instance: Peripheral

+ Into + 'static { /// Enables interrupts for the TWAI peripheral. fn enable_interrupts(&self) { - let register_block = self.register_block(); - cfg_if::cfg_if! { if #[cfg(any(esp32, esp32c3, esp32s2, esp32s3))] { - register_block.int_ena().modify(|_, w| { + self.register_block().int_ena().modify(|_, w| { w.rx_int_ena().set_bit(); w.tx_int_ena().set_bit(); w.bus_err_int_ena().set_bit(); @@ -1353,7 +1317,7 @@ pub trait Instance: Peripheral

+ Into + 'static { w.err_passive_int_ena().set_bit() }); } else { - register_block.interrupt_enable().modify(|_, w| { + self.register_block().interrupt_enable().modify(|_, w| { w.ext_receive_int_ena().set_bit(); w.ext_transmit_int_ena().set_bit(); w.bus_err_int_ena().set_bit(); @@ -1675,8 +1639,7 @@ mod asynch { poll_fn(|cx| { self.twai.async_state().tx_waker.register(cx.waker()); - let register_block = self.twai.register_block(); - let status = register_block.status().read(); + let status = self.regs().status().read(); // Check that the peripheral is not in a bus off state. if status.bus_off_st().bit_is_set() { @@ -1687,7 +1650,7 @@ mod asynch { return Poll::Pending; } - write_frame(register_block, frame); + write_frame(self.regs(), frame); Poll::Ready(Ok(())) }) @@ -1706,8 +1669,7 @@ mod asynch { return Poll::Ready(result); } - let register_block = self.twai.register_block(); - let status = register_block.status().read(); + let status = self.regs().status().read(); // Check that the peripheral is not in a bus off state. if status.bus_off_st().bit_is_set() { @@ -1796,17 +1758,13 @@ mod asynch { #[handler] pub(super) fn twai0() { let twai = unsafe { TWAI0::steal() }; - let register_block = twai.register_block(); - let async_state = twai.async_state(); - handle_interrupt(register_block, async_state); + handle_interrupt(twai.register_block(), twai.async_state()); } #[cfg(twai1)] #[handler] pub(super) fn twai1() { let twai = unsafe { TWAI1::steal() }; - let register_block = twai.register_block(); - let async_state = twai.async_state(); - handle_interrupt(register_block, async_state); + handle_interrupt(twai.register_block(), twai.async_state()); } } diff --git a/esp-hal/src/uart.rs b/esp-hal/src/uart.rs index deeb3f8eeb9..189d119b758 100644 --- a/esp-hal/src/uart.rs +++ b/esp-hal/src/uart.rs @@ -649,7 +649,7 @@ where fn write_byte(&mut self, word: u8) { while self.tx_fifo_count() >= UART_FIFO_SIZE {} - self.register_block() + self.regs() .fifo() .write(|w| unsafe { w.rxfifo_rd_byte().bits(word) }); } @@ -658,12 +658,7 @@ where /// Returns the number of bytes currently in the TX FIFO for this UART /// instance. fn tx_fifo_count(&self) -> u16 { - self.register_block() - .status() - .read() - .txfifo_cnt() - .bits() - .into() + self.regs().status().read().txfifo_cnt().bits().into() } /// Flush the transmit buffer of the UART @@ -677,9 +672,9 @@ where /// currently being transmitted. fn is_tx_idle(&self) -> bool { #[cfg(esp32)] - let status = self.register_block().status(); + let status = self.regs().status(); #[cfg(not(esp32))] - let status = self.register_block().fsm_status(); + let status = self.regs().fsm_status(); status.read().st_utx_out().bits() == 0x0 } @@ -690,14 +685,14 @@ where /// `transmit break done`, `transmit break idle done`, and `transmit done` /// interrupts. fn disable_tx_interrupts(&self) { - self.register_block().int_clr().write(|w| { + self.regs().int_clr().write(|w| { w.txfifo_empty().clear_bit_by_one(); w.tx_brk_done().clear_bit_by_one(); w.tx_brk_idle_done().clear_bit_by_one(); w.tx_done().clear_bit_by_one() }); - self.register_block().int_ena().write(|w| { + self.regs().int_ena().write(|w| { w.txfifo_empty().clear_bit(); w.tx_brk_done().clear_bit(); w.tx_brk_idle_done().clear_bit(); @@ -705,8 +700,8 @@ where }); } - fn register_block(&self) -> &RegisterBlock { - self.uart.info().register_block() + fn regs(&self) -> &RegisterBlock { + self.uart.info().regs() } } @@ -781,6 +776,10 @@ impl<'d, Dm> UartRx<'d, Dm> where Dm: DriverMode, { + fn regs(&self) -> &RegisterBlock { + self.uart.info().regs() + } + /// Configure CTS pin pub fn with_cts(self, cts: impl Peripheral

+ 'd) -> Self { crate::into_mapped_ref!(cts); @@ -835,11 +834,11 @@ where if #[cfg(esp32s2)] { // On the ESP32-S2 we need to use PeriBus2 to read the FIFO: let fifo = unsafe { - &*((self.register_block().fifo().as_ptr() as *mut u8).add(0x20C00000) + &*((self.regs().fifo().as_ptr() as *mut u8).add(0x20C00000) as *mut crate::pac::uart0::FIFO) }; } else { - let fifo = self.register_block().fifo(); + let fifo = self.regs().fifo(); } } @@ -916,20 +915,14 @@ where #[allow(clippy::useless_conversion)] fn rx_fifo_count(&self) -> u16 { - let fifo_cnt: u16 = self - .register_block() - .status() - .read() - .rxfifo_cnt() - .bits() - .into(); + let fifo_cnt: u16 = self.regs().status().read().rxfifo_cnt().bits().into(); // Calculate the real count based on the FIFO read and write offset address: // https://www.espressif.com/sites/default/files/documentation/esp32_errata_en.pdf // section 3.17 #[cfg(esp32)] { - let status = self.register_block().mem_rx_status().read(); + let status = self.regs().mem_rx_status().read(); let rd_addr = status.mem_rx_rd_addr().bits(); let wr_addr = status.mem_rx_wr_addr().bits(); @@ -954,24 +947,20 @@ where /// `receive FIFO overflow`, `receive FIFO timeout`, and `AT command /// character detection` interrupts. fn disable_rx_interrupts(&self) { - self.register_block().int_clr().write(|w| { + self.regs().int_clr().write(|w| { w.rxfifo_full().clear_bit_by_one(); w.rxfifo_ovf().clear_bit_by_one(); w.rxfifo_tout().clear_bit_by_one(); w.at_cmd_char_det().clear_bit_by_one() }); - self.register_block().int_ena().write(|w| { + self.regs().int_ena().write(|w| { w.rxfifo_full().clear_bit(); w.rxfifo_ovf().clear_bit(); w.rxfifo_tout().clear_bit(); w.at_cmd_char_det().clear_bit() }); } - - fn register_block(&self) -> &RegisterBlock { - self.uart.info().register_block() - } } impl<'d> UartRx<'d, Blocking> { @@ -1113,9 +1102,9 @@ where self } - fn register_block(&self) -> &RegisterBlock { + fn regs(&self) -> &RegisterBlock { // `self.tx.uart` and `self.rx.uart` are the same - self.tx.uart.info().register_block() + self.tx.uart.info().regs() } /// Split the UART into a transmitter and receiver @@ -1151,42 +1140,38 @@ where /// Configures the AT-CMD detection settings #[instability::unstable] pub fn set_at_cmd(&mut self, config: AtCmdConfig) { - let register_block = self.register_block(); - #[cfg(not(any(esp32, esp32s2)))] - register_block + self.regs() .clk_conf() .modify(|_, w| w.sclk_en().clear_bit()); - register_block.at_cmd_char().write(|w| unsafe { + self.regs().at_cmd_char().write(|w| unsafe { w.at_cmd_char().bits(config.cmd_char); w.char_num().bits(config.char_num) }); if let Some(pre_idle_count) = config.pre_idle_count { - register_block + self.regs() .at_cmd_precnt() .write(|w| unsafe { w.pre_idle_num().bits(pre_idle_count as _) }); } if let Some(post_idle_count) = config.post_idle_count { - register_block + self.regs() .at_cmd_postcnt() .write(|w| unsafe { w.post_idle_num().bits(post_idle_count as _) }); } if let Some(gap_timeout) = config.gap_timeout { - register_block + self.regs() .at_cmd_gaptout() .write(|w| unsafe { w.rx_gap_tout().bits(gap_timeout as _) }); } #[cfg(not(any(esp32, esp32s2)))] - register_block - .clk_conf() - .modify(|_, w| w.sclk_en().set_bit()); + self.regs().clk_conf().modify(|_, w| w.sclk_en().set_bit()); - sync_regs(register_block); + sync_regs(self.regs()); } /// Flush the transmit buffer of the UART @@ -1210,7 +1195,7 @@ where .perip_clk_en0() .modify(|_, w| w.uart_mem_clk_en().set_bit()); } else { - self.register_block() + self.regs() .conf0() .modify(|_, w| w.mem_clk_en().set_bit()); } @@ -1225,17 +1210,13 @@ where // Setting err_wr_mask stops uart from storing data when data is wrong according // to reference manual - self.register_block() - .conf0() - .modify(|_, w| w.err_wr_mask().set_bit()); + self.regs().conf0().modify(|_, w| w.err_wr_mask().set_bit()); crate::rom::ets_delay_us(15); // Make sure we are starting in a "clean state" - previous operations might have // run into error conditions - self.register_block() - .int_clr() - .write(|w| unsafe { w.bits(u32::MAX) }); + self.regs().int_clr().write(|w| unsafe { w.bits(u32::MAX) }); Ok(()) } @@ -1267,9 +1248,9 @@ where .modify(|_, w| w.rst_core().bit(_enable)); } - rst_core(self.register_block(), true); + rst_core(self.regs(), true); PeripheralClockControl::reset(self.tx.uart.info().peripheral); - rst_core(self.register_block(), false); + rst_core(self.regs(), false); } } @@ -1567,7 +1548,7 @@ impl UartTxFuture { } fn triggered_events(&self) -> bool { - let interrupts_enabled = self.uart.register_block().int_ena().read(); + let interrupts_enabled = self.uart.regs().int_ena().read(); let mut event_triggered = false; for event in self.events { event_triggered |= match event { @@ -1579,7 +1560,7 @@ impl UartTxFuture { } fn enable_listen(&self, enable: bool) { - self.uart.register_block().int_ena().modify(|_, w| { + self.uart.regs().int_ena().modify(|_, w| { for event in self.events { match event { TxEvent::Done => w.tx_done().bit(enable), @@ -1719,16 +1700,15 @@ impl UartRx<'_, Async> { | RxEvent::GlitchDetected | RxEvent::ParityError; - let register_block = self.uart.info().register_block(); - if register_block.at_cmd_char().read().char_num().bits() > 0 { + if self.regs().at_cmd_char().read().char_num().bits() > 0 { events |= RxEvent::CmdCharDetected; } cfg_if::cfg_if! { if #[cfg(any(esp32c6, esp32h2))] { - let reg_en = register_block.tout_conf(); + let reg_en = self.regs().tout_conf(); } else { - let reg_en = register_block.conf1(); + let reg_en = self.regs().conf1(); } }; if reg_en.read().rx_tout_en().bit_is_set() { @@ -1744,7 +1724,7 @@ impl UartRx<'_, Async> { // data in the fifo, even if the interrupt is disabled and the status bit // cleared. Since we do not drain the fifo in the interrupt handler, we need to // reset the counter here, after draining the fifo. - self.register_block() + self.regs() .int_clr() .write(|w| w.rxfifo_tout().clear_bit_by_one()); @@ -1806,7 +1786,7 @@ impl embedded_io_async::Write for UartTx<'_, Async> { /// bit set. The fact that an interrupt has been disabled is used by the /// futures to detect that they should indeed resolve after being woken up pub(super) fn intr_handler(uart: &Info, state: &State) { - let interrupts = uart.register_block().int_st().read(); + let interrupts = uart.regs().int_st().read(); let interrupt_bits = interrupts.bits(); // = int_raw & int_ena let rx_wake = interrupts.rxfifo_full().bit_is_set() || interrupts.rxfifo_ovf().bit_is_set() @@ -1816,10 +1796,10 @@ pub(super) fn intr_handler(uart: &Info, state: &State) { || interrupts.frm_err().bit_is_set() || interrupts.parity_err().bit_is_set(); let tx_wake = interrupts.tx_done().bit_is_set() || interrupts.txfifo_empty().bit_is_set(); - uart.register_block() + uart.regs() .int_clr() .write(|w| unsafe { w.bits(interrupt_bits) }); - uart.register_block() + uart.regs() .int_ena() .modify(|r, w| unsafe { w.bits(r.bits() & !interrupt_bits) }); @@ -1869,26 +1849,24 @@ pub mod lp_uart { .modify(|_, w| unsafe { w.mcu_sel().bits(1) }); let mut me = Self { uart }; + let uart = me.uart.register_block(); // Set UART mode - do nothing for LP // Disable UART parity // 8-bit world // 1-bit stop bit - me.uart.conf0().modify(|_, w| unsafe { + uart.conf0().modify(|_, w| unsafe { w.parity().clear_bit(); w.parity_en().clear_bit(); w.bit_num().bits(0x3); w.stop_bit_num().bits(0x1) }); // Set tx idle - me.uart - .idle_conf() + uart.idle_conf() .modify(|_, w| unsafe { w.tx_idle_num().bits(0) }); // Disable hw-flow control - me.uart - .hwfc_conf() - .modify(|_, w| w.rx_flow_en().clear_bit()); + uart.hwfc_conf().modify(|_, w| w.rx_flow_en().clear_bit()); // Get source clock frequency // default == SOC_MOD_CLK_RTC_FAST == 2 @@ -1918,26 +1896,39 @@ pub mod lp_uart { } fn rxfifo_reset(&mut self) { - self.uart.conf0().modify(|_, w| w.rxfifo_rst().set_bit()); + self.uart + .register_block() + .conf0() + .modify(|_, w| w.rxfifo_rst().set_bit()); self.update(); - self.uart.conf0().modify(|_, w| w.rxfifo_rst().clear_bit()); + self.uart + .register_block() + .conf0() + .modify(|_, w| w.rxfifo_rst().clear_bit()); self.update(); } fn txfifo_reset(&mut self) { - self.uart.conf0().modify(|_, w| w.txfifo_rst().set_bit()); + self.uart + .register_block() + .conf0() + .modify(|_, w| w.txfifo_rst().set_bit()); self.update(); - self.uart.conf0().modify(|_, w| w.txfifo_rst().clear_bit()); + self.uart + .register_block() + .conf0() + .modify(|_, w| w.txfifo_rst().clear_bit()); self.update(); } fn update(&mut self) { - self.uart + let register_block = self.uart.register_block(); + register_block .reg_update() .modify(|_, w| w.reg_update().set_bit()); - while self.uart.reg_update().read().reg_update().bit_is_set() { + while register_block.reg_update().read().reg_update().bit_is_set() { // wait } } @@ -1948,7 +1939,7 @@ pub mod lp_uart { let max_div = 0b1111_1111_1111 - 1; let clk_div = clk.div_ceil(max_div * baudrate); - self.uart.clk_conf().modify(|_, w| unsafe { + self.uart.register_block().clk_conf().modify(|_, w| unsafe { w.sclk_div_a().bits(0); w.sclk_div_b().bits(0); w.sclk_div_num().bits(clk_div as u8 - 1); @@ -1965,6 +1956,7 @@ pub mod lp_uart { let divider = divider as u16; self.uart + .register_block() .clkdiv() .write(|w| unsafe { w.clkdiv().bits(divider).frag().bits(0) }); @@ -1981,21 +1973,26 @@ pub mod lp_uart { fn change_parity(&mut self, parity: Parity) -> &mut Self { if parity != Parity::None { self.uart + .register_block() .conf0() .modify(|_, w| w.parity().bit((parity as u8 & 0x1) != 0)); } - self.uart.conf0().modify(|_, w| match parity { - Parity::None => w.parity_en().clear_bit(), - Parity::Even => w.parity_en().set_bit().parity().clear_bit(), - Parity::Odd => w.parity_en().set_bit().parity().set_bit(), - }); + self.uart + .register_block() + .conf0() + .modify(|_, w| match parity { + Parity::None => w.parity_en().clear_bit(), + Parity::Even => w.parity_en().set_bit().parity().clear_bit(), + Parity::Odd => w.parity_en().set_bit().parity().set_bit(), + }); self } fn change_data_bits(&mut self, data_bits: DataBits) -> &mut Self { self.uart + .register_block() .conf0() .modify(|_, w| unsafe { w.bit_num().bits(data_bits as u8) }); @@ -2006,6 +2003,7 @@ pub mod lp_uart { fn change_stop_bits(&mut self, stop_bits: StopBits) -> &mut Self { self.uart + .register_block() .conf0() .modify(|_, w| unsafe { w.stop_bit_num().bits(stop_bits as u8) }); @@ -2015,6 +2013,7 @@ pub mod lp_uart { fn change_tx_idle(&mut self, idle_num: u16) -> &mut Self { self.uart + .register_block() .idle_conf() .modify(|_, w| unsafe { w.tx_idle_num().bits(idle_num) }); @@ -2093,13 +2092,13 @@ pub struct State { impl Info { /// Returns the register block for this UART instance. - pub fn register_block(&self) -> &RegisterBlock { + pub fn regs(&self) -> &RegisterBlock { unsafe { &*self.register_block } } /// Listen for the given interrupts fn enable_listen(&self, interrupts: EnumSet, enable: bool) { - let reg_block = self.register_block(); + let reg_block = self.regs(); reg_block.int_ena().modify(|_, w| { for interrupt in interrupts { @@ -2115,7 +2114,7 @@ impl Info { fn interrupts(&self) -> EnumSet { let mut res = EnumSet::new(); - let reg_block = self.register_block(); + let reg_block = self.regs(); let ints = reg_block.int_raw().read(); @@ -2133,7 +2132,7 @@ impl Info { } fn clear_interrupts(&self, interrupts: EnumSet) { - let reg_block = self.register_block(); + let reg_block = self.regs(); reg_block.int_clr().write(|w| { for interrupt in interrupts { @@ -2177,7 +2176,7 @@ impl Info { } fn enable_listen_rx(&self, events: EnumSet, enable: bool) { - self.register_block().int_ena().modify(|_, w| { + self.regs().int_ena().modify(|_, w| { for event in events { match event { RxEvent::FifoFull => w.rxfifo_full().bit(enable), @@ -2196,7 +2195,7 @@ impl Info { fn enabled_rx_events(&self, events: impl Into>) -> EnumSet { let events = events.into(); - let interrupts_enabled = self.register_block().int_ena().read(); + let interrupts_enabled = self.regs().int_ena().read(); let mut events_triggered = EnumSet::new(); for event in events { let event_triggered = match event { @@ -2218,7 +2217,7 @@ impl Info { fn rx_events(&self, events: impl Into>) -> EnumSet { let events = events.into(); - let interrupts_enabled = self.register_block().int_st().read(); + let interrupts_enabled = self.regs().int_st().read(); let mut events_triggered = EnumSet::new(); for event in events { let event_triggered = match event { @@ -2240,7 +2239,7 @@ impl Info { fn clear_rx_events(&self, events: impl Into>) { let events = events.into(); - self.register_block().int_clr().write(|w| { + self.regs().int_clr().write(|w| { for event in events { match event { RxEvent::FifoFull => w.rxfifo_full().clear_bit_by_one(), @@ -2283,7 +2282,7 @@ impl Info { return Err(ConfigError::UnsupportedFifoThreshold); } - self.register_block() + self.regs() .conf1() .modify(|_, w| unsafe { w.rxfifo_full_thrhd().bits(threshold as _) }); @@ -2312,7 +2311,7 @@ impl Info { } } - let register_block = self.register_block(); + let register_block = self.regs(); if let Some(timeout) = timeout { // the esp32 counts directly in number of symbols (symbol len fixed to 8) @@ -2373,7 +2372,7 @@ impl Info { let max_div = 0b1111_1111_1111 - 1; let clk_div = clk.div_ceil(max_div * baudrate); - self.register_block().clk_conf().write(|w| unsafe { + self.regs().clk_conf().write(|w| unsafe { w.sclk_sel().bits(match clock_source { ClockSource::Apb => 1, ClockSource::RcFast => 2, @@ -2389,7 +2388,7 @@ impl Info { let divider = (clk << 4) / (baudrate * clk_div); let divider_integer = (divider >> 4) as u16; let divider_frag = (divider & 0xf) as u8; - self.register_block() + self.regs() .clkdiv() .write(|w| unsafe { w.clkdiv().bits(divider_integer).frag().bits(divider_frag) }); } @@ -2399,7 +2398,7 @@ impl Info { } fn sync_regs(&self) { - sync_regs(self.register_block()); + sync_regs(self.regs()); } #[cfg(any(esp32c6, esp32h2))] @@ -2453,7 +2452,7 @@ impl Info { let divider = clk / baudrate; let divider = divider as u16; - self.register_block() + self.regs() .clkdiv() .write(|w| unsafe { w.clkdiv().bits(divider).frag().bits(0) }); @@ -2468,25 +2467,25 @@ impl Info { ClockSource::RefTick => crate::soc::constants::REF_TICK.to_Hz(), }; - self.register_block() + self.regs() .conf0() .modify(|_, w| w.tick_ref_always_on().bit(clock_source == ClockSource::Apb)); let divider = clk / baudrate; - self.register_block() + self.regs() .clkdiv() .write(|w| unsafe { w.clkdiv().bits(divider).frag().bits(0) }); } fn change_data_bits(&self, data_bits: DataBits) { - self.register_block() + self.regs() .conf0() .modify(|_, w| unsafe { w.bit_num().bits(data_bits as u8) }); } fn change_parity(&self, parity: Parity) { - self.register_block().conf0().modify(|_, w| match parity { + self.regs().conf0().modify(|_, w| match parity { Parity::None => w.parity_en().clear_bit(), Parity::Even => w.parity_en().set_bit().parity().clear_bit(), Parity::Odd => w.parity_en().set_bit().parity().set_bit(), @@ -2498,18 +2497,18 @@ impl Info { { // workaround for hardware issue, when UART stop bit set as 2-bit mode. if stop_bits == StopBits::_2 { - self.register_block() + self.regs() .rs485_conf() .modify(|_, w| w.dl1_en().bit(stop_bits == StopBits::_2)); - self.register_block() + self.regs() .conf0() .modify(|_, w| unsafe { w.stop_bit_num().bits(1) }); } } #[cfg(not(esp32))] - self.register_block() + self.regs() .conf0() .modify(|_, w| unsafe { w.stop_bit_num().bits(stop_bits as u8) }); } @@ -2520,8 +2519,8 @@ impl Info { sync_regs(reg_block); } - rxfifo_rst(self.register_block(), true); - rxfifo_rst(self.register_block(), false); + rxfifo_rst(self.regs(), true); + rxfifo_rst(self.regs(), false); } fn txfifo_reset(&self) { @@ -2530,8 +2529,8 @@ impl Info { sync_regs(reg_block); } - txfifo_rst(self.register_block(), true); - txfifo_rst(self.register_block(), false); + txfifo_rst(self.regs(), true); + txfifo_rst(self.regs(), false); } } diff --git a/esp-hal/src/usb_serial_jtag.rs b/esp-hal/src/usb_serial_jtag.rs index f83c8b04912..6d5403c982d 100644 --- a/esp-hal/src/usb_serial_jtag.rs +++ b/esp-hal/src/usb_serial_jtag.rs @@ -179,19 +179,22 @@ where } } + fn regs(&self) -> &RegisterBlock { + self.peripheral.register_block() + } + /// Write data to the serial output in chunks of up to 64 bytes pub fn write_bytes(&mut self, data: &[u8]) -> Result<(), Error> { - let reg_block = USB_DEVICE::register_block(); - for chunk in data.chunks(64) { for byte in chunk { - reg_block + self.regs() .ep1() .write(|w| unsafe { w.rdwr_byte().bits(*byte) }); } - reg_block.ep1_conf().modify(|_, w| w.wr_done().set_bit()); + self.regs().ep1_conf().modify(|_, w| w.wr_done().set_bit()); - while reg_block.ep1_conf().read().bits() & 0b011 == 0b000 { + // FIXME: raw register access + while self.regs().ep1_conf().read().bits() & 0b011 == 0b000 { // wait } } @@ -202,18 +205,15 @@ where /// Write data to the serial output in a non-blocking manner /// Requires manual flushing (automatically flushed every 64 bytes) pub fn write_byte_nb(&mut self, word: u8) -> nb::Result<(), Error> { - let reg_block = USB_DEVICE::register_block(); - - if reg_block + if self + .regs() .ep1_conf() .read() .serial_in_ep_data_free() .bit_is_set() { // the FIFO is not full - unsafe { - reg_block.ep1().write(|w| w.rdwr_byte().bits(word)); - } + unsafe { self.regs().ep1().write(|w| w.rdwr_byte().bits(word)) }; Ok(()) } else { @@ -223,10 +223,10 @@ where /// Flush the output FIFO and block until it has been sent pub fn flush_tx(&mut self) -> Result<(), Error> { - let reg_block = USB_DEVICE::register_block(); - reg_block.ep1_conf().modify(|_, w| w.wr_done().set_bit()); + self.regs().ep1_conf().modify(|_, w| w.wr_done().set_bit()); - while reg_block.ep1_conf().read().bits() & 0b011 == 0b000 { + // FIXME: raw register access + while self.regs().ep1_conf().read().bits() & 0b011 == 0b000 { // wait } @@ -235,10 +235,10 @@ where /// Flush the output FIFO but don't block if it isn't ready immediately pub fn flush_tx_nb(&mut self) -> nb::Result<(), Error> { - let reg_block = USB_DEVICE::register_block(); - reg_block.ep1_conf().modify(|_, w| w.wr_done().set_bit()); + self.regs().ep1_conf().modify(|_, w| w.wr_done().set_bit()); - if reg_block.ep1_conf().read().bits() & 0b011 == 0b000 { + // FIXME: raw register access + if self.regs().ep1_conf().read().bits() & 0b011 == 0b000 { Err(nb::Error::WouldBlock) } else { Ok(()) @@ -258,18 +258,21 @@ where } } + fn regs(&self) -> &RegisterBlock { + self.peripheral.register_block() + } + /// Read a byte from the UART in a non-blocking manner pub fn read_byte(&mut self) -> nb::Result { - let reg_block = USB_DEVICE::register_block(); - // Check if there are any bytes to read - if reg_block + if self + .regs() .ep1_conf() .read() .serial_out_ep_data_avail() .bit_is_set() { - let value = reg_block.ep1().read().rdwr_byte().bits(); + let value = self.regs().ep1().read().rdwr_byte().bits(); Ok(value) } else { @@ -294,21 +297,21 @@ where /// Listen for RX-PACKET-RECV interrupts pub fn listen_rx_packet_recv_interrupt(&mut self) { - USB_DEVICE::register_block() + self.regs() .int_ena() .modify(|_, w| w.serial_out_recv_pkt().set_bit()); } /// Stop listening for RX-PACKET-RECV interrupts pub fn unlisten_rx_packet_recv_interrupt(&mut self) { - USB_DEVICE::register_block() + self.regs() .int_ena() .modify(|_, w| w.serial_out_recv_pkt().clear_bit()); } /// Checks if RX-PACKET-RECV interrupt is set pub fn rx_packet_recv_interrupt_set(&mut self) -> bool { - USB_DEVICE::register_block() + self.regs() .int_st() .read() .serial_out_recv_pkt() @@ -317,7 +320,7 @@ where /// Reset RX-PACKET-RECV interrupt pub fn reset_rx_packet_recv_interrupt(&mut self) { - USB_DEVICE::register_block() + self.regs() .int_clr() .write(|w| w.serial_out_recv_pkt().clear_bit_by_one()); } @@ -371,8 +374,10 @@ where // connection. PeripheralClockControl::enable(crate::system::Peripheral::UsbDevice); - USB_DEVICE::disable_tx_interrupts(); - USB_DEVICE::disable_rx_interrupts(); + crate::into_ref!(usb_device); + + usb_device.disable_tx_interrupts(); + usb_device.disable_rx_interrupts(); #[cfg(any(esp32c3, esp32s3))] { @@ -381,7 +386,7 @@ where // On the esp32c3, and esp32s3 the USB_EXCHG_PINS efuse is bugged and // doesn't swap the pullups too, this works around that. if Efuse::read_bit(USB_EXCHG_PINS) { - USB_DEVICE::register_block().conf0().modify(|_, w| { + usb_device.register_block().conf0().modify(|_, w| { w.pad_pull_override().set_bit(); w.dm_pullup().clear_bit(); w.dp_pullup().set_bit() @@ -454,26 +459,26 @@ where #[doc(hidden)] pub trait Instance: crate::private::Sealed { /// Get a reference to the peripheral's underlying register block - fn register_block() -> &'static RegisterBlock; + fn register_block(&self) -> &RegisterBlock; /// Disable all transmit interrupts for the peripheral - fn disable_tx_interrupts() { - Self::register_block() + fn disable_tx_interrupts(&self) { + self.register_block() .int_ena() .modify(|_, w| w.serial_in_empty().clear_bit()); - Self::register_block() + self.register_block() .int_clr() .write(|w| w.serial_in_empty().clear_bit_by_one()); } /// Disable all receive interrupts for the peripheral - fn disable_rx_interrupts() { - Self::register_block() + fn disable_rx_interrupts(&self) { + self.register_block() .int_ena() .modify(|_, w| w.serial_out_recv_pkt().clear_bit()); - Self::register_block() + self.register_block() .int_clr() .write(|w| w.serial_out_recv_pkt().clear_bit_by_one()); } @@ -481,8 +486,8 @@ pub trait Instance: crate::private::Sealed { impl Instance for USB_DEVICE { #[inline(always)] - fn register_block() -> &'static RegisterBlock { - unsafe { &*USB_DEVICE::ptr() } + fn register_block(&self) -> &RegisterBlock { + USB_DEVICE::regs() } } @@ -638,25 +643,27 @@ static WAKER_RX: AtomicWaker = AtomicWaker::new(); #[cfg_attr(docsrs, doc(cfg(feature = "unstable")))] #[must_use = "futures do nothing unless you `.await` or poll them"] struct UsbSerialJtagWriteFuture<'d> { - _peripheral: PeripheralRef<'d, USB_DEVICE>, + peripheral: PeripheralRef<'d, USB_DEVICE>, } #[cfg(any(doc, feature = "unstable"))] #[cfg_attr(docsrs, doc(cfg(feature = "unstable")))] impl<'d> UsbSerialJtagWriteFuture<'d> { - fn new(_peripheral: impl Peripheral

+ 'd) -> Self { - crate::into_ref!(_peripheral); + fn new(peripheral: impl Peripheral

+ 'd) -> Self { + crate::into_ref!(peripheral); // Set the interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT // interrupt - USB_DEVICE::register_block() + peripheral + .register_block() .int_ena() .modify(|_, w| w.serial_in_empty().set_bit()); - Self { _peripheral } + Self { peripheral } } fn event_bit_is_clear(&self) -> bool { - USB_DEVICE::register_block() + self.peripheral + .register_block() .int_ena() .read() .serial_in_empty() @@ -686,25 +693,27 @@ impl core::future::Future for UsbSerialJtagWriteFuture<'_> { #[cfg(any(doc, feature = "unstable"))] #[cfg_attr(docsrs, doc(cfg(feature = "unstable")))] struct UsbSerialJtagReadFuture<'d> { - _peripheral: PeripheralRef<'d, USB_DEVICE>, + peripheral: PeripheralRef<'d, USB_DEVICE>, } #[cfg(any(doc, feature = "unstable"))] #[cfg_attr(docsrs, doc(cfg(feature = "unstable")))] impl<'d> UsbSerialJtagReadFuture<'d> { - fn new(_peripheral: impl Peripheral

+ 'd) -> Self { - crate::into_ref!(_peripheral); + fn new(peripheral: impl Peripheral

+ 'd) -> Self { + crate::into_ref!(peripheral); // Set the interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT // interrupt - USB_DEVICE::register_block() + peripheral + .register_block() .int_ena() .modify(|_, w| w.serial_out_recv_pkt().set_bit()); - Self { _peripheral } + Self { peripheral } } fn event_bit_is_clear(&self) -> bool { - USB_DEVICE::register_block() + self.peripheral + .register_block() .int_ena() .read() .serial_out_recv_pkt() @@ -752,15 +761,13 @@ impl UsbSerialJtagTx<'_, Async> { #[cfg(any(doc, feature = "unstable"))] #[cfg_attr(docsrs, doc(cfg(feature = "unstable")))] async fn write_bytes_async(&mut self, words: &[u8]) -> Result<(), Error> { - let reg_block = USB_DEVICE::register_block(); - for chunk in words.chunks(64) { for byte in chunk { - reg_block + self.regs() .ep1() .write(|w| unsafe { w.rdwr_byte().bits(*byte) }); } - reg_block.ep1_conf().modify(|_, w| w.wr_done().set_bit()); + self.regs().ep1_conf().modify(|_, w| w.wr_done().set_bit()); UsbSerialJtagWriteFuture::new(self.peripheral.reborrow()).await; } @@ -771,7 +778,8 @@ impl UsbSerialJtagTx<'_, Async> { #[cfg(any(doc, feature = "unstable"))] #[cfg_attr(docsrs, doc(cfg(feature = "unstable")))] async fn flush_tx_async(&mut self) -> Result<(), Error> { - if USB_DEVICE::register_block() + if self + .regs() .jfifo_st() .read() .out_fifo_empty() diff --git a/hil-test/tests/interrupt.rs b/hil-test/tests/interrupt.rs index 4d1c3bff15c..bee4e190eaa 100644 --- a/hil-test/tests/interrupt.rs +++ b/hil-test/tests/interrupt.rs @@ -77,7 +77,7 @@ mod tests { } } - let sw0_trigger_addr = cpu_intr.cpu_intr_from_cpu_0() as *const _ as u32; + let sw0_trigger_addr = cpu_intr.register_block().cpu_intr_from_cpu_0() as *const _ as u32; critical_section::with(|cs| { SWINT0