From 0782ff73d82f4ac3b4402d89236008da48455a03 Mon Sep 17 00:00:00 2001 From: Taji Hossein Date: Fri, 31 Mar 2023 11:45:48 +0200 Subject: [PATCH 01/22] add code structure --- sw/device/lib/drivers/gpio/gpio.c | 80 +++++++++++++++++++++++++++ sw/device/lib/drivers/gpio/gpio.h | 89 +++++++++++++++++++++++++++---- 2 files changed, 158 insertions(+), 11 deletions(-) diff --git a/sw/device/lib/drivers/gpio/gpio.c b/sw/device/lib/drivers/gpio/gpio.c index 597cc0604..cefdf44f6 100644 --- a/sw/device/lib/drivers/gpio/gpio.c +++ b/sw/device/lib/drivers/gpio/gpio.c @@ -1,3 +1,83 @@ +/* + ******************* +******************************* C SOURCE FILE ***************************** +** ******************* +** +** project : X-HEEP +** filename : gpio.c +** +*************************************************************************** +** +** Copyright (c) EPFL contributors. +** All rights reserved. +** +*************************************************************************** +*/ + +/***************************************************************************/ +/***************************************************************************/ +/** +* @file gpio.c +* @date 30/03/2023 +* @author Hossein taji +* @version 1 +* @brief GPIO driver +*/ + +/****************************************************************************/ +/** **/ +/* MODULES USED */ +/** **/ +/****************************************************************************/ + +/****************************************************************************/ +/** **/ +/* DEFINITIONS AND MACROS */ +/** **/ +/****************************************************************************/ + +/****************************************************************************/ +/** **/ +/* TYPEDEFS AND STRUCTURES */ +/** **/ +/****************************************************************************/ + +/****************************************************************************/ +/** **/ +/* PROTOTYPES OF LOCAL FUNCTIONS */ +/** **/ +/****************************************************************************/ + +/****************************************************************************/ +/** **/ +/* EXPORTED VARIABLES */ +/** **/ +/****************************************************************************/ + +/****************************************************************************/ +/** **/ +/* GLOBAL VARIABLES */ +/** **/ +/****************************************************************************/ + +/****************************************************************************/ +/** **/ +/* EXPORTED FUNCTIONS */ +/** **/ +/****************************************************************************/ + +/****************************************************************************/ +/** **/ +/* LOCAL FUNCTIONS */ +/** **/ +/****************************************************************************/ + +/****************************************************************************/ +/** **/ +/* EOF */ +/** **/ +/****************************************************************************/ + // Copyright lowRISC contributors. // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 diff --git a/sw/device/lib/drivers/gpio/gpio.h b/sw/device/lib/drivers/gpio/gpio.h index a6879371c..bc80bba24 100644 --- a/sw/device/lib/drivers/gpio/gpio.h +++ b/sw/device/lib/drivers/gpio/gpio.h @@ -1,26 +1,93 @@ -// Copyright lowRISC contributors. -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 +/* + ******************* +******************************* H SOURCE FILE ******************************* +** ******************* ** +** ** +** project : X-HEEP ** +** filename : gpio.h ** +** ** +***************************************************************************** +** +** Copyright (c) EPFL contributors. +** All rights reserved. +** +***************************************************************************** +*/ -// Modified version for core-v-mini-mcu -// original at: https://github.com/lowRISC/opentitan/blob/master/sw/ +/***************************************************************************/ +/***************************************************************************/ +/** +* @file gpio.h +* @date 30/03/2023 +* @author Hossein taji +* @version 1 +* @brief GPIO driver +*/ #ifndef GPIO_H_ #define GPIO_H_ -/** - * @file - * @brief GPIO Device Interface Functions - */ +#ifdef __cplusplus +extern "C" { +#endif + +/****************************************************************************/ +/** **/ +/** MODULES USED **/ +/** **/ +/****************************************************************************/ #include #include #include "mmio.h" +/****************************************************************************/ +/** **/ +/** DEFINITIONS AND MACROS **/ +/** **/ +/****************************************************************************/ + +/****************************************************************************/ +/** **/ +/** TYPEDEFS AND STRUCTURES **/ +/** **/ +/****************************************************************************/ + +/****************************************************************************/ +/** **/ +/** EXPORTED VARIABLES **/ +/** **/ +/****************************************************************************/ + +/****************************************************************************/ +/** **/ +/** EXPORTED FUNCTIONS **/ +/** **/ +/****************************************************************************/ + +/****************************************************************************/ +/** **/ +/** INLINE FUNCTIONS **/ +/** **/ +/****************************************************************************/ + +/****************************************************************************/ +/** **/ +/** EOF **/ +/** **/ +/****************************************************************************/ #ifdef __cplusplus -extern "C" { -#endif // __cplusplus +} +#endif + +#endif // _GPIO_H_ + + + + + + /** * A toggle state: enabled, or disabled. From 4c13714bcda141225cc7c2398ca4999abf679efb Mon Sep 17 00:00:00 2001 From: Hossein Date: Tue, 4 Apr 2023 09:37:37 +0200 Subject: [PATCH 02/22] Adding gpio functionalities --- sw/device/lib/drivers/gpio/gpio.c | 568 +++++++++++++++++++++++++++++- sw/device/lib/drivers/gpio/gpio.h | 284 ++++++++++++++- 2 files changed, 849 insertions(+), 3 deletions(-) diff --git a/sw/device/lib/drivers/gpio/gpio.c b/sw/device/lib/drivers/gpio/gpio.c index cefdf44f6..73a170ab5 100644 --- a/sw/device/lib/drivers/gpio/gpio.c +++ b/sw/device/lib/drivers/gpio/gpio.c @@ -30,6 +30,11 @@ /** **/ /****************************************************************************/ +#include "gpio.h" +#include "gpio_regs.h" // Generated. +#include "gpio_structs.h" +#include "mmio.h" + /****************************************************************************/ /** **/ /* DEFINITIONS AND MACROS */ @@ -47,7 +52,30 @@ /* PROTOTYPES OF LOCAL FUNCTIONS */ /** **/ /****************************************************************************/ +/** + * @brief get some bitfield of a 32b reg. + * @param reg the register that bitwise field selects from. + * @param mask the mask w/o offset. + * @param sel this the offset used for mask and value. + */ +static inline uint32_t getBitfield( uint32_t reg, uint32_t mask, uint8_t sel ) +{ + return (reg & ( mask << sel )); +} +/** + * @brief do a bitwise operation on 32b register. + * @param reg the register pointer that bitwise operation is done on it. + * @param val the value should be written in part of reg w/o offset. + * @param mask the mask w/o offset. + * @param sel this the offset used for mask and value. + */ +static inline void setBitfield( uint32_t *reg, uint32_t val, + uint32_t mask, uint8_t sel ) +{ + *reg &= ~( mask << sel ); + *reg |= (val & mask) << sel; +} /****************************************************************************/ /** **/ /* EXPORTED VARIABLES */ @@ -66,12 +94,550 @@ /** **/ /****************************************************************************/ +gpio_result_t gpio_set_mode (gpio_pin_number_t pin, gpio_mode_t mode) +{ + if (pin >= 0 && pin < 16) + { + setBitfield(&(gpio_peri->GPIO_MODE0), mode, 0b11, 2*pin); + return GpioOk; + } + else if (pin >= 16 && pin <32) + { + reg = setBit(&(gpio_peri->GPIO_MODE1), mode, 0b11, 2*(pin-16)); + return GpioOk; + } + else + { + return GpioError; + } +} + +gpio_result_t gpio_en_input (gpio_pin_number_t pin) +{ + if (pin >= 0 && pin < 32) + { + setBitfield(&(gpio_peri->GPIO_EN0), 1, 0b1, pin); + return GpioOk; + } + else + { + return GpioError; + } +} + +gpio_result_t gpio_dis_input (gpio_pin_number_t pin) +{ + if (pin >= 0 && pin < 32) + { + setBitfield(&(gpio_peri->GPIO_EN0), 0, 0b1, pin); + return GpioOk; + } + else + { + return GpioError; + } +} + +gpio_result_t gpio_pin_reset (gpio_pin_number_t pin) +{ + if (pin >= 0 && pin < 32) + { + gpio_intr_mode (0); + gpio_set_mode (pin, GpioModeIn); + gpio_dis_input (pin); + setBitfield(&(gpio_peri->GPIO_CLEAR0), 0, 0b1, pin); + setBitfield(&(gpio_peri->GPIO_SET0), 0, 0b1, pin); + gpio_intr_dis_all(pin); + gpio_intr_clear_stat(pin); + return GpioOk; + } + else + { + return GpioError; + } +} + +gpio_result_t gpio_reset_all (void) +{ + setBitfield(&(gpio_peri->GPIO_CLEAR0), 0, 0b1, 0); + gpio_peri->GPIO_MODE0 = 0; + gpio_peri->GPIO_MODE1 = 0; + gpio_peri->GPIO_EN0 = 0; + gpio_peri->GPIO_CLEAR0 = 0; + gpio_peri->GPIO_SET0 = 0; + gpio_peri->GPIO_TOGGLE0 = 0; + gpio_peri->INTRPT_RISE_EN0 = 0; + gpio_peri->INTRPT_FALL_EN0 = 0; + gpio_peri->INTRPT_LVL_HIGH_EN0 = 0; + gpio_peri->INTRPT_LVL_LOW_EN0 = 0; + gpio_peri->INTRPT_STATUS0 = 0xFFFFFFFF; +} + +gpio_result_t gpio_pin_read (gpio_pin_number_t pin, bool *val) +{ + if (pin >= 0 && pin < 32) + { + if ( getBitfield(gpio_peri->GPIO_IN0, 0b1, pin) == 1) + *val = true; + else + *val = false; + return GpioOk; + } + else + { + return GpioError; + } +} + +// gpio_result_t gpio_pin_set (gpio_pin_number_t pin) +// { +// if (pin >= 0 && pin < 32) +// { +// gpio_peri->GPIO_SET0 = 1 << pin; +// gpio_peri->GPIO_OUT0 = 1 << pin; +// return GpioOk; +// } +// else +// { +// return GpioError; +// } +// } + +// gpio_result_t gpio_pin_clear (gpio_pin_number_t pin) +// { +// if (pin >= 0 && pin < 32) +// { +// gpio_peri->GPIO_CLEAR0 = 1 << pin; +// gpio_peri->GPIO_OUT0 &= ~(1 << pin); +// return GpioOk; +// } +// else +// { +// return GpioError; +// } +// } + +//todo: check to see its toggling or just writing one +gpio_result_t gpio_pin_toggle (gpio_pin_number_t pin) +{ + if (pin >= 0 && pin < 32) + { + gpio_peri->GPIO_TOGGLE0 = 1 << pin; + gpio_peri->GPIO_OUT0 = 1 << pin; + return GpioOk; + } + else + { + return GpioError; + } +} + +gpio_result_t gpio_pin_write (gpio_pin_number_t pin, gpio_value val) +{ + if (pin >= 0 && pin < 32) + { + if (val == true) + setBitfield(&(gpio_peri->GPIO_OUT0), 1, 1, pin); + else + setBitfield(&(gpio_peri->GPIO_OUT0), 0, 1, pin); + return GpioOk; + } + else + { + return GpioError; + } +} + +gpio_result_t gpio_intr_en_rise (gpio_pin_number_t pin) +{ + if (pin >= 0 && pin < 32) + { + setBitfield(&(gpio_peri->INTRPT_RISE_EN0), 1, 1, pin); + return GpioOk; + } + else + { + return GpioError; + } +} + +gpio_result_t gpio_intr_en_fall (gpio_pin_number_t pin) +{ + if (pin >= 0 && pin < 32) + { + setBitfield(&(gpio_peri->INTRPT_FALL_EN0), 1, 1, pin); + return GpioOk; + } + else + { + return GpioError; + } +} + +gpio_result_t gpio_intr_en_lvl_high (gpio_pin_number_t pin) +{ + if (pin >= 0 && pin < 32) + { + setBitfield(&(gpio_peri->INTRPT_LVL_HIGH_EN0), 1, 1, pin); + return GpioOk; + } + else + { + return GpioError; + } +} + +gpio_result_t gpio_intr_en_lvl_low (gpio_pin_number_t pin) +{ + if (pin >= 0 && pin < 32) + { + setBitfield(&(gpio_peri->INTRPT_LVL_LOW_EN0), 1, 1, pin); + return GpioOk; + } + else + { + return GpioError; + } +} + +gpio_result_t gpio_intr_dis_rise (gpio_pin_number_t pin) +{ + if (pin >= 0 && pin < 32) + { + setBitfield(&(gpio_peri->INTRPT_RISE_EN0), 0, 1, pin); + return GpioOk; + } + else + { + return GpioError; + } +} + +gpio_result_t gpio_intr_dis_fall (gpio_pin_number_t pin) +{ + if (pin >= 0 && pin < 32) + { + setBitfield(&(gpio_peri->INTRPT_FALL_EN0), 0, 1, pin); + return GpioOk; + } + else + { + return GpioError; + } +} + +gpio_result_t gpio_intr_dis_lvl_high (gpio_pin_number_t pin) +{ + if (pin >= 0 && pin < 32) + { + setBitfield(&(gpio_peri->INTRPT_LVL_HIGH_EN0), 0, 1, pin); + return GpioOk; + } + else + { + return GpioError; + } +} + +gpio_result_t gpio_intr_dis_lvl_low (gpio_pin_number_t pin) +{ + if (pin >= 0 && pin < 32) + { + setBitfield(&(gpio_peri->INTRPT_LVL_LOW_EN0), 0, 1, pin); + return GpioOk; + } + else + { + return GpioError; + } +} + +gpio_result_t gpio_intr_dis_all (gpio_pin_number_t pin){ + if (pin >= 0 && pin < 32) + { + setBitfield(&(gpio_peri->INTRPT_RISE_EN0), 0, 1, pin); + setBitfield(&(gpio_peri->INTRPT_FALL_EN0), 0, 1, pin); + setBitfield(&(gpio_peri->INTRPT_LVL_HIGH_EN0), 0, 1, pin); + setBitfield(&(gpio_peri->INTRPT_LVL_LOW_EN0), 0, 1, pin); + return GpioOk; + } + else + { + return GpioError; + } + +} + +gpio_result_t gpio_intr_en (gpio_pin_number_t pin, gpio_intr_type_t type) +{ + if (pin >= 0 && pin < 32) + { + gpio_intr_dis_all(pin); + + switch(type) + { + case GpioIntrEdgeRising: + gpio_intr_en_rise(pin); + break; + + case GpioIntrEdgeFalling: + gpio_intr_en_fall(pin); + break; + + case GpioIntrLevelLow: + gpio_intr_en_lvl_low(pin); + break; + + case GpioIntrLevelHigh: + gpio_intr_en_lvl_high(pin); + break; + + case GpioIntrEdgeRisingFalling: + gpio_intr_en_rise(pin); + gpio_intr_en_fall(pin); + break; + + case GpioIntrEdgeRisingLevelLow: + gpio_intr_en_rise(pin); + gpio_intr_en_lvl_low(pin); + break; + + case GpioIntrEdgeFallingLevelHigh: + gpio_intr_en_fall(pin); + gpio_intr_en_lvl_high(pin); + break; + + default: + return GpioError; + } + return GpioOk; + } + else + { + return GpioError; + } +} + +// gpio_result_t gpio_intr_dis (gpio_pin_number_t pin, gpio_intr_type_t type) +// { +// if (pin >= 0 && pin < 32) +// { +// switch(type) +// { +// case GpioIntrEdgeRising: +// gpio_intr_dis_rise(pin); +// break; + +// case GpioIntrEdgeFalling: +// gpio_intr_dis_fall(pin); +// break; + +// case GpioIntrLevelLow: +// gpio_intr_dis_lvl_low(pin); +// break; + +// case GpioIntrLevelHigh: +// gpio_intr_dis_lvl_high(pin); +// break; + +// case GpioIntrEdgeRisingFalling: +// gpio_intr_dis_rise(pin); +// gpio_intr_dis_fall(pin); +// break; + +// case GpioIntrEdgeRisingLevelLow: +// gpio_intr_dis_rise(pin); +// gpio_intr_dis_lvl_low(pin); +// break; + +// case GpioIntrEdgeFallingLevelHigh: +// gpio_intr_dis_fall(pin); +// gpio_intr_dis_lvl_high(pin); +// break; + +// default: +// return GpioError; +// } +// return GpioOk; +// } +// else +// { +// return GpioError; +// } +// } + +gpio_result_t gpio_intr_check_stat_rise (gpio_pin_number_t pin, bool *is_pending) +{ + if (pin >= 0 && pin < 32) + { + if (getBitfield(gpio_peri->INTRPT_RISE_STATUS0, 1, pin) == 1) + *is_pending = true; + else + *is_pending = false; + return GpioOk; + } + else + { + *is_pending = false; + return GpioError; + } +} + +gpio_result_t gpio_intr_check_stat_fall (gpio_pin_number_t pin, bool *is_pending) +{ + if (pin >= 0 && pin < 32) + { + if (getBitfield(gpio_peri->INTRPT_FALL_STATUS0, 1, pin) == 1) + *is_pending = true; + else + *is_pending = false; + return GpioOk; + } + else + { + *is_pending = false; + return GpioError; + } +} + +gpio_result_t gpio_intr_check_stat_lvl_low (gpio_pin_number_t pin, bool *is_pending) +{ + if (pin >= 0 && pin < 32) + { + if (getBitfield(gpio_peri->INTRPT_LVL_LOW_STATUS0, 1, pin) == 1) + *is_pending = true; + else + *is_pending = false; + return GpioOk; + } + else + { + *is_pending = false; + return GpioError; + } +} + +gpio_result_t gpio_intr_check_stat_lvl_high (gpio_pin_number_t pin, bool *is_pending) +{ + if (pin >= 0 && pin < 32) + { + if (getBitfield(gpio_peri->INTRPT_LVL_HIGH_STATUS0, 1, pin) == 1) + *is_pending = true; + else + *is_pending = false; + return GpioOk; + } + else + { + *is_pending = false; + return GpioError; + } +} + +gpio_result_t gpio_intr_check_stat (gpio_pin_number_t pin, bool *is_pending) +{ + if (pin >= 0 && pin < 32) + { + if (getBitfield(gpio_peri->INTRPT_STATUS0, 1, pin) == 1) + *is_pending = true; + else + *is_pending = false; + return GpioOk; + } + else + { + *is_pending = false; + return GpioError; + } +} + +gpio_result_t gpio_intr_clear_stat_rise (gpio_pin_number_t pin) +{ + if (pin >= 0 && pin < 32) + { + setBitfield(&(gpio_peri->INTRPT_RISE_STATUS0), 1, 1, pin); + return GpioOk; + } + else + { + return GpioError; + } +} + +gpio_result_t gpio_intr_clear_stat_fall (gpio_pin_number_t pin) +{ + if (pin >= 0 && pin < 32) + { + setBitfield(&(gpio_peri->INTRPT_FALL_STATUS0), 1, 1, pin); + return GpioOk; + } + else + { + return GpioError; + } +} + +gpio_result_t gpio_intr_clear_stat_lvl_low (gpio_pin_number_t pin) +{ + if (pin >= 0 && pin < 32) + { + setBitfield(&(gpio_peri->INTRPT_LVL_LOW_STATUS0), 1, 1, pin); + return GpioOk; + } + else + { + return GpioError; + } +} + +gpio_result_t gpio_intr_clear_stat_lvl_high (gpio_pin_number_t pin) +{ + if (pin >= 0 && pin < 32) + { + setBitfield(&(gpio_peri->INTRPT_LVL_HIGH_STATUS0), 1, 1, pin); + return GpioOk; + } + else + { + return GpioError; + } +} + +gpio_result_t gpio_intr_clear_stat (gpio_pin_number_t pin) +{ + if (pin >= 0 && pin < 32) + { + setBitfield(&(gpio_peri->INTRPT_STATUS0), 1, 1, pin); + return GpioOk; + } + else + { + return GpioError; + } +} + +gpio_result_t gpio_intr_mode (bool gpio_intr_mode) +{ + if (pin >= 0 && pin < 32) + { + if (gpio_intr_mode) + setBitfield(&(gpio_peri->CFG), 1, 1, 0); + else + setBitfield(&(gpio_peri->CFG), 0, 1, 0); + return GpioOk; + } + else + { + return GpioError; + } +} /****************************************************************************/ /** **/ /* LOCAL FUNCTIONS */ /** **/ /****************************************************************************/ + /****************************************************************************/ /** **/ /* EOF */ @@ -85,9 +651,7 @@ // Modified version for core-v-mini-mcu // original at: https://github.com/lowRISC/opentitan/blob/master/sw/ -#include "gpio.h" -#include "gpio_regs.h" // Generated. /** * Gives the mask that corresponds to the given bit index. diff --git a/sw/device/lib/drivers/gpio/gpio.h b/sw/device/lib/drivers/gpio/gpio.h index bc80bba24..6f3361637 100644 --- a/sw/device/lib/drivers/gpio/gpio.h +++ b/sw/device/lib/drivers/gpio/gpio.h @@ -48,35 +48,318 @@ extern "C" { /** **/ /****************************************************************************/ +/** + * The format use for pin number. As the gpio pins are only 32 number, + * uint8_t would be enough. + */ +typedef uint8_t gpio_pin_number_t; + +/** + * gpio mode. + * 0 configure GPIO as input. 1 configures GPIO as a push-pull output. + * 2 configures the GPIO to be in open_drain0 (0 -> High-Z, 1 -> Drive High) + * mode. 3 configures the GPIO to be in open_drain1 (0 -> Drive Low, 1 -> + * High-Z) mode. + */ +typedef enum gpio_mode +{ + GpioModeIn = 0, /*!< input. */ + GpioModeOutPushPull = 1, /*!< push-pull output. */ + GpioModeoutOpenDrain0 = 2, /*!< open_drain0 (0->High-Z, 1->Drive High) mode. */ + GpioModeoutOpenDrain1 = 3, /*!< open_drain1 (0->Drive Low, 1->High-Z) mode. */ +} gpio_mode_t; + +/** + * This type is used in almost all the operations, and it is returned when + * there is a problem with functions given parameters or operation for example + * pin number not being in the range of accepting pins. + */ +typedef enum gpio_result +{ + GpioOk = 0, /*!< The operation was ok. */ + GpioError = 1, /*!< There is a problem. */ +} gpio_result_t; + +// /** +// * Gpio pin values: low or high +// */ +// typedef enum gpio_value +// { +// GpioLow = 0, +// GpioHigh = 1, +// } gpio_value_t; + +/** + * + */ +typedef enum gpio_intr_type +{ + GpioIntrEdgeRising, /*!< Trigger on rising edge. */ + GpioIntrEdgeFalling, /*!< Trigger on falling edge. */ + GpioIntrLevelLow, /*!< Trigger when input is low. */ + GpioIntrLevelHigh, /*!< rigger when input is high. */ + GpioIntrEdgeRisingFalling, /*!< Trigger on rising and falling edges. */ + GpioIntrEdgeRisingLevelLow, /*!< Trigger on rising edge or when the + input is low. */ + GpioIntrEdgeFallingLevelHigh,/*!< Trigger on falling edge or when the + input is high. */ +} gpio_intr_type_t; + + /****************************************************************************/ /** **/ /** TYPEDEFS AND STRUCTURES **/ /** **/ /****************************************************************************/ + /****************************************************************************/ /** **/ /** EXPORTED VARIABLES **/ /** **/ /****************************************************************************/ + /****************************************************************************/ /** **/ /** EXPORTED FUNCTIONS **/ /** **/ /****************************************************************************/ +/** + * @brief setting the a pins mode by writing in GPIO_MODE0 and GPIO_MODE1. + * @param gpio_pin_number_t specify the pin. + * @param gpio_mode_t specify pin mode: 0 as input, 1 push-pull as output, + * 2 as open_drain0, and 3 as open_drain1. + * @retval GpioOk if there is no problem with the given parameters or + * operation. + * @retval GpioError if there is an error with the given parameters or + * operation. + */ +gpio_result_t gpio_set_mode (gpio_pin_number_t pin, gpio_mode_t mode); + +/** + * @brief enable sampling as input by writing one in GPIO_EN. If disables + * (0) the corresponding GPIO will not sample the inputs (saves power) and + * will not generate any interrupts. + */ +gpio_result_t gpio_en_input (gpio_pin_number_t pin); + +/** + * @brief disable sampling as input by writing zero in GPIO_EN. + */ +gpio_result_t gpio_dis_input (gpio_pin_number_t pin); + +/** + * @brief reset completely all the configurations set for the pin + * @param gpio_pin_number_t specify pin number + */ +gpio_result_t gpio_pin_reset (gpio_pin_number_t pin); + +/** + * @brief reset completely all the configurations for all the pins + */ +gpio_result_t gpio_reset_all (void); + + +/** + * @brief reading from a gpio pin, which is done by reading from GPIO_IN reg + * @param gpio_pin_number_t specify pin number + * @return gpio value as GpioLow (false) or GpioHigh (true) + */ +gpio_result_t gpio_pin_read (gpio_pin_number_t pin); + +// /** +// * @brief set a pin as high. Using masking through GPIO_SET, and then writing +// * to GPIO_OUT +// * @param gpio_pin_number_t specify pin number +// */ +// gpio_result_t gpio_pin_set (gpio_pin_number_t pin); + +// /** +// * @brief clear a pin as low. Using masking through GPIO_CLEAR, and then +// * writing to GPIO_OUT +// * @param gpio_pin_number_t specify pin number +// */ +// gpio_result_t gpio_pin_clear (gpio_pin_number_t pin); + +/** + * @brief toggle a pin. Using masking through GPIO_TOGGLE, and then + * writing to GPIO_OUT + * @param gpio_pin_number_t specify pin number + */ +gpio_result_t gpio_pin_toggle (gpio_pin_number_t pin); + +/** + * @brief write to a pin. using gpio_set and gpio_clear functions. + * @param gpio_pin_number_t specify pin number + */ +gpio_result_t gpio_pin_write (gpio_pin_number_t pin, gpio_value val); + +/** + * @brief enable rising edge interrupt for the given pin. + * @param gpio_pin_number_t specify pin number + */ +gpio_result_t gpio_intr_en_rise (gpio_pin_number_t pin); + +/** + * @brief disable rising edge interrupt for the given pin. + * @param gpio_pin_number_t specify pin number + */ +gpio_result_t gpio_intr_dis_rise (gpio_pin_number_t pin); + +/** + * @brief enable falling edge interrupt for the given pin. + * @param gpio_pin_number_t specify pin number + */ +gpio_result_t gpio_intr_en_fall (gpio_pin_number_t pin); + +/** + * @brief disable falling edge interrupt for the given pin. + * @param gpio_pin_number_t specify pin number + */ +gpio_result_t gpio_intr_dis_fall (gpio_pin_number_t pin); + +/** + * @brief enable logic-high level-sensitive interrupt for the given pin. + * @param gpio_pin_number_t specify pin number + */ +gpio_result_t gpio_intr_en_lvl_high (gpio_pin_number_t pin); + +/** + * @brief disable logic-high level-sensitive interrupt for the given pin. + * @param gpio_pin_number_t specify pin number + */ +gpio_result_t gpio_intr_dis_lvl_high (gpio_pin_number_t pin); + +/** + * @brief enable logic-low level-sensitive interrupt for the given pin. + * @param gpio_pin_number_t specify pin number + */ +gpio_result_t gpio_intr_en_lvl_low (gpio_pin_number_t pin); + +/** + * @brief disable logic-low level-sensitive interrupt for the given pin. + * @param gpio_pin_number_t specify pin number + */ +gpio_result_t gpio_intr_dis_lvl_low (gpio_pin_number_t pin); + +/** + * @brief enable the interrupt for the given pin. Type of interrupt + * specified by user. + * @param gpio_pin_number_t specify pin number + * @param gpio_intr_type_t specify the type of the interrupt + */ +gpio_result_t gpio_intr_en (gpio_pin_number_t pin, gpio_intr_type_t type); + +// /** +// * @brief disable the given type of interrupt on the given pin. +// * @param gpio_pin_number_t specify pin number +// */ +// gpio_result_t gpio_intr_dis (gpio_pin_number_t pin, gpio_intr_type_t type); + +/** + * @brief disable all the types of interrupt on the given pin. + * @param gpio_pin_number_t specify pin number + */ +gpio_result_t gpio_intr_dis_all (gpio_pin_number_t pin); + +/** + * @brief Each bit indicates if there is a pending rising-edge interrupt + * on the corresponding GPIO. + * @param gpio_pin_number_t specify pin number + */ +gpio_result_t gpio_intr_check_stat_rise (gpio_pin_number_t pin, bool *is_pending); + +/** + * @brief Each bit indicates if there is a pending falling-edge interrupt + * on the corresponding GPIO. + * @param gpio_pin_number_t specify pin number + */ +gpio_result_t gpio_intr_check_stat_fall (gpio_pin_number_t pin, bool *is_pending); + +/** + * @brief Each bit indicates if there is a pending low level-sensitive + * interrupt on the corresponding GPIO. + * @param gpio_pin_number_t specify pin number + */ +gpio_result_t gpio_intr_check_stat_lvl_low (gpio_pin_number_t pin, bool *is_pending); + +/** + * @brief Each bit indicates if there is a pending high level-sensitive + * interrupt on the corresponding GPIO. + * @param gpio_pin_number_t specify pin number + */ +gpio_result_t gpio_intr_check_stat_lvl_high (gpio_pin_number_t pin, bool *is_pending); + +/** + * @brief Each bit indicates if there is a pending interrupt on the + * corresponding GPIO in any form (rise, fall, low level, and high level) + * @param gpio_pin_number_t specify pin number + */ +gpio_result_t gpio_intr_check_stat (gpio_pin_number_t pin, bool *is_pending); + +/** + * @brief Clearing interrupt rise status. Writing a 1 to a specific bit + * clears the interrupt for the corresponding GPIO. + * @param gpio_pin_number_t specify pin number + */ +gpio_result_t gpio_intr_clear_stat_rise (gpio_pin_number_t pin); + +/** + * @brief Clearing interrupt fall status. Writing a 1 to a specific bit + * clears the interrupt for the corresponding GPIO. + * @param gpio_pin_number_t specify pin number + */ +gpio_result_t gpio_intr_clear_stat_fall (gpio_pin_number_t pin); + +/** + * @brief Clearing interrupt low level-sensitive status. Writing a 1 to a + * specific bit clears the interrupt for the corresponding GPIO. + * @param gpio_pin_number_t specify pin number + */ +gpio_result_t gpio_intr_clear_stat_lvl_low (gpio_pin_number_t pin); + +/** + * @brief Clearing interrupt high level-sensitive status. Writing a 1 to a + * specific bit clears the interrupt for the corresponding GPIO. + * @param gpio_pin_number_t specify pin number + */ +gpio_result_t gpio_intr_clear_stat_lvl_high (gpio_pin_number_t pin); + +/** + * @brief Clearing interrupt status regardless of its type. Writing a 1 to + * a specific bit clears the interrupt for the corresponding GPIO. + * @param gpio_pin_number_t specify pin number + */ +gpio_result_t gpio_intr_clear_stat (gpio_pin_number_t pin); + +/** + * @brief Controls the interrupt mode of the gpios. + * @gpio_intr_mode If true, keep the interrupt line asserted until all + * interrupts for all GPIOs are cleared. If false, generate one cycle wide + * pulses for every new interrupt. + */ +gpio_result_t gpio_intr_mode (bool gpio_intr_mode); + + + + + /****************************************************************************/ /** **/ /** INLINE FUNCTIONS **/ /** **/ /****************************************************************************/ + + /****************************************************************************/ /** **/ /** EOF **/ /** **/ /****************************************************************************/ + #ifdef __cplusplus } #endif @@ -88,7 +371,6 @@ extern "C" { - /** * A toggle state: enabled, or disabled. * From e75d77b7bac1952f6a89c6f2700838d0f79abab5 Mon Sep 17 00:00:00 2001 From: Taji Hossein Date: Tue, 4 Apr 2023 12:15:54 +0200 Subject: [PATCH 03/22] removing pre version from code --- sw/device/lib/drivers/gpio/gpio.c | 216 +----------------------------- 1 file changed, 2 insertions(+), 214 deletions(-) diff --git a/sw/device/lib/drivers/gpio/gpio.c b/sw/device/lib/drivers/gpio/gpio.c index 73a170ab5..df6b9d83d 100644 --- a/sw/device/lib/drivers/gpio/gpio.c +++ b/sw/device/lib/drivers/gpio/gpio.c @@ -33,7 +33,7 @@ #include "gpio.h" #include "gpio_regs.h" // Generated. #include "gpio_structs.h" -#include "mmio.h" +// #include "mmio.h" /****************************************************************************/ /** **/ @@ -642,216 +642,4 @@ gpio_result_t gpio_intr_mode (bool gpio_intr_mode) /** **/ /* EOF */ /** **/ -/****************************************************************************/ - -// Copyright lowRISC contributors. -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 - -// Modified version for core-v-mini-mcu -// original at: https://github.com/lowRISC/opentitan/blob/master/sw/ - - - -/** - * Gives the mask that corresponds to the given bit index. - * - * @param index Bit index in a 32-bit register. - */ -static uint32_t index_to_mask(uint32_t index) { return 1u << index; } - -gpio_result_t gpio_init(gpio_params_t params, gpio_t *gpio) { - if (gpio == NULL) { - return kGpioBadArg; - } - - gpio->params = params; - - return kGpioOk; -} - -gpio_result_t gpio_reset(const gpio_t *gpio) { - if (gpio == NULL) { - return kGpioBadArg; - } - - mmio_region_write32(gpio->params.base_addr, - GPIO_CFG_REG_OFFSET, 0); - mmio_region_write32(gpio->params.base_addr, - GPIO_GPIO_MODE_0_REG_OFFSET, 0); - mmio_region_write32(gpio->params.base_addr, - GPIO_GPIO_MODE_1_REG_OFFSET, 0); - mmio_region_write32(gpio->params.base_addr, - GPIO_GPIO_EN_REG_OFFSET, 0); - mmio_region_write32(gpio->params.base_addr, - GPIO_GPIO_CLEAR_REG_OFFSET, 0); - mmio_region_write32(gpio->params.base_addr, - GPIO_GPIO_SET_REG_OFFSET, 0); - // Also clear all pending interrupts - mmio_region_write32(gpio->params.base_addr, - GPIO_INTRPT_STATUS_REG_OFFSET, 0); - - return kGpioOk; -} - -gpio_result_t gpio_irq_is_pending(const gpio_t *gpio, - gpio_pin_t pin, - bool *is_pending) { - if (gpio == NULL || is_pending == NULL) { - return kGpioBadArg; - } - - *is_pending = mmio_region_get_bit32(gpio->params.base_addr, - GPIO_INTRPT_STATUS_REG_OFFSET, pin); - - return kGpioOk; -} - -gpio_result_t gpio_irq_is_pending_all(const gpio_t *gpio, - gpio_state_t *is_pending) { - if (gpio == NULL || is_pending == NULL) { - return kGpioBadArg; - } - - *is_pending = - mmio_region_read32(gpio->params.base_addr, GPIO_INTRPT_STATUS_REG_OFFSET); - - return kGpioOk; -} - -gpio_result_t gpio_irq_acknowledge(const gpio_t *gpio, - gpio_pin_t pin) { - if (gpio == NULL) { - return kGpioBadArg; - } - - mmio_region_write32(gpio->params.base_addr, GPIO_INTRPT_STATUS_REG_OFFSET, - pin); - - return kGpioOk; -} - -gpio_result_t gpio_irq_get_enabled(const gpio_t *gpio, - gpio_pin_t pin, - gpio_toggle_t *state) { - if (gpio == NULL || state == NULL) { - return kGpioBadArg; - } - - bool is_enabled = mmio_region_get_bit32(gpio->params.base_addr, - GPIO_INTRPT_LVL_HIGH_EN_REG_OFFSET, pin); - *state = is_enabled ? kGpioToggleEnabled : kGpioToggleDisabled; - - return kGpioOk; -} - -gpio_result_t gpio_irq_set_trigger(const gpio_t *gpio, - gpio_pin_t pin, - bool state, - gpio_irq_trigger_t trigger) { - if (gpio == NULL) { - return kGpioBadArg; - } - - // Disable all interrupt triggers for the given mask. - mmio_region_write32( - gpio->params.base_addr, GPIO_INTRPT_RISE_EN_REG_OFFSET, 0); - mmio_region_write32( - gpio->params.base_addr, GPIO_INTRPT_FALL_EN_REG_OFFSET, 0); - mmio_region_write32( - gpio->params.base_addr, GPIO_INTRPT_LVL_HIGH_EN_REG_OFFSET, 0); - mmio_region_write32( - gpio->params.base_addr, GPIO_INTRPT_LVL_LOW_EN_REG_OFFSET, 0); - - switch (trigger) { - case kGpioIrqTriggerEdgeRising: - mmio_region_write32(gpio->params.base_addr, GPIO_INTRPT_RISE_EN_REG_OFFSET, 1 << pin); - break; - case kGpioIrqTriggerEdgeFalling: - mmio_region_write32(gpio->params.base_addr, GPIO_INTRPT_FALL_EN_REG_OFFSET, 1 << pin); - break; - case kGpioIrqTriggerLevelLow: - mmio_region_write32(gpio->params.base_addr, GPIO_INTRPT_LVL_LOW_EN_REG_OFFSET, 1 << pin); - break; - case kGpioIrqTriggerLevelHigh: - mmio_region_write32(gpio->params.base_addr, GPIO_INTRPT_LVL_HIGH_EN_REG_OFFSET, 1 << pin); - break; - case kGpioIrqTriggerEdgeRisingFalling: - mmio_region_write32(gpio->params.base_addr, GPIO_INTRPT_RISE_EN_REG_OFFSET, 1 << pin); - mmio_region_write32(gpio->params.base_addr,GPIO_INTRPT_FALL_EN_REG_OFFSET, 1 << pin); - break; - case kGpioIrqTriggerEdgeRisingLevelLow: - mmio_region_write32(gpio->params.base_addr, GPIO_INTRPT_RISE_EN_REG_OFFSET, 1 << pin); - mmio_region_write32(gpio->params.base_addr, GPIO_INTRPT_LVL_LOW_EN_REG_OFFSET, 1 << pin); - break; - case kGpioIrqTriggerEdgeFallingLevelHigh: - mmio_region_write32(gpio->params.base_addr, GPIO_INTRPT_RISE_EN_REG_OFFSET, 1 << pin); - mmio_region_write32(gpio->params.base_addr, GPIO_INTRPT_FALL_EN_REG_OFFSET, 1 << pin); - mmio_region_write32(gpio->params.base_addr, GPIO_INTRPT_LVL_LOW_EN_REG_OFFSET, 1 << pin); - break; - default: - return kGpioError; - } - - return kGpioOk; -} - -gpio_result_t gpio_read(const gpio_t *gpio, gpio_pin_t pin, - bool *state) { - if (gpio == NULL || state == NULL) { - return kGpioBadArg; - } - - *state = mmio_region_get_bit32(gpio->params.base_addr, - GPIO_GPIO_IN_REG_OFFSET, pin); - - return kGpioOk; -} - -gpio_result_t gpio_write(const gpio_t *gpio, gpio_pin_t pin, - bool state) { - - if (gpio == NULL) { - return kGpioBadArg; - } - - uint32_t reg_value = mmio_region_read32(gpio->params.base_addr, GPIO_GPIO_OUT_REG_OFFSET); - reg_value = bitfield_bit32_write(reg_value, pin, state); - mmio_region_write32(gpio->params.base_addr, GPIO_GPIO_OUT_REG_OFFSET, reg_value); - - return kGpioOk; -} - - -gpio_result_t gpio_output_set_enabled(const gpio_t *gpio, - gpio_pin_t pin, - gpio_toggle_t state) { - if (gpio == NULL) { - return kGpioBadArg; - } - - if(pin<16) { - uint32_t reg_value = mmio_region_read32(gpio->params.base_addr, GPIO_GPIO_MODE_0_REG_OFFSET); - reg_value = bitfield_bit32_write(reg_value, 2*pin, state); - mmio_region_write32(gpio->params.base_addr, GPIO_GPIO_MODE_0_REG_OFFSET, reg_value); - } else { - uint32_t reg_value = mmio_region_read32(gpio->params.base_addr, GPIO_GPIO_MODE_1_REG_OFFSET); - reg_value = bitfield_bit32_write(reg_value, 2*(pin-16), state); - mmio_region_write32(gpio->params.base_addr, GPIO_GPIO_MODE_1_REG_OFFSET, reg_value); - } - - return kGpioOk; -} - -gpio_result_t gpio_input_enabled(const gpio_t *gpio, - gpio_pin_t pin, gpio_toggle_t state) { - if (gpio == NULL) { - return kGpioBadArg; - } - - uint32_t reg_value = mmio_region_read32(gpio->params.base_addr, GPIO_GPIO_EN_REG_OFFSET); - reg_value = bitfield_bit32_write(reg_value, pin, state); - mmio_region_write32(gpio->params.base_addr, GPIO_GPIO_EN_REG_OFFSET, reg_value); - - return kGpioOk; -} \ No newline at end of file +/****************************************************************************/ \ No newline at end of file From 1c336d5eb81badd2732f408ebf4a91ddc4874042 Mon Sep 17 00:00:00 2001 From: Taji Hossein Date: Wed, 5 Apr 2023 15:27:33 +0200 Subject: [PATCH 04/22] removing some bugs of function definition --- sw/applications/example_gpio_cnt/main.c | 46 ++-- sw/device/lib/drivers/gpio/gpio.c | 27 +-- sw/device/lib/drivers/gpio/gpio.h | 284 +----------------------- 3 files changed, 46 insertions(+), 311 deletions(-) diff --git a/sw/applications/example_gpio_cnt/main.c b/sw/applications/example_gpio_cnt/main.c index 7ad10b5f4..fa7974c6b 100644 --- a/sw/applications/example_gpio_cnt/main.c +++ b/sw/applications/example_gpio_cnt/main.c @@ -71,15 +71,16 @@ int main(int argc, char *argv[]) pad_control_set_mux(&pad_control, (ptrdiff_t)(PAD_CONTROL_PAD_MUX_I2C_SDA_REG_OFFSET), 1); #endif - gpio_params_t gpio_params; - gpio_t gpio; - gpio_result_t gpio_res; - gpio_params.base_addr = mmio_region_from_addr((uintptr_t)GPIO_START_ADDRESS); - gpio_res = gpio_init(gpio_params, &gpio); - if (gpio_res != kGpioOk) { - printf("Failed\n;"); - return -1; - } + // gpio_params_t gpio_params; + // gpio_t gpio; + // gpio_result_t gpio_res; + // gpio_params.base_addr = mmio_region_from_addr((uintptr_t)GPIO_START_ADDRESS); + // gpio_res = gpio_init(gpio_params, &gpio); + // if (gpio_res != kGpioOk) { + // printf("Failed\n;"); + // return -1; + // } + plic_res = dif_plic_irq_set_priority(&rv_plic, GPIO_INTR, 1); if (plic_res != kDifPlicOk) { @@ -101,29 +102,40 @@ int main(int argc, char *argv[]) CSR_SET_BITS(CSR_REG_MIE, mask); external_intr_flag = 0; - gpio_res = gpio_output_set_enabled(&gpio, GPIO_TB_OUT, true); - if (gpio_res != kGpioOk) { + // gpio_res = gpio_output_set_enabled(&gpio, GPIO_TB_OUT, true); + // if (gpio_res != kGpioOk) { + // printf("Failed\n;"); + // return -1; + // } + gpio_result_t gpio_res; + gpio_res = gpio_set_mode(GPIO_TB_OUT, GpioModeOutPushPull); + if (gpio_res != GpioOk) { printf("Failed\n;"); return -1; } - gpio_write(&gpio, GPIO_TB_OUT, false); + // gpio_write(&gpio, GPIO_TB_OUT, false); + gpio_res = gpio_write(GPIO_TB_OUT, false); - gpio_res = gpio_input_enabled(&gpio, GPIO_TB_IN, true); - if (gpio_res != kGpioOk) { + // gpio_res = gpio_input_enabled(&gpio, GPIO_TB_IN, true); + gpio_res = gpio_set_mode(GPIO_TB_IN, GpioModeIn); + gpio_res = gpio_en_input(GPIO_TB_IN); + if (gpio_res != GpioOk) { printf("Failed\n;"); return -1; } - gpio_res = gpio_irq_set_trigger(&gpio, GPIO_TB_IN, true, kGpioIrqTriggerEdgeRising); - if (gpio_res != kGpioOk) { + // gpio_res = gpio_irq_set_trigger(&gpio, GPIO_TB_IN, true, kGpioIrqTriggerEdgeRising); + gpio_res = gpio_intr_en (GPIO_TB_IN, GpioIntrEdgeRisingFalling); + if (gpio_res != GpioOk) { printf("Failed\n;"); return -1; } printf("Write 1 to GPIO 30 and wait for interrupt...\n"); while(external_intr_flag==0) { - gpio_write(&gpio, GPIO_TB_OUT, true); + //gpio_write(&gpio, GPIO_TB_OUT, true); + gpio_res = gpio_write(GPIO_TB_OUT, true); wait_for_interrupt(); } printf("Success\n"); diff --git a/sw/device/lib/drivers/gpio/gpio.c b/sw/device/lib/drivers/gpio/gpio.c index df6b9d83d..0b53ca09a 100644 --- a/sw/device/lib/drivers/gpio/gpio.c +++ b/sw/device/lib/drivers/gpio/gpio.c @@ -103,7 +103,7 @@ gpio_result_t gpio_set_mode (gpio_pin_number_t pin, gpio_mode_t mode) } else if (pin >= 16 && pin <32) { - reg = setBit(&(gpio_peri->GPIO_MODE1), mode, 0b11, 2*(pin-16)); + setBitfield(&(gpio_peri->GPIO_MODE1), mode, 0b11, 2*(pin-16)); return GpioOk; } else @@ -138,7 +138,7 @@ gpio_result_t gpio_dis_input (gpio_pin_number_t pin) } } -gpio_result_t gpio_pin_reset (gpio_pin_number_t pin) +gpio_result_t gpio_reset (gpio_pin_number_t pin) { if (pin >= 0 && pin < 32) { @@ -173,7 +173,7 @@ gpio_result_t gpio_reset_all (void) gpio_peri->INTRPT_STATUS0 = 0xFFFFFFFF; } -gpio_result_t gpio_pin_read (gpio_pin_number_t pin, bool *val) +gpio_result_t gpio_read (gpio_pin_number_t pin, bool *val) { if (pin >= 0 && pin < 32) { @@ -218,7 +218,7 @@ gpio_result_t gpio_pin_read (gpio_pin_number_t pin, bool *val) // } //todo: check to see its toggling or just writing one -gpio_result_t gpio_pin_toggle (gpio_pin_number_t pin) +gpio_result_t gpio_toggle (gpio_pin_number_t pin) { if (pin >= 0 && pin < 32) { @@ -232,7 +232,7 @@ gpio_result_t gpio_pin_toggle (gpio_pin_number_t pin) } } -gpio_result_t gpio_pin_write (gpio_pin_number_t pin, gpio_value val) +gpio_result_t gpio_write (gpio_pin_number_t pin, bool val) { if (pin >= 0 && pin < 32) { @@ -616,20 +616,13 @@ gpio_result_t gpio_intr_clear_stat (gpio_pin_number_t pin) } } -gpio_result_t gpio_intr_mode (bool gpio_intr_mode) +gpio_result_t gpio_intr_set_mode (bool gpio_intr_mode) { - if (pin >= 0 && pin < 32) - { - if (gpio_intr_mode) - setBitfield(&(gpio_peri->CFG), 1, 1, 0); - else - setBitfield(&(gpio_peri->CFG), 0, 1, 0); - return GpioOk; - } + if (gpio_intr_mode) + setBitfield(&(gpio_peri->CFG), 1, 1, 0); else - { - return GpioError; - } + setBitfield(&(gpio_peri->CFG), 0, 1, 0); + return GpioOk; } /****************************************************************************/ /** **/ diff --git a/sw/device/lib/drivers/gpio/gpio.h b/sw/device/lib/drivers/gpio/gpio.h index 6f3361637..f4086e162 100644 --- a/sw/device/lib/drivers/gpio/gpio.h +++ b/sw/device/lib/drivers/gpio/gpio.h @@ -154,7 +154,7 @@ gpio_result_t gpio_dis_input (gpio_pin_number_t pin); * @brief reset completely all the configurations set for the pin * @param gpio_pin_number_t specify pin number */ -gpio_result_t gpio_pin_reset (gpio_pin_number_t pin); +gpio_result_t gpio_reset (gpio_pin_number_t pin); /** * @brief reset completely all the configurations for all the pins @@ -167,7 +167,7 @@ gpio_result_t gpio_reset_all (void); * @param gpio_pin_number_t specify pin number * @return gpio value as GpioLow (false) or GpioHigh (true) */ -gpio_result_t gpio_pin_read (gpio_pin_number_t pin); +gpio_result_t gpio_read (gpio_pin_number_t pin, bool *val); // /** // * @brief set a pin as high. Using masking through GPIO_SET, and then writing @@ -188,13 +188,13 @@ gpio_result_t gpio_pin_read (gpio_pin_number_t pin); * writing to GPIO_OUT * @param gpio_pin_number_t specify pin number */ -gpio_result_t gpio_pin_toggle (gpio_pin_number_t pin); +gpio_result_t gpio_toggle (gpio_pin_number_t pin); /** * @brief write to a pin. using gpio_set and gpio_clear functions. * @param gpio_pin_number_t specify pin number */ -gpio_result_t gpio_pin_write (gpio_pin_number_t pin, gpio_value val); +gpio_result_t gpio_write (gpio_pin_number_t pin, bool val); /** * @brief enable rising edge interrupt for the given pin. @@ -340,7 +340,7 @@ gpio_result_t gpio_intr_clear_stat (gpio_pin_number_t pin); * interrupts for all GPIOs are cleared. If false, generate one cycle wide * pulses for every new interrupt. */ -gpio_result_t gpio_intr_mode (bool gpio_intr_mode); +gpio_result_t gpio_intr_set_mode (bool gpio_intr_mode); @@ -353,279 +353,9 @@ gpio_result_t gpio_intr_mode (bool gpio_intr_mode); /****************************************************************************/ - +#endif // _GPIO_H_ /****************************************************************************/ /** **/ /** EOF **/ /** **/ -/****************************************************************************/ - -#ifdef __cplusplus -} -#endif - -#endif // _GPIO_H_ - - - - - - -/** - * A toggle state: enabled, or disabled. - * - * This enum may be used instead of a `bool` when describing an enabled/disabled - * state. - * - * This enum may be used with `gpio_toggle_vec_t` to set individual bits - * within it; `gpio_toggle_t`'s variants are guaranteed to be compatible - * with `gpio_toggle_vec_t`. - */ -typedef enum gpio_toggle { - /* - * The "enabled" state. - */ - kGpioToggleEnabled = true, - /** - * The "disabled" state. - */ - kGpioToggleDisabled = false, -} gpio_toggle_t; - -/** - * Hardware instantiation parameters for GPIO. - * - * This struct describes information about the underlying hardware that is - * not determined until the hardware design is used as part of a top-level - * design. - */ -typedef struct gpio_params { - /** - * The base address for the GPIO hardware registers. - */ - mmio_region_t base_addr; -} gpio_params_t; - -/** - * A handle to GPIO. - * - * This type should be treated as opaque by users. - */ -typedef struct gpio { gpio_params_t params; } gpio_t; - -/** - * The result of a GPIO operation. - */ -typedef enum gpio_result { - /** - * Indicates that the operation succeeded. - */ - kGpioOk = 0, - /** - * Indicates some unspecified failure. - */ - kGpioError = 1, - /** - * Indicates that some parameter passed into a function failed a - * precondition. - * - * When this value is returned, no hardware operations occurred. - */ - kGpioBadArg = 2, -} gpio_result_t; - -/** - * A GPIO interrupt request trigger. - * - * Each GPIO pin has an associated interrupt that can be independently - * configured - * to be edge and/or level sensitive. This enum defines supported configurations - * for - * these interrupts. - */ -typedef enum gpio_irq_trigger { - /** - * Trigger on rising edge. - */ - kGpioIrqTriggerEdgeRising, - /** - * Trigger on falling edge. - */ - kGpioIrqTriggerEdgeFalling, - /** - * Trigger when input is low. - */ - kGpioIrqTriggerLevelLow, - /** - * Trigger when input is high. - */ - kGpioIrqTriggerLevelHigh, - /** - * Trigger on rising and falling edges. - */ - kGpioIrqTriggerEdgeRisingFalling, - /** - * Trigger on rising edge or when the input is low. - */ - kGpioIrqTriggerEdgeRisingLevelLow, - /** - * Trigger on falling edge or when the input is high. - */ - kGpioIrqTriggerEdgeFallingLevelHigh, -} gpio_irq_trigger_t; - -/** - * A GPIO pin index, ranging from 0 to 31. - * - * This type serves as the GPIO interrupt request type. - */ -typedef uint32_t gpio_pin_t; - -/** - * State for all 32 GPIO pins, given as bit fields. - * - * The Nth bit represents the state of the Nth pin. - * - * This type is also used as a vector of `gpio_toggle_t`s, to indicate - * toggle state across all 32 pins. A set bit corresponds to - * `kGpioToggleEnabled`. - * - * It is also used with `gpio_irq_disable_all()` and - * `gpio_irq_restore_all()`. - */ -typedef uint32_t gpio_state_t; - -/** - * A mask for selecting GPIO pins. - * - * If the Nth bit is enabled, then the Nth pin is selected by the mask. - */ -typedef uint32_t gpio_mask_t; - -/** - * Creates a new handle for GPIO. - * - * This function does not actuate the hardware. - * - * @param params Hardware instantiation parameters. - * @param[out] gpio Out param for the initialized handle. - * @return The result of the operation. - */ -gpio_result_t gpio_init(gpio_params_t params, gpio_t *gpio); - -/** - * Resets a GPIO device. - * - * Resets the given GPIO device by setting its configuration registers to - * reset values. Disables interrupts, output, and input filter. - * - * @param gpio A GPIO handle. - * @return The result of the operation. - */ -gpio_result_t gpio_reset(const gpio_t *gpio); - -/** - * Returns whether a particular pin's interrupt is currently pending. - * - * @param gpio A GPIO handle. - * @param pin A GPIO pin. - * @param[out] is_pending Out-param for whether the interrupt is pending. - * @return The result of the operation. - */ -gpio_result_t gpio_irq_is_pending(const gpio_t *gpio, - gpio_pin_t pin, bool *is_pending); - -/** - * Returns a GPIO state representing which pins have interrupts enabled. - * - * @param gpio A GPIO handle. - * @param[out] is_pending Out-param for which interrupts are pending. - * @return The result of the operation. - */ -gpio_result_t gpio_irq_is_pending_all(const gpio_t *gpio, - gpio_state_t *is_pending); - -/** - * Acknowledges a particular pin's interrupt, indicating to the hardware that it - * has - * been successfully serviced. - * - * @param gpio A GPIO handle. - * @param pin A GPIO pin. - * @return The result of the operation. - */ -gpio_result_t gpio_irq_acknowledge(const gpio_t *gpio, - gpio_pin_t pin); - -/** - * Configures interrupt triggers for a set of pins. - * - * This function configures interrupt triggers, i.e. rising-edge, falling-edge, - * level-high, and level-low, for the pins given by the mask. Note that - * interrupt of the pin must also be enabled to generate interrupts. - * - * @param gpio A GPIO handle. - * @param mask Mask that identifies the pins whose interrupt triggers will be - * configured. - * @param trigger New configuration of interrupt triggers. - * @return The result of the operation. - */ -gpio_result_t gpio_irq_set_trigger(const gpio_t *gpio, - gpio_pin_t pin, - bool state, - gpio_irq_trigger_t trigger); - -/** - * Reads from a pin. - * - * The value returned by this function is independent of the output enable - * setting and includes the effects of the input noise filter and the load on - * the pin. - * - * @param gpio A GPIO handle. - * @param pin A GPIO pin. - * @param[out] state Pin value. - * @return The result of the operation. - */ -gpio_result_t gpio_read(const gpio_t *gpio, gpio_pin_t pin, - bool *state); - -/** - * Writes to a pin. - * - * The actual value on the pin depends on the output enable setting. - * - * @param gpio A GPIO handle. - * @param pin A GPIO pin. - * @param state Value to write. - * @return The result of the operation. - */ -gpio_result_t gpio_write(const gpio_t *gpio, gpio_pin_t pin, - bool state); -/** - * Sets output modes of all pins. - * - * @param gpio A GPIO handle. - * @param pin A GPIO pin. - * @param state Output modes of the pins. - * @return The result of the operation. - */ -gpio_result_t gpio_input_set_enabled(const gpio_t *gpio, - gpio_pin_t pin, - gpio_state_t state); -/** - * Enable sampling on GPIO - * * - * @param gpio A GPIO handle. - * @param pin A GPIO pin. - * @param state Value to write. - */ -gpio_result_t gpio_input_enabled(const gpio_t *gpio, - gpio_pin_t pin, gpio_toggle_t state); - - -#ifdef __cplusplus -} // extern "C" -#endif // __cplusplus - -#endif // GPIO_H_ +/****************************************************************************/ \ No newline at end of file From 873a93f3b936e37bda30817b167a6bd657014867 Mon Sep 17 00:00:00 2001 From: Taji Hossein Date: Wed, 5 Apr 2023 19:01:25 +0200 Subject: [PATCH 05/22] solving the bug on gpio_reset, and updating example_gpio_cnt --- run.sh | 28 +++++++++++++++++++ sw/applications/example_gpio_cnt/main.c | 37 ++++++------------------- sw/device/lib/drivers/gpio/gpio.c | 9 ++++-- 3 files changed, 42 insertions(+), 32 deletions(-) create mode 100755 run.sh diff --git a/run.sh b/run.sh new file mode 100755 index 000000000..cbb486275 --- /dev/null +++ b/run.sh @@ -0,0 +1,28 @@ +#! usr/bin/bash# This script is to be run in the x-heep base directory (aka BASE) + # It takes only one argument: the application name. + # It takes for granted that myApplication.c is located in + # BASE/sw/applications/myApplication/# Run this script from the BASE with + # $ sudo bash pynq-run # The pynq-z2 board must be + #   - Powered + #   - Loaded with the appropriate bitstream (use vivado) + #   - Connected to the EPFL programmer + #   - With sw1=0(outside) and sw0=1(inside) +#echo Will build for $1 +echo Will run application $1 + +make app-clean + # Compile and build the binaries to be loaded in the flash. + # To use different LINKER options, just modify this script. + # (remember to also change the make flash-load command below) +make app PROJECT=$1 LINKER=flash_load TARGET=pynq-z2 + + + + # To use the iceprog + +( cd sw/vendor/yosyshq_icestorm/iceprog && make clean && make all) + +# Make and load the flash programmable binary into the iceprog +make flash-prog && + # Open picocom to communicate with the board through UART +picocom -b 115200 -r -l --imap lfcrlf /dev/ttyUSB2 \ No newline at end of file diff --git a/sw/applications/example_gpio_cnt/main.c b/sw/applications/example_gpio_cnt/main.c index fa7974c6b..551f1ea66 100644 --- a/sw/applications/example_gpio_cnt/main.c +++ b/sw/applications/example_gpio_cnt/main.c @@ -71,17 +71,6 @@ int main(int argc, char *argv[]) pad_control_set_mux(&pad_control, (ptrdiff_t)(PAD_CONTROL_PAD_MUX_I2C_SDA_REG_OFFSET), 1); #endif - // gpio_params_t gpio_params; - // gpio_t gpio; - // gpio_result_t gpio_res; - // gpio_params.base_addr = mmio_region_from_addr((uintptr_t)GPIO_START_ADDRESS); - // gpio_res = gpio_init(gpio_params, &gpio); - // if (gpio_res != kGpioOk) { - // printf("Failed\n;"); - // return -1; - // } - - plic_res = dif_plic_irq_set_priority(&rv_plic, GPIO_INTR, 1); if (plic_res != kDifPlicOk) { printf("Failed\n;"); @@ -102,40 +91,30 @@ int main(int argc, char *argv[]) CSR_SET_BITS(CSR_REG_MIE, mask); external_intr_flag = 0; - // gpio_res = gpio_output_set_enabled(&gpio, GPIO_TB_OUT, true); - // if (gpio_res != kGpioOk) { - // printf("Failed\n;"); - // return -1; - // } + //gpio_reset_all(); gpio_result_t gpio_res; + + gpio_reset(GPIO_TB_OUT); gpio_res = gpio_set_mode(GPIO_TB_OUT, GpioModeOutPushPull); if (gpio_res != GpioOk) { printf("Failed\n;"); return -1; } - // gpio_write(&gpio, GPIO_TB_OUT, false); gpio_res = gpio_write(GPIO_TB_OUT, false); - // gpio_res = gpio_input_enabled(&gpio, GPIO_TB_IN, true); + gpio_reset(GPIO_TB_IN); gpio_res = gpio_set_mode(GPIO_TB_IN, GpioModeIn); - gpio_res = gpio_en_input(GPIO_TB_IN); - if (gpio_res != GpioOk) { - printf("Failed\n;"); - return -1; - } - - - // gpio_res = gpio_irq_set_trigger(&gpio, GPIO_TB_IN, true, kGpioIrqTriggerEdgeRising); - gpio_res = gpio_intr_en (GPIO_TB_IN, GpioIntrEdgeRisingFalling); + gpio_res |= gpio_en_input(GPIO_TB_IN); + gpio_res |= gpio_intr_en (GPIO_TB_IN, GpioIntrEdgeRising); if (gpio_res != GpioOk) { printf("Failed\n;"); return -1; } printf("Write 1 to GPIO 30 and wait for interrupt...\n"); + external_intr_flag = 0; while(external_intr_flag==0) { - //gpio_write(&gpio, GPIO_TB_OUT, true); - gpio_res = gpio_write(GPIO_TB_OUT, true); + //gpio_res = gpio_write(GPIO_TB_OUT, true); wait_for_interrupt(); } printf("Success\n"); diff --git a/sw/device/lib/drivers/gpio/gpio.c b/sw/device/lib/drivers/gpio/gpio.c index 0b53ca09a..bb14a825e 100644 --- a/sw/device/lib/drivers/gpio/gpio.c +++ b/sw/device/lib/drivers/gpio/gpio.c @@ -60,7 +60,10 @@ */ static inline uint32_t getBitfield( uint32_t reg, uint32_t mask, uint8_t sel ) { - return (reg & ( mask << sel )); + uint32_t ret_val = 0; + ret_val = reg & ( mask << sel ); + ret_val = ret_val >> sel; + return ret_val; } /** @@ -142,7 +145,7 @@ gpio_result_t gpio_reset (gpio_pin_number_t pin) { if (pin >= 0 && pin < 32) { - gpio_intr_mode (0); + gpio_intr_set_mode (0); gpio_set_mode (pin, GpioModeIn); gpio_dis_input (pin); setBitfield(&(gpio_peri->GPIO_CLEAR0), 0, 0b1, pin); @@ -177,7 +180,7 @@ gpio_result_t gpio_read (gpio_pin_number_t pin, bool *val) { if (pin >= 0 && pin < 32) { - if ( getBitfield(gpio_peri->GPIO_IN0, 0b1, pin) == 1) + if ( getBitfield(gpio_peri->GPIO_IN0, 0b1, pin) == 0b1) *val = true; else *val = false; From 0d289a5df5abd296d40cf99b9e420cd2703a973b Mon Sep 17 00:00:00 2001 From: Taji Hossein Date: Thu, 6 Apr 2023 09:51:31 +0200 Subject: [PATCH 06/22] removing mmio header --- .gitignore | 2 ++ sw/device/lib/drivers/gpio/gpio.c | 29 +++++++++++++++-------------- sw/device/lib/drivers/gpio/gpio.h | 7 ++----- 3 files changed, 19 insertions(+), 19 deletions(-) diff --git a/.gitignore b/.gitignore index 085c4cf74..f60b5d810 100644 --- a/.gitignore +++ b/.gitignore @@ -46,3 +46,5 @@ sw/device/lib/drivers/**/*_structs.h # openroad flow/OpenROAD-flow-scripts + +run.sh diff --git a/sw/device/lib/drivers/gpio/gpio.c b/sw/device/lib/drivers/gpio/gpio.c index bb14a825e..32dc62fe3 100644 --- a/sw/device/lib/drivers/gpio/gpio.c +++ b/sw/device/lib/drivers/gpio/gpio.c @@ -33,7 +33,6 @@ #include "gpio.h" #include "gpio_regs.h" // Generated. #include "gpio_structs.h" -// #include "mmio.h" /****************************************************************************/ /** **/ @@ -52,19 +51,6 @@ /* PROTOTYPES OF LOCAL FUNCTIONS */ /** **/ /****************************************************************************/ -/** - * @brief get some bitfield of a 32b reg. - * @param reg the register that bitwise field selects from. - * @param mask the mask w/o offset. - * @param sel this the offset used for mask and value. - */ -static inline uint32_t getBitfield( uint32_t reg, uint32_t mask, uint8_t sel ) -{ - uint32_t ret_val = 0; - ret_val = reg & ( mask << sel ); - ret_val = ret_val >> sel; - return ret_val; -} /** * @brief do a bitwise operation on 32b register. @@ -79,6 +65,21 @@ static inline void setBitfield( uint32_t *reg, uint32_t val, *reg &= ~( mask << sel ); *reg |= (val & mask) << sel; } + +/** + * @brief get some bitfield of a 32b reg. + * @param reg the register that bitwise field selects from. + * @param mask the mask w/o offset. + * @param sel this the offset used for mask and value. + */ +static inline uint32_t getBitfield( uint32_t reg, uint32_t mask, uint8_t sel ) +{ + uint32_t ret_val = 0; + ret_val = reg & ( mask << sel ); + ret_val = ret_val >> sel; + return ret_val; +} + /****************************************************************************/ /** **/ /* EXPORTED VARIABLES */ diff --git a/sw/device/lib/drivers/gpio/gpio.h b/sw/device/lib/drivers/gpio/gpio.h index f4086e162..0838e567c 100644 --- a/sw/device/lib/drivers/gpio/gpio.h +++ b/sw/device/lib/drivers/gpio/gpio.h @@ -27,10 +27,6 @@ #ifndef GPIO_H_ #define GPIO_H_ -#ifdef __cplusplus -extern "C" { -#endif - /****************************************************************************/ /** **/ /** MODULES USED **/ @@ -39,8 +35,9 @@ extern "C" { #include #include +#include -#include "mmio.h" +// #include "mmio.h" /****************************************************************************/ /** **/ From 4c878039ad9cdb36de925bff19e90f7e8c6ba2d7 Mon Sep 17 00:00:00 2001 From: Taji Hossein Date: Thu, 6 Apr 2023 11:47:50 +0200 Subject: [PATCH 07/22] easily configuration of pins by gpio_config --- sw/applications/example_gpio_cnt/main.c | 22 +++++--- sw/device/lib/drivers/gpio/gpio.c | 38 +++++++++++-- sw/device/lib/drivers/gpio/gpio.h | 71 ++++++++++++++----------- 3 files changed, 90 insertions(+), 41 deletions(-) diff --git a/sw/applications/example_gpio_cnt/main.c b/sw/applications/example_gpio_cnt/main.c index 551f1ea66..701adb1e3 100644 --- a/sw/applications/example_gpio_cnt/main.c +++ b/sw/applications/example_gpio_cnt/main.c @@ -14,6 +14,7 @@ #include "pad_control.h" #include "pad_control_regs.h" // Generated. #include "x-heep.h" +#include "gpio_structs.h" //remove /* Notes: @@ -94,18 +95,25 @@ int main(int argc, char *argv[]) //gpio_reset_all(); gpio_result_t gpio_res; - gpio_reset(GPIO_TB_OUT); - gpio_res = gpio_set_mode(GPIO_TB_OUT, GpioModeOutPushPull); + gpio_cfg_t cfg_out = { + .pin = GPIO_TB_OUT, + .mode = GpioModeOutPushPull + }; + gpio_res = gpio_config(cfg_out); if (gpio_res != GpioOk) { printf("Failed\n;"); return -1; } gpio_res = gpio_write(GPIO_TB_OUT, false); - gpio_reset(GPIO_TB_IN); - gpio_res = gpio_set_mode(GPIO_TB_IN, GpioModeIn); - gpio_res |= gpio_en_input(GPIO_TB_IN); - gpio_res |= gpio_intr_en (GPIO_TB_IN, GpioIntrEdgeRising); + gpio_cfg_t cfg_in = { + .pin = GPIO_TB_IN, + .mode = GpioModeIn, + .en_input_sampling = true, + .en_intr = true, + .intr_type = GpioIntrEdgeRising + }; + gpio_res = gpio_config(cfg_in); if (gpio_res != GpioOk) { printf("Failed\n;"); return -1; @@ -114,7 +122,7 @@ int main(int argc, char *argv[]) printf("Write 1 to GPIO 30 and wait for interrupt...\n"); external_intr_flag = 0; while(external_intr_flag==0) { - //gpio_res = gpio_write(GPIO_TB_OUT, true); + gpio_res = gpio_write(GPIO_TB_OUT, true); wait_for_interrupt(); } printf("Success\n"); diff --git a/sw/device/lib/drivers/gpio/gpio.c b/sw/device/lib/drivers/gpio/gpio.c index 32dc62fe3..59c83085c 100644 --- a/sw/device/lib/drivers/gpio/gpio.c +++ b/sw/device/lib/drivers/gpio/gpio.c @@ -32,7 +32,7 @@ #include "gpio.h" #include "gpio_regs.h" // Generated. -#include "gpio_structs.h" +#include "gpio_structs.h" //todo: remove it /****************************************************************************/ /** **/ @@ -40,6 +40,12 @@ /** **/ /****************************************************************************/ +/** + * As the hw is configurable, we can have setups with different number of + * Gpio pins + */ +#define MAX_PIN 32 + /****************************************************************************/ /** **/ /* TYPEDEFS AND STRUCTURES */ @@ -98,6 +104,30 @@ static inline uint32_t getBitfield( uint32_t reg, uint32_t mask, uint8_t sel ) /** **/ /****************************************************************************/ +gpio_result_t gpio_config (gpio_cfg_t cfg){ + // /* check that passed arg is not empty*/ + // if (cfg == NULL) + // return GpioError; + /* check that pin is in acceptable range. */ + if (cfg.pin > (MAX_PIN-1) || cfg.pin < 0) + return GpioError; + /* reset pin coniguration first.*/ + gpio_reset (cfg.pin); + /* check mode. */ + if ((cfg.mode < GpioModeIn) || (cfg.mode > GpioModeoutOpenDrain1)) + return GpioError; + /* set mode. */ + gpio_set_mode (cfg.pin, cfg.mode); + /* if input sampling is enabled */ + if (cfg.en_input_sampling == true) + gpio_en_input_sampling (cfg.pin); + /* if interrupt is enabled. Also after enabling check for error */ + if (cfg.en_intr == true) + if (gpio_intr_en (cfg.pin, cfg.intr_type) == GpioError) + return GpioError; + return GpioOk; +} + gpio_result_t gpio_set_mode (gpio_pin_number_t pin, gpio_mode_t mode) { if (pin >= 0 && pin < 16) @@ -116,7 +146,7 @@ gpio_result_t gpio_set_mode (gpio_pin_number_t pin, gpio_mode_t mode) } } -gpio_result_t gpio_en_input (gpio_pin_number_t pin) +gpio_result_t gpio_en_input_sampling (gpio_pin_number_t pin) { if (pin >= 0 && pin < 32) { @@ -129,7 +159,7 @@ gpio_result_t gpio_en_input (gpio_pin_number_t pin) } } -gpio_result_t gpio_dis_input (gpio_pin_number_t pin) +gpio_result_t gpio_dis_input_sampling (gpio_pin_number_t pin) { if (pin >= 0 && pin < 32) { @@ -148,7 +178,7 @@ gpio_result_t gpio_reset (gpio_pin_number_t pin) { gpio_intr_set_mode (0); gpio_set_mode (pin, GpioModeIn); - gpio_dis_input (pin); + gpio_dis_input_sampling (pin); setBitfield(&(gpio_peri->GPIO_CLEAR0), 0, 0b1, pin); setBitfield(&(gpio_peri->GPIO_SET0), 0, 0b1, pin); gpio_intr_dis_all(pin); diff --git a/sw/device/lib/drivers/gpio/gpio.h b/sw/device/lib/drivers/gpio/gpio.h index 0838e567c..f4da061ae 100644 --- a/sw/device/lib/drivers/gpio/gpio.h +++ b/sw/device/lib/drivers/gpio/gpio.h @@ -37,8 +37,6 @@ #include #include -// #include "mmio.h" - /****************************************************************************/ /** **/ /** DEFINITIONS AND MACROS **/ @@ -62,8 +60,10 @@ typedef enum gpio_mode { GpioModeIn = 0, /*!< input. */ GpioModeOutPushPull = 1, /*!< push-pull output. */ - GpioModeoutOpenDrain0 = 2, /*!< open_drain0 (0->High-Z, 1->Drive High) mode. */ - GpioModeoutOpenDrain1 = 3, /*!< open_drain1 (0->Drive Low, 1->High-Z) mode. */ + GpioModeoutOpenDrain0 = 2, /*!< open_drain0 (0->High-Z, 1->Drive High) + mode. */ + GpioModeoutOpenDrain1 = 3, /*!< open_drain1 (0->Drive Low, 1->High-Z) + mode. */ } gpio_mode_t; /** @@ -77,17 +77,8 @@ typedef enum gpio_result GpioError = 1, /*!< There is a problem. */ } gpio_result_t; -// /** -// * Gpio pin values: low or high -// */ -// typedef enum gpio_value -// { -// GpioLow = 0, -// GpioHigh = 1, -// } gpio_value_t; - /** - * + * The different interrupt types can be set by user */ typedef enum gpio_intr_type { @@ -102,6 +93,21 @@ typedef enum gpio_intr_type input is high. */ } gpio_intr_type_t; +/** + * The structure should be used by user for configuring gpio. + * it includes pin number, mode, enable sampling, enable intr, and its mode. + */ +typedef struct gpio_cfg +{ + gpio_pin_number_t pin; /*!< pin number. */ + gpio_pin_number_t mode; /*!< pin mode. */ + bool en_input_sampling; /*!< enable sampling (being input is req). */ + bool en_intr; /*!< enable intr (being input is req). */ + gpio_intr_type_t intr_type; /*!< intr type (enabling intr is req). */ +} gpio_cfg_t; + + + /****************************************************************************/ /** **/ @@ -116,22 +122,36 @@ typedef enum gpio_intr_type /** **/ /****************************************************************************/ - /****************************************************************************/ /** **/ /** EXPORTED FUNCTIONS **/ /** **/ /****************************************************************************/ +/** + * @brief gpio configuration. It first reset the pin configuration. + * @param gpio_struct_t contatining pin, mode, en_input_sampling, en_intr, + * intr_type + * @return GpioOk: no problem, GpioError: there is an error. + */ +gpio_result_t gpio_config (gpio_cfg_t cfg); + +/** + * @brief reset completely all the configurations set for the pin + * @param gpio_pin_number_t specify pin number + */ +gpio_result_t gpio_reset (gpio_pin_number_t pin); + +/** + * @brief reset completely all the configurations for all the pins + */ +gpio_result_t gpio_reset_all (void); + /** * @brief setting the a pins mode by writing in GPIO_MODE0 and GPIO_MODE1. * @param gpio_pin_number_t specify the pin. * @param gpio_mode_t specify pin mode: 0 as input, 1 push-pull as output, * 2 as open_drain0, and 3 as open_drain1. - * @retval GpioOk if there is no problem with the given parameters or - * operation. - * @retval GpioError if there is an error with the given parameters or - * operation. */ gpio_result_t gpio_set_mode (gpio_pin_number_t pin, gpio_mode_t mode); @@ -140,23 +160,14 @@ gpio_result_t gpio_set_mode (gpio_pin_number_t pin, gpio_mode_t mode); * (0) the corresponding GPIO will not sample the inputs (saves power) and * will not generate any interrupts. */ -gpio_result_t gpio_en_input (gpio_pin_number_t pin); +gpio_result_t gpio_en_input_sampling (gpio_pin_number_t pin); /** * @brief disable sampling as input by writing zero in GPIO_EN. */ -gpio_result_t gpio_dis_input (gpio_pin_number_t pin); +gpio_result_t gpio_dis_input_sampling (gpio_pin_number_t pin); -/** - * @brief reset completely all the configurations set for the pin - * @param gpio_pin_number_t specify pin number - */ -gpio_result_t gpio_reset (gpio_pin_number_t pin); -/** - * @brief reset completely all the configurations for all the pins - */ -gpio_result_t gpio_reset_all (void); /** From 6436e16aeca14888b3b03f62f89d735000f74df1 Mon Sep 17 00:00:00 2001 From: Taji Hossein Date: Thu, 6 Apr 2023 12:01:17 +0200 Subject: [PATCH 08/22] adding MAX_PIN --- sw/device/lib/drivers/gpio/gpio.c | 102 ++++++++---------------------- 1 file changed, 27 insertions(+), 75 deletions(-) diff --git a/sw/device/lib/drivers/gpio/gpio.c b/sw/device/lib/drivers/gpio/gpio.c index 59c83085c..5c376fa24 100644 --- a/sw/device/lib/drivers/gpio/gpio.c +++ b/sw/device/lib/drivers/gpio/gpio.c @@ -135,7 +135,7 @@ gpio_result_t gpio_set_mode (gpio_pin_number_t pin, gpio_mode_t mode) setBitfield(&(gpio_peri->GPIO_MODE0), mode, 0b11, 2*pin); return GpioOk; } - else if (pin >= 16 && pin <32) + else if (pin >= 16 && pin GPIO_MODE1), mode, 0b11, 2*(pin-16)); return GpioOk; @@ -148,7 +148,7 @@ gpio_result_t gpio_set_mode (gpio_pin_number_t pin, gpio_mode_t mode) gpio_result_t gpio_en_input_sampling (gpio_pin_number_t pin) { - if (pin >= 0 && pin < 32) + if (pin >= 0 && pin < MAX_PIN) { setBitfield(&(gpio_peri->GPIO_EN0), 1, 0b1, pin); return GpioOk; @@ -161,7 +161,7 @@ gpio_result_t gpio_en_input_sampling (gpio_pin_number_t pin) gpio_result_t gpio_dis_input_sampling (gpio_pin_number_t pin) { - if (pin >= 0 && pin < 32) + if (pin >= 0 && pin < MAX_PIN) { setBitfield(&(gpio_peri->GPIO_EN0), 0, 0b1, pin); return GpioOk; @@ -174,7 +174,7 @@ gpio_result_t gpio_dis_input_sampling (gpio_pin_number_t pin) gpio_result_t gpio_reset (gpio_pin_number_t pin) { - if (pin >= 0 && pin < 32) + if (pin >= 0 && pin < MAX_PIN) { gpio_intr_set_mode (0); gpio_set_mode (pin, GpioModeIn); @@ -209,7 +209,7 @@ gpio_result_t gpio_reset_all (void) gpio_result_t gpio_read (gpio_pin_number_t pin, bool *val) { - if (pin >= 0 && pin < 32) + if (pin >= 0 && pin < MAX_PIN) { if ( getBitfield(gpio_peri->GPIO_IN0, 0b1, pin) == 0b1) *val = true; @@ -254,7 +254,7 @@ gpio_result_t gpio_read (gpio_pin_number_t pin, bool *val) //todo: check to see its toggling or just writing one gpio_result_t gpio_toggle (gpio_pin_number_t pin) { - if (pin >= 0 && pin < 32) + if (pin >= 0 && pin < MAX_PIN) { gpio_peri->GPIO_TOGGLE0 = 1 << pin; gpio_peri->GPIO_OUT0 = 1 << pin; @@ -268,7 +268,7 @@ gpio_result_t gpio_toggle (gpio_pin_number_t pin) gpio_result_t gpio_write (gpio_pin_number_t pin, bool val) { - if (pin >= 0 && pin < 32) + if (pin >= 0 && pin < MAX_PIN) { if (val == true) setBitfield(&(gpio_peri->GPIO_OUT0), 1, 1, pin); @@ -284,7 +284,7 @@ gpio_result_t gpio_write (gpio_pin_number_t pin, bool val) gpio_result_t gpio_intr_en_rise (gpio_pin_number_t pin) { - if (pin >= 0 && pin < 32) + if (pin >= 0 && pin < MAX_PIN) { setBitfield(&(gpio_peri->INTRPT_RISE_EN0), 1, 1, pin); return GpioOk; @@ -297,7 +297,7 @@ gpio_result_t gpio_intr_en_rise (gpio_pin_number_t pin) gpio_result_t gpio_intr_en_fall (gpio_pin_number_t pin) { - if (pin >= 0 && pin < 32) + if (pin >= 0 && pin < MAX_PIN) { setBitfield(&(gpio_peri->INTRPT_FALL_EN0), 1, 1, pin); return GpioOk; @@ -310,7 +310,7 @@ gpio_result_t gpio_intr_en_fall (gpio_pin_number_t pin) gpio_result_t gpio_intr_en_lvl_high (gpio_pin_number_t pin) { - if (pin >= 0 && pin < 32) + if (pin >= 0 && pin < MAX_PIN) { setBitfield(&(gpio_peri->INTRPT_LVL_HIGH_EN0), 1, 1, pin); return GpioOk; @@ -323,7 +323,7 @@ gpio_result_t gpio_intr_en_lvl_high (gpio_pin_number_t pin) gpio_result_t gpio_intr_en_lvl_low (gpio_pin_number_t pin) { - if (pin >= 0 && pin < 32) + if (pin >= 0 && pin < MAX_PIN) { setBitfield(&(gpio_peri->INTRPT_LVL_LOW_EN0), 1, 1, pin); return GpioOk; @@ -336,7 +336,7 @@ gpio_result_t gpio_intr_en_lvl_low (gpio_pin_number_t pin) gpio_result_t gpio_intr_dis_rise (gpio_pin_number_t pin) { - if (pin >= 0 && pin < 32) + if (pin >= 0 && pin < MAX_PIN) { setBitfield(&(gpio_peri->INTRPT_RISE_EN0), 0, 1, pin); return GpioOk; @@ -349,7 +349,7 @@ gpio_result_t gpio_intr_dis_rise (gpio_pin_number_t pin) gpio_result_t gpio_intr_dis_fall (gpio_pin_number_t pin) { - if (pin >= 0 && pin < 32) + if (pin >= 0 && pin < MAX_PIN) { setBitfield(&(gpio_peri->INTRPT_FALL_EN0), 0, 1, pin); return GpioOk; @@ -362,7 +362,7 @@ gpio_result_t gpio_intr_dis_fall (gpio_pin_number_t pin) gpio_result_t gpio_intr_dis_lvl_high (gpio_pin_number_t pin) { - if (pin >= 0 && pin < 32) + if (pin >= 0 && pin < MAX_PIN) { setBitfield(&(gpio_peri->INTRPT_LVL_HIGH_EN0), 0, 1, pin); return GpioOk; @@ -375,7 +375,7 @@ gpio_result_t gpio_intr_dis_lvl_high (gpio_pin_number_t pin) gpio_result_t gpio_intr_dis_lvl_low (gpio_pin_number_t pin) { - if (pin >= 0 && pin < 32) + if (pin >= 0 && pin < MAX_PIN) { setBitfield(&(gpio_peri->INTRPT_LVL_LOW_EN0), 0, 1, pin); return GpioOk; @@ -387,7 +387,7 @@ gpio_result_t gpio_intr_dis_lvl_low (gpio_pin_number_t pin) } gpio_result_t gpio_intr_dis_all (gpio_pin_number_t pin){ - if (pin >= 0 && pin < 32) + if (pin >= 0 && pin < MAX_PIN) { setBitfield(&(gpio_peri->INTRPT_RISE_EN0), 0, 1, pin); setBitfield(&(gpio_peri->INTRPT_FALL_EN0), 0, 1, pin); @@ -404,7 +404,7 @@ gpio_result_t gpio_intr_dis_all (gpio_pin_number_t pin){ gpio_result_t gpio_intr_en (gpio_pin_number_t pin, gpio_intr_type_t type) { - if (pin >= 0 && pin < 32) + if (pin >= 0 && pin < MAX_PIN) { gpio_intr_dis_all(pin); @@ -452,57 +452,9 @@ gpio_result_t gpio_intr_en (gpio_pin_number_t pin, gpio_intr_type_t type) } } -// gpio_result_t gpio_intr_dis (gpio_pin_number_t pin, gpio_intr_type_t type) -// { -// if (pin >= 0 && pin < 32) -// { -// switch(type) -// { -// case GpioIntrEdgeRising: -// gpio_intr_dis_rise(pin); -// break; - -// case GpioIntrEdgeFalling: -// gpio_intr_dis_fall(pin); -// break; - -// case GpioIntrLevelLow: -// gpio_intr_dis_lvl_low(pin); -// break; - -// case GpioIntrLevelHigh: -// gpio_intr_dis_lvl_high(pin); -// break; - -// case GpioIntrEdgeRisingFalling: -// gpio_intr_dis_rise(pin); -// gpio_intr_dis_fall(pin); -// break; - -// case GpioIntrEdgeRisingLevelLow: -// gpio_intr_dis_rise(pin); -// gpio_intr_dis_lvl_low(pin); -// break; - -// case GpioIntrEdgeFallingLevelHigh: -// gpio_intr_dis_fall(pin); -// gpio_intr_dis_lvl_high(pin); -// break; - -// default: -// return GpioError; -// } -// return GpioOk; -// } -// else -// { -// return GpioError; -// } -// } - gpio_result_t gpio_intr_check_stat_rise (gpio_pin_number_t pin, bool *is_pending) { - if (pin >= 0 && pin < 32) + if (pin >= 0 && pin < MAX_PIN) { if (getBitfield(gpio_peri->INTRPT_RISE_STATUS0, 1, pin) == 1) *is_pending = true; @@ -519,7 +471,7 @@ gpio_result_t gpio_intr_check_stat_rise (gpio_pin_number_t pin, bool *is_pending gpio_result_t gpio_intr_check_stat_fall (gpio_pin_number_t pin, bool *is_pending) { - if (pin >= 0 && pin < 32) + if (pin >= 0 && pin < MAX_PIN) { if (getBitfield(gpio_peri->INTRPT_FALL_STATUS0, 1, pin) == 1) *is_pending = true; @@ -536,7 +488,7 @@ gpio_result_t gpio_intr_check_stat_fall (gpio_pin_number_t pin, bool *is_pending gpio_result_t gpio_intr_check_stat_lvl_low (gpio_pin_number_t pin, bool *is_pending) { - if (pin >= 0 && pin < 32) + if (pin >= 0 && pin < MAX_PIN) { if (getBitfield(gpio_peri->INTRPT_LVL_LOW_STATUS0, 1, pin) == 1) *is_pending = true; @@ -553,7 +505,7 @@ gpio_result_t gpio_intr_check_stat_lvl_low (gpio_pin_number_t pin, bool *is_pend gpio_result_t gpio_intr_check_stat_lvl_high (gpio_pin_number_t pin, bool *is_pending) { - if (pin >= 0 && pin < 32) + if (pin >= 0 && pin < MAX_PIN) { if (getBitfield(gpio_peri->INTRPT_LVL_HIGH_STATUS0, 1, pin) == 1) *is_pending = true; @@ -570,7 +522,7 @@ gpio_result_t gpio_intr_check_stat_lvl_high (gpio_pin_number_t pin, bool *is_pen gpio_result_t gpio_intr_check_stat (gpio_pin_number_t pin, bool *is_pending) { - if (pin >= 0 && pin < 32) + if (pin >= 0 && pin < MAX_PIN) { if (getBitfield(gpio_peri->INTRPT_STATUS0, 1, pin) == 1) *is_pending = true; @@ -587,7 +539,7 @@ gpio_result_t gpio_intr_check_stat (gpio_pin_number_t pin, bool *is_pending) gpio_result_t gpio_intr_clear_stat_rise (gpio_pin_number_t pin) { - if (pin >= 0 && pin < 32) + if (pin >= 0 && pin < MAX_PIN) { setBitfield(&(gpio_peri->INTRPT_RISE_STATUS0), 1, 1, pin); return GpioOk; @@ -600,7 +552,7 @@ gpio_result_t gpio_intr_clear_stat_rise (gpio_pin_number_t pin) gpio_result_t gpio_intr_clear_stat_fall (gpio_pin_number_t pin) { - if (pin >= 0 && pin < 32) + if (pin >= 0 && pin < MAX_PIN) { setBitfield(&(gpio_peri->INTRPT_FALL_STATUS0), 1, 1, pin); return GpioOk; @@ -613,7 +565,7 @@ gpio_result_t gpio_intr_clear_stat_fall (gpio_pin_number_t pin) gpio_result_t gpio_intr_clear_stat_lvl_low (gpio_pin_number_t pin) { - if (pin >= 0 && pin < 32) + if (pin >= 0 && pin < MAX_PIN) { setBitfield(&(gpio_peri->INTRPT_LVL_LOW_STATUS0), 1, 1, pin); return GpioOk; @@ -626,7 +578,7 @@ gpio_result_t gpio_intr_clear_stat_lvl_low (gpio_pin_number_t pin) gpio_result_t gpio_intr_clear_stat_lvl_high (gpio_pin_number_t pin) { - if (pin >= 0 && pin < 32) + if (pin >= 0 && pin < MAX_PIN) { setBitfield(&(gpio_peri->INTRPT_LVL_HIGH_STATUS0), 1, 1, pin); return GpioOk; @@ -639,7 +591,7 @@ gpio_result_t gpio_intr_clear_stat_lvl_high (gpio_pin_number_t pin) gpio_result_t gpio_intr_clear_stat (gpio_pin_number_t pin) { - if (pin >= 0 && pin < 32) + if (pin >= 0 && pin < MAX_PIN) { setBitfield(&(gpio_peri->INTRPT_STATUS0), 1, 1, pin); return GpioOk; From 267f99c597e9757685604ffc63575bf78cf9d798 Mon Sep 17 00:00:00 2001 From: Taji Hossein Date: Thu, 6 Apr 2023 15:50:15 +0200 Subject: [PATCH 09/22] example_power_gating_corewas updated --- .../example_power_gating_core/main.c | 29 ++++++++++++------- 1 file changed, 19 insertions(+), 10 deletions(-) diff --git a/sw/applications/example_power_gating_core/main.c b/sw/applications/example_power_gating_core/main.c index de0fae976..4f07c4efa 100644 --- a/sw/applications/example_power_gating_core/main.c +++ b/sw/applications/example_power_gating_core/main.c @@ -22,13 +22,13 @@ static const uint64_t kTickFreqHz = 1000 * 1000; // 1 MHz static power_manager_t power_manager; static dif_plic_t rv_plic; -static gpio_t gpio; +// static gpio_t gpio; int main(int argc, char *argv[]) { // Setup fast interrupt controller - fast_intr_ctrl_t fast_intr_ctrl; - fast_intr_ctrl.base_addr = mmio_region_from_addr((uintptr_t)FAST_INTR_CTRL_START_ADDRESS); + // fast_intr_ctrl_t fast_intr_ctrl; + // fast_intr_ctrl.base_addr = mmio_region_from_addr((uintptr_t)FAST_INTR_CTRL_START_ADDRESS); // Setup power_manager mmio_region_t power_manager_reg = mmio_region_from_addr(POWER_MANAGER_START_ADDRESS); @@ -56,9 +56,9 @@ int main(int argc, char *argv[]) rv_timer_init(timer_2_3_reg, (rv_timer_config_t){.hart_count = 2, .comparator_count = 1}, &timer_2_3); // Setup gpio - gpio_params_t gpio_params; - gpio_params.base_addr = mmio_region_from_addr((uintptr_t)GPIO_START_ADDRESS); - gpio_init(gpio_params, &gpio); + // gpio_params_t gpio_params; + // gpio_params.base_addr = mmio_region_from_addr((uintptr_t)GPIO_START_ADDRESS); + // gpio_init(gpio_params, &gpio); // Init cpu_subsystem's counters if (power_gate_counters_init(&power_manager_cpu_counters, 30, 30, 30, 30, 30, 30, 0, 0) != kPowerManagerOk_e) @@ -127,10 +127,19 @@ int main(int argc, char *argv[]) // Power-gate and wake-up due to plic dif_plic_irq_set_priority(&rv_plic, GPIO_INTR_31, 1); dif_plic_irq_set_enabled(&rv_plic, GPIO_INTR_31, 0, kDifPlicToggleEnabled); - gpio_output_set_enabled(&gpio, 30, true); - gpio_irq_set_trigger(&gpio, 1 << 31, kGpioIrqTriggerLevelHigh); - gpio_irq_set_enabled(&gpio, 31, true); - gpio_write(&gpio, 30, true); + + // gpio_output_set_enabled(&gpio, 30, true); + gpio_cfg_t pin1_cfg = {.pin = 30, .mode = GpioModeOutPushPull}; + gpio_config (pin1_cfg); + + // gpio_irq_set_trigger(&gpio, 1 << 31, kGpioIrqTriggerLevelHigh); + // gpio_irq_set_enabled(&gpio, 31, true); + gpio_cfg_t pin2_cfg = {.pin = 31, .mode = GpioModeIn,.en_input_sampling = true, + .en_intr = true, .intr_type = GpioIntrLevelHigh}; + gpio_config (pin2_cfg); + + // gpio_write(&gpio, 30, true); + gpio_write(30, true); CSR_CLEAR_BITS(CSR_REG_MSTATUS, 0x8); if (power_gate_core(&power_manager, kPlic_pm_e, &power_manager_cpu_counters) != kPowerManagerOk_e) From b8260df6b0df53e825ca0dfc17d3296352cd9de0 Mon Sep 17 00:00:00 2001 From: Taji Hossein Date: Thu, 6 Apr 2023 16:37:15 +0200 Subject: [PATCH 10/22] updating gpio_pmw --- sw/applications/gpio_pmw/main.c | 29 ++++++++++++++++++++--------- 1 file changed, 20 insertions(+), 9 deletions(-) diff --git a/sw/applications/gpio_pmw/main.c b/sw/applications/gpio_pmw/main.c index 55fcf640d..d6e0c7736 100644 --- a/sw/applications/gpio_pmw/main.c +++ b/sw/applications/gpio_pmw/main.c @@ -12,26 +12,37 @@ int main(int argc, char *argv[]) { - gpio_params_t gpio_params; - gpio_t gpio; + // gpio_params_t gpio_params; + // gpio_t gpio; gpio_result_t gpio_res; - gpio_params.base_addr = mmio_region_from_addr((uintptr_t)GPIO_AO_START_ADDRESS); - gpio_res = gpio_init(gpio_params, &gpio); - gpio_res = gpio_output_set_enabled(&gpio, GPIO_PMW, true); + // gpio_params.base_addr = mmio_region_from_addr((uintptr_t)GPIO_AO_START_ADDRESS); + // gpio_res = gpio_init(gpio_params, &gpio); + // gpio_res = gpio_output_set_enabled(&gpio, GPIO_PMW, true); + gpio_cfg_t pin_cfg = { + .pin = GPIO_PMW, + .mode = GpioModeOutPushPull + }; + gpio_res = gpio_config (pin_cfg); + if (gpio_res != GpioOk) + printf("Gpio initialization failed!\n"); #ifdef TARGET_PYNQ_Z2 #pragma message ( "this application never ends" ) while(1) { - gpio_write(&gpio, GPIO_PMW, true); + // gpio_write(&gpio, GPIO_PMW, true); + gpio_write(GPIO_PMW, true); for(int i=0;i<10;i++) asm volatile("nop"); - gpio_write(&gpio, GPIO_PMW, false); + // gpio_write(&gpio, GPIO_PMW, false); + gpio_write(GPIO_PMW, false); for(int i=0;i<10;i++) asm volatile("nop"); } #else for(int i=0;i<100;i++) { - gpio_write(&gpio, GPIO_PMW, true); + // gpio_write(&gpio, GPIO_PMW, true); + pio_write(GPIO_PMW, true); for(int i=0;i<10;i++) asm volatile("nop"); - gpio_write(&gpio, GPIO_PMW, false); + // gpio_write(&gpio, GPIO_PMW, false); + gpio_write(GPIO_PMW, false); for(int i=0;i<10;i++) asm volatile("nop"); } #endif From da57c41ddf49175f59fa4b42ce2719a7653fc2ff Mon Sep 17 00:00:00 2001 From: Taji Hossein Date: Thu, 6 Apr 2023 16:51:15 +0200 Subject: [PATCH 11/22] updating blinky_freertos --- sw/applications/blinky_freertos/main.c | 58 ++++++++++++-------------- 1 file changed, 26 insertions(+), 32 deletions(-) diff --git a/sw/applications/blinky_freertos/main.c b/sw/applications/blinky_freertos/main.c index 77ee77f32..2cdca8a62 100644 --- a/sw/applications/blinky_freertos/main.c +++ b/sw/applications/blinky_freertos/main.c @@ -225,9 +225,6 @@ int8_t intr_flag = 0; /* Temporal counter to store blinking status */ int8_t intr_blink = 0; -/* GPIO struct */ -gpio_t gpio; - /****************************************************************************/ /** **/ /* EXPORTED FUNCTIONS */ @@ -251,25 +248,22 @@ void system_init(void) soc_ctrl.base_addr = mmio_region_from_addr((uintptr_t)SOC_CTRL_START_ADDRESS); uint32_t freq_hz = soc_ctrl_get_frequency(&soc_ctrl); - // Set GPIOs - gpio_params_t gpio_params; - gpio_result_t gpio_res; - gpio_params.base_addr = mmio_region_from_addr((uintptr_t)GPIO_START_ADDRESS); - gpio_res = gpio_init(gpio_params, &gpio); - if (gpio_res != kGpioOk) - { - printf("GPIO Failed\n;"); - } - gpio_res = gpio_output_set_enabled(&gpio, GPIO_LD5_R, true); - if (gpio_res != kGpioOk) printf("Failed\n;"); - gpio_write(&gpio, GPIO_LD5_R, false); - gpio_res = gpio_output_set_enabled(&gpio, GPIO_LD5_B, true); - if (gpio_res != kGpioOk) printf("Failed\n;"); - gpio_write(&gpio, GPIO_LD5_B, false); - gpio_res = gpio_output_set_enabled(&gpio, GPIO_LD5_G, true); + gpio_result_t gpio_res; + gpio_cfg_t pin_cfg = { + .pin= GPIO_LD5_R, + .mode= GpioModeOutPushPull + }; + gpio_res = gpio_config(pin_cfg); + pin_cfg.pin = GPIO_LD5_B; + gpio_res |= gpio_config(pin_cfg); + pin_cfg.pin = GPIO_LD5_G; + gpio_res |= gpio_config(pin_cfg); if (gpio_res != kGpioOk) printf("Failed\n;"); - gpio_write(&gpio, GPIO_LD5_G, false); + + gpio_write(GPIO_LD5_R, false); + gpio_write(GPIO_LD5_B, false); + gpio_write(GPIO_LD5_G, false); // Setup rv_timer_0_1 mmio_region_t timer_0_1_reg = mmio_region_from_addr(RV_TIMER_AO_START_ADDRESS); @@ -444,30 +438,30 @@ void vToggleLED( void ) { if (intr_blink == 0) { - gpio_write(&gpio, GPIO_LD5_R, true); - gpio_write(&gpio, GPIO_LD5_B, false); - gpio_write(&gpio, GPIO_LD5_G, false); + gpio_write(GPIO_LD5_R, true); + gpio_write(GPIO_LD5_B, false); + gpio_write(GPIO_LD5_G, false); intr_blink++; } else if (intr_blink == 1) { - gpio_write(&gpio, GPIO_LD5_R, false); - gpio_write(&gpio, GPIO_LD5_B, true); - gpio_write(&gpio, GPIO_LD5_G, false); + gpio_write(GPIO_LD5_R, false); + gpio_write(GPIO_LD5_B, true); + gpio_write(GPIO_LD5_G, false); intr_blink++; } else if (intr_blink == 2) { - gpio_write(&gpio, GPIO_LD5_R, false); - gpio_write(&gpio, GPIO_LD5_B, false); - gpio_write(&gpio, GPIO_LD5_G, true); + gpio_write(GPIO_LD5_R, false); + gpio_write(GPIO_LD5_B, false); + gpio_write(GPIO_LD5_G, true); intr_blink++; } else { - gpio_write(&gpio, GPIO_LD5_R, false); - gpio_write(&gpio, GPIO_LD5_B, false); - gpio_write(&gpio, GPIO_LD5_G, false); + gpio_write(GPIO_LD5_R, false); + gpio_write(GPIO_LD5_B, false); + gpio_write(GPIO_LD5_G, false); intr_blink = 0; } From d4878dc732d87a3724b9765e5e272ab5ca9735b2 Mon Sep 17 00:00:00 2001 From: Taji Hossein Date: Thu, 6 Apr 2023 17:05:47 +0200 Subject: [PATCH 12/22] removing left comments --- sw/applications/blinky_freertos/main.c | 2 +- .../example_power_gating_core/main.c | 17 +---------------- sw/applications/gpio_pmw/main.c | 19 +++++-------------- 3 files changed, 7 insertions(+), 31 deletions(-) diff --git a/sw/applications/blinky_freertos/main.c b/sw/applications/blinky_freertos/main.c index 2cdca8a62..80d092b48 100644 --- a/sw/applications/blinky_freertos/main.c +++ b/sw/applications/blinky_freertos/main.c @@ -263,7 +263,7 @@ void system_init(void) gpio_write(GPIO_LD5_R, false); gpio_write(GPIO_LD5_B, false); - gpio_write(GPIO_LD5_G, false); + gpio_write(GPIO_LD5_G, false); // Setup rv_timer_0_1 mmio_region_t timer_0_1_reg = mmio_region_from_addr(RV_TIMER_AO_START_ADDRESS); diff --git a/sw/applications/example_power_gating_core/main.c b/sw/applications/example_power_gating_core/main.c index 4f07c4efa..3942cc637 100644 --- a/sw/applications/example_power_gating_core/main.c +++ b/sw/applications/example_power_gating_core/main.c @@ -22,14 +22,9 @@ static const uint64_t kTickFreqHz = 1000 * 1000; // 1 MHz static power_manager_t power_manager; static dif_plic_t rv_plic; -// static gpio_t gpio; int main(int argc, char *argv[]) { - // Setup fast interrupt controller - // fast_intr_ctrl_t fast_intr_ctrl; - // fast_intr_ctrl.base_addr = mmio_region_from_addr((uintptr_t)FAST_INTR_CTRL_START_ADDRESS); - // Setup power_manager mmio_region_t power_manager_reg = mmio_region_from_addr(POWER_MANAGER_START_ADDRESS); power_manager.base_addr = power_manager_reg; @@ -55,11 +50,6 @@ int main(int argc, char *argv[]) mmio_region_t timer_2_3_reg = mmio_region_from_addr(RV_TIMER_START_ADDRESS); rv_timer_init(timer_2_3_reg, (rv_timer_config_t){.hart_count = 2, .comparator_count = 1}, &timer_2_3); - // Setup gpio - // gpio_params_t gpio_params; - // gpio_params.base_addr = mmio_region_from_addr((uintptr_t)GPIO_START_ADDRESS); - // gpio_init(gpio_params, &gpio); - // Init cpu_subsystem's counters if (power_gate_counters_init(&power_manager_cpu_counters, 30, 30, 30, 30, 30, 30, 0, 0) != kPowerManagerOk_e) { @@ -128,19 +118,14 @@ int main(int argc, char *argv[]) dif_plic_irq_set_priority(&rv_plic, GPIO_INTR_31, 1); dif_plic_irq_set_enabled(&rv_plic, GPIO_INTR_31, 0, kDifPlicToggleEnabled); - // gpio_output_set_enabled(&gpio, 30, true); gpio_cfg_t pin1_cfg = {.pin = 30, .mode = GpioModeOutPushPull}; gpio_config (pin1_cfg); + gpio_write(30, true); - // gpio_irq_set_trigger(&gpio, 1 << 31, kGpioIrqTriggerLevelHigh); - // gpio_irq_set_enabled(&gpio, 31, true); gpio_cfg_t pin2_cfg = {.pin = 31, .mode = GpioModeIn,.en_input_sampling = true, .en_intr = true, .intr_type = GpioIntrLevelHigh}; gpio_config (pin2_cfg); - // gpio_write(&gpio, 30, true); - gpio_write(30, true); - CSR_CLEAR_BITS(CSR_REG_MSTATUS, 0x8); if (power_gate_core(&power_manager, kPlic_pm_e, &power_manager_cpu_counters) != kPowerManagerOk_e) { diff --git a/sw/applications/gpio_pmw/main.c b/sw/applications/gpio_pmw/main.c index d6e0c7736..ff37baea5 100644 --- a/sw/applications/gpio_pmw/main.c +++ b/sw/applications/gpio_pmw/main.c @@ -12,12 +12,7 @@ int main(int argc, char *argv[]) { - // gpio_params_t gpio_params; - // gpio_t gpio; gpio_result_t gpio_res; - // gpio_params.base_addr = mmio_region_from_addr((uintptr_t)GPIO_AO_START_ADDRESS); - // gpio_res = gpio_init(gpio_params, &gpio); - // gpio_res = gpio_output_set_enabled(&gpio, GPIO_PMW, true); gpio_cfg_t pin_cfg = { .pin = GPIO_PMW, .mode = GpioModeOutPushPull @@ -29,21 +24,17 @@ int main(int argc, char *argv[]) #ifdef TARGET_PYNQ_Z2 #pragma message ( "this application never ends" ) while(1) { - // gpio_write(&gpio, GPIO_PMW, true); gpio_write(GPIO_PMW, true); - for(int i=0;i<10;i++) asm volatile("nop"); - // gpio_write(&gpio, GPIO_PMW, false); + for(int i=0;i<10;i++) asm volatile("nop"); gpio_write(GPIO_PMW, false); - for(int i=0;i<10;i++) asm volatile("nop"); + for(int i=0;i<10;i++) asm volatile("nop"); } #else for(int i=0;i<100;i++) { - // gpio_write(&gpio, GPIO_PMW, true); - pio_write(GPIO_PMW, true); - for(int i=0;i<10;i++) asm volatile("nop"); - // gpio_write(&gpio, GPIO_PMW, false); + gpio_write(GPIO_PMW, true); + for(int i=0;i<10;i++) asm volatile("nop"); gpio_write(GPIO_PMW, false); - for(int i=0;i<10;i++) asm volatile("nop"); + for(int i=0;i<10;i++) asm volatile("nop"); } #endif From 017f8fc4f362c7cb28ad35008c9566ba1053edf9 Mon Sep 17 00:00:00 2001 From: Taji Hossein Date: Thu, 6 Apr 2023 17:40:21 +0200 Subject: [PATCH 13/22] removing run.sh --- .gitignore | 2 -- run.sh | 28 ---------------------------- 2 files changed, 30 deletions(-) delete mode 100755 run.sh diff --git a/.gitignore b/.gitignore index f60b5d810..085c4cf74 100644 --- a/.gitignore +++ b/.gitignore @@ -46,5 +46,3 @@ sw/device/lib/drivers/**/*_structs.h # openroad flow/OpenROAD-flow-scripts - -run.sh diff --git a/run.sh b/run.sh deleted file mode 100755 index cbb486275..000000000 --- a/run.sh +++ /dev/null @@ -1,28 +0,0 @@ -#! usr/bin/bash# This script is to be run in the x-heep base directory (aka BASE) - # It takes only one argument: the application name. - # It takes for granted that myApplication.c is located in - # BASE/sw/applications/myApplication/# Run this script from the BASE with - # $ sudo bash pynq-run # The pynq-z2 board must be - #   - Powered - #   - Loaded with the appropriate bitstream (use vivado) - #   - Connected to the EPFL programmer - #   - With sw1=0(outside) and sw0=1(inside) -#echo Will build for $1 -echo Will run application $1 - -make app-clean - # Compile and build the binaries to be loaded in the flash. - # To use different LINKER options, just modify this script. - # (remember to also change the make flash-load command below) -make app PROJECT=$1 LINKER=flash_load TARGET=pynq-z2 - - - - # To use the iceprog - -( cd sw/vendor/yosyshq_icestorm/iceprog && make clean && make all) - -# Make and load the flash programmable binary into the iceprog -make flash-prog && - # Open picocom to communicate with the board through UART -picocom -b 115200 -r -l --imap lfcrlf /dev/ttyUSB2 \ No newline at end of file From d299e2bb444491bfe32e25c00981cdfebef065d0 Mon Sep 17 00:00:00 2001 From: Taji Hossein Date: Mon, 17 Apr 2023 11:48:14 +0200 Subject: [PATCH 14/22] bitfield modification, removing magic numbers --- sw/device/lib/base/bitfield.h | 45 +++ sw/device/lib/drivers/gpio/gpio.c | 591 +++++++++++++----------------- sw/device/lib/drivers/gpio/gpio.h | 23 +- 3 files changed, 312 insertions(+), 347 deletions(-) diff --git a/sw/device/lib/base/bitfield.h b/sw/device/lib/base/bitfield.h index 3177f1491..76a94e866 100644 --- a/sw/device/lib/base/bitfield.h +++ b/sw/device/lib/base/bitfield.h @@ -60,6 +60,27 @@ inline uint32_t bitfield_field32_read(uint32_t bitfield, return (bitfield >> field.index) & field.mask; } +/** + * Reads a value from `bitfield` based on given "mask" and "index" + * + * This function uses the `mask` and 'index' parameters to read the value + * from `bitfield`. + * The resulting value will be shifted right and zero-extended so the field's + * zero-bit is the return value's zero-bit. + * + * @param bitfield Bitfield to get the field from. + * @param mask the mask should be one on the affected bits. + * @index index number of bits bitfield is shifted before applying mask. + * @return Zero-extended `field` from `bitfield`. + */ +BITFIELD_WARN_UNUSED_RESULT +inline uint32_t bitfield_read(uint32_t bitfield, + uint32_t mask, + uint32_t index) +{ + return (bitfield >> index) & mask; +} + /** * Writes `value` to `field` in `bitfield`. * @@ -81,6 +102,30 @@ inline uint32_t bitfield_field32_write(uint32_t bitfield, return bitfield; } +/** + * Writes `value` in `bitfield` based on given "mask" and "index" + * + * This function uses the `mask` and 'index' parameters to set specific bits + * in `bitfield`. + * The relevant portion of `bitfield` is zeroed before the bits are set to + * `value`. + * + * @param bitfield Bitfield to set the field in. + * @param field Field within bitfield to be set. + * @param value Value for the new field. + * @return `bitfield` with `field` set to `value`. + */ +BITFIELD_WARN_UNUSED_RESULT +inline uint32_t bitfield_write(uint32_t bitfield, + uint32_t mask, + uint32_t index, + uint32_t value) +{ + bitfield &= ~(mask << index); + bitfield |= (value & mask) << index; + return bitfield; +} + /** * A single bit in a 32-bit bitfield. * diff --git a/sw/device/lib/drivers/gpio/gpio.c b/sw/device/lib/drivers/gpio/gpio.c index 5c376fa24..37e04695c 100644 --- a/sw/device/lib/drivers/gpio/gpio.c +++ b/sw/device/lib/drivers/gpio/gpio.c @@ -32,7 +32,8 @@ #include "gpio.h" #include "gpio_regs.h" // Generated. -#include "gpio_structs.h" //todo: remove it +#include "gpio_structs.h" +#include "bitfield.h" /****************************************************************************/ /** **/ @@ -46,6 +47,57 @@ */ #define MAX_PIN 32 +/** + * Mask for different bit field width + */ +#define MASK_1b 0b1 +#define MASK_2b 0b11 + +/** + * GPIO_EN values + */ +#define GPIO_EN__ENABLED 1 +#define GPIO_EN__DISABLED 0 + +/** + * GPIO_CLEAR and GPIO_SET putting and removing mask + */ +#define GPIO_CLEAR__PUT_MASK 1 +#define GPIO_CLEAR__REMOVE_MASK 0 +#define GPIO_SET__PUT_MASK 1 +#define GPIO_SET__REMOVE_MASK 0 + +/** + * GPIO is set or reset. The value read from gpio_peri->GPIO_IN0 or + * write to gpio_peri->GPIO_OUT0 + */ +#define GPIO_IS_SET 1 +#define GPIO_IS_RESET 0 + +/** + * To enable and disable intr by wrting to INTR_EN registers + */ +#define GPIO_INTR_ENABLE 1 +#define GPIO_INTR_DISABLE 0 + +/** + * Values read after checking intr status registers to see they are + * triggered or not + */ +#define GPIO_INTR_IS_TRIGGERED 1 +#define GPIO_INTR_IS_NOT_TRIGGERED 0 + +/** + * Clearing the status bit by writing one into int + */ +#define GPIO_INTR_CLEAR 1 + +/** + * GPIO intr mode configration index inside GPIO_CFG register. + */ +#define GPIO_CFG_INTR_MODE_INDEX 0 + + /****************************************************************************/ /** **/ /* TYPEDEFS AND STRUCTURES */ @@ -58,34 +110,6 @@ /** **/ /****************************************************************************/ -/** - * @brief do a bitwise operation on 32b register. - * @param reg the register pointer that bitwise operation is done on it. - * @param val the value should be written in part of reg w/o offset. - * @param mask the mask w/o offset. - * @param sel this the offset used for mask and value. - */ -static inline void setBitfield( uint32_t *reg, uint32_t val, - uint32_t mask, uint8_t sel ) -{ - *reg &= ~( mask << sel ); - *reg |= (val & mask) << sel; -} - -/** - * @brief get some bitfield of a 32b reg. - * @param reg the register that bitwise field selects from. - * @param mask the mask w/o offset. - * @param sel this the offset used for mask and value. - */ -static inline uint32_t getBitfield( uint32_t reg, uint32_t mask, uint8_t sel ) -{ - uint32_t ret_val = 0; - ret_val = reg & ( mask << sel ); - ret_val = ret_val >> sel; - return ret_val; -} - /****************************************************************************/ /** **/ /* EXPORTED VARIABLES */ @@ -106,7 +130,7 @@ static inline uint32_t getBitfield( uint32_t reg, uint32_t mask, uint8_t sel ) gpio_result_t gpio_config (gpio_cfg_t cfg){ // /* check that passed arg is not empty*/ - // if (cfg == NULL) + // if (&cfg == NULL) // return GpioError; /* check that pin is in acceptable range. */ if (cfg.pin > (MAX_PIN-1) || cfg.pin < 0) @@ -132,12 +156,14 @@ gpio_result_t gpio_set_mode (gpio_pin_number_t pin, gpio_mode_t mode) { if (pin >= 0 && pin < 16) { - setBitfield(&(gpio_peri->GPIO_MODE0), mode, 0b11, 2*pin); + gpio_peri->GPIO_MODE0 = bitfield_write(gpio_peri->GPIO_MODE0, + MASK_2b, 2*pin, mode); return GpioOk; } else if (pin >= 16 && pin GPIO_MODE1), mode, 0b11, 2*(pin-16)); + gpio_peri->GPIO_MODE1 = bitfield_write(gpio_peri->GPIO_MODE1, + MASK_2b, 2*(pin-16), mode); return GpioOk; } else @@ -148,52 +174,41 @@ gpio_result_t gpio_set_mode (gpio_pin_number_t pin, gpio_mode_t mode) gpio_result_t gpio_en_input_sampling (gpio_pin_number_t pin) { - if (pin >= 0 && pin < MAX_PIN) - { - setBitfield(&(gpio_peri->GPIO_EN0), 1, 0b1, pin); - return GpioOk; - } - else - { + if (pin > (MAX_PIN-1) || pin < 0) return GpioError; - } + gpio_peri->GPIO_EN0 = bitfield_write(gpio_peri->GPIO_EN0, + MASK_1b, pin, GPIO_EN__ENABLED); + return GpioOk; } gpio_result_t gpio_dis_input_sampling (gpio_pin_number_t pin) { - if (pin >= 0 && pin < MAX_PIN) - { - setBitfield(&(gpio_peri->GPIO_EN0), 0, 0b1, pin); - return GpioOk; - } - else - { + if (pin > (MAX_PIN-1) || pin < 0) return GpioError; - } + gpio_peri->GPIO_EN0 = bitfield_write(gpio_peri->GPIO_EN0, + MASK_1b, pin, GPIO_EN__DISABLED); + return GpioOk; } gpio_result_t gpio_reset (gpio_pin_number_t pin) { - if (pin >= 0 && pin < MAX_PIN) - { - gpio_intr_set_mode (0); - gpio_set_mode (pin, GpioModeIn); - gpio_dis_input_sampling (pin); - setBitfield(&(gpio_peri->GPIO_CLEAR0), 0, 0b1, pin); - setBitfield(&(gpio_peri->GPIO_SET0), 0, 0b1, pin); - gpio_intr_dis_all(pin); - gpio_intr_clear_stat(pin); - return GpioOk; - } - else - { + if (pin > (MAX_PIN-1) || pin < 0) return GpioError; - } + + gpio_intr_set_mode (0); + gpio_set_mode (pin, GpioModeIn); + gpio_dis_input_sampling (pin); + gpio_peri->GPIO_CLEAR0 = bitfield_write(gpio_peri->GPIO_CLEAR0, + MASK_1b, pin, GPIO_CLEAR__REMOVE_MASK); + gpio_peri->GPIO_SET0 = bitfield_write(gpio_peri->GPIO_SET0, + MASK_1b, pin, GPIO_SET__REMOVE_MASK); + gpio_intr_dis_all(pin); + gpio_intr_clear_stat(pin); + return GpioOk; } gpio_result_t gpio_reset_all (void) { - setBitfield(&(gpio_peri->GPIO_CLEAR0), 0, 0b1, 0); gpio_peri->GPIO_MODE0 = 0; gpio_peri->GPIO_MODE1 = 0; gpio_peri->GPIO_EN0 = 0; @@ -209,405 +224,297 @@ gpio_result_t gpio_reset_all (void) gpio_result_t gpio_read (gpio_pin_number_t pin, bool *val) { - if (pin >= 0 && pin < MAX_PIN) - { - if ( getBitfield(gpio_peri->GPIO_IN0, 0b1, pin) == 0b1) - *val = true; - else - *val = false; - return GpioOk; - } - else - { + if (pin > (MAX_PIN-1) || pin < 0) return GpioError; - } + if (bitfield_read(gpio_peri->GPIO_IN0, MASK_1b, pin) == GPIO_IS_SET) + *val = true; + else + *val = false; + return GpioOk; } -// gpio_result_t gpio_pin_set (gpio_pin_number_t pin) -// { -// if (pin >= 0 && pin < 32) -// { -// gpio_peri->GPIO_SET0 = 1 << pin; -// gpio_peri->GPIO_OUT0 = 1 << pin; -// return GpioOk; -// } -// else -// { -// return GpioError; -// } -// } - -// gpio_result_t gpio_pin_clear (gpio_pin_number_t pin) -// { -// if (pin >= 0 && pin < 32) -// { -// gpio_peri->GPIO_CLEAR0 = 1 << pin; -// gpio_peri->GPIO_OUT0 &= ~(1 << pin); -// return GpioOk; -// } -// else -// { -// return GpioError; -// } -// } - -//todo: check to see its toggling or just writing one +//todo: check it gpio_result_t gpio_toggle (gpio_pin_number_t pin) { - if (pin >= 0 && pin < MAX_PIN) - { - gpio_peri->GPIO_TOGGLE0 = 1 << pin; - gpio_peri->GPIO_OUT0 = 1 << pin; - return GpioOk; - } - else - { + if (pin > (MAX_PIN-1) || pin < 0) return GpioError; - } + if (bitfield_read(gpio_peri->GPIO_IN0, MASK_1b, pin) == GPIO_IS_SET) + gpio_peri->GPIO_OUT0 = bitfield_write(gpio_peri->GPIO_OUT0, + MASK_1b, pin, GPIO_IS_RESET); + else + gpio_peri->GPIO_OUT0 = bitfield_write(gpio_peri->GPIO_OUT0, + MASK_1b, pin, GPIO_IS_SET); + return GpioOk; } gpio_result_t gpio_write (gpio_pin_number_t pin, bool val) { - if (pin >= 0 && pin < MAX_PIN) - { - if (val == true) - setBitfield(&(gpio_peri->GPIO_OUT0), 1, 1, pin); - else - setBitfield(&(gpio_peri->GPIO_OUT0), 0, 1, pin); - return GpioOk; - } - else - { + if (pin > (MAX_PIN-1) || pin < 0) return GpioError; - } + if (val == GPIO_IS_SET) + gpio_peri->GPIO_OUT0 = bitfield_write(gpio_peri->GPIO_OUT0, + MASK_1b, pin, GPIO_IS_SET); + else + gpio_peri->GPIO_OUT0 = bitfield_write(gpio_peri->GPIO_OUT0, + MASK_1b, pin, GPIO_IS_RESET); + return GpioOk; + } gpio_result_t gpio_intr_en_rise (gpio_pin_number_t pin) { - if (pin >= 0 && pin < MAX_PIN) - { - setBitfield(&(gpio_peri->INTRPT_RISE_EN0), 1, 1, pin); - return GpioOk; - } - else - { + if (pin > (MAX_PIN-1) || pin < 0) return GpioError; - } + gpio_peri->INTRPT_RISE_EN0 = bitfield_write( + gpio_peri->INTRPT_RISE_EN0, MASK_1b, pin, GPIO_INTR_ENABLE); + return GpioOk; } gpio_result_t gpio_intr_en_fall (gpio_pin_number_t pin) { - if (pin >= 0 && pin < MAX_PIN) - { - setBitfield(&(gpio_peri->INTRPT_FALL_EN0), 1, 1, pin); - return GpioOk; - } - else - { + if (pin > (MAX_PIN-1) || pin < 0) return GpioError; - } + gpio_peri->INTRPT_FALL_EN0 = bitfield_write(gpio_peri->INTRPT_FALL_EN0, + MASK_1b, pin, GPIO_INTR_ENABLE); + return GpioOk; } gpio_result_t gpio_intr_en_lvl_high (gpio_pin_number_t pin) { - if (pin >= 0 && pin < MAX_PIN) - { - setBitfield(&(gpio_peri->INTRPT_LVL_HIGH_EN0), 1, 1, pin); - return GpioOk; - } - else - { + if (pin > (MAX_PIN-1) || pin < 0) return GpioError; - } + gpio_peri->INTRPT_LVL_HIGH_EN0 = bitfield_write( + gpio_peri->INTRPT_LVL_HIGH_EN0, MASK_1b, pin, GPIO_INTR_ENABLE); + return GpioOk; } gpio_result_t gpio_intr_en_lvl_low (gpio_pin_number_t pin) { - if (pin >= 0 && pin < MAX_PIN) - { - setBitfield(&(gpio_peri->INTRPT_LVL_LOW_EN0), 1, 1, pin); - return GpioOk; - } - else - { + if (pin > (MAX_PIN-1) || pin < 0) return GpioError; - } + gpio_peri->INTRPT_LVL_LOW_EN0 = bitfield_write( + gpio_peri->INTRPT_LVL_LOW_EN0, MASK_1b, pin, GPIO_INTR_ENABLE); + return GpioOk; } gpio_result_t gpio_intr_dis_rise (gpio_pin_number_t pin) { - if (pin >= 0 && pin < MAX_PIN) - { - setBitfield(&(gpio_peri->INTRPT_RISE_EN0), 0, 1, pin); - return GpioOk; - } - else - { + if (pin > (MAX_PIN-1) || pin < 0) return GpioError; - } + gpio_peri->INTRPT_RISE_EN0 = bitfield_write( + gpio_peri->INTRPT_RISE_EN0, MASK_1b, pin, GPIO_INTR_DISABLE); + return GpioOk; } gpio_result_t gpio_intr_dis_fall (gpio_pin_number_t pin) { - if (pin >= 0 && pin < MAX_PIN) - { - setBitfield(&(gpio_peri->INTRPT_FALL_EN0), 0, 1, pin); - return GpioOk; - } - else - { + if (pin > (MAX_PIN-1) || pin < 0) return GpioError; - } + gpio_peri->INTRPT_FALL_EN0 = bitfield_write( + gpio_peri->INTRPT_FALL_EN0, MASK_1b, pin, GPIO_INTR_DISABLE); + return GpioOk; } gpio_result_t gpio_intr_dis_lvl_high (gpio_pin_number_t pin) { - if (pin >= 0 && pin < MAX_PIN) - { - setBitfield(&(gpio_peri->INTRPT_LVL_HIGH_EN0), 0, 1, pin); - return GpioOk; - } - else - { + if (pin > (MAX_PIN-1) || pin < 0) return GpioError; - } + gpio_peri->INTRPT_LVL_HIGH_EN0 = bitfield_write( + gpio_peri->INTRPT_LVL_HIGH_EN0, MASK_1b, pin, GPIO_INTR_DISABLE); + return GpioOk; } gpio_result_t gpio_intr_dis_lvl_low (gpio_pin_number_t pin) { - if (pin >= 0 && pin < MAX_PIN) - { - setBitfield(&(gpio_peri->INTRPT_LVL_LOW_EN0), 0, 1, pin); - return GpioOk; - } - else - { + if (pin > (MAX_PIN-1) || pin < 0) return GpioError; - } + gpio_peri->INTRPT_LVL_LOW_EN0 = bitfield_write( + gpio_peri->INTRPT_LVL_LOW_EN0, MASK_1b, pin, GPIO_INTR_DISABLE); + return GpioOk; } gpio_result_t gpio_intr_dis_all (gpio_pin_number_t pin){ - if (pin >= 0 && pin < MAX_PIN) - { - setBitfield(&(gpio_peri->INTRPT_RISE_EN0), 0, 1, pin); - setBitfield(&(gpio_peri->INTRPT_FALL_EN0), 0, 1, pin); - setBitfield(&(gpio_peri->INTRPT_LVL_HIGH_EN0), 0, 1, pin); - setBitfield(&(gpio_peri->INTRPT_LVL_LOW_EN0), 0, 1, pin); - return GpioOk; - } - else - { + if (pin > (MAX_PIN-1) || pin < 0) return GpioError; - } + gpio_peri->INTRPT_RISE_EN0 = bitfield_write( + gpio_peri->INTRPT_RISE_EN0, MASK_1b, pin, GPIO_INTR_DISABLE); + gpio_peri->INTRPT_FALL_EN0 = bitfield_write( + gpio_peri->INTRPT_FALL_EN0, MASK_1b, pin, GPIO_INTR_DISABLE); + gpio_peri->INTRPT_LVL_HIGH_EN0 = bitfield_write( + gpio_peri->INTRPT_LVL_HIGH_EN0, MASK_1b, pin, GPIO_INTR_DISABLE); + gpio_peri->INTRPT_LVL_LOW_EN0 = bitfield_write( + gpio_peri->INTRPT_LVL_LOW_EN0, MASK_1b, pin, GPIO_INTR_DISABLE); + return GpioOk; } gpio_result_t gpio_intr_en (gpio_pin_number_t pin, gpio_intr_type_t type) { - if (pin >= 0 && pin < MAX_PIN) - { - gpio_intr_dis_all(pin); - - switch(type) - { - case GpioIntrEdgeRising: - gpio_intr_en_rise(pin); - break; - - case GpioIntrEdgeFalling: - gpio_intr_en_fall(pin); - break; - - case GpioIntrLevelLow: - gpio_intr_en_lvl_low(pin); - break; - - case GpioIntrLevelHigh: - gpio_intr_en_lvl_high(pin); - break; - - case GpioIntrEdgeRisingFalling: - gpio_intr_en_rise(pin); - gpio_intr_en_fall(pin); - break; - - case GpioIntrEdgeRisingLevelLow: - gpio_intr_en_rise(pin); - gpio_intr_en_lvl_low(pin); - break; - - case GpioIntrEdgeFallingLevelHigh: - gpio_intr_en_fall(pin); - gpio_intr_en_lvl_high(pin); - break; - - default: - return GpioError; - } - return GpioOk; - } - else - { + if (pin > (MAX_PIN-1) || pin < 0) + return GpioError; + gpio_intr_dis_all(pin); + switch(type) + { + case GpioIntrEdgeRising: + gpio_intr_en_rise(pin); + break; + case GpioIntrEdgeFalling: + gpio_intr_en_fall(pin); + break; + case GpioIntrLevelLow: + gpio_intr_en_lvl_low(pin); + break; + case GpioIntrLevelHigh: + gpio_intr_en_lvl_high(pin); + break; + case GpioIntrEdgeRisingFalling: + gpio_intr_en_rise(pin); + gpio_intr_en_fall(pin); + break; + case GpioIntrEdgeRisingLevelLow: + gpio_intr_en_rise(pin); + gpio_intr_en_lvl_low(pin); + break; + case GpioIntrEdgeFallingLevelHigh: + gpio_intr_en_fall(pin); + gpio_intr_en_lvl_high(pin); + break; + default: return GpioError; } + return GpioOk; } gpio_result_t gpio_intr_check_stat_rise (gpio_pin_number_t pin, bool *is_pending) { - if (pin >= 0 && pin < MAX_PIN) - { - if (getBitfield(gpio_peri->INTRPT_RISE_STATUS0, 1, pin) == 1) - *is_pending = true; - else - *is_pending = false; - return GpioOk; - } - else - { - *is_pending = false; + if (pin > (MAX_PIN-1) || pin < 0) + { + *is_pending = GPIO_INTR_IS_NOT_TRIGGERED; return GpioError; } + + if (bitfield_read(gpio_peri->INTRPT_RISE_STATUS0, MASK_1b, pin) == + GPIO_INTR_IS_TRIGGERED) + *is_pending = GPIO_INTR_IS_TRIGGERED; + else + *is_pending = GPIO_INTR_IS_NOT_TRIGGERED; + return GpioOk; } gpio_result_t gpio_intr_check_stat_fall (gpio_pin_number_t pin, bool *is_pending) { - if (pin >= 0 && pin < MAX_PIN) - { - if (getBitfield(gpio_peri->INTRPT_FALL_STATUS0, 1, pin) == 1) - *is_pending = true; - else - *is_pending = false; - return GpioOk; - } - else - { - *is_pending = false; + if (pin > (MAX_PIN-1) || pin < 0) + { + *is_pending = GPIO_INTR_IS_NOT_TRIGGERED; return GpioError; } + + if (bitfield_read(gpio_peri->INTRPT_FALL_STATUS0, MASK_1b, pin) == + GPIO_INTR_IS_TRIGGERED) + *is_pending = GPIO_INTR_IS_TRIGGERED; + else + *is_pending = GPIO_INTR_IS_NOT_TRIGGERED; + return GpioOk; } gpio_result_t gpio_intr_check_stat_lvl_low (gpio_pin_number_t pin, bool *is_pending) { - if (pin >= 0 && pin < MAX_PIN) - { - if (getBitfield(gpio_peri->INTRPT_LVL_LOW_STATUS0, 1, pin) == 1) - *is_pending = true; - else - *is_pending = false; - return GpioOk; - } - else - { - *is_pending = false; + if (pin > (MAX_PIN-1) || pin < 0) + { + *is_pending = GPIO_INTR_IS_NOT_TRIGGERED; return GpioError; } + + if (bitfield_read(gpio_peri->INTRPT_LVL_LOW_STATUS0, MASK_1b, pin) == + GPIO_INTR_IS_TRIGGERED) + *is_pending = GPIO_INTR_IS_TRIGGERED; + else + *is_pending = GPIO_INTR_IS_NOT_TRIGGERED; + return GpioOk; } gpio_result_t gpio_intr_check_stat_lvl_high (gpio_pin_number_t pin, bool *is_pending) { - if (pin >= 0 && pin < MAX_PIN) - { - if (getBitfield(gpio_peri->INTRPT_LVL_HIGH_STATUS0, 1, pin) == 1) - *is_pending = true; - else - *is_pending = false; - return GpioOk; - } - else - { - *is_pending = false; + if (pin > (MAX_PIN-1) || pin < 0) + { + *is_pending = GPIO_INTR_IS_NOT_TRIGGERED; return GpioError; } + + if (bitfield_read(gpio_peri->INTRPT_LVL_HIGH_STATUS0, MASK_1b, pin) == + GPIO_INTR_IS_TRIGGERED) + *is_pending = GPIO_INTR_IS_TRIGGERED; + else + *is_pending = GPIO_INTR_IS_NOT_TRIGGERED; + return GpioOk; } gpio_result_t gpio_intr_check_stat (gpio_pin_number_t pin, bool *is_pending) { - if (pin >= 0 && pin < MAX_PIN) - { - if (getBitfield(gpio_peri->INTRPT_STATUS0, 1, pin) == 1) - *is_pending = true; - else - *is_pending = false; - return GpioOk; - } - else - { - *is_pending = false; + if (pin > (MAX_PIN-1) || pin < 0) + { + *is_pending = GPIO_INTR_IS_NOT_TRIGGERED; return GpioError; } + + if (bitfield_read(gpio_peri->INTRPT_STATUS0, MASK_1b, pin) == + GPIO_INTR_IS_TRIGGERED) + *is_pending = GPIO_INTR_IS_TRIGGERED; + else + *is_pending = GPIO_INTR_IS_NOT_TRIGGERED; + return GpioOk; } gpio_result_t gpio_intr_clear_stat_rise (gpio_pin_number_t pin) { - if (pin >= 0 && pin < MAX_PIN) - { - setBitfield(&(gpio_peri->INTRPT_RISE_STATUS0), 1, 1, pin); - return GpioOk; - } - else - { + if (pin > (MAX_PIN-1) || pin < 0) return GpioError; - } + gpio_peri->INTRPT_RISE_STATUS0 = bitfield_write( + gpio_peri->INTRPT_RISE_STATUS0, MASK_1b, pin, GPIO_INTR_CLEAR); + return GpioOk; + } gpio_result_t gpio_intr_clear_stat_fall (gpio_pin_number_t pin) { - if (pin >= 0 && pin < MAX_PIN) - { - setBitfield(&(gpio_peri->INTRPT_FALL_STATUS0), 1, 1, pin); - return GpioOk; - } - else - { + if (pin > (MAX_PIN-1) || pin < 0) return GpioError; - } + gpio_peri->INTRPT_FALL_STATUS0 = bitfield_write( + gpio_peri->INTRPT_FALL_STATUS0, MASK_1b, pin, GPIO_INTR_CLEAR); + return GpioOk; } gpio_result_t gpio_intr_clear_stat_lvl_low (gpio_pin_number_t pin) { - if (pin >= 0 && pin < MAX_PIN) - { - setBitfield(&(gpio_peri->INTRPT_LVL_LOW_STATUS0), 1, 1, pin); - return GpioOk; - } - else - { + if (pin > (MAX_PIN-1) || pin < 0) return GpioError; - } + gpio_peri->INTRPT_LVL_LOW_STATUS0 = bitfield_write( + gpio_peri->INTRPT_LVL_LOW_STATUS0, MASK_1b, pin, GPIO_INTR_CLEAR); + return GpioOk; } gpio_result_t gpio_intr_clear_stat_lvl_high (gpio_pin_number_t pin) { - if (pin >= 0 && pin < MAX_PIN) - { - setBitfield(&(gpio_peri->INTRPT_LVL_HIGH_STATUS0), 1, 1, pin); - return GpioOk; - } - else - { + if (pin > (MAX_PIN-1) || pin < 0) return GpioError; - } + gpio_peri->INTRPT_LVL_HIGH_STATUS0 = bitfield_write( + gpio_peri->INTRPT_LVL_HIGH_STATUS0, MASK_1b, pin, GPIO_INTR_CLEAR); + return GpioOk; } gpio_result_t gpio_intr_clear_stat (gpio_pin_number_t pin) { - if (pin >= 0 && pin < MAX_PIN) - { - setBitfield(&(gpio_peri->INTRPT_STATUS0), 1, 1, pin); - return GpioOk; - } - else - { + if (pin > (MAX_PIN-1) || pin < 0) return GpioError; - } + gpio_peri->INTRPT_STATUS0 = bitfield_write( + gpio_peri->INTRPT_STATUS0, MASK_1b, pin, GPIO_INTR_CLEAR); + return GpioOk; } -gpio_result_t gpio_intr_set_mode (bool gpio_intr_mode) +gpio_result_t gpio_intr_set_mode (gpio_intr_general_mode_t mode) { - if (gpio_intr_mode) - setBitfield(&(gpio_peri->CFG), 1, 1, 0); - else - setBitfield(&(gpio_peri->CFG), 0, 1, 0); + gpio_peri->CFG = bitfield_write( + gpio_peri->CFG, MASK_1b, GPIO_CFG_INTR_MODE_INDEX, mode); return GpioOk; } /****************************************************************************/ diff --git a/sw/device/lib/drivers/gpio/gpio.h b/sw/device/lib/drivers/gpio/gpio.h index f4da061ae..90e0309bf 100644 --- a/sw/device/lib/drivers/gpio/gpio.h +++ b/sw/device/lib/drivers/gpio/gpio.h @@ -66,6 +66,22 @@ typedef enum gpio_mode mode. */ } gpio_mode_t; +/** + * gpio_intr_general_mode + * 1 keep the interrupt line asserted until all interrupts for all GPIOs + * are cleared. + * 0 generate one cycle wide pulses for every new interrupt. + */ +typedef enum gpio_intr_general_mode +{ + IntrOnePulse = 0, /*!< keep the interrupt line asserted until all + interrupts for all GPIOs are cleared. */ + IntrAsserted = 1, /*!< generate one cycle wide pulses for every + new interrupt. */ +} gpio_intr_general_mode_t; + + + /** * This type is used in almost all the operations, and it is returned when * there is a problem with functions given parameters or operation for example @@ -100,7 +116,7 @@ typedef enum gpio_intr_type typedef struct gpio_cfg { gpio_pin_number_t pin; /*!< pin number. */ - gpio_pin_number_t mode; /*!< pin mode. */ + gpio_mode_t mode; /*!< pin mode. */ bool en_input_sampling; /*!< enable sampling (being input is req). */ bool en_intr; /*!< enable intr (being input is req). */ gpio_intr_type_t intr_type; /*!< intr type (enabling intr is req). */ @@ -167,9 +183,6 @@ gpio_result_t gpio_en_input_sampling (gpio_pin_number_t pin); */ gpio_result_t gpio_dis_input_sampling (gpio_pin_number_t pin); - - - /** * @brief reading from a gpio pin, which is done by reading from GPIO_IN reg * @param gpio_pin_number_t specify pin number @@ -348,7 +361,7 @@ gpio_result_t gpio_intr_clear_stat (gpio_pin_number_t pin); * interrupts for all GPIOs are cleared. If false, generate one cycle wide * pulses for every new interrupt. */ -gpio_result_t gpio_intr_set_mode (bool gpio_intr_mode); +gpio_result_t gpio_intr_set_mode (gpio_intr_general_mode_t mode); From 83e9e91766f243c413858d5f6b64075ae24d6a3a Mon Sep 17 00:00:00 2001 From: Taji Hossein Date: Mon, 24 Apr 2023 15:02:41 +0200 Subject: [PATCH 15/22] adding max pin to xheep.h --- sw/applications/example_gpio_cnt/main.c | 11 ++++++++++- sw/device/lib/drivers/gpio/gpio.c | 7 +------ sw/device/target/pynq-z2/x-heep.h | 6 ++++++ 3 files changed, 17 insertions(+), 7 deletions(-) diff --git a/sw/applications/example_gpio_cnt/main.c b/sw/applications/example_gpio_cnt/main.c index 701adb1e3..bf77156d2 100644 --- a/sw/applications/example_gpio_cnt/main.c +++ b/sw/applications/example_gpio_cnt/main.c @@ -14,7 +14,7 @@ #include "pad_control.h" #include "pad_control_regs.h" // Generated. #include "x-heep.h" -#include "gpio_structs.h" //remove +#include //todo: remove /* Notes: @@ -119,6 +119,15 @@ int main(int argc, char *argv[]) return -1; } + uint8_t val = 0; + while(1){ + gpio_toggle(GPIO_TB_OUT); + for( uint32_t i; i < 1<<30; i++ ){ asm("nop"); } + gpio_read(GPIO_TB_IN, &val); + printf("val: %d\r\n", val); + + } + printf("Write 1 to GPIO 30 and wait for interrupt...\n"); external_intr_flag = 0; while(external_intr_flag==0) { diff --git a/sw/device/lib/drivers/gpio/gpio.c b/sw/device/lib/drivers/gpio/gpio.c index 37e04695c..de8585005 100644 --- a/sw/device/lib/drivers/gpio/gpio.c +++ b/sw/device/lib/drivers/gpio/gpio.c @@ -34,6 +34,7 @@ #include "gpio_regs.h" // Generated. #include "gpio_structs.h" #include "bitfield.h" +#include "x-heep.h" /****************************************************************************/ /** **/ @@ -41,12 +42,6 @@ /** **/ /****************************************************************************/ -/** - * As the hw is configurable, we can have setups with different number of - * Gpio pins - */ -#define MAX_PIN 32 - /** * Mask for different bit field width */ diff --git a/sw/device/target/pynq-z2/x-heep.h b/sw/device/target/pynq-z2/x-heep.h index e1b5833a2..ec6c43e9c 100644 --- a/sw/device/target/pynq-z2/x-heep.h +++ b/sw/device/target/pynq-z2/x-heep.h @@ -16,6 +16,12 @@ extern "C" { #define UART_BAUDRATE 115200 #define TARGET_PYNQ_Z2 +/** + * As the hw is configurable, we can have setups with different number of + * Gpio pins + */ +#define MAX_PIN 32 + #ifdef __cplusplus } // extern "C" From 128ab634ebaa2ef42d615ecaf7e7db1385ccfa2b Mon Sep 17 00:00:00 2001 From: Taji Hossein Date: Mon, 24 Apr 2023 17:43:52 +0200 Subject: [PATCH 16/22] gpio_toggle bug was solved --- sw/applications/example_gpio_cnt/main.c | 6 ++++ sw/device/lib/base/bitfield.h | 45 ------------------------- sw/device/lib/drivers/gpio/gpio.c | 6 +++- 3 files changed, 11 insertions(+), 46 deletions(-) diff --git a/sw/applications/example_gpio_cnt/main.c b/sw/applications/example_gpio_cnt/main.c index bf77156d2..e15114c4a 100644 --- a/sw/applications/example_gpio_cnt/main.c +++ b/sw/applications/example_gpio_cnt/main.c @@ -120,8 +120,14 @@ int main(int argc, char *argv[]) } uint8_t val = 0; + + gpio_write(GPIO_TB_OUT, true); + printf("HEY\r\n"); + gpio_toggle(GPIO_TB_OUT); + while(1){ gpio_toggle(GPIO_TB_OUT); + printf("HEY\r\n"); for( uint32_t i; i < 1<<30; i++ ){ asm("nop"); } gpio_read(GPIO_TB_IN, &val); printf("val: %d\r\n", val); diff --git a/sw/device/lib/base/bitfield.h b/sw/device/lib/base/bitfield.h index 06f7117f2..394e3a31b 100644 --- a/sw/device/lib/base/bitfield.h +++ b/sw/device/lib/base/bitfield.h @@ -60,27 +60,6 @@ inline uint32_t bitfield_field32_read(uint32_t bitfield, return (bitfield >> field.index) & field.mask; } -/** - * Reads a value from `bitfield` based on given "mask" and "index" - * - * This function uses the `mask` and 'index' parameters to read the value - * from `bitfield`. - * The resulting value will be shifted right and zero-extended so the field's - * zero-bit is the return value's zero-bit. - * - * @param bitfield Bitfield to get the field from. - * @param mask the mask should be one on the affected bits. - * @index index number of bits bitfield is shifted before applying mask. - * @return Zero-extended `field` from `bitfield`. - */ -BITFIELD_WARN_UNUSED_RESULT -inline uint32_t bitfield_read(uint32_t bitfield, - uint32_t mask, - uint32_t index) -{ - return (bitfield >> index) & mask; -} - /** * Writes `value` to `field` in `bitfield`. * @@ -102,30 +81,6 @@ inline uint32_t bitfield_field32_write(uint32_t bitfield, return bitfield; } -/** - * Writes `value` in `bitfield` based on given "mask" and "index" - * - * This function uses the `mask` and 'index' parameters to set specific bits - * in `bitfield`. - * The relevant portion of `bitfield` is zeroed before the bits are set to - * `value`. - * - * @param bitfield Bitfield to set the field in. - * @param field Field within bitfield to be set. - * @param value Value for the new field. - * @return `bitfield` with `field` set to `value`. - */ -BITFIELD_WARN_UNUSED_RESULT -inline uint32_t bitfield_write(uint32_t bitfield, - uint32_t mask, - uint32_t index, - uint32_t value) -{ - bitfield &= ~(mask << index); - bitfield |= (value & mask) << index; - return bitfield; -} - /** * A single bit in a 32-bit bitfield. * diff --git a/sw/device/lib/drivers/gpio/gpio.c b/sw/device/lib/drivers/gpio/gpio.c index de8585005..97bed077a 100644 --- a/sw/device/lib/drivers/gpio/gpio.c +++ b/sw/device/lib/drivers/gpio/gpio.c @@ -233,12 +233,16 @@ gpio_result_t gpio_toggle (gpio_pin_number_t pin) { if (pin > (MAX_PIN-1) || pin < 0) return GpioError; - if (bitfield_read(gpio_peri->GPIO_IN0, MASK_1b, pin) == GPIO_IS_SET) + if (bitfield_read(gpio_peri->GPIO_OUT0, MASK_1b, pin) == GPIO_IS_SET) + { gpio_peri->GPIO_OUT0 = bitfield_write(gpio_peri->GPIO_OUT0, MASK_1b, pin, GPIO_IS_RESET); + } else + { gpio_peri->GPIO_OUT0 = bitfield_write(gpio_peri->GPIO_OUT0, MASK_1b, pin, GPIO_IS_SET); + } return GpioOk; } From dc3683f028b54725dd5f467c500ef099a1a6b736 Mon Sep 17 00:00:00 2001 From: Taji Hossein Date: Mon, 24 Apr 2023 18:46:09 +0200 Subject: [PATCH 17/22] adding error types --- sw/applications/example_gpio_cnt/main.c | 21 +++----- sw/device/lib/drivers/gpio/gpio.c | 71 ++++++++++++------------- sw/device/lib/drivers/gpio/gpio.h | 17 +++--- 3 files changed, 47 insertions(+), 62 deletions(-) diff --git a/sw/applications/example_gpio_cnt/main.c b/sw/applications/example_gpio_cnt/main.c index e15114c4a..fbf24c401 100644 --- a/sw/applications/example_gpio_cnt/main.c +++ b/sw/applications/example_gpio_cnt/main.c @@ -119,20 +119,15 @@ int main(int argc, char *argv[]) return -1; } - uint8_t val = 0; - - gpio_write(GPIO_TB_OUT, true); - printf("HEY\r\n"); - gpio_toggle(GPIO_TB_OUT); - - while(1){ - gpio_toggle(GPIO_TB_OUT); - printf("HEY\r\n"); - for( uint32_t i; i < 1<<30; i++ ){ asm("nop"); } - gpio_read(GPIO_TB_IN, &val); - printf("val: %d\r\n", val); - } + // while(1){ + // gpio_toggle(GPIO_TB_OUT); + // printf("HEY\r\n"); + // for( uint32_t i; i < 1<<30; i++ ){ asm("nop"); } + // gpio_read(GPIO_TB_IN, &val); + // printf("val: %d\r\n", val); + + // } printf("Write 1 to GPIO 30 and wait for interrupt...\n"); external_intr_flag = 0; diff --git a/sw/device/lib/drivers/gpio/gpio.c b/sw/device/lib/drivers/gpio/gpio.c index 97bed077a..43c26f66c 100644 --- a/sw/device/lib/drivers/gpio/gpio.c +++ b/sw/device/lib/drivers/gpio/gpio.c @@ -124,17 +124,14 @@ /****************************************************************************/ gpio_result_t gpio_config (gpio_cfg_t cfg){ - // /* check that passed arg is not empty*/ - // if (&cfg == NULL) - // return GpioError; /* check that pin is in acceptable range. */ if (cfg.pin > (MAX_PIN-1) || cfg.pin < 0) - return GpioError; + return GpioPinNotAcceptable; /* reset pin coniguration first.*/ gpio_reset (cfg.pin); /* check mode. */ if ((cfg.mode < GpioModeIn) || (cfg.mode > GpioModeoutOpenDrain1)) - return GpioError; + return GpioModeNotAcceptable; /* set mode. */ gpio_set_mode (cfg.pin, cfg.mode); /* if input sampling is enabled */ @@ -142,8 +139,8 @@ gpio_result_t gpio_config (gpio_cfg_t cfg){ gpio_en_input_sampling (cfg.pin); /* if interrupt is enabled. Also after enabling check for error */ if (cfg.en_intr == true) - if (gpio_intr_en (cfg.pin, cfg.intr_type) == GpioError) - return GpioError; + if (gpio_intr_en (cfg.pin, cfg.intr_type) != GpioOk) + return GpioIntrTypeNotAcceptable; return GpioOk; } @@ -163,14 +160,14 @@ gpio_result_t gpio_set_mode (gpio_pin_number_t pin, gpio_mode_t mode) } else { - return GpioError; + return GpioModeNotAcceptable; } } gpio_result_t gpio_en_input_sampling (gpio_pin_number_t pin) { if (pin > (MAX_PIN-1) || pin < 0) - return GpioError; + return GpioPinNotAcceptable; gpio_peri->GPIO_EN0 = bitfield_write(gpio_peri->GPIO_EN0, MASK_1b, pin, GPIO_EN__ENABLED); return GpioOk; @@ -179,7 +176,7 @@ gpio_result_t gpio_en_input_sampling (gpio_pin_number_t pin) gpio_result_t gpio_dis_input_sampling (gpio_pin_number_t pin) { if (pin > (MAX_PIN-1) || pin < 0) - return GpioError; + return GpioPinNotAcceptable; gpio_peri->GPIO_EN0 = bitfield_write(gpio_peri->GPIO_EN0, MASK_1b, pin, GPIO_EN__DISABLED); return GpioOk; @@ -188,7 +185,7 @@ gpio_result_t gpio_dis_input_sampling (gpio_pin_number_t pin) gpio_result_t gpio_reset (gpio_pin_number_t pin) { if (pin > (MAX_PIN-1) || pin < 0) - return GpioError; + return GpioPinNotAcceptable; gpio_intr_set_mode (0); gpio_set_mode (pin, GpioModeIn); @@ -220,7 +217,7 @@ gpio_result_t gpio_reset_all (void) gpio_result_t gpio_read (gpio_pin_number_t pin, bool *val) { if (pin > (MAX_PIN-1) || pin < 0) - return GpioError; + return GpioPinNotAcceptable; if (bitfield_read(gpio_peri->GPIO_IN0, MASK_1b, pin) == GPIO_IS_SET) *val = true; else @@ -232,7 +229,7 @@ gpio_result_t gpio_read (gpio_pin_number_t pin, bool *val) gpio_result_t gpio_toggle (gpio_pin_number_t pin) { if (pin > (MAX_PIN-1) || pin < 0) - return GpioError; + return GpioPinNotAcceptable; if (bitfield_read(gpio_peri->GPIO_OUT0, MASK_1b, pin) == GPIO_IS_SET) { gpio_peri->GPIO_OUT0 = bitfield_write(gpio_peri->GPIO_OUT0, @@ -249,7 +246,7 @@ gpio_result_t gpio_toggle (gpio_pin_number_t pin) gpio_result_t gpio_write (gpio_pin_number_t pin, bool val) { if (pin > (MAX_PIN-1) || pin < 0) - return GpioError; + return GpioPinNotAcceptable; if (val == GPIO_IS_SET) gpio_peri->GPIO_OUT0 = bitfield_write(gpio_peri->GPIO_OUT0, MASK_1b, pin, GPIO_IS_SET); @@ -263,7 +260,7 @@ gpio_result_t gpio_write (gpio_pin_number_t pin, bool val) gpio_result_t gpio_intr_en_rise (gpio_pin_number_t pin) { if (pin > (MAX_PIN-1) || pin < 0) - return GpioError; + return GpioPinNotAcceptable; gpio_peri->INTRPT_RISE_EN0 = bitfield_write( gpio_peri->INTRPT_RISE_EN0, MASK_1b, pin, GPIO_INTR_ENABLE); return GpioOk; @@ -272,7 +269,7 @@ gpio_result_t gpio_intr_en_rise (gpio_pin_number_t pin) gpio_result_t gpio_intr_en_fall (gpio_pin_number_t pin) { if (pin > (MAX_PIN-1) || pin < 0) - return GpioError; + return GpioPinNotAcceptable; gpio_peri->INTRPT_FALL_EN0 = bitfield_write(gpio_peri->INTRPT_FALL_EN0, MASK_1b, pin, GPIO_INTR_ENABLE); return GpioOk; @@ -281,7 +278,7 @@ gpio_result_t gpio_intr_en_fall (gpio_pin_number_t pin) gpio_result_t gpio_intr_en_lvl_high (gpio_pin_number_t pin) { if (pin > (MAX_PIN-1) || pin < 0) - return GpioError; + return GpioPinNotAcceptable; gpio_peri->INTRPT_LVL_HIGH_EN0 = bitfield_write( gpio_peri->INTRPT_LVL_HIGH_EN0, MASK_1b, pin, GPIO_INTR_ENABLE); return GpioOk; @@ -290,7 +287,7 @@ gpio_result_t gpio_intr_en_lvl_high (gpio_pin_number_t pin) gpio_result_t gpio_intr_en_lvl_low (gpio_pin_number_t pin) { if (pin > (MAX_PIN-1) || pin < 0) - return GpioError; + return GpioPinNotAcceptable; gpio_peri->INTRPT_LVL_LOW_EN0 = bitfield_write( gpio_peri->INTRPT_LVL_LOW_EN0, MASK_1b, pin, GPIO_INTR_ENABLE); return GpioOk; @@ -299,7 +296,7 @@ gpio_result_t gpio_intr_en_lvl_low (gpio_pin_number_t pin) gpio_result_t gpio_intr_dis_rise (gpio_pin_number_t pin) { if (pin > (MAX_PIN-1) || pin < 0) - return GpioError; + return GpioPinNotAcceptable; gpio_peri->INTRPT_RISE_EN0 = bitfield_write( gpio_peri->INTRPT_RISE_EN0, MASK_1b, pin, GPIO_INTR_DISABLE); return GpioOk; @@ -308,7 +305,7 @@ gpio_result_t gpio_intr_dis_rise (gpio_pin_number_t pin) gpio_result_t gpio_intr_dis_fall (gpio_pin_number_t pin) { if (pin > (MAX_PIN-1) || pin < 0) - return GpioError; + return GpioPinNotAcceptable; gpio_peri->INTRPT_FALL_EN0 = bitfield_write( gpio_peri->INTRPT_FALL_EN0, MASK_1b, pin, GPIO_INTR_DISABLE); return GpioOk; @@ -317,7 +314,7 @@ gpio_result_t gpio_intr_dis_fall (gpio_pin_number_t pin) gpio_result_t gpio_intr_dis_lvl_high (gpio_pin_number_t pin) { if (pin > (MAX_PIN-1) || pin < 0) - return GpioError; + return GpioPinNotAcceptable; gpio_peri->INTRPT_LVL_HIGH_EN0 = bitfield_write( gpio_peri->INTRPT_LVL_HIGH_EN0, MASK_1b, pin, GPIO_INTR_DISABLE); return GpioOk; @@ -326,7 +323,7 @@ gpio_result_t gpio_intr_dis_lvl_high (gpio_pin_number_t pin) gpio_result_t gpio_intr_dis_lvl_low (gpio_pin_number_t pin) { if (pin > (MAX_PIN-1) || pin < 0) - return GpioError; + return GpioPinNotAcceptable; gpio_peri->INTRPT_LVL_LOW_EN0 = bitfield_write( gpio_peri->INTRPT_LVL_LOW_EN0, MASK_1b, pin, GPIO_INTR_DISABLE); return GpioOk; @@ -334,7 +331,7 @@ gpio_result_t gpio_intr_dis_lvl_low (gpio_pin_number_t pin) gpio_result_t gpio_intr_dis_all (gpio_pin_number_t pin){ if (pin > (MAX_PIN-1) || pin < 0) - return GpioError; + return GpioPinNotAcceptable; gpio_peri->INTRPT_RISE_EN0 = bitfield_write( gpio_peri->INTRPT_RISE_EN0, MASK_1b, pin, GPIO_INTR_DISABLE); gpio_peri->INTRPT_FALL_EN0 = bitfield_write( @@ -344,13 +341,12 @@ gpio_result_t gpio_intr_dis_all (gpio_pin_number_t pin){ gpio_peri->INTRPT_LVL_LOW_EN0 = bitfield_write( gpio_peri->INTRPT_LVL_LOW_EN0, MASK_1b, pin, GPIO_INTR_DISABLE); return GpioOk; - } gpio_result_t gpio_intr_en (gpio_pin_number_t pin, gpio_intr_type_t type) { if (pin > (MAX_PIN-1) || pin < 0) - return GpioError; + return GpioPinNotAcceptable; gpio_intr_dis_all(pin); switch(type) { @@ -379,7 +375,7 @@ gpio_result_t gpio_intr_en (gpio_pin_number_t pin, gpio_intr_type_t type) gpio_intr_en_lvl_high(pin); break; default: - return GpioError; + return GpioIntrTypeNotAcceptable; } return GpioOk; } @@ -389,7 +385,7 @@ gpio_result_t gpio_intr_check_stat_rise (gpio_pin_number_t pin, bool *is_pending if (pin > (MAX_PIN-1) || pin < 0) { *is_pending = GPIO_INTR_IS_NOT_TRIGGERED; - return GpioError; + return GpioPinNotAcceptable; } if (bitfield_read(gpio_peri->INTRPT_RISE_STATUS0, MASK_1b, pin) == @@ -405,7 +401,7 @@ gpio_result_t gpio_intr_check_stat_fall (gpio_pin_number_t pin, bool *is_pending if (pin > (MAX_PIN-1) || pin < 0) { *is_pending = GPIO_INTR_IS_NOT_TRIGGERED; - return GpioError; + return GpioPinNotAcceptable; } if (bitfield_read(gpio_peri->INTRPT_FALL_STATUS0, MASK_1b, pin) == @@ -421,7 +417,7 @@ gpio_result_t gpio_intr_check_stat_lvl_low (gpio_pin_number_t pin, bool *is_pend if (pin > (MAX_PIN-1) || pin < 0) { *is_pending = GPIO_INTR_IS_NOT_TRIGGERED; - return GpioError; + return GpioPinNotAcceptable; } if (bitfield_read(gpio_peri->INTRPT_LVL_LOW_STATUS0, MASK_1b, pin) == @@ -437,7 +433,7 @@ gpio_result_t gpio_intr_check_stat_lvl_high (gpio_pin_number_t pin, bool *is_pen if (pin > (MAX_PIN-1) || pin < 0) { *is_pending = GPIO_INTR_IS_NOT_TRIGGERED; - return GpioError; + return GpioPinNotAcceptable; } if (bitfield_read(gpio_peri->INTRPT_LVL_HIGH_STATUS0, MASK_1b, pin) == @@ -453,7 +449,7 @@ gpio_result_t gpio_intr_check_stat (gpio_pin_number_t pin, bool *is_pending) if (pin > (MAX_PIN-1) || pin < 0) { *is_pending = GPIO_INTR_IS_NOT_TRIGGERED; - return GpioError; + return GpioPinNotAcceptable; } if (bitfield_read(gpio_peri->INTRPT_STATUS0, MASK_1b, pin) == @@ -467,7 +463,7 @@ gpio_result_t gpio_intr_check_stat (gpio_pin_number_t pin, bool *is_pending) gpio_result_t gpio_intr_clear_stat_rise (gpio_pin_number_t pin) { if (pin > (MAX_PIN-1) || pin < 0) - return GpioError; + return GpioPinNotAcceptable; gpio_peri->INTRPT_RISE_STATUS0 = bitfield_write( gpio_peri->INTRPT_RISE_STATUS0, MASK_1b, pin, GPIO_INTR_CLEAR); return GpioOk; @@ -477,7 +473,7 @@ gpio_result_t gpio_intr_clear_stat_rise (gpio_pin_number_t pin) gpio_result_t gpio_intr_clear_stat_fall (gpio_pin_number_t pin) { if (pin > (MAX_PIN-1) || pin < 0) - return GpioError; + return GpioPinNotAcceptable; gpio_peri->INTRPT_FALL_STATUS0 = bitfield_write( gpio_peri->INTRPT_FALL_STATUS0, MASK_1b, pin, GPIO_INTR_CLEAR); return GpioOk; @@ -486,7 +482,7 @@ gpio_result_t gpio_intr_clear_stat_fall (gpio_pin_number_t pin) gpio_result_t gpio_intr_clear_stat_lvl_low (gpio_pin_number_t pin) { if (pin > (MAX_PIN-1) || pin < 0) - return GpioError; + return GpioPinNotAcceptable; gpio_peri->INTRPT_LVL_LOW_STATUS0 = bitfield_write( gpio_peri->INTRPT_LVL_LOW_STATUS0, MASK_1b, pin, GPIO_INTR_CLEAR); return GpioOk; @@ -495,7 +491,7 @@ gpio_result_t gpio_intr_clear_stat_lvl_low (gpio_pin_number_t pin) gpio_result_t gpio_intr_clear_stat_lvl_high (gpio_pin_number_t pin) { if (pin > (MAX_PIN-1) || pin < 0) - return GpioError; + return GpioPinNotAcceptable; gpio_peri->INTRPT_LVL_HIGH_STATUS0 = bitfield_write( gpio_peri->INTRPT_LVL_HIGH_STATUS0, MASK_1b, pin, GPIO_INTR_CLEAR); return GpioOk; @@ -504,17 +500,16 @@ gpio_result_t gpio_intr_clear_stat_lvl_high (gpio_pin_number_t pin) gpio_result_t gpio_intr_clear_stat (gpio_pin_number_t pin) { if (pin > (MAX_PIN-1) || pin < 0) - return GpioError; + return GpioPinNotAcceptable; gpio_peri->INTRPT_STATUS0 = bitfield_write( gpio_peri->INTRPT_STATUS0, MASK_1b, pin, GPIO_INTR_CLEAR); return GpioOk; } -gpio_result_t gpio_intr_set_mode (gpio_intr_general_mode_t mode) +void gpio_intr_set_mode (gpio_intr_general_mode_t mode) { gpio_peri->CFG = bitfield_write( gpio_peri->CFG, MASK_1b, GPIO_CFG_INTR_MODE_INDEX, mode); - return GpioOk; } /****************************************************************************/ /** **/ diff --git a/sw/device/lib/drivers/gpio/gpio.h b/sw/device/lib/drivers/gpio/gpio.h index 90e0309bf..abd81c6de 100644 --- a/sw/device/lib/drivers/gpio/gpio.h +++ b/sw/device/lib/drivers/gpio/gpio.h @@ -80,8 +80,6 @@ typedef enum gpio_intr_general_mode new interrupt. */ } gpio_intr_general_mode_t; - - /** * This type is used in almost all the operations, and it is returned when * there is a problem with functions given parameters or operation for example @@ -91,6 +89,11 @@ typedef enum gpio_result { GpioOk = 0, /*!< The operation was ok. */ GpioError = 1, /*!< There is a problem. */ + GpioPinNotAcceptable = 2, /*!< Given pin is not inside of acceptable range. */ + GpioModeNotAcceptable = 3, /*!< Given pin mode is not one of the defined modes + in gpio_mode_t. */ + GpioIntrTypeNotAcceptable = 4, /*!< Given interrupt type is not one of the + defined types in gpio_intr_type_t. */ } gpio_result_t; /** @@ -122,16 +125,12 @@ typedef struct gpio_cfg gpio_intr_type_t intr_type; /*!< intr type (enabling intr is req). */ } gpio_cfg_t; - - - /****************************************************************************/ /** **/ /** TYPEDEFS AND STRUCTURES **/ /** **/ /****************************************************************************/ - /****************************************************************************/ /** **/ /** EXPORTED VARIABLES **/ @@ -361,11 +360,7 @@ gpio_result_t gpio_intr_clear_stat (gpio_pin_number_t pin); * interrupts for all GPIOs are cleared. If false, generate one cycle wide * pulses for every new interrupt. */ -gpio_result_t gpio_intr_set_mode (gpio_intr_general_mode_t mode); - - - - +void gpio_intr_set_mode (gpio_intr_general_mode_t mode); /****************************************************************************/ /** **/ From 4583c7cd5cc2845531fbf92b20d3018826adf32b Mon Sep 17 00:00:00 2001 From: Taji Hossein Date: Mon, 8 May 2023 18:56:22 +0200 Subject: [PATCH 18/22] some minor modifications --- sw/device/lib/drivers/gpio/gpio.c | 93 ++++++++++++++----------------- 1 file changed, 43 insertions(+), 50 deletions(-) diff --git a/sw/device/lib/drivers/gpio/gpio.c b/sw/device/lib/drivers/gpio/gpio.c index 43c26f66c..e2684ab87 100644 --- a/sw/device/lib/drivers/gpio/gpio.c +++ b/sw/device/lib/drivers/gpio/gpio.c @@ -42,12 +42,6 @@ /** **/ /****************************************************************************/ -/** - * Mask for different bit field width - */ -#define MASK_1b 0b1 -#define MASK_2b 0b11 - /** * GPIO_EN values */ @@ -57,10 +51,8 @@ /** * GPIO_CLEAR and GPIO_SET putting and removing mask */ -#define GPIO_CLEAR__PUT_MASK 1 -#define GPIO_CLEAR__REMOVE_MASK 0 -#define GPIO_SET__PUT_MASK 1 -#define GPIO_SET__REMOVE_MASK 0 +#define GPIO_PUT_MASK 0x01 +#define GPIO_REMOVE_MASK 0x00 /** * GPIO is set or reset. The value read from gpio_peri->GPIO_IN0 or @@ -149,13 +141,13 @@ gpio_result_t gpio_set_mode (gpio_pin_number_t pin, gpio_mode_t mode) if (pin >= 0 && pin < 16) { gpio_peri->GPIO_MODE0 = bitfield_write(gpio_peri->GPIO_MODE0, - MASK_2b, 2*pin, mode); + BIT_MASK_3, 2*pin, mode); return GpioOk; } else if (pin >= 16 && pin GPIO_MODE1 = bitfield_write(gpio_peri->GPIO_MODE1, - MASK_2b, 2*(pin-16), mode); + BIT_MASK_3, 2*(pin-16), mode); return GpioOk; } else @@ -169,7 +161,7 @@ gpio_result_t gpio_en_input_sampling (gpio_pin_number_t pin) if (pin > (MAX_PIN-1) || pin < 0) return GpioPinNotAcceptable; gpio_peri->GPIO_EN0 = bitfield_write(gpio_peri->GPIO_EN0, - MASK_1b, pin, GPIO_EN__ENABLED); + BIT_MASK_1, pin, GPIO_EN__ENABLED); return GpioOk; } @@ -178,7 +170,7 @@ gpio_result_t gpio_dis_input_sampling (gpio_pin_number_t pin) if (pin > (MAX_PIN-1) || pin < 0) return GpioPinNotAcceptable; gpio_peri->GPIO_EN0 = bitfield_write(gpio_peri->GPIO_EN0, - MASK_1b, pin, GPIO_EN__DISABLED); + BIT_MASK_1, pin, GPIO_EN__DISABLED); return GpioOk; } @@ -191,9 +183,9 @@ gpio_result_t gpio_reset (gpio_pin_number_t pin) gpio_set_mode (pin, GpioModeIn); gpio_dis_input_sampling (pin); gpio_peri->GPIO_CLEAR0 = bitfield_write(gpio_peri->GPIO_CLEAR0, - MASK_1b, pin, GPIO_CLEAR__REMOVE_MASK); + BIT_MASK_1, pin, GPIO_REMOVE_MASK); gpio_peri->GPIO_SET0 = bitfield_write(gpio_peri->GPIO_SET0, - MASK_1b, pin, GPIO_SET__REMOVE_MASK); + BIT_MASK_1, pin, GPIO_REMOVE_MASK); gpio_intr_dis_all(pin); gpio_intr_clear_stat(pin); return GpioOk; @@ -218,27 +210,26 @@ gpio_result_t gpio_read (gpio_pin_number_t pin, bool *val) { if (pin > (MAX_PIN-1) || pin < 0) return GpioPinNotAcceptable; - if (bitfield_read(gpio_peri->GPIO_IN0, MASK_1b, pin) == GPIO_IS_SET) + if (bitfield_read(gpio_peri->GPIO_IN0, BIT_MASK_1, pin) == GPIO_IS_SET) *val = true; else *val = false; return GpioOk; } -//todo: check it gpio_result_t gpio_toggle (gpio_pin_number_t pin) { if (pin > (MAX_PIN-1) || pin < 0) return GpioPinNotAcceptable; - if (bitfield_read(gpio_peri->GPIO_OUT0, MASK_1b, pin) == GPIO_IS_SET) + if (bitfield_read(gpio_peri->GPIO_OUT0, BIT_MASK_1, pin) == GPIO_IS_SET) { gpio_peri->GPIO_OUT0 = bitfield_write(gpio_peri->GPIO_OUT0, - MASK_1b, pin, GPIO_IS_RESET); + BIT_MASK_1, pin, GPIO_IS_RESET); } else { gpio_peri->GPIO_OUT0 = bitfield_write(gpio_peri->GPIO_OUT0, - MASK_1b, pin, GPIO_IS_SET); + BIT_MASK_1, pin, GPIO_IS_SET); } return GpioOk; } @@ -247,12 +238,14 @@ gpio_result_t gpio_write (gpio_pin_number_t pin, bool val) { if (pin > (MAX_PIN-1) || pin < 0) return GpioPinNotAcceptable; - if (val == GPIO_IS_SET) - gpio_peri->GPIO_OUT0 = bitfield_write(gpio_peri->GPIO_OUT0, - MASK_1b, pin, GPIO_IS_SET); - else - gpio_peri->GPIO_OUT0 = bitfield_write(gpio_peri->GPIO_OUT0, - MASK_1b, pin, GPIO_IS_RESET); + // if (val == GPIO_IS_SET) + // gpio_peri->GPIO_OUT0 = bitfield_write(gpio_peri->GPIO_OUT0, + // BIT_MASK_1, pin, GPIO_IS_SET); + // else + // gpio_peri->GPIO_OUT0 = bitfield_write(gpio_peri->GPIO_OUT0, + // BIT_MASK_1, pin, GPIO_IS_RESET); + gpio_peri->GPIO_OUT0 = bitfield_write(gpio_peri->GPIO_OUT0, + BIT_MASK_1, pin, val); return GpioOk; } @@ -262,7 +255,7 @@ gpio_result_t gpio_intr_en_rise (gpio_pin_number_t pin) if (pin > (MAX_PIN-1) || pin < 0) return GpioPinNotAcceptable; gpio_peri->INTRPT_RISE_EN0 = bitfield_write( - gpio_peri->INTRPT_RISE_EN0, MASK_1b, pin, GPIO_INTR_ENABLE); + gpio_peri->INTRPT_RISE_EN0, BIT_MASK_1, pin, GPIO_INTR_ENABLE); return GpioOk; } @@ -271,7 +264,7 @@ gpio_result_t gpio_intr_en_fall (gpio_pin_number_t pin) if (pin > (MAX_PIN-1) || pin < 0) return GpioPinNotAcceptable; gpio_peri->INTRPT_FALL_EN0 = bitfield_write(gpio_peri->INTRPT_FALL_EN0, - MASK_1b, pin, GPIO_INTR_ENABLE); + BIT_MASK_1, pin, GPIO_INTR_ENABLE); return GpioOk; } @@ -280,7 +273,7 @@ gpio_result_t gpio_intr_en_lvl_high (gpio_pin_number_t pin) if (pin > (MAX_PIN-1) || pin < 0) return GpioPinNotAcceptable; gpio_peri->INTRPT_LVL_HIGH_EN0 = bitfield_write( - gpio_peri->INTRPT_LVL_HIGH_EN0, MASK_1b, pin, GPIO_INTR_ENABLE); + gpio_peri->INTRPT_LVL_HIGH_EN0, BIT_MASK_1, pin, GPIO_INTR_ENABLE); return GpioOk; } @@ -289,7 +282,7 @@ gpio_result_t gpio_intr_en_lvl_low (gpio_pin_number_t pin) if (pin > (MAX_PIN-1) || pin < 0) return GpioPinNotAcceptable; gpio_peri->INTRPT_LVL_LOW_EN0 = bitfield_write( - gpio_peri->INTRPT_LVL_LOW_EN0, MASK_1b, pin, GPIO_INTR_ENABLE); + gpio_peri->INTRPT_LVL_LOW_EN0, BIT_MASK_1, pin, GPIO_INTR_ENABLE); return GpioOk; } @@ -298,7 +291,7 @@ gpio_result_t gpio_intr_dis_rise (gpio_pin_number_t pin) if (pin > (MAX_PIN-1) || pin < 0) return GpioPinNotAcceptable; gpio_peri->INTRPT_RISE_EN0 = bitfield_write( - gpio_peri->INTRPT_RISE_EN0, MASK_1b, pin, GPIO_INTR_DISABLE); + gpio_peri->INTRPT_RISE_EN0, BIT_MASK_1, pin, GPIO_INTR_DISABLE); return GpioOk; } @@ -307,7 +300,7 @@ gpio_result_t gpio_intr_dis_fall (gpio_pin_number_t pin) if (pin > (MAX_PIN-1) || pin < 0) return GpioPinNotAcceptable; gpio_peri->INTRPT_FALL_EN0 = bitfield_write( - gpio_peri->INTRPT_FALL_EN0, MASK_1b, pin, GPIO_INTR_DISABLE); + gpio_peri->INTRPT_FALL_EN0, BIT_MASK_1, pin, GPIO_INTR_DISABLE); return GpioOk; } @@ -316,7 +309,7 @@ gpio_result_t gpio_intr_dis_lvl_high (gpio_pin_number_t pin) if (pin > (MAX_PIN-1) || pin < 0) return GpioPinNotAcceptable; gpio_peri->INTRPT_LVL_HIGH_EN0 = bitfield_write( - gpio_peri->INTRPT_LVL_HIGH_EN0, MASK_1b, pin, GPIO_INTR_DISABLE); + gpio_peri->INTRPT_LVL_HIGH_EN0, BIT_MASK_1, pin, GPIO_INTR_DISABLE); return GpioOk; } @@ -325,7 +318,7 @@ gpio_result_t gpio_intr_dis_lvl_low (gpio_pin_number_t pin) if (pin > (MAX_PIN-1) || pin < 0) return GpioPinNotAcceptable; gpio_peri->INTRPT_LVL_LOW_EN0 = bitfield_write( - gpio_peri->INTRPT_LVL_LOW_EN0, MASK_1b, pin, GPIO_INTR_DISABLE); + gpio_peri->INTRPT_LVL_LOW_EN0, BIT_MASK_1, pin, GPIO_INTR_DISABLE); return GpioOk; } @@ -333,13 +326,13 @@ gpio_result_t gpio_intr_dis_all (gpio_pin_number_t pin){ if (pin > (MAX_PIN-1) || pin < 0) return GpioPinNotAcceptable; gpio_peri->INTRPT_RISE_EN0 = bitfield_write( - gpio_peri->INTRPT_RISE_EN0, MASK_1b, pin, GPIO_INTR_DISABLE); + gpio_peri->INTRPT_RISE_EN0, BIT_MASK_1, pin, GPIO_INTR_DISABLE); gpio_peri->INTRPT_FALL_EN0 = bitfield_write( - gpio_peri->INTRPT_FALL_EN0, MASK_1b, pin, GPIO_INTR_DISABLE); + gpio_peri->INTRPT_FALL_EN0, BIT_MASK_1, pin, GPIO_INTR_DISABLE); gpio_peri->INTRPT_LVL_HIGH_EN0 = bitfield_write( - gpio_peri->INTRPT_LVL_HIGH_EN0, MASK_1b, pin, GPIO_INTR_DISABLE); + gpio_peri->INTRPT_LVL_HIGH_EN0, BIT_MASK_1, pin, GPIO_INTR_DISABLE); gpio_peri->INTRPT_LVL_LOW_EN0 = bitfield_write( - gpio_peri->INTRPT_LVL_LOW_EN0, MASK_1b, pin, GPIO_INTR_DISABLE); + gpio_peri->INTRPT_LVL_LOW_EN0, BIT_MASK_1, pin, GPIO_INTR_DISABLE); return GpioOk; } @@ -388,7 +381,7 @@ gpio_result_t gpio_intr_check_stat_rise (gpio_pin_number_t pin, bool *is_pending return GpioPinNotAcceptable; } - if (bitfield_read(gpio_peri->INTRPT_RISE_STATUS0, MASK_1b, pin) == + if (bitfield_read(gpio_peri->INTRPT_RISE_STATUS0, BIT_MASK_1, pin) == GPIO_INTR_IS_TRIGGERED) *is_pending = GPIO_INTR_IS_TRIGGERED; else @@ -404,7 +397,7 @@ gpio_result_t gpio_intr_check_stat_fall (gpio_pin_number_t pin, bool *is_pending return GpioPinNotAcceptable; } - if (bitfield_read(gpio_peri->INTRPT_FALL_STATUS0, MASK_1b, pin) == + if (bitfield_read(gpio_peri->INTRPT_FALL_STATUS0, BIT_MASK_1, pin) == GPIO_INTR_IS_TRIGGERED) *is_pending = GPIO_INTR_IS_TRIGGERED; else @@ -420,7 +413,7 @@ gpio_result_t gpio_intr_check_stat_lvl_low (gpio_pin_number_t pin, bool *is_pend return GpioPinNotAcceptable; } - if (bitfield_read(gpio_peri->INTRPT_LVL_LOW_STATUS0, MASK_1b, pin) == + if (bitfield_read(gpio_peri->INTRPT_LVL_LOW_STATUS0, BIT_MASK_1, pin) == GPIO_INTR_IS_TRIGGERED) *is_pending = GPIO_INTR_IS_TRIGGERED; else @@ -436,7 +429,7 @@ gpio_result_t gpio_intr_check_stat_lvl_high (gpio_pin_number_t pin, bool *is_pen return GpioPinNotAcceptable; } - if (bitfield_read(gpio_peri->INTRPT_LVL_HIGH_STATUS0, MASK_1b, pin) == + if (bitfield_read(gpio_peri->INTRPT_LVL_HIGH_STATUS0, BIT_MASK_1, pin) == GPIO_INTR_IS_TRIGGERED) *is_pending = GPIO_INTR_IS_TRIGGERED; else @@ -452,7 +445,7 @@ gpio_result_t gpio_intr_check_stat (gpio_pin_number_t pin, bool *is_pending) return GpioPinNotAcceptable; } - if (bitfield_read(gpio_peri->INTRPT_STATUS0, MASK_1b, pin) == + if (bitfield_read(gpio_peri->INTRPT_STATUS0, BIT_MASK_1, pin) == GPIO_INTR_IS_TRIGGERED) *is_pending = GPIO_INTR_IS_TRIGGERED; else @@ -465,7 +458,7 @@ gpio_result_t gpio_intr_clear_stat_rise (gpio_pin_number_t pin) if (pin > (MAX_PIN-1) || pin < 0) return GpioPinNotAcceptable; gpio_peri->INTRPT_RISE_STATUS0 = bitfield_write( - gpio_peri->INTRPT_RISE_STATUS0, MASK_1b, pin, GPIO_INTR_CLEAR); + gpio_peri->INTRPT_RISE_STATUS0, BIT_MASK_1, pin, GPIO_INTR_CLEAR); return GpioOk; } @@ -475,7 +468,7 @@ gpio_result_t gpio_intr_clear_stat_fall (gpio_pin_number_t pin) if (pin > (MAX_PIN-1) || pin < 0) return GpioPinNotAcceptable; gpio_peri->INTRPT_FALL_STATUS0 = bitfield_write( - gpio_peri->INTRPT_FALL_STATUS0, MASK_1b, pin, GPIO_INTR_CLEAR); + gpio_peri->INTRPT_FALL_STATUS0, BIT_MASK_1, pin, GPIO_INTR_CLEAR); return GpioOk; } @@ -484,7 +477,7 @@ gpio_result_t gpio_intr_clear_stat_lvl_low (gpio_pin_number_t pin) if (pin > (MAX_PIN-1) || pin < 0) return GpioPinNotAcceptable; gpio_peri->INTRPT_LVL_LOW_STATUS0 = bitfield_write( - gpio_peri->INTRPT_LVL_LOW_STATUS0, MASK_1b, pin, GPIO_INTR_CLEAR); + gpio_peri->INTRPT_LVL_LOW_STATUS0, BIT_MASK_1, pin, GPIO_INTR_CLEAR); return GpioOk; } @@ -493,7 +486,7 @@ gpio_result_t gpio_intr_clear_stat_lvl_high (gpio_pin_number_t pin) if (pin > (MAX_PIN-1) || pin < 0) return GpioPinNotAcceptable; gpio_peri->INTRPT_LVL_HIGH_STATUS0 = bitfield_write( - gpio_peri->INTRPT_LVL_HIGH_STATUS0, MASK_1b, pin, GPIO_INTR_CLEAR); + gpio_peri->INTRPT_LVL_HIGH_STATUS0, BIT_MASK_1, pin, GPIO_INTR_CLEAR); return GpioOk; } @@ -502,14 +495,14 @@ gpio_result_t gpio_intr_clear_stat (gpio_pin_number_t pin) if (pin > (MAX_PIN-1) || pin < 0) return GpioPinNotAcceptable; gpio_peri->INTRPT_STATUS0 = bitfield_write( - gpio_peri->INTRPT_STATUS0, MASK_1b, pin, GPIO_INTR_CLEAR); + gpio_peri->INTRPT_STATUS0, BIT_MASK_1, pin, GPIO_INTR_CLEAR); return GpioOk; } void gpio_intr_set_mode (gpio_intr_general_mode_t mode) { gpio_peri->CFG = bitfield_write( - gpio_peri->CFG, MASK_1b, GPIO_CFG_INTR_MODE_INDEX, mode); + gpio_peri->CFG, BIT_MASK_1, GPIO_CFG_INTR_MODE_INDEX, mode); } /****************************************************************************/ /** **/ From 8f060ab06e9566de1b3ac000b0fa20fd311979a5 Mon Sep 17 00:00:00 2001 From: Taji Hossein Date: Fri, 26 May 2023 12:02:43 +0200 Subject: [PATCH 19/22] trim code --- sw/applications/example_gpio_cnt/main.c | 10 +++ sw/device/lib/drivers/gpio/gpio.c | 83 ++++++------------------- sw/device/target/sim/x-heep.h | 6 ++ 3 files changed, 36 insertions(+), 63 deletions(-) diff --git a/sw/applications/example_gpio_cnt/main.c b/sw/applications/example_gpio_cnt/main.c index be7e3dec1..851b78820 100644 --- a/sw/applications/example_gpio_cnt/main.c +++ b/sw/applications/example_gpio_cnt/main.c @@ -120,6 +120,16 @@ int main(int argc, char *argv[]) return -1; } + /* gpio toggle test. connect gpio in and out.*/ + // bool rd_val = false; + // gpio_res = gpio_write(GPIO_TB_OUT, true); + // while(1){ + // gpio_toggle (GPIO_TB_OUT); + // gpio_read (GPIO_TB_IN, &rd_val); + // printf("input val: %d\r\n", rd_val); + // for( uint32_t i; i < UINT_MAX; i++ ){ asm("nop"); } + // } + printf("Write 1 to GPIO 30 and wait for interrupt...\n"); while(plic_intr_flag==0) { gpio_res = gpio_write(GPIO_TB_OUT, true); diff --git a/sw/device/lib/drivers/gpio/gpio.c b/sw/device/lib/drivers/gpio/gpio.c index e2684ab87..f3a50f9c0 100644 --- a/sw/device/lib/drivers/gpio/gpio.c +++ b/sw/device/lib/drivers/gpio/gpio.c @@ -84,6 +84,11 @@ */ #define GPIO_CFG_INTR_MODE_INDEX 0 +/** + * GPIO mode, number of pins it includes + */ +#define GPIO_MODE_NUM_PINS 16 + /****************************************************************************/ /** **/ @@ -138,22 +143,16 @@ gpio_result_t gpio_config (gpio_cfg_t cfg){ gpio_result_t gpio_set_mode (gpio_pin_number_t pin, gpio_mode_t mode) { - if (pin >= 0 && pin < 16) - { + if (pin < 0 && pin > (MAX_PIN-1)) + return GpioModeNotAcceptable; + + if (pin >= 0 && pin < 1*GPIO_MODE_NUM_PINS) gpio_peri->GPIO_MODE0 = bitfield_write(gpio_peri->GPIO_MODE0, BIT_MASK_3, 2*pin, mode); - return GpioOk; - } - else if (pin >= 16 && pin GPIO_MODE1 = bitfield_write(gpio_peri->GPIO_MODE1, - BIT_MASK_3, 2*(pin-16), mode); - return GpioOk; - } - else - { - return GpioModeNotAcceptable; - } + BIT_MASK_3, 2*(pin-GPIO_MODE_NUM_PINS), mode); + return GpioOk; } gpio_result_t gpio_en_input_sampling (gpio_pin_number_t pin) @@ -210,10 +209,7 @@ gpio_result_t gpio_read (gpio_pin_number_t pin, bool *val) { if (pin > (MAX_PIN-1) || pin < 0) return GpioPinNotAcceptable; - if (bitfield_read(gpio_peri->GPIO_IN0, BIT_MASK_1, pin) == GPIO_IS_SET) - *val = true; - else - *val = false; + *val = bitfield_read(gpio_peri->GPIO_IN0, BIT_MASK_1, pin); return GpioOk; } @@ -221,16 +217,8 @@ gpio_result_t gpio_toggle (gpio_pin_number_t pin) { if (pin > (MAX_PIN-1) || pin < 0) return GpioPinNotAcceptable; - if (bitfield_read(gpio_peri->GPIO_OUT0, BIT_MASK_1, pin) == GPIO_IS_SET) - { - gpio_peri->GPIO_OUT0 = bitfield_write(gpio_peri->GPIO_OUT0, - BIT_MASK_1, pin, GPIO_IS_RESET); - } - else - { - gpio_peri->GPIO_OUT0 = bitfield_write(gpio_peri->GPIO_OUT0, - BIT_MASK_1, pin, GPIO_IS_SET); - } + gpio_peri->GPIO_OUT0 = bitfield_write(gpio_peri->GPIO_OUT0, BIT_MASK_1, + pin, !(bitfield_read(gpio_peri->GPIO_OUT0, BIT_MASK_1, pin))); return GpioOk; } @@ -238,12 +226,6 @@ gpio_result_t gpio_write (gpio_pin_number_t pin, bool val) { if (pin > (MAX_PIN-1) || pin < 0) return GpioPinNotAcceptable; - // if (val == GPIO_IS_SET) - // gpio_peri->GPIO_OUT0 = bitfield_write(gpio_peri->GPIO_OUT0, - // BIT_MASK_1, pin, GPIO_IS_SET); - // else - // gpio_peri->GPIO_OUT0 = bitfield_write(gpio_peri->GPIO_OUT0, - // BIT_MASK_1, pin, GPIO_IS_RESET); gpio_peri->GPIO_OUT0 = bitfield_write(gpio_peri->GPIO_OUT0, BIT_MASK_1, pin, val); return GpioOk; @@ -380,12 +362,7 @@ gpio_result_t gpio_intr_check_stat_rise (gpio_pin_number_t pin, bool *is_pending *is_pending = GPIO_INTR_IS_NOT_TRIGGERED; return GpioPinNotAcceptable; } - - if (bitfield_read(gpio_peri->INTRPT_RISE_STATUS0, BIT_MASK_1, pin) == - GPIO_INTR_IS_TRIGGERED) - *is_pending = GPIO_INTR_IS_TRIGGERED; - else - *is_pending = GPIO_INTR_IS_NOT_TRIGGERED; + *is_pending = bitfield_read(gpio_peri->INTRPT_RISE_STATUS0, BIT_MASK_1, pin); return GpioOk; } @@ -396,12 +373,7 @@ gpio_result_t gpio_intr_check_stat_fall (gpio_pin_number_t pin, bool *is_pending *is_pending = GPIO_INTR_IS_NOT_TRIGGERED; return GpioPinNotAcceptable; } - - if (bitfield_read(gpio_peri->INTRPT_FALL_STATUS0, BIT_MASK_1, pin) == - GPIO_INTR_IS_TRIGGERED) - *is_pending = GPIO_INTR_IS_TRIGGERED; - else - *is_pending = GPIO_INTR_IS_NOT_TRIGGERED; + *is_pending = bitfield_read(gpio_peri->INTRPT_FALL_STATUS0, BIT_MASK_1, pin); return GpioOk; } @@ -412,12 +384,7 @@ gpio_result_t gpio_intr_check_stat_lvl_low (gpio_pin_number_t pin, bool *is_pend *is_pending = GPIO_INTR_IS_NOT_TRIGGERED; return GpioPinNotAcceptable; } - - if (bitfield_read(gpio_peri->INTRPT_LVL_LOW_STATUS0, BIT_MASK_1, pin) == - GPIO_INTR_IS_TRIGGERED) - *is_pending = GPIO_INTR_IS_TRIGGERED; - else - *is_pending = GPIO_INTR_IS_NOT_TRIGGERED; + *is_pending = bitfield_read(gpio_peri->INTRPT_LVL_LOW_STATUS0, BIT_MASK_1, pin); return GpioOk; } @@ -428,12 +395,7 @@ gpio_result_t gpio_intr_check_stat_lvl_high (gpio_pin_number_t pin, bool *is_pen *is_pending = GPIO_INTR_IS_NOT_TRIGGERED; return GpioPinNotAcceptable; } - - if (bitfield_read(gpio_peri->INTRPT_LVL_HIGH_STATUS0, BIT_MASK_1, pin) == - GPIO_INTR_IS_TRIGGERED) - *is_pending = GPIO_INTR_IS_TRIGGERED; - else - *is_pending = GPIO_INTR_IS_NOT_TRIGGERED; + *is_pending = bitfield_read(gpio_peri->INTRPT_LVL_HIGH_STATUS0, BIT_MASK_1, pin); return GpioOk; } @@ -444,12 +406,7 @@ gpio_result_t gpio_intr_check_stat (gpio_pin_number_t pin, bool *is_pending) *is_pending = GPIO_INTR_IS_NOT_TRIGGERED; return GpioPinNotAcceptable; } - - if (bitfield_read(gpio_peri->INTRPT_STATUS0, BIT_MASK_1, pin) == - GPIO_INTR_IS_TRIGGERED) - *is_pending = GPIO_INTR_IS_TRIGGERED; - else - *is_pending = GPIO_INTR_IS_NOT_TRIGGERED; + *is_pending = bitfield_read(gpio_peri->INTRPT_STATUS0, BIT_MASK_1, pin); return GpioOk; } diff --git a/sw/device/target/sim/x-heep.h b/sw/device/target/sim/x-heep.h index 59921e29f..4e18db182 100644 --- a/sw/device/target/sim/x-heep.h +++ b/sw/device/target/sim/x-heep.h @@ -16,6 +16,12 @@ extern "C" { #define UART_BAUDRATE 256000 #define TARGET_SIM +/** + * As the hw is configurable, we can have setups with different number of + * Gpio pins + */ +#define MAX_PIN 32 + #ifdef __cplusplus } // extern "C" From 85cc508a4ac23daed3b6e14749b442825d81b01d Mon Sep 17 00:00:00 2001 From: Taji Hossein Date: Fri, 26 May 2023 12:57:00 +0200 Subject: [PATCH 20/22] blinky_freertos bug --- sw/applications/blinky_freertos/main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sw/applications/blinky_freertos/main.c b/sw/applications/blinky_freertos/main.c index 80d092b48..1659e351b 100644 --- a/sw/applications/blinky_freertos/main.c +++ b/sw/applications/blinky_freertos/main.c @@ -259,7 +259,7 @@ void system_init(void) gpio_res |= gpio_config(pin_cfg); pin_cfg.pin = GPIO_LD5_G; gpio_res |= gpio_config(pin_cfg); - if (gpio_res != kGpioOk) printf("Failed\n;"); + if (gpio_res != GpioOk) printf("Failed\n;"); gpio_write(GPIO_LD5_R, false); gpio_write(GPIO_LD5_B, false); From a0a4861ab6c5c11b8f3ebe65a27686fe2652b1b5 Mon Sep 17 00:00:00 2001 From: Juan Sapriza Date: Thu, 29 Jun 2023 11:55:17 +0200 Subject: [PATCH 21/22] Updated the GPIOS being used for the LED5 --- sw/applications/example_freertos_blinky/main.c | 6 +++--- tb/ext_bus.sv | 5 ++--- 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/sw/applications/example_freertos_blinky/main.c b/sw/applications/example_freertos_blinky/main.c index 1659e351b..fbb9941f4 100644 --- a/sw/applications/example_freertos_blinky/main.c +++ b/sw/applications/example_freertos_blinky/main.c @@ -149,9 +149,9 @@ or 0 to run the more comprehensive test and demo application. */ #ifdef TARGET_PYNQ_Z2 - #define GPIO_LD5_R 20 - #define GPIO_LD5_B 21 - #define GPIO_LD5_G 22 + #define GPIO_LD5_R 15 + #define GPIO_LD5_B 16 + #define GPIO_LD5_G 17 #pragma message ( "Executing FreeRTOS using X-HEEP and Pynq-z2" ) #else #define GPIO_LD5_R 29 diff --git a/tb/ext_bus.sv b/tb/ext_bus.sv index d0001514f..74755de30 100644 --- a/tb/ext_bus.sv +++ b/tb/ext_bus.sv @@ -122,9 +122,8 @@ module ext_bus #( // show writes if requested always_ff @(posedge clk_i, negedge rst_ni) begin : verbose_writes if ($test$plusargs("verbose") != 0 && heep_core_data_req_i.req && heep_core_data_req_i.we) - $display( - "write addr=0x%08x: data=0x%08x", heep_core_data_req_i.addr, heep_core_data_req_i.wdata - ); + $display("write addr=0x%08x: data=0x%08x", heep_core_data_req_i.addr, + heep_core_data_req_i.wdata); end `endif From 2cd850e753efbc09085afa76368c970850e9dae4 Mon Sep 17 00:00:00 2001 From: Juan Sapriza Date: Mon, 10 Jul 2023 16:42:45 +0200 Subject: [PATCH 22/22] removed unnecessary comments --- sw/device/lib/drivers/gpio/gpio.c | 79 ++++++------------- sw/device/lib/drivers/gpio/gpio.h | 125 ++++++++++-------------------- 2 files changed, 67 insertions(+), 137 deletions(-) diff --git a/sw/device/lib/drivers/gpio/gpio.c b/sw/device/lib/drivers/gpio/gpio.c index f3a50f9c0..80e051d20 100644 --- a/sw/device/lib/drivers/gpio/gpio.c +++ b/sw/device/lib/drivers/gpio/gpio.c @@ -1,16 +1,16 @@ /* ******************* ******************************* C SOURCE FILE ***************************** -** ******************* -** -** project : X-HEEP -** filename : gpio.c -** +** ******************* +** +** project : X-HEEP +** filename : gpio.c +** *************************************************************************** -** -** Copyright (c) EPFL contributors. -** All rights reserved. -** +** +** Copyright (c) EPFL contributors. +** All rights reserved. +** *************************************************************************** */ @@ -21,7 +21,7 @@ * @date 30/03/2023 * @author Hossein taji * @version 1 -* @brief GPIO driver +* @brief GPIO driver */ /****************************************************************************/ @@ -43,7 +43,7 @@ /****************************************************************************/ /** - * GPIO_EN values + * GPIO_EN values */ #define GPIO_EN__ENABLED 1 #define GPIO_EN__DISABLED 0 @@ -68,7 +68,7 @@ #define GPIO_INTR_DISABLE 0 /** - * Values read after checking intr status registers to see they are + * Values read after checking intr status registers to see they are * triggered or not */ #define GPIO_INTR_IS_TRIGGERED 1 @@ -89,31 +89,6 @@ */ #define GPIO_MODE_NUM_PINS 16 - -/****************************************************************************/ -/** **/ -/* TYPEDEFS AND STRUCTURES */ -/** **/ -/****************************************************************************/ - -/****************************************************************************/ -/** **/ -/* PROTOTYPES OF LOCAL FUNCTIONS */ -/** **/ -/****************************************************************************/ - -/****************************************************************************/ -/** **/ -/* EXPORTED VARIABLES */ -/** **/ -/****************************************************************************/ - -/****************************************************************************/ -/** **/ -/* GLOBAL VARIABLES */ -/** **/ -/****************************************************************************/ - /****************************************************************************/ /** **/ /* EXPORTED FUNCTIONS */ @@ -147,11 +122,11 @@ gpio_result_t gpio_set_mode (gpio_pin_number_t pin, gpio_mode_t mode) return GpioModeNotAcceptable; if (pin >= 0 && pin < 1*GPIO_MODE_NUM_PINS) - gpio_peri->GPIO_MODE0 = bitfield_write(gpio_peri->GPIO_MODE0, + gpio_peri->GPIO_MODE0 = bitfield_write(gpio_peri->GPIO_MODE0, BIT_MASK_3, 2*pin, mode); - else - gpio_peri->GPIO_MODE1 = bitfield_write(gpio_peri->GPIO_MODE1, - BIT_MASK_3, 2*(pin-GPIO_MODE_NUM_PINS), mode); + else + gpio_peri->GPIO_MODE1 = bitfield_write(gpio_peri->GPIO_MODE1, + BIT_MASK_3, 2*(pin-GPIO_MODE_NUM_PINS), mode); return GpioOk; } @@ -217,7 +192,7 @@ gpio_result_t gpio_toggle (gpio_pin_number_t pin) { if (pin > (MAX_PIN-1) || pin < 0) return GpioPinNotAcceptable; - gpio_peri->GPIO_OUT0 = bitfield_write(gpio_peri->GPIO_OUT0, BIT_MASK_1, + gpio_peri->GPIO_OUT0 = bitfield_write(gpio_peri->GPIO_OUT0, BIT_MASK_1, pin, !(bitfield_read(gpio_peri->GPIO_OUT0, BIT_MASK_1, pin))); return GpioOk; } @@ -226,7 +201,7 @@ gpio_result_t gpio_write (gpio_pin_number_t pin, bool val) { if (pin > (MAX_PIN-1) || pin < 0) return GpioPinNotAcceptable; - gpio_peri->GPIO_OUT0 = bitfield_write(gpio_peri->GPIO_OUT0, + gpio_peri->GPIO_OUT0 = bitfield_write(gpio_peri->GPIO_OUT0, BIT_MASK_1, pin, val); return GpioOk; @@ -245,7 +220,7 @@ gpio_result_t gpio_intr_en_fall (gpio_pin_number_t pin) { if (pin > (MAX_PIN-1) || pin < 0) return GpioPinNotAcceptable; - gpio_peri->INTRPT_FALL_EN0 = bitfield_write(gpio_peri->INTRPT_FALL_EN0, + gpio_peri->INTRPT_FALL_EN0 = bitfield_write(gpio_peri->INTRPT_FALL_EN0, BIT_MASK_1, pin, GPIO_INTR_ENABLE); return GpioOk; } @@ -358,7 +333,7 @@ gpio_result_t gpio_intr_en (gpio_pin_number_t pin, gpio_intr_type_t type) gpio_result_t gpio_intr_check_stat_rise (gpio_pin_number_t pin, bool *is_pending) { if (pin > (MAX_PIN-1) || pin < 0) - { + { *is_pending = GPIO_INTR_IS_NOT_TRIGGERED; return GpioPinNotAcceptable; } @@ -369,7 +344,7 @@ gpio_result_t gpio_intr_check_stat_rise (gpio_pin_number_t pin, bool *is_pending gpio_result_t gpio_intr_check_stat_fall (gpio_pin_number_t pin, bool *is_pending) { if (pin > (MAX_PIN-1) || pin < 0) - { + { *is_pending = GPIO_INTR_IS_NOT_TRIGGERED; return GpioPinNotAcceptable; } @@ -380,7 +355,7 @@ gpio_result_t gpio_intr_check_stat_fall (gpio_pin_number_t pin, bool *is_pending gpio_result_t gpio_intr_check_stat_lvl_low (gpio_pin_number_t pin, bool *is_pending) { if (pin > (MAX_PIN-1) || pin < 0) - { + { *is_pending = GPIO_INTR_IS_NOT_TRIGGERED; return GpioPinNotAcceptable; } @@ -391,7 +366,7 @@ gpio_result_t gpio_intr_check_stat_lvl_low (gpio_pin_number_t pin, bool *is_pend gpio_result_t gpio_intr_check_stat_lvl_high (gpio_pin_number_t pin, bool *is_pending) { if (pin > (MAX_PIN-1) || pin < 0) - { + { *is_pending = GPIO_INTR_IS_NOT_TRIGGERED; return GpioPinNotAcceptable; } @@ -402,7 +377,7 @@ gpio_result_t gpio_intr_check_stat_lvl_high (gpio_pin_number_t pin, bool *is_pen gpio_result_t gpio_intr_check_stat (gpio_pin_number_t pin, bool *is_pending) { if (pin > (MAX_PIN-1) || pin < 0) - { + { *is_pending = GPIO_INTR_IS_NOT_TRIGGERED; return GpioPinNotAcceptable; } @@ -461,12 +436,6 @@ void gpio_intr_set_mode (gpio_intr_general_mode_t mode) gpio_peri->CFG = bitfield_write( gpio_peri->CFG, BIT_MASK_1, GPIO_CFG_INTR_MODE_INDEX, mode); } -/****************************************************************************/ -/** **/ -/* LOCAL FUNCTIONS */ -/** **/ -/****************************************************************************/ - /****************************************************************************/ /** **/ diff --git a/sw/device/lib/drivers/gpio/gpio.h b/sw/device/lib/drivers/gpio/gpio.h index abd81c6de..8389cfe43 100644 --- a/sw/device/lib/drivers/gpio/gpio.h +++ b/sw/device/lib/drivers/gpio/gpio.h @@ -7,10 +7,10 @@ ** filename : gpio.h ** ** ** ***************************************************************************** -** -** Copyright (c) EPFL contributors. -** All rights reserved. -** +** +** Copyright (c) EPFL contributors. +** All rights reserved. +** ***************************************************************************** */ @@ -21,7 +21,7 @@ * @date 30/03/2023 * @author Hossein taji * @version 1 -* @brief GPIO driver +* @brief GPIO driver */ #ifndef GPIO_H_ @@ -44,55 +44,55 @@ /****************************************************************************/ /** - * The format use for pin number. As the gpio pins are only 32 number, + * The format use for pin number. As the gpio pins are only 32 number, * uint8_t would be enough. */ typedef uint8_t gpio_pin_number_t; /** - * gpio mode. - * 0 configure GPIO as input. 1 configures GPIO as a push-pull output. - * 2 configures the GPIO to be in open_drain0 (0 -> High-Z, 1 -> Drive High) - * mode. 3 configures the GPIO to be in open_drain1 (0 -> Drive Low, 1 -> + * gpio mode. + * 0 configure GPIO as input. 1 configures GPIO as a push-pull output. + * 2 configures the GPIO to be in open_drain0 (0 -> High-Z, 1 -> Drive High) + * mode. 3 configures the GPIO to be in open_drain1 (0 -> Drive Low, 1 -> * High-Z) mode. */ -typedef enum gpio_mode +typedef enum gpio_mode { GpioModeIn = 0, /*!< input. */ GpioModeOutPushPull = 1, /*!< push-pull output. */ - GpioModeoutOpenDrain0 = 2, /*!< open_drain0 (0->High-Z, 1->Drive High) + GpioModeoutOpenDrain0 = 2, /*!< open_drain0 (0->High-Z, 1->Drive High) mode. */ - GpioModeoutOpenDrain1 = 3, /*!< open_drain1 (0->Drive Low, 1->High-Z) + GpioModeoutOpenDrain1 = 3, /*!< open_drain1 (0->Drive Low, 1->High-Z) mode. */ } gpio_mode_t; /** - * gpio_intr_general_mode - * 1 keep the interrupt line asserted until all interrupts for all GPIOs - * are cleared. + * gpio_intr_general_mode + * 1 keep the interrupt line asserted until all interrupts for all GPIOs + * are cleared. * 0 generate one cycle wide pulses for every new interrupt. */ typedef enum gpio_intr_general_mode -{ - IntrOnePulse = 0, /*!< keep the interrupt line asserted until all +{ + IntrOnePulse = 0, /*!< keep the interrupt line asserted until all interrupts for all GPIOs are cleared. */ - IntrAsserted = 1, /*!< generate one cycle wide pulses for every + IntrAsserted = 1, /*!< generate one cycle wide pulses for every new interrupt. */ } gpio_intr_general_mode_t; /** * This type is used in almost all the operations, and it is returned when - * there is a problem with functions given parameters or operation for example + * there is a problem with functions given parameters or operation for example * pin number not being in the range of accepting pins. */ -typedef enum gpio_result +typedef enum gpio_result { GpioOk = 0, /*!< The operation was ok. */ GpioError = 1, /*!< There is a problem. */ GpioPinNotAcceptable = 2, /*!< Given pin is not inside of acceptable range. */ GpioModeNotAcceptable = 3, /*!< Given pin mode is not one of the defined modes in gpio_mode_t. */ - GpioIntrTypeNotAcceptable = 4, /*!< Given interrupt type is not one of the + GpioIntrTypeNotAcceptable = 4, /*!< Given interrupt type is not one of the defined types in gpio_intr_type_t. */ } gpio_result_t; @@ -106,9 +106,9 @@ typedef enum gpio_intr_type GpioIntrLevelLow, /*!< Trigger when input is low. */ GpioIntrLevelHigh, /*!< rigger when input is high. */ GpioIntrEdgeRisingFalling, /*!< Trigger on rising and falling edges. */ - GpioIntrEdgeRisingLevelLow, /*!< Trigger on rising edge or when the + GpioIntrEdgeRisingLevelLow, /*!< Trigger on rising edge or when the input is low. */ - GpioIntrEdgeFallingLevelHigh,/*!< Trigger on falling edge or when the + GpioIntrEdgeFallingLevelHigh,/*!< Trigger on falling edge or when the input is high. */ } gpio_intr_type_t; @@ -125,18 +125,6 @@ typedef struct gpio_cfg gpio_intr_type_t intr_type; /*!< intr type (enabling intr is req). */ } gpio_cfg_t; -/****************************************************************************/ -/** **/ -/** TYPEDEFS AND STRUCTURES **/ -/** **/ -/****************************************************************************/ - -/****************************************************************************/ -/** **/ -/** EXPORTED VARIABLES **/ -/** **/ -/****************************************************************************/ - /****************************************************************************/ /** **/ /** EXPORTED FUNCTIONS **/ @@ -144,7 +132,7 @@ typedef struct gpio_cfg /****************************************************************************/ /** - * @brief gpio configuration. It first reset the pin configuration. + * @brief gpio configuration. It first reset the pin configuration. * @param gpio_struct_t contatining pin, mode, en_input_sampling, en_intr, * intr_type * @return GpioOk: no problem, GpioError: there is an error. @@ -165,14 +153,14 @@ gpio_result_t gpio_reset_all (void); /** * @brief setting the a pins mode by writing in GPIO_MODE0 and GPIO_MODE1. * @param gpio_pin_number_t specify the pin. - * @param gpio_mode_t specify pin mode: 0 as input, 1 push-pull as output, + * @param gpio_mode_t specify pin mode: 0 as input, 1 push-pull as output, * 2 as open_drain0, and 3 as open_drain1. */ gpio_result_t gpio_set_mode (gpio_pin_number_t pin, gpio_mode_t mode); /** - * @brief enable sampling as input by writing one in GPIO_EN. If disables - * (0) the corresponding GPIO will not sample the inputs (saves power) and + * @brief enable sampling as input by writing one in GPIO_EN. If disables + * (0) the corresponding GPIO will not sample the inputs (saves power) and * will not generate any interrupts. */ gpio_result_t gpio_en_input_sampling (gpio_pin_number_t pin); @@ -189,23 +177,9 @@ gpio_result_t gpio_dis_input_sampling (gpio_pin_number_t pin); */ gpio_result_t gpio_read (gpio_pin_number_t pin, bool *val); -// /** -// * @brief set a pin as high. Using masking through GPIO_SET, and then writing -// * to GPIO_OUT -// * @param gpio_pin_number_t specify pin number -// */ -// gpio_result_t gpio_pin_set (gpio_pin_number_t pin); - -// /** -// * @brief clear a pin as low. Using masking through GPIO_CLEAR, and then -// * writing to GPIO_OUT -// * @param gpio_pin_number_t specify pin number -// */ -// gpio_result_t gpio_pin_clear (gpio_pin_number_t pin); - /** - * @brief toggle a pin. Using masking through GPIO_TOGGLE, and then - * writing to GPIO_OUT + * @brief toggle a pin. Using masking through GPIO_TOGGLE, and then + * writing to GPIO_OUT * @param gpio_pin_number_t specify pin number */ gpio_result_t gpio_toggle (gpio_pin_number_t pin); @@ -265,19 +239,13 @@ gpio_result_t gpio_intr_en_lvl_low (gpio_pin_number_t pin); gpio_result_t gpio_intr_dis_lvl_low (gpio_pin_number_t pin); /** - * @brief enable the interrupt for the given pin. Type of interrupt + * @brief enable the interrupt for the given pin. Type of interrupt * specified by user. * @param gpio_pin_number_t specify pin number * @param gpio_intr_type_t specify the type of the interrupt */ gpio_result_t gpio_intr_en (gpio_pin_number_t pin, gpio_intr_type_t type); -// /** -// * @brief disable the given type of interrupt on the given pin. -// * @param gpio_pin_number_t specify pin number -// */ -// gpio_result_t gpio_intr_dis (gpio_pin_number_t pin, gpio_intr_type_t type); - /** * @brief disable all the types of interrupt on the given pin. * @param gpio_pin_number_t specify pin number @@ -285,70 +253,70 @@ gpio_result_t gpio_intr_en (gpio_pin_number_t pin, gpio_intr_type_t type); gpio_result_t gpio_intr_dis_all (gpio_pin_number_t pin); /** - * @brief Each bit indicates if there is a pending rising-edge interrupt + * @brief Each bit indicates if there is a pending rising-edge interrupt * on the corresponding GPIO. * @param gpio_pin_number_t specify pin number */ gpio_result_t gpio_intr_check_stat_rise (gpio_pin_number_t pin, bool *is_pending); /** - * @brief Each bit indicates if there is a pending falling-edge interrupt + * @brief Each bit indicates if there is a pending falling-edge interrupt * on the corresponding GPIO. * @param gpio_pin_number_t specify pin number */ gpio_result_t gpio_intr_check_stat_fall (gpio_pin_number_t pin, bool *is_pending); /** - * @brief Each bit indicates if there is a pending low level-sensitive + * @brief Each bit indicates if there is a pending low level-sensitive * interrupt on the corresponding GPIO. * @param gpio_pin_number_t specify pin number */ gpio_result_t gpio_intr_check_stat_lvl_low (gpio_pin_number_t pin, bool *is_pending); /** - * @brief Each bit indicates if there is a pending high level-sensitive + * @brief Each bit indicates if there is a pending high level-sensitive * interrupt on the corresponding GPIO. * @param gpio_pin_number_t specify pin number */ gpio_result_t gpio_intr_check_stat_lvl_high (gpio_pin_number_t pin, bool *is_pending); /** - * @brief Each bit indicates if there is a pending interrupt on the + * @brief Each bit indicates if there is a pending interrupt on the * corresponding GPIO in any form (rise, fall, low level, and high level) * @param gpio_pin_number_t specify pin number */ gpio_result_t gpio_intr_check_stat (gpio_pin_number_t pin, bool *is_pending); /** - * @brief Clearing interrupt rise status. Writing a 1 to a specific bit + * @brief Clearing interrupt rise status. Writing a 1 to a specific bit * clears the interrupt for the corresponding GPIO. * @param gpio_pin_number_t specify pin number */ gpio_result_t gpio_intr_clear_stat_rise (gpio_pin_number_t pin); /** - * @brief Clearing interrupt fall status. Writing a 1 to a specific bit + * @brief Clearing interrupt fall status. Writing a 1 to a specific bit * clears the interrupt for the corresponding GPIO. * @param gpio_pin_number_t specify pin number */ gpio_result_t gpio_intr_clear_stat_fall (gpio_pin_number_t pin); /** - * @brief Clearing interrupt low level-sensitive status. Writing a 1 to a + * @brief Clearing interrupt low level-sensitive status. Writing a 1 to a * specific bit clears the interrupt for the corresponding GPIO. * @param gpio_pin_number_t specify pin number */ gpio_result_t gpio_intr_clear_stat_lvl_low (gpio_pin_number_t pin); /** - * @brief Clearing interrupt high level-sensitive status. Writing a 1 to a + * @brief Clearing interrupt high level-sensitive status. Writing a 1 to a * specific bit clears the interrupt for the corresponding GPIO. * @param gpio_pin_number_t specify pin number */ gpio_result_t gpio_intr_clear_stat_lvl_high (gpio_pin_number_t pin); /** - * @brief Clearing interrupt status regardless of its type. Writing a 1 to + * @brief Clearing interrupt status regardless of its type. Writing a 1 to * a specific bit clears the interrupt for the corresponding GPIO. * @param gpio_pin_number_t specify pin number */ @@ -356,19 +324,12 @@ gpio_result_t gpio_intr_clear_stat (gpio_pin_number_t pin); /** * @brief Controls the interrupt mode of the gpios. - * @gpio_intr_mode If true, keep the interrupt line asserted until all - * interrupts for all GPIOs are cleared. If false, generate one cycle wide + * @gpio_intr_mode If true, keep the interrupt line asserted until all + * interrupts for all GPIOs are cleared. If false, generate one cycle wide * pulses for every new interrupt. */ void gpio_intr_set_mode (gpio_intr_general_mode_t mode); -/****************************************************************************/ -/** **/ -/** INLINE FUNCTIONS **/ -/** **/ -/****************************************************************************/ - - #endif // _GPIO_H_ /****************************************************************************/ /** **/