diff --git a/litex/tools/simout2/gateware/dut.v b/litex/tools/simout2/gateware/dut.v
deleted file mode 100644
index e95d8549eb..0000000000
--- a/litex/tools/simout2/gateware/dut.v
+++ /dev/null
@@ -1,4788 +0,0 @@
-//--------------------------------------------------------------------------------
-// Auto-generated by Migen (57a7311) & LiteX (2be3450) on 2019-10-10 17:58:20
-//--------------------------------------------------------------------------------
-module dut(
-	input sys_clk,
-	output serial_source_valid,
-	input serial_source_ready,
-	output [7:0] serial_source_data,
-	input serial_sink_valid,
-	output serial_sink_ready,
-	input [7:0] serial_sink_data
-);
-
-wire simsoc_ctrl_reset_reset_re;
-wire simsoc_ctrl_reset_reset_r;
-wire simsoc_ctrl_reset_reset_we;
-reg simsoc_ctrl_reset_reset_w = 1'd0;
-reg [31:0] simsoc_ctrl_storage = 32'd305419896;
-reg simsoc_ctrl_re = 1'd0;
-wire [31:0] simsoc_ctrl_bus_errors_status;
-wire simsoc_ctrl_bus_errors_we;
-wire simsoc_ctrl_reset;
-wire simsoc_ctrl_bus_error;
-reg [31:0] simsoc_ctrl_bus_errors = 32'd0;
-wire simsoc_blackparrotrv64_reset;
-reg [3:0] simsoc_blackparrotrv64_interrupt = 4'd0;
-wire simsoc_blackparrotrv64_mem_axi_aw_valid;
-reg simsoc_blackparrotrv64_mem_axi_aw_ready = 1'd0;
-reg simsoc_blackparrotrv64_mem_axi_aw_first = 1'd0;
-reg simsoc_blackparrotrv64_mem_axi_aw_last = 1'd0;
-wire [31:0] simsoc_blackparrotrv64_mem_axi_aw_payload_addr;
-wire [1:0] simsoc_blackparrotrv64_mem_axi_aw_payload_burst;
-wire [7:0] simsoc_blackparrotrv64_mem_axi_aw_payload_len;
-wire [3:0] simsoc_blackparrotrv64_mem_axi_aw_payload_size;
-wire [1:0] simsoc_blackparrotrv64_mem_axi_aw_payload_lock;
-wire [2:0] simsoc_blackparrotrv64_mem_axi_aw_payload_prot;
-wire [3:0] simsoc_blackparrotrv64_mem_axi_aw_payload_cache;
-wire [3:0] simsoc_blackparrotrv64_mem_axi_aw_payload_qos;
-wire [3:0] simsoc_blackparrotrv64_mem_axi_aw_payload_id;
-wire simsoc_blackparrotrv64_mem_axi_w_valid;
-reg simsoc_blackparrotrv64_mem_axi_w_ready = 1'd0;
-wire simsoc_blackparrotrv64_mem_axi_w_last;
-wire [63:0] simsoc_blackparrotrv64_mem_axi_w_payload_data;
-wire [7:0] simsoc_blackparrotrv64_mem_axi_w_payload_strb;
-reg simsoc_blackparrotrv64_mem_axi_b_valid = 1'd0;
-wire simsoc_blackparrotrv64_mem_axi_b_ready;
-reg [1:0] simsoc_blackparrotrv64_mem_axi_b_payload_resp = 2'd0;
-reg [3:0] simsoc_blackparrotrv64_mem_axi_b_payload_id = 4'd0;
-wire simsoc_blackparrotrv64_mem_axi_ar_valid;
-reg simsoc_blackparrotrv64_mem_axi_ar_ready = 1'd0;
-reg simsoc_blackparrotrv64_mem_axi_ar_first = 1'd0;
-reg simsoc_blackparrotrv64_mem_axi_ar_last = 1'd0;
-wire [31:0] simsoc_blackparrotrv64_mem_axi_ar_payload_addr;
-wire [1:0] simsoc_blackparrotrv64_mem_axi_ar_payload_burst;
-wire [7:0] simsoc_blackparrotrv64_mem_axi_ar_payload_len;
-wire [3:0] simsoc_blackparrotrv64_mem_axi_ar_payload_size;
-wire [1:0] simsoc_blackparrotrv64_mem_axi_ar_payload_lock;
-wire [2:0] simsoc_blackparrotrv64_mem_axi_ar_payload_prot;
-wire [3:0] simsoc_blackparrotrv64_mem_axi_ar_payload_cache;
-wire [3:0] simsoc_blackparrotrv64_mem_axi_ar_payload_qos;
-wire [3:0] simsoc_blackparrotrv64_mem_axi_ar_payload_id;
-reg simsoc_blackparrotrv64_mem_axi_r_valid = 1'd0;
-wire simsoc_blackparrotrv64_mem_axi_r_ready;
-reg simsoc_blackparrotrv64_mem_axi_r_last = 1'd0;
-reg [1:0] simsoc_blackparrotrv64_mem_axi_r_payload_resp = 2'd0;
-reg [63:0] simsoc_blackparrotrv64_mem_axi_r_payload_data = 64'd0;
-reg [3:0] simsoc_blackparrotrv64_mem_axi_r_payload_id = 4'd0;
-wire simsoc_blackparrotrv64_mmio_axi_aw_valid;
-reg simsoc_blackparrotrv64_mmio_axi_aw_ready = 1'd0;
-reg simsoc_blackparrotrv64_mmio_axi_aw_first = 1'd0;
-reg simsoc_blackparrotrv64_mmio_axi_aw_last = 1'd0;
-wire [31:0] simsoc_blackparrotrv64_mmio_axi_aw_payload_addr;
-wire [1:0] simsoc_blackparrotrv64_mmio_axi_aw_payload_burst;
-wire [7:0] simsoc_blackparrotrv64_mmio_axi_aw_payload_len;
-wire [3:0] simsoc_blackparrotrv64_mmio_axi_aw_payload_size;
-wire [1:0] simsoc_blackparrotrv64_mmio_axi_aw_payload_lock;
-wire [2:0] simsoc_blackparrotrv64_mmio_axi_aw_payload_prot;
-wire [3:0] simsoc_blackparrotrv64_mmio_axi_aw_payload_cache;
-wire [3:0] simsoc_blackparrotrv64_mmio_axi_aw_payload_qos;
-wire [3:0] simsoc_blackparrotrv64_mmio_axi_aw_payload_id;
-wire simsoc_blackparrotrv64_mmio_axi_w_valid;
-reg simsoc_blackparrotrv64_mmio_axi_w_ready = 1'd0;
-wire simsoc_blackparrotrv64_mmio_axi_w_last;
-wire [63:0] simsoc_blackparrotrv64_mmio_axi_w_payload_data;
-wire [7:0] simsoc_blackparrotrv64_mmio_axi_w_payload_strb;
-reg simsoc_blackparrotrv64_mmio_axi_b_valid = 1'd0;
-wire simsoc_blackparrotrv64_mmio_axi_b_ready;
-reg [1:0] simsoc_blackparrotrv64_mmio_axi_b_payload_resp = 2'd0;
-reg [3:0] simsoc_blackparrotrv64_mmio_axi_b_payload_id = 4'd0;
-wire simsoc_blackparrotrv64_mmio_axi_ar_valid;
-reg simsoc_blackparrotrv64_mmio_axi_ar_ready = 1'd0;
-reg simsoc_blackparrotrv64_mmio_axi_ar_first = 1'd0;
-reg simsoc_blackparrotrv64_mmio_axi_ar_last = 1'd0;
-wire [31:0] simsoc_blackparrotrv64_mmio_axi_ar_payload_addr;
-wire [1:0] simsoc_blackparrotrv64_mmio_axi_ar_payload_burst;
-wire [7:0] simsoc_blackparrotrv64_mmio_axi_ar_payload_len;
-wire [3:0] simsoc_blackparrotrv64_mmio_axi_ar_payload_size;
-wire [1:0] simsoc_blackparrotrv64_mmio_axi_ar_payload_lock;
-wire [2:0] simsoc_blackparrotrv64_mmio_axi_ar_payload_prot;
-wire [3:0] simsoc_blackparrotrv64_mmio_axi_ar_payload_cache;
-wire [3:0] simsoc_blackparrotrv64_mmio_axi_ar_payload_qos;
-wire [3:0] simsoc_blackparrotrv64_mmio_axi_ar_payload_id;
-reg simsoc_blackparrotrv64_mmio_axi_r_valid = 1'd0;
-wire simsoc_blackparrotrv64_mmio_axi_r_ready;
-reg simsoc_blackparrotrv64_mmio_axi_r_last = 1'd0;
-reg [1:0] simsoc_blackparrotrv64_mmio_axi_r_payload_resp = 2'd0;
-reg [63:0] simsoc_blackparrotrv64_mmio_axi_r_payload_data = 64'd0;
-reg [3:0] simsoc_blackparrotrv64_mmio_axi_r_payload_id = 4'd0;
-reg [28:0] simsoc_blackparrotrv64_mem_wb_adr = 29'd0;
-reg [63:0] simsoc_blackparrotrv64_mem_wb_dat_w = 64'd0;
-wire [63:0] simsoc_blackparrotrv64_mem_wb_dat_r;
-reg [7:0] simsoc_blackparrotrv64_mem_wb_sel = 8'd0;
-reg simsoc_blackparrotrv64_mem_wb_cyc = 1'd0;
-reg simsoc_blackparrotrv64_mem_wb_stb = 1'd0;
-reg simsoc_blackparrotrv64_mem_wb_ack = 1'd0;
-reg simsoc_blackparrotrv64_mem_wb_we = 1'd0;
-reg [28:0] simsoc_blackparrotrv64_mmio_wb_adr = 29'd0;
-reg [63:0] simsoc_blackparrotrv64_mmio_wb_dat_w = 64'd0;
-wire [63:0] simsoc_blackparrotrv64_mmio_wb_dat_r;
-reg [7:0] simsoc_blackparrotrv64_mmio_wb_sel = 8'd0;
-reg simsoc_blackparrotrv64_mmio_wb_cyc = 1'd0;
-reg simsoc_blackparrotrv64_mmio_wb_stb = 1'd0;
-reg simsoc_blackparrotrv64_mmio_wb_ack = 1'd0;
-reg simsoc_blackparrotrv64_mmio_wb_we = 1'd0;
-wire [29:0] simsoc_blackparrotrv64_ibus_adr;
-reg [31:0] simsoc_blackparrotrv64_ibus_dat_w = 32'd0;
-wire [31:0] simsoc_blackparrotrv64_ibus_dat_r;
-reg [3:0] simsoc_blackparrotrv64_ibus_sel = 4'd0;
-reg simsoc_blackparrotrv64_ibus_cyc = 1'd0;
-reg simsoc_blackparrotrv64_ibus_stb = 1'd0;
-wire simsoc_blackparrotrv64_ibus_ack;
-reg simsoc_blackparrotrv64_ibus_we = 1'd0;
-reg [2:0] simsoc_blackparrotrv64_ibus_cti = 3'd0;
-reg [1:0] simsoc_blackparrotrv64_ibus_bte = 2'd0;
-wire simsoc_blackparrotrv64_ibus_err;
-wire [29:0] simsoc_blackparrotrv64_dbus_adr;
-reg [31:0] simsoc_blackparrotrv64_dbus_dat_w = 32'd0;
-wire [31:0] simsoc_blackparrotrv64_dbus_dat_r;
-reg [3:0] simsoc_blackparrotrv64_dbus_sel = 4'd0;
-reg simsoc_blackparrotrv64_dbus_cyc = 1'd0;
-reg simsoc_blackparrotrv64_dbus_stb = 1'd0;
-wire simsoc_blackparrotrv64_dbus_ack;
-reg simsoc_blackparrotrv64_dbus_we = 1'd0;
-reg [2:0] simsoc_blackparrotrv64_dbus_cti = 3'd0;
-reg [1:0] simsoc_blackparrotrv64_dbus_bte = 2'd0;
-wire simsoc_blackparrotrv64_dbus_err;
-reg simsoc_blackparrotrv64_axi2wishbone0_aw_valid = 1'd0;
-reg simsoc_blackparrotrv64_axi2wishbone0_aw_ready = 1'd0;
-reg [31:0] simsoc_blackparrotrv64_axi2wishbone0_aw_payload_addr = 32'd0;
-reg simsoc_blackparrotrv64_axi2wishbone0_w_valid = 1'd0;
-reg simsoc_blackparrotrv64_axi2wishbone0_w_ready = 1'd0;
-reg [63:0] simsoc_blackparrotrv64_axi2wishbone0_w_payload_data = 64'd0;
-reg [7:0] simsoc_blackparrotrv64_axi2wishbone0_w_payload_strb = 8'd0;
-reg simsoc_blackparrotrv64_axi2wishbone0_b_valid = 1'd0;
-wire simsoc_blackparrotrv64_axi2wishbone0_b_ready;
-reg [1:0] simsoc_blackparrotrv64_axi2wishbone0_b_payload_resp = 2'd0;
-reg simsoc_blackparrotrv64_axi2wishbone0_ar_valid = 1'd0;
-reg simsoc_blackparrotrv64_axi2wishbone0_ar_ready = 1'd0;
-reg [31:0] simsoc_blackparrotrv64_axi2wishbone0_ar_payload_addr = 32'd0;
-reg simsoc_blackparrotrv64_axi2wishbone0_r_valid = 1'd0;
-reg simsoc_blackparrotrv64_axi2wishbone0_r_ready = 1'd0;
-reg [1:0] simsoc_blackparrotrv64_axi2wishbone0_r_payload_resp = 2'd0;
-reg [63:0] simsoc_blackparrotrv64_axi2wishbone0_r_payload_data = 64'd0;
-wire simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_sink_valid;
-wire simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_sink_ready;
-wire simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_sink_first;
-wire simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_sink_last;
-wire [31:0] simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_sink_payload_addr;
-wire [1:0] simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_sink_payload_burst;
-wire [7:0] simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_sink_payload_len;
-wire [3:0] simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_sink_payload_size;
-wire [1:0] simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_sink_payload_lock;
-wire [2:0] simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_sink_payload_prot;
-wire [3:0] simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_sink_payload_cache;
-wire [3:0] simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_sink_payload_qos;
-wire [3:0] simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_sink_payload_id;
-wire simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_source_valid;
-reg simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_source_ready = 1'd0;
-wire simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_source_first;
-wire simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_source_last;
-reg [31:0] simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_source_payload_addr = 32'd0;
-reg [1:0] simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_source_payload_burst = 2'd0;
-reg [7:0] simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_source_payload_len = 8'd0;
-reg [3:0] simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_source_payload_size = 4'd0;
-reg [1:0] simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_source_payload_lock = 2'd0;
-reg [2:0] simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_source_payload_prot = 3'd0;
-reg [3:0] simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_source_payload_cache = 4'd0;
-reg [3:0] simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_source_payload_qos = 4'd0;
-reg [3:0] simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_source_payload_id = 4'd0;
-wire simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_pipe_ce;
-wire simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_busy;
-reg simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_valid_n = 1'd0;
-reg simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_first_n = 1'd0;
-reg simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_last_n = 1'd0;
-reg simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_valid = 1'd0;
-wire simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_ready;
-reg simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_first = 1'd0;
-reg simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_last = 1'd0;
-reg [31:0] simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_payload_addr = 32'd0;
-reg [1:0] simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_payload_burst = 2'd0;
-reg [7:0] simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_payload_len = 8'd0;
-reg [3:0] simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_payload_size = 4'd0;
-reg [1:0] simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_payload_lock = 2'd0;
-reg [2:0] simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_payload_prot = 3'd0;
-reg [3:0] simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_payload_cache = 4'd0;
-reg [3:0] simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_payload_qos = 4'd0;
-reg [3:0] simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_payload_id = 4'd0;
-wire simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_beat_valid;
-reg simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_beat_ready = 1'd0;
-wire simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_beat_first;
-wire simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_beat_last;
-wire [31:0] simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_beat_payload_addr;
-wire [3:0] simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_beat_payload_id;
-reg [7:0] simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_beat_count = 8'd0;
-wire [11:0] simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_beat_size;
-reg [11:0] simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_beat_offset = 12'd0;
-wire [11:0] simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_beat_wrap;
-reg simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_cmd_done = 1'd0;
-reg simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_last_ar_aw_n = 1'd0;
-reg [63:0] simsoc_blackparrotrv64_axi2wishbone0_axi_lite2wishbone_data = 64'd0;
-wire [31:0] simsoc_blackparrotrv64_axi2wishbone0_axi_lite2wishbone_r_addr;
-wire [31:0] simsoc_blackparrotrv64_axi2wishbone0_axi_lite2wishbone_w_addr;
-reg simsoc_blackparrotrv64_axi2wishbone0_axi_lite2wishbone_last_ar_aw_n = 1'd0;
-wire simsoc_blackparrotrv64_mem_a2w_reset;
-reg simsoc_blackparrotrv64_axi2wishbone1_aw_valid = 1'd0;
-reg simsoc_blackparrotrv64_axi2wishbone1_aw_ready = 1'd0;
-reg [31:0] simsoc_blackparrotrv64_axi2wishbone1_aw_payload_addr = 32'd0;
-reg simsoc_blackparrotrv64_axi2wishbone1_w_valid = 1'd0;
-reg simsoc_blackparrotrv64_axi2wishbone1_w_ready = 1'd0;
-reg [63:0] simsoc_blackparrotrv64_axi2wishbone1_w_payload_data = 64'd0;
-reg [7:0] simsoc_blackparrotrv64_axi2wishbone1_w_payload_strb = 8'd0;
-reg simsoc_blackparrotrv64_axi2wishbone1_b_valid = 1'd0;
-wire simsoc_blackparrotrv64_axi2wishbone1_b_ready;
-reg [1:0] simsoc_blackparrotrv64_axi2wishbone1_b_payload_resp = 2'd0;
-reg simsoc_blackparrotrv64_axi2wishbone1_ar_valid = 1'd0;
-reg simsoc_blackparrotrv64_axi2wishbone1_ar_ready = 1'd0;
-reg [31:0] simsoc_blackparrotrv64_axi2wishbone1_ar_payload_addr = 32'd0;
-reg simsoc_blackparrotrv64_axi2wishbone1_r_valid = 1'd0;
-reg simsoc_blackparrotrv64_axi2wishbone1_r_ready = 1'd0;
-reg [1:0] simsoc_blackparrotrv64_axi2wishbone1_r_payload_resp = 2'd0;
-reg [63:0] simsoc_blackparrotrv64_axi2wishbone1_r_payload_data = 64'd0;
-wire simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_sink_valid;
-wire simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_sink_ready;
-wire simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_sink_first;
-wire simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_sink_last;
-wire [31:0] simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_sink_payload_addr;
-wire [1:0] simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_sink_payload_burst;
-wire [7:0] simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_sink_payload_len;
-wire [3:0] simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_sink_payload_size;
-wire [1:0] simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_sink_payload_lock;
-wire [2:0] simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_sink_payload_prot;
-wire [3:0] simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_sink_payload_cache;
-wire [3:0] simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_sink_payload_qos;
-wire [3:0] simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_sink_payload_id;
-wire simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_source_valid;
-reg simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_source_ready = 1'd0;
-wire simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_source_first;
-wire simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_source_last;
-reg [31:0] simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_source_payload_addr = 32'd0;
-reg [1:0] simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_source_payload_burst = 2'd0;
-reg [7:0] simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_source_payload_len = 8'd0;
-reg [3:0] simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_source_payload_size = 4'd0;
-reg [1:0] simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_source_payload_lock = 2'd0;
-reg [2:0] simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_source_payload_prot = 3'd0;
-reg [3:0] simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_source_payload_cache = 4'd0;
-reg [3:0] simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_source_payload_qos = 4'd0;
-reg [3:0] simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_source_payload_id = 4'd0;
-wire simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_pipe_ce;
-wire simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_busy;
-reg simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_valid_n = 1'd0;
-reg simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_first_n = 1'd0;
-reg simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_last_n = 1'd0;
-reg simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_valid = 1'd0;
-wire simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_ready;
-reg simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_first = 1'd0;
-reg simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_last = 1'd0;
-reg [31:0] simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_payload_addr = 32'd0;
-reg [1:0] simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_payload_burst = 2'd0;
-reg [7:0] simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_payload_len = 8'd0;
-reg [3:0] simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_payload_size = 4'd0;
-reg [1:0] simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_payload_lock = 2'd0;
-reg [2:0] simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_payload_prot = 3'd0;
-reg [3:0] simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_payload_cache = 4'd0;
-reg [3:0] simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_payload_qos = 4'd0;
-reg [3:0] simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_payload_id = 4'd0;
-wire simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_beat_valid;
-reg simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_beat_ready = 1'd0;
-wire simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_beat_first;
-wire simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_beat_last;
-wire [31:0] simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_beat_payload_addr;
-wire [3:0] simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_beat_payload_id;
-reg [7:0] simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_beat_count = 8'd0;
-wire [11:0] simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_beat_size;
-reg [11:0] simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_beat_offset = 12'd0;
-wire [11:0] simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_beat_wrap;
-reg simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_cmd_done = 1'd0;
-reg simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_last_ar_aw_n = 1'd0;
-reg [63:0] simsoc_blackparrotrv64_axi2wishbone1_axi_lite2wishbone_data = 64'd0;
-wire [31:0] simsoc_blackparrotrv64_axi2wishbone1_axi_lite2wishbone_r_addr;
-wire [31:0] simsoc_blackparrotrv64_axi2wishbone1_axi_lite2wishbone_w_addr;
-reg simsoc_blackparrotrv64_axi2wishbone1_axi_lite2wishbone_last_ar_aw_n = 1'd0;
-wire simsoc_blackparrotrv64_mmio_a2w_reset;
-reg simsoc_blackparrotrv64_mem_dc_read = 1'd0;
-reg simsoc_blackparrotrv64_mem_dc_write = 1'd0;
-reg simsoc_blackparrotrv64_mem_dc_counter = 1'd0;
-reg simsoc_blackparrotrv64_mem_dc_counter_reset = 1'd0;
-reg simsoc_blackparrotrv64_mem_dc_counter_ce = 1'd0;
-wire simsoc_blackparrotrv64_mem_dc_counter_done;
-reg [63:0] simsoc_blackparrotrv64_mem_dc_cached_data = 64'd0;
-reg simsoc_blackparrotrv64_mmio_dc_read = 1'd0;
-reg simsoc_blackparrotrv64_mmio_dc_write = 1'd0;
-reg simsoc_blackparrotrv64_mmio_dc_counter = 1'd0;
-reg simsoc_blackparrotrv64_mmio_dc_counter_reset = 1'd0;
-reg simsoc_blackparrotrv64_mmio_dc_counter_ce = 1'd0;
-wire simsoc_blackparrotrv64_mmio_dc_counter_done;
-reg [63:0] simsoc_blackparrotrv64_mmio_dc_cached_data = 64'd0;
-wire [29:0] simsoc_rom_bus_adr;
-wire [31:0] simsoc_rom_bus_dat_w;
-wire [31:0] simsoc_rom_bus_dat_r;
-wire [3:0] simsoc_rom_bus_sel;
-wire simsoc_rom_bus_cyc;
-wire simsoc_rom_bus_stb;
-reg simsoc_rom_bus_ack = 1'd0;
-wire simsoc_rom_bus_we;
-wire [2:0] simsoc_rom_bus_cti;
-wire [1:0] simsoc_rom_bus_bte;
-reg simsoc_rom_bus_err = 1'd0;
-wire [12:0] simsoc_rom_adr;
-wire [31:0] simsoc_rom_dat_r;
-wire [29:0] simsoc_sram_bus_adr;
-wire [31:0] simsoc_sram_bus_dat_w;
-wire [31:0] simsoc_sram_bus_dat_r;
-wire [3:0] simsoc_sram_bus_sel;
-wire simsoc_sram_bus_cyc;
-wire simsoc_sram_bus_stb;
-reg simsoc_sram_bus_ack = 1'd0;
-wire simsoc_sram_bus_we;
-wire [2:0] simsoc_sram_bus_cti;
-wire [1:0] simsoc_sram_bus_bte;
-reg simsoc_sram_bus_err = 1'd0;
-wire [9:0] simsoc_sram_adr;
-wire [31:0] simsoc_sram_dat_r;
-reg [3:0] simsoc_sram_we = 4'd0;
-wire [31:0] simsoc_sram_dat_w;
-wire [29:0] simsoc_main_ram_bus_adr;
-wire [31:0] simsoc_main_ram_bus_dat_w;
-wire [31:0] simsoc_main_ram_bus_dat_r;
-wire [3:0] simsoc_main_ram_bus_sel;
-wire simsoc_main_ram_bus_cyc;
-wire simsoc_main_ram_bus_stb;
-reg simsoc_main_ram_bus_ack = 1'd0;
-wire simsoc_main_ram_bus_we;
-wire [2:0] simsoc_main_ram_bus_cti;
-wire [1:0] simsoc_main_ram_bus_bte;
-reg simsoc_main_ram_bus_err = 1'd0;
-wire [25:0] simsoc_main_ram_adr;
-wire [31:0] simsoc_main_ram_dat_r;
-reg [3:0] simsoc_main_ram_we = 4'd0;
-wire [31:0] simsoc_main_ram_dat_w;
-reg [31:0] simsoc_load_storage = 32'd0;
-reg simsoc_load_re = 1'd0;
-reg [31:0] simsoc_reload_storage = 32'd0;
-reg simsoc_reload_re = 1'd0;
-reg simsoc_en_storage = 1'd0;
-reg simsoc_en_re = 1'd0;
-reg simsoc_update_value_storage = 1'd0;
-reg simsoc_update_value_re = 1'd0;
-reg [31:0] simsoc_value_status = 32'd0;
-wire simsoc_value_we;
-wire simsoc_irq;
-wire simsoc_zero_status;
-reg simsoc_zero_pending = 1'd0;
-wire simsoc_zero_trigger;
-reg simsoc_zero_clear = 1'd0;
-reg simsoc_zero_old_trigger = 1'd0;
-wire simsoc_eventmanager_status_re;
-wire simsoc_eventmanager_status_r;
-wire simsoc_eventmanager_status_we;
-wire simsoc_eventmanager_status_w;
-wire simsoc_eventmanager_pending_re;
-wire simsoc_eventmanager_pending_r;
-wire simsoc_eventmanager_pending_we;
-wire simsoc_eventmanager_pending_w;
-reg simsoc_eventmanager_storage = 1'd0;
-reg simsoc_eventmanager_re = 1'd0;
-reg [31:0] simsoc_value = 32'd0;
-reg [13:0] simsoc_interface_adr = 14'd0;
-reg simsoc_interface_we = 1'd0;
-wire [7:0] simsoc_interface_dat_w;
-wire [7:0] simsoc_interface_dat_r;
-wire [29:0] simsoc_bus_wishbone_adr;
-wire [31:0] simsoc_bus_wishbone_dat_w;
-wire [31:0] simsoc_bus_wishbone_dat_r;
-wire [3:0] simsoc_bus_wishbone_sel;
-wire simsoc_bus_wishbone_cyc;
-wire simsoc_bus_wishbone_stb;
-reg simsoc_bus_wishbone_ack = 1'd0;
-wire simsoc_bus_wishbone_we;
-wire [2:0] simsoc_bus_wishbone_cti;
-wire [1:0] simsoc_bus_wishbone_bte;
-reg simsoc_bus_wishbone_err = 1'd0;
-wire sys_clk_1;
-wire sys_rst;
-wire por_clk;
-reg int_rst = 1'd1;
-wire sink_valid;
-wire sink_ready;
-wire sink_first;
-wire sink_last;
-wire [7:0] sink_payload_data;
-wire source_valid;
-wire source_ready;
-reg source_first = 1'd0;
-reg source_last = 1'd0;
-wire [7:0] source_payload_data;
-wire uart_rxtx_re;
-wire [7:0] uart_rxtx_r;
-wire uart_rxtx_we;
-wire [7:0] uart_rxtx_w;
-wire uart_txfull_status;
-wire uart_txfull_we;
-wire uart_rxempty_status;
-wire uart_rxempty_we;
-wire uart_irq;
-wire uart_tx_status;
-reg uart_tx_pending = 1'd0;
-wire uart_tx_trigger;
-reg uart_tx_clear = 1'd0;
-reg uart_tx_old_trigger = 1'd0;
-wire uart_rx_status;
-reg uart_rx_pending = 1'd0;
-wire uart_rx_trigger;
-reg uart_rx_clear = 1'd0;
-reg uart_rx_old_trigger = 1'd0;
-wire uart_eventmanager_status_re;
-wire [1:0] uart_eventmanager_status_r;
-wire uart_eventmanager_status_we;
-reg [1:0] uart_eventmanager_status_w = 2'd0;
-wire uart_eventmanager_pending_re;
-wire [1:0] uart_eventmanager_pending_r;
-wire uart_eventmanager_pending_we;
-reg [1:0] uart_eventmanager_pending_w = 2'd0;
-reg [1:0] uart_eventmanager_storage = 2'd0;
-reg uart_eventmanager_re = 1'd0;
-wire uart_tx_fifo_sink_valid;
-wire uart_tx_fifo_sink_ready;
-reg uart_tx_fifo_sink_first = 1'd0;
-reg uart_tx_fifo_sink_last = 1'd0;
-wire [7:0] uart_tx_fifo_sink_payload_data;
-wire uart_tx_fifo_source_valid;
-wire uart_tx_fifo_source_ready;
-wire uart_tx_fifo_source_first;
-wire uart_tx_fifo_source_last;
-wire [7:0] uart_tx_fifo_source_payload_data;
-wire uart_tx_fifo_re;
-reg uart_tx_fifo_readable = 1'd0;
-wire uart_tx_fifo_syncfifo_we;
-wire uart_tx_fifo_syncfifo_writable;
-wire uart_tx_fifo_syncfifo_re;
-wire uart_tx_fifo_syncfifo_readable;
-wire [9:0] uart_tx_fifo_syncfifo_din;
-wire [9:0] uart_tx_fifo_syncfifo_dout;
-reg [4:0] uart_tx_fifo_level0 = 5'd0;
-reg uart_tx_fifo_replace = 1'd0;
-reg [3:0] uart_tx_fifo_produce = 4'd0;
-reg [3:0] uart_tx_fifo_consume = 4'd0;
-reg [3:0] uart_tx_fifo_wrport_adr = 4'd0;
-wire [9:0] uart_tx_fifo_wrport_dat_r;
-wire uart_tx_fifo_wrport_we;
-wire [9:0] uart_tx_fifo_wrport_dat_w;
-wire uart_tx_fifo_do_read;
-wire [3:0] uart_tx_fifo_rdport_adr;
-wire [9:0] uart_tx_fifo_rdport_dat_r;
-wire uart_tx_fifo_rdport_re;
-wire [4:0] uart_tx_fifo_level1;
-wire [7:0] uart_tx_fifo_fifo_in_payload_data;
-wire uart_tx_fifo_fifo_in_first;
-wire uart_tx_fifo_fifo_in_last;
-wire [7:0] uart_tx_fifo_fifo_out_payload_data;
-wire uart_tx_fifo_fifo_out_first;
-wire uart_tx_fifo_fifo_out_last;
-wire uart_rx_fifo_sink_valid;
-wire uart_rx_fifo_sink_ready;
-wire uart_rx_fifo_sink_first;
-wire uart_rx_fifo_sink_last;
-wire [7:0] uart_rx_fifo_sink_payload_data;
-wire uart_rx_fifo_source_valid;
-wire uart_rx_fifo_source_ready;
-wire uart_rx_fifo_source_first;
-wire uart_rx_fifo_source_last;
-wire [7:0] uart_rx_fifo_source_payload_data;
-wire uart_rx_fifo_re;
-reg uart_rx_fifo_readable = 1'd0;
-wire uart_rx_fifo_syncfifo_we;
-wire uart_rx_fifo_syncfifo_writable;
-wire uart_rx_fifo_syncfifo_re;
-wire uart_rx_fifo_syncfifo_readable;
-wire [9:0] uart_rx_fifo_syncfifo_din;
-wire [9:0] uart_rx_fifo_syncfifo_dout;
-reg [4:0] uart_rx_fifo_level0 = 5'd0;
-reg uart_rx_fifo_replace = 1'd0;
-reg [3:0] uart_rx_fifo_produce = 4'd0;
-reg [3:0] uart_rx_fifo_consume = 4'd0;
-reg [3:0] uart_rx_fifo_wrport_adr = 4'd0;
-wire [9:0] uart_rx_fifo_wrport_dat_r;
-wire uart_rx_fifo_wrport_we;
-wire [9:0] uart_rx_fifo_wrport_dat_w;
-wire uart_rx_fifo_do_read;
-wire [3:0] uart_rx_fifo_rdport_adr;
-wire [9:0] uart_rx_fifo_rdport_dat_r;
-wire uart_rx_fifo_rdport_re;
-wire [4:0] uart_rx_fifo_level1;
-wire [7:0] uart_rx_fifo_fifo_in_payload_data;
-wire uart_rx_fifo_fifo_in_first;
-wire uart_rx_fifo_fifo_in_last;
-wire [7:0] uart_rx_fifo_fifo_out_payload_data;
-wire uart_rx_fifo_fifo_out_first;
-wire uart_rx_fifo_fifo_out_last;
-reg [1:0] axi2axilite0_state = 2'd0;
-reg [1:0] axi2axilite0_next_state = 2'd0;
-reg simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_cmd_done_axi2axilite0_next_value0 = 1'd0;
-reg simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_cmd_done_axi2axilite0_next_value_ce0 = 1'd0;
-reg simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_last_ar_aw_n_axi2axilite0_next_value1 = 1'd0;
-reg simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_last_ar_aw_n_axi2axilite0_next_value_ce1 = 1'd0;
-reg [2:0] axilite2wishbone0_state = 3'd0;
-reg [2:0] axilite2wishbone0_next_state = 3'd0;
-reg simsoc_blackparrotrv64_axi2wishbone0_axi_lite2wishbone_last_ar_aw_n_axilite2wishbone0_next_value0 = 1'd0;
-reg simsoc_blackparrotrv64_axi2wishbone0_axi_lite2wishbone_last_ar_aw_n_axilite2wishbone0_next_value_ce0 = 1'd0;
-reg [63:0] simsoc_blackparrotrv64_axi2wishbone0_axi_lite2wishbone_data_axilite2wishbone0_next_value1 = 64'd0;
-reg simsoc_blackparrotrv64_axi2wishbone0_axi_lite2wishbone_data_axilite2wishbone0_next_value_ce1 = 1'd0;
-reg [1:0] converter0_state = 2'd0;
-reg [1:0] converter0_next_state = 2'd0;
-reg [1:0] axi2axilite1_state = 2'd0;
-reg [1:0] axi2axilite1_next_state = 2'd0;
-reg simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_cmd_done_axi2axilite1_next_value0 = 1'd0;
-reg simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_cmd_done_axi2axilite1_next_value_ce0 = 1'd0;
-reg simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_last_ar_aw_n_axi2axilite1_next_value1 = 1'd0;
-reg simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_last_ar_aw_n_axi2axilite1_next_value_ce1 = 1'd0;
-reg [2:0] axilite2wishbone1_state = 3'd0;
-reg [2:0] axilite2wishbone1_next_state = 3'd0;
-reg simsoc_blackparrotrv64_axi2wishbone1_axi_lite2wishbone_last_ar_aw_n_axilite2wishbone1_next_value0 = 1'd0;
-reg simsoc_blackparrotrv64_axi2wishbone1_axi_lite2wishbone_last_ar_aw_n_axilite2wishbone1_next_value_ce0 = 1'd0;
-reg [63:0] simsoc_blackparrotrv64_axi2wishbone1_axi_lite2wishbone_data_axilite2wishbone1_next_value1 = 64'd0;
-reg simsoc_blackparrotrv64_axi2wishbone1_axi_lite2wishbone_data_axilite2wishbone1_next_value_ce1 = 1'd0;
-reg [1:0] converter1_state = 2'd0;
-reg [1:0] converter1_next_state = 2'd0;
-reg state = 1'd0;
-reg next_state = 1'd0;
-wire [29:0] shared_adr;
-wire [31:0] shared_dat_w;
-reg [31:0] shared_dat_r = 32'd0;
-wire [3:0] shared_sel;
-wire shared_cyc;
-wire shared_stb;
-reg shared_ack = 1'd0;
-wire shared_we;
-wire [2:0] shared_cti;
-wire [1:0] shared_bte;
-wire shared_err;
-wire [1:0] request;
-reg grant = 1'd0;
-reg [3:0] slave_sel = 4'd0;
-reg [3:0] slave_sel_r = 4'd0;
-reg error = 1'd0;
-wire wait_1;
-wire done;
-reg [19:0] count = 20'd1000000;
-wire [13:0] csrbankarray_interface0_bank_bus_adr;
-wire csrbankarray_interface0_bank_bus_we;
-wire [7:0] csrbankarray_interface0_bank_bus_dat_w;
-reg [7:0] csrbankarray_interface0_bank_bus_dat_r = 8'd0;
-wire csrbankarray_csrbank0_scratch3_re;
-wire [7:0] csrbankarray_csrbank0_scratch3_r;
-wire csrbankarray_csrbank0_scratch3_we;
-wire [7:0] csrbankarray_csrbank0_scratch3_w;
-wire csrbankarray_csrbank0_scratch2_re;
-wire [7:0] csrbankarray_csrbank0_scratch2_r;
-wire csrbankarray_csrbank0_scratch2_we;
-wire [7:0] csrbankarray_csrbank0_scratch2_w;
-wire csrbankarray_csrbank0_scratch1_re;
-wire [7:0] csrbankarray_csrbank0_scratch1_r;
-wire csrbankarray_csrbank0_scratch1_we;
-wire [7:0] csrbankarray_csrbank0_scratch1_w;
-wire csrbankarray_csrbank0_scratch0_re;
-wire [7:0] csrbankarray_csrbank0_scratch0_r;
-wire csrbankarray_csrbank0_scratch0_we;
-wire [7:0] csrbankarray_csrbank0_scratch0_w;
-wire csrbankarray_csrbank0_bus_errors3_re;
-wire [7:0] csrbankarray_csrbank0_bus_errors3_r;
-wire csrbankarray_csrbank0_bus_errors3_we;
-wire [7:0] csrbankarray_csrbank0_bus_errors3_w;
-wire csrbankarray_csrbank0_bus_errors2_re;
-wire [7:0] csrbankarray_csrbank0_bus_errors2_r;
-wire csrbankarray_csrbank0_bus_errors2_we;
-wire [7:0] csrbankarray_csrbank0_bus_errors2_w;
-wire csrbankarray_csrbank0_bus_errors1_re;
-wire [7:0] csrbankarray_csrbank0_bus_errors1_r;
-wire csrbankarray_csrbank0_bus_errors1_we;
-wire [7:0] csrbankarray_csrbank0_bus_errors1_w;
-wire csrbankarray_csrbank0_bus_errors0_re;
-wire [7:0] csrbankarray_csrbank0_bus_errors0_r;
-wire csrbankarray_csrbank0_bus_errors0_we;
-wire [7:0] csrbankarray_csrbank0_bus_errors0_w;
-wire csrbankarray_csrbank0_sel;
-wire [13:0] csrbankarray_sram_bus_adr;
-wire csrbankarray_sram_bus_we;
-wire [7:0] csrbankarray_sram_bus_dat_w;
-reg [7:0] csrbankarray_sram_bus_dat_r = 8'd0;
-wire [5:0] csrbankarray_adr;
-wire [7:0] csrbankarray_dat_r;
-wire csrbankarray_sel;
-reg csrbankarray_sel_r = 1'd0;
-wire [13:0] csrbankarray_interface1_bank_bus_adr;
-wire csrbankarray_interface1_bank_bus_we;
-wire [7:0] csrbankarray_interface1_bank_bus_dat_w;
-reg [7:0] csrbankarray_interface1_bank_bus_dat_r = 8'd0;
-wire csrbankarray_csrbank1_load3_re;
-wire [7:0] csrbankarray_csrbank1_load3_r;
-wire csrbankarray_csrbank1_load3_we;
-wire [7:0] csrbankarray_csrbank1_load3_w;
-wire csrbankarray_csrbank1_load2_re;
-wire [7:0] csrbankarray_csrbank1_load2_r;
-wire csrbankarray_csrbank1_load2_we;
-wire [7:0] csrbankarray_csrbank1_load2_w;
-wire csrbankarray_csrbank1_load1_re;
-wire [7:0] csrbankarray_csrbank1_load1_r;
-wire csrbankarray_csrbank1_load1_we;
-wire [7:0] csrbankarray_csrbank1_load1_w;
-wire csrbankarray_csrbank1_load0_re;
-wire [7:0] csrbankarray_csrbank1_load0_r;
-wire csrbankarray_csrbank1_load0_we;
-wire [7:0] csrbankarray_csrbank1_load0_w;
-wire csrbankarray_csrbank1_reload3_re;
-wire [7:0] csrbankarray_csrbank1_reload3_r;
-wire csrbankarray_csrbank1_reload3_we;
-wire [7:0] csrbankarray_csrbank1_reload3_w;
-wire csrbankarray_csrbank1_reload2_re;
-wire [7:0] csrbankarray_csrbank1_reload2_r;
-wire csrbankarray_csrbank1_reload2_we;
-wire [7:0] csrbankarray_csrbank1_reload2_w;
-wire csrbankarray_csrbank1_reload1_re;
-wire [7:0] csrbankarray_csrbank1_reload1_r;
-wire csrbankarray_csrbank1_reload1_we;
-wire [7:0] csrbankarray_csrbank1_reload1_w;
-wire csrbankarray_csrbank1_reload0_re;
-wire [7:0] csrbankarray_csrbank1_reload0_r;
-wire csrbankarray_csrbank1_reload0_we;
-wire [7:0] csrbankarray_csrbank1_reload0_w;
-wire csrbankarray_csrbank1_en0_re;
-wire csrbankarray_csrbank1_en0_r;
-wire csrbankarray_csrbank1_en0_we;
-wire csrbankarray_csrbank1_en0_w;
-wire csrbankarray_csrbank1_update_value0_re;
-wire csrbankarray_csrbank1_update_value0_r;
-wire csrbankarray_csrbank1_update_value0_we;
-wire csrbankarray_csrbank1_update_value0_w;
-wire csrbankarray_csrbank1_value3_re;
-wire [7:0] csrbankarray_csrbank1_value3_r;
-wire csrbankarray_csrbank1_value3_we;
-wire [7:0] csrbankarray_csrbank1_value3_w;
-wire csrbankarray_csrbank1_value2_re;
-wire [7:0] csrbankarray_csrbank1_value2_r;
-wire csrbankarray_csrbank1_value2_we;
-wire [7:0] csrbankarray_csrbank1_value2_w;
-wire csrbankarray_csrbank1_value1_re;
-wire [7:0] csrbankarray_csrbank1_value1_r;
-wire csrbankarray_csrbank1_value1_we;
-wire [7:0] csrbankarray_csrbank1_value1_w;
-wire csrbankarray_csrbank1_value0_re;
-wire [7:0] csrbankarray_csrbank1_value0_r;
-wire csrbankarray_csrbank1_value0_we;
-wire [7:0] csrbankarray_csrbank1_value0_w;
-wire csrbankarray_csrbank1_ev_enable0_re;
-wire csrbankarray_csrbank1_ev_enable0_r;
-wire csrbankarray_csrbank1_ev_enable0_we;
-wire csrbankarray_csrbank1_ev_enable0_w;
-wire csrbankarray_csrbank1_sel;
-wire [13:0] csrbankarray_interface2_bank_bus_adr;
-wire csrbankarray_interface2_bank_bus_we;
-wire [7:0] csrbankarray_interface2_bank_bus_dat_w;
-reg [7:0] csrbankarray_interface2_bank_bus_dat_r = 8'd0;
-wire csrbankarray_csrbank2_txfull_re;
-wire csrbankarray_csrbank2_txfull_r;
-wire csrbankarray_csrbank2_txfull_we;
-wire csrbankarray_csrbank2_txfull_w;
-wire csrbankarray_csrbank2_rxempty_re;
-wire csrbankarray_csrbank2_rxempty_r;
-wire csrbankarray_csrbank2_rxempty_we;
-wire csrbankarray_csrbank2_rxempty_w;
-wire csrbankarray_csrbank2_ev_enable0_re;
-wire [1:0] csrbankarray_csrbank2_ev_enable0_r;
-wire csrbankarray_csrbank2_ev_enable0_we;
-wire [1:0] csrbankarray_csrbank2_ev_enable0_w;
-wire csrbankarray_csrbank2_sel;
-wire [13:0] csrcon_adr;
-wire csrcon_we;
-wire [7:0] csrcon_dat_w;
-wire [7:0] csrcon_dat_r;
-reg [29:0] array_muxed0 = 30'd0;
-reg [31:0] array_muxed1 = 32'd0;
-reg [3:0] array_muxed2 = 4'd0;
-reg array_muxed3 = 1'd0;
-reg array_muxed4 = 1'd0;
-reg array_muxed5 = 1'd0;
-reg [2:0] array_muxed6 = 3'd0;
-reg [1:0] array_muxed7 = 2'd0;
-
-assign csrbankarray_csrbank0_bus_errors3_w = simsoc_ctrl_bus_errors_status[31:24];
-assign simsoc_ctrl_reset_reset_re = ((csrbankarray_csrbank0_sel & csrbankarray_interface0_bank_bus_we) & (csrbankarray_interface0_bank_bus_adr[3:0] == 1'd0));
-assign simsoc_ctrl_reset_reset_r = csrbankarray_interface0_bank_bus_dat_w[0];
-assign simsoc_ctrl_reset_reset_we = ((csrbankarray_csrbank0_sel & (~csrbankarray_interface0_bank_bus_we)) & (csrbankarray_interface0_bank_bus_adr[3:0] == 1'd0));
-assign csrbankarray_csrbank0_bus_errors2_we = ((csrbankarray_csrbank0_sel & (~csrbankarray_interface0_bank_bus_we)) & (csrbankarray_interface0_bank_bus_adr[3:0] == 3'd6));
-assign csrbankarray_csrbank0_bus_errors2_w = simsoc_ctrl_bus_errors_status[23:16];
-assign csrbankarray_csrbank1_value3_w = simsoc_value_status[31:24];
-assign csrbankarray_csrbank0_bus_errors1_re = ((csrbankarray_csrbank0_sel & csrbankarray_interface0_bank_bus_we) & (csrbankarray_interface0_bank_bus_adr[3:0] == 3'd7));
-assign simsoc_ctrl_bus_errors_status = simsoc_ctrl_bus_errors;
-assign csrbankarray_csrbank0_bus_errors1_we = ((csrbankarray_csrbank0_sel & (~csrbankarray_interface0_bank_bus_we)) & (csrbankarray_interface0_bank_bus_adr[3:0] == 3'd7));
-assign simsoc_ctrl_reset = simsoc_ctrl_reset_reset_re;
-assign simsoc_ctrl_bus_error = error;
-assign csrbankarray_csrbank0_bus_errors0_re = ((csrbankarray_csrbank0_sel & csrbankarray_interface0_bank_bus_we) & (csrbankarray_interface0_bank_bus_adr[3:0] == 4'd8));
-assign simsoc_main_ram_bus_adr = shared_adr;
-assign simsoc_bus_wishbone_adr = shared_adr;
-assign simsoc_main_ram_bus_dat_w = shared_dat_w;
-assign csrbankarray_csrbank0_bus_errors0_we = ((csrbankarray_csrbank0_sel & (~csrbankarray_interface0_bank_bus_we)) & (csrbankarray_interface0_bank_bus_adr[3:0] == 4'd8));
-assign simsoc_main_ram_bus_dat_r = simsoc_main_ram_dat_r;
-assign simsoc_blackparrotrv64_reset = simsoc_ctrl_reset;
-assign simsoc_main_ram_bus_sel = shared_sel;
-always @(*) begin
-	simsoc_blackparrotrv64_interrupt = 4'd0;
-	simsoc_blackparrotrv64_interrupt[0] = simsoc_irq;
-	simsoc_blackparrotrv64_interrupt[1] = uart_irq;
-end
-assign simsoc_main_ram_bus_cyc = (shared_cyc & slave_sel[2]);
-assign simsoc_main_ram_bus_stb = shared_stb;
-always @(*) begin
-	simsoc_blackparrotrv64_mem_axi_aw_ready = 1'd0;
-	case (axi2axilite0_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		default: begin
-			if ((simsoc_blackparrotrv64_mem_axi_ar_valid & simsoc_blackparrotrv64_mem_axi_aw_valid)) begin
-				if (simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_last_ar_aw_n) begin
-					simsoc_blackparrotrv64_mem_axi_aw_ready = simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_ready;
-				end else begin
-				end
-			end else begin
-				if (simsoc_blackparrotrv64_mem_axi_ar_valid) begin
-				end else begin
-					if (simsoc_blackparrotrv64_mem_axi_aw_valid) begin
-						simsoc_blackparrotrv64_mem_axi_aw_ready = simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_ready;
-					end
-				end
-			end
-		end
-	endcase
-end
-assign simsoc_bus_wishbone_dat_w = shared_dat_w;
-assign simsoc_main_ram_bus_we = shared_we;
-assign simsoc_main_ram_bus_cti = shared_cti;
-assign csrbankarray_csrbank0_bus_errors2_r = csrbankarray_interface0_bank_bus_dat_w[7:0];
-assign simsoc_main_ram_bus_bte = shared_bte;
-assign csrbankarray_csrbank1_reload0_w = simsoc_reload_storage[7:0];
-assign simsoc_main_ram_adr = simsoc_main_ram_bus_adr[25:0];
-assign csrbankarray_interface2_bank_bus_we = csrcon_we;
-always @(*) begin
-	simsoc_main_ram_we = 4'd0;
-	simsoc_main_ram_we[0] = (((simsoc_main_ram_bus_cyc & simsoc_main_ram_bus_stb) & simsoc_main_ram_bus_we) & simsoc_main_ram_bus_sel[0]);
-	simsoc_main_ram_we[1] = (((simsoc_main_ram_bus_cyc & simsoc_main_ram_bus_stb) & simsoc_main_ram_bus_we) & simsoc_main_ram_bus_sel[1]);
-	simsoc_main_ram_we[2] = (((simsoc_main_ram_bus_cyc & simsoc_main_ram_bus_stb) & simsoc_main_ram_bus_we) & simsoc_main_ram_bus_sel[2]);
-	simsoc_main_ram_we[3] = (((simsoc_main_ram_bus_cyc & simsoc_main_ram_bus_stb) & simsoc_main_ram_bus_we) & simsoc_main_ram_bus_sel[3]);
-end
-assign simsoc_main_ram_dat_w = simsoc_main_ram_bus_dat_w;
-assign csrbankarray_csrbank1_update_value0_we = ((csrbankarray_csrbank1_sel & (~csrbankarray_interface1_bank_bus_we)) & (csrbankarray_interface1_bank_bus_adr[4:0] == 4'd9));
-always @(*) begin
-	simsoc_blackparrotrv64_mem_axi_w_ready = 1'd0;
-	case (axi2axilite0_state)
-		1'd1: begin
-		end
-		2'd2: begin
-			simsoc_blackparrotrv64_mem_axi_w_ready = simsoc_blackparrotrv64_axi2wishbone0_w_ready;
-		end
-		2'd3: begin
-		end
-		default: begin
-		end
-	endcase
-end
-assign csrbankarray_csrbank0_sel = (csrbankarray_interface0_bank_bus_adr[13:9] == 1'd0);
-always @(*) begin
-	simsoc_blackparrotrv64_mem_axi_b_valid = 1'd0;
-	case (axi2axilite0_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-			simsoc_blackparrotrv64_mem_axi_b_valid = 1'd1;
-		end
-		default: begin
-		end
-	endcase
-end
-always @(*) begin
-	simsoc_blackparrotrv64_mem_axi_b_payload_resp = 2'd0;
-	case (axi2axilite0_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-			simsoc_blackparrotrv64_mem_axi_b_payload_resp = 1'd0;
-		end
-		default: begin
-		end
-	endcase
-end
-always @(*) begin
-	simsoc_blackparrotrv64_mem_axi_b_payload_id = 4'd0;
-	case (axi2axilite0_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-			simsoc_blackparrotrv64_mem_axi_b_payload_id = simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_beat_payload_id;
-		end
-		default: begin
-		end
-	endcase
-end
-always @(*) begin
-	simsoc_blackparrotrv64_mem_axi_ar_ready = 1'd0;
-	case (axi2axilite0_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		default: begin
-			if ((simsoc_blackparrotrv64_mem_axi_ar_valid & simsoc_blackparrotrv64_mem_axi_aw_valid)) begin
-				if (simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_last_ar_aw_n) begin
-				end else begin
-					simsoc_blackparrotrv64_mem_axi_ar_ready = simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_ready;
-				end
-			end else begin
-				if (simsoc_blackparrotrv64_mem_axi_ar_valid) begin
-					simsoc_blackparrotrv64_mem_axi_ar_ready = simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_ready;
-				end else begin
-				end
-			end
-		end
-	endcase
-end
-assign csrbankarray_csrbank0_bus_errors1_r = csrbankarray_interface0_bank_bus_dat_w[7:0];
-assign simsoc_value_we = csrbankarray_csrbank1_value0_we;
-assign simsoc_irq = (simsoc_eventmanager_pending_w & simsoc_eventmanager_storage);
-always @(*) begin
-	simsoc_blackparrotrv64_mem_axi_r_valid = 1'd0;
-	case (axi2axilite0_state)
-		1'd1: begin
-			simsoc_blackparrotrv64_mem_axi_r_valid = simsoc_blackparrotrv64_axi2wishbone0_r_valid;
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		default: begin
-		end
-	endcase
-end
-assign simsoc_zero_status = simsoc_zero_trigger;
-assign simsoc_ctrl_bus_errors_we = csrbankarray_csrbank0_bus_errors0_we;
-assign simsoc_zero_trigger = (simsoc_value != 1'd0);
-always @(*) begin
-	simsoc_blackparrotrv64_mem_axi_r_last = 1'd0;
-	case (axi2axilite0_state)
-		1'd1: begin
-			simsoc_blackparrotrv64_mem_axi_r_last = simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_cmd_done;
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		default: begin
-		end
-	endcase
-end
-always @(*) begin
-	simsoc_zero_clear = 1'd0;
-	if ((simsoc_eventmanager_pending_re & simsoc_eventmanager_pending_r)) begin
-		simsoc_zero_clear = 1'd1;
-	end
-end
-always @(*) begin
-	simsoc_blackparrotrv64_mem_axi_r_payload_resp = 2'd0;
-	case (axi2axilite0_state)
-		1'd1: begin
-			simsoc_blackparrotrv64_mem_axi_r_payload_resp = 1'd0;
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		default: begin
-		end
-	endcase
-end
-always @(*) begin
-	simsoc_blackparrotrv64_mem_axi_r_payload_data = 64'd0;
-	case (axi2axilite0_state)
-		1'd1: begin
-			simsoc_blackparrotrv64_mem_axi_r_payload_data = simsoc_blackparrotrv64_axi2wishbone0_r_payload_data;
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		default: begin
-		end
-	endcase
-end
-always @(*) begin
-	simsoc_blackparrotrv64_mem_axi_r_payload_id = 4'd0;
-	case (axi2axilite0_state)
-		1'd1: begin
-			simsoc_blackparrotrv64_mem_axi_r_payload_id = simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_beat_payload_id;
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		default: begin
-		end
-	endcase
-end
-assign csrbankarray_csrbank0_bus_errors1_w = simsoc_ctrl_bus_errors_status[15:8];
-always @(*) begin
-	simsoc_blackparrotrv64_mmio_axi_aw_ready = 1'd0;
-	case (axi2axilite1_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		default: begin
-			if ((simsoc_blackparrotrv64_mmio_axi_ar_valid & simsoc_blackparrotrv64_mmio_axi_aw_valid)) begin
-				if (simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_last_ar_aw_n) begin
-					simsoc_blackparrotrv64_mmio_axi_aw_ready = simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_ready;
-				end else begin
-				end
-			end else begin
-				if (simsoc_blackparrotrv64_mmio_axi_ar_valid) begin
-				end else begin
-					if (simsoc_blackparrotrv64_mmio_axi_aw_valid) begin
-						simsoc_blackparrotrv64_mmio_axi_aw_ready = simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_ready;
-					end
-				end
-			end
-		end
-	endcase
-end
-assign simsoc_eventmanager_status_r = csrbankarray_interface1_bank_bus_dat_w[0];
-assign simsoc_eventmanager_status_we = ((csrbankarray_csrbank1_sel & (~csrbankarray_interface1_bank_bus_we)) & (csrbankarray_interface1_bank_bus_adr[4:0] == 4'd14));
-assign simsoc_eventmanager_status_w = simsoc_zero_status;
-assign simsoc_eventmanager_pending_re = ((csrbankarray_csrbank1_sel & csrbankarray_interface1_bank_bus_we) & (csrbankarray_interface1_bank_bus_adr[4:0] == 4'd15));
-assign simsoc_eventmanager_pending_r = csrbankarray_interface1_bank_bus_dat_w[0];
-assign simsoc_eventmanager_pending_we = ((csrbankarray_csrbank1_sel & (~csrbankarray_interface1_bank_bus_we)) & (csrbankarray_interface1_bank_bus_adr[4:0] == 4'd15));
-assign simsoc_eventmanager_pending_w = simsoc_zero_pending;
-assign csrbankarray_csrbank1_load3_w = simsoc_load_storage[31:24];
-always @(*) begin
-	simsoc_blackparrotrv64_mmio_axi_w_ready = 1'd0;
-	case (axi2axilite1_state)
-		1'd1: begin
-		end
-		2'd2: begin
-			simsoc_blackparrotrv64_mmio_axi_w_ready = simsoc_blackparrotrv64_axi2wishbone1_w_ready;
-		end
-		2'd3: begin
-		end
-		default: begin
-		end
-	endcase
-end
-assign csrbankarray_sram_bus_adr = csrcon_adr;
-assign csrbankarray_sram_bus_we = csrcon_we;
-assign csrbankarray_sram_bus_dat_w = csrcon_dat_w;
-assign csrbankarray_csrbank0_bus_errors0_r = csrbankarray_interface0_bank_bus_dat_w[7:0];
-always @(*) begin
-	csrbankarray_sram_bus_dat_r = 8'd0;
-	if (csrbankarray_sel_r) begin
-		csrbankarray_sram_bus_dat_r = csrbankarray_dat_r;
-	end
-end
-assign csrbankarray_csrbank1_load1_w = simsoc_load_storage[15:8];
-assign csrbankarray_adr = csrbankarray_sram_bus_adr[5:0];
-always @(*) begin
-	simsoc_blackparrotrv64_mmio_axi_b_valid = 1'd0;
-	case (axi2axilite1_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-			simsoc_blackparrotrv64_mmio_axi_b_valid = 1'd1;
-		end
-		default: begin
-		end
-	endcase
-end
-always @(*) begin
-	simsoc_interface_we = 1'd0;
-	case (state)
-		1'd1: begin
-		end
-		default: begin
-			if ((simsoc_bus_wishbone_cyc & simsoc_bus_wishbone_stb)) begin
-				simsoc_interface_we = simsoc_bus_wishbone_we;
-			end
-		end
-	endcase
-end
-assign simsoc_interface_dat_w = simsoc_bus_wishbone_dat_w;
-assign csrbankarray_sel = (csrbankarray_sram_bus_adr[13:9] == 2'd2);
-assign simsoc_interface_dat_r = csrcon_dat_r;
-always @(*) begin
-	simsoc_blackparrotrv64_mmio_axi_b_payload_resp = 2'd0;
-	case (axi2axilite1_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-			simsoc_blackparrotrv64_mmio_axi_b_payload_resp = 1'd0;
-		end
-		default: begin
-		end
-	endcase
-end
-always @(*) begin
-	simsoc_blackparrotrv64_mmio_axi_b_payload_id = 4'd0;
-	case (axi2axilite1_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-			simsoc_blackparrotrv64_mmio_axi_b_payload_id = simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_beat_payload_id;
-		end
-		default: begin
-		end
-	endcase
-end
-assign simsoc_bus_wishbone_dat_r = simsoc_interface_dat_r;
-assign csrbankarray_interface1_bank_bus_adr = csrcon_adr;
-always @(*) begin
-	simsoc_blackparrotrv64_mmio_axi_ar_ready = 1'd0;
-	case (axi2axilite1_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		default: begin
-			if ((simsoc_blackparrotrv64_mmio_axi_ar_valid & simsoc_blackparrotrv64_mmio_axi_aw_valid)) begin
-				if (simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_last_ar_aw_n) begin
-				end else begin
-					simsoc_blackparrotrv64_mmio_axi_ar_ready = simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_ready;
-				end
-			end else begin
-				if (simsoc_blackparrotrv64_mmio_axi_ar_valid) begin
-					simsoc_blackparrotrv64_mmio_axi_ar_ready = simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_ready;
-				end else begin
-				end
-			end
-		end
-	endcase
-end
-assign csrbankarray_interface1_bank_bus_we = csrcon_we;
-assign simsoc_bus_wishbone_cyc = (shared_cyc & slave_sel[3]);
-assign csrbankarray_interface1_bank_bus_dat_w = csrcon_dat_w;
-assign simsoc_bus_wishbone_stb = shared_stb;
-always @(*) begin
-	simsoc_bus_wishbone_ack = 1'd0;
-	case (state)
-		1'd1: begin
-			simsoc_bus_wishbone_ack = 1'd1;
-		end
-		default: begin
-		end
-	endcase
-end
-assign simsoc_bus_wishbone_we = shared_we;
-assign simsoc_bus_wishbone_cti = shared_cti;
-always @(*) begin
-	simsoc_blackparrotrv64_ibus_cti = 3'd0;
-	if (simsoc_blackparrotrv64_mem_dc_counter_done) begin
-		simsoc_blackparrotrv64_ibus_cti = 3'd7;
-	end else begin
-		simsoc_blackparrotrv64_ibus_cti = 2'd2;
-	end
-end
-assign simsoc_bus_wishbone_bte = shared_bte;
-always @(*) begin
-	axi2axilite1_next_state = 2'd0;
-	axi2axilite1_next_state = axi2axilite1_state;
-	case (axi2axilite1_state)
-		1'd1: begin
-			if (((simsoc_blackparrotrv64_mmio_axi_r_valid & simsoc_blackparrotrv64_mmio_axi_r_last) & simsoc_blackparrotrv64_mmio_axi_r_ready)) begin
-				axi2axilite1_next_state = 1'd0;
-			end
-		end
-		2'd2: begin
-			if (((simsoc_blackparrotrv64_mmio_axi_w_valid & simsoc_blackparrotrv64_mmio_axi_w_last) & simsoc_blackparrotrv64_mmio_axi_w_ready)) begin
-				axi2axilite1_next_state = 2'd3;
-			end
-		end
-		2'd3: begin
-			if (simsoc_blackparrotrv64_mmio_axi_b_ready) begin
-				axi2axilite1_next_state = 1'd0;
-			end
-		end
-		default: begin
-			if ((simsoc_blackparrotrv64_mmio_axi_ar_valid & simsoc_blackparrotrv64_mmio_axi_aw_valid)) begin
-				if (simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_last_ar_aw_n) begin
-					axi2axilite1_next_state = 2'd2;
-				end else begin
-					axi2axilite1_next_state = 1'd1;
-				end
-			end else begin
-				if (simsoc_blackparrotrv64_mmio_axi_ar_valid) begin
-					axi2axilite1_next_state = 1'd1;
-				end else begin
-					if (simsoc_blackparrotrv64_mmio_axi_aw_valid) begin
-						axi2axilite1_next_state = 2'd2;
-					end
-				end
-			end
-		end
-	endcase
-end
-assign csrbankarray_csrbank1_en0_re = ((csrbankarray_csrbank1_sel & csrbankarray_interface1_bank_bus_we) & (csrbankarray_interface1_bank_bus_adr[4:0] == 4'd8));
-assign csrbankarray_csrbank1_load2_re = ((csrbankarray_csrbank1_sel & csrbankarray_interface1_bank_bus_we) & (csrbankarray_interface1_bank_bus_adr[4:0] == 1'd1));
-assign csrbankarray_csrbank1_load2_r = csrbankarray_interface1_bank_bus_dat_w[7:0];
-assign csrbankarray_csrbank1_load2_we = ((csrbankarray_csrbank1_sel & (~csrbankarray_interface1_bank_bus_we)) & (csrbankarray_interface1_bank_bus_adr[4:0] == 1'd1));
-always @(*) begin
-	simsoc_blackparrotrv64_mmio_axi_r_valid = 1'd0;
-	case (axi2axilite1_state)
-		1'd1: begin
-			simsoc_blackparrotrv64_mmio_axi_r_valid = simsoc_blackparrotrv64_axi2wishbone1_r_valid;
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		default: begin
-		end
-	endcase
-end
-assign csrbankarray_csrbank1_load2_w = simsoc_load_storage[23:16];
-always @(*) begin
-	simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_cmd_done_axi2axilite1_next_value0 = 1'd0;
-	case (axi2axilite1_state)
-		1'd1: begin
-			if ((simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_beat_valid & simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_beat_last)) begin
-				if (simsoc_blackparrotrv64_axi2wishbone1_ar_ready) begin
-					simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_cmd_done_axi2axilite1_next_value0 = 1'd1;
-				end
-			end
-		end
-		2'd2: begin
-			if ((simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_beat_valid & simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_beat_last)) begin
-				if (simsoc_blackparrotrv64_axi2wishbone1_aw_ready) begin
-					simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_cmd_done_axi2axilite1_next_value0 = 1'd1;
-				end
-			end
-		end
-		2'd3: begin
-		end
-		default: begin
-			simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_cmd_done_axi2axilite1_next_value0 = 1'd0;
-		end
-	endcase
-end
-always @(*) begin
-	simsoc_blackparrotrv64_mmio_axi_r_last = 1'd0;
-	case (axi2axilite1_state)
-		1'd1: begin
-			simsoc_blackparrotrv64_mmio_axi_r_last = simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_cmd_done;
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		default: begin
-		end
-	endcase
-end
-always @(*) begin
-	simsoc_blackparrotrv64_mmio_axi_r_payload_resp = 2'd0;
-	case (axi2axilite1_state)
-		1'd1: begin
-			simsoc_blackparrotrv64_mmio_axi_r_payload_resp = 1'd0;
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		default: begin
-		end
-	endcase
-end
-always @(*) begin
-	simsoc_blackparrotrv64_mmio_axi_r_payload_data = 64'd0;
-	case (axi2axilite1_state)
-		1'd1: begin
-			simsoc_blackparrotrv64_mmio_axi_r_payload_data = simsoc_blackparrotrv64_axi2wishbone1_r_payload_data;
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		default: begin
-		end
-	endcase
-end
-always @(*) begin
-	simsoc_blackparrotrv64_mmio_axi_r_payload_id = 4'd0;
-	case (axi2axilite1_state)
-		1'd1: begin
-			simsoc_blackparrotrv64_mmio_axi_r_payload_id = simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_beat_payload_id;
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		default: begin
-		end
-	endcase
-end
-always @(*) begin
-	simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_cmd_done_axi2axilite1_next_value_ce0 = 1'd0;
-	case (axi2axilite1_state)
-		1'd1: begin
-			if ((simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_beat_valid & simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_beat_last)) begin
-				if (simsoc_blackparrotrv64_axi2wishbone1_ar_ready) begin
-					simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_cmd_done_axi2axilite1_next_value_ce0 = 1'd1;
-				end
-			end
-		end
-		2'd2: begin
-			if ((simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_beat_valid & simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_beat_last)) begin
-				if (simsoc_blackparrotrv64_axi2wishbone1_aw_ready) begin
-					simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_cmd_done_axi2axilite1_next_value_ce0 = 1'd1;
-				end
-			end
-		end
-		2'd3: begin
-		end
-		default: begin
-			simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_cmd_done_axi2axilite1_next_value_ce0 = 1'd1;
-		end
-	endcase
-end
-assign csrbankarray_csrbank0_bus_errors2_re = ((csrbankarray_csrbank0_sel & csrbankarray_interface0_bank_bus_we) & (csrbankarray_interface0_bank_bus_adr[3:0] == 3'd6));
-always @(*) begin
-	simsoc_blackparrotrv64_mem_wb_dat_w = 64'd0;
-	case (axilite2wishbone0_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-			simsoc_blackparrotrv64_mem_wb_dat_w = simsoc_blackparrotrv64_axi2wishbone0_w_payload_data;
-		end
-		3'd4: begin
-		end
-		default: begin
-		end
-	endcase
-end
-assign csrbankarray_csrbank1_load0_re = ((csrbankarray_csrbank1_sel & csrbankarray_interface1_bank_bus_we) & (csrbankarray_interface1_bank_bus_adr[4:0] == 2'd3));
-assign sys_clk_1 = sys_clk;
-assign csrbankarray_csrbank1_load0_r = csrbankarray_interface1_bank_bus_dat_w[7:0];
-assign sys_rst = int_rst;
-assign csrbankarray_csrbank1_load0_we = ((csrbankarray_csrbank1_sel & (~csrbankarray_interface1_bank_bus_we)) & (csrbankarray_interface1_bank_bus_adr[4:0] == 2'd3));
-always @(*) begin
-	simsoc_blackparrotrv64_mem_wb_cyc = 1'd0;
-	case (axilite2wishbone0_state)
-		1'd1: begin
-			simsoc_blackparrotrv64_mem_wb_cyc = 1'd1;
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-			simsoc_blackparrotrv64_mem_wb_cyc = simsoc_blackparrotrv64_axi2wishbone0_w_valid;
-		end
-		3'd4: begin
-		end
-		default: begin
-		end
-	endcase
-end
-assign csrbankarray_csrbank1_load0_w = simsoc_load_storage[7:0];
-always @(*) begin
-	simsoc_blackparrotrv64_mem_wb_stb = 1'd0;
-	case (axilite2wishbone0_state)
-		1'd1: begin
-			simsoc_blackparrotrv64_mem_wb_stb = 1'd1;
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-			simsoc_blackparrotrv64_mem_wb_stb = simsoc_blackparrotrv64_axi2wishbone0_w_valid;
-		end
-		3'd4: begin
-		end
-		default: begin
-		end
-	endcase
-end
-always @(*) begin
-	simsoc_blackparrotrv64_mem_wb_ack = 1'd0;
-	case (converter0_state)
-		1'd1: begin
-			if ((simsoc_blackparrotrv64_mem_wb_stb & simsoc_blackparrotrv64_mem_wb_cyc)) begin
-				if (simsoc_blackparrotrv64_ibus_ack) begin
-					if (simsoc_blackparrotrv64_mem_dc_counter_done) begin
-						simsoc_blackparrotrv64_mem_wb_ack = 1'd1;
-					end
-				end
-			end else begin
-			end
-		end
-		2'd2: begin
-			if ((simsoc_blackparrotrv64_mem_wb_stb & simsoc_blackparrotrv64_mem_wb_cyc)) begin
-				if (simsoc_blackparrotrv64_ibus_ack) begin
-					if (simsoc_blackparrotrv64_mem_dc_counter_done) begin
-						simsoc_blackparrotrv64_mem_wb_ack = 1'd1;
-					end
-				end
-			end else begin
-			end
-		end
-		default: begin
-		end
-	endcase
-end
-assign serial_source_valid = sink_valid;
-always @(*) begin
-	simsoc_blackparrotrv64_mem_wb_we = 1'd0;
-	case (axilite2wishbone0_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-			simsoc_blackparrotrv64_mem_wb_we = 1'd1;
-		end
-		3'd4: begin
-		end
-		default: begin
-		end
-	endcase
-end
-assign csrbankarray_csrbank1_reload3_r = csrbankarray_interface1_bank_bus_dat_w[7:0];
-assign serial_source_data = sink_payload_data;
-assign csrbankarray_csrbank1_reload3_we = ((csrbankarray_csrbank1_sel & (~csrbankarray_interface1_bank_bus_we)) & (csrbankarray_interface1_bank_bus_adr[4:0] == 3'd4));
-assign csrbankarray_csrbank1_reload3_w = simsoc_reload_storage[31:24];
-assign serial_sink_ready = source_ready;
-always @(*) begin
-	simsoc_blackparrotrv64_mmio_wb_adr = 29'd0;
-	case (axilite2wishbone1_state)
-		1'd1: begin
-			simsoc_blackparrotrv64_mmio_wb_adr = simsoc_blackparrotrv64_axi2wishbone1_axi_lite2wishbone_r_addr[31:3];
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-			simsoc_blackparrotrv64_mmio_wb_adr = simsoc_blackparrotrv64_axi2wishbone1_axi_lite2wishbone_w_addr[31:3];
-		end
-		3'd4: begin
-		end
-		default: begin
-		end
-	endcase
-end
-always @(*) begin
-	simsoc_blackparrotrv64_mmio_wb_dat_w = 64'd0;
-	case (axilite2wishbone1_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-			simsoc_blackparrotrv64_mmio_wb_dat_w = simsoc_blackparrotrv64_axi2wishbone1_w_payload_data;
-		end
-		3'd4: begin
-		end
-		default: begin
-		end
-	endcase
-end
-assign sink_valid = uart_tx_fifo_source_valid;
-assign simsoc_blackparrotrv64_mmio_wb_dat_r = {simsoc_blackparrotrv64_dbus_dat_r, simsoc_blackparrotrv64_mmio_dc_cached_data[63:32]};
-assign sink_ready = serial_source_ready;
-always @(*) begin
-	simsoc_blackparrotrv64_mmio_wb_sel = 8'd0;
-	case (axilite2wishbone1_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-			simsoc_blackparrotrv64_mmio_wb_sel = simsoc_blackparrotrv64_axi2wishbone1_w_payload_strb;
-		end
-		3'd4: begin
-		end
-		default: begin
-		end
-	endcase
-end
-assign sink_first = uart_tx_fifo_source_first;
-always @(*) begin
-	simsoc_blackparrotrv64_mmio_wb_cyc = 1'd0;
-	case (axilite2wishbone1_state)
-		1'd1: begin
-			simsoc_blackparrotrv64_mmio_wb_cyc = 1'd1;
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-			simsoc_blackparrotrv64_mmio_wb_cyc = simsoc_blackparrotrv64_axi2wishbone1_w_valid;
-		end
-		3'd4: begin
-		end
-		default: begin
-		end
-	endcase
-end
-assign sink_last = uart_tx_fifo_source_last;
-always @(*) begin
-	simsoc_blackparrotrv64_mmio_wb_stb = 1'd0;
-	case (axilite2wishbone1_state)
-		1'd1: begin
-			simsoc_blackparrotrv64_mmio_wb_stb = 1'd1;
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-			simsoc_blackparrotrv64_mmio_wb_stb = simsoc_blackparrotrv64_axi2wishbone1_w_valid;
-		end
-		3'd4: begin
-		end
-		default: begin
-		end
-	endcase
-end
-assign sink_payload_data = uart_tx_fifo_source_payload_data;
-always @(*) begin
-	simsoc_blackparrotrv64_mmio_wb_ack = 1'd0;
-	case (converter1_state)
-		1'd1: begin
-			if ((simsoc_blackparrotrv64_mmio_wb_stb & simsoc_blackparrotrv64_mmio_wb_cyc)) begin
-				if (simsoc_blackparrotrv64_dbus_ack) begin
-					if (simsoc_blackparrotrv64_mmio_dc_counter_done) begin
-						simsoc_blackparrotrv64_mmio_wb_ack = 1'd1;
-					end
-				end
-			end else begin
-			end
-		end
-		2'd2: begin
-			if ((simsoc_blackparrotrv64_mmio_wb_stb & simsoc_blackparrotrv64_mmio_wb_cyc)) begin
-				if (simsoc_blackparrotrv64_dbus_ack) begin
-					if (simsoc_blackparrotrv64_mmio_dc_counter_done) begin
-						simsoc_blackparrotrv64_mmio_wb_ack = 1'd1;
-					end
-				end
-			end else begin
-			end
-		end
-		default: begin
-		end
-	endcase
-end
-assign source_valid = serial_sink_valid;
-always @(*) begin
-	simsoc_blackparrotrv64_mmio_wb_we = 1'd0;
-	case (axilite2wishbone1_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-			simsoc_blackparrotrv64_mmio_wb_we = 1'd1;
-		end
-		3'd4: begin
-		end
-		default: begin
-		end
-	endcase
-end
-assign source_ready = uart_rx_fifo_sink_ready;
-assign csrbankarray_csrbank1_reload1_r = csrbankarray_interface1_bank_bus_dat_w[7:0];
-assign csrbankarray_csrbank1_reload1_we = ((csrbankarray_csrbank1_sel & (~csrbankarray_interface1_bank_bus_we)) & (csrbankarray_interface1_bank_bus_adr[4:0] == 3'd6));
-assign csrbankarray_csrbank1_reload1_w = simsoc_reload_storage[15:8];
-assign source_payload_data = serial_sink_data;
-assign simsoc_blackparrotrv64_ibus_adr = {simsoc_blackparrotrv64_mem_wb_adr, simsoc_blackparrotrv64_mem_dc_counter};
-always @(*) begin
-	simsoc_blackparrotrv64_ibus_dat_w = 32'd0;
-	case (simsoc_blackparrotrv64_mem_dc_counter)
-		1'd0: begin
-			simsoc_blackparrotrv64_ibus_dat_w = simsoc_blackparrotrv64_mem_wb_dat_w[31:0];
-		end
-		1'd1: begin
-			simsoc_blackparrotrv64_ibus_dat_w = simsoc_blackparrotrv64_mem_wb_dat_w[63:32];
-		end
-	endcase
-end
-assign csrbankarray_csrbank1_reload0_re = ((csrbankarray_csrbank1_sel & csrbankarray_interface1_bank_bus_we) & (csrbankarray_interface1_bank_bus_adr[4:0] == 3'd7));
-assign simsoc_blackparrotrv64_ibus_dat_r = shared_dat_r;
-always @(*) begin
-	simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_payload_len = 8'd0;
-	case (axi2axilite0_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		default: begin
-			if ((simsoc_blackparrotrv64_mem_axi_ar_valid & simsoc_blackparrotrv64_mem_axi_aw_valid)) begin
-				if (simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_last_ar_aw_n) begin
-					simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_payload_len = simsoc_blackparrotrv64_mem_axi_aw_payload_len;
-				end else begin
-					simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_payload_len = simsoc_blackparrotrv64_mem_axi_ar_payload_len;
-				end
-			end else begin
-				if (simsoc_blackparrotrv64_mem_axi_ar_valid) begin
-					simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_payload_len = simsoc_blackparrotrv64_mem_axi_ar_payload_len;
-				end else begin
-					if (simsoc_blackparrotrv64_mem_axi_aw_valid) begin
-						simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_payload_len = simsoc_blackparrotrv64_mem_axi_aw_payload_len;
-					end
-				end
-			end
-		end
-	endcase
-end
-always @(*) begin
-	simsoc_blackparrotrv64_ibus_sel = 4'd0;
-	case (simsoc_blackparrotrv64_mem_dc_counter)
-		1'd0: begin
-			simsoc_blackparrotrv64_ibus_sel = simsoc_blackparrotrv64_mem_wb_sel[7:0];
-		end
-		1'd1: begin
-			simsoc_blackparrotrv64_ibus_sel = simsoc_blackparrotrv64_mem_wb_sel[7:4];
-		end
-	endcase
-end
-assign csrbankarray_csrbank1_reload0_we = ((csrbankarray_csrbank1_sel & (~csrbankarray_interface1_bank_bus_we)) & (csrbankarray_interface1_bank_bus_adr[4:0] == 3'd7));
-always @(*) begin
-	simsoc_blackparrotrv64_ibus_cyc = 1'd0;
-	case (converter0_state)
-		1'd1: begin
-			simsoc_blackparrotrv64_ibus_cyc = 1'd1;
-		end
-		2'd2: begin
-			simsoc_blackparrotrv64_ibus_cyc = 1'd1;
-		end
-		default: begin
-		end
-	endcase
-end
-assign csrbankarray_csrbank1_en0_r = csrbankarray_interface1_bank_bus_dat_w[0];
-always @(*) begin
-	simsoc_blackparrotrv64_ibus_stb = 1'd0;
-	case (converter0_state)
-		1'd1: begin
-			if ((simsoc_blackparrotrv64_mem_wb_stb & simsoc_blackparrotrv64_mem_wb_cyc)) begin
-				simsoc_blackparrotrv64_ibus_stb = 1'd1;
-			end else begin
-			end
-		end
-		2'd2: begin
-			if ((simsoc_blackparrotrv64_mem_wb_stb & simsoc_blackparrotrv64_mem_wb_cyc)) begin
-				simsoc_blackparrotrv64_ibus_stb = 1'd1;
-			end else begin
-			end
-		end
-		default: begin
-		end
-	endcase
-end
-assign uart_txfull_status = (~uart_tx_fifo_sink_ready);
-assign simsoc_blackparrotrv64_ibus_ack = (shared_ack & (grant == 1'd0));
-assign uart_txfull_we = csrbankarray_csrbank2_txfull_we;
-always @(*) begin
-	simsoc_blackparrotrv64_ibus_we = 1'd0;
-	case (converter0_state)
-		1'd1: begin
-			simsoc_blackparrotrv64_ibus_we = 1'd1;
-		end
-		2'd2: begin
-		end
-		default: begin
-		end
-	endcase
-end
-assign uart_rxempty_status = (~uart_rx_fifo_source_valid);
-assign csrbankarray_csrbank1_en0_we = ((csrbankarray_csrbank1_sel & (~csrbankarray_interface1_bank_bus_we)) & (csrbankarray_interface1_bank_bus_adr[4:0] == 4'd8));
-assign simsoc_blackparrotrv64_ibus_err = (shared_err & (grant == 1'd0));
-assign uart_rxempty_we = csrbankarray_csrbank2_rxempty_we;
-assign simsoc_blackparrotrv64_dbus_adr = {simsoc_blackparrotrv64_mmio_wb_adr, simsoc_blackparrotrv64_mmio_dc_counter};
-assign uart_tx_status = uart_tx_trigger;
-always @(*) begin
-	simsoc_blackparrotrv64_dbus_dat_w = 32'd0;
-	case (simsoc_blackparrotrv64_mmio_dc_counter)
-		1'd0: begin
-			simsoc_blackparrotrv64_dbus_dat_w = simsoc_blackparrotrv64_mmio_wb_dat_w[31:0];
-		end
-		1'd1: begin
-			simsoc_blackparrotrv64_dbus_dat_w = simsoc_blackparrotrv64_mmio_wb_dat_w[63:32];
-		end
-	endcase
-end
-assign csrbankarray_csrbank1_update_value0_re = ((csrbankarray_csrbank1_sel & csrbankarray_interface1_bank_bus_we) & (csrbankarray_interface1_bank_bus_adr[4:0] == 4'd9));
-assign simsoc_blackparrotrv64_dbus_dat_r = shared_dat_r;
-assign uart_tx_trigger = (~uart_tx_fifo_sink_ready);
-always @(*) begin
-	simsoc_blackparrotrv64_dbus_sel = 4'd0;
-	case (simsoc_blackparrotrv64_mmio_dc_counter)
-		1'd0: begin
-			simsoc_blackparrotrv64_dbus_sel = simsoc_blackparrotrv64_mmio_wb_sel[7:0];
-		end
-		1'd1: begin
-			simsoc_blackparrotrv64_dbus_sel = simsoc_blackparrotrv64_mmio_wb_sel[7:4];
-		end
-	endcase
-end
-always @(*) begin
-	uart_tx_clear = 1'd0;
-	if ((uart_eventmanager_pending_re & uart_eventmanager_pending_r[0])) begin
-		uart_tx_clear = 1'd1;
-	end
-end
-always @(*) begin
-	simsoc_blackparrotrv64_dbus_cyc = 1'd0;
-	case (converter1_state)
-		1'd1: begin
-			simsoc_blackparrotrv64_dbus_cyc = 1'd1;
-		end
-		2'd2: begin
-			simsoc_blackparrotrv64_dbus_cyc = 1'd1;
-		end
-		default: begin
-		end
-	endcase
-end
-assign csrbankarray_csrbank1_update_value0_w = simsoc_update_value_storage;
-always @(*) begin
-	simsoc_blackparrotrv64_dbus_stb = 1'd0;
-	case (converter1_state)
-		1'd1: begin
-			if ((simsoc_blackparrotrv64_mmio_wb_stb & simsoc_blackparrotrv64_mmio_wb_cyc)) begin
-				simsoc_blackparrotrv64_dbus_stb = 1'd1;
-			end else begin
-			end
-		end
-		2'd2: begin
-			if ((simsoc_blackparrotrv64_mmio_wb_stb & simsoc_blackparrotrv64_mmio_wb_cyc)) begin
-				simsoc_blackparrotrv64_dbus_stb = 1'd1;
-			end else begin
-			end
-		end
-		default: begin
-		end
-	endcase
-end
-assign simsoc_blackparrotrv64_dbus_ack = (shared_ack & (grant == 1'd1));
-always @(*) begin
-	simsoc_blackparrotrv64_dbus_we = 1'd0;
-	case (converter1_state)
-		1'd1: begin
-			simsoc_blackparrotrv64_dbus_we = 1'd1;
-		end
-		2'd2: begin
-		end
-		default: begin
-		end
-	endcase
-end
-always @(*) begin
-	simsoc_blackparrotrv64_dbus_cti = 3'd0;
-	if (simsoc_blackparrotrv64_mmio_dc_counter_done) begin
-		simsoc_blackparrotrv64_dbus_cti = 3'd7;
-	end else begin
-		simsoc_blackparrotrv64_dbus_cti = 2'd2;
-	end
-end
-assign csrbankarray_csrbank1_value3_we = ((csrbankarray_csrbank1_sel & (~csrbankarray_interface1_bank_bus_we)) & (csrbankarray_interface1_bank_bus_adr[4:0] == 4'd10));
-assign uart_rx_trigger = (~uart_rx_fifo_source_valid);
-always @(*) begin
-	uart_rx_clear = 1'd0;
-	if ((uart_eventmanager_pending_re & uart_eventmanager_pending_r[1])) begin
-		uart_rx_clear = 1'd1;
-	end
-end
-assign csrbankarray_csrbank1_value2_re = ((csrbankarray_csrbank1_sel & csrbankarray_interface1_bank_bus_we) & (csrbankarray_interface1_bank_bus_adr[4:0] == 4'd11));
-assign csrbankarray_csrbank1_value2_r = csrbankarray_interface1_bank_bus_dat_w[7:0];
-assign csrbankarray_csrbank1_value2_we = ((csrbankarray_csrbank1_sel & (~csrbankarray_interface1_bank_bus_we)) & (csrbankarray_interface1_bank_bus_adr[4:0] == 4'd11));
-assign simsoc_blackparrotrv64_mem_wb_dat_r = {simsoc_blackparrotrv64_ibus_dat_r, simsoc_blackparrotrv64_mem_dc_cached_data[63:32]};
-assign uart_eventmanager_status_re = ((csrbankarray_csrbank2_sel & csrbankarray_interface2_bank_bus_we) & (csrbankarray_interface2_bank_bus_adr[2:0] == 2'd3));
-always @(*) begin
-	simsoc_blackparrotrv64_axi2wishbone0_aw_valid = 1'd0;
-	case (axi2axilite0_state)
-		1'd1: begin
-		end
-		2'd2: begin
-			simsoc_blackparrotrv64_axi2wishbone0_aw_valid = (simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_beat_valid & (~simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_cmd_done));
-		end
-		2'd3: begin
-		end
-		default: begin
-		end
-	endcase
-end
-assign csrbankarray_csrbank1_value1_re = ((csrbankarray_csrbank1_sel & csrbankarray_interface1_bank_bus_we) & (csrbankarray_interface1_bank_bus_adr[4:0] == 4'd12));
-always @(*) begin
-	simsoc_blackparrotrv64_axi2wishbone0_aw_ready = 1'd0;
-	case (axilite2wishbone0_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-			if (simsoc_blackparrotrv64_mem_wb_ack) begin
-				simsoc_blackparrotrv64_axi2wishbone0_aw_ready = 1'd1;
-			end
-		end
-		3'd4: begin
-		end
-		default: begin
-		end
-	endcase
-end
-assign csrbankarray_csrbank1_value1_r = csrbankarray_interface1_bank_bus_dat_w[7:0];
-always @(*) begin
-	uart_eventmanager_status_w = 2'd0;
-	uart_eventmanager_status_w[0] = uart_tx_status;
-	uart_eventmanager_status_w[1] = uart_rx_status;
-end
-assign csrbankarray_csrbank1_value1_we = ((csrbankarray_csrbank1_sel & (~csrbankarray_interface1_bank_bus_we)) & (csrbankarray_interface1_bank_bus_adr[4:0] == 4'd12));
-assign csrbankarray_csrbank1_value1_w = simsoc_value_status[15:8];
-always @(*) begin
-	simsoc_blackparrotrv64_axi2wishbone0_aw_payload_addr = 32'd0;
-	case (axi2axilite0_state)
-		1'd1: begin
-		end
-		2'd2: begin
-			simsoc_blackparrotrv64_axi2wishbone0_aw_payload_addr = simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_beat_payload_addr;
-		end
-		2'd3: begin
-		end
-		default: begin
-		end
-	endcase
-end
-always @(*) begin
-	simsoc_blackparrotrv64_mem_wb_sel = 8'd0;
-	case (axilite2wishbone0_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-			simsoc_blackparrotrv64_mem_wb_sel = simsoc_blackparrotrv64_axi2wishbone0_w_payload_strb;
-		end
-		3'd4: begin
-		end
-		default: begin
-		end
-	endcase
-end
-always @(*) begin
-	simsoc_blackparrotrv64_axi2wishbone0_w_valid = 1'd0;
-	case (axi2axilite0_state)
-		1'd1: begin
-		end
-		2'd2: begin
-			simsoc_blackparrotrv64_axi2wishbone0_w_valid = simsoc_blackparrotrv64_mem_axi_w_valid;
-		end
-		2'd3: begin
-		end
-		default: begin
-		end
-	endcase
-end
-assign csrbankarray_csrbank1_value0_re = ((csrbankarray_csrbank1_sel & csrbankarray_interface1_bank_bus_we) & (csrbankarray_interface1_bank_bus_adr[4:0] == 4'd13));
-always @(*) begin
-	simsoc_blackparrotrv64_axi2wishbone0_w_ready = 1'd0;
-	case (axilite2wishbone0_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-			if (simsoc_blackparrotrv64_mem_wb_ack) begin
-				simsoc_blackparrotrv64_axi2wishbone0_w_ready = 1'd1;
-			end
-		end
-		3'd4: begin
-		end
-		default: begin
-		end
-	endcase
-end
-always @(*) begin
-	uart_eventmanager_pending_w = 2'd0;
-	uart_eventmanager_pending_w[0] = uart_tx_pending;
-	uart_eventmanager_pending_w[1] = uart_rx_pending;
-end
-assign csrbankarray_csrbank1_value0_we = ((csrbankarray_csrbank1_sel & (~csrbankarray_interface1_bank_bus_we)) & (csrbankarray_interface1_bank_bus_adr[4:0] == 4'd13));
-assign csrbankarray_csrbank1_value0_w = simsoc_value_status[7:0];
-always @(*) begin
-	simsoc_blackparrotrv64_axi2wishbone0_w_payload_data = 64'd0;
-	case (axi2axilite0_state)
-		1'd1: begin
-		end
-		2'd2: begin
-			simsoc_blackparrotrv64_axi2wishbone0_w_payload_data = simsoc_blackparrotrv64_mem_axi_w_payload_data;
-		end
-		2'd3: begin
-		end
-		default: begin
-		end
-	endcase
-end
-always @(*) begin
-	simsoc_blackparrotrv64_axi2wishbone0_w_payload_strb = 8'd0;
-	case (axi2axilite0_state)
-		1'd1: begin
-		end
-		2'd2: begin
-			simsoc_blackparrotrv64_axi2wishbone0_w_payload_strb = simsoc_blackparrotrv64_mem_axi_w_payload_strb;
-		end
-		2'd3: begin
-		end
-		default: begin
-		end
-	endcase
-end
-assign por_clk = sys_clk;
-always @(*) begin
-	simsoc_blackparrotrv64_axi2wishbone0_b_valid = 1'd0;
-	case (axilite2wishbone0_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		3'd4: begin
-			simsoc_blackparrotrv64_axi2wishbone0_b_valid = 1'd1;
-		end
-		default: begin
-		end
-	endcase
-end
-assign csrbankarray_csrbank1_ev_enable0_r = csrbankarray_interface1_bank_bus_dat_w[0];
-assign simsoc_blackparrotrv64_axi2wishbone0_b_ready = 1'd1;
-assign csrbankarray_csrbank1_ev_enable0_we = ((csrbankarray_csrbank1_sel & (~csrbankarray_interface1_bank_bus_we)) & (csrbankarray_interface1_bank_bus_adr[4:0] == 5'd16));
-assign csrbankarray_csrbank1_ev_enable0_w = simsoc_eventmanager_storage;
-always @(*) begin
-	simsoc_blackparrotrv64_axi2wishbone0_b_payload_resp = 2'd0;
-	case (axilite2wishbone0_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		3'd4: begin
-			simsoc_blackparrotrv64_axi2wishbone0_b_payload_resp = 1'd0;
-		end
-		default: begin
-		end
-	endcase
-end
-assign csrbankarray_csrbank1_sel = (csrbankarray_interface1_bank_bus_adr[13:9] == 2'd3);
-always @(*) begin
-	simsoc_blackparrotrv64_axi2wishbone0_ar_valid = 1'd0;
-	case (axi2axilite0_state)
-		1'd1: begin
-			simsoc_blackparrotrv64_axi2wishbone0_ar_valid = (simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_beat_valid & (~simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_cmd_done));
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		default: begin
-		end
-	endcase
-end
-always @(*) begin
-	simsoc_blackparrotrv64_axi2wishbone0_ar_ready = 1'd0;
-	case (axilite2wishbone0_state)
-		1'd1: begin
-			if (simsoc_blackparrotrv64_mem_wb_ack) begin
-				simsoc_blackparrotrv64_axi2wishbone0_ar_ready = 1'd1;
-			end
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		3'd4: begin
-		end
-		default: begin
-		end
-	endcase
-end
-assign simsoc_bus_wishbone_sel = shared_sel;
-assign uart_tx_fifo_sink_valid = uart_rxtx_re;
-assign uart_tx_fifo_sink_ready = uart_tx_fifo_syncfifo_writable;
-always @(*) begin
-	simsoc_blackparrotrv64_axi2wishbone0_ar_payload_addr = 32'd0;
-	case (axi2axilite0_state)
-		1'd1: begin
-			simsoc_blackparrotrv64_axi2wishbone0_ar_payload_addr = simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_beat_payload_addr;
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		default: begin
-		end
-	endcase
-end
-always @(*) begin
-	simsoc_blackparrotrv64_axi2wishbone0_r_valid = 1'd0;
-	case (axilite2wishbone0_state)
-		1'd1: begin
-		end
-		2'd2: begin
-			simsoc_blackparrotrv64_axi2wishbone0_r_valid = 1'd1;
-		end
-		2'd3: begin
-		end
-		3'd4: begin
-		end
-		default: begin
-		end
-	endcase
-end
-always @(*) begin
-	simsoc_blackparrotrv64_axi2wishbone0_r_ready = 1'd0;
-	case (axi2axilite0_state)
-		1'd1: begin
-			simsoc_blackparrotrv64_axi2wishbone0_r_ready = simsoc_blackparrotrv64_mem_axi_r_ready;
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		default: begin
-		end
-	endcase
-end
-assign uart_tx_fifo_sink_payload_data = uart_rxtx_r;
-assign uart_tx_fifo_source_valid = uart_tx_fifo_readable;
-assign uart_tx_fifo_source_ready = sink_ready;
-always @(*) begin
-	simsoc_blackparrotrv64_axi2wishbone0_r_payload_resp = 2'd0;
-	case (axilite2wishbone0_state)
-		1'd1: begin
-		end
-		2'd2: begin
-			simsoc_blackparrotrv64_axi2wishbone0_r_payload_resp = 1'd0;
-		end
-		2'd3: begin
-		end
-		3'd4: begin
-		end
-		default: begin
-		end
-	endcase
-end
-assign uart_tx_fifo_source_first = uart_tx_fifo_fifo_out_first;
-always @(*) begin
-	simsoc_blackparrotrv64_axi2wishbone0_r_payload_data = 64'd0;
-	case (axilite2wishbone0_state)
-		1'd1: begin
-		end
-		2'd2: begin
-			simsoc_blackparrotrv64_axi2wishbone0_r_payload_data = simsoc_blackparrotrv64_axi2wishbone0_axi_lite2wishbone_data;
-		end
-		2'd3: begin
-		end
-		3'd4: begin
-		end
-		default: begin
-		end
-	endcase
-end
-assign uart_tx_fifo_source_last = uart_tx_fifo_fifo_out_last;
-assign simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_sink_valid = simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_valid;
-assign uart_tx_fifo_source_payload_data = uart_tx_fifo_fifo_out_payload_data;
-assign simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_sink_ready = simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_pipe_ce;
-assign csrbankarray_csrbank1_reload3_re = ((csrbankarray_csrbank1_sel & csrbankarray_interface1_bank_bus_we) & (csrbankarray_interface1_bank_bus_adr[4:0] == 3'd4));
-assign simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_sink_first = simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_first;
-assign simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_sink_last = simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_last;
-assign uart_tx_fifo_re = uart_tx_fifo_source_ready;
-assign simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_sink_payload_addr = simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_payload_addr;
-assign simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_sink_payload_burst = simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_payload_burst;
-assign simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_sink_payload_len = simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_payload_len;
-assign simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_sink_payload_size = simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_payload_size;
-assign uart_tx_fifo_syncfifo_we = uart_tx_fifo_sink_valid;
-assign simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_sink_payload_lock = simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_payload_lock;
-assign uart_tx_fifo_syncfifo_writable = (uart_tx_fifo_level0 != 5'd16);
-assign simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_sink_payload_prot = simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_payload_prot;
-assign uart_tx_fifo_syncfifo_re = (uart_tx_fifo_syncfifo_readable & ((~uart_tx_fifo_readable) | uart_tx_fifo_re));
-assign simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_sink_payload_cache = simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_payload_cache;
-assign uart_tx_fifo_syncfifo_readable = (uart_tx_fifo_level0 != 1'd0);
-assign simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_sink_payload_qos = simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_payload_qos;
-assign uart_tx_fifo_syncfifo_din = {uart_tx_fifo_fifo_in_last, uart_tx_fifo_fifo_in_first, uart_tx_fifo_fifo_in_payload_data};
-assign simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_sink_payload_id = simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_payload_id;
-assign uart_tx_fifo_syncfifo_dout = uart_tx_fifo_rdport_dat_r;
-assign simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_source_valid = simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_valid_n;
-always @(*) begin
-	simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_source_ready = 1'd0;
-	if (simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_beat_ready) begin
-		if (simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_beat_last) begin
-			simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_source_ready = 1'd1;
-		end
-	end
-end
-assign simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_source_first = simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_first_n;
-assign csrbankarray_csrbank0_scratch1_we = ((csrbankarray_csrbank0_sel & (~csrbankarray_interface0_bank_bus_we)) & (csrbankarray_interface0_bank_bus_adr[3:0] == 2'd3));
-assign simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_source_last = simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_last_n;
-always @(*) begin
-	uart_tx_fifo_wrport_adr = 4'd0;
-	if (uart_tx_fifo_replace) begin
-		uart_tx_fifo_wrport_adr = (uart_tx_fifo_produce - 1'd1);
-	end else begin
-		uart_tx_fifo_wrport_adr = uart_tx_fifo_produce;
-	end
-end
-assign uart_tx_fifo_wrport_we = (uart_tx_fifo_syncfifo_we & (uart_tx_fifo_syncfifo_writable | uart_tx_fifo_replace));
-assign csrbankarray_csrbank1_value3_r = csrbankarray_interface1_bank_bus_dat_w[7:0];
-assign uart_tx_fifo_wrport_dat_w = uart_tx_fifo_syncfifo_din;
-assign csrbankarray_interface2_bank_bus_dat_w = csrcon_dat_w;
-assign csrbankarray_csrbank1_load1_re = ((csrbankarray_csrbank1_sel & csrbankarray_interface1_bank_bus_we) & (csrbankarray_interface1_bank_bus_adr[4:0] == 2'd2));
-assign simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_pipe_ce = (simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_source_ready | (~simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_valid_n));
-assign simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_busy = (1'd0 | simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_valid_n);
-assign uart_tx_fifo_do_read = (uart_tx_fifo_syncfifo_readable & uart_tx_fifo_syncfifo_re);
-assign uart_tx_fifo_rdport_adr = uart_tx_fifo_consume;
-assign uart_tx_fifo_rdport_re = uart_tx_fifo_do_read;
-always @(*) begin
-	simsoc_blackparrotrv64_mem_wb_adr = 29'd0;
-	case (axilite2wishbone0_state)
-		1'd1: begin
-			simsoc_blackparrotrv64_mem_wb_adr = simsoc_blackparrotrv64_axi2wishbone0_axi_lite2wishbone_r_addr[31:3];
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-			simsoc_blackparrotrv64_mem_wb_adr = simsoc_blackparrotrv64_axi2wishbone0_axi_lite2wishbone_w_addr[31:3];
-		end
-		3'd4: begin
-		end
-		default: begin
-		end
-	endcase
-end
-assign uart_rx_fifo_fifo_in_last = uart_rx_fifo_sink_last;
-always @(*) begin
-	simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_valid = 1'd0;
-	case (axi2axilite0_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		default: begin
-			if ((simsoc_blackparrotrv64_mem_axi_ar_valid & simsoc_blackparrotrv64_mem_axi_aw_valid)) begin
-				if (simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_last_ar_aw_n) begin
-					simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_valid = simsoc_blackparrotrv64_mem_axi_aw_valid;
-				end else begin
-					simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_valid = simsoc_blackparrotrv64_mem_axi_ar_valid;
-				end
-			end else begin
-				if (simsoc_blackparrotrv64_mem_axi_ar_valid) begin
-					simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_valid = simsoc_blackparrotrv64_mem_axi_ar_valid;
-				end else begin
-					if (simsoc_blackparrotrv64_mem_axi_aw_valid) begin
-						simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_valid = simsoc_blackparrotrv64_mem_axi_aw_valid;
-					end
-				end
-			end
-		end
-	endcase
-end
-assign csrbankarray_csrbank1_reload2_re = ((csrbankarray_csrbank1_sel & csrbankarray_interface1_bank_bus_we) & (csrbankarray_interface1_bank_bus_adr[4:0] == 3'd5));
-assign simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_ready = simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_sink_ready;
-always @(*) begin
-	simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_first = 1'd0;
-	case (axi2axilite0_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		default: begin
-			if ((simsoc_blackparrotrv64_mem_axi_ar_valid & simsoc_blackparrotrv64_mem_axi_aw_valid)) begin
-				if (simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_last_ar_aw_n) begin
-					simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_first = simsoc_blackparrotrv64_mem_axi_aw_first;
-				end else begin
-					simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_first = simsoc_blackparrotrv64_mem_axi_ar_first;
-				end
-			end else begin
-				if (simsoc_blackparrotrv64_mem_axi_ar_valid) begin
-					simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_first = simsoc_blackparrotrv64_mem_axi_ar_first;
-				end else begin
-					if (simsoc_blackparrotrv64_mem_axi_aw_valid) begin
-						simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_first = simsoc_blackparrotrv64_mem_axi_aw_first;
-					end
-				end
-			end
-		end
-	endcase
-end
-always @(*) begin
-	simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_last = 1'd0;
-	case (axi2axilite0_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		default: begin
-			if ((simsoc_blackparrotrv64_mem_axi_ar_valid & simsoc_blackparrotrv64_mem_axi_aw_valid)) begin
-				if (simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_last_ar_aw_n) begin
-					simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_last = simsoc_blackparrotrv64_mem_axi_aw_last;
-				end else begin
-					simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_last = simsoc_blackparrotrv64_mem_axi_ar_last;
-				end
-			end else begin
-				if (simsoc_blackparrotrv64_mem_axi_ar_valid) begin
-					simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_last = simsoc_blackparrotrv64_mem_axi_ar_last;
-				end else begin
-					if (simsoc_blackparrotrv64_mem_axi_aw_valid) begin
-						simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_last = simsoc_blackparrotrv64_mem_axi_aw_last;
-					end
-				end
-			end
-		end
-	endcase
-end
-always @(*) begin
-	simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_payload_addr = 32'd0;
-	case (axi2axilite0_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		default: begin
-			if ((simsoc_blackparrotrv64_mem_axi_ar_valid & simsoc_blackparrotrv64_mem_axi_aw_valid)) begin
-				if (simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_last_ar_aw_n) begin
-					simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_payload_addr = simsoc_blackparrotrv64_mem_axi_aw_payload_addr;
-				end else begin
-					simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_payload_addr = simsoc_blackparrotrv64_mem_axi_ar_payload_addr;
-				end
-			end else begin
-				if (simsoc_blackparrotrv64_mem_axi_ar_valid) begin
-					simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_payload_addr = simsoc_blackparrotrv64_mem_axi_ar_payload_addr;
-				end else begin
-					if (simsoc_blackparrotrv64_mem_axi_aw_valid) begin
-						simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_payload_addr = simsoc_blackparrotrv64_mem_axi_aw_payload_addr;
-					end
-				end
-			end
-		end
-	endcase
-end
-always @(*) begin
-	simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_payload_burst = 2'd0;
-	case (axi2axilite0_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		default: begin
-			if ((simsoc_blackparrotrv64_mem_axi_ar_valid & simsoc_blackparrotrv64_mem_axi_aw_valid)) begin
-				if (simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_last_ar_aw_n) begin
-					simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_payload_burst = simsoc_blackparrotrv64_mem_axi_aw_payload_burst;
-				end else begin
-					simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_payload_burst = simsoc_blackparrotrv64_mem_axi_ar_payload_burst;
-				end
-			end else begin
-				if (simsoc_blackparrotrv64_mem_axi_ar_valid) begin
-					simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_payload_burst = simsoc_blackparrotrv64_mem_axi_ar_payload_burst;
-				end else begin
-					if (simsoc_blackparrotrv64_mem_axi_aw_valid) begin
-						simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_payload_burst = simsoc_blackparrotrv64_mem_axi_aw_payload_burst;
-					end
-				end
-			end
-		end
-	endcase
-end
-always @(*) begin
-	simsoc_blackparrotrv64_axi2wishbone1_aw_valid = 1'd0;
-	case (axi2axilite1_state)
-		1'd1: begin
-		end
-		2'd2: begin
-			simsoc_blackparrotrv64_axi2wishbone1_aw_valid = (simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_beat_valid & (~simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_cmd_done));
-		end
-		2'd3: begin
-		end
-		default: begin
-		end
-	endcase
-end
-assign uart_tx_fifo_level1 = (uart_tx_fifo_level0 + uart_tx_fifo_readable);
-assign csrbankarray_csrbank1_reload2_r = csrbankarray_interface1_bank_bus_dat_w[7:0];
-always @(*) begin
-	simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_payload_size = 4'd0;
-	case (axi2axilite0_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		default: begin
-			if ((simsoc_blackparrotrv64_mem_axi_ar_valid & simsoc_blackparrotrv64_mem_axi_aw_valid)) begin
-				if (simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_last_ar_aw_n) begin
-					simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_payload_size = simsoc_blackparrotrv64_mem_axi_aw_payload_size;
-				end else begin
-					simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_payload_size = simsoc_blackparrotrv64_mem_axi_ar_payload_size;
-				end
-			end else begin
-				if (simsoc_blackparrotrv64_mem_axi_ar_valid) begin
-					simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_payload_size = simsoc_blackparrotrv64_mem_axi_ar_payload_size;
-				end else begin
-					if (simsoc_blackparrotrv64_mem_axi_aw_valid) begin
-						simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_payload_size = simsoc_blackparrotrv64_mem_axi_aw_payload_size;
-					end
-				end
-			end
-		end
-	endcase
-end
-assign csrbankarray_csrbank1_en0_w = simsoc_en_storage;
-always @(*) begin
-	simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_payload_lock = 2'd0;
-	case (axi2axilite0_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		default: begin
-			if ((simsoc_blackparrotrv64_mem_axi_ar_valid & simsoc_blackparrotrv64_mem_axi_aw_valid)) begin
-				if (simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_last_ar_aw_n) begin
-					simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_payload_lock = simsoc_blackparrotrv64_mem_axi_aw_payload_lock;
-				end else begin
-					simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_payload_lock = simsoc_blackparrotrv64_mem_axi_ar_payload_lock;
-				end
-			end else begin
-				if (simsoc_blackparrotrv64_mem_axi_ar_valid) begin
-					simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_payload_lock = simsoc_blackparrotrv64_mem_axi_ar_payload_lock;
-				end else begin
-					if (simsoc_blackparrotrv64_mem_axi_aw_valid) begin
-						simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_payload_lock = simsoc_blackparrotrv64_mem_axi_aw_payload_lock;
-					end
-				end
-			end
-		end
-	endcase
-end
-always @(*) begin
-	array_muxed2 = 4'd0;
-	case (grant)
-		1'd0: begin
-			array_muxed2 = simsoc_blackparrotrv64_ibus_sel;
-		end
-		default: begin
-			array_muxed2 = simsoc_blackparrotrv64_dbus_sel;
-		end
-	endcase
-end
-always @(*) begin
-	simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_payload_prot = 3'd0;
-	case (axi2axilite0_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		default: begin
-			if ((simsoc_blackparrotrv64_mem_axi_ar_valid & simsoc_blackparrotrv64_mem_axi_aw_valid)) begin
-				if (simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_last_ar_aw_n) begin
-					simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_payload_prot = simsoc_blackparrotrv64_mem_axi_aw_payload_prot;
-				end else begin
-					simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_payload_prot = simsoc_blackparrotrv64_mem_axi_ar_payload_prot;
-				end
-			end else begin
-				if (simsoc_blackparrotrv64_mem_axi_ar_valid) begin
-					simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_payload_prot = simsoc_blackparrotrv64_mem_axi_ar_payload_prot;
-				end else begin
-					if (simsoc_blackparrotrv64_mem_axi_aw_valid) begin
-						simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_payload_prot = simsoc_blackparrotrv64_mem_axi_aw_payload_prot;
-					end
-				end
-			end
-		end
-	endcase
-end
-assign uart_tx_fifo_fifo_in_payload_data = uart_tx_fifo_sink_payload_data;
-assign uart_tx_fifo_fifo_in_first = uart_tx_fifo_sink_first;
-assign {uart_rx_fifo_fifo_out_last, uart_rx_fifo_fifo_out_first, uart_rx_fifo_fifo_out_payload_data} = uart_rx_fifo_syncfifo_dout;
-assign uart_tx_fifo_fifo_in_last = uart_tx_fifo_sink_last;
-assign csrbankarray_csrbank1_reload2_we = ((csrbankarray_csrbank1_sel & (~csrbankarray_interface1_bank_bus_we)) & (csrbankarray_interface1_bank_bus_adr[4:0] == 3'd5));
-assign {uart_tx_fifo_fifo_out_last, uart_tx_fifo_fifo_out_first, uart_tx_fifo_fifo_out_payload_data} = uart_tx_fifo_syncfifo_dout;
-assign {uart_tx_fifo_fifo_out_last, uart_tx_fifo_fifo_out_first, uart_tx_fifo_fifo_out_payload_data} = uart_tx_fifo_syncfifo_dout;
-assign {uart_tx_fifo_fifo_out_last, uart_tx_fifo_fifo_out_first, uart_tx_fifo_fifo_out_payload_data} = uart_tx_fifo_syncfifo_dout;
-assign simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_beat_last = (simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_beat_count == simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_source_payload_len);
-assign simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_beat_payload_addr = (simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_source_payload_addr + simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_beat_offset);
-assign uart_rx_fifo_sink_valid = source_valid;
-assign csrbankarray_csrbank1_reload2_w = simsoc_reload_storage[23:16];
-assign uart_rx_fifo_sink_ready = uart_rx_fifo_syncfifo_writable;
-assign uart_rx_fifo_sink_first = source_first;
-always @(*) begin
-	array_muxed3 = 1'd0;
-	case (grant)
-		1'd0: begin
-			array_muxed3 = simsoc_blackparrotrv64_ibus_cyc;
-		end
-		default: begin
-			array_muxed3 = simsoc_blackparrotrv64_dbus_cyc;
-		end
-	endcase
-end
-assign uart_rx_fifo_sink_last = source_last;
-assign uart_rx_fifo_sink_payload_data = source_payload_data;
-assign uart_rx_fifo_source_valid = uart_rx_fifo_readable;
-assign uart_rx_fifo_source_ready = uart_rx_clear;
-assign uart_rx_fifo_source_first = uart_rx_fifo_fifo_out_first;
-assign uart_rx_fifo_source_last = uart_rx_fifo_fifo_out_last;
-assign uart_rx_fifo_source_payload_data = uart_rx_fifo_fifo_out_payload_data;
-assign csrbankarray_interface0_bank_bus_dat_w = csrcon_dat_w;
-assign simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_beat_wrap = (simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_source_payload_len <<< simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_source_payload_size);
-assign uart_rx_fifo_re = uart_rx_fifo_source_ready;
-always @(*) begin
-	array_muxed4 = 1'd0;
-	case (grant)
-		1'd0: begin
-			array_muxed4 = simsoc_blackparrotrv64_ibus_stb;
-		end
-		default: begin
-			array_muxed4 = simsoc_blackparrotrv64_dbus_stb;
-		end
-	endcase
-end
-assign csrbankarray_csrbank1_reload1_re = ((csrbankarray_csrbank1_sel & csrbankarray_interface1_bank_bus_we) & (csrbankarray_interface1_bank_bus_adr[4:0] == 3'd6));
-always @(*) begin
-	simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_payload_cache = 4'd0;
-	case (axi2axilite0_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		default: begin
-			if ((simsoc_blackparrotrv64_mem_axi_ar_valid & simsoc_blackparrotrv64_mem_axi_aw_valid)) begin
-				if (simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_last_ar_aw_n) begin
-					simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_payload_cache = simsoc_blackparrotrv64_mem_axi_aw_payload_cache;
-				end else begin
-					simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_payload_cache = simsoc_blackparrotrv64_mem_axi_ar_payload_cache;
-				end
-			end else begin
-				if (simsoc_blackparrotrv64_mem_axi_ar_valid) begin
-					simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_payload_cache = simsoc_blackparrotrv64_mem_axi_ar_payload_cache;
-				end else begin
-					if (simsoc_blackparrotrv64_mem_axi_aw_valid) begin
-						simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_payload_cache = simsoc_blackparrotrv64_mem_axi_aw_payload_cache;
-					end
-				end
-			end
-		end
-	endcase
-end
-assign uart_rx_fifo_syncfifo_writable = (uart_rx_fifo_level0 != 5'd16);
-assign uart_rx_fifo_syncfifo_re = (uart_rx_fifo_syncfifo_readable & ((~uart_rx_fifo_readable) | uart_rx_fifo_re));
-assign uart_rx_fifo_syncfifo_readable = (uart_rx_fifo_level0 != 1'd0);
-assign uart_rx_fifo_syncfifo_din = {uart_rx_fifo_fifo_in_last, uart_rx_fifo_fifo_in_first, uart_rx_fifo_fifo_in_payload_data};
-assign uart_rx_fifo_syncfifo_dout = uart_rx_fifo_rdport_dat_r;
-always @(*) begin
-	axi2axilite0_next_state = 2'd0;
-	axi2axilite0_next_state = axi2axilite0_state;
-	case (axi2axilite0_state)
-		1'd1: begin
-			if (((simsoc_blackparrotrv64_mem_axi_r_valid & simsoc_blackparrotrv64_mem_axi_r_last) & simsoc_blackparrotrv64_mem_axi_r_ready)) begin
-				axi2axilite0_next_state = 1'd0;
-			end
-		end
-		2'd2: begin
-			if (((simsoc_blackparrotrv64_mem_axi_w_valid & simsoc_blackparrotrv64_mem_axi_w_last) & simsoc_blackparrotrv64_mem_axi_w_ready)) begin
-				axi2axilite0_next_state = 2'd3;
-			end
-		end
-		2'd3: begin
-			if (simsoc_blackparrotrv64_mem_axi_b_ready) begin
-				axi2axilite0_next_state = 1'd0;
-			end
-		end
-		default: begin
-			if ((simsoc_blackparrotrv64_mem_axi_ar_valid & simsoc_blackparrotrv64_mem_axi_aw_valid)) begin
-				if (simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_last_ar_aw_n) begin
-					axi2axilite0_next_state = 2'd2;
-				end else begin
-					axi2axilite0_next_state = 1'd1;
-				end
-			end else begin
-				if (simsoc_blackparrotrv64_mem_axi_ar_valid) begin
-					axi2axilite0_next_state = 1'd1;
-				end else begin
-					if (simsoc_blackparrotrv64_mem_axi_aw_valid) begin
-						axi2axilite0_next_state = 2'd2;
-					end
-				end
-			end
-		end
-	endcase
-end
-always @(*) begin
-	uart_rx_fifo_wrport_adr = 4'd0;
-	if (uart_rx_fifo_replace) begin
-		uart_rx_fifo_wrport_adr = (uart_rx_fifo_produce - 1'd1);
-	end else begin
-		uart_rx_fifo_wrport_adr = uart_rx_fifo_produce;
-	end
-end
-assign uart_rx_fifo_wrport_we = (uart_rx_fifo_syncfifo_we & (uart_rx_fifo_syncfifo_writable | uart_rx_fifo_replace));
-assign uart_rx_fifo_wrport_dat_w = uart_rx_fifo_syncfifo_din;
-assign uart_rx_fifo_do_read = (uart_rx_fifo_syncfifo_readable & uart_rx_fifo_syncfifo_re);
-assign uart_rx_fifo_rdport_adr = uart_rx_fifo_consume;
-assign uart_rx_fifo_rdport_re = uart_rx_fifo_do_read;
-assign simsoc_blackparrotrv64_axi2wishbone0_axi_lite2wishbone_r_addr = (simsoc_blackparrotrv64_axi2wishbone0_ar_payload_addr - 1'd0);
-assign simsoc_blackparrotrv64_axi2wishbone0_axi_lite2wishbone_w_addr = (simsoc_blackparrotrv64_axi2wishbone0_aw_payload_addr - 1'd0);
-assign uart_rxtx_re = ((csrbankarray_csrbank2_sel & csrbankarray_interface2_bank_bus_we) & (csrbankarray_interface2_bank_bus_adr[2:0] == 1'd0));
-always @(*) begin
-	simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_payload_qos = 4'd0;
-	case (axi2axilite0_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		default: begin
-			if ((simsoc_blackparrotrv64_mem_axi_ar_valid & simsoc_blackparrotrv64_mem_axi_aw_valid)) begin
-				if (simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_last_ar_aw_n) begin
-					simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_payload_qos = simsoc_blackparrotrv64_mem_axi_aw_payload_qos;
-				end else begin
-					simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_payload_qos = simsoc_blackparrotrv64_mem_axi_ar_payload_qos;
-				end
-			end else begin
-				if (simsoc_blackparrotrv64_mem_axi_ar_valid) begin
-					simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_payload_qos = simsoc_blackparrotrv64_mem_axi_ar_payload_qos;
-				end else begin
-					if (simsoc_blackparrotrv64_mem_axi_aw_valid) begin
-						simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_payload_qos = simsoc_blackparrotrv64_mem_axi_aw_payload_qos;
-					end
-				end
-			end
-		end
-	endcase
-end
-assign uart_rx_fifo_level1 = (uart_rx_fifo_level0 + uart_rx_fifo_readable);
-assign csrbankarray_csrbank2_ev_enable0_r = csrbankarray_interface2_bank_bus_dat_w[1:0];
-assign uart_rxtx_r = csrbankarray_interface2_bank_bus_dat_w[7:0];
-always @(*) begin
-	array_muxed0 = 30'd0;
-	case (grant)
-		1'd0: begin
-			array_muxed0 = simsoc_blackparrotrv64_ibus_adr;
-		end
-		default: begin
-			array_muxed0 = simsoc_blackparrotrv64_dbus_adr;
-		end
-	endcase
-end
-assign uart_rx_fifo_fifo_in_payload_data = uart_rx_fifo_sink_payload_data;
-assign uart_rx_fifo_fifo_in_first = uart_rx_fifo_sink_first;
-always @(*) begin
-	array_muxed1 = 32'd0;
-	case (grant)
-		1'd0: begin
-			array_muxed1 = simsoc_blackparrotrv64_ibus_dat_w;
-		end
-		default: begin
-			array_muxed1 = simsoc_blackparrotrv64_dbus_dat_w;
-		end
-	endcase
-end
-assign simsoc_blackparrotrv64_mem_a2w_reset = (sys_rst | simsoc_blackparrotrv64_reset);
-assign csrbankarray_csrbank2_txfull_re = ((csrbankarray_csrbank2_sel & csrbankarray_interface2_bank_bus_we) & (csrbankarray_interface2_bank_bus_adr[2:0] == 1'd1));
-assign {uart_rx_fifo_fifo_out_last, uart_rx_fifo_fifo_out_first, uart_rx_fifo_fifo_out_payload_data} = uart_rx_fifo_syncfifo_dout;
-assign csrbankarray_csrbank2_txfull_r = csrbankarray_interface2_bank_bus_dat_w[0];
-always @(*) begin
-	simsoc_blackparrotrv64_axi2wishbone1_aw_ready = 1'd0;
-	case (axilite2wishbone1_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-			if (simsoc_blackparrotrv64_mmio_wb_ack) begin
-				simsoc_blackparrotrv64_axi2wishbone1_aw_ready = 1'd1;
-			end
-		end
-		3'd4: begin
-		end
-		default: begin
-		end
-	endcase
-end
-assign csrbankarray_csrbank2_txfull_we = ((csrbankarray_csrbank2_sel & (~csrbankarray_interface2_bank_bus_we)) & (csrbankarray_interface2_bank_bus_adr[2:0] == 1'd1));
-assign {uart_rx_fifo_fifo_out_last, uart_rx_fifo_fifo_out_first, uart_rx_fifo_fifo_out_payload_data} = uart_rx_fifo_syncfifo_dout;
-assign csrbankarray_csrbank2_txfull_w = uart_txfull_status;
-always @(*) begin
-	simsoc_blackparrotrv64_axi2wishbone1_aw_payload_addr = 32'd0;
-	case (axi2axilite1_state)
-		1'd1: begin
-		end
-		2'd2: begin
-			simsoc_blackparrotrv64_axi2wishbone1_aw_payload_addr = simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_beat_payload_addr;
-		end
-		2'd3: begin
-		end
-		default: begin
-		end
-	endcase
-end
-assign csrbankarray_csrbank2_rxempty_re = ((csrbankarray_csrbank2_sel & csrbankarray_interface2_bank_bus_we) & (csrbankarray_interface2_bank_bus_adr[2:0] == 2'd2));
-always @(*) begin
-	simsoc_blackparrotrv64_axi2wishbone1_w_valid = 1'd0;
-	case (axi2axilite1_state)
-		1'd1: begin
-		end
-		2'd2: begin
-			simsoc_blackparrotrv64_axi2wishbone1_w_valid = simsoc_blackparrotrv64_mmio_axi_w_valid;
-		end
-		2'd3: begin
-		end
-		default: begin
-		end
-	endcase
-end
-assign csrbankarray_csrbank2_rxempty_r = csrbankarray_interface2_bank_bus_dat_w[0];
-always @(*) begin
-	simsoc_blackparrotrv64_axi2wishbone1_w_ready = 1'd0;
-	case (axilite2wishbone1_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-			if (simsoc_blackparrotrv64_mmio_wb_ack) begin
-				simsoc_blackparrotrv64_axi2wishbone1_w_ready = 1'd1;
-			end
-		end
-		3'd4: begin
-		end
-		default: begin
-		end
-	endcase
-end
-assign csrbankarray_csrbank2_rxempty_we = ((csrbankarray_csrbank2_sel & (~csrbankarray_interface2_bank_bus_we)) & (csrbankarray_interface2_bank_bus_adr[2:0] == 2'd2));
-always @(*) begin
-	simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_cmd_done_axi2axilite0_next_value0 = 1'd0;
-	case (axi2axilite0_state)
-		1'd1: begin
-			if ((simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_beat_valid & simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_beat_last)) begin
-				if (simsoc_blackparrotrv64_axi2wishbone0_ar_ready) begin
-					simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_cmd_done_axi2axilite0_next_value0 = 1'd1;
-				end
-			end
-		end
-		2'd2: begin
-			if ((simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_beat_valid & simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_beat_last)) begin
-				if (simsoc_blackparrotrv64_axi2wishbone0_aw_ready) begin
-					simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_cmd_done_axi2axilite0_next_value0 = 1'd1;
-				end
-			end
-		end
-		2'd3: begin
-		end
-		default: begin
-			simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_cmd_done_axi2axilite0_next_value0 = 1'd0;
-		end
-	endcase
-end
-assign csrbankarray_csrbank2_rxempty_w = uart_rxempty_status;
-always @(*) begin
-	simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_cmd_done_axi2axilite0_next_value_ce0 = 1'd0;
-	case (axi2axilite0_state)
-		1'd1: begin
-			if ((simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_beat_valid & simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_beat_last)) begin
-				if (simsoc_blackparrotrv64_axi2wishbone0_ar_ready) begin
-					simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_cmd_done_axi2axilite0_next_value_ce0 = 1'd1;
-				end
-			end
-		end
-		2'd2: begin
-			if ((simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_beat_valid & simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_beat_last)) begin
-				if (simsoc_blackparrotrv64_axi2wishbone0_aw_ready) begin
-					simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_cmd_done_axi2axilite0_next_value_ce0 = 1'd1;
-				end
-			end
-		end
-		2'd3: begin
-		end
-		default: begin
-			simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_cmd_done_axi2axilite0_next_value_ce0 = 1'd1;
-		end
-	endcase
-end
-always @(*) begin
-	array_muxed6 = 3'd0;
-	case (grant)
-		1'd0: begin
-			array_muxed6 = simsoc_blackparrotrv64_ibus_cti;
-		end
-		default: begin
-			array_muxed6 = simsoc_blackparrotrv64_dbus_cti;
-		end
-	endcase
-end
-always @(*) begin
-	simsoc_blackparrotrv64_axi2wishbone1_w_payload_data = 64'd0;
-	case (axi2axilite1_state)
-		1'd1: begin
-		end
-		2'd2: begin
-			simsoc_blackparrotrv64_axi2wishbone1_w_payload_data = simsoc_blackparrotrv64_mmio_axi_w_payload_data;
-		end
-		2'd3: begin
-		end
-		default: begin
-		end
-	endcase
-end
-assign csrbankarray_csrbank2_ev_enable0_re = ((csrbankarray_csrbank2_sel & csrbankarray_interface2_bank_bus_we) & (csrbankarray_interface2_bank_bus_adr[2:0] == 3'd5));
-always @(*) begin
-	simsoc_blackparrotrv64_axi2wishbone1_w_payload_strb = 8'd0;
-	case (axi2axilite1_state)
-		1'd1: begin
-		end
-		2'd2: begin
-			simsoc_blackparrotrv64_axi2wishbone1_w_payload_strb = simsoc_blackparrotrv64_mmio_axi_w_payload_strb;
-		end
-		2'd3: begin
-		end
-		default: begin
-		end
-	endcase
-end
-always @(*) begin
-	simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_last_ar_aw_n_axi2axilite0_next_value1 = 1'd0;
-	case (axi2axilite0_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		default: begin
-			if ((simsoc_blackparrotrv64_mem_axi_ar_valid & simsoc_blackparrotrv64_mem_axi_aw_valid)) begin
-				if (simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_last_ar_aw_n) begin
-					simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_last_ar_aw_n_axi2axilite0_next_value1 = 1'd0;
-				end else begin
-					simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_last_ar_aw_n_axi2axilite0_next_value1 = 1'd1;
-				end
-			end else begin
-				if (simsoc_blackparrotrv64_mem_axi_ar_valid) begin
-					simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_last_ar_aw_n_axi2axilite0_next_value1 = 1'd1;
-				end else begin
-					if (simsoc_blackparrotrv64_mem_axi_aw_valid) begin
-						simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_last_ar_aw_n_axi2axilite0_next_value1 = 1'd0;
-					end
-				end
-			end
-		end
-	endcase
-end
-always @(*) begin
-	simsoc_blackparrotrv64_axi2wishbone1_b_valid = 1'd0;
-	case (axilite2wishbone1_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		3'd4: begin
-			simsoc_blackparrotrv64_axi2wishbone1_b_valid = 1'd1;
-		end
-		default: begin
-		end
-	endcase
-end
-always @(*) begin
-	simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_last_ar_aw_n_axi2axilite0_next_value_ce1 = 1'd0;
-	case (axi2axilite0_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		default: begin
-			if ((simsoc_blackparrotrv64_mem_axi_ar_valid & simsoc_blackparrotrv64_mem_axi_aw_valid)) begin
-				if (simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_last_ar_aw_n) begin
-					simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_last_ar_aw_n_axi2axilite0_next_value_ce1 = 1'd1;
-				end else begin
-					simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_last_ar_aw_n_axi2axilite0_next_value_ce1 = 1'd1;
-				end
-			end else begin
-				if (simsoc_blackparrotrv64_mem_axi_ar_valid) begin
-					simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_last_ar_aw_n_axi2axilite0_next_value_ce1 = 1'd1;
-				end else begin
-					if (simsoc_blackparrotrv64_mem_axi_aw_valid) begin
-						simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_last_ar_aw_n_axi2axilite0_next_value_ce1 = 1'd1;
-					end
-				end
-			end
-		end
-	endcase
-end
-assign simsoc_blackparrotrv64_axi2wishbone1_b_ready = 1'd1;
-assign csrbankarray_csrbank2_ev_enable0_w = uart_eventmanager_storage[1:0];
-assign csrbankarray_csrbank2_sel = (csrbankarray_interface2_bank_bus_adr[13:9] == 3'd4);
-always @(*) begin
-	simsoc_blackparrotrv64_axi2wishbone1_b_payload_resp = 2'd0;
-	case (axilite2wishbone1_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		3'd4: begin
-			simsoc_blackparrotrv64_axi2wishbone1_b_payload_resp = 1'd0;
-		end
-		default: begin
-		end
-	endcase
-end
-always @(*) begin
-	simsoc_blackparrotrv64_axi2wishbone1_ar_valid = 1'd0;
-	case (axi2axilite1_state)
-		1'd1: begin
-			simsoc_blackparrotrv64_axi2wishbone1_ar_valid = (simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_beat_valid & (~simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_cmd_done));
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		default: begin
-		end
-	endcase
-end
-always @(*) begin
-	simsoc_blackparrotrv64_axi2wishbone1_ar_ready = 1'd0;
-	case (axilite2wishbone1_state)
-		1'd1: begin
-			if (simsoc_blackparrotrv64_mmio_wb_ack) begin
-				simsoc_blackparrotrv64_axi2wishbone1_ar_ready = 1'd1;
-			end
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		3'd4: begin
-		end
-		default: begin
-		end
-	endcase
-end
-assign csrbankarray_csrbank1_load3_re = ((csrbankarray_csrbank1_sel & csrbankarray_interface1_bank_bus_we) & (csrbankarray_interface1_bank_bus_adr[4:0] == 1'd0));
-always @(*) begin
-	simsoc_blackparrotrv64_axi2wishbone1_ar_payload_addr = 32'd0;
-	case (axi2axilite1_state)
-		1'd1: begin
-			simsoc_blackparrotrv64_axi2wishbone1_ar_payload_addr = simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_beat_payload_addr;
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		default: begin
-		end
-	endcase
-end
-always @(*) begin
-	simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_payload_id = 4'd0;
-	case (axi2axilite0_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		default: begin
-			if ((simsoc_blackparrotrv64_mem_axi_ar_valid & simsoc_blackparrotrv64_mem_axi_aw_valid)) begin
-				if (simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_last_ar_aw_n) begin
-					simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_payload_id = simsoc_blackparrotrv64_mem_axi_aw_payload_id;
-				end else begin
-					simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_payload_id = simsoc_blackparrotrv64_mem_axi_ar_payload_id;
-				end
-			end else begin
-				if (simsoc_blackparrotrv64_mem_axi_ar_valid) begin
-					simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_payload_id = simsoc_blackparrotrv64_mem_axi_ar_payload_id;
-				end else begin
-					if (simsoc_blackparrotrv64_mem_axi_aw_valid) begin
-						simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_burst_payload_id = simsoc_blackparrotrv64_mem_axi_aw_payload_id;
-					end
-				end
-			end
-		end
-	endcase
-end
-always @(*) begin
-	simsoc_blackparrotrv64_axi2wishbone1_r_valid = 1'd0;
-	case (axilite2wishbone1_state)
-		1'd1: begin
-		end
-		2'd2: begin
-			simsoc_blackparrotrv64_axi2wishbone1_r_valid = 1'd1;
-		end
-		2'd3: begin
-		end
-		3'd4: begin
-		end
-		default: begin
-		end
-	endcase
-end
-always @(*) begin
-	simsoc_blackparrotrv64_axi2wishbone1_r_ready = 1'd0;
-	case (axi2axilite1_state)
-		1'd1: begin
-			simsoc_blackparrotrv64_axi2wishbone1_r_ready = simsoc_blackparrotrv64_mmio_axi_r_ready;
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		default: begin
-		end
-	endcase
-end
-always @(*) begin
-	simsoc_blackparrotrv64_axi2wishbone1_r_payload_resp = 2'd0;
-	case (axilite2wishbone1_state)
-		1'd1: begin
-		end
-		2'd2: begin
-			simsoc_blackparrotrv64_axi2wishbone1_r_payload_resp = 1'd0;
-		end
-		2'd3: begin
-		end
-		3'd4: begin
-		end
-		default: begin
-		end
-	endcase
-end
-always @(*) begin
-	simsoc_blackparrotrv64_axi2wishbone1_r_payload_data = 64'd0;
-	case (axilite2wishbone1_state)
-		1'd1: begin
-		end
-		2'd2: begin
-			simsoc_blackparrotrv64_axi2wishbone1_r_payload_data = simsoc_blackparrotrv64_axi2wishbone1_axi_lite2wishbone_data;
-		end
-		2'd3: begin
-		end
-		3'd4: begin
-		end
-		default: begin
-		end
-	endcase
-end
-assign simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_sink_valid = simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_valid;
-assign simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_sink_ready = simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_pipe_ce;
-assign simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_sink_first = simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_first;
-assign simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_sink_last = simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_last;
-assign simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_sink_payload_addr = simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_payload_addr;
-assign simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_sink_payload_burst = simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_payload_burst;
-assign simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_sink_payload_len = simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_payload_len;
-always @(*) begin
-	axilite2wishbone0_next_state = 3'd0;
-	axilite2wishbone0_next_state = axilite2wishbone0_state;
-	case (axilite2wishbone0_state)
-		1'd1: begin
-			if (simsoc_blackparrotrv64_mem_wb_ack) begin
-				axilite2wishbone0_next_state = 2'd2;
-			end
-		end
-		2'd2: begin
-			if (simsoc_blackparrotrv64_axi2wishbone0_r_ready) begin
-				axilite2wishbone0_next_state = 1'd0;
-			end
-		end
-		2'd3: begin
-			if (simsoc_blackparrotrv64_mem_wb_ack) begin
-				axilite2wishbone0_next_state = 3'd4;
-			end
-		end
-		3'd4: begin
-			if (simsoc_blackparrotrv64_axi2wishbone0_b_ready) begin
-				axilite2wishbone0_next_state = 1'd0;
-			end
-		end
-		default: begin
-			if ((simsoc_blackparrotrv64_axi2wishbone0_ar_valid & simsoc_blackparrotrv64_axi2wishbone0_aw_valid)) begin
-				if (simsoc_blackparrotrv64_axi2wishbone0_axi_lite2wishbone_last_ar_aw_n) begin
-					axilite2wishbone0_next_state = 2'd3;
-				end else begin
-					axilite2wishbone0_next_state = 1'd1;
-				end
-			end else begin
-				if (simsoc_blackparrotrv64_axi2wishbone0_ar_valid) begin
-					axilite2wishbone0_next_state = 1'd1;
-				end else begin
-					if (simsoc_blackparrotrv64_axi2wishbone0_aw_valid) begin
-						axilite2wishbone0_next_state = 2'd3;
-					end
-				end
-			end
-		end
-	endcase
-end
-assign simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_sink_payload_size = simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_payload_size;
-assign simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_sink_payload_lock = simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_payload_lock;
-assign simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_sink_payload_prot = simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_payload_prot;
-assign simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_sink_payload_cache = simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_payload_cache;
-assign simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_sink_payload_qos = simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_payload_qos;
-assign simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_sink_payload_id = simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_payload_id;
-assign simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_source_valid = simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_valid_n;
-always @(*) begin
-	simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_source_ready = 1'd0;
-	if (simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_beat_ready) begin
-		if (simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_beat_last) begin
-			simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_source_ready = 1'd1;
-		end
-	end
-end
-assign simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_source_first = simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_first_n;
-assign simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_source_last = simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_last_n;
-always @(*) begin
-	simsoc_blackparrotrv64_axi2wishbone0_axi_lite2wishbone_data_axilite2wishbone0_next_value1 = 64'd0;
-	case (axilite2wishbone0_state)
-		1'd1: begin
-			if (simsoc_blackparrotrv64_mem_wb_ack) begin
-				simsoc_blackparrotrv64_axi2wishbone0_axi_lite2wishbone_data_axilite2wishbone0_next_value1 = simsoc_blackparrotrv64_mem_wb_dat_r;
-			end
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		3'd4: begin
-		end
-		default: begin
-		end
-	endcase
-end
-assign uart_irq = ((uart_eventmanager_pending_w[0] & uart_eventmanager_storage[0]) | (uart_eventmanager_pending_w[1] & uart_eventmanager_storage[1]));
-always @(*) begin
-	simsoc_blackparrotrv64_axi2wishbone0_axi_lite2wishbone_data_axilite2wishbone0_next_value_ce1 = 1'd0;
-	case (axilite2wishbone0_state)
-		1'd1: begin
-			if (simsoc_blackparrotrv64_mem_wb_ack) begin
-				simsoc_blackparrotrv64_axi2wishbone0_axi_lite2wishbone_data_axilite2wishbone0_next_value_ce1 = 1'd1;
-			end
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		3'd4: begin
-		end
-		default: begin
-		end
-	endcase
-end
-assign csrbankarray_interface0_bank_bus_adr = csrcon_adr;
-assign csrbankarray_csrbank1_load3_r = csrbankarray_interface1_bank_bus_dat_w[7:0];
-assign simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_pipe_ce = (simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_source_ready | (~simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_valid_n));
-always @(*) begin
-	converter0_next_state = 2'd0;
-	converter0_next_state = converter0_state;
-	case (converter0_state)
-		1'd1: begin
-			if ((simsoc_blackparrotrv64_mem_wb_stb & simsoc_blackparrotrv64_mem_wb_cyc)) begin
-				if (simsoc_blackparrotrv64_ibus_ack) begin
-					if (simsoc_blackparrotrv64_mem_dc_counter_done) begin
-						converter0_next_state = 1'd0;
-					end
-				end
-			end else begin
-				if ((~simsoc_blackparrotrv64_mem_wb_cyc)) begin
-					converter0_next_state = 1'd0;
-				end
-			end
-		end
-		2'd2: begin
-			if ((simsoc_blackparrotrv64_mem_wb_stb & simsoc_blackparrotrv64_mem_wb_cyc)) begin
-				if (simsoc_blackparrotrv64_ibus_ack) begin
-					if (simsoc_blackparrotrv64_mem_dc_counter_done) begin
-						converter0_next_state = 1'd0;
-					end
-				end
-			end else begin
-				if ((~simsoc_blackparrotrv64_mem_wb_cyc)) begin
-					converter0_next_state = 1'd0;
-				end
-			end
-		end
-		default: begin
-			if ((simsoc_blackparrotrv64_mem_wb_stb & simsoc_blackparrotrv64_mem_wb_cyc)) begin
-				if (simsoc_blackparrotrv64_mem_wb_we) begin
-					converter0_next_state = 1'd1;
-				end else begin
-					converter0_next_state = 2'd2;
-				end
-			end
-		end
-	endcase
-end
-assign simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_busy = (1'd0 | simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_valid_n);
-assign csrcon_adr = simsoc_interface_adr;
-assign uart_eventmanager_pending_we = ((csrbankarray_csrbank2_sel & (~csrbankarray_interface2_bank_bus_we)) & (csrbankarray_interface2_bank_bus_adr[2:0] == 3'd4));
-assign csrcon_we = simsoc_interface_we;
-assign csrcon_dat_w = simsoc_interface_dat_w;
-assign csrcon_dat_r = (((csrbankarray_interface0_bank_bus_dat_r | csrbankarray_interface1_bank_bus_dat_r) | csrbankarray_interface2_bank_bus_dat_r) | csrbankarray_sram_bus_dat_r);
-always @(*) begin
-	simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_valid = 1'd0;
-	case (axi2axilite1_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		default: begin
-			if ((simsoc_blackparrotrv64_mmio_axi_ar_valid & simsoc_blackparrotrv64_mmio_axi_aw_valid)) begin
-				if (simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_last_ar_aw_n) begin
-					simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_valid = simsoc_blackparrotrv64_mmio_axi_aw_valid;
-				end else begin
-					simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_valid = simsoc_blackparrotrv64_mmio_axi_ar_valid;
-				end
-			end else begin
-				if (simsoc_blackparrotrv64_mmio_axi_ar_valid) begin
-					simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_valid = simsoc_blackparrotrv64_mmio_axi_ar_valid;
-				end else begin
-					if (simsoc_blackparrotrv64_mmio_axi_aw_valid) begin
-						simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_valid = simsoc_blackparrotrv64_mmio_axi_aw_valid;
-					end
-				end
-			end
-		end
-	endcase
-end
-assign simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_ready = simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_sink_ready;
-always @(*) begin
-	array_muxed5 = 1'd0;
-	case (grant)
-		1'd0: begin
-			array_muxed5 = simsoc_blackparrotrv64_ibus_we;
-		end
-		default: begin
-			array_muxed5 = simsoc_blackparrotrv64_dbus_we;
-		end
-	endcase
-end
-always @(*) begin
-	simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_first = 1'd0;
-	case (axi2axilite1_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		default: begin
-			if ((simsoc_blackparrotrv64_mmio_axi_ar_valid & simsoc_blackparrotrv64_mmio_axi_aw_valid)) begin
-				if (simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_last_ar_aw_n) begin
-					simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_first = simsoc_blackparrotrv64_mmio_axi_aw_first;
-				end else begin
-					simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_first = simsoc_blackparrotrv64_mmio_axi_ar_first;
-				end
-			end else begin
-				if (simsoc_blackparrotrv64_mmio_axi_ar_valid) begin
-					simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_first = simsoc_blackparrotrv64_mmio_axi_ar_first;
-				end else begin
-					if (simsoc_blackparrotrv64_mmio_axi_aw_valid) begin
-						simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_first = simsoc_blackparrotrv64_mmio_axi_aw_first;
-					end
-				end
-			end
-		end
-	endcase
-end
-always @(*) begin
-	simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_last = 1'd0;
-	case (axi2axilite1_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		default: begin
-			if ((simsoc_blackparrotrv64_mmio_axi_ar_valid & simsoc_blackparrotrv64_mmio_axi_aw_valid)) begin
-				if (simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_last_ar_aw_n) begin
-					simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_last = simsoc_blackparrotrv64_mmio_axi_aw_last;
-				end else begin
-					simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_last = simsoc_blackparrotrv64_mmio_axi_ar_last;
-				end
-			end else begin
-				if (simsoc_blackparrotrv64_mmio_axi_ar_valid) begin
-					simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_last = simsoc_blackparrotrv64_mmio_axi_ar_last;
-				end else begin
-					if (simsoc_blackparrotrv64_mmio_axi_aw_valid) begin
-						simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_last = simsoc_blackparrotrv64_mmio_axi_aw_last;
-					end
-				end
-			end
-		end
-	endcase
-end
-always @(*) begin
-	simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_payload_addr = 32'd0;
-	case (axi2axilite1_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		default: begin
-			if ((simsoc_blackparrotrv64_mmio_axi_ar_valid & simsoc_blackparrotrv64_mmio_axi_aw_valid)) begin
-				if (simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_last_ar_aw_n) begin
-					simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_payload_addr = simsoc_blackparrotrv64_mmio_axi_aw_payload_addr;
-				end else begin
-					simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_payload_addr = simsoc_blackparrotrv64_mmio_axi_ar_payload_addr;
-				end
-			end else begin
-				if (simsoc_blackparrotrv64_mmio_axi_ar_valid) begin
-					simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_payload_addr = simsoc_blackparrotrv64_mmio_axi_ar_payload_addr;
-				end else begin
-					if (simsoc_blackparrotrv64_mmio_axi_aw_valid) begin
-						simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_payload_addr = simsoc_blackparrotrv64_mmio_axi_aw_payload_addr;
-					end
-				end
-			end
-		end
-	endcase
-end
-always @(*) begin
-	simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_payload_burst = 2'd0;
-	case (axi2axilite1_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		default: begin
-			if ((simsoc_blackparrotrv64_mmio_axi_ar_valid & simsoc_blackparrotrv64_mmio_axi_aw_valid)) begin
-				if (simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_last_ar_aw_n) begin
-					simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_payload_burst = simsoc_blackparrotrv64_mmio_axi_aw_payload_burst;
-				end else begin
-					simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_payload_burst = simsoc_blackparrotrv64_mmio_axi_ar_payload_burst;
-				end
-			end else begin
-				if (simsoc_blackparrotrv64_mmio_axi_ar_valid) begin
-					simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_payload_burst = simsoc_blackparrotrv64_mmio_axi_ar_payload_burst;
-				end else begin
-					if (simsoc_blackparrotrv64_mmio_axi_aw_valid) begin
-						simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_payload_burst = simsoc_blackparrotrv64_mmio_axi_aw_payload_burst;
-					end
-				end
-			end
-		end
-	endcase
-end
-always @(*) begin
-	simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_payload_len = 8'd0;
-	case (axi2axilite1_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		default: begin
-			if ((simsoc_blackparrotrv64_mmio_axi_ar_valid & simsoc_blackparrotrv64_mmio_axi_aw_valid)) begin
-				if (simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_last_ar_aw_n) begin
-					simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_payload_len = simsoc_blackparrotrv64_mmio_axi_aw_payload_len;
-				end else begin
-					simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_payload_len = simsoc_blackparrotrv64_mmio_axi_ar_payload_len;
-				end
-			end else begin
-				if (simsoc_blackparrotrv64_mmio_axi_ar_valid) begin
-					simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_payload_len = simsoc_blackparrotrv64_mmio_axi_ar_payload_len;
-				end else begin
-					if (simsoc_blackparrotrv64_mmio_axi_aw_valid) begin
-						simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_payload_len = simsoc_blackparrotrv64_mmio_axi_aw_payload_len;
-					end
-				end
-			end
-		end
-	endcase
-end
-always @(*) begin
-	simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_payload_size = 4'd0;
-	case (axi2axilite1_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		default: begin
-			if ((simsoc_blackparrotrv64_mmio_axi_ar_valid & simsoc_blackparrotrv64_mmio_axi_aw_valid)) begin
-				if (simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_last_ar_aw_n) begin
-					simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_payload_size = simsoc_blackparrotrv64_mmio_axi_aw_payload_size;
-				end else begin
-					simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_payload_size = simsoc_blackparrotrv64_mmio_axi_ar_payload_size;
-				end
-			end else begin
-				if (simsoc_blackparrotrv64_mmio_axi_ar_valid) begin
-					simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_payload_size = simsoc_blackparrotrv64_mmio_axi_ar_payload_size;
-				end else begin
-					if (simsoc_blackparrotrv64_mmio_axi_aw_valid) begin
-						simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_payload_size = simsoc_blackparrotrv64_mmio_axi_aw_payload_size;
-					end
-				end
-			end
-		end
-	endcase
-end
-always @(*) begin
-	simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_last_ar_aw_n_axi2axilite1_next_value1 = 1'd0;
-	case (axi2axilite1_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		default: begin
-			if ((simsoc_blackparrotrv64_mmio_axi_ar_valid & simsoc_blackparrotrv64_mmio_axi_aw_valid)) begin
-				if (simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_last_ar_aw_n) begin
-					simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_last_ar_aw_n_axi2axilite1_next_value1 = 1'd0;
-				end else begin
-					simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_last_ar_aw_n_axi2axilite1_next_value1 = 1'd1;
-				end
-			end else begin
-				if (simsoc_blackparrotrv64_mmio_axi_ar_valid) begin
-					simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_last_ar_aw_n_axi2axilite1_next_value1 = 1'd1;
-				end else begin
-					if (simsoc_blackparrotrv64_mmio_axi_aw_valid) begin
-						simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_last_ar_aw_n_axi2axilite1_next_value1 = 1'd0;
-					end
-				end
-			end
-		end
-	endcase
-end
-always @(*) begin
-	simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_payload_lock = 2'd0;
-	case (axi2axilite1_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		default: begin
-			if ((simsoc_blackparrotrv64_mmio_axi_ar_valid & simsoc_blackparrotrv64_mmio_axi_aw_valid)) begin
-				if (simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_last_ar_aw_n) begin
-					simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_payload_lock = simsoc_blackparrotrv64_mmio_axi_aw_payload_lock;
-				end else begin
-					simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_payload_lock = simsoc_blackparrotrv64_mmio_axi_ar_payload_lock;
-				end
-			end else begin
-				if (simsoc_blackparrotrv64_mmio_axi_ar_valid) begin
-					simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_payload_lock = simsoc_blackparrotrv64_mmio_axi_ar_payload_lock;
-				end else begin
-					if (simsoc_blackparrotrv64_mmio_axi_aw_valid) begin
-						simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_payload_lock = simsoc_blackparrotrv64_mmio_axi_aw_payload_lock;
-					end
-				end
-			end
-		end
-	endcase
-end
-always @(*) begin
-	simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_last_ar_aw_n_axi2axilite1_next_value_ce1 = 1'd0;
-	case (axi2axilite1_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		default: begin
-			if ((simsoc_blackparrotrv64_mmio_axi_ar_valid & simsoc_blackparrotrv64_mmio_axi_aw_valid)) begin
-				if (simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_last_ar_aw_n) begin
-					simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_last_ar_aw_n_axi2axilite1_next_value_ce1 = 1'd1;
-				end else begin
-					simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_last_ar_aw_n_axi2axilite1_next_value_ce1 = 1'd1;
-				end
-			end else begin
-				if (simsoc_blackparrotrv64_mmio_axi_ar_valid) begin
-					simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_last_ar_aw_n_axi2axilite1_next_value_ce1 = 1'd1;
-				end else begin
-					if (simsoc_blackparrotrv64_mmio_axi_aw_valid) begin
-						simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_last_ar_aw_n_axi2axilite1_next_value_ce1 = 1'd1;
-					end
-				end
-			end
-		end
-	endcase
-end
-always @(*) begin
-	simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_payload_prot = 3'd0;
-	case (axi2axilite1_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		default: begin
-			if ((simsoc_blackparrotrv64_mmio_axi_ar_valid & simsoc_blackparrotrv64_mmio_axi_aw_valid)) begin
-				if (simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_last_ar_aw_n) begin
-					simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_payload_prot = simsoc_blackparrotrv64_mmio_axi_aw_payload_prot;
-				end else begin
-					simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_payload_prot = simsoc_blackparrotrv64_mmio_axi_ar_payload_prot;
-				end
-			end else begin
-				if (simsoc_blackparrotrv64_mmio_axi_ar_valid) begin
-					simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_payload_prot = simsoc_blackparrotrv64_mmio_axi_ar_payload_prot;
-				end else begin
-					if (simsoc_blackparrotrv64_mmio_axi_aw_valid) begin
-						simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_payload_prot = simsoc_blackparrotrv64_mmio_axi_aw_payload_prot;
-					end
-				end
-			end
-		end
-	endcase
-end
-always @(*) begin
-	simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_payload_cache = 4'd0;
-	case (axi2axilite1_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		default: begin
-			if ((simsoc_blackparrotrv64_mmio_axi_ar_valid & simsoc_blackparrotrv64_mmio_axi_aw_valid)) begin
-				if (simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_last_ar_aw_n) begin
-					simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_payload_cache = simsoc_blackparrotrv64_mmio_axi_aw_payload_cache;
-				end else begin
-					simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_payload_cache = simsoc_blackparrotrv64_mmio_axi_ar_payload_cache;
-				end
-			end else begin
-				if (simsoc_blackparrotrv64_mmio_axi_ar_valid) begin
-					simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_payload_cache = simsoc_blackparrotrv64_mmio_axi_ar_payload_cache;
-				end else begin
-					if (simsoc_blackparrotrv64_mmio_axi_aw_valid) begin
-						simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_payload_cache = simsoc_blackparrotrv64_mmio_axi_aw_payload_cache;
-					end
-				end
-			end
-		end
-	endcase
-end
-always @(*) begin
-	simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_payload_qos = 4'd0;
-	case (axi2axilite1_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		default: begin
-			if ((simsoc_blackparrotrv64_mmio_axi_ar_valid & simsoc_blackparrotrv64_mmio_axi_aw_valid)) begin
-				if (simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_last_ar_aw_n) begin
-					simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_payload_qos = simsoc_blackparrotrv64_mmio_axi_aw_payload_qos;
-				end else begin
-					simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_payload_qos = simsoc_blackparrotrv64_mmio_axi_ar_payload_qos;
-				end
-			end else begin
-				if (simsoc_blackparrotrv64_mmio_axi_ar_valid) begin
-					simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_payload_qos = simsoc_blackparrotrv64_mmio_axi_ar_payload_qos;
-				end else begin
-					if (simsoc_blackparrotrv64_mmio_axi_aw_valid) begin
-						simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_payload_qos = simsoc_blackparrotrv64_mmio_axi_aw_payload_qos;
-					end
-				end
-			end
-		end
-	endcase
-end
-always @(*) begin
-	simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_payload_id = 4'd0;
-	case (axi2axilite1_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		default: begin
-			if ((simsoc_blackparrotrv64_mmio_axi_ar_valid & simsoc_blackparrotrv64_mmio_axi_aw_valid)) begin
-				if (simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_last_ar_aw_n) begin
-					simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_payload_id = simsoc_blackparrotrv64_mmio_axi_aw_payload_id;
-				end else begin
-					simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_payload_id = simsoc_blackparrotrv64_mmio_axi_ar_payload_id;
-				end
-			end else begin
-				if (simsoc_blackparrotrv64_mmio_axi_ar_valid) begin
-					simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_payload_id = simsoc_blackparrotrv64_mmio_axi_ar_payload_id;
-				end else begin
-					if (simsoc_blackparrotrv64_mmio_axi_aw_valid) begin
-						simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_burst_payload_id = simsoc_blackparrotrv64_mmio_axi_aw_payload_id;
-					end
-				end
-			end
-		end
-	endcase
-end
-assign simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_beat_valid = (simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_source_valid | (~simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_beat_first));
-always @(*) begin
-	simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_beat_ready = 1'd0;
-	case (axi2axilite1_state)
-		1'd1: begin
-			simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_beat_ready = (simsoc_blackparrotrv64_axi2wishbone1_ar_ready & (~simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_cmd_done));
-			if ((simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_beat_valid & simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_beat_last)) begin
-				if (simsoc_blackparrotrv64_axi2wishbone1_ar_ready) begin
-					simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_beat_ready = 1'd0;
-				end
-			end
-			if (((simsoc_blackparrotrv64_mmio_axi_r_valid & simsoc_blackparrotrv64_mmio_axi_r_last) & simsoc_blackparrotrv64_mmio_axi_r_ready)) begin
-				simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_beat_ready = 1'd1;
-			end
-		end
-		2'd2: begin
-			simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_beat_ready = (simsoc_blackparrotrv64_axi2wishbone1_aw_ready & (~simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_cmd_done));
-			if ((simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_beat_valid & simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_beat_last)) begin
-				if (simsoc_blackparrotrv64_axi2wishbone1_aw_ready) begin
-					simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_beat_ready = 1'd0;
-				end
-			end
-		end
-		2'd3: begin
-			if (simsoc_blackparrotrv64_mmio_axi_b_ready) begin
-				simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_beat_ready = 1'd1;
-			end
-		end
-		default: begin
-		end
-	endcase
-end
-assign simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_beat_first = (simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_beat_count == 1'd0);
-assign simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_beat_last = (simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_beat_count == simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_source_payload_len);
-assign simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_beat_payload_addr = (simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_source_payload_addr + simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_beat_offset);
-assign csrbankarray_csrbank1_load3_we = ((csrbankarray_csrbank1_sel & (~csrbankarray_interface1_bank_bus_we)) & (csrbankarray_interface1_bank_bus_adr[4:0] == 1'd0));
-assign simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_beat_valid = (simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_source_valid | (~simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_beat_first));
-assign csrbankarray_csrbank0_scratch3_we = ((csrbankarray_csrbank0_sel & (~csrbankarray_interface0_bank_bus_we)) & (csrbankarray_interface0_bank_bus_adr[3:0] == 1'd1));
-assign simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_beat_payload_id = simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_source_payload_id;
-always @(*) begin
-	simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_beat_ready = 1'd0;
-	case (axi2axilite0_state)
-		1'd1: begin
-			simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_beat_ready = (simsoc_blackparrotrv64_axi2wishbone0_ar_ready & (~simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_cmd_done));
-			if ((simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_beat_valid & simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_beat_last)) begin
-				if (simsoc_blackparrotrv64_axi2wishbone0_ar_ready) begin
-					simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_beat_ready = 1'd0;
-				end
-			end
-			if (((simsoc_blackparrotrv64_mem_axi_r_valid & simsoc_blackparrotrv64_mem_axi_r_last) & simsoc_blackparrotrv64_mem_axi_r_ready)) begin
-				simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_beat_ready = 1'd1;
-			end
-		end
-		2'd2: begin
-			simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_beat_ready = (simsoc_blackparrotrv64_axi2wishbone0_aw_ready & (~simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_cmd_done));
-			if ((simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_beat_valid & simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_beat_last)) begin
-				if (simsoc_blackparrotrv64_axi2wishbone0_aw_ready) begin
-					simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_beat_ready = 1'd0;
-				end
-			end
-		end
-		2'd3: begin
-			if (simsoc_blackparrotrv64_mem_axi_b_ready) begin
-				simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_beat_ready = 1'd1;
-			end
-		end
-		default: begin
-		end
-	endcase
-end
-assign simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_beat_size = (1'd1 <<< simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_source_payload_size);
-assign simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_beat_wrap = (simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_source_payload_len <<< simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_source_payload_size);
-always @(*) begin
-	axilite2wishbone1_next_state = 3'd0;
-	axilite2wishbone1_next_state = axilite2wishbone1_state;
-	case (axilite2wishbone1_state)
-		1'd1: begin
-			if (simsoc_blackparrotrv64_mmio_wb_ack) begin
-				axilite2wishbone1_next_state = 2'd2;
-			end
-		end
-		2'd2: begin
-			if (simsoc_blackparrotrv64_axi2wishbone1_r_ready) begin
-				axilite2wishbone1_next_state = 1'd0;
-			end
-		end
-		2'd3: begin
-			if (simsoc_blackparrotrv64_mmio_wb_ack) begin
-				axilite2wishbone1_next_state = 3'd4;
-			end
-		end
-		3'd4: begin
-			if (simsoc_blackparrotrv64_axi2wishbone1_b_ready) begin
-				axilite2wishbone1_next_state = 1'd0;
-			end
-		end
-		default: begin
-			if ((simsoc_blackparrotrv64_axi2wishbone1_ar_valid & simsoc_blackparrotrv64_axi2wishbone1_aw_valid)) begin
-				if (simsoc_blackparrotrv64_axi2wishbone1_axi_lite2wishbone_last_ar_aw_n) begin
-					axilite2wishbone1_next_state = 2'd3;
-				end else begin
-					axilite2wishbone1_next_state = 1'd1;
-				end
-			end else begin
-				if (simsoc_blackparrotrv64_axi2wishbone1_ar_valid) begin
-					axilite2wishbone1_next_state = 1'd1;
-				end else begin
-					if (simsoc_blackparrotrv64_axi2wishbone1_aw_valid) begin
-						axilite2wishbone1_next_state = 2'd3;
-					end
-				end
-			end
-		end
-	endcase
-end
-assign csrbankarray_csrbank1_value3_re = ((csrbankarray_csrbank1_sel & csrbankarray_interface1_bank_bus_we) & (csrbankarray_interface1_bank_bus_adr[4:0] == 4'd10));
-always @(*) begin
-	simsoc_blackparrotrv64_axi2wishbone1_axi_lite2wishbone_last_ar_aw_n_axilite2wishbone1_next_value0 = 1'd0;
-	case (axilite2wishbone1_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		3'd4: begin
-		end
-		default: begin
-			if ((simsoc_blackparrotrv64_axi2wishbone1_ar_valid & simsoc_blackparrotrv64_axi2wishbone1_aw_valid)) begin
-				if (simsoc_blackparrotrv64_axi2wishbone1_axi_lite2wishbone_last_ar_aw_n) begin
-					simsoc_blackparrotrv64_axi2wishbone1_axi_lite2wishbone_last_ar_aw_n_axilite2wishbone1_next_value0 = 1'd0;
-				end else begin
-					simsoc_blackparrotrv64_axi2wishbone1_axi_lite2wishbone_last_ar_aw_n_axilite2wishbone1_next_value0 = 1'd1;
-				end
-			end else begin
-				if (simsoc_blackparrotrv64_axi2wishbone1_ar_valid) begin
-					simsoc_blackparrotrv64_axi2wishbone1_axi_lite2wishbone_last_ar_aw_n_axilite2wishbone1_next_value0 = 1'd1;
-				end else begin
-					if (simsoc_blackparrotrv64_axi2wishbone1_aw_valid) begin
-						simsoc_blackparrotrv64_axi2wishbone1_axi_lite2wishbone_last_ar_aw_n_axilite2wishbone1_next_value0 = 1'd0;
-					end
-				end
-			end
-		end
-	endcase
-end
-always @(*) begin
-	simsoc_blackparrotrv64_axi2wishbone1_axi_lite2wishbone_last_ar_aw_n_axilite2wishbone1_next_value_ce0 = 1'd0;
-	case (axilite2wishbone1_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		3'd4: begin
-		end
-		default: begin
-			if ((simsoc_blackparrotrv64_axi2wishbone1_ar_valid & simsoc_blackparrotrv64_axi2wishbone1_aw_valid)) begin
-				if (simsoc_blackparrotrv64_axi2wishbone1_axi_lite2wishbone_last_ar_aw_n) begin
-					simsoc_blackparrotrv64_axi2wishbone1_axi_lite2wishbone_last_ar_aw_n_axilite2wishbone1_next_value_ce0 = 1'd1;
-				end else begin
-					simsoc_blackparrotrv64_axi2wishbone1_axi_lite2wishbone_last_ar_aw_n_axilite2wishbone1_next_value_ce0 = 1'd1;
-				end
-			end else begin
-				if (simsoc_blackparrotrv64_axi2wishbone1_ar_valid) begin
-					simsoc_blackparrotrv64_axi2wishbone1_axi_lite2wishbone_last_ar_aw_n_axilite2wishbone1_next_value_ce0 = 1'd1;
-				end else begin
-					if (simsoc_blackparrotrv64_axi2wishbone1_aw_valid) begin
-						simsoc_blackparrotrv64_axi2wishbone1_axi_lite2wishbone_last_ar_aw_n_axilite2wishbone1_next_value_ce0 = 1'd1;
-					end
-				end
-			end
-		end
-	endcase
-end
-assign uart_rx_status = uart_rx_trigger;
-always @(*) begin
-	simsoc_blackparrotrv64_axi2wishbone1_axi_lite2wishbone_data_axilite2wishbone1_next_value1 = 64'd0;
-	case (axilite2wishbone1_state)
-		1'd1: begin
-			if (simsoc_blackparrotrv64_mmio_wb_ack) begin
-				simsoc_blackparrotrv64_axi2wishbone1_axi_lite2wishbone_data_axilite2wishbone1_next_value1 = simsoc_blackparrotrv64_mmio_wb_dat_r;
-			end
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		3'd4: begin
-		end
-		default: begin
-		end
-	endcase
-end
-always @(*) begin
-	simsoc_blackparrotrv64_axi2wishbone1_axi_lite2wishbone_data_axilite2wishbone1_next_value_ce1 = 1'd0;
-	case (axilite2wishbone1_state)
-		1'd1: begin
-			if (simsoc_blackparrotrv64_mmio_wb_ack) begin
-				simsoc_blackparrotrv64_axi2wishbone1_axi_lite2wishbone_data_axilite2wishbone1_next_value_ce1 = 1'd1;
-			end
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		3'd4: begin
-		end
-		default: begin
-		end
-	endcase
-end
-assign simsoc_blackparrotrv64_dbus_err = (shared_err & (grant == 1'd1));
-assign simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_beat_first = (simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_beat_count == 1'd0);
-always @(*) begin
-	converter1_next_state = 2'd0;
-	converter1_next_state = converter1_state;
-	case (converter1_state)
-		1'd1: begin
-			if ((simsoc_blackparrotrv64_mmio_wb_stb & simsoc_blackparrotrv64_mmio_wb_cyc)) begin
-				if (simsoc_blackparrotrv64_dbus_ack) begin
-					if (simsoc_blackparrotrv64_mmio_dc_counter_done) begin
-						converter1_next_state = 1'd0;
-					end
-				end
-			end else begin
-				if ((~simsoc_blackparrotrv64_mmio_wb_cyc)) begin
-					converter1_next_state = 1'd0;
-				end
-			end
-		end
-		2'd2: begin
-			if ((simsoc_blackparrotrv64_mmio_wb_stb & simsoc_blackparrotrv64_mmio_wb_cyc)) begin
-				if (simsoc_blackparrotrv64_dbus_ack) begin
-					if (simsoc_blackparrotrv64_mmio_dc_counter_done) begin
-						converter1_next_state = 1'd0;
-					end
-				end
-			end else begin
-				if ((~simsoc_blackparrotrv64_mmio_wb_cyc)) begin
-					converter1_next_state = 1'd0;
-				end
-			end
-		end
-		default: begin
-			if ((simsoc_blackparrotrv64_mmio_wb_stb & simsoc_blackparrotrv64_mmio_wb_cyc)) begin
-				if (simsoc_blackparrotrv64_mmio_wb_we) begin
-					converter1_next_state = 1'd1;
-				end else begin
-					converter1_next_state = 2'd2;
-				end
-			end
-		end
-	endcase
-end
-assign csrbankarray_csrbank2_ev_enable0_we = ((csrbankarray_csrbank2_sel & (~csrbankarray_interface2_bank_bus_we)) & (csrbankarray_interface2_bank_bus_adr[2:0] == 3'd5));
-assign simsoc_blackparrotrv64_axi2wishbone1_axi_lite2wishbone_r_addr = (simsoc_blackparrotrv64_axi2wishbone1_ar_payload_addr - 1'd0);
-assign simsoc_blackparrotrv64_axi2wishbone1_axi_lite2wishbone_w_addr = (simsoc_blackparrotrv64_axi2wishbone1_aw_payload_addr - 1'd0);
-assign simsoc_eventmanager_status_re = ((csrbankarray_csrbank1_sel & csrbankarray_interface1_bank_bus_we) & (csrbankarray_interface1_bank_bus_adr[4:0] == 4'd14));
-assign shared_adr = array_muxed0;
-assign shared_dat_w = array_muxed1;
-always @(*) begin
-	shared_dat_r = 32'd0;
-	shared_dat_r = (((({32{slave_sel_r[0]}} & simsoc_rom_bus_dat_r) | ({32{slave_sel_r[1]}} & simsoc_sram_bus_dat_r)) | ({32{slave_sel_r[2]}} & simsoc_main_ram_bus_dat_r)) | ({32{slave_sel_r[3]}} & simsoc_bus_wishbone_dat_r));
-	if (done) begin
-		shared_dat_r = 32'd4294967295;
-	end
-end
-assign shared_sel = array_muxed2;
-assign shared_cyc = array_muxed3;
-assign shared_stb = array_muxed4;
-always @(*) begin
-	shared_ack = 1'd0;
-	shared_ack = (((simsoc_rom_bus_ack | simsoc_sram_bus_ack) | simsoc_main_ram_bus_ack) | simsoc_bus_wishbone_ack);
-	if (done) begin
-		shared_ack = 1'd1;
-	end
-end
-assign simsoc_blackparrotrv64_mmio_a2w_reset = (sys_rst | simsoc_blackparrotrv64_reset);
-assign shared_we = array_muxed5;
-assign shared_cti = array_muxed6;
-assign shared_bte = array_muxed7;
-always @(*) begin
-	simsoc_blackparrotrv64_mem_dc_read = 1'd0;
-	case (converter0_state)
-		1'd1: begin
-		end
-		2'd2: begin
-			simsoc_blackparrotrv64_mem_dc_read = 1'd1;
-		end
-		default: begin
-		end
-	endcase
-end
-assign shared_err = (((simsoc_rom_bus_err | simsoc_sram_bus_err) | simsoc_main_ram_bus_err) | simsoc_bus_wishbone_err);
-always @(*) begin
-	simsoc_blackparrotrv64_mem_dc_write = 1'd0;
-	case (converter0_state)
-		1'd1: begin
-			simsoc_blackparrotrv64_mem_dc_write = 1'd1;
-		end
-		2'd2: begin
-		end
-		default: begin
-		end
-	endcase
-end
-assign request = {simsoc_blackparrotrv64_dbus_cyc, simsoc_blackparrotrv64_ibus_cyc};
-always @(*) begin
-	simsoc_blackparrotrv64_mem_dc_counter_reset = 1'd0;
-	case (converter0_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		default: begin
-			simsoc_blackparrotrv64_mem_dc_counter_reset = 1'd1;
-		end
-	endcase
-end
-assign csrbankarray_csrbank1_value2_w = simsoc_value_status[23:16];
-always @(*) begin
-	simsoc_blackparrotrv64_mem_dc_counter_ce = 1'd0;
-	case (converter0_state)
-		1'd1: begin
-			if ((simsoc_blackparrotrv64_mem_wb_stb & simsoc_blackparrotrv64_mem_wb_cyc)) begin
-				if (simsoc_blackparrotrv64_ibus_ack) begin
-					simsoc_blackparrotrv64_mem_dc_counter_ce = 1'd1;
-				end
-			end else begin
-			end
-		end
-		2'd2: begin
-			if ((simsoc_blackparrotrv64_mem_wb_stb & simsoc_blackparrotrv64_mem_wb_cyc)) begin
-				if (simsoc_blackparrotrv64_ibus_ack) begin
-					simsoc_blackparrotrv64_mem_dc_counter_ce = 1'd1;
-				end
-			end else begin
-			end
-		end
-		default: begin
-		end
-	endcase
-end
-always @(*) begin
-	simsoc_blackparrotrv64_axi2wishbone0_axi_lite2wishbone_last_ar_aw_n_axilite2wishbone0_next_value0 = 1'd0;
-	case (axilite2wishbone0_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		3'd4: begin
-		end
-		default: begin
-			if ((simsoc_blackparrotrv64_axi2wishbone0_ar_valid & simsoc_blackparrotrv64_axi2wishbone0_aw_valid)) begin
-				if (simsoc_blackparrotrv64_axi2wishbone0_axi_lite2wishbone_last_ar_aw_n) begin
-					simsoc_blackparrotrv64_axi2wishbone0_axi_lite2wishbone_last_ar_aw_n_axilite2wishbone0_next_value0 = 1'd0;
-				end else begin
-					simsoc_blackparrotrv64_axi2wishbone0_axi_lite2wishbone_last_ar_aw_n_axilite2wishbone0_next_value0 = 1'd1;
-				end
-			end else begin
-				if (simsoc_blackparrotrv64_axi2wishbone0_ar_valid) begin
-					simsoc_blackparrotrv64_axi2wishbone0_axi_lite2wishbone_last_ar_aw_n_axilite2wishbone0_next_value0 = 1'd1;
-				end else begin
-					if (simsoc_blackparrotrv64_axi2wishbone0_aw_valid) begin
-						simsoc_blackparrotrv64_axi2wishbone0_axi_lite2wishbone_last_ar_aw_n_axilite2wishbone0_next_value0 = 1'd0;
-					end
-				end
-			end
-		end
-	endcase
-end
-assign simsoc_blackparrotrv64_mem_dc_counter_done = (simsoc_blackparrotrv64_mem_dc_counter == 1'd1);
-assign csrbankarray_csrbank0_scratch1_r = csrbankarray_interface0_bank_bus_dat_w[7:0];
-assign csrbankarray_interface2_bank_bus_adr = csrcon_adr;
-always @(*) begin
-	simsoc_blackparrotrv64_axi2wishbone0_axi_lite2wishbone_last_ar_aw_n_axilite2wishbone0_next_value_ce0 = 1'd0;
-	case (axilite2wishbone0_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		3'd4: begin
-		end
-		default: begin
-			if ((simsoc_blackparrotrv64_axi2wishbone0_ar_valid & simsoc_blackparrotrv64_axi2wishbone0_aw_valid)) begin
-				if (simsoc_blackparrotrv64_axi2wishbone0_axi_lite2wishbone_last_ar_aw_n) begin
-					simsoc_blackparrotrv64_axi2wishbone0_axi_lite2wishbone_last_ar_aw_n_axilite2wishbone0_next_value_ce0 = 1'd1;
-				end else begin
-					simsoc_blackparrotrv64_axi2wishbone0_axi_lite2wishbone_last_ar_aw_n_axilite2wishbone0_next_value_ce0 = 1'd1;
-				end
-			end else begin
-				if (simsoc_blackparrotrv64_axi2wishbone0_ar_valid) begin
-					simsoc_blackparrotrv64_axi2wishbone0_axi_lite2wishbone_last_ar_aw_n_axilite2wishbone0_next_value_ce0 = 1'd1;
-				end else begin
-					if (simsoc_blackparrotrv64_axi2wishbone0_aw_valid) begin
-						simsoc_blackparrotrv64_axi2wishbone0_axi_lite2wishbone_last_ar_aw_n_axilite2wishbone0_next_value_ce0 = 1'd1;
-					end
-				end
-			end
-		end
-	endcase
-end
-assign uart_eventmanager_status_r = csrbankarray_interface2_bank_bus_dat_w[1:0];
-assign simsoc_sram_bus_stb = shared_stb;
-assign csrbankarray_csrbank1_load1_we = ((csrbankarray_csrbank1_sel & (~csrbankarray_interface1_bank_bus_we)) & (csrbankarray_interface1_bank_bus_adr[4:0] == 2'd2));
-assign csrbankarray_csrbank1_update_value0_r = csrbankarray_interface1_bank_bus_dat_w[0];
-always @(*) begin
-	next_state = 1'd0;
-	next_state = state;
-	case (state)
-		1'd1: begin
-			next_state = 1'd0;
-		end
-		default: begin
-			if ((simsoc_bus_wishbone_cyc & simsoc_bus_wishbone_stb)) begin
-				next_state = 1'd1;
-			end
-		end
-	endcase
-end
-assign simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_beat_payload_id = simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_source_payload_id;
-assign uart_eventmanager_status_we = ((csrbankarray_csrbank2_sel & (~csrbankarray_interface2_bank_bus_we)) & (csrbankarray_interface2_bank_bus_adr[2:0] == 2'd3));
-always @(*) begin
-	slave_sel = 4'd0;
-	slave_sel[0] = (shared_adr[28:13] == 1'd0);
-	slave_sel[1] = (shared_adr[28:10] == 13'd4096);
-	slave_sel[2] = (shared_adr[28:26] == 3'd4);
-	slave_sel[3] = (shared_adr[28:22] == 2'd2);
-end
-assign csrbankarray_csrbank0_scratch1_w = simsoc_ctrl_storage[15:8];
-always @(*) begin
-	simsoc_blackparrotrv64_mmio_dc_read = 1'd0;
-	case (converter1_state)
-		1'd1: begin
-		end
-		2'd2: begin
-			simsoc_blackparrotrv64_mmio_dc_read = 1'd1;
-		end
-		default: begin
-		end
-	endcase
-end
-always @(*) begin
-	simsoc_blackparrotrv64_mmio_dc_write = 1'd0;
-	case (converter1_state)
-		1'd1: begin
-			simsoc_blackparrotrv64_mmio_dc_write = 1'd1;
-		end
-		2'd2: begin
-		end
-		default: begin
-		end
-	endcase
-end
-always @(*) begin
-	simsoc_blackparrotrv64_mmio_dc_counter_reset = 1'd0;
-	case (converter1_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		default: begin
-			simsoc_blackparrotrv64_mmio_dc_counter_reset = 1'd1;
-		end
-	endcase
-end
-always @(*) begin
-	simsoc_blackparrotrv64_mmio_dc_counter_ce = 1'd0;
-	case (converter1_state)
-		1'd1: begin
-			if ((simsoc_blackparrotrv64_mmio_wb_stb & simsoc_blackparrotrv64_mmio_wb_cyc)) begin
-				if (simsoc_blackparrotrv64_dbus_ack) begin
-					simsoc_blackparrotrv64_mmio_dc_counter_ce = 1'd1;
-				end
-			end else begin
-			end
-		end
-		2'd2: begin
-			if ((simsoc_blackparrotrv64_mmio_wb_stb & simsoc_blackparrotrv64_mmio_wb_cyc)) begin
-				if (simsoc_blackparrotrv64_dbus_ack) begin
-					simsoc_blackparrotrv64_mmio_dc_counter_ce = 1'd1;
-				end
-			end else begin
-			end
-		end
-		default: begin
-		end
-	endcase
-end
-assign simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_beat_size = (1'd1 <<< simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_source_payload_size);
-assign simsoc_blackparrotrv64_mmio_dc_counter_done = (simsoc_blackparrotrv64_mmio_dc_counter == 1'd1);
-assign uart_eventmanager_pending_re = ((csrbankarray_csrbank2_sel & csrbankarray_interface2_bank_bus_we) & (csrbankarray_interface2_bank_bus_adr[2:0] == 3'd4));
-assign csrbankarray_csrbank0_scratch0_re = ((csrbankarray_csrbank0_sel & csrbankarray_interface0_bank_bus_we) & (csrbankarray_interface0_bank_bus_adr[3:0] == 3'd4));
-assign uart_eventmanager_pending_r = csrbankarray_interface2_bank_bus_dat_w[1:0];
-assign csrbankarray_csrbank0_scratch1_re = ((csrbankarray_csrbank0_sel & csrbankarray_interface0_bank_bus_we) & (csrbankarray_interface0_bank_bus_adr[3:0] == 2'd3));
-always @(*) begin
-	error = 1'd0;
-	if (done) begin
-		error = 1'd1;
-	end
-end
-assign uart_rxtx_we = ((csrbankarray_csrbank2_sel & (~csrbankarray_interface2_bank_bus_we)) & (csrbankarray_interface2_bank_bus_adr[2:0] == 1'd0));
-assign wait_1 = ((shared_stb & shared_cyc) & (~shared_ack));
-assign csrbankarray_csrbank1_reload0_r = csrbankarray_interface1_bank_bus_dat_w[7:0];
-assign done = (count == 1'd0);
-assign csrbankarray_csrbank1_load1_r = csrbankarray_interface1_bank_bus_dat_w[7:0];
-always @(*) begin
-	array_muxed7 = 2'd0;
-	case (grant)
-		1'd0: begin
-			array_muxed7 = simsoc_blackparrotrv64_ibus_bte;
-		end
-		default: begin
-			array_muxed7 = simsoc_blackparrotrv64_dbus_bte;
-		end
-	endcase
-end
-assign simsoc_rom_bus_adr = shared_adr;
-assign simsoc_rom_bus_dat_w = shared_dat_w;
-assign simsoc_rom_bus_dat_r = simsoc_rom_dat_r;
-assign simsoc_rom_bus_sel = shared_sel;
-assign csrbankarray_csrbank1_value0_r = csrbankarray_interface1_bank_bus_dat_w[7:0];
-assign simsoc_rom_bus_cyc = (shared_cyc & slave_sel[0]);
-assign csrbankarray_csrbank0_scratch0_w = simsoc_ctrl_storage[7:0];
-assign simsoc_rom_bus_stb = shared_stb;
-assign csrbankarray_interface0_bank_bus_we = csrcon_we;
-assign simsoc_rom_bus_we = shared_we;
-assign simsoc_rom_bus_cti = shared_cti;
-assign simsoc_rom_bus_bte = shared_bte;
-assign csrbankarray_csrbank0_scratch3_re = ((csrbankarray_csrbank0_sel & csrbankarray_interface0_bank_bus_we) & (csrbankarray_interface0_bank_bus_adr[3:0] == 1'd1));
-assign csrbankarray_csrbank0_scratch3_r = csrbankarray_interface0_bank_bus_dat_w[7:0];
-assign simsoc_rom_adr = simsoc_rom_bus_adr[12:0];
-assign csrbankarray_csrbank0_scratch3_w = simsoc_ctrl_storage[31:24];
-assign csrbankarray_csrbank0_scratch2_re = ((csrbankarray_csrbank0_sel & csrbankarray_interface0_bank_bus_we) & (csrbankarray_interface0_bank_bus_adr[3:0] == 2'd2));
-assign csrbankarray_csrbank0_scratch2_r = csrbankarray_interface0_bank_bus_dat_w[7:0];
-assign csrbankarray_csrbank0_scratch2_we = ((csrbankarray_csrbank0_sel & (~csrbankarray_interface0_bank_bus_we)) & (csrbankarray_interface0_bank_bus_adr[3:0] == 2'd2));
-assign simsoc_sram_bus_adr = shared_adr;
-assign csrbankarray_csrbank0_scratch2_w = simsoc_ctrl_storage[23:16];
-assign simsoc_sram_bus_dat_w = shared_dat_w;
-assign simsoc_sram_bus_dat_r = simsoc_sram_dat_r;
-assign simsoc_sram_bus_sel = shared_sel;
-assign simsoc_sram_bus_cyc = (shared_cyc & slave_sel[1]);
-assign csrbankarray_csrbank0_bus_errors0_w = simsoc_ctrl_bus_errors_status[7:0];
-assign uart_rx_fifo_syncfifo_we = uart_rx_fifo_sink_valid;
-always @(*) begin
-	simsoc_interface_adr = 14'd0;
-	case (state)
-		1'd1: begin
-		end
-		default: begin
-			if ((simsoc_bus_wishbone_cyc & simsoc_bus_wishbone_stb)) begin
-				simsoc_interface_adr = simsoc_bus_wishbone_adr;
-			end
-		end
-	endcase
-end
-assign simsoc_sram_bus_we = shared_we;
-assign simsoc_sram_bus_cti = shared_cti;
-assign uart_rxtx_w = uart_rx_fifo_source_payload_data;
-assign simsoc_sram_bus_bte = shared_bte;
-assign csrbankarray_csrbank0_scratch0_r = csrbankarray_interface0_bank_bus_dat_w[7:0];
-assign csrbankarray_csrbank1_ev_enable0_re = ((csrbankarray_csrbank1_sel & csrbankarray_interface1_bank_bus_we) & (csrbankarray_interface1_bank_bus_adr[4:0] == 5'd16));
-assign csrbankarray_csrbank0_scratch0_we = ((csrbankarray_csrbank0_sel & (~csrbankarray_interface0_bank_bus_we)) & (csrbankarray_interface0_bank_bus_adr[3:0] == 3'd4));
-assign simsoc_sram_adr = simsoc_sram_bus_adr[9:0];
-always @(*) begin
-	simsoc_sram_we = 4'd0;
-	simsoc_sram_we[0] = (((simsoc_sram_bus_cyc & simsoc_sram_bus_stb) & simsoc_sram_bus_we) & simsoc_sram_bus_sel[0]);
-	simsoc_sram_we[1] = (((simsoc_sram_bus_cyc & simsoc_sram_bus_stb) & simsoc_sram_bus_we) & simsoc_sram_bus_sel[1]);
-	simsoc_sram_we[2] = (((simsoc_sram_bus_cyc & simsoc_sram_bus_stb) & simsoc_sram_bus_we) & simsoc_sram_bus_sel[2]);
-	simsoc_sram_we[3] = (((simsoc_sram_bus_cyc & simsoc_sram_bus_stb) & simsoc_sram_bus_we) & simsoc_sram_bus_sel[3]);
-end
-assign csrbankarray_csrbank0_bus_errors3_re = ((csrbankarray_csrbank0_sel & csrbankarray_interface0_bank_bus_we) & (csrbankarray_interface0_bank_bus_adr[3:0] == 3'd5));
-assign simsoc_sram_dat_w = simsoc_sram_bus_dat_w;
-assign csrbankarray_csrbank0_bus_errors3_r = csrbankarray_interface0_bank_bus_dat_w[7:0];
-assign csrbankarray_csrbank0_bus_errors3_we = ((csrbankarray_csrbank0_sel & (~csrbankarray_interface0_bank_bus_we)) & (csrbankarray_interface0_bank_bus_adr[3:0] == 3'd5));
-
-always @(posedge por_clk) begin
-	int_rst <= 1'd0;
-end
-
-always @(posedge sys_clk_1) begin
-	if ((simsoc_ctrl_bus_errors != 32'd4294967295)) begin
-		if (simsoc_ctrl_bus_error) begin
-			simsoc_ctrl_bus_errors <= (simsoc_ctrl_bus_errors + 1'd1);
-		end
-	end
-	if (simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_pipe_ce) begin
-		simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_valid_n <= simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_sink_valid;
-	end
-	if (simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_pipe_ce) begin
-		simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_first_n <= (simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_sink_valid & simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_sink_first);
-		simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_last_n <= (simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_sink_valid & simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_sink_last);
-	end
-	if (simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_pipe_ce) begin
-		simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_source_payload_addr <= simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_sink_payload_addr;
-		simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_source_payload_burst <= simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_sink_payload_burst;
-		simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_source_payload_len <= simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_sink_payload_len;
-		simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_source_payload_size <= simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_sink_payload_size;
-		simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_source_payload_lock <= simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_sink_payload_lock;
-		simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_source_payload_prot <= simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_sink_payload_prot;
-		simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_source_payload_cache <= simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_sink_payload_cache;
-		simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_source_payload_qos <= simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_sink_payload_qos;
-		simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_source_payload_id <= simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_sink_payload_id;
-	end
-	if ((simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_beat_valid & simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_beat_ready)) begin
-		if (simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_ax_beat_last) begin
-			simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_beat_count <= 1'd0;
-			simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_beat_offset <= 1'd0;
-		end else begin
-			simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_beat_count <= (simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_beat_count + 1'd1);
-			if ((((simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_source_payload_burst == 1'd1) & 1'd1) | ((simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_source_payload_burst == 2'd2) & 1'd1))) begin
-				simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_beat_offset <= (simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_beat_offset + simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_beat_size);
-			end
-		end
-		if (((simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_source_payload_burst == 2'd2) & 1'd1)) begin
-			if ((simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_beat_offset == simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_beat_wrap)) begin
-				simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_beat_offset <= 1'd0;
-			end
-		end
-	end
-	axi2axilite0_state <= axi2axilite0_next_state;
-	if (simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_cmd_done_axi2axilite0_next_value_ce0) begin
-		simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_cmd_done <= simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_cmd_done_axi2axilite0_next_value0;
-	end
-	if (simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_last_ar_aw_n_axi2axilite0_next_value_ce1) begin
-		simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_last_ar_aw_n <= simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_last_ar_aw_n_axi2axilite0_next_value1;
-	end
-	axilite2wishbone0_state <= axilite2wishbone0_next_state;
-	if (simsoc_blackparrotrv64_axi2wishbone0_axi_lite2wishbone_last_ar_aw_n_axilite2wishbone0_next_value_ce0) begin
-		simsoc_blackparrotrv64_axi2wishbone0_axi_lite2wishbone_last_ar_aw_n <= simsoc_blackparrotrv64_axi2wishbone0_axi_lite2wishbone_last_ar_aw_n_axilite2wishbone0_next_value0;
-	end
-	if (simsoc_blackparrotrv64_axi2wishbone0_axi_lite2wishbone_data_axilite2wishbone0_next_value_ce1) begin
-		simsoc_blackparrotrv64_axi2wishbone0_axi_lite2wishbone_data <= simsoc_blackparrotrv64_axi2wishbone0_axi_lite2wishbone_data_axilite2wishbone0_next_value1;
-	end
-	if (simsoc_blackparrotrv64_mem_a2w_reset) begin
-		simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_source_payload_addr <= 32'd0;
-		simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_source_payload_burst <= 2'd0;
-		simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_source_payload_len <= 8'd0;
-		simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_source_payload_size <= 4'd0;
-		simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_source_payload_lock <= 2'd0;
-		simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_source_payload_prot <= 3'd0;
-		simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_source_payload_cache <= 4'd0;
-		simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_source_payload_qos <= 4'd0;
-		simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_source_payload_id <= 4'd0;
-		simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_valid_n <= 1'd0;
-		simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_first_n <= 1'd0;
-		simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_last_n <= 1'd0;
-		simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_beat_count <= 8'd0;
-		simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_beat_offset <= 12'd0;
-		simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_cmd_done <= 1'd0;
-		simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_last_ar_aw_n <= 1'd0;
-		simsoc_blackparrotrv64_axi2wishbone0_axi_lite2wishbone_data <= 64'd0;
-		simsoc_blackparrotrv64_axi2wishbone0_axi_lite2wishbone_last_ar_aw_n <= 1'd0;
-		axi2axilite0_state <= 2'd0;
-		axilite2wishbone0_state <= 3'd0;
-	end
-	if (simsoc_blackparrotrv64_mem_dc_counter_reset) begin
-		simsoc_blackparrotrv64_mem_dc_counter <= 1'd0;
-	end else begin
-		if (simsoc_blackparrotrv64_mem_dc_counter_ce) begin
-			simsoc_blackparrotrv64_mem_dc_counter <= (simsoc_blackparrotrv64_mem_dc_counter + 1'd1);
-		end
-	end
-	if ((simsoc_blackparrotrv64_mem_dc_read & simsoc_blackparrotrv64_mem_dc_counter_ce)) begin
-		simsoc_blackparrotrv64_mem_dc_cached_data <= simsoc_blackparrotrv64_mem_wb_dat_r;
-	end
-	converter0_state <= converter0_next_state;
-	if (simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_pipe_ce) begin
-		simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_valid_n <= simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_sink_valid;
-	end
-	if (simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_pipe_ce) begin
-		simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_first_n <= (simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_sink_valid & simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_sink_first);
-		simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_last_n <= (simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_sink_valid & simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_sink_last);
-	end
-	if (simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_pipe_ce) begin
-		simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_source_payload_addr <= simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_sink_payload_addr;
-		simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_source_payload_burst <= simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_sink_payload_burst;
-		simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_source_payload_len <= simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_sink_payload_len;
-		simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_source_payload_size <= simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_sink_payload_size;
-		simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_source_payload_lock <= simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_sink_payload_lock;
-		simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_source_payload_prot <= simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_sink_payload_prot;
-		simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_source_payload_cache <= simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_sink_payload_cache;
-		simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_source_payload_qos <= simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_sink_payload_qos;
-		simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_source_payload_id <= simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_sink_payload_id;
-	end
-	if ((simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_beat_valid & simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_beat_ready)) begin
-		if (simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_ax_beat_last) begin
-			simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_beat_count <= 1'd0;
-			simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_beat_offset <= 1'd0;
-		end else begin
-			simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_beat_count <= (simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_beat_count + 1'd1);
-			if ((((simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_source_payload_burst == 1'd1) & 1'd1) | ((simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_source_payload_burst == 2'd2) & 1'd1))) begin
-				simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_beat_offset <= (simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_beat_offset + simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_beat_size);
-			end
-		end
-		if (((simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_source_payload_burst == 2'd2) & 1'd1)) begin
-			if ((simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_beat_offset == simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_beat_wrap)) begin
-				simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_beat_offset <= 1'd0;
-			end
-		end
-	end
-	axi2axilite1_state <= axi2axilite1_next_state;
-	if (simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_cmd_done_axi2axilite1_next_value_ce0) begin
-		simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_cmd_done <= simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_cmd_done_axi2axilite1_next_value0;
-	end
-	if (simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_last_ar_aw_n_axi2axilite1_next_value_ce1) begin
-		simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_last_ar_aw_n <= simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_last_ar_aw_n_axi2axilite1_next_value1;
-	end
-	axilite2wishbone1_state <= axilite2wishbone1_next_state;
-	if (simsoc_blackparrotrv64_axi2wishbone1_axi_lite2wishbone_last_ar_aw_n_axilite2wishbone1_next_value_ce0) begin
-		simsoc_blackparrotrv64_axi2wishbone1_axi_lite2wishbone_last_ar_aw_n <= simsoc_blackparrotrv64_axi2wishbone1_axi_lite2wishbone_last_ar_aw_n_axilite2wishbone1_next_value0;
-	end
-	if (simsoc_blackparrotrv64_axi2wishbone1_axi_lite2wishbone_data_axilite2wishbone1_next_value_ce1) begin
-		simsoc_blackparrotrv64_axi2wishbone1_axi_lite2wishbone_data <= simsoc_blackparrotrv64_axi2wishbone1_axi_lite2wishbone_data_axilite2wishbone1_next_value1;
-	end
-	if (simsoc_blackparrotrv64_mmio_a2w_reset) begin
-		simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_source_payload_addr <= 32'd0;
-		simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_source_payload_burst <= 2'd0;
-		simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_source_payload_len <= 8'd0;
-		simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_source_payload_size <= 4'd0;
-		simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_source_payload_lock <= 2'd0;
-		simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_source_payload_prot <= 3'd0;
-		simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_source_payload_cache <= 4'd0;
-		simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_source_payload_qos <= 4'd0;
-		simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_source_payload_id <= 4'd0;
-		simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_valid_n <= 1'd0;
-		simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_first_n <= 1'd0;
-		simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_last_n <= 1'd0;
-		simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_beat_count <= 8'd0;
-		simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_beat_offset <= 12'd0;
-		simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_cmd_done <= 1'd0;
-		simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_last_ar_aw_n <= 1'd0;
-		simsoc_blackparrotrv64_axi2wishbone1_axi_lite2wishbone_data <= 64'd0;
-		simsoc_blackparrotrv64_axi2wishbone1_axi_lite2wishbone_last_ar_aw_n <= 1'd0;
-		axi2axilite1_state <= 2'd0;
-		axilite2wishbone1_state <= 3'd0;
-	end
-	if (simsoc_blackparrotrv64_mmio_dc_counter_reset) begin
-		simsoc_blackparrotrv64_mmio_dc_counter <= 1'd0;
-	end else begin
-		if (simsoc_blackparrotrv64_mmio_dc_counter_ce) begin
-			simsoc_blackparrotrv64_mmio_dc_counter <= (simsoc_blackparrotrv64_mmio_dc_counter + 1'd1);
-		end
-	end
-	if ((simsoc_blackparrotrv64_mmio_dc_read & simsoc_blackparrotrv64_mmio_dc_counter_ce)) begin
-		simsoc_blackparrotrv64_mmio_dc_cached_data <= simsoc_blackparrotrv64_mmio_wb_dat_r;
-	end
-	converter1_state <= converter1_next_state;
-	simsoc_rom_bus_ack <= 1'd0;
-	if (((simsoc_rom_bus_cyc & simsoc_rom_bus_stb) & (~simsoc_rom_bus_ack))) begin
-		simsoc_rom_bus_ack <= 1'd1;
-	end
-	simsoc_sram_bus_ack <= 1'd0;
-	if (((simsoc_sram_bus_cyc & simsoc_sram_bus_stb) & (~simsoc_sram_bus_ack))) begin
-		simsoc_sram_bus_ack <= 1'd1;
-	end
-	simsoc_main_ram_bus_ack <= 1'd0;
-	if (((simsoc_main_ram_bus_cyc & simsoc_main_ram_bus_stb) & (~simsoc_main_ram_bus_ack))) begin
-		simsoc_main_ram_bus_ack <= 1'd1;
-	end
-	if (simsoc_en_storage) begin
-		if ((simsoc_value == 1'd0)) begin
-			simsoc_value <= simsoc_reload_storage;
-		end else begin
-			simsoc_value <= (simsoc_value - 1'd1);
-		end
-	end else begin
-		simsoc_value <= simsoc_load_storage;
-	end
-	if (simsoc_update_value_re) begin
-		simsoc_value_status <= simsoc_value;
-	end
-	if (simsoc_zero_clear) begin
-		simsoc_zero_pending <= 1'd0;
-	end
-	simsoc_zero_old_trigger <= simsoc_zero_trigger;
-	if (((~simsoc_zero_trigger) & simsoc_zero_old_trigger)) begin
-		simsoc_zero_pending <= 1'd1;
-	end
-	state <= next_state;
-	if (uart_tx_clear) begin
-		uart_tx_pending <= 1'd0;
-	end
-	uart_tx_old_trigger <= uart_tx_trigger;
-	if (((~uart_tx_trigger) & uart_tx_old_trigger)) begin
-		uart_tx_pending <= 1'd1;
-	end
-	if (uart_rx_clear) begin
-		uart_rx_pending <= 1'd0;
-	end
-	uart_rx_old_trigger <= uart_rx_trigger;
-	if (((~uart_rx_trigger) & uart_rx_old_trigger)) begin
-		uart_rx_pending <= 1'd1;
-	end
-	if (uart_tx_fifo_syncfifo_re) begin
-		uart_tx_fifo_readable <= 1'd1;
-	end else begin
-		if (uart_tx_fifo_re) begin
-			uart_tx_fifo_readable <= 1'd0;
-		end
-	end
-	if (((uart_tx_fifo_syncfifo_we & uart_tx_fifo_syncfifo_writable) & (~uart_tx_fifo_replace))) begin
-		uart_tx_fifo_produce <= (uart_tx_fifo_produce + 1'd1);
-	end
-	if (uart_tx_fifo_do_read) begin
-		uart_tx_fifo_consume <= (uart_tx_fifo_consume + 1'd1);
-	end
-	if (((uart_tx_fifo_syncfifo_we & uart_tx_fifo_syncfifo_writable) & (~uart_tx_fifo_replace))) begin
-		if ((~uart_tx_fifo_do_read)) begin
-			uart_tx_fifo_level0 <= (uart_tx_fifo_level0 + 1'd1);
-		end
-	end else begin
-		if (uart_tx_fifo_do_read) begin
-			uart_tx_fifo_level0 <= (uart_tx_fifo_level0 - 1'd1);
-		end
-	end
-	if (uart_rx_fifo_syncfifo_re) begin
-		uart_rx_fifo_readable <= 1'd1;
-	end else begin
-		if (uart_rx_fifo_re) begin
-			uart_rx_fifo_readable <= 1'd0;
-		end
-	end
-	if (((uart_rx_fifo_syncfifo_we & uart_rx_fifo_syncfifo_writable) & (~uart_rx_fifo_replace))) begin
-		uart_rx_fifo_produce <= (uart_rx_fifo_produce + 1'd1);
-	end
-	if (uart_rx_fifo_do_read) begin
-		uart_rx_fifo_consume <= (uart_rx_fifo_consume + 1'd1);
-	end
-	if (((uart_rx_fifo_syncfifo_we & uart_rx_fifo_syncfifo_writable) & (~uart_rx_fifo_replace))) begin
-		if ((~uart_rx_fifo_do_read)) begin
-			uart_rx_fifo_level0 <= (uart_rx_fifo_level0 + 1'd1);
-		end
-	end else begin
-		if (uart_rx_fifo_do_read) begin
-			uart_rx_fifo_level0 <= (uart_rx_fifo_level0 - 1'd1);
-		end
-	end
-	case (grant)
-		1'd0: begin
-			if ((~request[0])) begin
-				if (request[1]) begin
-					grant <= 1'd1;
-				end
-			end
-		end
-		1'd1: begin
-			if ((~request[1])) begin
-				if (request[0]) begin
-					grant <= 1'd0;
-				end
-			end
-		end
-	endcase
-	slave_sel_r <= slave_sel;
-	if (wait_1) begin
-		if ((~done)) begin
-			count <= (count - 1'd1);
-		end
-	end else begin
-		count <= 20'd1000000;
-	end
-	csrbankarray_interface0_bank_bus_dat_r <= 1'd0;
-	if (csrbankarray_csrbank0_sel) begin
-		case (csrbankarray_interface0_bank_bus_adr[3:0])
-			1'd0: begin
-				csrbankarray_interface0_bank_bus_dat_r <= simsoc_ctrl_reset_reset_w;
-			end
-			1'd1: begin
-				csrbankarray_interface0_bank_bus_dat_r <= csrbankarray_csrbank0_scratch3_w;
-			end
-			2'd2: begin
-				csrbankarray_interface0_bank_bus_dat_r <= csrbankarray_csrbank0_scratch2_w;
-			end
-			2'd3: begin
-				csrbankarray_interface0_bank_bus_dat_r <= csrbankarray_csrbank0_scratch1_w;
-			end
-			3'd4: begin
-				csrbankarray_interface0_bank_bus_dat_r <= csrbankarray_csrbank0_scratch0_w;
-			end
-			3'd5: begin
-				csrbankarray_interface0_bank_bus_dat_r <= csrbankarray_csrbank0_bus_errors3_w;
-			end
-			3'd6: begin
-				csrbankarray_interface0_bank_bus_dat_r <= csrbankarray_csrbank0_bus_errors2_w;
-			end
-			3'd7: begin
-				csrbankarray_interface0_bank_bus_dat_r <= csrbankarray_csrbank0_bus_errors1_w;
-			end
-			4'd8: begin
-				csrbankarray_interface0_bank_bus_dat_r <= csrbankarray_csrbank0_bus_errors0_w;
-			end
-		endcase
-	end
-	if (csrbankarray_csrbank0_scratch3_re) begin
-		simsoc_ctrl_storage[31:24] <= csrbankarray_csrbank0_scratch3_r;
-	end
-	if (csrbankarray_csrbank0_scratch2_re) begin
-		simsoc_ctrl_storage[23:16] <= csrbankarray_csrbank0_scratch2_r;
-	end
-	if (csrbankarray_csrbank0_scratch1_re) begin
-		simsoc_ctrl_storage[15:8] <= csrbankarray_csrbank0_scratch1_r;
-	end
-	if (csrbankarray_csrbank0_scratch0_re) begin
-		simsoc_ctrl_storage[7:0] <= csrbankarray_csrbank0_scratch0_r;
-	end
-	simsoc_ctrl_re <= csrbankarray_csrbank0_scratch0_re;
-	csrbankarray_sel_r <= csrbankarray_sel;
-	csrbankarray_interface1_bank_bus_dat_r <= 1'd0;
-	if (csrbankarray_csrbank1_sel) begin
-		case (csrbankarray_interface1_bank_bus_adr[4:0])
-			1'd0: begin
-				csrbankarray_interface1_bank_bus_dat_r <= csrbankarray_csrbank1_load3_w;
-			end
-			1'd1: begin
-				csrbankarray_interface1_bank_bus_dat_r <= csrbankarray_csrbank1_load2_w;
-			end
-			2'd2: begin
-				csrbankarray_interface1_bank_bus_dat_r <= csrbankarray_csrbank1_load1_w;
-			end
-			2'd3: begin
-				csrbankarray_interface1_bank_bus_dat_r <= csrbankarray_csrbank1_load0_w;
-			end
-			3'd4: begin
-				csrbankarray_interface1_bank_bus_dat_r <= csrbankarray_csrbank1_reload3_w;
-			end
-			3'd5: begin
-				csrbankarray_interface1_bank_bus_dat_r <= csrbankarray_csrbank1_reload2_w;
-			end
-			3'd6: begin
-				csrbankarray_interface1_bank_bus_dat_r <= csrbankarray_csrbank1_reload1_w;
-			end
-			3'd7: begin
-				csrbankarray_interface1_bank_bus_dat_r <= csrbankarray_csrbank1_reload0_w;
-			end
-			4'd8: begin
-				csrbankarray_interface1_bank_bus_dat_r <= csrbankarray_csrbank1_en0_w;
-			end
-			4'd9: begin
-				csrbankarray_interface1_bank_bus_dat_r <= csrbankarray_csrbank1_update_value0_w;
-			end
-			4'd10: begin
-				csrbankarray_interface1_bank_bus_dat_r <= csrbankarray_csrbank1_value3_w;
-			end
-			4'd11: begin
-				csrbankarray_interface1_bank_bus_dat_r <= csrbankarray_csrbank1_value2_w;
-			end
-			4'd12: begin
-				csrbankarray_interface1_bank_bus_dat_r <= csrbankarray_csrbank1_value1_w;
-			end
-			4'd13: begin
-				csrbankarray_interface1_bank_bus_dat_r <= csrbankarray_csrbank1_value0_w;
-			end
-			4'd14: begin
-				csrbankarray_interface1_bank_bus_dat_r <= simsoc_eventmanager_status_w;
-			end
-			4'd15: begin
-				csrbankarray_interface1_bank_bus_dat_r <= simsoc_eventmanager_pending_w;
-			end
-			5'd16: begin
-				csrbankarray_interface1_bank_bus_dat_r <= csrbankarray_csrbank1_ev_enable0_w;
-			end
-		endcase
-	end
-	if (csrbankarray_csrbank1_load3_re) begin
-		simsoc_load_storage[31:24] <= csrbankarray_csrbank1_load3_r;
-	end
-	if (csrbankarray_csrbank1_load2_re) begin
-		simsoc_load_storage[23:16] <= csrbankarray_csrbank1_load2_r;
-	end
-	if (csrbankarray_csrbank1_load1_re) begin
-		simsoc_load_storage[15:8] <= csrbankarray_csrbank1_load1_r;
-	end
-	if (csrbankarray_csrbank1_load0_re) begin
-		simsoc_load_storage[7:0] <= csrbankarray_csrbank1_load0_r;
-	end
-	simsoc_load_re <= csrbankarray_csrbank1_load0_re;
-	if (csrbankarray_csrbank1_reload3_re) begin
-		simsoc_reload_storage[31:24] <= csrbankarray_csrbank1_reload3_r;
-	end
-	if (csrbankarray_csrbank1_reload2_re) begin
-		simsoc_reload_storage[23:16] <= csrbankarray_csrbank1_reload2_r;
-	end
-	if (csrbankarray_csrbank1_reload1_re) begin
-		simsoc_reload_storage[15:8] <= csrbankarray_csrbank1_reload1_r;
-	end
-	if (csrbankarray_csrbank1_reload0_re) begin
-		simsoc_reload_storage[7:0] <= csrbankarray_csrbank1_reload0_r;
-	end
-	simsoc_reload_re <= csrbankarray_csrbank1_reload0_re;
-	if (csrbankarray_csrbank1_en0_re) begin
-		simsoc_en_storage <= csrbankarray_csrbank1_en0_r;
-	end
-	simsoc_en_re <= csrbankarray_csrbank1_en0_re;
-	if (csrbankarray_csrbank1_update_value0_re) begin
-		simsoc_update_value_storage <= csrbankarray_csrbank1_update_value0_r;
-	end
-	simsoc_update_value_re <= csrbankarray_csrbank1_update_value0_re;
-	if (csrbankarray_csrbank1_ev_enable0_re) begin
-		simsoc_eventmanager_storage <= csrbankarray_csrbank1_ev_enable0_r;
-	end
-	simsoc_eventmanager_re <= csrbankarray_csrbank1_ev_enable0_re;
-	csrbankarray_interface2_bank_bus_dat_r <= 1'd0;
-	if (csrbankarray_csrbank2_sel) begin
-		case (csrbankarray_interface2_bank_bus_adr[2:0])
-			1'd0: begin
-				csrbankarray_interface2_bank_bus_dat_r <= uart_rxtx_w;
-			end
-			1'd1: begin
-				csrbankarray_interface2_bank_bus_dat_r <= csrbankarray_csrbank2_txfull_w;
-			end
-			2'd2: begin
-				csrbankarray_interface2_bank_bus_dat_r <= csrbankarray_csrbank2_rxempty_w;
-			end
-			2'd3: begin
-				csrbankarray_interface2_bank_bus_dat_r <= uart_eventmanager_status_w;
-			end
-			3'd4: begin
-				csrbankarray_interface2_bank_bus_dat_r <= uart_eventmanager_pending_w;
-			end
-			3'd5: begin
-				csrbankarray_interface2_bank_bus_dat_r <= csrbankarray_csrbank2_ev_enable0_w;
-			end
-		endcase
-	end
-	if (csrbankarray_csrbank2_ev_enable0_re) begin
-		uart_eventmanager_storage[1:0] <= csrbankarray_csrbank2_ev_enable0_r;
-	end
-	uart_eventmanager_re <= csrbankarray_csrbank2_ev_enable0_re;
-	if (sys_rst) begin
-		simsoc_ctrl_storage <= 32'd305419896;
-		simsoc_ctrl_re <= 1'd0;
-		simsoc_ctrl_bus_errors <= 32'd0;
-		simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_source_payload_addr <= 32'd0;
-		simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_source_payload_burst <= 2'd0;
-		simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_source_payload_len <= 8'd0;
-		simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_source_payload_size <= 4'd0;
-		simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_source_payload_lock <= 2'd0;
-		simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_source_payload_prot <= 3'd0;
-		simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_source_payload_cache <= 4'd0;
-		simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_source_payload_qos <= 4'd0;
-		simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_source_payload_id <= 4'd0;
-		simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_valid_n <= 1'd0;
-		simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_first_n <= 1'd0;
-		simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_last_n <= 1'd0;
-		simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_beat_count <= 8'd0;
-		simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_beat_offset <= 12'd0;
-		simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_cmd_done <= 1'd0;
-		simsoc_blackparrotrv64_axi2wishbone0_axi2axi_lite_last_ar_aw_n <= 1'd0;
-		simsoc_blackparrotrv64_axi2wishbone0_axi_lite2wishbone_data <= 64'd0;
-		simsoc_blackparrotrv64_axi2wishbone0_axi_lite2wishbone_last_ar_aw_n <= 1'd0;
-		simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_source_payload_addr <= 32'd0;
-		simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_source_payload_burst <= 2'd0;
-		simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_source_payload_len <= 8'd0;
-		simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_source_payload_size <= 4'd0;
-		simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_source_payload_lock <= 2'd0;
-		simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_source_payload_prot <= 3'd0;
-		simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_source_payload_cache <= 4'd0;
-		simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_source_payload_qos <= 4'd0;
-		simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_source_payload_id <= 4'd0;
-		simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_valid_n <= 1'd0;
-		simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_first_n <= 1'd0;
-		simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_last_n <= 1'd0;
-		simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_beat_count <= 8'd0;
-		simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_beat_offset <= 12'd0;
-		simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_cmd_done <= 1'd0;
-		simsoc_blackparrotrv64_axi2wishbone1_axi2axi_lite_last_ar_aw_n <= 1'd0;
-		simsoc_blackparrotrv64_axi2wishbone1_axi_lite2wishbone_data <= 64'd0;
-		simsoc_blackparrotrv64_axi2wishbone1_axi_lite2wishbone_last_ar_aw_n <= 1'd0;
-		simsoc_blackparrotrv64_mem_dc_counter <= 1'd0;
-		simsoc_blackparrotrv64_mem_dc_cached_data <= 64'd0;
-		simsoc_blackparrotrv64_mmio_dc_counter <= 1'd0;
-		simsoc_blackparrotrv64_mmio_dc_cached_data <= 64'd0;
-		simsoc_rom_bus_ack <= 1'd0;
-		simsoc_sram_bus_ack <= 1'd0;
-		simsoc_main_ram_bus_ack <= 1'd0;
-		simsoc_load_storage <= 32'd0;
-		simsoc_load_re <= 1'd0;
-		simsoc_reload_storage <= 32'd0;
-		simsoc_reload_re <= 1'd0;
-		simsoc_en_storage <= 1'd0;
-		simsoc_en_re <= 1'd0;
-		simsoc_update_value_storage <= 1'd0;
-		simsoc_update_value_re <= 1'd0;
-		simsoc_value_status <= 32'd0;
-		simsoc_zero_pending <= 1'd0;
-		simsoc_zero_old_trigger <= 1'd0;
-		simsoc_eventmanager_storage <= 1'd0;
-		simsoc_eventmanager_re <= 1'd0;
-		simsoc_value <= 32'd0;
-		uart_tx_pending <= 1'd0;
-		uart_tx_old_trigger <= 1'd0;
-		uart_rx_pending <= 1'd0;
-		uart_rx_old_trigger <= 1'd0;
-		uart_eventmanager_storage <= 2'd0;
-		uart_eventmanager_re <= 1'd0;
-		uart_tx_fifo_readable <= 1'd0;
-		uart_tx_fifo_level0 <= 5'd0;
-		uart_tx_fifo_produce <= 4'd0;
-		uart_tx_fifo_consume <= 4'd0;
-		uart_rx_fifo_readable <= 1'd0;
-		uart_rx_fifo_level0 <= 5'd0;
-		uart_rx_fifo_produce <= 4'd0;
-		uart_rx_fifo_consume <= 4'd0;
-		axi2axilite0_state <= 2'd0;
-		axilite2wishbone0_state <= 3'd0;
-		converter0_state <= 2'd0;
-		axi2axilite1_state <= 2'd0;
-		axilite2wishbone1_state <= 3'd0;
-		converter1_state <= 2'd0;
-		state <= 1'd0;
-		grant <= 1'd0;
-		slave_sel_r <= 4'd0;
-		count <= 20'd1000000;
-		csrbankarray_interface0_bank_bus_dat_r <= 8'd0;
-		csrbankarray_sel_r <= 1'd0;
-		csrbankarray_interface1_bank_bus_dat_r <= 8'd0;
-		csrbankarray_interface2_bank_bus_dat_r <= 8'd0;
-	end
-end
-
-ExampleBlackParrotSystemHEY ExampleBlackParrotSystemHEY(
-	.clock(sys_clk_1),
-	.debug_clockeddmi_dmiClock(1'd0),
-	.debug_clockeddmi_dmiReset(1'd0),
-	.debug_clockeddmi_dmi_req_bits_addr(1'd0),
-	.debug_clockeddmi_dmi_req_bits_data(1'd0),
-	.debug_clockeddmi_dmi_req_bits_op(1'd0),
-	.debug_clockeddmi_dmi_req_valid(1'd0),
-	.debug_clockeddmi_dmi_resp_ready(1'd0),
-	.interrupts(simsoc_blackparrotrv64_interrupt),
-	.mem_axi4_0_ar_ready(simsoc_blackparrotrv64_mem_axi_ar_ready),
-	.mem_axi4_0_aw_ready(simsoc_blackparrotrv64_mem_axi_aw_ready),
-	.mem_axi4_0_b_bits_id(simsoc_blackparrotrv64_mem_axi_b_payload_id),
-	.mem_axi4_0_b_bits_resp(simsoc_blackparrotrv64_mem_axi_b_payload_resp),
-	.mem_axi4_0_b_valid(simsoc_blackparrotrv64_mem_axi_b_valid),
-	.mem_axi4_0_r_bits_data(simsoc_blackparrotrv64_mem_axi_r_payload_data),
-	.mem_axi4_0_r_bits_id(simsoc_blackparrotrv64_mem_axi_r_payload_id),
-	.mem_axi4_0_r_bits_last(simsoc_blackparrotrv64_mem_axi_r_last),
-	.mem_axi4_0_r_bits_resp(simsoc_blackparrotrv64_mem_axi_r_payload_resp),
-	.mem_axi4_0_r_valid(simsoc_blackparrotrv64_mem_axi_r_valid),
-	.mem_axi4_0_w_ready(simsoc_blackparrotrv64_mem_axi_w_ready),
-	.mmio_axi4_0_ar_ready(simsoc_blackparrotrv64_mmio_axi_ar_ready),
-	.mmio_axi4_0_aw_ready(simsoc_blackparrotrv64_mmio_axi_aw_ready),
-	.mmio_axi4_0_b_bits_id(simsoc_blackparrotrv64_mmio_axi_b_payload_id),
-	.mmio_axi4_0_b_bits_resp(simsoc_blackparrotrv64_mmio_axi_b_payload_resp),
-	.mmio_axi4_0_b_valid(simsoc_blackparrotrv64_mmio_axi_b_valid),
-	.mmio_axi4_0_r_bits_data(simsoc_blackparrotrv64_mmio_axi_r_payload_data),
-	.mmio_axi4_0_r_bits_id(simsoc_blackparrotrv64_mmio_axi_r_payload_id),
-	.mmio_axi4_0_r_bits_last(simsoc_blackparrotrv64_mmio_axi_r_last),
-	.mmio_axi4_0_r_bits_resp(simsoc_blackparrotrv64_mmio_axi_r_payload_resp),
-	.mmio_axi4_0_r_valid(simsoc_blackparrotrv64_mmio_axi_r_valid),
-	.mmio_axi4_0_w_ready(simsoc_blackparrotrv64_mmio_axi_w_ready),
-	.reset((sys_rst | simsoc_blackparrotrv64_reset)),
-	.mem_axi4_0_ar_bits_addr(simsoc_blackparrotrv64_mem_axi_ar_payload_addr),
-	.mem_axi4_0_ar_bits_burst(simsoc_blackparrotrv64_mem_axi_ar_payload_burst),
-	.mem_axi4_0_ar_bits_cache(simsoc_blackparrotrv64_mem_axi_ar_payload_cache),
-	.mem_axi4_0_ar_bits_id(simsoc_blackparrotrv64_mem_axi_ar_payload_id),
-	.mem_axi4_0_ar_bits_len(simsoc_blackparrotrv64_mem_axi_ar_payload_len),
-	.mem_axi4_0_ar_bits_lock(simsoc_blackparrotrv64_mem_axi_ar_payload_lock),
-	.mem_axi4_0_ar_bits_prot(simsoc_blackparrotrv64_mem_axi_ar_payload_prot),
-	.mem_axi4_0_ar_bits_qos(simsoc_blackparrotrv64_mem_axi_ar_payload_qos),
-	.mem_axi4_0_ar_bits_size(simsoc_blackparrotrv64_mem_axi_ar_payload_size),
-	.mem_axi4_0_ar_valid(simsoc_blackparrotrv64_mem_axi_ar_valid),
-	.mem_axi4_0_aw_bits_addr(simsoc_blackparrotrv64_mem_axi_aw_payload_addr),
-	.mem_axi4_0_aw_bits_burst(simsoc_blackparrotrv64_mem_axi_aw_payload_burst),
-	.mem_axi4_0_aw_bits_cache(simsoc_blackparrotrv64_mem_axi_aw_payload_cache),
-	.mem_axi4_0_aw_bits_id(simsoc_blackparrotrv64_mem_axi_aw_payload_id),
-	.mem_axi4_0_aw_bits_len(simsoc_blackparrotrv64_mem_axi_aw_payload_len),
-	.mem_axi4_0_aw_bits_lock(simsoc_blackparrotrv64_mem_axi_aw_payload_lock),
-	.mem_axi4_0_aw_bits_prot(simsoc_blackparrotrv64_mem_axi_aw_payload_prot),
-	.mem_axi4_0_aw_bits_qos(simsoc_blackparrotrv64_mem_axi_aw_payload_qos),
-	.mem_axi4_0_aw_bits_size(simsoc_blackparrotrv64_mem_axi_aw_payload_size),
-	.mem_axi4_0_aw_valid(simsoc_blackparrotrv64_mem_axi_aw_valid),
-	.mem_axi4_0_b_ready(simsoc_blackparrotrv64_mem_axi_b_ready),
-	.mem_axi4_0_r_ready(simsoc_blackparrotrv64_mem_axi_r_ready),
-	.mem_axi4_0_w_bits_data(simsoc_blackparrotrv64_mem_axi_w_payload_data),
-	.mem_axi4_0_w_bits_last(simsoc_blackparrotrv64_mem_axi_w_last),
-	.mem_axi4_0_w_bits_strb(simsoc_blackparrotrv64_mem_axi_w_payload_strb),
-	.mem_axi4_0_w_valid(simsoc_blackparrotrv64_mem_axi_w_valid),
-	.mmio_axi4_0_ar_bits_addr(simsoc_blackparrotrv64_mmio_axi_ar_payload_addr),
-	.mmio_axi4_0_ar_bits_burst(simsoc_blackparrotrv64_mmio_axi_ar_payload_burst),
-	.mmio_axi4_0_ar_bits_cache(simsoc_blackparrotrv64_mmio_axi_ar_payload_cache),
-	.mmio_axi4_0_ar_bits_id(simsoc_blackparrotrv64_mmio_axi_ar_payload_id),
-	.mmio_axi4_0_ar_bits_len(simsoc_blackparrotrv64_mmio_axi_ar_payload_len),
-	.mmio_axi4_0_ar_bits_lock(simsoc_blackparrotrv64_mmio_axi_ar_payload_lock),
-	.mmio_axi4_0_ar_bits_prot(simsoc_blackparrotrv64_mmio_axi_ar_payload_prot),
-	.mmio_axi4_0_ar_bits_qos(simsoc_blackparrotrv64_mmio_axi_ar_payload_qos),
-	.mmio_axi4_0_ar_bits_size(simsoc_blackparrotrv64_mmio_axi_ar_payload_size),
-	.mmio_axi4_0_ar_valid(simsoc_blackparrotrv64_mmio_axi_ar_valid),
-	.mmio_axi4_0_aw_bits_addr(simsoc_blackparrotrv64_mmio_axi_aw_payload_addr),
-	.mmio_axi4_0_aw_bits_burst(simsoc_blackparrotrv64_mmio_axi_aw_payload_burst),
-	.mmio_axi4_0_aw_bits_cache(simsoc_blackparrotrv64_mmio_axi_aw_payload_cache),
-	.mmio_axi4_0_aw_bits_id(simsoc_blackparrotrv64_mmio_axi_aw_payload_id),
-	.mmio_axi4_0_aw_bits_len(simsoc_blackparrotrv64_mmio_axi_aw_payload_len),
-	.mmio_axi4_0_aw_bits_lock(simsoc_blackparrotrv64_mmio_axi_aw_payload_lock),
-	.mmio_axi4_0_aw_bits_prot(simsoc_blackparrotrv64_mmio_axi_aw_payload_prot),
-	.mmio_axi4_0_aw_bits_qos(simsoc_blackparrotrv64_mmio_axi_aw_payload_qos),
-	.mmio_axi4_0_aw_bits_size(simsoc_blackparrotrv64_mmio_axi_aw_payload_size),
-	.mmio_axi4_0_aw_valid(simsoc_blackparrotrv64_mmio_axi_aw_valid),
-	.mmio_axi4_0_b_ready(simsoc_blackparrotrv64_mmio_axi_b_ready),
-	.mmio_axi4_0_r_ready(simsoc_blackparrotrv64_mmio_axi_r_ready),
-	.mmio_axi4_0_w_bits_data(simsoc_blackparrotrv64_mmio_axi_w_payload_data),
-	.mmio_axi4_0_w_bits_last(simsoc_blackparrotrv64_mmio_axi_w_last),
-	.mmio_axi4_0_w_bits_strb(simsoc_blackparrotrv64_mmio_axi_w_payload_strb),
-	.mmio_axi4_0_w_valid(simsoc_blackparrotrv64_mmio_axi_w_valid)
-);
-
-reg [31:0] mem[0:8191];
-reg [31:0] memdat;
-always @(posedge sys_clk_1) begin
-	memdat <= mem[simsoc_rom_adr];
-end
-
-assign simsoc_rom_dat_r = memdat;
-
-initial begin
-	$readmemh("mem.init", mem);
-end
-
-reg [31:0] mem_1[0:1023];
-reg [9:0] memadr;
-always @(posedge sys_clk_1) begin
-	if (simsoc_sram_we[0])
-		mem_1[simsoc_sram_adr][7:0] <= simsoc_sram_dat_w[7:0];
-	if (simsoc_sram_we[1])
-		mem_1[simsoc_sram_adr][15:8] <= simsoc_sram_dat_w[15:8];
-	if (simsoc_sram_we[2])
-		mem_1[simsoc_sram_adr][23:16] <= simsoc_sram_dat_w[23:16];
-	if (simsoc_sram_we[3])
-		mem_1[simsoc_sram_adr][31:24] <= simsoc_sram_dat_w[31:24];
-	memadr <= simsoc_sram_adr;
-end
-
-assign simsoc_sram_dat_r = mem_1[memadr];
-
-initial begin
-	$readmemh("mem_1.init", mem_1);
-end
-
-reg [31:0] mem_2[0:67108863];
-reg [25:0] memadr_1;
-always @(posedge sys_clk_1) begin
-	if (simsoc_main_ram_we[0])
-		mem_2[simsoc_main_ram_adr][7:0] <= simsoc_main_ram_dat_w[7:0];
-	if (simsoc_main_ram_we[1])
-		mem_2[simsoc_main_ram_adr][15:8] <= simsoc_main_ram_dat_w[15:8];
-	if (simsoc_main_ram_we[2])
-		mem_2[simsoc_main_ram_adr][23:16] <= simsoc_main_ram_dat_w[23:16];
-	if (simsoc_main_ram_we[3])
-		mem_2[simsoc_main_ram_adr][31:24] <= simsoc_main_ram_dat_w[31:24];
-	memadr_1 <= simsoc_main_ram_adr;
-end
-
-assign simsoc_main_ram_dat_r = mem_2[memadr_1];
-
-initial begin
-	$readmemh("mem_2.init", mem_2);
-end
-
-reg [7:0] mem_3[0:36];
-reg [5:0] memadr_2;
-always @(posedge sys_clk_1) begin
-	memadr_2 <= csrbankarray_adr;
-end
-
-assign csrbankarray_dat_r = mem_3[memadr_2];
-
-initial begin
-	$readmemh("mem_3.init", mem_3);
-end
-
-reg [9:0] storage[0:15];
-reg [9:0] memdat_1;
-reg [9:0] memdat_2;
-always @(posedge sys_clk_1) begin
-	if (uart_tx_fifo_wrport_we)
-		storage[uart_tx_fifo_wrport_adr] <= uart_tx_fifo_wrport_dat_w;
-	memdat_1 <= storage[uart_tx_fifo_wrport_adr];
-end
-
-always @(posedge sys_clk_1) begin
-	if (uart_tx_fifo_rdport_re)
-		memdat_2 <= storage[uart_tx_fifo_rdport_adr];
-end
-
-assign uart_tx_fifo_wrport_dat_r = memdat_1;
-assign uart_tx_fifo_rdport_dat_r = memdat_2;
-
-reg [9:0] storage_1[0:15];
-reg [9:0] memdat_3;
-reg [9:0] memdat_4;
-always @(posedge sys_clk_1) begin
-	if (uart_rx_fifo_wrport_we)
-		storage_1[uart_rx_fifo_wrport_adr] <= uart_rx_fifo_wrport_dat_w;
-	memdat_3 <= storage_1[uart_rx_fifo_wrport_adr];
-end
-
-always @(posedge sys_clk_1) begin
-	if (uart_rx_fifo_rdport_re)
-		memdat_4 <= storage_1[uart_rx_fifo_rdport_adr];
-end
-
-assign uart_rx_fifo_wrport_dat_r = memdat_3;
-assign uart_rx_fifo_rdport_dat_r = memdat_4;
-
-endmodule
diff --git a/litex/tools/simout2/gateware/log b/litex/tools/simout2/gateware/log
deleted file mode 100644
index 58b143cd48..0000000000
--- a/litex/tools/simout2/gateware/log
+++ /dev/null
@@ -1,52 +0,0 @@
-make: Entering directory '/home/scanakci/Research_sado/litex/litex/litex/tools/simout2/gateware'
-$VV_FILE is [-f /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/bp_top/syn/flist.verilator]
-mkdir -p /home/scanakci/Research_sado/litex/litex/litex/tools/simout2/gateware/obj_dir
-make -C /home/scanakci/Research_sado/litex/litex/litex/build/sim/core/modules
-make[1]: Entering directory '/home/scanakci/Research_sado/litex/litex/litex/build/sim/core/modules'
-make -C ethernet
-make[2]: Entering directory '/home/scanakci/Research_sado/litex/litex/litex/build/sim/core/modules/ethernet'
-gcc -c -Wall -O3 -ggdb -fPIC -Werror -Itapcfg/src/include -I../.. -o /home/scanakci/Research_sado/litex/litex/litex/tools/simout2/gateware/obj_dir/ethernet.o ethernet.c
-gcc -Wall -O3 -ggdb -fPIC -Werror -Itapcfg/src/include -c -o /home/scanakci/Research_sado/litex/litex/litex/tools/simout2/gateware/obj_dir/tapcfg.o tapcfg/src/lib/tapcfg.c
-gcc -Wall -O3 -ggdb -fPIC -Werror -Itapcfg/src/include -c -o /home/scanakci/Research_sado/litex/litex/litex/tools/simout2/gateware/obj_dir/taplog.o tapcfg/src/lib/taplog.c
-gcc -levent -shared -fPIC -Wl,-soname,/home/scanakci/Research_sado/litex/litex/litex/tools/simout2/gateware/obj_dir/ethernet.so -o /home/scanakci/Research_sado/litex/litex/litex/tools/simout2/gateware/obj_dir/ethernet.so /home/scanakci/Research_sado/litex/litex/litex/tools/simout2/gateware/obj_dir/ethernet.o /home/scanakci/Research_sado/litex/litex/litex/tools/simout2/gateware/obj_dir/tapcfg.o /home/scanakci/Research_sado/litex/litex/litex/tools/simout2/gateware/obj_dir/taplog.o
-make[2]: Leaving directory '/home/scanakci/Research_sado/litex/litex/litex/build/sim/core/modules/ethernet'
-make -C serial2console
-make[2]: Entering directory '/home/scanakci/Research_sado/litex/litex/litex/build/sim/core/modules/serial2console'
-gcc -c -Wall -O3 -ggdb -fPIC -Werror -I../.. -o /home/scanakci/Research_sado/litex/litex/litex/tools/simout2/gateware/obj_dir/serial2console.o serial2console.c
-gcc -levent -shared -fPIC -Wl,-soname,/home/scanakci/Research_sado/litex/litex/litex/tools/simout2/gateware/obj_dir/serial2console.so -o /home/scanakci/Research_sado/litex/litex/litex/tools/simout2/gateware/obj_dir/serial2console.so /home/scanakci/Research_sado/litex/litex/litex/tools/simout2/gateware/obj_dir/serial2console.o
-rm /home/scanakci/Research_sado/litex/litex/litex/tools/simout2/gateware/obj_dir/serial2console.o
-make[2]: Leaving directory '/home/scanakci/Research_sado/litex/litex/litex/build/sim/core/modules/serial2console'
-make -C serial2tcp
-make[2]: Entering directory '/home/scanakci/Research_sado/litex/litex/litex/build/sim/core/modules/serial2tcp'
-gcc -c -Wall -O3 -ggdb -fPIC -Werror -I../.. -o /home/scanakci/Research_sado/litex/litex/litex/tools/simout2/gateware/obj_dir/serial2tcp.o serial2tcp.c
-gcc -levent -shared -fPIC -Wl,-soname,/home/scanakci/Research_sado/litex/litex/litex/tools/simout2/gateware/obj_dir/serial2tcp.so -o /home/scanakci/Research_sado/litex/litex/litex/tools/simout2/gateware/obj_dir/serial2tcp.so /home/scanakci/Research_sado/litex/litex/litex/tools/simout2/gateware/obj_dir/serial2tcp.o
-rm /home/scanakci/Research_sado/litex/litex/litex/tools/simout2/gateware/obj_dir/serial2tcp.o
-make[2]: Leaving directory '/home/scanakci/Research_sado/litex/litex/litex/build/sim/core/modules/serial2tcp'
-make -C clocker
-make[2]: Entering directory '/home/scanakci/Research_sado/litex/litex/litex/build/sim/core/modules/clocker'
-gcc -c -Wall -O3 -ggdb -fPIC -Werror -I../.. -o /home/scanakci/Research_sado/litex/litex/litex/tools/simout2/gateware/obj_dir/clocker.o clocker.c
-gcc -levent -shared -fPIC -Wl,-soname,/home/scanakci/Research_sado/litex/litex/litex/tools/simout2/gateware/obj_dir/clocker.so -o /home/scanakci/Research_sado/litex/litex/litex/tools/simout2/gateware/obj_dir/clocker.so /home/scanakci/Research_sado/litex/litex/litex/tools/simout2/gateware/obj_dir/clocker.o
-rm /home/scanakci/Research_sado/litex/litex/litex/tools/simout2/gateware/obj_dir/clocker.o
-make[2]: Leaving directory '/home/scanakci/Research_sado/litex/litex/litex/build/sim/core/modules/clocker'
-make[1]: Leaving directory '/home/scanakci/Research_sado/litex/litex/litex/build/sim/core/modules'
-gcc -c -Wall -O3 -ggdb  -o /home/scanakci/Research_sado/litex/litex/litex/tools/simout2/gateware/obj_dir/modules.o /home/scanakci/Research_sado/litex/litex/litex/build/sim/core/modules.c
-gcc -c -Wall -O3 -ggdb  -o /home/scanakci/Research_sado/litex/litex/litex/tools/simout2/gateware/obj_dir/pads.o /home/scanakci/Research_sado/litex/litex/litex/build/sim/core/pads.c
-gcc -c -Wall -O3 -ggdb  -o /home/scanakci/Research_sado/litex/litex/litex/tools/simout2/gateware/obj_dir/sim.o /home/scanakci/Research_sado/litex/litex/litex/build/sim/core/sim.c
-gcc -c -Wall -O3 -ggdb  -o /home/scanakci/Research_sado/litex/litex/litex/tools/simout2/gateware/obj_dir/libdylib.o /home/scanakci/Research_sado/litex/litex/litex/build/sim/core/libdylib.c
-gcc -c -Wall -O3 -ggdb  -o /home/scanakci/Research_sado/litex/litex/litex/tools/simout2/gateware/obj_dir/parse.o /home/scanakci/Research_sado/litex/litex/litex/build/sim/core/parse.c
-verilator -Wno-fatal -O3 --cc dut.v --top-module dut --exe \
-	-DPRINTF_COND=0 \
-	dut_init.cpp /home/scanakci/Research_sado/litex/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \
-	--top-module dut \
-	 \
-	-CFLAGS "-Wall -O3 -ggdb  -I/home/scanakci/Research_sado/litex/litex/litex/build/sim/core" \
-	-LDFLAGS "-lpthread -ljson-c -lm -lstdc++ -ldl -levent" \
-	--trace \
-	 \
-	--unroll-count 256 \
-	-I/home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard  \
-	-Wno-BLKANDNBLK \
-	-Wno-WIDTH \
-	/home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/bp_top/syn/flist.verilator
-/home/scanakci/Research_sado/litex/litex/litex/build/sim/core/Makefile:31: recipe for target 'sim' failed
-make: Leaving directory '/home/scanakci/Research_sado/litex/litex/litex/tools/simout2/gateware'
diff --git a/litex/tools/simout2/gateware/mem.init b/litex/tools/simout2/gateware/mem.init
deleted file mode 100644
index 04566302cd..0000000000
--- a/litex/tools/simout2/gateware/mem.init
+++ /dev/null
@@ -1,3011 +0,0 @@
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-1bb997f4
diff --git a/litex/tools/simout2/gateware/mem_3.init b/litex/tools/simout2/gateware/mem_3.init
deleted file mode 100644
index 00d40a63f0..0000000000
--- a/litex/tools/simout2/gateware/mem_3.init
+++ /dev/null
@@ -1,37 +0,0 @@
-4c
-69
-74
-65
-58
-20
-53
-69
-6d
-75
-6c
-61
-74
-69
-6f
-6e
-20
-32
-30
-31
-39
-2d
-31
-30
-2d
-31
-30
-20
-31
-37
-3a
-35
-38
-3a
-31
-39
-0
diff --git a/litex/tools/simout2/software/bios/bios.bin b/litex/tools/simout2/software/bios/bios.bin
deleted file mode 100644
index 57fefb3201..0000000000
Binary files a/litex/tools/simout2/software/bios/bios.bin and /dev/null differ
diff --git a/litex/tools/simout2/software/bios/bios.elf b/litex/tools/simout2/software/bios/bios.elf
deleted file mode 100644
index 52fc3cec1c..0000000000
Binary files a/litex/tools/simout2/software/bios/bios.elf and /dev/null differ
diff --git a/litex/tools/simout2/software/bios/boot.o b/litex/tools/simout2/software/bios/boot.o
deleted file mode 100644
index f8b8cefbb5..0000000000
Binary files a/litex/tools/simout2/software/bios/boot.o and /dev/null differ
diff --git a/litex/tools/simout2/software/bios/isr.o b/litex/tools/simout2/software/bios/isr.o
deleted file mode 100644
index 0265a49225..0000000000
Binary files a/litex/tools/simout2/software/bios/isr.o and /dev/null differ
diff --git a/litex/tools/simout2/software/bios/main.o b/litex/tools/simout2/software/bios/main.o
deleted file mode 100644
index f767821b7b..0000000000
Binary files a/litex/tools/simout2/software/bios/main.o and /dev/null differ
diff --git a/litex/tools/simout2/software/bios/sdram.o b/litex/tools/simout2/software/bios/sdram.o
deleted file mode 100644
index 0cb40931ce..0000000000
Binary files a/litex/tools/simout2/software/bios/sdram.o and /dev/null differ
diff --git a/litex/tools/simout2/software/include/generated/csr.h b/litex/tools/simout2/software/include/generated/csr.h
deleted file mode 100644
index 499b467bfd..0000000000
--- a/litex/tools/simout2/software/include/generated/csr.h
+++ /dev/null
@@ -1,252 +0,0 @@
-//--------------------------------------------------------------------------------
-// Auto-generated by Migen (57a7311) & LiteX (2be3450) on 2019-10-10 17:58:20
-//--------------------------------------------------------------------------------
-#ifndef __GENERATED_CSR_H
-#define __GENERATED_CSR_H
-#include <stdint.h>
-#ifdef CSR_ACCESSORS_DEFINED
-extern void csr_writeb(uint8_t value, unsigned long addr);
-extern uint8_t csr_readb(unsigned long addr);
-extern void csr_writew(uint16_t value, unsigned long addr);
-extern uint16_t csr_readw(unsigned long addr);
-extern void csr_writel(uint32_t value, unsigned long addr);
-extern uint32_t csr_readl(unsigned long addr);
-#else /* ! CSR_ACCESSORS_DEFINED */
-#include <hw/common.h>
-#endif /* ! CSR_ACCESSORS_DEFINED */
-
-/* ctrl */
-#define CSR_CTRL_BASE 0x82000000L
-#define CSR_CTRL_RESET_ADDR 0x82000000L
-#define CSR_CTRL_RESET_SIZE 1
-static inline unsigned char ctrl_reset_read(void) {
-	unsigned char r = csr_readl(0x82000000L);
-	return r;
-}
-static inline void ctrl_reset_write(unsigned char value) {
-	csr_writel(value, 0x82000000L);
-}
-#define CSR_CTRL_SCRATCH_ADDR 0x82000004L
-#define CSR_CTRL_SCRATCH_SIZE 4
-static inline unsigned int ctrl_scratch_read(void) {
-	unsigned int r = csr_readl(0x82000004L);
-	r <<= 8;
-	r |= csr_readl(0x82000008L);
-	r <<= 8;
-	r |= csr_readl(0x8200000cL);
-	r <<= 8;
-	r |= csr_readl(0x82000010L);
-	return r;
-}
-static inline void ctrl_scratch_write(unsigned int value) {
-	csr_writel(value >> 24, 0x82000004L);
-	csr_writel(value >> 16, 0x82000008L);
-	csr_writel(value >> 8, 0x8200000cL);
-	csr_writel(value, 0x82000010L);
-}
-#define CSR_CTRL_BUS_ERRORS_ADDR 0x82000014L
-#define CSR_CTRL_BUS_ERRORS_SIZE 4
-static inline unsigned int ctrl_bus_errors_read(void) {
-	unsigned int r = csr_readl(0x82000014L);
-	r <<= 8;
-	r |= csr_readl(0x82000018L);
-	r <<= 8;
-	r |= csr_readl(0x8200001cL);
-	r <<= 8;
-	r |= csr_readl(0x82000020L);
-	return r;
-}
-
-/* timer0 */
-#define CSR_TIMER0_BASE 0x82001800L
-#define CSR_TIMER0_LOAD_ADDR 0x82001800L
-#define CSR_TIMER0_LOAD_SIZE 4
-static inline unsigned int timer0_load_read(void) {
-	unsigned int r = csr_readl(0x82001800L);
-	r <<= 8;
-	r |= csr_readl(0x82001804L);
-	r <<= 8;
-	r |= csr_readl(0x82001808L);
-	r <<= 8;
-	r |= csr_readl(0x8200180cL);
-	return r;
-}
-static inline void timer0_load_write(unsigned int value) {
-	csr_writel(value >> 24, 0x82001800L);
-	csr_writel(value >> 16, 0x82001804L);
-	csr_writel(value >> 8, 0x82001808L);
-	csr_writel(value, 0x8200180cL);
-}
-#define CSR_TIMER0_RELOAD_ADDR 0x82001810L
-#define CSR_TIMER0_RELOAD_SIZE 4
-static inline unsigned int timer0_reload_read(void) {
-	unsigned int r = csr_readl(0x82001810L);
-	r <<= 8;
-	r |= csr_readl(0x82001814L);
-	r <<= 8;
-	r |= csr_readl(0x82001818L);
-	r <<= 8;
-	r |= csr_readl(0x8200181cL);
-	return r;
-}
-static inline void timer0_reload_write(unsigned int value) {
-	csr_writel(value >> 24, 0x82001810L);
-	csr_writel(value >> 16, 0x82001814L);
-	csr_writel(value >> 8, 0x82001818L);
-	csr_writel(value, 0x8200181cL);
-}
-#define CSR_TIMER0_EN_ADDR 0x82001820L
-#define CSR_TIMER0_EN_SIZE 1
-static inline unsigned char timer0_en_read(void) {
-	unsigned char r = csr_readl(0x82001820L);
-	return r;
-}
-static inline void timer0_en_write(unsigned char value) {
-	csr_writel(value, 0x82001820L);
-}
-#define CSR_TIMER0_UPDATE_VALUE_ADDR 0x82001824L
-#define CSR_TIMER0_UPDATE_VALUE_SIZE 1
-static inline unsigned char timer0_update_value_read(void) {
-	unsigned char r = csr_readl(0x82001824L);
-	return r;
-}
-static inline void timer0_update_value_write(unsigned char value) {
-	csr_writel(value, 0x82001824L);
-}
-#define CSR_TIMER0_VALUE_ADDR 0x82001828L
-#define CSR_TIMER0_VALUE_SIZE 4
-static inline unsigned int timer0_value_read(void) {
-	unsigned int r = csr_readl(0x82001828L);
-	r <<= 8;
-	r |= csr_readl(0x8200182cL);
-	r <<= 8;
-	r |= csr_readl(0x82001830L);
-	r <<= 8;
-	r |= csr_readl(0x82001834L);
-	return r;
-}
-#define CSR_TIMER0_EV_STATUS_ADDR 0x82001838L
-#define CSR_TIMER0_EV_STATUS_SIZE 1
-static inline unsigned char timer0_ev_status_read(void) {
-	unsigned char r = csr_readl(0x82001838L);
-	return r;
-}
-static inline void timer0_ev_status_write(unsigned char value) {
-	csr_writel(value, 0x82001838L);
-}
-#define CSR_TIMER0_EV_PENDING_ADDR 0x8200183cL
-#define CSR_TIMER0_EV_PENDING_SIZE 1
-static inline unsigned char timer0_ev_pending_read(void) {
-	unsigned char r = csr_readl(0x8200183cL);
-	return r;
-}
-static inline void timer0_ev_pending_write(unsigned char value) {
-	csr_writel(value, 0x8200183cL);
-}
-#define CSR_TIMER0_EV_ENABLE_ADDR 0x82001840L
-#define CSR_TIMER0_EV_ENABLE_SIZE 1
-static inline unsigned char timer0_ev_enable_read(void) {
-	unsigned char r = csr_readl(0x82001840L);
-	return r;
-}
-static inline void timer0_ev_enable_write(unsigned char value) {
-	csr_writel(value, 0x82001840L);
-}
-
-/* uart */
-#define CSR_UART_BASE 0x82002000L
-#define CSR_UART_RXTX_ADDR 0x82002000L
-#define CSR_UART_RXTX_SIZE 1
-static inline unsigned char uart_rxtx_read(void) {
-	unsigned char r = csr_readl(0x82002000L);
-	return r;
-}
-static inline void uart_rxtx_write(unsigned char value) {
-	csr_writel(value, 0x82002000L);
-}
-#define CSR_UART_TXFULL_ADDR 0x82002004L
-#define CSR_UART_TXFULL_SIZE 1
-static inline unsigned char uart_txfull_read(void) {
-	unsigned char r = csr_readl(0x82002004L);
-	return r;
-}
-#define CSR_UART_RXEMPTY_ADDR 0x82002008L
-#define CSR_UART_RXEMPTY_SIZE 1
-static inline unsigned char uart_rxempty_read(void) {
-	unsigned char r = csr_readl(0x82002008L);
-	return r;
-}
-#define CSR_UART_EV_STATUS_ADDR 0x8200200cL
-#define CSR_UART_EV_STATUS_SIZE 1
-static inline unsigned char uart_ev_status_read(void) {
-	unsigned char r = csr_readl(0x8200200cL);
-	return r;
-}
-static inline void uart_ev_status_write(unsigned char value) {
-	csr_writel(value, 0x8200200cL);
-}
-#define CSR_UART_EV_PENDING_ADDR 0x82002010L
-#define CSR_UART_EV_PENDING_SIZE 1
-static inline unsigned char uart_ev_pending_read(void) {
-	unsigned char r = csr_readl(0x82002010L);
-	return r;
-}
-static inline void uart_ev_pending_write(unsigned char value) {
-	csr_writel(value, 0x82002010L);
-}
-#define CSR_UART_EV_ENABLE_ADDR 0x82002014L
-#define CSR_UART_EV_ENABLE_SIZE 1
-static inline unsigned char uart_ev_enable_read(void) {
-	unsigned char r = csr_readl(0x82002014L);
-	return r;
-}
-static inline void uart_ev_enable_write(unsigned char value) {
-	csr_writel(value, 0x82002014L);
-}
-
-/* identifier_mem */
-#define CSR_IDENTIFIER_MEM_BASE 0x82001000L
-
-/* constants */
-#define TIMER0_INTERRUPT 0
-static inline int timer0_interrupt_read(void) {
-	return 0;
-}
-#define UART_INTERRUPT 1
-static inline int uart_interrupt_read(void) {
-	return 1;
-}
-#define CONFIG_CLOCK_FREQUENCY 1000000
-static inline int config_clock_frequency_read(void) {
-	return 1000000;
-}
-#define CONFIG_CPU_RESET_ADDR 0
-static inline int config_cpu_reset_addr_read(void) {
-	return 0;
-}
-#define CONFIG_CPU_TYPE "BLACKPARROT"
-static inline const char * config_cpu_type_read(void) {
-	return "BLACKPARROT";
-}
-#define CONFIG_CPU_TYPE_BLACKPARROT 1
-static inline int config_cpu_type_blackparrot_read(void) {
-	return 1;
-}
-#define CONFIG_CPU_VARIANT "STANDARD"
-static inline const char * config_cpu_variant_read(void) {
-	return "STANDARD";
-}
-#define CONFIG_CPU_VARIANT_STANDARD 1
-static inline int config_cpu_variant_standard_read(void) {
-	return 1;
-}
-#define CONFIG_CSR_ALIGNMENT 32
-static inline int config_csr_alignment_read(void) {
-	return 32;
-}
-#define CONFIG_CSR_DATA_WIDTH 8
-static inline int config_csr_data_width_read(void) {
-	return 8;
-}
-
-#endif
diff --git a/litex/tools/simout2/software/include/generated/git.h b/litex/tools/simout2/software/include/generated/git.h
deleted file mode 100644
index 6f4b99cd9e..0000000000
--- a/litex/tools/simout2/software/include/generated/git.h
+++ /dev/null
@@ -1,9 +0,0 @@
-//--------------------------------------------------------------------------------
-// Auto-generated by Migen (57a7311) & LiteX (2be3450) on 2019-10-10 17:58:20
-//--------------------------------------------------------------------------------
-#ifndef __GENERATED_GIT_H
-#define __GENERATED_GIT_H
-
-#define MIGEN_GIT_SHA1 "57a7311"
-#define LITEX_GIT_SHA1 "2be3450"
-#endif
diff --git a/litex/tools/simout2/software/include/generated/mem.h b/litex/tools/simout2/software/include/generated/mem.h
deleted file mode 100644
index 3b66ba9dbb..0000000000
--- a/litex/tools/simout2/software/include/generated/mem.h
+++ /dev/null
@@ -1,21 +0,0 @@
-//--------------------------------------------------------------------------------
-// Auto-generated by Migen (57a7311) & LiteX (2be3450) on 2019-10-10 17:58:20
-//--------------------------------------------------------------------------------
-#ifndef __GENERATED_MEM_H
-#define __GENERATED_MEM_H
-
-#define ROM_BASE 0x00000000L
-#define ROM_SIZE 0x00008000
-
-#define SRAM_BASE 0x01000000L
-#define SRAM_SIZE 0x00001000
-
-#define MAIN_RAM_BASE 0x40000000L
-#define MAIN_RAM_SIZE 0x10000000
-
-#define CSR_BASE 0x02000000L
-#define CSR_SIZE 0x01000000
-
-#define SHADOW_BASE 0x80000000L
-
-#endif
diff --git a/litex/tools/simout2/software/include/generated/variables.mak b/litex/tools/simout2/software/include/generated/variables.mak
deleted file mode 100644
index a91644ec3f..0000000000
--- a/litex/tools/simout2/software/include/generated/variables.mak
+++ /dev/null
@@ -1,15 +0,0 @@
-TRIPLE=riscv64-unknown-elf
-CPU=blackparrot
-CPUFLAGS=-mno-save-restore -march=rv64imac   -mabi=lp64 -D__blackparrot__ 
-CPUENDIANNESS=little
-CLANG=0
-LITEX=1
-COPY_TO_MAIN_RAM=1
-EXECUTE_IN_PLACE=0
-SOC_DIRECTORY=/home/scanakci/Research_sado/litex/litex/litex/soc
-export BUILDINC_DIRECTORY
-BUILDINC_DIRECTORY=/home/scanakci/Research_sado/litex/litex/litex/tools/simout2/software/include
-LIBCOMPILER_RT_DIRECTORY=/home/scanakci/Research_sado/litex/litex/litex/soc/software/libcompiler_rt
-LIBBASE_DIRECTORY=/home/scanakci/Research_sado/litex/litex/litex/soc/software/libbase
-LIBNET_DIRECTORY=/home/scanakci/Research_sado/litex/litex/litex/soc/software/libnet
-BIOS_DIRECTORY=/home/scanakci/Research_sado/litex/litex/litex/soc/software/bios
diff --git a/litex/tools/simout2/software/libbase/exception.o b/litex/tools/simout2/software/libbase/exception.o
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