MOS 6502 Decoder dump from HDL model

[ogamespec]

Wrote a small HDL test bench that goes through all the decoder inputs and outputs the values of all 130 outputs for each combination of inputs.

The lower six bits of input vector represent the Tx. The remaining high bits are IR.

The numbering of the outputs corresponds: https://github.com/emu-russia/breaks/blob/master/BreakingNESWiki_DeepL/6502/decoder.md

Note the special 129th output ("pp") (it occurs twice in the real processor), and that the decoder does not use /PRDY and IR0, which in the real processor are hardcoded directly into the PLA matrix.

It can be used to verify your 6502 designs.

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This discussion was created from the release MOS 6502 Decoder dump from HDL model.