APU HDL Release 1.0

[ogamespec]

• Topological masks were reconstructed from the chip photo
• Transistor circuits were reconstructed from topological masks
• Transistor circuits were converted into logic circuits (gates)
• Logic circuits were formalized on Verilog

Also inside the archive is the Test Bench for Icarus Verilog, which was used for verification.

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This discussion was created from the release APU HDL Release 1.0.