[proposal] reduce stacking by storing PC to link register, instead of HANDLER_RETURN pattern

[jnk0le]

This proposal aims to reduce number of stacked registers or have another caller saved register defined in EABI.

Instead of stacking PC and generating HANDLER_RETURN pattern which is inserted into the link register, we can just store PC into the link register with the lowest bit set to indicate an unstacking operation when returning from handler function.

The control bits defined in HANDLER_RETURN pattern will have to be moved into status csr.

The JALR to address with lsb set, will now cause:

• handler return procedure if hart is currently running in handler mode.
• Instruction address misaligned exception otherwise. Or at least forbid any use of function pointers with "auxiliary information" bit set in EABI compliant software, except the handler return case.
  (lsb in immediate field can be ignored since we care only about pointers).

Of course this proposal requires a slight redefinition of JALR instruction which is currently defined to ignore the lowest bit of calculated address. I'm not certainly sure if such kind of ISA changes in embedded profile are even possible, but jumps to unaligned addresses are sign that something went wrong with pointer arithmetic, it is rather instruction side-effect change and prior software anyway will not be compatible with EABI calling conventions, so I thought that it might be worth for further discussion.

[ilg-ul]

Thank you, I added a note in the Exceptions and Interrupts page.

[jnk0le]

As to reduce profanation of the base ISA, we can make JALR modifications exclusive to link register only. So the EABI will mandate that all function returns must be handled through link register.

And I would recommend to reserve 'closed' state of public issues to those that were accepter/rejected/fixed etc. So it is easier to find pending proposals and leave feedback on them.

[ilg-ul]

I reopened this issue if you think it is useful.

As for using the alignment reserved bits vs a separate HANDLER_RETURN pattern, I think that the latter is more versatile, since it allows more bits to be used for multiple modes (as in Cortex-M case).

Also I think that making modifications to the base ISA might be problematic with regards to passing compliance tests.