From c1a6896ed799efa91f9cc7ff10f5f5d6b7981de3 Mon Sep 17 00:00:00 2001 From: slavek-kucera <53339291+slavek-kucera@users.noreply.github.com> Date: Fri, 16 Jul 2021 19:19:28 +0200 Subject: [PATCH] fix: Various small fixes (#149) docs: Remove references to proc_conf refactor: Remove references to proc_conf fix: Inline macro not available when the matching instruction was deleted by OPSYN fix: Vector register 16-31 not recognized. * fixes eclipse/che-che4z-lsp-for-hlasm#143, fixes eclipse/che-che4z-lsp-for-hlasm#142 --- clients/vscode-hlasmplugin/README.md | 4 +- .../src/checking/asm_instr_check.cpp | 6 +- .../src/checking/asm_instr_class.cpp | 2 + parser_library/src/config/CMakeLists.txt | 4 +- .../config/{proc_conf.cpp => proc_grps.cpp} | 6 +- .../src/config/{proc_conf.h => proc_grps.h} | 12 +- parser_library/src/context/hlasm_context.cpp | 33 +- parser_library/src/context/instruction.cpp | 491 +++++++----------- parser_library/src/context/instruction.h | 6 +- .../instruction_sets/asm_processor.cpp | 12 +- .../src/workspaces/processor_group.cpp | 2 +- parser_library/src/workspaces/workspace.cpp | 4 +- parser_library/src/workspaces/workspace.h | 4 +- .../test/checking/mach_instr_diag_test.cpp | 17 +- parser_library/test/config/CMakeLists.txt | 2 +- ...{proc_conf_test.cpp => proc_grps_test.cpp} | 54 +- parser_library/test/processing/opsyn_test.cpp | 38 ++ 17 files changed, 331 insertions(+), 366 deletions(-) rename parser_library/src/config/{proc_conf.cpp => proc_grps.cpp} (96%) rename parser_library/src/config/{proc_conf.h => proc_grps.h} (88%) rename parser_library/test/config/{proc_conf_test.cpp => proc_grps_test.cpp} (84%) diff --git a/clients/vscode-hlasmplugin/README.md b/clients/vscode-hlasmplugin/README.md index 19c27e1ae..e518af1a4 100644 --- a/clients/vscode-hlasmplugin/README.md +++ b/clients/vscode-hlasmplugin/README.md @@ -171,12 +171,12 @@ In this example, GROUP1 is used for all open code programs. The `alwaysRecognize` option in `pgm_conf.json` has been deprecated in favour of the standard VSCode user and workspace level setting `file.associations`. -`proc_conf.json` can include an optional parameter `macro_extensions` which contains a list of extensions that are to be used to identify files with macro definitions. +`proc_grps.json` can include an optional parameter `macro_extensions` which contains a list of extensions that are to be used to identify files with macro definitions. The options can be specified both at the top level of the file, providing the default list for all libraries in all process groups, and at the level of individual library definitions, overriding the default from the top level. For example, with the extension `.hlasm`, a user can add the macro `MAC` to his source code even if it is in a file called `MAC.hlasm`. -The following example of `proc_conf.json` specifies that files with the extension `.hlasm` are recognized as macros, with the exception of macros in the `C:/external/project/macs` directory, where they need to have the extension `.mac`. +The following example of `proc_grps.json` specifies that files with the extension `.hlasm` are recognized as macros, with the exception of macros in the `C:/external/project/macs` directory, where they need to have the extension `.mac`. ``` { diff --git a/parser_library/src/checking/asm_instr_check.cpp b/parser_library/src/checking/asm_instr_check.cpp index 8ce0b8175..876f8599d 100644 --- a/parser_library/src/checking/asm_instr_check.cpp +++ b/parser_library/src/checking/asm_instr_check.cpp @@ -498,6 +498,8 @@ bool opsyn::check(const std::vector& to_check, { if (!operands_size_corresponding(to_check, stmt_range, add_diagnostic)) return false; + if (has_one_comma(to_check)) + return true; if (to_check.size() == 1) { if (is_operand_complex(to_check[0])) @@ -583,6 +585,8 @@ bool iseq::check(const std::vector& to_check, { if (to_check.empty()) return true; + if (has_one_comma(to_check)) + return true; if (to_check.size() == 2) { auto first = get_simple_operand(to_check[0]); @@ -1019,7 +1023,7 @@ bool expression_instruction::check(const std::vector& to_che if (to_check.empty()) return true; // an if for the specific "SPACE , " case which should return true - if (to_check.size() == 2 && is_operand_empty(to_check[0]) && is_operand_empty(to_check[1])) + if (has_one_comma(to_check)) return true; if (!operands_size_corresponding(to_check, stmt_range, add_diagnostic)) return false; diff --git a/parser_library/src/checking/asm_instr_class.cpp b/parser_library/src/checking/asm_instr_class.cpp index 675f35ff5..61597dd2b 100644 --- a/parser_library/src/checking/asm_instr_class.cpp +++ b/parser_library/src/checking/asm_instr_class.cpp @@ -31,6 +31,8 @@ bool assembler_instruction::operands_size_corresponding(const std::vector= min_operands && ((int)to_check.size() <= max_operands || max_operands == -1)) return true; + if (min_operands == 0 && has_one_comma(to_check)) + return true; // handles classic " instr , comment" pattern if (max_operands == -1) add_diagnostic(diagnostic_op::error_A010_minimum(name_of_instruction, min_operands, stmt_range)); else if (min_operands == max_operands) diff --git a/parser_library/src/config/CMakeLists.txt b/parser_library/src/config/CMakeLists.txt index 2c12b19b6..36ecf6ef6 100644 --- a/parser_library/src/config/CMakeLists.txt +++ b/parser_library/src/config/CMakeLists.txt @@ -13,6 +13,6 @@ target_sources(parser_library PRIVATE pgm_conf.cpp pgm_conf.h - proc_conf.cpp - proc_conf.h + proc_grps.cpp + proc_grps.h ) diff --git a/parser_library/src/config/proc_conf.cpp b/parser_library/src/config/proc_grps.cpp similarity index 96% rename from parser_library/src/config/proc_conf.cpp rename to parser_library/src/config/proc_grps.cpp index 986017f94..4d571c422 100644 --- a/parser_library/src/config/proc_conf.cpp +++ b/parser_library/src/config/proc_grps.cpp @@ -12,7 +12,7 @@ * Broadcom, Inc. - initial API and implementation */ -#include "proc_conf.h" +#include "proc_grps.h" #include "nlohmann/json.hpp" @@ -106,13 +106,13 @@ void from_json(const nlohmann::json& j, processor_group& p) } } -void to_json(nlohmann::json& j, const proc_conf& p) +void to_json(nlohmann::json& j, const proc_grps& p) { j = nlohmann::json { { "pgroups", p.pgroups } }; if (auto m = nlohmann::json(p.macro_extensions); !m.empty()) j["macro_extensions"] = std::move(m); } -void from_json(const nlohmann::json& j, proc_conf& p) +void from_json(const nlohmann::json& j, proc_grps& p) { j.at("pgroups").get_to(p.pgroups); if (auto it = j.find("macro_extensions"); it != j.end()) diff --git a/parser_library/src/config/proc_conf.h b/parser_library/src/config/proc_grps.h similarity index 88% rename from parser_library/src/config/proc_conf.h rename to parser_library/src/config/proc_grps.h index 1ef4d8ea8..8f5bd8287 100644 --- a/parser_library/src/config/proc_conf.h +++ b/parser_library/src/config/proc_grps.h @@ -12,8 +12,8 @@ * Broadcom, Inc. - initial API and implementation */ -#ifndef HLASMPARSER_PARSERLIBRARY_CONFIG_PROC_CONF_H -#define HLASMPARSER_PARSERLIBRARY_CONFIG_PROC_CONF_H +#ifndef HLASMPARSER_PARSERLIBRARY_CONFIG_PROC_GRPS_H +#define HLASMPARSER_PARSERLIBRARY_CONFIG_PROC_GRPS_H #include #include @@ -68,14 +68,14 @@ struct processor_group void to_json(nlohmann::json& j, const processor_group& p); void from_json(const nlohmann::json& j, processor_group& p); -struct proc_conf +struct proc_grps { std::vector pgroups; std::vector macro_extensions; }; -void to_json(nlohmann::json& j, const proc_conf& p); -void from_json(const nlohmann::json& j, proc_conf& p); +void to_json(nlohmann::json& j, const proc_grps& p); +void from_json(const nlohmann::json& j, proc_grps& p); } // namespace hlasm_plugin::parser_library::config -#endif // HLASMPARSER_PARSERLIBRARY_CONFIG_PROC_CONF_H +#endif // HLASMPARSER_PARSERLIBRARY_CONFIG_PROC_GRPS_H diff --git a/parser_library/src/context/hlasm_context.cpp b/parser_library/src/context/hlasm_context.cpp index a7b957c7e..a515027e7 100644 --- a/parser_library/src/context/hlasm_context.cpp +++ b/parser_library/src/context/hlasm_context.cpp @@ -676,20 +676,25 @@ macro_def_ptr hlasm_context::add_macro(id_index name, location definition_location, std::unordered_set used_copy_members) { - return macros_ - .insert_or_assign(name, - std::make_shared(name, - label_param_name, - std::move(params), - std::move(definition), - std::move(copy_nests), - std::move(labels), - std::move(definition_location), - std::move(used_copy_members))) - .first->second; -} - -void hlasm_context::add_macro(macro_def_ptr macro) { macros_[macro->id] = std::move(macro); }; + auto result = std::make_shared(name, + label_param_name, + std::move(params), + std::move(definition), + std::move(copy_nests), + std::move(labels), + std::move(definition_location), + std::move(used_copy_members)); + add_macro(result); + return result; +} + +void hlasm_context::add_macro(macro_def_ptr macro) +{ + const auto& m = macros_[macro->id] = std::move(macro); + // associate mnemonic if previously deleted by OPSYN + if (auto m_op = opcode_mnemo_.find(m->id); m_op != opcode_mnemo_.end() && !m_op->second) + m_op->second = opcode_t { m->id, m }; +}; const hlasm_context::macro_storage& hlasm_context::macros() const { return macros_; } diff --git a/parser_library/src/context/instruction.cpp b/parser_library/src/context/instruction.cpp index 61a9b8c1b..88b66713f 100644 --- a/parser_library/src/context/instruction.cpp +++ b/parser_library/src/context/instruction.cpp @@ -262,16 +262,7 @@ hlasm_plugin::parser_library::context::instruction::get_machine_instructions() add_machine_instr(result, "AGH", mach_format::RXY_a, { reg_4_U, dxb_20_4x4_S }, 512); add_machine_instr(result, "AHI", mach_format::RI_a, { reg_4_U, imm_16_S }, 512); add_machine_instr(result, "AGHI", mach_format::RI_a, { reg_4_U, imm_16_S }, 513); - add_machine_instr(result, - "AHHHR", - mach_format::RRF_a, - { - reg_4_U, - reg_4_U, - reg_4_U, - }, - - 513); + add_machine_instr(result, "AHHHR", mach_format::RRF_a, { reg_4_U, reg_4_U, reg_4_U }, 513); add_machine_instr(result, "AHHLR", mach_format::RRF_a, { reg_4_U, reg_4_U, reg_4_U }, 513); add_machine_instr(result, "AIH", mach_format::RIL_a, { reg_4_U, imm_32_S }, 513); add_machine_instr(result, "ALR", mach_format::RR, { reg_4_U, reg_4_U }, 514); @@ -327,27 +318,9 @@ hlasm_plugin::parser_library::context::instruction::get_machine_instructions() add_machine_instr(result, "BCT", mach_format::RX_a, { reg_4_U, dxb_12_4x4_U }, 525); add_machine_instr(result, "BCTG", mach_format::RXY_a, { reg_4_U, dxb_20_4x4_S }, 525); add_machine_instr(result, "BXH", mach_format::RS_a, { reg_4_U, reg_4_U, db_12_4_U }, 526); - add_machine_instr(result, - "BXHG", - mach_format::RSY_a, - { - reg_4_U, - reg_4_U, - db_20_4_S, - }, - - 526); + add_machine_instr(result, "BXHG", mach_format::RSY_a, { reg_4_U, reg_4_U, db_20_4_S }, 526); add_machine_instr(result, "BXLE", mach_format::RS_a, { reg_4_U, reg_4_U, db_12_4_U }, 526); - add_machine_instr(result, - "BXLEG", - mach_format::RSY_a, - { - reg_4_U, - reg_4_U, - db_20_4_S, - }, - - 526); + add_machine_instr(result, "BXLEG", mach_format::RSY_a, { reg_4_U, reg_4_U, db_20_4_S }, 526); add_machine_instr(result, "BPP", mach_format::SMI, { mask_4_U, rel_addr_imm_16_S, db_12_4_U }, 527); add_machine_instr(result, "BPRP", mach_format::MII, { mask_4_U, rel_addr_imm_12_S, rel_addr_imm_24_S }, 527); add_machine_instr(result, "BRAS", mach_format::RI_b, { reg_4_U, rel_addr_imm_16_S }, 530); @@ -384,28 +357,8 @@ hlasm_plugin::parser_library::context::instruction::get_machine_instructions() add_machine_instr(result, "CGRB", mach_format::RRS, { reg_4_U, reg_4_U, mask_4_U, db_12_4_U }, 619); add_machine_instr(result, "CRJ", mach_format::RIE_b, { reg_4_U, reg_4_U, mask_4_U, rel_addr_imm_16_S }, 619); add_machine_instr(result, "CGRJ", mach_format::RIE_b, { reg_4_U, reg_4_U, mask_4_U, rel_addr_imm_16_S }, 620); - add_machine_instr(result, - "CIB", - mach_format::RIS, - { - reg_4_U, - imm_8_S, - mask_4_U, - db_12_4_U, - }, - - 620); - add_machine_instr(result, - "CGIB", - mach_format::RIS, - { - reg_4_U, - imm_8_S, - mask_4_U, - db_12_4_U, - }, - - 620); + add_machine_instr(result, "CIB", mach_format::RIS, { reg_4_U, imm_8_S, mask_4_U, db_12_4_U }, 620); + add_machine_instr(result, "CGIB", mach_format::RIS, { reg_4_U, imm_8_S, mask_4_U, db_12_4_U }, 620); add_machine_instr(result, "CIJ", mach_format::RIE_c, { reg_4_U, imm_8_S, mask_4_U, rel_addr_imm_16_S }, 620); add_machine_instr(result, "CGIJ", mach_format::RIE_c, { reg_4_U, imm_8_S, mask_4_U, rel_addr_imm_16_S }, 620); add_machine_instr(result, "CFC", mach_format::S, { db_12_4_U }, 621); @@ -441,15 +394,7 @@ hlasm_plugin::parser_library::context::instruction::get_machine_instructions() add_machine_instr(result, "CLY", mach_format::RXY_a, { reg_4_U, dxb_20_4x4_S }, 636); add_machine_instr(result, "CLG", mach_format::RXY_a, { reg_4_U, dxb_20_4x4_S }, 636); add_machine_instr(result, "CLGF", mach_format::RXY_a, { reg_4_U, dxb_20_4x4_S }, 636); - add_machine_instr(result, - "CLC", - mach_format::SS_a, - { - db_12_8x4L_U, - db_12_4_U, - }, - - 636); + add_machine_instr(result, "CLC", mach_format::SS_a, { db_12_8x4L_U, db_12_4_U }, 636); add_machine_instr(result, "CLFI", mach_format::RIL_a, { reg_4_U, imm_32_S }, 636); add_machine_instr(result, "CLGFI", mach_format::RIL_a, { reg_4_U, imm_32_S }, 636); add_machine_instr(result, "CLI", mach_format::SI, { db_12_4_U, imm_8_U }, 636); @@ -1368,324 +1313,284 @@ hlasm_plugin::parser_library::context::instruction::get_machine_instructions() add_machine_instr(result, "TDGET", mach_format::RXE, { reg_4_U, dxb_12_4x4_U }, 1529); add_machine_instr(result, "TDGDT", mach_format::RXE, { reg_4_U, dxb_12_4x4_U }, 1529); add_machine_instr(result, "TDGXT", mach_format::RXE, { reg_4_U, dxb_12_4x4_U }, 1529); - add_machine_instr(result, "VBPERM", mach_format::VRR_c, { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U }, 1536); - add_machine_instr(result, "VGEF", mach_format::VRV, { vec_reg_4_U, dvb_12_4x4_U, mask_4_U }, 1536); + add_machine_instr(result, "VBPERM", mach_format::VRR_c, { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U }, 1536); + add_machine_instr(result, "VGEF", mach_format::VRV, { vec_reg_5_U, dvb_12_5x4_U, mask_4_U }, 1536); add_machine_instr( - result, "VCFPS", mach_format::VRR_a, { vec_reg_4_U, vec_reg_4_U, mask_4_U, mask_4_U, mask_4_U }, 1641); + result, "VCFPS", mach_format::VRR_a, { vec_reg_5_U, vec_reg_5_U, mask_4_U, mask_4_U, mask_4_U }, 1641); add_machine_instr( - result, "VCLFP", mach_format::VRR_a, { vec_reg_4_U, vec_reg_4_U, mask_4_U, mask_4_U, mask_4_U }, 1611); - add_machine_instr(result, "VGEG", mach_format::VRV, { vec_reg_4_U, dvb_12_4x4_U, mask_4_U }, 1536); - add_machine_instr(result, "VGBM", mach_format::VRI_a, { vec_reg_4_U, imm_16_U }, 1537); - add_machine_instr(result, "VGM", mach_format::VRI_b, { vec_reg_4_U, imm_8_U, imm_8_U, mask_4_U }, 1537); - add_machine_instr(result, "VL", mach_format::VRX, { vec_reg_4_U, dxb_12_4x4_U, mask_4_U }, 1, 1538); - add_machine_instr(result, "VSTEBRF", mach_format::VRX, { vec_reg_4_U, dxb_12_4x4_U, mask_4_U }, 1576); - add_machine_instr(result, "VSTEBRG", mach_format::VRX, { vec_reg_4_U, dxb_12_4x4_U, mask_4_U }, 1576); - add_machine_instr(result, "VLLEBRZ", mach_format::VRX, { vec_reg_4_U, dxb_12_4x4_U, mask_4_U }, 1562); - add_machine_instr(result, "VLREP", mach_format::VRX, { vec_reg_4_U, dxb_12_4x4_U, mask_4_U }, 1538); - add_machine_instr(result, "VLR", mach_format::VRR_a, { vec_reg_4_U, vec_reg_4_U }, 1538); - add_machine_instr(result, "VLEB", mach_format::VRX, { vec_reg_4_U, dxb_12_4x4_U, mask_4_U }, 1538); - add_machine_instr(result, "VLEBRH", mach_format::VRX, { vec_reg_4_U, dxb_12_4x4_U, mask_4_U }, 1561); - add_machine_instr(result, "VLEBRG", mach_format::VRX, { vec_reg_4_U, dxb_12_4x4_U, mask_4_U }, 1561); - add_machine_instr(result, "VLBRREP", mach_format::VRX, { vec_reg_4_U, dxb_12_4x4_U, mask_4_U }, 1562); - add_machine_instr(result, "VLER", mach_format::VRX, { vec_reg_4_U, dxb_12_4x4_U, mask_4_U }, 1564); - add_machine_instr(result, "VLBR", mach_format::VRX, { vec_reg_4_U, dxb_12_4x4_U, mask_4_U }, 1563); - add_machine_instr(result, "VLEH", mach_format::VRX, { vec_reg_4_U, dxb_12_4x4_U, mask_4_U }, 1539); - add_machine_instr(result, "VLEIH", mach_format::VRI_a, { vec_reg_4_U, imm_16_S, mask_4_U }, 1539); - add_machine_instr(result, "VLEF", mach_format::VRX, { vec_reg_4_U, dxb_12_4x4_U, mask_4_U }, 1539); - add_machine_instr(result, "VLEIF", mach_format::VRI_a, { vec_reg_4_U, imm_16_S, mask_4_U }, 1539); - add_machine_instr(result, "VLEG", mach_format::VRX, { vec_reg_4_U, dxb_12_4x4_U, mask_4_U }, 1539); - add_machine_instr(result, "VLEIG", mach_format::VRI_a, { vec_reg_4_U, imm_16_S, mask_4_U }, 1539); - add_machine_instr(result, "VLEIB", mach_format::VRI_a, { vec_reg_4_U, imm_16_S, mask_4_U }, 1539); - add_machine_instr(result, "VLGV", mach_format::VRS_c, { reg_4_U, vec_reg_4_U, db_12_4_U, mask_4_U }, 1539); - add_machine_instr(result, "VLLEZ", mach_format::VRX, { vec_reg_4_U, dxb_12_4x4_U, mask_4_U }, 1540); - add_machine_instr(result, "VLM", mach_format::VRS_a, { vec_reg_4_U, vec_reg_4_U, db_12_4_U, mask_4_U }, 1, 1541); - add_machine_instr(result, "VLRLR", mach_format::VRS_d, { vec_reg_4_U, reg_4_U, db_12_4_U }, 1541); - add_machine_instr(result, "VLRL", mach_format::VSI, { vec_reg_4_U, db_12_4_U, imm_8_U }, 1541); - add_machine_instr(result, "VLBB", mach_format::VRX, { vec_reg_4_U, dxb_12_4x4_U, mask_4_U }, 1542); - add_machine_instr(result, "VLVG", mach_format::VRS_b, { vec_reg_4_U, reg_4_U, db_12_4_U, mask_4_U }, 1543); - add_machine_instr(result, "VLVGP", mach_format::VRR_f, { vec_reg_4_U, reg_4_U, reg_4_U }, 1543); - add_machine_instr(result, "VLL", mach_format::VRS_b, { vec_reg_4_U, reg_4_U, db_12_4_U }, 1543); - add_machine_instr(result, "VMRH", mach_format::VRR_c, { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, mask_4_U }, 1544); - add_machine_instr(result, "VMRL", mach_format::VRR_c, { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, mask_4_U }, 1544); - add_machine_instr(result, "VPK", mach_format::VRR_c, { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, mask_4_U }, 1545); + result, "VCLFP", mach_format::VRR_a, { vec_reg_5_U, vec_reg_5_U, mask_4_U, mask_4_U, mask_4_U }, 1611); + add_machine_instr(result, "VGEG", mach_format::VRV, { vec_reg_5_U, dvb_12_5x4_U, mask_4_U }, 1536); + add_machine_instr(result, "VGBM", mach_format::VRI_a, { vec_reg_5_U, imm_16_U }, 1537); + add_machine_instr(result, "VGM", mach_format::VRI_b, { vec_reg_5_U, imm_8_U, imm_8_U, mask_4_U }, 1537); + add_machine_instr(result, "VL", mach_format::VRX, { vec_reg_5_U, dxb_12_4x4_U, mask_4_U }, 1, 1538); + add_machine_instr(result, "VSTEBRF", mach_format::VRX, { vec_reg_5_U, dxb_12_4x4_U, mask_4_U }, 1576); + add_machine_instr(result, "VSTEBRG", mach_format::VRX, { vec_reg_5_U, dxb_12_4x4_U, mask_4_U }, 1576); + add_machine_instr(result, "VLLEBRZ", mach_format::VRX, { vec_reg_5_U, dxb_12_4x4_U, mask_4_U }, 1562); + add_machine_instr(result, "VLREP", mach_format::VRX, { vec_reg_5_U, dxb_12_4x4_U, mask_4_U }, 1538); + add_machine_instr(result, "VLR", mach_format::VRR_a, { vec_reg_5_U, vec_reg_5_U }, 1538); + add_machine_instr(result, "VLEB", mach_format::VRX, { vec_reg_5_U, dxb_12_4x4_U, mask_4_U }, 1538); + add_machine_instr(result, "VLEBRH", mach_format::VRX, { vec_reg_5_U, dxb_12_4x4_U, mask_4_U }, 1561); + add_machine_instr(result, "VLEBRG", mach_format::VRX, { vec_reg_5_U, dxb_12_4x4_U, mask_4_U }, 1561); + add_machine_instr(result, "VLBRREP", mach_format::VRX, { vec_reg_5_U, dxb_12_4x4_U, mask_4_U }, 1562); + add_machine_instr(result, "VLER", mach_format::VRX, { vec_reg_5_U, dxb_12_4x4_U, mask_4_U }, 1564); + add_machine_instr(result, "VLBR", mach_format::VRX, { vec_reg_5_U, dxb_12_4x4_U, mask_4_U }, 1563); + add_machine_instr(result, "VLEH", mach_format::VRX, { vec_reg_5_U, dxb_12_4x4_U, mask_4_U }, 1539); + add_machine_instr(result, "VLEIH", mach_format::VRI_a, { vec_reg_5_U, imm_16_S, mask_4_U }, 1539); + add_machine_instr(result, "VLEF", mach_format::VRX, { vec_reg_5_U, dxb_12_4x4_U, mask_4_U }, 1539); + add_machine_instr(result, "VLEIF", mach_format::VRI_a, { vec_reg_5_U, imm_16_S, mask_4_U }, 1539); + add_machine_instr(result, "VLEG", mach_format::VRX, { vec_reg_5_U, dxb_12_4x4_U, mask_4_U }, 1539); + add_machine_instr(result, "VLEIG", mach_format::VRI_a, { vec_reg_5_U, imm_16_S, mask_4_U }, 1539); + add_machine_instr(result, "VLEIB", mach_format::VRI_a, { vec_reg_5_U, imm_16_S, mask_4_U }, 1539); + add_machine_instr(result, "VLGV", mach_format::VRS_c, { reg_4_U, vec_reg_5_U, db_12_4_U, mask_4_U }, 1539); + add_machine_instr(result, "VLLEZ", mach_format::VRX, { vec_reg_5_U, dxb_12_4x4_U, mask_4_U }, 1540); + add_machine_instr(result, "VLM", mach_format::VRS_a, { vec_reg_5_U, vec_reg_5_U, db_12_4_U, mask_4_U }, 1, 1541); + add_machine_instr(result, "VLRLR", mach_format::VRS_d, { vec_reg_5_U, reg_4_U, db_12_4_U }, 1541); + add_machine_instr(result, "VLRL", mach_format::VSI, { vec_reg_5_U, db_12_4_U, imm_8_U }, 1541); + add_machine_instr(result, "VLBB", mach_format::VRX, { vec_reg_5_U, dxb_12_4x4_U, mask_4_U }, 1542); + add_machine_instr(result, "VLVG", mach_format::VRS_b, { vec_reg_5_U, reg_4_U, db_12_4_U, mask_4_U }, 1543); + add_machine_instr(result, "VLVGP", mach_format::VRR_f, { vec_reg_5_U, reg_4_U, reg_4_U }, 1543); + add_machine_instr(result, "VLL", mach_format::VRS_b, { vec_reg_5_U, reg_4_U, db_12_4_U }, 1543); + add_machine_instr(result, "VMRH", mach_format::VRR_c, { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, mask_4_U }, 1544); + add_machine_instr(result, "VMRL", mach_format::VRR_c, { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, mask_4_U }, 1544); + add_machine_instr(result, "VPK", mach_format::VRR_c, { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, mask_4_U }, 1545); add_machine_instr( - result, "VPKS", mach_format::VRR_b, { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, mask_4_U, mask_4_U }, 1545); + result, "VPKS", mach_format::VRR_b, { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, mask_4_U, mask_4_U }, 1545); add_machine_instr( - result, "VPKLS", mach_format::VRR_b, { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, mask_4_U, mask_4_U }, 1546); + result, "VPKLS", mach_format::VRR_b, { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, mask_4_U, mask_4_U }, 1546); add_machine_instr( - result, "VPERM", mach_format::VRR_e, { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, vec_reg_4_U }, 1547); - add_machine_instr(result, "VPDI", mach_format::VRR_c, { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, mask_4_U }, 1547); - add_machine_instr(result, "VREP", mach_format::VRI_c, { vec_reg_4_U, vec_reg_4_U, imm_16_U, mask_4_U }, 1547); - add_machine_instr(result, "VREPI", mach_format::VRI_a, { vec_reg_4_U, imm_16_S, mask_4_U }, 1548); - add_machine_instr(result, "VSCEF", mach_format::VRV, { vec_reg_4_U, dvb_12_4x4_U, mask_4_U }, 1548); - add_machine_instr(result, "VSCEG", mach_format::VRV, { vec_reg_4_U, dvb_12_4x4_U, mask_4_U }, 1548); - add_machine_instr(result, "VSEL", mach_format::VRR_e, { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, vec_reg_4_U }, 1549); - add_machine_instr(result, "VSEG", mach_format::VRR_a, { vec_reg_4_U, vec_reg_4_U, mask_4_U }, 1549); - add_machine_instr(result, "VSTBR", mach_format::VRX, { vec_reg_4_U, dxb_12_4x4_U, mask_4_U }, 1576); - add_machine_instr(result, "VST", mach_format::VRX, { vec_reg_4_U, dxb_12_4x4_U, mask_4_U }, 1, 1550); - add_machine_instr(result, "VSTEB", mach_format::VRX, { vec_reg_4_U, dxb_12_4x4_U, mask_4_U }, 1550); - add_machine_instr(result, "VSTEBRH", mach_format::VRX, { vec_reg_4_U, dxb_12_4x4_U, mask_4_U }, 1576); - add_machine_instr(result, "VSTEH", mach_format::VRX, { vec_reg_4_U, dxb_12_4x4_U, mask_4_U }, 1550); - add_machine_instr(result, "VSTEF", mach_format::VRX, { vec_reg_4_U, dxb_12_4x4_U, mask_4_U }, 1550); - add_machine_instr(result, "VSTEG", mach_format::VRX, { vec_reg_4_U, dxb_12_4x4_U, mask_4_U }, 1550); - add_machine_instr(result, "VSTER", mach_format::VRX, { vec_reg_4_U, dxb_12_4x4_U, mask_4_U }, 1578); - add_machine_instr(result, "VSTM", mach_format::VRS_a, { vec_reg_4_U, vec_reg_4_U, db_12_4_U, mask_4_U }, 1, 1551); - add_machine_instr(result, "VSTRLR", mach_format::VRS_d, { vec_reg_4_U, reg_4_U, db_12_4_U }, 1551); - add_machine_instr(result, "VSTRL", mach_format::VSI, { vec_reg_4_U, db_12_4_U, imm_8_U }, 1551); - add_machine_instr(result, "VSTL", mach_format::VRS_b, { vec_reg_4_U, reg_4_U, db_12_4_U }, 1552); - add_machine_instr(result, "VUPH", mach_format::VRR_a, { vec_reg_4_U, vec_reg_4_U, mask_4_U }, 1552); - add_machine_instr(result, "VUPL", mach_format::VRR_a, { vec_reg_4_U, vec_reg_4_U, mask_4_U }, 1553); - add_machine_instr(result, "VUPLH", mach_format::VRR_a, { vec_reg_4_U, vec_reg_4_U, mask_4_U }, 1553); - add_machine_instr(result, "VUPLL", mach_format::VRR_a, { vec_reg_4_U, vec_reg_4_U, mask_4_U }, 1554); - add_machine_instr(result, "VA", mach_format::VRR_c, { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, mask_4_U }, 1557); - add_machine_instr(result, "VACC", mach_format::VRR_c, { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, mask_4_U }, 1558); + result, "VPERM", mach_format::VRR_e, { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, vec_reg_5_U }, 1547); + add_machine_instr(result, "VPDI", mach_format::VRR_c, { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, mask_4_U }, 1547); + add_machine_instr(result, "VREP", mach_format::VRI_c, { vec_reg_5_U, vec_reg_5_U, imm_16_U, mask_4_U }, 1547); + add_machine_instr(result, "VREPI", mach_format::VRI_a, { vec_reg_5_U, imm_16_S, mask_4_U }, 1548); + add_machine_instr(result, "VSCEF", mach_format::VRV, { vec_reg_5_U, dvb_12_5x4_U, mask_4_U }, 1548); + add_machine_instr(result, "VSCEG", mach_format::VRV, { vec_reg_5_U, dvb_12_5x4_U, mask_4_U }, 1548); + add_machine_instr(result, "VSEL", mach_format::VRR_e, { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, vec_reg_5_U }, 1549); + add_machine_instr(result, "VSEG", mach_format::VRR_a, { vec_reg_5_U, vec_reg_5_U, mask_4_U }, 1549); + add_machine_instr(result, "VSTBR", mach_format::VRX, { vec_reg_5_U, dxb_12_4x4_U, mask_4_U }, 1576); + add_machine_instr(result, "VST", mach_format::VRX, { vec_reg_5_U, dxb_12_4x4_U, mask_4_U }, 1, 1550); + add_machine_instr(result, "VSTEB", mach_format::VRX, { vec_reg_5_U, dxb_12_4x4_U, mask_4_U }, 1550); + add_machine_instr(result, "VSTEBRH", mach_format::VRX, { vec_reg_5_U, dxb_12_4x4_U, mask_4_U }, 1576); + add_machine_instr(result, "VSTEH", mach_format::VRX, { vec_reg_5_U, dxb_12_4x4_U, mask_4_U }, 1550); + add_machine_instr(result, "VSTEF", mach_format::VRX, { vec_reg_5_U, dxb_12_4x4_U, mask_4_U }, 1550); + add_machine_instr(result, "VSTEG", mach_format::VRX, { vec_reg_5_U, dxb_12_4x4_U, mask_4_U }, 1550); + add_machine_instr(result, "VSTER", mach_format::VRX, { vec_reg_5_U, dxb_12_4x4_U, mask_4_U }, 1578); + add_machine_instr(result, "VSTM", mach_format::VRS_a, { vec_reg_5_U, vec_reg_5_U, db_12_4_U, mask_4_U }, 1, 1551); + add_machine_instr(result, "VSTRLR", mach_format::VRS_d, { vec_reg_5_U, reg_4_U, db_12_4_U }, 1551); + add_machine_instr(result, "VSTRL", mach_format::VSI, { vec_reg_5_U, db_12_4_U, imm_8_U }, 1551); + add_machine_instr(result, "VSTL", mach_format::VRS_b, { vec_reg_5_U, reg_4_U, db_12_4_U }, 1552); + add_machine_instr(result, "VUPH", mach_format::VRR_a, { vec_reg_5_U, vec_reg_5_U, mask_4_U }, 1552); + add_machine_instr(result, "VUPL", mach_format::VRR_a, { vec_reg_5_U, vec_reg_5_U, mask_4_U }, 1553); + add_machine_instr(result, "VUPLH", mach_format::VRR_a, { vec_reg_5_U, vec_reg_5_U, mask_4_U }, 1553); + add_machine_instr(result, "VUPLL", mach_format::VRR_a, { vec_reg_5_U, vec_reg_5_U, mask_4_U }, 1554); + add_machine_instr(result, "VA", mach_format::VRR_c, { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, mask_4_U }, 1557); + add_machine_instr(result, "VACC", mach_format::VRR_c, { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, mask_4_U }, 1558); add_machine_instr( - result, "VAC", mach_format::VRR_d, { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, mask_4_U }, 1558); - add_machine_instr(result, - "VACCC", - mach_format::VRR_d, - { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, mask_4_U }, - - 1559); - add_machine_instr(result, "VN", mach_format::VRR_c, { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U }, 1559); - add_machine_instr(result, "VNC", mach_format::VRR_c, { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U }, 1559); - add_machine_instr(result, "VAVG", mach_format::VRR_c, { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, mask_4_U }, 1560); - add_machine_instr(result, "VAVGL", mach_format::VRR_c, { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, mask_4_U }, 1560); - add_machine_instr(result, "VCKSM", mach_format::VRR_c, { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U }, 1560); - add_machine_instr(result, "VEC", mach_format::VRR_a, { vec_reg_4_U, vec_reg_4_U, mask_4_U }, 1561); - add_machine_instr(result, "VECL", mach_format::VRR_a, { vec_reg_4_U, vec_reg_4_U, mask_4_U }, 1561); + result, "VAC", mach_format::VRR_d, { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, mask_4_U }, 1558); add_machine_instr( - result, "VCEQ", mach_format::VRR_b, { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, mask_4_U, mask_4_U }, 1561); + result, "VACCC", mach_format::VRR_d, { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, mask_4_U }, 1559); + add_machine_instr(result, "VN", mach_format::VRR_c, { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U }, 1559); + add_machine_instr(result, "VNC", mach_format::VRR_c, { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U }, 1559); + add_machine_instr(result, "VAVG", mach_format::VRR_c, { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, mask_4_U }, 1560); + add_machine_instr(result, "VAVGL", mach_format::VRR_c, { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, mask_4_U }, 1560); + add_machine_instr(result, "VCKSM", mach_format::VRR_c, { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U }, 1560); + add_machine_instr(result, "VEC", mach_format::VRR_a, { vec_reg_5_U, vec_reg_5_U, mask_4_U }, 1561); + add_machine_instr(result, "VECL", mach_format::VRR_a, { vec_reg_5_U, vec_reg_5_U, mask_4_U }, 1561); add_machine_instr( - result, "VCH", mach_format::VRR_b, { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, mask_4_U, mask_4_U }, 1562); + result, "VCEQ", mach_format::VRR_b, { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, mask_4_U, mask_4_U }, 1561); add_machine_instr( - result, "VCHL", mach_format::VRR_b, { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, mask_4_U, mask_4_U }, 1563); - add_machine_instr(result, "VCLZ", mach_format::VRR_a, { vec_reg_4_U, vec_reg_4_U, mask_4_U }, 1564); - add_machine_instr(result, "VCTZ", mach_format::VRR_a, { vec_reg_4_U, vec_reg_4_U, mask_4_U }, 1564); - add_machine_instr(result, "VGFM", mach_format::VRR_c, { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, mask_4_U }, 1565); - add_machine_instr(result, "VX", mach_format::VRR_c, { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U }, 1565); - add_machine_instr(result, "VLC", mach_format::VRR_a, { vec_reg_4_U, vec_reg_4_U, mask_4_U }, 1566); - add_machine_instr(result, - "VGFMA", - mach_format::VRR_d, - { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, mask_4_U }, - - 1566); - add_machine_instr(result, "VLP", mach_format::VRR_a, { vec_reg_4_U, vec_reg_4_U, mask_4_U }, 1566); - add_machine_instr(result, "VMX", mach_format::VRR_c, { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, mask_4_U }, 1567); - add_machine_instr(result, "VMXL", mach_format::VRR_c, { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, mask_4_U }, 1567); - add_machine_instr(result, "VMN", mach_format::VRR_c, { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, mask_4_U }, 1567); - add_machine_instr(result, "VMNL", mach_format::VRR_c, { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, mask_4_U }, 1568); + result, "VCH", mach_format::VRR_b, { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, mask_4_U, mask_4_U }, 1562); add_machine_instr( - result, "VMAL", mach_format::VRR_d, { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, mask_4_U }, 1568); + result, "VCHL", mach_format::VRR_b, { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, mask_4_U, mask_4_U }, 1563); + add_machine_instr(result, "VCLZ", mach_format::VRR_a, { vec_reg_5_U, vec_reg_5_U, mask_4_U }, 1564); + add_machine_instr(result, "VCTZ", mach_format::VRR_a, { vec_reg_5_U, vec_reg_5_U, mask_4_U }, 1564); + add_machine_instr(result, "VGFM", mach_format::VRR_c, { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, mask_4_U }, 1565); + add_machine_instr(result, "VX", mach_format::VRR_c, { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U }, 1565); + add_machine_instr(result, "VLC", mach_format::VRR_a, { vec_reg_5_U, vec_reg_5_U, mask_4_U }, 1566); add_machine_instr( - result, "VMAH", mach_format::VRR_d, { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, mask_4_U }, 1569); - add_machine_instr(result, - "VMALH", - mach_format::VRR_d, - { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, mask_4_U }, - - 1569); + result, "VGFMA", mach_format::VRR_d, { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, mask_4_U }, 1566); + add_machine_instr(result, "VLP", mach_format::VRR_a, { vec_reg_5_U, vec_reg_5_U, mask_4_U }, 1566); + add_machine_instr(result, "VMX", mach_format::VRR_c, { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, mask_4_U }, 1567); + add_machine_instr(result, "VMXL", mach_format::VRR_c, { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, mask_4_U }, 1567); + add_machine_instr(result, "VMN", mach_format::VRR_c, { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, mask_4_U }, 1567); + add_machine_instr(result, "VMNL", mach_format::VRR_c, { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, mask_4_U }, 1568); add_machine_instr( - result, "VMAE", mach_format::VRR_d, { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, mask_4_U }, 1569); - add_machine_instr(result, - "VMALE", - mach_format::VRR_d, - { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, mask_4_U }, - - 1569); + result, "VMAL", mach_format::VRR_d, { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, mask_4_U }, 1568); add_machine_instr( - result, "VMAO", mach_format::VRR_d, { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, mask_4_U }, 1570); - add_machine_instr(result, - "VMALO", - mach_format::VRR_d, - { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, mask_4_U }, - - 1570); - add_machine_instr(result, "VMH", mach_format::VRR_c, { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, mask_4_U }, 1570); - add_machine_instr(result, "VMLH", mach_format::VRR_c, { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, mask_4_U }, 1571); - add_machine_instr(result, "VML", mach_format::VRR_c, { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, mask_4_U }, 1571); - add_machine_instr(result, "VME", mach_format::VRR_c, { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, mask_4_U }, 1572); - add_machine_instr(result, "VMLE", mach_format::VRR_c, { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, mask_4_U }, 1572); - add_machine_instr(result, "VMO", mach_format::VRR_c, { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, mask_4_U }, 1572); - add_machine_instr(result, "VMLO", mach_format::VRR_c, { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, mask_4_U }, 1572); + result, "VMAH", mach_format::VRR_d, { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, mask_4_U }, 1569); + add_machine_instr( + result, "VMALH", mach_format::VRR_d, { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, mask_4_U }, 1569); + add_machine_instr( + result, "VMAE", mach_format::VRR_d, { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, mask_4_U }, 1569); + add_machine_instr( + result, "VMALE", mach_format::VRR_d, { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, mask_4_U }, 1569); + add_machine_instr( + result, "VMAO", mach_format::VRR_d, { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, mask_4_U }, 1570); + add_machine_instr( + result, "VMALO", mach_format::VRR_d, { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, mask_4_U }, 1570); + add_machine_instr(result, "VMH", mach_format::VRR_c, { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, mask_4_U }, 1570); + add_machine_instr(result, "VMLH", mach_format::VRR_c, { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, mask_4_U }, 1571); + add_machine_instr(result, "VML", mach_format::VRR_c, { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, mask_4_U }, 1571); + add_machine_instr(result, "VME", mach_format::VRR_c, { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, mask_4_U }, 1572); + add_machine_instr(result, "VMLE", mach_format::VRR_c, { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, mask_4_U }, 1572); + add_machine_instr(result, "VMO", mach_format::VRR_c, { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, mask_4_U }, 1572); + add_machine_instr(result, "VMLO", mach_format::VRR_c, { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, mask_4_U }, 1572); add_machine_instr(result, "VMSL", mach_format::VRR_d, - { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, mask_4_U, mask_4_U }, - + { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, mask_4_U, mask_4_U }, 1573); - add_machine_instr(result, "VNN", mach_format::VRR_c, { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U }, 1574); - add_machine_instr(result, "VNO", mach_format::VRR_c, { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U }, 1574); - add_machine_instr(result, "VNX", mach_format::VRR_c, { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U }, 1574); - add_machine_instr(result, "VO", mach_format::VRR_c, { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U }, 1574); - add_machine_instr(result, "VOC", mach_format::VRR_c, { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U }, 1575); - add_machine_instr(result, "VPOPCT", mach_format::VRR_a, { vec_reg_4_U, vec_reg_4_U, mask_4_U }, 1575); - add_machine_instr(result, "VERLLV", mach_format::VRR_c, { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, mask_4_U }, 1575); - add_machine_instr(result, "VERLL", mach_format::VRS_a, { vec_reg_4_U, vec_reg_4_U, db_12_4_U, mask_4_U }, 1575); + add_machine_instr(result, "VNN", mach_format::VRR_c, { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U }, 1574); + add_machine_instr(result, "VNO", mach_format::VRR_c, { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U }, 1574); + add_machine_instr(result, "VNX", mach_format::VRR_c, { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U }, 1574); + add_machine_instr(result, "VO", mach_format::VRR_c, { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U }, 1574); + add_machine_instr(result, "VOC", mach_format::VRR_c, { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U }, 1575); + add_machine_instr(result, "VPOPCT", mach_format::VRR_a, { vec_reg_5_U, vec_reg_5_U, mask_4_U }, 1575); + add_machine_instr(result, "VERLLV", mach_format::VRR_c, { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, mask_4_U }, 1575); + add_machine_instr(result, "VERLL", mach_format::VRS_a, { vec_reg_5_U, vec_reg_5_U, db_12_4_U, mask_4_U }, 1575); add_machine_instr( - result, "VERIM", mach_format::VRI_d, { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, imm_8_U, mask_4_U }, 1576); - add_machine_instr(result, "VESLV", mach_format::VRR_c, { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, mask_4_U }, 1577); - add_machine_instr(result, "VESL", mach_format::VRS_a, { vec_reg_4_U, vec_reg_4_U, db_12_4_U, mask_4_U }, 1577); - add_machine_instr(result, "VESRAV", mach_format::VRR_c, { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, mask_4_U }, 1577); - add_machine_instr(result, "VESRA", mach_format::VRS_a, { vec_reg_4_U, vec_reg_4_U, db_12_4_U, mask_4_U }, 1577); - add_machine_instr(result, "VESRLV", mach_format::VRR_c, { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, mask_4_U }, 1578); - add_machine_instr(result, "VESRL", mach_format::VRS_a, { vec_reg_4_U, vec_reg_4_U, db_12_4_U, mask_4_U }, 1578); - add_machine_instr(result, "VSLD", mach_format::VRI_d, { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, imm_8_U }, 1607); - add_machine_instr(result, "VSRD", mach_format::VRI_d, { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, imm_8_U }, 1608); - add_machine_instr(result, "VSLDB", mach_format::VRI_d, { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, imm_8_U }, 1579); - add_machine_instr(result, "VSL", mach_format::VRR_c, { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U }, 1579); - add_machine_instr(result, "VSLB", mach_format::VRR_c, { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U }, 1579); - add_machine_instr(result, "VSRA", mach_format::VRR_c, { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U }, 1579); - add_machine_instr(result, "VSRAB", mach_format::VRR_c, { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U }, 1580); - add_machine_instr(result, "VSRL", mach_format::VRR_c, { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U }, 1580); - add_machine_instr(result, "VSRLB", mach_format::VRR_c, { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U }, 1580); - add_machine_instr(result, "VS", mach_format::VRR_c, { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, mask_4_U }, 1580); - add_machine_instr(result, "VSCBI", mach_format::VRR_c, { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, mask_4_U }, 1581); + result, "VERIM", mach_format::VRI_d, { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, imm_8_U, mask_4_U }, 1576); + add_machine_instr(result, "VESLV", mach_format::VRR_c, { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, mask_4_U }, 1577); + add_machine_instr(result, "VESL", mach_format::VRS_a, { vec_reg_5_U, vec_reg_5_U, db_12_4_U, mask_4_U }, 1577); + add_machine_instr(result, "VESRAV", mach_format::VRR_c, { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, mask_4_U }, 1577); + add_machine_instr(result, "VESRA", mach_format::VRS_a, { vec_reg_5_U, vec_reg_5_U, db_12_4_U, mask_4_U }, 1577); + add_machine_instr(result, "VESRLV", mach_format::VRR_c, { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, mask_4_U }, 1578); + add_machine_instr(result, "VESRL", mach_format::VRS_a, { vec_reg_5_U, vec_reg_5_U, db_12_4_U, mask_4_U }, 1578); + add_machine_instr(result, "VSLD", mach_format::VRI_d, { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, imm_8_U }, 1607); + add_machine_instr(result, "VSRD", mach_format::VRI_d, { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, imm_8_U }, 1608); + add_machine_instr(result, "VSLDB", mach_format::VRI_d, { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, imm_8_U }, 1579); + add_machine_instr(result, "VSL", mach_format::VRR_c, { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U }, 1579); + add_machine_instr(result, "VSLB", mach_format::VRR_c, { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U }, 1579); + add_machine_instr(result, "VSRA", mach_format::VRR_c, { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U }, 1579); + add_machine_instr(result, "VSRAB", mach_format::VRR_c, { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U }, 1580); + add_machine_instr(result, "VSRL", mach_format::VRR_c, { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U }, 1580); + add_machine_instr(result, "VSRLB", mach_format::VRR_c, { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U }, 1580); + add_machine_instr(result, "VS", mach_format::VRR_c, { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, mask_4_U }, 1580); + add_machine_instr(result, "VSCBI", mach_format::VRR_c, { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, mask_4_U }, 1581); add_machine_instr( - result, "VCSFP", mach_format::VRR_a, { vec_reg_4_U, vec_reg_4_U, mask_4_U, mask_4_U, mask_4_U }, 1644); + result, "VCSFP", mach_format::VRR_a, { vec_reg_5_U, vec_reg_5_U, mask_4_U, mask_4_U, mask_4_U }, 1644); add_machine_instr( - result, "VSBI", mach_format::VRR_d, { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, mask_4_U }, 1581); - add_machine_instr(result, - "VSBCBI", - mach_format::VRR_d, - { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, mask_4_U }, - - 1582); - add_machine_instr(result, "VSUMG", mach_format::VRR_c, { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, mask_4_U }, 1582); - add_machine_instr(result, "VSUMQ", mach_format::VRR_c, { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, mask_4_U }, 1583); - add_machine_instr(result, "VSUM", mach_format::VRR_c, { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, mask_4_U }, 1583); - add_machine_instr(result, "VTM", mach_format::VRR_a, { vec_reg_4_U, vec_reg_4_U }, 1584); + result, "VSBI", mach_format::VRR_d, { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, mask_4_U }, 1581); add_machine_instr( - result, "VFAE", mach_format::VRR_b, { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, mask_4_U, mask_4_U }, 1, 1585); + result, "VSBCBI", mach_format::VRR_d, { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, mask_4_U }, 1582); + add_machine_instr(result, "VSUMG", mach_format::VRR_c, { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, mask_4_U }, 1582); + add_machine_instr(result, "VSUMQ", mach_format::VRR_c, { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, mask_4_U }, 1583); + add_machine_instr(result, "VSUM", mach_format::VRR_c, { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, mask_4_U }, 1583); + add_machine_instr(result, "VTM", mach_format::VRR_a, { vec_reg_5_U, vec_reg_5_U }, 1584); add_machine_instr( - result, "VFEE", mach_format::VRR_b, { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, mask_4_U, mask_4_U }, 1, 1587); - add_machine_instr(result, - "VFENE", - mach_format::VRR_b, - { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, mask_4_U, mask_4_U }, - 1, - - 1588); - add_machine_instr(result, "VISTR", mach_format::VRR_a, { vec_reg_4_U, vec_reg_4_U, mask_4_U, mask_4_U }, 1, 1589); + result, "VFAE", mach_format::VRR_b, { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, mask_4_U, mask_4_U }, 1, 1585); + add_machine_instr( + result, "VFEE", mach_format::VRR_b, { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, mask_4_U, mask_4_U }, 1, 1587); + add_machine_instr( + result, "VFENE", mach_format::VRR_b, { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, mask_4_U, mask_4_U }, 1, 1588); + add_machine_instr(result, "VISTR", mach_format::VRR_a, { vec_reg_5_U, vec_reg_5_U, mask_4_U, mask_4_U }, 1, 1589); add_machine_instr(result, "VSTRC", mach_format::VRR_d, - { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, mask_4_U, mask_4_U }, + { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, mask_4_U, mask_4_U }, 1, - 1590); add_machine_instr(result, "VSTRS", mach_format::VRR_d, - { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, mask_4_U, mask_4_U }, + { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, mask_4_U, mask_4_U }, 1, 1622); add_machine_instr( - result, "VFA", mach_format::VRR_c, { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, mask_4_U, mask_4_U }, 1595); - add_machine_instr(result, "WFC", mach_format::VRR_a, { vec_reg_4_U, vec_reg_4_U, mask_4_U, mask_4_U }, 1599); - add_machine_instr(result, "WFK", mach_format::VRR_a, { vec_reg_4_U, vec_reg_4_U, mask_4_U, mask_4_U }, 1600); + result, "VFA", mach_format::VRR_c, { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, mask_4_U, mask_4_U }, 1595); + add_machine_instr(result, "WFC", mach_format::VRR_a, { vec_reg_5_U, vec_reg_5_U, mask_4_U, mask_4_U }, 1599); + add_machine_instr(result, "WFK", mach_format::VRR_a, { vec_reg_5_U, vec_reg_5_U, mask_4_U, mask_4_U }, 1600); add_machine_instr(result, "VFCE", mach_format::VRR_c, - { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, mask_4_U, mask_4_U, mask_4_U }, - + { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, mask_4_U, mask_4_U, mask_4_U }, 1601); add_machine_instr(result, "VFCH", mach_format::VRR_c, - { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, mask_4_U, mask_4_U, mask_4_U }, - + { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, mask_4_U, mask_4_U, mask_4_U }, 1603); add_machine_instr(result, "VFCHE", mach_format::VRR_c, - { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, mask_4_U, mask_4_U, mask_4_U }, - + { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, mask_4_U, mask_4_U, mask_4_U }, 1605); add_machine_instr( - result, "VCFPS", mach_format::VRR_a, { vec_reg_4_U, vec_reg_4_U, mask_4_U, mask_4_U, mask_4_U }, 1607); + result, "VCFPS", mach_format::VRR_a, { vec_reg_5_U, vec_reg_5_U, mask_4_U, mask_4_U, mask_4_U }, 1607); add_machine_instr( - result, "VCFPL", mach_format::VRR_a, { vec_reg_4_U, vec_reg_4_U, mask_4_U, mask_4_U, mask_4_U }, 1643); + result, "VCFPL", mach_format::VRR_a, { vec_reg_5_U, vec_reg_5_U, mask_4_U, mask_4_U, mask_4_U }, 1643); add_machine_instr( - result, "VCLGD", mach_format::VRR_a, { vec_reg_4_U, vec_reg_4_U, mask_4_U, mask_4_U, mask_4_U }, 1611); + result, "VCLGD", mach_format::VRR_a, { vec_reg_5_U, vec_reg_5_U, mask_4_U, mask_4_U, mask_4_U }, 1611); add_machine_instr( - result, "VFD", mach_format::VRR_c, { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, mask_4_U, mask_4_U }, 1613); + result, "VFD", mach_format::VRR_c, { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, mask_4_U, mask_4_U }, 1613); add_machine_instr( - result, "VFI", mach_format::VRR_a, { vec_reg_4_U, vec_reg_4_U, mask_4_U, mask_4_U, mask_4_U }, 1615); - add_machine_instr(result, "VFLL", mach_format::VRR_a, { vec_reg_4_U, vec_reg_4_U, mask_4_U, mask_4_U }, 1617); + result, "VFI", mach_format::VRR_a, { vec_reg_5_U, vec_reg_5_U, mask_4_U, mask_4_U, mask_4_U }, 1615); + add_machine_instr(result, "VFLL", mach_format::VRR_a, { vec_reg_5_U, vec_reg_5_U, mask_4_U, mask_4_U }, 1617); add_machine_instr( - result, "VFLR", mach_format::VRR_a, { vec_reg_4_U, vec_reg_4_U, mask_4_U, mask_4_U, mask_4_U }, 1618); + result, "VFLR", mach_format::VRR_a, { vec_reg_5_U, vec_reg_5_U, mask_4_U, mask_4_U, mask_4_U }, 1618); add_machine_instr(result, "VFMAX", mach_format::VRR_c, - { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, mask_4_U, mask_4_U, mask_4_U }, - + { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, mask_4_U, mask_4_U, mask_4_U }, 1619); add_machine_instr(result, "VFMIN", mach_format::VRR_c, - { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, mask_4_U, mask_4_U, mask_4_U }, - + { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, mask_4_U, mask_4_U, mask_4_U }, 1625); add_machine_instr( - result, "VFM", mach_format::VRR_c, { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, mask_4_U, mask_4_U }, 1631); + result, "VFM", mach_format::VRR_c, { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, mask_4_U, mask_4_U }, 1631); add_machine_instr(result, "VFMA", mach_format::VRR_e, - { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, mask_4_U, mask_4_U }, - + { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, mask_4_U, mask_4_U }, 1633); add_machine_instr(result, "VFMS", mach_format::VRR_e, - { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, mask_4_U, mask_4_U }, - + { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, mask_4_U, mask_4_U }, 1633); add_machine_instr(result, "VFNMA", mach_format::VRR_e, - { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, mask_4_U, mask_4_U }, - + { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, mask_4_U, mask_4_U }, 1633); add_machine_instr(result, "VFNMS", mach_format::VRR_e, - { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, mask_4_U, mask_4_U }, - + { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, mask_4_U, mask_4_U }, 1633); add_machine_instr( - result, "VFPSO", mach_format::VRR_a, { vec_reg_4_U, vec_reg_4_U, mask_4_U, mask_4_U, mask_4_U }, 1635); - add_machine_instr(result, "VFSQ", mach_format::VRR_a, { vec_reg_4_U, vec_reg_4_U, mask_4_U, mask_4_U }, 1636); + result, "VFPSO", mach_format::VRR_a, { vec_reg_5_U, vec_reg_5_U, mask_4_U, mask_4_U, mask_4_U }, 1635); + add_machine_instr(result, "VFSQ", mach_format::VRR_a, { vec_reg_5_U, vec_reg_5_U, mask_4_U, mask_4_U }, 1636); add_machine_instr( - result, "VFS", mach_format::VRR_c, { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, mask_4_U, mask_4_U }, 1637); + result, "VFS", mach_format::VRR_c, { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, mask_4_U, mask_4_U }, 1637); add_machine_instr( - result, "VFTCI", mach_format::VRI_e, { vec_reg_4_U, vec_reg_4_U, imm_12_S, mask_4_U, mask_4_U }, 1638); + result, "VFTCI", mach_format::VRI_e, { vec_reg_5_U, vec_reg_5_U, imm_12_S, mask_4_U, mask_4_U }, 1638); add_machine_instr( - result, "VAP", mach_format::VRI_f, { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, imm_8_U, mask_4_U }, 1643); - add_machine_instr(result, "VCP", mach_format::VRR_h, { vec_reg_4_U, vec_reg_4_U, mask_4_U }, 1644); - add_machine_instr(result, "VCVB", mach_format::VRR_i, { reg_4_U, vec_reg_4_U, mask_4_U }, 1645); - add_machine_instr(result, "VCVBG", mach_format::VRR_i, { reg_4_U, vec_reg_4_U, mask_4_U }, 1645); - add_machine_instr(result, "VCVD", mach_format::VRI_i, { vec_reg_4_U, reg_4_U, imm_8_S, mask_4_U }, 1646); - add_machine_instr(result, "VCVDG", mach_format::VRI_i, { vec_reg_4_U, reg_4_U, imm_8_S, mask_4_U }, 1646); + result, "VAP", mach_format::VRI_f, { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, imm_8_U, mask_4_U }, 1643); + add_machine_instr(result, "VCP", mach_format::VRR_h, { vec_reg_5_U, vec_reg_5_U, mask_4_U }, 1644); + add_machine_instr(result, "VCVB", mach_format::VRR_i, { reg_4_U, vec_reg_5_U, mask_4_U }, 1645); + add_machine_instr(result, "VCVBG", mach_format::VRR_i, { reg_4_U, vec_reg_5_U, mask_4_U }, 1645); + add_machine_instr(result, "VCVD", mach_format::VRI_i, { vec_reg_5_U, reg_4_U, imm_8_S, mask_4_U }, 1646); + add_machine_instr(result, "VCVDG", mach_format::VRI_i, { vec_reg_5_U, reg_4_U, imm_8_S, mask_4_U }, 1646); add_machine_instr( - result, "VDP", mach_format::VRI_f, { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, imm_8_U, mask_4_U }, 1648); + result, "VDP", mach_format::VRI_f, { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, imm_8_U, mask_4_U }, 1648); add_machine_instr( - result, "VMP", mach_format::VRI_f, { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, imm_8_U, mask_4_U }, 1650); + result, "VMP", mach_format::VRI_f, { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, imm_8_U, mask_4_U }, 1650); add_machine_instr( - result, "VMSP", mach_format::VRI_f, { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, imm_8_U, mask_4_U }, 1651); + result, "VMSP", mach_format::VRI_f, { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, imm_8_U, mask_4_U }, 1651); add_machine_instr( - result, "VRP", mach_format::VRI_f, { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, imm_8_U, mask_4_U }, 1654); + result, "VRP", mach_format::VRI_f, { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, imm_8_U, mask_4_U }, 1654); add_machine_instr( - result, "VSDP", mach_format::VRI_f, { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, imm_8_U, mask_4_U }, 1656); + result, "VSDP", mach_format::VRI_f, { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, imm_8_U, mask_4_U }, 1656); add_machine_instr( - result, "VSP", mach_format::VRI_f, { vec_reg_4_U, vec_reg_4_U, vec_reg_4_U, imm_8_U, mask_4_U }, 1658); - add_machine_instr(result, "VLIP", mach_format::VRI_h, { vec_reg_4_U, imm_16_S, imm_4_U }, 1649); - add_machine_instr(result, "VPKZ", mach_format::VSI, { vec_reg_4_U, db_12_4_U, imm_8_U }, 1652); + result, "VSP", mach_format::VRI_f, { vec_reg_5_U, vec_reg_5_U, vec_reg_5_U, imm_8_U, mask_4_U }, 1658); + add_machine_instr(result, "VLIP", mach_format::VRI_h, { vec_reg_5_U, imm_16_S, imm_4_U }, 1649); + add_machine_instr(result, "VPKZ", mach_format::VSI, { vec_reg_5_U, db_12_4_U, imm_8_U }, 1652); add_machine_instr( - result, "VPSOP", mach_format::VRI_g, { vec_reg_4_U, vec_reg_4_U, imm_8_U, imm_8_U, mask_4_U }, 1653); + result, "VPSOP", mach_format::VRI_g, { vec_reg_5_U, vec_reg_5_U, imm_8_U, imm_8_U, mask_4_U }, 1653); add_machine_instr( - result, "VSRP", mach_format::VRI_g, { vec_reg_4_U, vec_reg_4_U, imm_8_U, imm_8_S, mask_4_U }, 1657); + result, "VSRP", mach_format::VRI_g, { vec_reg_5_U, vec_reg_5_U, imm_8_U, imm_8_S, mask_4_U }, 1657); add_machine_instr(result, "SIE", mach_format::S, { db_12_4_U }, 7); add_machine_instr(result, "VAD", mach_format::RI_a, { reg_4_U, imm_16_U }, 0); add_machine_instr(result, "VSD", mach_format::RI_a, { reg_4_U, imm_16_U }, 0); @@ -1756,8 +1661,8 @@ hlasm_plugin::parser_library::context::instruction::get_machine_instructions() add_machine_instr(result, "VCVM", mach_format::RRE, { reg_4_U, reg_4_U }, 0); add_machine_instr(result, "VCZVM", mach_format::RRE, { reg_4_U, reg_4_U }, 0); add_machine_instr(result, "VCOVM", mach_format::RRE, { reg_4_U, reg_4_U }, 0); - add_machine_instr(result, "VTP", mach_format::VRR_g, { vec_reg_4_U }, 1660); - add_machine_instr(result, "VUPKZ", mach_format::VSI, { vec_reg_4_U, db_12_4_U, imm_8_U }, 1660); + add_machine_instr(result, "VTP", mach_format::VRR_g, { vec_reg_5_U }, 1660); + add_machine_instr(result, "VUPKZ", mach_format::VSI, { vec_reg_5_U, db_12_4_U, imm_8_U }, 1660); add_machine_instr(result, "VSTK", mach_format::RI_a, { reg_4_U, imm_16_U }, 0); add_machine_instr(result, "VSE", mach_format::RI_a, { reg_4_U, imm_16_U }, 0); add_machine_instr(result, "VSES", mach_format::RI_a, { reg_4_U, imm_16_U }, 0); diff --git a/parser_library/src/context/instruction.h b/parser_library/src/context/instruction.h index 13df5e24c..4a906fc00 100644 --- a/parser_library/src/context/instruction.h +++ b/parser_library/src/context/instruction.h @@ -135,7 +135,7 @@ const checking::parameter imm_16u = { false, 16, checking::machine_operand_type: const checking::parameter imm_24s = { true, 24, checking::machine_operand_type::IMM }; const checking::parameter imm_32s = { true, 32, checking::machine_operand_type::IMM }; const checking::parameter imm_32u = { false, 32, checking::machine_operand_type::IMM }; -const checking::parameter vec_reg = { false, 4, checking::machine_operand_type::VEC_REG }; +const checking::parameter vec_reg = { false, 5, checking::machine_operand_type::VEC_REG }; const checking::parameter reladdr_imm_12s = { true, 12, checking::machine_operand_type::RELOC_IMM }; const checking::parameter reladdr_imm_16s = { true, 16, checking::machine_operand_type::RELOC_IMM }; const checking::parameter reladdr_imm_24s = { true, 24, checking::machine_operand_type::RELOC_IMM }; @@ -155,7 +155,7 @@ const checking::machine_operand_format db_20_4_S = checking::machine_operand_for const checking::machine_operand_format drb_12_4x4_U = checking::machine_operand_format(dis_12u, dis_reg_r, base_); const checking::machine_operand_format dxb_12_4x4_U = checking::machine_operand_format(dis_12u, dis_reg, base_); const checking::machine_operand_format dxb_20_4x4_S = checking::machine_operand_format(dis_20s, dis_reg, base_); -const checking::machine_operand_format dvb_12_4x4_U = checking::machine_operand_format(dis_12u, vec_reg, base_); +const checking::machine_operand_format dvb_12_5x4_U = checking::machine_operand_format(dis_12u, vec_reg, base_); const checking::machine_operand_format reg_4_U = checking::machine_operand_format(reg, empty, empty); const checking::machine_operand_format mask_4_U = checking::machine_operand_format(mask, empty, empty); const checking::machine_operand_format imm_4_U = checking::machine_operand_format(imm_4u, empty, empty); @@ -166,7 +166,7 @@ const checking::machine_operand_format imm_12_S = checking::machine_operand_form const checking::machine_operand_format imm_16_S = checking::machine_operand_format(imm_16s, empty, empty); const checking::machine_operand_format imm_32_S = checking::machine_operand_format(imm_32s, empty, empty); const checking::machine_operand_format imm_32_U = checking::machine_operand_format(imm_32u, empty, empty); -const checking::machine_operand_format vec_reg_4_U = checking::machine_operand_format(vec_reg, empty, empty); +const checking::machine_operand_format vec_reg_5_U = checking::machine_operand_format(vec_reg, empty, empty); const checking::machine_operand_format db_12_8x4L_U = checking::machine_operand_format(dis_12u, length_8, base_); const checking::machine_operand_format db_12_4x4L_U = checking::machine_operand_format(dis_12u, length_4, base_); const checking::machine_operand_format rel_addr_imm_12_S = diff --git a/parser_library/src/processing/instruction_sets/asm_processor.cpp b/parser_library/src/processing/instruction_sets/asm_processor.cpp index c39c34ff0..ba883f2e7 100644 --- a/parser_library/src/processing/instruction_sets/asm_processor.cpp +++ b/parser_library/src/processing/instruction_sets/asm_processor.cpp @@ -452,11 +452,9 @@ void asm_processor::process_ORG(rebuilt_statement stmt) void asm_processor::process_OPSYN(rebuilt_statement stmt) { - if (stmt.operands_ref().value.size() > 1) - { - check(stmt, hlasm_ctx, checker_, *this); + const auto& operands = stmt.operands_ref().value; + if (!check(stmt, hlasm_ctx, checker_, *this)) return; - } auto label = find_label_symbol(stmt); if (label == context::id_storage::empty_id) @@ -467,9 +465,9 @@ void asm_processor::process_OPSYN(rebuilt_statement stmt) } context::id_index operand = context::id_storage::empty_id; - if (stmt.operands_ref().value.size() == 1) + if (operands.size() == 1) // covers also the " , " case { - auto expr_op = stmt.operands_ref().value.front()->access_asm()->access_expr(); + auto expr_op = operands.front()->access_asm()->access_expr(); if (expr_op) { if (auto expr = dynamic_cast(expr_op->expression.get())) @@ -489,7 +487,7 @@ void asm_processor::process_OPSYN(rebuilt_statement stmt) if (hlasm_ctx.get_operation_code(operand)) hlasm_ctx.add_mnemonic(label, operand); else - add_diagnostic(diagnostic_op::error_A246_OPSYN(stmt.operands_ref().value.front()->operand_range)); + add_diagnostic(diagnostic_op::error_A246_OPSYN(operands.front()->operand_range)); } } diff --git a/parser_library/src/workspaces/processor_group.cpp b/parser_library/src/workspaces/processor_group.cpp index fc13f2a15..61b82eafb 100644 --- a/parser_library/src/workspaces/processor_group.cpp +++ b/parser_library/src/workspaces/processor_group.cpp @@ -14,7 +14,7 @@ #include "processor_group.h" -#include "config/proc_conf.h" +#include "config/proc_grps.h" namespace hlasm_plugin::parser_library::workspaces { diff --git a/parser_library/src/workspaces/workspace.cpp b/parser_library/src/workspaces/workspace.cpp index c509e6bf0..e2645b26d 100644 --- a/parser_library/src/workspaces/workspace.cpp +++ b/parser_library/src/workspaces/workspace.cpp @@ -339,7 +339,7 @@ bool workspace::load_and_process_config() opened_ = true; config::pgm_conf pgm_config; - config::proc_conf proc_groups; + config::proc_grps proc_groups; file_ptr pgm_conf_file; bool load_ok = load_config(proc_groups, pgm_config, pgm_conf_file); @@ -421,7 +421,7 @@ bool workspace::load_and_process_config() return true; } -bool workspace::load_config(config::proc_conf& proc_groups, config::pgm_conf& pgm_config, file_ptr& pgm_conf_file) +bool workspace::load_config(config::proc_grps& proc_groups, config::pgm_conf& pgm_config, file_ptr& pgm_conf_file) { std::filesystem::path hlasm_base = utils::path::join(uri_, HLASM_PLUGIN_FOLDER); diff --git a/parser_library/src/workspaces/workspace.h b/parser_library/src/workspaces/workspace.h index 6bd3b06b0..5c67c4712 100644 --- a/parser_library/src/workspaces/workspace.h +++ b/parser_library/src/workspaces/workspace.h @@ -25,7 +25,7 @@ #include #include "config/pgm_conf.h" -#include "config/proc_conf.h" +#include "config/proc_grps.h" #include "diagnosable_impl.h" #include "file_manager.h" #include "lib_config.h" @@ -146,7 +146,7 @@ class workspace : public diagnosable_impl, public parse_lib_provider, public lsp bool load_and_process_config(); // Loads the pgm_conf.json and proc_grps.json from disk, adds them to file_manager_ and parses both jsons. // Returns false if there is any error. - bool load_config(config::proc_conf& proc_groups, config::pgm_conf& pgm_config, file_ptr& pgm_conf_file); + bool load_config(config::proc_grps& proc_groups, config::pgm_conf& pgm_config, file_ptr& pgm_conf_file); bool is_wildcard(const std::string& str); diff --git a/parser_library/test/checking/mach_instr_diag_test.cpp b/parser_library/test/checking/mach_instr_diag_test.cpp index a450bbc0c..57e4b517e 100644 --- a/parser_library/test/checking/mach_instr_diag_test.cpp +++ b/parser_library/test/checking/mach_instr_diag_test.cpp @@ -159,7 +159,7 @@ TEST(diagnostics, vec_reg_not_corresponding) { std::string input( R"( - VGEF 1,1(17,1),1 + VGEF 1,1(32,1),1 )"); analyzer a(input); a.analyze(); @@ -496,4 +496,17 @@ LEN120 DS CL1 a.collect_diags(); ASSERT_EQ(a.diags().size(), (size_t)1); ASSERT_EQ(a.diags().at(0).code, "ME003"); -} \ No newline at end of file +} + +TEST(diagnostics, vec_reg_limits) +{ + std::string input( + R"( + VAC 31,31,31,31,15 +)"); + analyzer a(input); + a.analyze(); + a.collect_diags(); + ASSERT_EQ(a.parser().getNumberOfSyntaxErrors(), (size_t)0); + ASSERT_EQ(a.diags().size(), (size_t)0); +} diff --git a/parser_library/test/config/CMakeLists.txt b/parser_library/test/config/CMakeLists.txt index 44cb9030d..74f468bb0 100644 --- a/parser_library/test/config/CMakeLists.txt +++ b/parser_library/test/config/CMakeLists.txt @@ -12,5 +12,5 @@ target_sources(library_test PRIVATE pgm_conf_test.cpp - proc_conf_test.cpp + proc_grps_test.cpp ) diff --git a/parser_library/test/config/proc_conf_test.cpp b/parser_library/test/config/proc_grps_test.cpp similarity index 84% rename from parser_library/test/config/proc_conf_test.cpp rename to parser_library/test/config/proc_grps_test.cpp index 9be6cb73d..94020047a 100644 --- a/parser_library/test/config/proc_conf_test.cpp +++ b/parser_library/test/config/proc_grps_test.cpp @@ -16,12 +16,12 @@ #include "gtest/gtest.h" -#include "config/proc_conf.h" +#include "config/proc_grps.h" #include "nlohmann/json.hpp" using namespace hlasm_plugin::parser_library::config; -TEST(proc_conf, library_read) +TEST(proc_grps, library_read) { const auto cases = { std::make_pair(R"("lib")"_json, library { "lib", {}, false }), @@ -39,7 +39,7 @@ TEST(proc_conf, library_read) } } -TEST(proc_conf, library_write) +TEST(proc_grps, library_write) { const library l = { "lib", {}, true }; const auto expected = R"({"path":"lib","optional":true})"_json; @@ -47,7 +47,7 @@ TEST(proc_conf, library_write) EXPECT_EQ(nlohmann::json(l), expected); } -TEST(proc_conf, assembler_options_read) +TEST(proc_grps, assembler_options_read) { const auto cases = { std::make_pair(R"({})"_json, assembler_options {}), @@ -64,7 +64,7 @@ TEST(proc_conf, assembler_options_read) } } -TEST(proc_conf, assembler_options_write) +TEST(proc_grps, assembler_options_write) { const auto cases = { std::make_pair(R"({})"_json, assembler_options {}), @@ -77,7 +77,7 @@ TEST(proc_conf, assembler_options_write) EXPECT_EQ(nlohmann::json(input), expected); } -static void compare_proc_conf(const proc_conf& pg, const proc_conf& expected) +static void compare_proc_grps(const proc_grps& pg, const proc_grps& expected) { ASSERT_EQ(pg.pgroups.size(), expected.pgroups.size()); for (size_t i = 0; i < pg.pgroups.size(); ++i) @@ -96,68 +96,68 @@ static void compare_proc_conf(const proc_conf& pg, const proc_conf& expected) } } -TEST(proc_conf, full_content_read) +TEST(proc_grps, full_content_read) { const auto cases = { - std::make_pair(R"({"pgroups":[]})"_json, proc_conf {}), + std::make_pair(R"({"pgroups":[]})"_json, proc_grps {}), std::make_pair(R"({"pgroups":[{"name":"P1", "libs":["lib1", {"path": "lib2", "optional":true}]}]})"_json, - proc_conf { { { "P1", { { "lib1", {}, false }, { "lib2", {}, true } } } } }), + proc_grps { { { "P1", { { "lib1", {}, false }, { "lib2", {}, true } } } } }), std::make_pair( R"({"pgroups":[{"name":"P1", "libs":["lib1", {"path": "lib2", "optional":true}]},{"name":"P2", "libs":["lib2_1", {"path": "lib2_2", "optional":true}]}]})"_json, - proc_conf { { { "P1", { { "lib1", {}, false }, { "lib2", {}, true } } }, + proc_grps { { { "P1", { { "lib1", {}, false }, { "lib2", {}, true } } }, { "P2", { { "lib2_1", {}, false }, { "lib2_2", {}, true } } } } }), std::make_pair( R"({"pgroups":[{"name":"P1", "libs":["lib1", {"path": "lib2", "optional":true}],"asm_options":{"SYSPARM":"PARAM","PROFILE":"PROFMAC"}},{"name":"P2", "libs":["lib2_1", {"path": "lib2_2", "optional":true}]}]})"_json, - proc_conf { { { "P1", { { "lib1", {}, false }, { "lib2", {}, true } }, { "PARAM", "PROFMAC" } }, + proc_grps { { { "P1", { { "lib1", {}, false }, { "lib2", {}, true } }, { "PARAM", "PROFMAC" } }, { "P2", { { "lib2_1", {}, false }, { "lib2_2", {}, true } } } } }), std::make_pair( R"({"pgroups":[{"name":"P1", "libs":["lib1", {"path": "lib2", "optional":true,"macro_extensions":["mac"]}],"asm_options":{"SYSPARM":"PARAM","PROFILE":"PROFMAC"}},{"name":"P2", "libs":["lib2_1", {"path": "lib2_2", "optional":true}]}],"macro_extensions":["asmmac"]})"_json, - proc_conf { { { "P1", { { "lib1", {}, false }, { "lib2", { "mac" }, true } }, { "PARAM", "PROFMAC" } }, + proc_grps { { { "P1", { { "lib1", {}, false }, { "lib2", { "mac" }, true } }, { "PARAM", "PROFMAC" } }, { "P2", { { "lib2_1", {}, false }, { "lib2_2", {}, true } } } }, { "asmmac" } }), std::make_pair( - R"({"pgroups":[{"name":"P1", "libs":[]}]})"_json, proc_conf { { { "P1", {}, {}, std::monostate {} } } }), + R"({"pgroups":[{"name":"P1", "libs":[]}]})"_json, proc_grps { { { "P1", {}, {}, std::monostate {} } } }), std::make_pair(R"({"pgroups":[{"name":"P1", "libs":[], "preprocessor":"DB2"}]})"_json, - proc_conf { { { "P1", {}, {}, db2_preprocessor {} } } }), + proc_grps { { { "P1", {}, {}, db2_preprocessor {} } } }), std::make_pair(R"({"pgroups":[{"name":"P1", "libs":[], "preprocessor":{"name":"DB2"}}]})"_json, - proc_conf { { { "P1", {}, {}, db2_preprocessor {} } } }), + proc_grps { { { "P1", {}, {}, db2_preprocessor {} } } }), }; for (const auto& [input, expected] : cases) - compare_proc_conf(input.get(), expected); + compare_proc_grps(input.get(), expected); } -TEST(proc_conf, full_content_write) +TEST(proc_grps, full_content_write) { const auto cases = { - std::make_pair(R"({"pgroups":[]})"_json, proc_conf {}), + std::make_pair(R"({"pgroups":[]})"_json, proc_grps {}), std::make_pair( R"({"pgroups":[{"name":"P1", "libs":[{"path":"lib1","optional":false}, {"path": "lib2", "optional":true}]}]})"_json, - proc_conf { { { "P1", { { "lib1", {}, false }, { "lib2", {}, true } } } } }), + proc_grps { { { "P1", { { "lib1", {}, false }, { "lib2", {}, true } } } } }), std::make_pair( R"({"pgroups":[{"name":"P1", "libs":[{"path":"lib1","optional":false}, {"path": "lib2", "optional":true}]},{"name":"P2", "libs":[{"path":"lib2_1","optional":false}, {"path": "lib2_2", "optional":true}]}]})"_json, - proc_conf { { { "P1", { { "lib1", {}, false }, { "lib2", {}, true } } }, + proc_grps { { { "P1", { { "lib1", {}, false }, { "lib2", {}, true } } }, { "P2", { { "lib2_1", {}, false }, { "lib2_2", {}, true } } } } }), std::make_pair( R"({"pgroups":[{"name":"P1", "libs":[{"path":"lib1","optional":false}, {"path": "lib2", "optional":true}],"asm_options":{"SYSPARM":"PARAM","PROFILE":"PROFMAC"}},{"name":"P2", "libs":[{"path":"lib2_1","optional":false}, {"path": "lib2_2", "optional":true}]}]})"_json, - proc_conf { { { "P1", { { "lib1", {}, false }, { "lib2", {}, true } }, { "PARAM", "PROFMAC" } }, + proc_grps { { { "P1", { { "lib1", {}, false }, { "lib2", {}, true } }, { "PARAM", "PROFMAC" } }, { "P2", { { "lib2_1", {}, false }, { "lib2_2", {}, true } } } } }), std::make_pair( R"({"pgroups":[{"name":"P1", "libs":[{"path":"lib1","optional":false}, {"path": "lib2", "optional":true,"macro_extensions":["mac"]}],"asm_options":{"SYSPARM":"PARAM","PROFILE":"PROFMAC"}},{"name":"P2", "libs":[{"path":"lib2_1","optional":false}, {"path": "lib2_2", "optional":true}]}],"macro_extensions":["asmmac"]})"_json, - proc_conf { { { "P1", { { "lib1", {}, false }, { "lib2", { "mac" }, true } }, { "PARAM", "PROFMAC" } }, + proc_grps { { { "P1", { { "lib1", {}, false }, { "lib2", { "mac" }, true } }, { "PARAM", "PROFMAC" } }, { "P2", { { "lib2_1", {}, false }, { "lib2_2", {}, true } } } }, { "asmmac" } }), std::make_pair( - R"({"pgroups":[{"name":"P1", "libs":[]}]})"_json, proc_conf { { { "P1", {}, {}, std::monostate {} } } }), + R"({"pgroups":[{"name":"P1", "libs":[]}]})"_json, proc_grps { { { "P1", {}, {}, std::monostate {} } } }), std::make_pair(R"({"pgroups":[{"name":"P1", "libs":[], "preprocessor":"DB2"}]})"_json, - proc_conf { { { "P1", {}, {}, db2_preprocessor {} } } }), + proc_grps { { { "P1", {}, {}, db2_preprocessor {} } } }), }; for (const auto& [expected, input] : cases) EXPECT_EQ(nlohmann::json(input), expected); } -TEST(proc_conf, invalid) +TEST(proc_grps, invalid) { const auto cases = { R"({})"_json, @@ -172,10 +172,10 @@ TEST(proc_conf, invalid) }; for (const auto& input : cases) - EXPECT_THROW(input.get(), nlohmann::json::exception); + EXPECT_THROW(input.get(), nlohmann::json::exception); } -TEST(proc_conf, assembler_options_validate) +TEST(proc_grps, assembler_options_validate) { const auto cases = { std::make_pair(assembler_options {}, true), diff --git a/parser_library/test/processing/opsyn_test.cpp b/parser_library/test/processing/opsyn_test.cpp index 70828a3be..9f3660ecd 100644 --- a/parser_library/test/processing/opsyn_test.cpp +++ b/parser_library/test/processing/opsyn_test.cpp @@ -279,3 +279,41 @@ LR OPSYN a.collect_diags(); ASSERT_EQ(a.diags().size(), (size_t)0); } + +TEST(OPSYN, tolerate_comma_argument) +{ + std::string input(R"( +LR OPSYN , +)"); + analyzer a(input); + a.analyze(); + a.collect_diags(); + EXPECT_TRUE(a.diags().empty()); +} + +TEST(OPSYN, full_circle) +{ + std::string input(R"( + GBLA &CNT +XDS OPSYN DS +DS OPSYN , + + MACRO , +&Label DS + GBLA &CNT +&CNT SETA &CNT+1 + MEND , + +A DS C + +DS OPSYN XDS +XDS OPSYN , + +B DS C +)"); + analyzer a(input); + a.analyze(); + a.collect_diags(); + EXPECT_TRUE(a.diags().empty()); + EXPECT_EQ(get_var_value(a.hlasm_ctx(), "CNT"), 1); +}