- 1-8 Xilinx UltraScale+ VU9P based FPGA slots
- Per FPGA Slot, Interfaces available for Custom Logic(CL):
- One x16 PCIe Gen 3 Interface
- Four DDR4 RDIMM interfaces (with ECC)
- AXI4 protocol support on all interfaces
- User-defined clock frequency driving all CL to Shell interfaces
- Multiple free running auxiliary clocks
- PCIE endpoint presentation to Custom Logic(CL)
- Management PF (physical function)
- Application PF
- Virtual JTAG, Virtual LED, Virtual DIP Switches
- PCIE interface between Shell(SH) and Custom Logic(CL).
- SH to CL inbound 512-bit AXI4 interface
- CL to SH outbound 512-bit AXI4 interface * Multiple 32-bit AXI-Lite buses for register access, mapped to different PCIe BARs
- Maximum payload size set by the Shell
- Maximum read request size set by the Shell
- AXI4 error handling * DDR interface between SH and CL
- CL to SH 512-bit AXI4 interface
- 1 DDR controller implemented in the SH (always available)
- 3 DDR controllers implemented in the CL (configurable number of implemented controllers allowed)
Release 1.3.4 (See ERRATA for unsupported features)
- EDMA/XDMA Driver improvements
- Additional SDAccel Platforms
- 1DDR for faster build times and smaller expanded shell
- RTL Kernel Debug adds support for virtual jtag debug on RTL kernels * IP Integrator GUI (HLx) improvements
- CL_DRAM_DMA fixes and improvements
- Dual master support * Simulation environment fixes and improvements
- AXI/AXIL Protocol checkers
- Shell model improvements
- SW co-simulation support on cl_hello_world
- DDR Model patch * Updated SH_DDR module in preparation for upcoming feature release
Release 1.3.3 (See ERRATA for unsupported features)
* New FPGA Image APIs for deleting and reading/editing attributes
Release 1.3.2 (See ERRATA for unsupported features)
- SDAccel general availability
Release 1.3.1 (See ERRATA for unsupported features)
- EDMA Driver release 1.0.29 - MSI-X fixes
- Improved IPI documentation
- Documentation updates
- Build flow fixes
- Public LTX files for use with hdk examples AFIs
Release 1.3.0 (See ERRATA for unsupported features)
- FPGA initiated read/write over PCI (PCI-M)
- Redesigned Shell - improved the shell design to allow more complex place and route designs to meet timing
- Expanded DMA support
- Improved URAM utilization
- Improved AXI Interface checking
- New customer examples/workflows: IP Integrator, VHDL and GUI
- SDAccel preview is accepting developers - See README registration
During July, All AFIs created with previous HDK versions will no longer correctly load on an F1 instance, hence a fpga-load-local-image command executed with an AFI created prior to 1.3.0 will return an error and not load. Watch the forum for additional announcements.
The following major features are included in this HDK release:
- The floorplan has been enhanced to enable more optimal CL designs through better timing closure and reduced congestion at the CL to Shell interface.
- New Shell Stable: v071417d3
- AWS_Shell_Interface_Specification.md has been updated. See cl_ports.vh for the updated port list
- DCP for the latest shell v071417d3. AWS Shell DCP is stored in S3 and fetched/verified when
hdk_setup.shscript is sourced.
- DMA functionality has been enhanced to allow DMA transactions of up to 1MB.
- Multi-queue in each direction is now supported
- The DMA bus toward the CL is multiplexed over sh_cl_dma_pcis AXI4 interface so the same address space can be accessed via DMA or directly via PCIe AppPF BAR4
- DMA usage is covered in the new CL_DRAM_DMA example RTL verification/simulation and Software
- A corresponding AWS Elastic DMA (EDMA) driver is provided.
- EDMA Installation Readme provides installation and usage guidelines
- See Kernel_Drivers_README for more information on restrictions for this release
- The PCI-M interface is fully supported for CL generated transactions to the Shell.
- Restrictions on URAM have been updated to enable 100% of the URAM with a CL to be utilized. See documentation on enabling URAM utilization: URAM_options
- Vivado graphical design canvas and project based flow is now supported. This flow allows developers to create CL logic as either RTL or complex subsystems based on an IP centric block diagram. Prior experience in RTL or system block designs is recommended. The IP Integrator and GUI Vivado workflow enables a unified graphical environment to guide the developer through the common steps to design, implement, and verify FGPAs. To get started, start with the README that will take you through getting started steps and documents on IPI
- See Build_Scripts
- CL designs in VHDL are fully supported.
See example for more details CL_HELLO_WORLD_VHDL
- Protocol checks have been added to the CL-Shell interface to detect and report CL errors for enhanced CL debugging.
- Transaction timeout values on the CL-Shell interface have been increased to allow for longer CL response times.
- See Shell_Interface_Specification
- The FPGA Development AMI includes Vivado 2017.1 SDX
- Get the 1.3.0+ AMI by selecting the version from the marketplace.
- Older Vivado versions will not be supported
- Synchronous (default) mode for fpga-load-local-image and fpga-clear-local-image. For example, in synchronous mode (default) fpga-load-local-image will wait for the AFI to transition to the "loaded" state, perform a PCI device remove and recan in order to expose the unique AFI Vendor and Device Id, and display the final state for the given FPGA slot number. Asynchronous operation is preserved with the "-A" option to both fpga-load-local-image and fpga-clear-local-image.
- The corresponding fpga_mgmt_load_local_image_sync and fpga_mgmt_clear_local_image_sync are provided by the fpga_mgmt library for use in C/C++ programs.
- The HDK and SDK are designed for Linux environment and has not been tested on other platforms
- First installation of AWS FPGA SDK requires having gcc installed in the instance server. If that's not available, try
sudo yum update && sudo yum group install "Development Tools" - The HDK build step requires having Xilinx's Vivado tool and Vivado License Management running. Tools and licenses are provided with AWS FPGA Developer AMI at no additional cost
- This release is tested and validated with Xilinx 2017.1 SDX (Vivado)
- Developers that choose to not use the developer AMI in AWS EC2, need to have Xilinx license 'EF-VIVADO-SDX-VU9P-OP' installed on premises. For more help, please refer to On-premise licensing help
- Vivado XSIM RTL simulator supported by the HDK
- MentorGraphic's Questa RTL simulator supported by the HDK (but requires a purchase of separate license from MentorGraphics)
- Synopsys' VCS RTL simulator supported by the HDK (but requires a purchase of separate license from Synopsys)
The HDK and SDK in the development kit have different licenses. SDK is licensed under open source Apache license and HDK is licensed under Amazon Software License. Please refer to HDK License and SDK License.
**Q: How do I know which HDK version I have on my instance/machine? **
Look for hdk_version
**Q: How do I know what my Shell Version is? **
The Shell Version of an instance is available through the FPGA Image Management tools. See the description of fpga-describe-local-image for details on retrieving the shell version from an instance.
**Q: How do I know what version of FPGA Image management tools are running on my instance? **
The FPGA Image management tools version is reported with any command executed to those tools. See the description of fpga-describe-local-image for details on the tools version identification.
Q: How do I update my design with this release?
- Start by either cloning the entire GitHub structure for the HDK release or downloading new directories that have changed. AWS recommends an entire GitHub clone to ensure no files are missed
- Update the CL design to conform to the new AWS_Shell_Interface_Specification
- Follow the process for AFI generation outlined in aws-fpga/hdk/cl/examples/readme.md
- Update FPGA Image Management Tools to the version included in aws-fpga/sdk/management
Q: How do I get support for this release?
The AWS Forum FPGA Development provides an easy access to Developer support. The FPGA development user forum is the first place to go to post questions, suggestions and receive important announcements. To gain access to the user forum, please go to https://forums.aws.amazon.com/index.jspa and login. To be notified on important messages, posts you will need to click the “Watch Forum” button on the right side of the screen.
**Q: How do I know which HDK release I am working with? **
See the release notes at the top of the GitHub directory to identify the version of your GitHub clone.
- AWS SDK API
aws ec2 describe-fpga-imagesreleased. See describe-fpga-images document for details on how to use this API. Requires Developer AMI 1.2.4 or awscli upgrade:pip install --upgrade --user awscli - Fix cl_dram_dam debug probes (.ltx) generation in build scripts
- Fixed bugs with DMA in the simulation model and testbench
- New Errata
- Added debug probes (.ltx) generation to build scripts
- Fixed a bug with the simulation model that fixed the AXI behavior of wlast on unaligned address
- Added timeout debug documentation
- Expanded clock recipes
- Virtual JTAG documentation updates
- Reduced DCP build times by 13% (34 mins) for cl_dram_dma example by adding an option to disable virtual jtag
- Included encryption of .sv files for CL examples
- Updated CL example build scripts with Prohibit URAM sites
- EDMA Performance improvments
- Expanded EC2 Instance type support
- CL Examples @250Mhz (Clock recipe A1)
- Option to exclude Chipscope (Virtual JTAG) from building CL examples (DISABLE_VJTAG_DEBUG)
The following major features are included in this HDK release:
- New Shell Stable: 0x04151701: ./hdk/common/shell_v04151701
- cl_ports.vh have the updated port list
- AWS_Shell_Interface_Specification.md has been updated
- Updated the xdc timing constrains under constraints to match the new interfaces
- Updated CL HELLO WORLD example to use the new cl_ports.vh
- DCP for the latest shell v04151701. AWS Shell DCP is stored in S3 and fetched/verified when
hdk_setup.shscript is sourced.
- The DMA bus toward the CL is multiplexed over sh_cl_dma_pcis AXI4 interface so the same address space can be accessed via DMA or directly via PCIe AppPF BAR4
- DMA usage is covered in the new CL_DRAM_DMA example RTL verification/simulation and Software
- A corresponding AWS Elastic DMA (EDMA) driver is provided.
- EDMA Installation Readme provides installation and usage guidlines
- The initial release supports a single queue in each direction
- DMA support is in Beta stage with a known issue for DMA READ transactions that cross 4K address boundaries. See Kernel_Drivers_README for more information on restrictions for this release
-
- Usage covered in new CL_DRAM_DMA example
- A corresponding AWS EDMA driver is provided under /sdk/linux_kernel_drivers/edma
- EDMA Installation provides installation and usage guidlines
- The initial release supports a single user-defined interrupt
- File content defined in AFI Manifest
- AFI_Manifest.txt is created automatically if the developer is using the aws_build_dcp_from_cl.sh script
- PCI Vendor ID and Device ID are part of the manifest
- Shell Version is part of the manifest
- The Manifest.txt file is required for AFI generation
- All the examples and documentations for build include the description and dependency on the Manifest.txt
- All the Shell/CL interfaces running off clk_main_a0, and no longer required to be 250Mhz.
- The default frequency using the HDK build flow for
clk_main_a0is 125Mhz as specified in recipe number A0. Allowing CL designs to have flexible frequency and not be constrained to 250Mhz only. All CL designs must include the recipe number in the manifest.txt file in order to generate an AFI. - All xdc scripts have been updated to clk_main_a0 and to reference a table with the possible clocks’ frequencies combinations
- Updated CL_HELLO_WORLD and CL_DRAM_DMA examples to use the
clk_main_a0
Additional tunable auxiliary clocks are generated by the Shell and fed to the CL. The clocks frequencies are set by choosing a clock recipe per group from a set of predefined frequencies combination in clock recipes table
- Clock frequency selection is set during build time, and recorded in the manifest.txt (which should include the clock_recipe_a/b/c parameters)
- Clock frequency programming in the FPGA slot itself occurs when the AFI is loaded. The list of supported frequencies is available here
- See AWS_Shell_Interface_Specification for details on the clocking to the CL
- See AFI Manifest for details on the AFI manifest data
- xdc is automatically updated with the target frequency (WIP)
** The AppPF now has 4 different PCIe BARs:**
- BAR0 and BAR1 support 32-bit access for different memory ranges of the CL through separate AXI-L interfaces
- BAR2 is used exclusively for the DMA inside the Shell and MSI-X interrupt tables
- BAR4 expanded to 128GiB to cover all external DRAM memory space
** ManagementPF added additional PCIe BARs:**
- BAR2 is used for Virtual JTAG
- BAR4 is used for SDAccel Management (WIP)
- AWS Shell Interface Specification covers these changes in detail
- AWS FPGA PCIe Memory Map covers the address map details
- The FPGA PCI library provides simple APIs to take advantage of these BARs
** MgmtPF and AppPF are now represented as different PCIe devices in F1 instances:**
- Each FPGA Slot will occupy two PCIe buses, one for AppPF and one for MgmtPF
- BAR4 addressing space enables a CL to fully map FPGA card DRAM into the AppPF address space. AppPF BAR4 is now a 128GB BAR
- AWS Shell Interface Specification covers these changes in detail
- AWS FPGA PCIe Memory Map covers the address map in detail
- Wider access provides higher bandwidth DMA and host to FPGA access
- Instance CPU can now burst full 64-byte write burst to AppPF PCIe BAR4 if mapped as Burstable (a.k.a WC: WriteCombine) (WIP)
- pci_poke_burst() and pci_poke64() calls were added to fpga_pci library to take advantage of this
- CL_DRAM_DMA and CL_HELLO_WORLD examples support for a wider access was added
- Large inbound transaction going to AppPF PCIe BAR4 will be passed onward to the CL
- Large inbound transactions going to the other BARs will be split by the Shell to multiple 32-bit accesses, and satisfy AXI-L protocol specification.
- Additional error conditions detected on the CL to Shell Interface and reported through fpga-describe-image tool
- See AWS Shell Interface Specification for more details
- FPGA Management Tool metrics output covers the additional error handling details
- The AXI buses between Shell and CL support an expanded number of AXI ID bits to allow for bits to be added by AXI fabrics See AWS Shell Interface Specification for more details
- New metrics for monitoring the Shell to CL are available from the AFI Management Tools.
- See fpga mgmt tools readme for more details
- Added CL capability to present virtual LEDs and push virtual DIP switches indications to the CL, set and read by FPGA Management Tools and without involving CL logic, providing the developer an environment similar to developing on local boards with LED and DIP switches
- See new commands in FPGA Image Tools for description of the new functionality
- CL_HELLO_WORLD example includes some logic to set LED and adjust according to vDIP
- See AWS Shell Interface Specification for more details
- The Shell has the capability for supporting CL integrated Xilinx debug cores like Virtual I/O (VIO) and Integrated Logic Analyzer (ILA) and includes support for local/remote debug by running XVC
- Virtual_JTAG_XVC describes how to use Virtual JTAG from linux shell
- cl_debug_bridge module was added to HDK common directory
- Support for generating .ltx files after
create-fpga-imagewas added. .ltx file is required when running interactive ILA/VIO debug (WIP) - Build tcl and xdc includes the required changes to enable Virtual JTAG
- See CL_DRAM_DMA for examples on using Virtual JTAG and XVC for debug
- Example Summary Table covers which CL capabilities is demonstrated in each example
- Matching the new Shell/CL interface
- Add support for 32-bit peek/poke via ocl_ AXI-L bus
- Virtual JTAG support with Xilinx ILA and VIO debug cores
- Demonstrate the use of Virtual LED and Virtual DIPSwitch
- Runtime software examples, leveraging fpga_pci and fpga_mgmt C-libraries
- Updated PCIe Vendor ID and Device ID
- See CL HELLO WORLD readme for more details
- Mapping AppPF PCIe BAR4 to DRAM
- Using DMA to access same DRAM
- Using SystemVerilog Bus constructs to simplify the code
- Demonstrate the use of User interrupts
- Demonstrate the use of bar1_ AXI-L bus
- Includes Runtime C-code application under CL_DRAM_DMA software
- See CL_DRAM_DMA README
- The Software Programmer View document is added to explain the various ways a linux user-space application can work with AWS FPGA Slots
- The C-libraries are simplifying and adding more protections from developer’s mistakes when writing a runtime C-application
- Fpga_mgmt.h cover the APIs for calling management functions
- Fpga_pcie.h covers the API for access the various PCI memory spaces of the FPGA
- CL_HELLO_WORLD and CL_DRAM_DMA examples updated to use these libraries.
- Included Vivado encryption key file for VHDL
- Added VHDL-specific line in
encrypt.tclreference files - Developer would need to add
read_vhdlincreate_dcp_from_cl.tcl
- See FPGA Management Tools for more details
- The FPGA Development AMI includes Vivado 2017.1
- Older Vivado versions will not be supported
- Updated documentation in /sdk/SDAccel (NA)
- OpenCL runtime HAL for supporting SDAccel and OpenCL ICD in /sdk/userspace (NA)
- SDAccel build post-processing to register SDAccel xcl.bin as AFI. (NA)
- Developers can simply call `include "unused_BUS_NAME_template.inc" for every unused interface
- List of potential files to include is available in
$HDK_SHELL_DIR/design/interfaces/unused\* - cl_hello_world.sv and cl_dram_dma.sv provide examples (at the each of each file)
hdk_setup.shcompares between the list of Vivado versions supported by the HDK and the installed vivado versionshdk_setup.shwould automatically choose the Vivado version from the available binaries in AWS FPGA Developer's AMI
- Change address decoding to ROW_COL_INTLV mode
- Enable auto precharge on COL A3