#AWS FPGA - Frequently Asked Questions
Q: How is developing a FPGA design for the cloud different from the common practice outside the cloud?
AWS designed its FPGA instances to provide a developer experience with ease of use and as similar as possible to on-premises development environment with the following differences (advantages):
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Developers don’t need to purchase / design / bringup or debug the physical hardware where the FPGA is hosted, nor the platform/server hardware: all the hardware is verified, monitored, and maintained by AWS.
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AWS provides an FPGA Developer AMI that contains Xilinx Vivado development environment, with all the needed licenses. By using the FPGA developer AMI developers have a choice to a wide range of instance (different CPU and Memory configuration) allowing developers to optimize their development flow.
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AWS provides cloud based debug tools: Virtual JTAG which is equivalent to debug using JTAG with on-premises development, and Virtual LED together with Virtual DIP Switch emulation the LED and DIP switches in typical development board.
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For developers who want to develop on-premises, Xilinx provides an on-premises license that matches all the needed components needed to be licensed for F1 development on premises.
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The developers' output is a Design Checkpoint (DCP) and not an FPGA bitstream: The FPGA bitstream is actually generated by AWS after the developer submits the DCP.
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The FPGA in AWS platforms are loaded using "Partial Reconfiguration" mode.
Q: What is the extra time needed to develop on AWS FPGA instances compared with on-premises development?
There are two parts to answer this question:
- A one-time knowledge ramp how to use AWS and FPGA on AWS:
For developers that are familiar with AWS, there is almost no additional time to get right into F1 development environment, as long as the documentation and guidances in the FPGA HDK/SDK are followed.
For developers who are new to AWS, there is typically a one to two days ramp on AWS general topics such as launching EC2 instance, setting up S3 storage and its permissions, using AWS console, etc… For new developers to AWS, we recommend to start with the FPGA Developer Forum
- On-going development flow:
Once developers complete their DCP, they submit the design through an AWS EC2 API to create the Amazon FGPA Image (aka AFI, this API call can take a few hours to complete, and the status of the process is reported in the S3 log bucket provides by the developers. AWS is working to improve the turn time of AFI generation.
Q: What new skill sets will be required from an FPGA developer in the cloud?
As AWS has taken all the non-differentiating, heavy lifting of hardware design, debug and implementation of PCIe tuning, FPGA I/O assignment, power, thermal management, and runtime health monitoring. Therefore AWS FPGA developers can focus on their own differentiating logic, instead of spending time on hardware bringup/debug and maintenance.
On the business side, AWS Marketplace (MP) provides FPGA developers the opportunity to sell hardware accelerations to all of AWS users: Ramping on AWS MP services, capabilities and commercial opportunities are recommended knowledge for developers interested in selling their AFIs on AWS MP. Education and research institutes can use AWS MP to distribute their research work ; having access to vast amounts of free public data-sets can be of value when running research hardware accelerations on AWS.
Finally, AWS consulting and technology partners can offer their services through the AWS Partner Network to AWS users that don’t have specific FPGA development knowledge, in order to develop FPGA accelerations in the cloud by themselves.
Q: How is deployment FPGA in the cloud different compared to on-premises?
With AWS, FPGAs developers have a few advantages:
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Low entry bar: AWS FPGAs are charged on an hourly rate instead of the many thousands of dollars spent on hardware/licenses and 12+ months time it takes to design/manufacture and ship a production-ready FPGA hardware solution.
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Scalability and Elasticity: Developers can ramp up / down the number of deployed FPGAs within seconds based on offered load.
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Share: FPGA developers can share their designs easily through AWS Marketplace or APN. This is important for businesses as well as education and research use.
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AWS FPGA instances can be combined with other AWS services to create a solution pipeline or integrate an acceleration into existing customer workflows/datasets
Q: What is included in the FPGA HDK?
The HDK includes the following main components:
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Documentation for the Shell interface and other Custom Logic implementation guidelines, the Shell models needed for Custom Logic development, simulation models for the Shell, software for exercising.
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Custom Logic examples, a getting started guide for building your own Custom Logic, and examples for starting a Custom Logic Design.
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Scripts for building and submitting Amazon FPGA Image (AFI) from a Custom Logic.
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Reference software drivers to be used in conjunction with the Custom Logic examples.
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RTL Simulation models and RTL simulation.
Q: What is in the AWS Shell?
The AWS Shell is the part of the FPGA that is provided and managed by AWS: it implements the non-differentiated development and heavy lifting tasks like setting up the PCIe interface, FPGA image download, security, health monitoring, metrics and debug hooks.
Every FPGA deployed in AWS cloud includes an AWS Shell, and the developer Custom Logic (CL) interfaces with the available AWS Shell interfaces.
Q: What is an Amazon FPGA Image (AFI)?
It is the compiled FPGA code that is loaded into an FPGA in AWS for performing the Custom Logic (CL) function created by the developer. AFIs are maintained by AWS according and associated with the AWS account that created them. The AFI includes the CL and AWS FPGA Shell. An AFI ID is used to reference a particular AFI from an F1 instance.
The developer can create multiple AFIs at no extra cost, up to a defined limited (typically 100 AFIs per region per AWS account). An AFI can be loaded into as many FPGAs as needed.
Q: What regions are supported?
AWS FPGA generation and EC2 F1 instances are supported in us-east-1 (N. Virginia), us-west-2 (Oregon) and eu-west-1 (Ireland).
Q: What is the process for creating an AFI?
The AFI process starts by creating Custom Logic (CL) code that conforms to the Shell Specification. Then, the CL must be compiled using the HDK scripts which leverages Vivado tools to create a Design Checkpoint (DCP). That DCP is submitted to AWS for generating an AFI using the aws ec2 create-fpga-image API.
Use the AWS CLI describe-fpga-images API to get information about the created AFIs using the AFI ID provided by create-fpga-image, or to list available AFIs for your account. See describe-fpga-images document for details on how to use this API.
Q: Can I load an AFI on every region AWS FPGA is supported?
Yes, but you must first copy the AFI using the copy-fpga-image API. You should generate AFIs in one region and use copy to make them available in other regions. Copy preserves the Global AFI ID used to load an AFI on a EC2 instance.
Use describe-fpga-images with the --region command line option to list AFIs available in a specific region. Use FpgaImageGlobalId attribute and fpga-image-global-id filter to match AFI copies across regions.
Q: Can I share an AFI with other AWS accounts?
Yes, sharing allows accounts other than the owner account to load and use an AFI. Use modify-fpga-image-attribute API to update loadPermission attribute to grant/remove AFI load permission. AWS AFIs support two load permission types:
UserId: share AFI with specific AWS accounts using account IDs.UserGroups: only supportsallgroup to make an AFI public or private.
Use reset-fpga-image-attribute API to revoke all load permissions.
Q: Can I delete an AFI?
Yes, use delete-fpga-image to delete an AFI in a specific region. Deleting an AFI in one region does not affect AFIs in other regions.
Use delete-fpga-image carefully. Once all AFIs of the same global AFI ID are deleted, the AFIs cannot be recovered from deletion. Review IAM policy best practices to restrict access to this API.
Q: Can I bring my own bitstream for loading on an F1 FPGA?
No. There is no mechanism for loading a bitstream directly onto the FPGAs of an F1 instance. All Custom Logic is loaded onto the FPGA by calling $ fpga-local-load-image tool at AWS FPGA SDK.
Developers create an AFI by creating a Vivado Design Checkpoint (DCP) and submitting that DCP to AWS using aws ec2 create-fpga-image API. AWS creates the AFI and bitstream from that DCP and returns a unique AFI ID referencing that AFI.
Q: Can I generate my bitstream on my own desktop/server (not on AWS cloud)?
Yes, on-premises tools can be used to develop the Design Checkpoint needed for creating an AFI. The developer needs to download AWS FPGA HDK from GitHub and run on any local machine.
If a developer uses local tools and license, please check the supported versions of Vivado for the exact Xilinx Vivado tool version supported by the HDK. Developers have access to Xilinx Vivado running in the AWS by using the FPGA Developer AMI on AWS Marketplace
Q: Is there a “best practice” system template?
AWS prefers not to limit developers to a specific template in terms of how we advise to use AWS FPGAs. A good overview of these interfaces can be found here
Q: Do I need to get a Xilinx license to generate an AFI?
If you decide to use the FPGA Developer AMI on AWS Marketplace, Xilinx licenses for simulation, encryption, SDAccel and Design Checkpoint generation are included at no additional cost.
If you want to run using other methods or on a local machine, you will need to obtain any necessary licenses, specifically you will need to have setup the appropriate Xilinx Vivado license. For more details, please refer to On-premises licensing help
Q: Does AWS provide physical FPGA boards for on-premises development?
No. AWS supports a cloud-only development model and provides the necessary elements for doing 100% cloud development including Virtual JTAG (Vivado ChipScope), Virtual LEDs and Virtual DIP-switch. No development board is provided for on-premises development.
Q: Do I need to design for a specific power envelope?
Yes, the design scripts provided in the HDK include checks for power consumption that exceeds the allocated power for the Custom Logic (CL) region. Developers do not need to include design considerations for DRAM, Shell, or Thermal. AWS includes the design considerations for those as part of providing the power envelop for the CL region.
Q: What IP blocks are provided in the HDK?
The HDK includes IP for AWS Shell and DRAM interface controllers. Inside the Shell, there is a PCIe interface, DMA Engine, and one DRAM interface controller. These blocks are only accessible via the AXI interfaces defined by the Shell-Custom Logic interface. The HDK provides additional IP blocks for the other DRAM interfaces, enabling up to 3 additional DRAM interfaces instantiated by the developer in the Custom Logic region.
Note * future versions of the HDK will include IP for the FPGA Link interface.*
Q: Can I use other IP blocks from Xilinx or other 3rd parties?
Yes. Developers are free to use any IP blocks within the Custom Logic region. Those can be 3rd party IPs or IP available in the Vivado IP catalog.
Note * AWS supports only the IP blocks contained in the HDK.*
Q: What do I need to get started on building accelerators for FPGA instances?
Getting started requires downloading the latest HDK and SDK from the AWS FPGA GitHub repository. The HDK and SDK provide the needed code and information for building FPGA code. The HDK provides all the information needed for developing an FPGA image from source code, while the SDK provides all the runtime software for managing the Amazon FPGA Image (AFI) loaded into the F1 instance FPGA.
Typically, FPGA development process requires a simulator to perform functional test on the source code, and a Vivado tool set for synthesis of source code into compiled FPGA code. The FPGA Developer AMI provided by AWS includes the complete Xilinx Vivado tools for simulation (XSIM) and synthesis of FPGA.
Q: How do I develop accelerator code for an FPGA in an F1 instance?
Start with the Shell interface specification. This document describes the interface between Custom Logic and the AWS Shell. All Custom Logic for an accelerator resides within the Custom Logic region of the F1 FPGA.
The HDK README walks the developer through the steps to build an FPGA image from one of the provided examples as well as starting a new code.
Q: Are there examples for getting started on accelerators?
Yes, examples are in the examples directory:
The cl_hello_world example is an RTL/Verilog simple example to build and test the Custom Logic development process, it does not use any of the external interfaces of the FPGA except the PCIe to "peek" and "poke" registers in the memory space of the CL inside the FPGA.
The cl_dram_dma example provides expanded features that demonstrates the use and connectivity for many of the Shell/CL interfaces and functionality.
Q: How do I get access to AWS FPGA Developer AMI?
The FPGA Developer AMI on AWS Marketplace is avaliable on AWS Marketplace.
Q: Where do I go to for support?
For F1 related development support issues, we encourage you to use the AWS FPGA Developer Forum to post questions, suggestions and receive important announcements. To be notified on important messages and new posts, click the “Watch Forum” button on the right side of the screen. For general instance or AWS support issues, please use the avaliable AWS support options avaliable for AWS users.
Q: Is there any software I need on my F1 instance that will use the AFI?
To be able to manage and monitor the F1 FPGAs it is required to install the FPGA Management Tool set. This software manages loading and clearing AFIs for the instance FPGAs, it also allows developers to retrieve FPGAs status from within the instance. Developers will need to include in their F1 AMI all the drivers and runtime libraries needed for their specific FPGA application.
Typically, you will not need the HDK nor any Xilinx Vivado tools on an F1 instance that is using prebuilt AFIs; unless, you want to do in-field debug using Vivado's ChipScope (Virtual JTAG).
Q: How do I update the AWS CLI to use the latest EC2 commands to manage my AFI's?
On the FPGA Developer AMI, you can update your AWS CLI for all users using the command:
sudo pip install awscli --upgrade
If You want to upgrade the AWS CLI for just your user, you can run the following:
pip install awscli --upgrade --user
The AWS CLI documentation page shows steps to update the AWS CLI. We recommend using the latest available version to be able to use the expanding list of commands that we add.
Q: What does publishing my AFI/AMI to AWS Marketplace enables?
FPGA Developers can share or sell their AFI/AMI using the AWS Marketplace to other AWS users. Once in Marketplace, AWS users can launch an F1 instance with that AFI/AMI combination with the 1-click deployment feature. Marketplace Sellers can take advantage of the Management Portal to better build and analyze their business, using it to drive marketing activities and customer adoption. The metering, billing, collections, and disbursement of payments are managed by AWS, allowing developers to focus on marketing their solution. Please check out AWS Marketplace Tour for more details on how to become an AWS Marketplace seller, how to set pricing and collect metrics.
Q: How can I publish my AFI to AWS Marketplace?
First, you need to register as a Marketplace Seller. In parallel you should create an AMI that includes the drivers and runtime libraries needed to use your AFI. Finally, follow the standard flow to publish your AMI on AWS marketplace, providing the associated AFI IDs. In other words, AFIs are not published directly on AWS marketplace, rather AFI(s) should be associated with an AMI that gets published.
Q: Do AWS Marketplace customers see FPGA source code or a bitstream?
Neither, no FPGA internal design code is exposed. AWS Marketplace customers that pick up an AMI with one or more AFIs associated with it will not see any source code nor bitstream. Marketplace customers actually have permission to use the AFI but no permission to see its code. The only reference to the AFI is through its unique AFI ID. The AMI would call fpga-local-load-image with the correct AFI ID for that Marketplace offering, which will result in AWS loading the AFI into the FPGA in a sideband channel and without sending the AFI code through the customer's instance.
Q: What OS can run on the F1 instance?
Amazon Linux 2016.09 and CentOS 7.3 are supported and tested on AWS EC2 F1 instance. Developers can utilize the source code in the SDK directory to compile other variants of Linux for use on F1. Windows OSs are not supported on F1.
Q: What are the interfaces between the F1 instance host CPU and the FPGAs?
There are two types of interfaces from the instance host CPU to the FPGAs:
The first is the FPGA Image Management Tools. These APIs are detailed in the SDK portion of the GitHub repository. FPGA Image Management Tools include APIs to load, clear, and get status of the FPGA.
The second type of interface is direct address access to the Application PCIe Physical Functions (PF) of the FPGA. There is no API for this access. Rather, there is direct access to resources in the Custom Logic (CL) region or Shell that can be accessed by software written on the instance. For example, the ChipScope software (Virtual JTAG) uses address space in a PF to provide FPGA debug support. Developers can create any API to the resources in their CL. See the Shell Interface Specification for more details on the address space mapping as seen from the instance.
Q: Can I integrate the FPGA Image Management Tools in my application?
Yes, In addition to providing the FPGA Management Tools as linux shell commands, the SDK Userspace directory includes files in the include and hal to integrate the FPGA Management Tools into the developer's application(a) and avoid calling linux shell commands.
Q: Is the FPGA address space exposed to the instance Linux kernel or userspace?
Both. The FPGA PCIe memory address space can be mmap() to both kernel and userspace, with userspace being the recommended option for fault isolation.
Q: How do I change what AFI is loaded in an FPGA?
Changing the AFI loaded in an FPGA is done using the fpga-clear-local-image and fpga-load-local-image APIs from the FPGA Image Management tools. The fpga-load-local-image command takes the AFI ID and requests it to be programmed into the identified FPGA. The AWS infrastructure manages the actual FPGA image and programming of the FPGA using Partial Reconfiguration capabilities of the FPGA. The AFI image is not stored in the F1 instance nor AMI. The AFI image can’t be read or modified by the instance as there isn't a direct access to programming the FPGA from the instance. A user may call fpga-load-local-image at any time during the life of an instance, and may call fpga-load-local-image any number of times.
Q: I can not see the new AFI after fpga-load-local-image call returned?
The fpga-load-local-image call will initiate the loading of the AFI, however a successful return of fpga-load-local-image is just an indication that the loading process has started. The developer should poll on the status of the AFI via fpga-describe-local-image until the status would show loaded.
Q: What will happen to the FPGA state after my instance stops/terminates/crashes?
The AWS infrastructure scrubs FPGA state on termination of an F1 instance and any reuse of the FPGA hardware. Scrubbing includes both FPGA internal state and the contents of DRAM attached to the FPGA. Additionally, users can call the fpga-clear-local-image command from the FPGA Image Management tools to force a clear of FPGA and DRAM contents while the instance is running.
Q: How do the FPGAs connect to the x86 CPU?
Each FPGA in F1 is connected to the instance CPU via a x16 PCIe Gen3 interface. Physical Functions (PF) within the FPGA are directly mapped into the F1 instance. Software on the instance can directly access the address in the PF to take advantage of the high performance PCIe interface.
Q: Can the FPGAs on F1 directly access Amazon’s network?
No. The FPGAs do not have direct access to the network. The FPGAs communicate via PCIe to the instance CPU, where the Enhanced Networking (ENA) drivers run. ENA provides a high-performance, low-latency virtualized network interface suitable for data movement to the F1 instance. See the EC2 ENA driver documentation for more details.
The developer can take advantage of a userspace polling-mode driver framework like DPDK, to implement s fast and low-latency copy between the network and FPGAs, with the data most probably being stored in the x86 LastLevelCache (LLC).
Q: Can the FPGAs on F1 directly access the SSDs in the instance?
No. The FPGAs do not have direct access to the SSDs on F1. The SSDs on F1 are high-performance, NVMe SSD devices. The developer can take advantage of a userspace polling-mode driver framework like SPDK, to implement fast and low-latency copy between the NVMe SSD and the FPGA, with the data most probably being stored in the x86 LastLevelCache (LLC).
Q: Which HDL languages are supported?
For RTL level development: Verilog and VHDL are both supported in the FPGA Developer AMI and in generating a Design Checkpoint. The Xilinx Vivado tools and simulator support mixed mode simulation of Verilog and VHDL. The AWS Shell is written in Verilog. Support for mixed mode simulation may vary if developers use other simulators. Check your simulator documentation for Verilog/VHDL/System Verilog support.
Q: Is OpenCL and/or SDAccel Supported?
Yes. Please review the SDAccel README to get started
Q: Can I use High Level Synthesis(HLS) Tools to generate an AFI?
Yes. Vivado HLS and SDAccel are directly supported through the FPGA Developer AMI. Any other HLS tool that generates compatible Verilog or VHDL for Vivado input can also be used for writing in HLS.
Q: What RTL simulators are supported?
The FPGA Developer AMI has built-in support for the Xilinx XSIM simulator. All licensing and software for XSIM is included in the FPGA Developer AMI when launched.
Support for other simulators is included through the bring-your-own license in the FPGA Developer AMI. AWS tests the HDK with Synopsys VCS, Mentor Questa/ModelSim, and Cadence Incisive. Licenses for these simulators must be acquired by the developer and are not available with AWS FPGA Developer AMI.
Q: What FPGA is used in AWS EC2 F1 instance?
The FPGA for F1 is the Xilinx Ultrascale+ VU9P device with the -2 speed grade. The HDK scripts have the compile scripts needed for the VU9P device.
Q: What is FPGA Direct and how fast is it?
FPGA Direct is FPGA to FPGA low latency high throughput peer communication through the PCIe links on each FPGA, where all FPGAs shared the same memory space. The PCIe BAR space in the Application PF (see Shell Interface specification for more details) allows the developer to map regions of the Custom Logic, such as external DRAM space, to other FPGAs. The implementation of communication protocol and data transfer engine across the PCIe interface using FPGA direct is left to the developer.
Q: What is FPGA Link and how fast is it?
FPGA Link is based on 4 x 100Gbps links on each FPGA card. The FPGA Link is organized as a ring, with 2 x 100Gbps links to each adjacent card. This enables each FPGA card to send/receive data from an adjacent card at 200Gbps speeds. Details on the FPGA Link interface will be provided in the Shell Interface specification when available.
Q: What protocol is used for FPGA link?
The FPGA link is a generic raw streaming interface, no transport protocol is provided for it by AWS. It is expected that developers would take advantage of standard PCIe protocol, Ethernet protocol, or Xilinx's (reliable) Aurora protocol layer for this interface.
Details on the Shell Interface to the FPGA Link IP blocks are provided in the Shell Interface specification when available.
Q: What clock speed does the FPGA utilize?
The FPGA Shell provides a selectable frequency clocks (up to 8 clocks) from the Shell to the Custom Logic (CL) region, please refer to the Shell Interface Specification and the available clock recipe for the available clocks and frequency options.
*Note: All the AXI interfaces between Shell and CL are synchronous to clk_main_a0, which has a default of 125Mhz using A0 clock recipe.
Q: What memory is attached to the FPGA?
Each FPGA on F1 has 4 x DDR4 interfaces, each is 72bits wide (64bit data). Each DRAM interface has 16GiB of RDRAM attached. This yields 64GiB of total DRAM memory available localy to each F1 FPGA.
Q: What FPGA debug capabilities are supported?
AWS FPGA instances offer four debugging utilities:
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The first is the Virtual JTAG included in the AWS Shell. It provides an equivalent function to a physical JTAG debugger with exception that it's an emulated JTAG-over-PCIe. Based on Xilinxs' ChipScope circuit, the Virtual JTAG is pre-integrated with AWS Shell and available to the instance over memory-mapped PCIe space. The driver is included with the F1 SDK.
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The second is the usage metrics available through the FPGA Image Management tools. The
fpga-describe-local-imagecommand allows the F1 instance to query metrics from the Shell and Shell to Custom Logic (CL) interfaces. See Shell Interface specification and FPGA Image Management tools for more information on supported metrics. -
Virtual LEDs. An emulated LEDs that represents the status of 16 different LEDs (On/Off). The LED status is read through the PCIe management Physical Function (PF).
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Virtual DIP Switch. An emulated DIP Switch represents a generic 16 binary DIP switch that is passed to the CL.
Refer to Virtual JTAG readme for more details.
Q: Do I need to interface to the AWS Shell?
Yes. The only way to interface to PCIe and the instance CPU is using the AWS Shell. The AWS Shell is included with every FPGA. There is no option to run the F1 FPGA without a Shell. The Shell takes care of the non-differentiating heavy lifting tasks like PCIe tuning, FPGA I/O assignment, power, thermal management, and runtime health monitoring.
Q: Is a simulation model of the AWS Shell available?
Yes. The HDK includes a simulation model for the AWS shell. See the HDK common tree for more information on the Shell simulation model.
Q: What resources within the FPGA does the AWS Shell consume?
The Shell consumes about 20% of the FPGA resources, and that includes the PCIe Gen3 X16, DMA engine, DRAM controller interface, ChipScope (Virtual JTAG) and other health monitoring and image loading logic. No modifications to the Shell or the partition pins between the Shell and the Custom Logic are possible by the FPGA developer.
Q: Why do I see error “vivado not found” while running hdk_setup.sh?
This is an indication that Xilinx Vivado tool set are not installed. Try installing the tool if you are working on your own environment, or alternative use AWS FPGA Development AMI available on AWS Marketplace, which comes with pre-installed Vivado toolset and license.
Q: Why did my example job run and die without generating a DCP file?
The error message below indicates that you ran out of memory. Restart your instance with a different instance type that has 32GiB or more.
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:06:26 ; elapsed = 00:08:59 . Memory (MB): peak = 4032.184 ; gain = 3031.297 ; free physical = 1285 ; free virtual = 1957 /opt/Xilinx/Vivado/2016.3/bin/loader: line 164: 8160 Killed "$RDI_PROG" "$@" Parent process (pid 8160) has died. This helper process will now exit
Q: Why am I getting an error: A valid license was not found for feature 'XYZ' and/or device 'XYZ' from Xilinx Vivado while trying to build by dcp/running my examples?
For On Premise runs:
You would need a valid on premise license provided by Xilinx.
For runs using the FPGA Developer AMI:
NOTE:
- The license included on FPGA Developer AMI Versions 1.3.0_a and earlier expires on October 31 2017.
- If you see the above error, please update to FPGA Developer AMI Version 1.3.3 or later.
- All FPGA Developer AMI Versions 1.3.0_a and earlier will be deprecated once Version 1.3.3 is released.
- If you are using the FPGA Developer AMI Version 1.3.3 or later, please check if the environment variable
XILINXD_LICENSE_FILEis set to/opt/Xilinx/license/XilinxAWS.lic- If you still face the above error, please contact us on the forums and we'd be happy to help further.
Q: Why does Vivado in GUI mode show up blank ? or Why does Vivado in GUI mode show up as an empty window?
We have seen this issue when running RDP in 32 bit color mode where Vivado shows up as a blank window. Please modify RDP options to choose any color depth less than 32 bit and try re-connecting.