ARM64: Redundant movs done for zero extend the register #35254
Labels
arch-arm64
area-CodeGen-coreclr
CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI
optimization
Milestone
Redundant movs are done to zero the upper 32-bit of register, but if they are done after
ldr
, we can eliminate them.In framework libraries code, found 1098 such instructions that can eliminated.
Details :
redundant-mov-3.txt
category:cq
theme:optimization
skill-level:intermediate
cost:small
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