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codegencommon.cpp
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codegencommon.cpp
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// Licensed to the .NET Foundation under one or more agreements.
// The .NET Foundation licenses this file to you under the MIT license.
// See the LICENSE file in the project root for more information.
/*XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XX XX
XX Code Generator Common: XX
XX Methods common to all architectures and register allocation strategies XX
XX XX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
*/
// TODO-Cleanup: There are additional methods in CodeGen*.cpp that are almost
// identical, and which should probably be moved here.
#include "jitpch.h"
#ifdef _MSC_VER
#pragma hdrstop
#endif
#include "codegen.h"
#include "gcinfo.h"
#include "emit.h"
#ifndef JIT32_GCENCODER
#include "gcinfoencoder.h"
#endif
/*****************************************************************************/
const BYTE genTypeSizes[] = {
#define DEF_TP(tn, nm, jitType, verType, sz, sze, asze, st, al, tf, howUsed) sz,
#include "typelist.h"
#undef DEF_TP
};
const BYTE genTypeAlignments[] = {
#define DEF_TP(tn, nm, jitType, verType, sz, sze, asze, st, al, tf, howUsed) al,
#include "typelist.h"
#undef DEF_TP
};
const BYTE genTypeStSzs[] = {
#define DEF_TP(tn, nm, jitType, verType, sz, sze, asze, st, al, tf, howUsed) st,
#include "typelist.h"
#undef DEF_TP
};
const BYTE genActualTypes[] = {
#define DEF_TP(tn, nm, jitType, verType, sz, sze, asze, st, al, tf, howUsed) jitType,
#include "typelist.h"
#undef DEF_TP
};
void CodeGenInterface::setFramePointerRequiredEH(bool value)
{
m_cgFramePointerRequired = value;
#ifndef JIT32_GCENCODER
if (value)
{
// EnumGcRefs will only enumerate slots in aborted frames
// if they are fully-interruptible. So if we have a catch
// or finally that will keep frame-vars alive, we need to
// force fully-interruptible.
CLANG_FORMAT_COMMENT_ANCHOR;
#ifdef DEBUG
if (verbose)
{
printf("Method has EH, marking method as fully interruptible\n");
}
#endif
m_cgInterruptible = true;
}
#endif // JIT32_GCENCODER
}
/*****************************************************************************/
CodeGenInterface* getCodeGenerator(Compiler* comp)
{
return new (comp, CMK_Codegen) CodeGen(comp);
}
// CodeGen constructor
CodeGenInterface::CodeGenInterface(Compiler* theCompiler)
: gcInfo(theCompiler), regSet(theCompiler, gcInfo), compiler(theCompiler)
{
}
/*****************************************************************************/
CodeGen::CodeGen(Compiler* theCompiler) : CodeGenInterface(theCompiler)
{
#if defined(_TARGET_XARCH_) && !FEATURE_STACK_FP_X87
negBitmaskFlt = nullptr;
negBitmaskDbl = nullptr;
absBitmaskFlt = nullptr;
absBitmaskDbl = nullptr;
u8ToDblBitmask = nullptr;
#endif // defined(_TARGET_XARCH_) && !FEATURE_STACK_FP_X87
#if defined(FEATURE_PUT_STRUCT_ARG_STK) && !defined(_TARGET_X86_)
m_stkArgVarNum = BAD_VAR_NUM;
#endif
#if defined(UNIX_X86_ABI)
curNestedAlignment = 0;
maxNestedAlignment = 0;
#endif
regTracker.rsTrackInit(compiler, ®Set);
gcInfo.regSet = ®Set;
m_cgEmitter = new (compiler->getAllocator()) emitter();
m_cgEmitter->codeGen = this;
m_cgEmitter->gcInfo = &gcInfo;
#ifdef DEBUG
setVerbose(compiler->verbose);
#endif // DEBUG
compiler->tmpInit();
#ifdef DEBUG
#if defined(_TARGET_X86_) && defined(LEGACY_BACKEND)
// This appears to be x86-specific. It's attempting to make sure all offsets to temps
// are large. For ARM, this doesn't interact well with our decision about whether to use
// R10 or not as a reserved register.
if (regSet.rsStressRegs())
compiler->tmpIntSpillMax = (SCHAR_MAX / sizeof(int));
#endif // defined(_TARGET_X86_) && defined(LEGACY_BACKEND)
#endif // DEBUG
instInit();
#ifdef LEGACY_BACKEND
// TODO-Cleanup: These used to be set in rsInit() - should they be moved to RegSet??
// They are also accessed by the register allocators and fgMorphLclVar().
intRegState.rsCurRegArgNum = 0;
floatRegState.rsCurRegArgNum = 0;
#endif // LEGACY_BACKEND
#ifdef LATE_DISASM
getDisAssembler().disInit(compiler);
#endif
#ifdef DEBUG
genTempLiveChg = true;
genTrnslLocalVarCount = 0;
// Shouldn't be used before it is set in genFnProlog()
compiler->compCalleeRegsPushed = UninitializedWord<unsigned>();
#if defined(_TARGET_XARCH_) && !FEATURE_STACK_FP_X87
// Shouldn't be used before it is set in genFnProlog()
compiler->compCalleeFPRegsSavedMask = (regMaskTP)-1;
#endif // defined(_TARGET_XARCH_) && !FEATURE_STACK_FP_X87
#endif // DEBUG
#ifdef _TARGET_AMD64_
// This will be set before final frame layout.
compiler->compVSQuirkStackPaddingNeeded = 0;
// Set to true if we perform the Quirk that fixes the PPP issue
compiler->compQuirkForPPPflag = false;
#endif // _TARGET_AMD64_
#ifdef LEGACY_BACKEND
genFlagsEqualToNone();
#endif // LEGACY_BACKEND
// Initialize the IP-mapping logic.
compiler->genIPmappingList = nullptr;
compiler->genIPmappingLast = nullptr;
compiler->genCallSite2ILOffsetMap = nullptr;
/* Assume that we not fully interruptible */
genInterruptible = false;
#ifdef DEBUG
genInterruptibleUsed = false;
genCurDispOffset = (unsigned)-1;
#endif
}
void CodeGenInterface::genMarkTreeInReg(GenTreePtr tree, regNumber reg)
{
tree->gtRegNum = reg;
#ifdef LEGACY_BACKEND
tree->SetInReg();
#endif // LEGACY_BACKEND
}
#if CPU_LONG_USES_REGPAIR
void CodeGenInterface::genMarkTreeInRegPair(GenTreePtr tree, regPairNo regPair)
{
tree->gtRegPair = regPair;
#ifdef LEGACY_BACKEND
tree->SetInReg();
#endif // LEGACY_BACKEND
}
#endif
#if defined(_TARGET_X86_) || defined(_TARGET_ARM_)
//---------------------------------------------------------------------
// genTotalFrameSize - return the "total" size of the stack frame, including local size
// and callee-saved register size. There are a few things "missing" depending on the
// platform. The function genCallerSPtoInitialSPdelta() includes those things.
//
// For ARM, this doesn't include the prespilled registers.
//
// For x86, this doesn't include the frame pointer if codeGen->isFramePointerUsed() is true.
// It also doesn't include the pushed return address.
//
// Return value:
// Frame size
int CodeGenInterface::genTotalFrameSize()
{
assert(!IsUninitialized(compiler->compCalleeRegsPushed));
int totalFrameSize = compiler->compCalleeRegsPushed * REGSIZE_BYTES + compiler->compLclFrameSize;
assert(totalFrameSize >= 0);
return totalFrameSize;
}
//---------------------------------------------------------------------
// genSPtoFPdelta - return the offset from SP to the frame pointer.
// This number is going to be positive, since SP must be at the lowest
// address.
//
// There must be a frame pointer to call this function!
int CodeGenInterface::genSPtoFPdelta()
{
assert(isFramePointerUsed());
int delta;
delta = -genCallerSPtoInitialSPdelta() + genCallerSPtoFPdelta();
assert(delta >= 0);
return delta;
}
//---------------------------------------------------------------------
// genCallerSPtoFPdelta - return the offset from Caller-SP to the frame pointer.
// This number is going to be negative, since the Caller-SP is at a higher
// address than the frame pointer.
//
// There must be a frame pointer to call this function!
int CodeGenInterface::genCallerSPtoFPdelta()
{
assert(isFramePointerUsed());
int callerSPtoFPdelta = 0;
#if defined(_TARGET_ARM_)
// On ARM, we first push the prespill registers, then store LR, then R11 (FP), and point R11 at the saved R11.
callerSPtoFPdelta -= genCountBits(regSet.rsMaskPreSpillRegs(true)) * REGSIZE_BYTES;
callerSPtoFPdelta -= 2 * REGSIZE_BYTES;
#elif defined(_TARGET_X86_)
// Thanks to ebp chaining, the difference between ebp-based addresses
// and caller-SP-relative addresses is just the 2 pointers:
// return address
// pushed ebp
callerSPtoFPdelta -= 2 * REGSIZE_BYTES;
#else
#error "Unknown _TARGET_"
#endif // _TARGET_*
assert(callerSPtoFPdelta <= 0);
return callerSPtoFPdelta;
}
//---------------------------------------------------------------------
// genCallerSPtoInitialSPdelta - return the offset from Caller-SP to Initial SP.
//
// This number will be negative.
int CodeGenInterface::genCallerSPtoInitialSPdelta()
{
int callerSPtoSPdelta = 0;
#if defined(_TARGET_ARM_)
callerSPtoSPdelta -= genCountBits(regSet.rsMaskPreSpillRegs(true)) * REGSIZE_BYTES;
callerSPtoSPdelta -= genTotalFrameSize();
#elif defined(_TARGET_X86_)
callerSPtoSPdelta -= genTotalFrameSize();
callerSPtoSPdelta -= REGSIZE_BYTES; // caller-pushed return address
// compCalleeRegsPushed does not account for the frame pointer
// TODO-Cleanup: shouldn't this be part of genTotalFrameSize?
if (isFramePointerUsed())
{
callerSPtoSPdelta -= REGSIZE_BYTES;
}
#else
#error "Unknown _TARGET_"
#endif // _TARGET_*
assert(callerSPtoSPdelta <= 0);
return callerSPtoSPdelta;
}
#endif // defined(_TARGET_X86_) || defined(_TARGET_ARM_)
/*****************************************************************************
* Should we round simple operations (assignments, arithmetic operations, etc.)
*/
// inline
// static
bool CodeGen::genShouldRoundFP()
{
RoundLevel roundLevel = getRoundFloatLevel();
switch (roundLevel)
{
case ROUND_NEVER:
case ROUND_CMP_CONST:
case ROUND_CMP:
return false;
default:
assert(roundLevel == ROUND_ALWAYS);
return true;
}
}
/*****************************************************************************
*
* Initialize some global variables.
*/
void CodeGen::genPrepForCompiler()
{
unsigned varNum;
LclVarDsc* varDsc;
/* Figure out which non-register variables hold pointers */
VarSetOps::AssignNoCopy(compiler, gcInfo.gcTrkStkPtrLcls, VarSetOps::MakeEmpty(compiler));
// Figure out which variables live in registers.
// Also, initialize gcTrkStkPtrLcls to include all tracked variables that do not fully live
// in a register (i.e. they live on the stack for all or part of their lifetime).
// Note that lvRegister indicates that a lclVar is in a register for its entire lifetime.
VarSetOps::AssignNoCopy(compiler, compiler->raRegVarsMask, VarSetOps::MakeEmpty(compiler));
for (varNum = 0, varDsc = compiler->lvaTable; varNum < compiler->lvaCount; varNum++, varDsc++)
{
if (varDsc->lvTracked
#ifndef LEGACY_BACKEND
|| varDsc->lvIsRegCandidate()
#endif // !LEGACY_BACKEND
)
{
if (varDsc->lvRegister
#if FEATURE_STACK_FP_X87
&& !varDsc->IsFloatRegType()
#endif
)
{
VarSetOps::AddElemD(compiler, compiler->raRegVarsMask, varDsc->lvVarIndex);
}
else if (compiler->lvaIsGCTracked(varDsc))
{
VarSetOps::AddElemD(compiler, gcInfo.gcTrkStkPtrLcls, varDsc->lvVarIndex);
}
}
}
VarSetOps::AssignNoCopy(compiler, genLastLiveSet, VarSetOps::MakeEmpty(compiler));
genLastLiveMask = RBM_NONE;
#ifdef DEBUG
compiler->fgBBcountAtCodegen = compiler->fgBBcount;
#endif
}
/*****************************************************************************
* To report exception handling information to the VM, we need the size of the exception
* handling regions. To compute that, we need to emit labels for the beginning block of
* an EH region, and the block that immediately follows a region. Go through the EH
* table and mark all these blocks with BBF_HAS_LABEL to make this happen.
*
* The beginning blocks of the EH regions already should have this flag set.
*
* No blocks should be added or removed after this.
*
* This code is closely couple with genReportEH() in the sense that any block
* that this procedure has determined it needs to have a label has to be selected
* using the same logic both here and in genReportEH(), so basically any time there is
* a change in the way we handle EH reporting, we have to keep the logic of these two
* methods 'in sync'.
*/
void CodeGen::genPrepForEHCodegen()
{
assert(!compiler->fgSafeBasicBlockCreation);
EHblkDsc* HBtab;
EHblkDsc* HBtabEnd;
bool anyFinallys = false;
for (HBtab = compiler->compHndBBtab, HBtabEnd = compiler->compHndBBtab + compiler->compHndBBtabCount;
HBtab < HBtabEnd; HBtab++)
{
assert(HBtab->ebdTryBeg->bbFlags & BBF_HAS_LABEL);
assert(HBtab->ebdHndBeg->bbFlags & BBF_HAS_LABEL);
if (HBtab->ebdTryLast->bbNext != nullptr)
{
HBtab->ebdTryLast->bbNext->bbFlags |= BBF_HAS_LABEL;
}
if (HBtab->ebdHndLast->bbNext != nullptr)
{
HBtab->ebdHndLast->bbNext->bbFlags |= BBF_HAS_LABEL;
}
if (HBtab->HasFilter())
{
assert(HBtab->ebdFilter->bbFlags & BBF_HAS_LABEL);
// The block after the last block of the filter is
// the handler begin block, which we already asserted
// has BBF_HAS_LABEL set.
}
#ifdef _TARGET_AMD64_
if (HBtab->HasFinallyHandler())
{
anyFinallys = true;
}
#endif // _TARGET_AMD64_
}
#ifdef _TARGET_AMD64_
if (anyFinallys)
{
for (BasicBlock* block = compiler->fgFirstBB; block != nullptr; block = block->bbNext)
{
if (block->bbJumpKind == BBJ_CALLFINALLY)
{
BasicBlock* bbToLabel = block->bbNext;
if (block->isBBCallAlwaysPair())
{
bbToLabel = bbToLabel->bbNext; // skip the BBJ_ALWAYS
}
if (bbToLabel != nullptr)
{
bbToLabel->bbFlags |= BBF_HAS_LABEL;
}
} // block is BBJ_CALLFINALLY
} // for each block
} // if (anyFinallys)
#endif // _TARGET_AMD64_
}
void CodeGenInterface::genUpdateLife(GenTreePtr tree)
{
compiler->compUpdateLife</*ForCodeGen*/ true>(tree);
}
void CodeGenInterface::genUpdateLife(VARSET_VALARG_TP newLife)
{
compiler->compUpdateLife</*ForCodeGen*/ true>(newLife);
}
#ifdef LEGACY_BACKEND
// Returns the liveSet after tree has executed.
// "tree" MUST occur in the current statement, AFTER the most recent
// update of compiler->compCurLifeTree and compiler->compCurLife.
//
VARSET_VALRET_TP CodeGen::genUpdateLiveSetForward(GenTreePtr tree)
{
VARSET_TP startLiveSet(VarSetOps::MakeCopy(compiler, compiler->compCurLife));
GenTreePtr startNode;
assert(tree != compiler->compCurLifeTree);
if (compiler->compCurLifeTree == nullptr)
{
assert(compiler->compCurStmt != nullptr);
startNode = compiler->compCurStmt->gtStmt.gtStmtList;
}
else
{
startNode = compiler->compCurLifeTree->gtNext;
}
return compiler->fgUpdateLiveSet(startLiveSet, startNode, tree);
}
// Determine the registers that are live after "second" has been evaluated,
// but which are not live after "first".
// PRECONDITIONS:
// 1. "first" must occur after compiler->compCurLifeTree in execution order for the current statement
// 2. "second" must occur after "first" in the current statement
//
regMaskTP CodeGen::genNewLiveRegMask(GenTreePtr first, GenTreePtr second)
{
// First, compute the liveset after "first"
VARSET_TP firstLiveSet = genUpdateLiveSetForward(first);
// Now, update the set forward from "first" to "second"
VARSET_TP secondLiveSet = compiler->fgUpdateLiveSet(firstLiveSet, first->gtNext, second);
regMaskTP newLiveMask = genLiveMask(VarSetOps::Diff(compiler, secondLiveSet, firstLiveSet));
return newLiveMask;
}
#endif
// Return the register mask for the given register variable
// inline
regMaskTP CodeGenInterface::genGetRegMask(const LclVarDsc* varDsc)
{
regMaskTP regMask = RBM_NONE;
assert(varDsc->lvIsInReg());
if (varTypeIsFloating(varDsc->TypeGet()))
{
regMask = genRegMaskFloat(varDsc->lvRegNum, varDsc->TypeGet());
}
else
{
regMask = genRegMask(varDsc->lvRegNum);
if (isRegPairType(varDsc->lvType))
{
regMask |= genRegMask(varDsc->lvOtherReg);
}
}
return regMask;
}
// Return the register mask for the given lclVar or regVar tree node
// inline
regMaskTP CodeGenInterface::genGetRegMask(GenTreePtr tree)
{
assert(tree->gtOper == GT_LCL_VAR || tree->gtOper == GT_REG_VAR);
regMaskTP regMask = RBM_NONE;
const LclVarDsc* varDsc = compiler->lvaTable + tree->gtLclVarCommon.gtLclNum;
if (varDsc->lvPromoted)
{
for (unsigned i = varDsc->lvFieldLclStart; i < varDsc->lvFieldLclStart + varDsc->lvFieldCnt; ++i)
{
noway_assert(compiler->lvaTable[i].lvIsStructField);
if (compiler->lvaTable[i].lvIsInReg())
{
regMask |= genGetRegMask(&compiler->lvaTable[i]);
}
}
}
else if (varDsc->lvIsInReg())
{
regMask = genGetRegMask(varDsc);
}
return regMask;
}
// The given lclVar is either going live (being born) or dying.
// It might be both going live and dying (that is, it is a dead store) under MinOpts.
// Update regSet.rsMaskVars accordingly.
// inline
void CodeGenInterface::genUpdateRegLife(const LclVarDsc* varDsc, bool isBorn, bool isDying DEBUGARG(GenTreePtr tree))
{
#if FEATURE_STACK_FP_X87
// The stack fp reg vars are handled elsewhere
if (varTypeIsFloating(varDsc->TypeGet()))
return;
#endif
regMaskTP regMask = genGetRegMask(varDsc);
#ifdef DEBUG
if (compiler->verbose)
{
printf("\t\t\t\t\t\t\tV%02u in reg ", (varDsc - compiler->lvaTable));
varDsc->PrintVarReg();
printf(" is becoming %s ", (isDying) ? "dead" : "live");
Compiler::printTreeID(tree);
printf("\n");
}
#endif // DEBUG
if (isDying)
{
// We'd like to be able to assert the following, however if we are walking
// through a qmark/colon tree, we may encounter multiple last-use nodes.
// assert((regSet.rsMaskVars & regMask) == regMask);
regSet.RemoveMaskVars(regMask);
}
else
{
assert((regSet.rsMaskVars & regMask) == 0);
regSet.AddMaskVars(regMask);
}
}
// Gets a register mask that represent the kill set for a helper call since
// not all JIT Helper calls follow the standard ABI on the target architecture.
//
// TODO-CQ: Currently this list is incomplete (not all helpers calls are
// enumerated) and not 100% accurate (some killsets are bigger than
// what they really are).
// There's some work to be done in several places in the JIT to
// accurately track the registers that are getting killed by
// helper calls:
// a) LSRA needs several changes to accomodate more precise killsets
// for every helper call it sees (both explicitly [easy] and
// implicitly [hard])
// b) Currently for AMD64, when we generate code for a helper call
// we're independently over-pessimizing the killsets of the call
// (independently from LSRA) and this needs changes
// both in CodeGenAmd64.cpp and emitx86.cpp.
//
// The best solution for this problem would be to try to centralize
// the killset information in a single place but then make the
// corresponding changes so every code generation phase is in sync
// about this.
//
// The interim solution is to only add known helper calls that don't
// follow the AMD64 ABI and actually trash registers that are supposed to be non-volatile.
regMaskTP Compiler::compHelperCallKillSet(CorInfoHelpFunc helper)
{
switch (helper)
{
case CORINFO_HELP_ASSIGN_BYREF:
#if defined(_TARGET_AMD64_)
return RBM_RSI | RBM_RDI | RBM_CALLEE_TRASH;
#elif defined(_TARGET_ARM64_)
return RBM_WRITE_BARRIER_SRC_BYREF | RBM_WRITE_BARRIER_DST_BYREF | RBM_CALLEE_TRASH_NOGC;
#elif defined(_TARGET_X86_)
return RBM_ESI | RBM_EDI | RBM_ECX;
#elif defined(_TARGET_ARM_)
return RBM_ARG_1 | RBM_ARG_0 | RBM_CALLEE_TRASH_NOGC;
#else
NYI("Model kill set for CORINFO_HELP_ASSIGN_BYREF on target arch");
return RBM_CALLEE_TRASH;
#endif
case CORINFO_HELP_PROF_FCN_ENTER:
#ifdef RBM_PROFILER_ENTER_TRASH
return RBM_PROFILER_ENTER_TRASH;
#else
NYI("Model kill set for CORINFO_HELP_PROF_FCN_ENTER on target arch");
#endif
case CORINFO_HELP_PROF_FCN_LEAVE:
#ifdef RBM_PROFILER_LEAVE_TRASH
return RBM_PROFILER_LEAVE_TRASH;
#else
NYI("Model kill set for CORINFO_HELP_PROF_FCN_LEAVE on target arch");
#endif
case CORINFO_HELP_PROF_FCN_TAILCALL:
#ifdef RBM_PROFILER_TAILCALL_TRASH
return RBM_PROFILER_TAILCALL_TRASH;
#else
NYI("Model kill set for CORINFO_HELP_PROF_FCN_TAILCALL on target arch");
#endif
case CORINFO_HELP_STOP_FOR_GC:
return RBM_STOP_FOR_GC_TRASH;
case CORINFO_HELP_INIT_PINVOKE_FRAME:
return RBM_INIT_PINVOKE_FRAME_TRASH;
default:
return RBM_CALLEE_TRASH;
}
}
//
// Gets a register mask that represents the kill set for "NO GC" helper calls since
// not all JIT Helper calls follow the standard ABI on the target architecture.
//
// Note: This list may not be complete and defaults to the default NOGC registers.
//
regMaskTP Compiler::compNoGCHelperCallKillSet(CorInfoHelpFunc helper)
{
assert(emitter::emitNoGChelper(helper));
switch (helper)
{
#if defined(_TARGET_AMD64_) || defined(_TARGET_X86_)
case CORINFO_HELP_PROF_FCN_ENTER:
return RBM_PROFILER_ENTER_TRASH;
case CORINFO_HELP_PROF_FCN_LEAVE:
return RBM_PROFILER_LEAVE_TRASH;
case CORINFO_HELP_PROF_FCN_TAILCALL:
return RBM_PROFILER_TAILCALL_TRASH;
#endif // defined(_TARGET_AMD64_) || defined(_TARGET_X86_)
case CORINFO_HELP_ASSIGN_BYREF:
#if defined(_TARGET_AMD64_)
// this helper doesn't trash RSI and RDI
return RBM_CALLEE_TRASH_NOGC & ~(RBM_RSI | RBM_RDI);
#elif defined(_TARGET_X86_)
// This helper only trashes ECX.
return RBM_ECX;
#elif defined(_TARGET_ARM64_)
return RBM_CALLEE_TRASH_NOGC & ~(RBM_WRITE_BARRIER_SRC_BYREF | RBM_WRITE_BARRIER_DST_BYREF);
#else
return RBM_CALLEE_TRASH_NOGC;
#endif // defined(_TARGET_AMD64_)
default:
return RBM_CALLEE_TRASH_NOGC;
}
}
// Update liveness (always var liveness, i.e., compCurLife, and also, if "ForCodeGen" is true, reg liveness, i.e.,
// regSet.rsMaskVars as well)
// if the given lclVar (or indir(addr(local)))/regVar node is going live (being born) or dying.
template <bool ForCodeGen>
void Compiler::compUpdateLifeVar(GenTreePtr tree, VARSET_TP* pLastUseVars)
{
GenTreePtr indirAddrLocal = fgIsIndirOfAddrOfLocal(tree);
assert(tree->OperIsNonPhiLocal() || indirAddrLocal != nullptr);
// Get the local var tree -- if "tree" is "Ldobj(addr(x))", or "ind(addr(x))" this is "x", else it's "tree".
GenTreePtr lclVarTree = indirAddrLocal;
if (lclVarTree == nullptr)
{
lclVarTree = tree;
}
unsigned int lclNum = lclVarTree->gtLclVarCommon.gtLclNum;
LclVarDsc* varDsc = lvaTable + lclNum;
#ifdef DEBUG
#if !defined(_TARGET_AMD64_)
// There are no addr nodes on ARM and we are experimenting with encountering vars in 'random' order.
// Struct fields are not traversed in a consistent order, so ignore them when
// verifying that we see the var nodes in execution order
if (ForCodeGen)
{
if (tree->OperIsIndir())
{
assert(indirAddrLocal != NULL);
}
else if (tree->gtNext != NULL && tree->gtNext->gtOper == GT_ADDR &&
((tree->gtNext->gtNext == NULL || !tree->gtNext->gtNext->OperIsIndir())))
{
assert(tree->IsLocal()); // Can only take the address of a local.
// The ADDR might occur in a context where the address it contributes is eventually
// dereferenced, so we can't say that this is not a use or def.
}
#if 0
// TODO-ARM64-Bug?: These asserts don't seem right for ARM64: I don't understand why we have to assert
// two consecutive lclvars (in execution order) can only be observed if the first one is a struct field.
// It seems to me this is code only applicable to the legacy JIT and not RyuJIT (and therefore why it was
// ifdef'ed out for AMD64).
else if (!varDsc->lvIsStructField)
{
GenTreePtr prevTree;
for (prevTree = tree->gtPrev;
prevTree != NULL && prevTree != compCurLifeTree;
prevTree = prevTree->gtPrev)
{
if ((prevTree->gtOper == GT_LCL_VAR) || (prevTree->gtOper == GT_REG_VAR))
{
LclVarDsc * prevVarDsc = lvaTable + prevTree->gtLclVarCommon.gtLclNum;
// These are the only things for which this method MUST be called
assert(prevVarDsc->lvIsStructField);
}
}
assert(prevTree == compCurLifeTree);
}
#endif // 0
}
#endif // !_TARGET_AMD64_
#endif // DEBUG
compCurLifeTree = tree;
VARSET_TP newLife(VarSetOps::MakeCopy(this, compCurLife));
// By codegen, a struct may not be TYP_STRUCT, so we have to
// check lvPromoted, for the case where the fields are being
// tracked.
if (!varDsc->lvTracked && !varDsc->lvPromoted)
{
return;
}
bool isBorn = ((tree->gtFlags & GTF_VAR_DEF) != 0 && (tree->gtFlags & GTF_VAR_USEASG) == 0); // if it's "x <op>=
// ..." then variable
// "x" must have had a
// previous, original,
// site to be born.
bool isDying = ((tree->gtFlags & GTF_VAR_DEATH) != 0);
#ifndef LEGACY_BACKEND
bool spill = ((tree->gtFlags & GTF_SPILL) != 0);
#endif // !LEGACY_BACKEND
#ifndef LEGACY_BACKEND
// For RyuJIT backend, since all tracked vars are register candidates, but not all are in registers at all times,
// we maintain two separate sets of variables - the total set of variables that are either
// born or dying here, and the subset of those that are on the stack
VARSET_TP stackVarDeltaSet(VarSetOps::MakeEmpty(this));
#endif // !LEGACY_BACKEND
if (isBorn || isDying)
{
bool hasDeadTrackedFieldVars = false; // If this is true, then, for a LDOBJ(ADDR(<promoted struct local>)),
VARSET_TP* deadTrackedFieldVars =
nullptr; // *deadTrackedFieldVars indicates which tracked field vars are dying.
VARSET_TP varDeltaSet(VarSetOps::MakeEmpty(this));
if (varDsc->lvTracked)
{
VarSetOps::AddElemD(this, varDeltaSet, varDsc->lvVarIndex);
if (ForCodeGen)
{
#ifndef LEGACY_BACKEND
if (isBorn && varDsc->lvIsRegCandidate() && tree->gtHasReg())
{
codeGen->genUpdateVarReg(varDsc, tree);
}
#endif // !LEGACY_BACKEND
if (varDsc->lvIsInReg()
#ifndef LEGACY_BACKEND
&& tree->gtRegNum != REG_NA
#endif // !LEGACY_BACKEND
)
{
codeGen->genUpdateRegLife(varDsc, isBorn, isDying DEBUGARG(tree));
}
#ifndef LEGACY_BACKEND
else
{
VarSetOps::AddElemD(this, stackVarDeltaSet, varDsc->lvVarIndex);
}
#endif // !LEGACY_BACKEND
}
}
else if (varDsc->lvPromoted)
{
if (indirAddrLocal != nullptr && isDying)
{
assert(!isBorn); // GTF_VAR_DEATH only set for LDOBJ last use.
hasDeadTrackedFieldVars = GetPromotedStructDeathVars()->Lookup(indirAddrLocal, &deadTrackedFieldVars);
if (hasDeadTrackedFieldVars)
{
VarSetOps::Assign(this, varDeltaSet, *deadTrackedFieldVars);
}
}
for (unsigned i = varDsc->lvFieldLclStart; i < varDsc->lvFieldLclStart + varDsc->lvFieldCnt; ++i)
{
LclVarDsc* fldVarDsc = &(lvaTable[i]);
noway_assert(fldVarDsc->lvIsStructField);
if (fldVarDsc->lvTracked)
{
unsigned fldVarIndex = fldVarDsc->lvVarIndex;
noway_assert(fldVarIndex < lvaTrackedCount);
if (!hasDeadTrackedFieldVars)
{
VarSetOps::AddElemD(this, varDeltaSet, fldVarIndex);
if (ForCodeGen)
{
// We repeat this call here and below to avoid the VarSetOps::IsMember
// test in this, the common case, where we have no deadTrackedFieldVars.
if (fldVarDsc->lvIsInReg())
{
#ifndef LEGACY_BACKEND
if (isBorn)
{
codeGen->genUpdateVarReg(fldVarDsc, tree);
}
#endif // !LEGACY_BACKEND
codeGen->genUpdateRegLife(fldVarDsc, isBorn, isDying DEBUGARG(tree));
}
#ifndef LEGACY_BACKEND
else
{
VarSetOps::AddElemD(this, stackVarDeltaSet, fldVarIndex);
}
#endif // !LEGACY_BACKEND
}
}
else if (ForCodeGen && VarSetOps::IsMember(this, varDeltaSet, fldVarIndex))
{
if (lvaTable[i].lvIsInReg())
{
#ifndef LEGACY_BACKEND
if (isBorn)
{
codeGen->genUpdateVarReg(fldVarDsc, tree);
}
#endif // !LEGACY_BACKEND
codeGen->genUpdateRegLife(fldVarDsc, isBorn, isDying DEBUGARG(tree));
}
#ifndef LEGACY_BACKEND
else
{
VarSetOps::AddElemD(this, stackVarDeltaSet, fldVarIndex);
}
#endif // !LEGACY_BACKEND
}
}
}
}
// First, update the live set
if (isDying)
{
// We'd like to be able to assert the following, however if we are walking
// through a qmark/colon tree, we may encounter multiple last-use nodes.
// assert (VarSetOps::IsSubset(compiler, regVarDeltaSet, newLife));
VarSetOps::DiffD(this, newLife, varDeltaSet);
if (pLastUseVars != nullptr)
{
VarSetOps::Assign(this, *pLastUseVars, varDeltaSet);
}
}
else
{
// This shouldn't be in newLife, unless this is debug code, in which
// case we keep vars live everywhere, OR the variable is address-exposed,
// OR this block is part of a try block, in which case it may be live at the handler
// Could add a check that, if it's in newLife, that it's also in
// fgGetHandlerLiveVars(compCurBB), but seems excessive
//
// For a dead store, it can be the case that we set both isBorn and isDying to true.
// (We don't eliminate dead stores under MinOpts, so we can't assume they're always
// eliminated.) If it's both, we handled it above.
VarSetOps::UnionD(this, newLife, varDeltaSet);
}
}
if (!VarSetOps::Equal(this, compCurLife, newLife))
{
#ifdef DEBUG
if (verbose)
{
printf("\t\t\t\t\t\t\tLive vars: ");
dumpConvertedVarSet(this, compCurLife);
printf(" => ");
dumpConvertedVarSet(this, newLife);
printf("\n");
}
#endif // DEBUG
VarSetOps::Assign(this, compCurLife, newLife);
if (ForCodeGen)
{
#ifndef LEGACY_BACKEND
// Only add vars to the gcInfo.gcVarPtrSetCur if they are currently on stack, since the
// gcInfo.gcTrkStkPtrLcls
// includes all TRACKED vars that EVER live on the stack (i.e. are not always in a register).
VARSET_TP gcTrkStkDeltaSet(
VarSetOps::Intersection(this, codeGen->gcInfo.gcTrkStkPtrLcls, stackVarDeltaSet));
if (!VarSetOps::IsEmpty(this, gcTrkStkDeltaSet))
{
#ifdef DEBUG
if (verbose)
{
printf("\t\t\t\t\t\t\tGCvars: ");
dumpConvertedVarSet(this, codeGen->gcInfo.gcVarPtrSetCur);
printf(" => ");
}
#endif // DEBUG
if (isBorn)
{
VarSetOps::UnionD(this, codeGen->gcInfo.gcVarPtrSetCur, gcTrkStkDeltaSet);
}
else
{
VarSetOps::DiffD(this, codeGen->gcInfo.gcVarPtrSetCur, gcTrkStkDeltaSet);
}
#ifdef DEBUG
if (verbose)
{
dumpConvertedVarSet(this, codeGen->gcInfo.gcVarPtrSetCur);
printf("\n");
}
#endif // DEBUG
}
#else // LEGACY_BACKEND
#ifdef DEBUG
if (verbose)
{
VARSET_TP gcVarPtrSetNew(VarSetOps::Intersection(this, newLife, codeGen->gcInfo.gcTrkStkPtrLcls));
if (!VarSetOps::Equal(this, codeGen->gcInfo.gcVarPtrSetCur, gcVarPtrSetNew))
{
printf("\t\t\t\t\t\t\tGCvars: ");
dumpConvertedVarSet(this, codeGen->gcInfo.gcVarPtrSetCur);