diff --git a/chapters/3-CPU-Microarchitecture/3-4 Exploiting TLP.md b/chapters/3-CPU-Microarchitecture/3-4 Exploiting TLP.md
index d563c99b5e..c084db922e 100644
--- a/chapters/3-CPU-Microarchitecture/3-4 Exploiting TLP.md	
+++ b/chapters/3-CPU-Microarchitecture/3-4 Exploiting TLP.md	
@@ -43,6 +43,7 @@ The first mainstream hybrid architecture was ARM's big.LITTLE, which was introdu
 Hybrid architectures combine the best sides of both core types, but it comes with its own set of challenges. First of all, it requires cores to be fully ISA-compatible, i.e. they should be able to execute the same set of instructions. Otherwise, the schedulling becomes restricted. For example, if a big core features some fancy instructions that are not available on small cores, than you can only assign big cores to run workloads that use such instructions. That's why usualy vendors use the "greatest common denominator" approach when choosing the ISA for a hybrid processor.
 
 Even with ISA-compatible cores, schedulling becomes challenging. Different types of workloads call for specific schedulling scheme, e.g. bursty execution vs. steady execution, low IPC vs. high IPC, low improtance vs. high importance, etc. It becomes non-trivial very quickly. Here are a few considerations for optimal scheduling:
+
 * Leverage small cores to conserve power. Do not wake up big cores for the background work.
 * Recognize candidates (low importance, low IPC) for offloading to smaller cores. Similarly, promote high importance, high IPC tasks to big cores.
 * When assigning a new task, use an idle big core first. In case SMT, use big cores with both logical threads idle. After that, use idle small cores. After that, use sibling logical threads of big cores.