From d6534dc77b0735a625780c4b152381ac573982b8 Mon Sep 17 00:00:00 2001
From: Sergey Svishchev <shattered@users.noreply.github.com>
Date: Wed, 12 Jun 2024 18:50:35 +0300
Subject: [PATCH] 8080: flush register from cache when it's modified by ALU
 insn

---
 src/cowbe/arch8080.cow.ng | 10 +++++-----
 tests/build.py            |  1 +
 tests/regcache.good       |  5 +++++
 tests/regcache.test.cow   | 31 +++++++++++++++++++++++++++++++
 4 files changed, 42 insertions(+), 5 deletions(-)
 create mode 100644 tests/regcache.good
 create mode 100644 tests/regcache.test.cow

diff --git a/src/cowbe/arch8080.cow.ng b/src/cowbe/arch8080.cow.ng
index fe6adb34..d5d68097 100644
--- a/src/cowbe/arch8080.cow.ng
+++ b/src/cowbe/arch8080.cow.ng
@@ -892,7 +892,7 @@ gen a := ADD1(b|d|h:lhs, a)
 		{ E_add($lhs); }
 
 gen a := ADD1(DEREF1(hl), a)
-		{ E("\tadd m\n"); }
+		{ R_flush(REG_A); E("\tadd m\n"); }
 
 gen a|b|d|h := ADD1($$, CONSTANT(value==-1))
 		{ E_dcr($$); }
@@ -904,7 +904,7 @@ gen a := SUB1(a, b|d|h:rhs)
 		{ E_sub($rhs); }
 
 gen a := SUB1(a, DEREF1(hl))
-		{ E("\tsub m\n"); }
+		{ R_flush(REG_A); E("\tsub m\n"); }
 
 gen a|b|d|h := SUB1($$, CONSTANT(value==1))
 		{ E_dcr($$); }
@@ -928,7 +928,7 @@ gen a := OR1(a, b|d|h:lhs)
 		{ E_ora($lhs); }
 
 gen a := OR1(a, DEREF1(hl))
-		{ E("\tora m\n"); }
+		{ R_flush(REG_A); E("\tora m\n"); }
 
 gen a := OR1(a, CONSTANT():c)
 		{ E_ori($c.value as uint8); }
@@ -937,7 +937,7 @@ gen a := AND1(a, b|d|h:lhs)
 		{ E_ana($lhs); }
 
 gen a := AND1(a, DEREF1(hl))
-		{ E("\tana m\n"); }
+		{ R_flush(REG_A); E("\tana m\n"); }
 
 gen a := AND1(a, CONSTANT():c)
 		{ E_ani($c.value as uint8); }
@@ -946,7 +946,7 @@ gen a := EOR1(a, b|d|h:lhs)
 		{ E_xra($lhs); }
 
 gen a := EOR1(a, DEREF1(hl))
-		{ E("\txra m\n"); }
+		{ R_flush(REG_A); E("\txra m\n"); }
 
 gen a := EOR1(a, CONSTANT():c)
 		{ E_xri($c.value as uint8); }
diff --git a/tests/build.py b/tests/build.py
index b1a57d49..512cbb41 100644
--- a/tests/build.py
+++ b/tests/build.py
@@ -44,6 +44,7 @@
     "recordinitialisers",
     "records",
     "regalloc",
+    "regcache",
     "shifts-16bit",
     "shifts-32bit",
     "shifts-8bit",
diff --git a/tests/regcache.good b/tests/regcache.good
new file mode 100644
index 00000000..aabcd495
--- /dev/null
+++ b/tests/regcache.good
@@ -0,0 +1,5 @@
+regcache1 add: yes
+regcache1 sub: yes
+regcache1 or: yes
+regcache1 xor: yes
+regcache1 and: yes
diff --git a/tests/regcache.test.cow b/tests/regcache.test.cow
new file mode 100644
index 00000000..f7859bd0
--- /dev/null
+++ b/tests/regcache.test.cow
@@ -0,0 +1,31 @@
+include "cowgol.coh";
+include "tests/_framework.coh";
+
+# ALU insns referencing memory should flush cached target register value
+sub cache1() is
+    var a: uint8 := 2;
+    var b: uint8 := 1;
+    var c: uint8;
+    var d: uint8;
+
+    c := a + b;
+    d := a;
+    print("regcache1 add"); if c == 3 and d == 2 then yes(); else no(); end if;
+
+    c := a - b;
+    d := a;
+    print("regcache1 sub"); if c == 1 and d == 2 then yes(); else no(); end if;
+
+    c := a | b;
+    d := a;
+    print("regcache1 or"); if c == 3 and d == 2 then yes(); else no(); end if;
+
+    c := a ^ b;
+    d := a;
+    print("regcache1 xor"); if c == 3 and d == 2 then yes(); else no(); end if;
+
+    c := a & b;
+    d := a;
+    print("regcache1 and"); if c == 0 and d == 2 then yes(); else no(); end if;
+end sub;
+cache1();