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vhdl-mode.el
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;;; vhdl-mode.el --- major mode for editing VHDL code
;; Copyright (C) 1992-2012 Free Software Foundation, Inc.
;; Authors: Reto Zimmermann <[email protected]>
;; Rodney J. Whitby <[email protected]>
;; Maintainer: Reto Zimmermann <[email protected]>
;; Version: 3.38.1
;; RCS: $Id: vhdl-mode.el,v 33.102 2015/03/12 12:37:25 reto Exp reto $
;; Keywords: languages vhdl
;; WWW: http://www.iis.ee.ethz.ch/~zimmi/emacs/vhdl-mode.html
(defconst vhdl-version "3.38.1"
"VHDL Mode version number.")
(defconst vhdl-time-stamp "2015-03-12"
"VHDL Mode time stamp for last update.")
;; This file is part of GNU Emacs.
;; GNU Emacs is free software: you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation, either version 3 of the License, or
;; (at your option) any later version.
;; GNU Emacs is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
;; GNU General Public License for more details.
;; You should have received a copy of the GNU General Public License
;; along with GNU Emacs. If not, see <http://www.gnu.org/licenses/>.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;; Commentary:
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; This package provides an Emacs major mode for editing VHDL code.
;; It includes the following features:
;; - Syntax highlighting
;; - Indentation
;; - Template insertion (electrification)
;; - Insertion of file headers
;; - Insertion of user-specified models
;; - Port translation / testbench generation
;; - Structural composition
;; - Configuration generation
;; - Sensitivity list updating
;; - File browser
;; - Design hierarchy browser
;; - Source file compilation (syntax analysis)
;; - Makefile generation
;; - Code hiding
;; - Word/keyword completion
;; - Block commenting
;; - Code fixing/alignment/beautification
;; - Postscript printing
;; - VHDL'87/'93/'02/'08 and VHDL-AMS supported
;; - Comprehensive menu
;; - Fully customizable
;; - Works under GNU Emacs (recommended) and XEmacs
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; Documentation
;; See comment string of function `vhdl-mode' or type `C-c C-h' in Emacs.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; Emacs Versions
;; this updated version was only tested on: GNU Emacs 24.1
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; Installation
;; Prerequisites: GNU Emacs 20/21/22/23/24, XEmacs 20/21.
;; Put `vhdl-mode.el' into the `site-lisp' directory of your Emacs installation
;; or into an arbitrary directory that is added to the load path by the
;; following line in your Emacs start-up file `.emacs':
;; (push (expand-file-name "<directory-name>") load-path)
;; If you already have the compiled `vhdl-mode.elc' file, put it in the same
;; directory. Otherwise, byte-compile the source file:
;; Emacs: M-x byte-compile-file RET vhdl-mode.el RET
;; Unix: emacs -batch -q -no-site-file -f batch-byte-compile vhdl-mode.el
;; Add the following lines to the `site-start.el' file in the `site-lisp'
;; directory of your Emacs installation or to your Emacs start-up file `.emacs'
;; (not required in Emacs 20 and higher):
;; (autoload 'vhdl-mode "vhdl-mode" "VHDL Mode" t)
;; (push '("\\.vhdl?\\'" . vhdl-mode) auto-mode-alist)
;; More detailed installation instructions are included in the official
;; VHDL Mode distribution.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; Acknowledgements
;; Electrification ideas by Bob Pack <[email protected]>
;; and Steve Grout.
;; Fontification approach suggested by Ken Wood <[email protected]>.
;; Ideas about alignment from John Wiegley <[email protected]>.
;; Many thanks to all the users who sent me bug reports and enhancement
;; requests.
;; Thanks to Colin Marquardt for his serious beta testing, his innumerable
;; enhancement suggestions and the fruitful discussions.
;; Thanks to Dan Nicolaescu for reviewing the code and for his valuable hints.
;; Thanks to Ulf Klaperski for the indentation speedup hint.
;; Special thanks go to Wolfgang Fichtner and the crew from the Integrated
;; Systems Laboratory, Swiss Federal Institute of Technology Zurich, for
;; giving me the opportunity to develop this code.
;; This work has been funded in part by MICROSWISS, a Microelectronics Program
;; of the Swiss Government.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;; Code:
;; Emacs 21+ handling
(defconst vhdl-emacs-21 (and (<= 21 emacs-major-version) (not (featurep 'xemacs)))
"Non-nil if GNU Emacs 21, 22, ... is used.")
;; Emacs 22+ handling
(defconst vhdl-emacs-22 (and (<= 22 emacs-major-version) (not (featurep 'xemacs)))
"Non-nil if GNU Emacs 22, ... is used.")
(defvar compilation-file-regexp-alist)
(defvar itimer-version)
(defvar lazy-lock-defer-contextually)
(defvar lazy-lock-defer-on-scrolling)
(defvar lazy-lock-defer-on-the-fly)
(defvar speedbar-attached-frame)
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;; Variables
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; help function for user options
(defun vhdl-custom-set (variable value &rest functions)
"Set variables as in `custom-set-default' and call FUNCTIONS afterwards."
(if (fboundp 'custom-set-default)
(custom-set-default variable value)
(set-default variable value))
(while functions
(when (fboundp (car functions)) (funcall (car functions)))
(setq functions (cdr functions))))
(defun vhdl-widget-directory-validate (widget)
"Check that the value of WIDGET is a valid directory entry (i.e. ends with
'/' or is empty)."
(let ((val (widget-value widget)))
(unless (string-match "^\\(\\|.*/\\)$" val)
(widget-put widget :error "Invalid directory entry: must end with '/'")
widget)))
;; help string for user options
(defconst vhdl-name-doc-string "
FROM REGEXP is a regular expression matching the original name:
\".*\" matches the entire string
\"\\(...\\)\" matches a substring
TO STRING specifies the string to be inserted as new name:
\"\\&\" means substitute entire matched text
\"\\N\" means substitute what matched the Nth \"\\(...\\)\"
Examples:
\".*\" \"\\&\" inserts original string
\".*\" \"\\&_i\" attaches \"_i\" to original string
\"\\(.*\\)_[io]$\" \"\\1\" strips off \"_i\" or \"_o\" from original string
\".*\" \"foo\" inserts constant string \"foo\"
\".*\" \"\" inserts empty string")
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; User variables (customization options)
(defgroup vhdl nil
"Customizations for VHDL Mode."
:prefix "vhdl-"
:group 'languages
; :version "21.2" ; comment out for XEmacs
)
(defgroup vhdl-mode nil
"Customizations for modes."
:group 'vhdl)
(defcustom vhdl-electric-mode t
"*Non-nil enables electrification (automatic template generation).
If nil, template generators can still be invoked through key bindings and
menu. Is indicated in the modeline by \"/e\" after the mode name and can be
toggled by `\\[vhdl-electric-mode]'."
:type 'boolean
:group 'vhdl-mode)
(defcustom vhdl-stutter-mode t
"*Non-nil enables stuttering.
Is indicated in the modeline by \"/s\" after the mode name and can be toggled
by `\\[vhdl-stutter-mode]'."
:type 'boolean
:group 'vhdl-mode)
(defcustom vhdl-indent-tabs-mode nil
"*Non-nil means indentation can insert tabs.
Overrides local variable `indent-tabs-mode'."
:type 'boolean
:group 'vhdl-mode)
(defgroup vhdl-compile nil
"Customizations for compilation."
:group 'vhdl)
(defcustom vhdl-compiler-alist
'(
;; 60: docal <= false;
;; ^^^^^
;; [Error] Assignment error: variable is illegal target of signal assignment
("ADVance MS" "vacom" "-work \\1" "make" "-f \\1"
nil "valib \\1; vamap \\2 \\1" "./" "work/" "Makefile" "adms"
("^\\s-+\\([0-9]+\\):\\s-+" nil 1 nil) ("^Compiling file \\(.+\\)" 1)
("ENTI/\\1.vif" "ARCH/\\1-\\2.vif" "CONF/\\1.vif"
"PACK/\\1.vif" "BODY/\\1.vif" upcase))
;; Aldec
;; COMP96 ERROR COMP96_0018: "Identifier expected." "test.vhd" 66 3
("Aldec" "vcom" "-work \\1" "make" "-f \\1"
nil "vlib \\1; vmap \\2 \\1" "./" "work/" "Makefile" "aldec"
("^.* ERROR [^:]+: \".*\" \"\\([^ \t\n]+\\)\" \\([0-9]+\\) \\([0-9]+\\)" 1 2 3) ("" 0)
nil)
;; Cadence Leapfrog: cv -file test.vhd
;; duluth: *E,430 (test.vhd,13): identifier (POSITIV) is not declared
("Cadence Leapfrog" "cv" "-work \\1 -file" "make" "-f \\1"
nil "mkdir \\1" "./" "work/" "Makefile" "leapfrog"
("^duluth: \\*E,[0-9]+ (\\([^ \t\n]+\\),\\([0-9]+\\)):" 1 2 nil) ("" 0)
("\\1/entity" "\\2/\\1" "\\1/configuration"
"\\1/package" "\\1/body" downcase))
;; Cadence Affirma NC vhdl: ncvhdl test.vhd
;; ncvhdl_p: *E,IDENTU (test.vhd,13|25): identifier
;; (PLL_400X_TOP) is not declared [10.3].
("Cadence NC" "ncvhdl" "-work \\1" "make" "-f \\1"
nil "mkdir \\1" "./" "work/" "Makefile" "ncvhdl"
("^ncvhdl_p: \\*E,\\w+ (\\([^ \t\n]+\\),\\([0-9]+\\)|\\([0-9]+\\)):" 1 2 3) ("" 0)
("\\1/entity/pc.db" "\\2/\\1/pc.db" "\\1/configuration/pc.db"
"\\1/package/pc.db" "\\1/body/pc.db" downcase))
;; ghdl vhdl
;; ghdl -a bad_counter.vhdl
;; bad_counter.vhdl:13:14: operator "=" is overloaded
("GHDL" "ghdl" "-i --workdir=\\1 --ieee=synopsys -fexplicit " "make" "-f \\1"
nil "mkdir \\1" "./" "work/" "Makefile" "ghdl"
("^ghdl_p: \\*E,\\w+ (\\([^ \t\n]+\\),\\([0-9]+\\)|\\([0-9]+\\)):" 1 2 3) ("" 0)
("\\1/entity" "\\2/\\1" "\\1/configuration"
"\\1/package" "\\1/body" downcase))
;; IBM Compiler
;; 00 COACHDL* | [CCHDL-1]: File: adder.vhd, line.column: 120.6
("IBM Compiler" "g2tvc" "-src" "precomp" "\\1"
nil "mkdir \\1" "./" "work/" "Makefile" "ibm"
("^[0-9]+ COACHDL.*: File: \\([^ \t\n]+\\), *line.column: \\([0-9]+\\).\\([0-9]+\\)" 1 2 3) (" " 0)
nil)
;; Ikos Voyager: analyze test.vhd
;; analyze test.vhd
;; E L4/C5: this library unit is inaccessible
("Ikos" "analyze" "-l \\1" "make" "-f \\1"
nil "mkdir \\1" "./" "work/" "Makefile" "ikos"
("^E L\\([0-9]+\\)/C\\([0-9]+\\):" nil 1 2)
("^analyze +\\(.+ +\\)*\\(.+\\)$" 2)
nil)
;; ModelSim, Model Technology: vcom test.vhd
;; ERROR: test.vhd(14): Unknown identifier: positiv
;; WARNING[2]: test.vhd(85): Possible infinite loop
;; ** Warning: [4] ../src/emacsvsim.vhd(43): An abstract ...
;; ** Error: adder.vhd(190): Unknown identifier: ctl_numb
("ModelSim" "vcom" "-93 -work \\1" "make" "-f \\1"
nil "vlib \\1; vmap \\2 \\1" "./" "work/" "Makefile" "modelsim"
("^\\(ERROR\\|WARNING\\|\\*\\* Error\\|\\*\\* Warning\\)[^:]*:\\( *\[[0-9]+\]\\)? \\([^ \t\n]+\\)(\\([0-9]+\\)):" 3 4 nil) ("" 0)
("\\1/_primary.dat" "\\2/\\1.dat" "\\1/_primary.dat"
"\\1/_primary.dat" "\\1/body.dat" downcase))
;; ProVHDL, Synopsys LEDA: provhdl -w work -f test.vhd
;; test.vhd:34: error message
("LEDA ProVHDL" "provhdl" "-w \\1 -f" "make" "-f \\1"
nil "mkdir \\1" "./" "work/" "Makefile" "provhdl"
("^\\([^ \t\n:]+\\):\\([0-9]+\\): " 1 2 nil) ("" 0)
("ENTI/\\1.vif" "ARCH/\\1-\\2.vif" "CONF/\\1.vif"
"PACK/\\1.vif" "BODY/BODY-\\1.vif" upcase))
;; Quartus compiler
;; Error: VHDL error at dvi2sdi.vhd(473): object k2_alto_out_lvl is used
;; Error: Verilog HDL syntax error at otsuif_v1_top.vhd(147) near text
;; Error: VHDL syntax error at otsuif_v1_top.vhd(147): clk_ is an illegal
;; Error: VHDL Use Clause error at otsuif_v1_top.vhd(455): design library
;; Warning: VHDL Process Statement warning at dvi2sdi_tst.vhd(172): ...
("Quartus" "make" "-work \\1" "make" "-f \\1"
nil "mkdir \\1" "./" "work/" "Makefile" "quartus"
("^\\(Error\\|Warning\\): .* \\([^ \t\n]+\\)(\\([0-9]+\\))" 2 3 nil) ("" 0)
nil)
;; QuickHDL, Mentor Graphics: qvhcom test.vhd
;; ERROR: test.vhd(24): near "dnd": expecting: END
;; WARNING[4]: test.vhd(30): A space is required between ...
("QuickHDL" "qvhcom" "-work \\1" "make" "-f \\1"
nil "mkdir \\1" "./" "work/" "Makefile" "quickhdl"
("^\\(ERROR\\|WARNING\\)[^:]*: \\([^ \t\n]+\\)(\\([0-9]+\\)):" 2 3 nil) ("" 0)
("\\1/_primary.dat" "\\2/\\1.dat" "\\1/_primary.dat"
"\\1/_primary.dat" "\\1/body.dat" downcase))
;; Savant: scram -publish-cc test.vhd
;; test.vhd:87: _set_passed_through_out_port(IIR_Boolean) not defined for
("Savant" "scram" "-publish-cc -design-library-name \\1" "make" "-f \\1"
nil "mkdir \\1" "./" "work._savant_lib/" "Makefile" "savant"
("^\\([^ \t\n:]+\\):\\([0-9]+\\): " 1 2 nil) ("" 0)
("\\1_entity.vhdl" "\\2_secondary_units._savant_lib/\\2_\\1.vhdl"
"\\1_config.vhdl" "\\1_package.vhdl"
"\\1_secondary_units._savant_lib/\\1_package_body.vhdl" downcase))
;; Simili: vhdlp -work test.vhd
;; Error: CSVHDL0002: test.vhd: (line 97): Invalid prefix
("Simili" "vhdlp" "-work \\1" "make" "-f \\1"
nil "mkdir \\1" "./" "work/" "Makefile" "simili"
("^\\(Error\\|Warning\\): \\w+: \\([^ \t\n]+\\): (line \\([0-9]+\\)): " 2 3 nil) ("" 0)
("\\1/prim.var" "\\2/_\\1.var" "\\1/prim.var"
"\\1/prim.var" "\\1/_body.var" downcase))
;; Speedwave (Innoveda): analyze -libfile vsslib.ini -src test.vhd
;; ERROR[11]::File test.vhd Line 100: Use of undeclared identifier
("Speedwave" "analyze" "-libfile vsslib.ini -src" "make" "-f \\1"
nil "mkdir \\1" "./" "work/" "Makefile" "speedwave"
("^ *ERROR\[[0-9]+\]::File \\([^ \t\n]+\\) Line \\([0-9]+\\):" 1 2 nil) ("" 0)
nil)
;; Synopsys, VHDL Analyzer (sim): vhdlan -nc test.vhd
;; **Error: vhdlan,703 test.vhd(22): OTHERS is not legal in this context.
("Synopsys" "vhdlan" "-nc -work \\1" "make" "-f \\1"
nil "mkdir \\1" "./" "work/" "Makefile" "synopsys"
("^\\*\\*Error: vhdlan,[0-9]+ \\([^ \t\n]+\\)(\\([0-9]+\\)):" 1 2 nil) ("" 0)
("\\1.sim" "\\2__\\1.sim" "\\1.sim" "\\1.sim" "\\1__.sim" upcase))
;; Synopsys, VHDL Analyzer (syn): vhdlan -nc -spc test.vhd
;; **Error: vhdlan,703 test.vhd(22): OTHERS is not legal in this context.
("Synopsys Design Compiler" "vhdlan" "-nc -spc -work \\1" "make" "-f \\1"
nil "mkdir \\1" "./" "work/" "Makefile" "synopsys_dc"
("^\\*\\*Error: vhdlan,[0-9]+ \\([^ \t\n]+\\)(\\([0-9]+\\)):" 1 2 nil) ("" 0)
("\\1.syn" "\\2__\\1.syn" "\\1.syn" "\\1.syn" "\\1__.syn" upcase))
;; Synplify:
;; @W:"test.vhd":57:8:57:9|Optimizing register bit count_x(5) to a constant 0
("Synplify" "n/a" "n/a" "make" "-f \\1"
nil "mkdir \\1" "./" "work/" "Makefile" "synplify"
("^@[EWN]:\"\\([^ \t\n]+\\)\":\\([0-9]+\\):\\([0-9]+\\):" 1 2 3) ("" 0)
nil)
;; Vantage: analyze -libfile vsslib.ini -src test.vhd
;; Compiling "test.vhd" line 1...
;; **Error: LINE 49 *** No aggregate value is valid in this context.
("Vantage" "analyze" "-libfile vsslib.ini -src" "make" "-f \\1"
nil "mkdir \\1" "./" "work/" "Makefile" "vantage"
("^\\*\\*Error: LINE \\([0-9]+\\) \\*\\*\\*" nil 1 nil)
("^ *Compiling \"\\(.+\\)\" " 1)
nil)
;; VeriBest: vc vhdl test.vhd
;; (no file name printed out!)
;; 32: Z <= A and BitA ;
;; ^^^^
;; [Error] Name BITA is unknown
("VeriBest" "vc" "vhdl" "make" "-f \\1"
nil "mkdir \\1" "./" "work/" "Makefile" "veribest"
("^ +\\([0-9]+\\): +[^ ]" nil 1 nil) ("" 0)
nil)
;; Viewlogic: analyze -libfile vsslib.ini -src test.vhd
;; Compiling "test.vhd" line 1...
;; **Error: LINE 49 *** No aggregate value is valid in this context.
("Viewlogic" "analyze" "-libfile vsslib.ini -src" "make" "-f \\1"
nil "mkdir \\1" "./" "work/" "Makefile" "viewlogic"
("^\\*\\*Error: LINE \\([0-9]+\\) \\*\\*\\*" nil 1 nil)
("^ *Compiling \"\\(.+\\)\" " 1)
nil)
;; Xilinx XST:
;; ERROR:HDLParsers:164 - "test.vhd" Line 3. parse error
("Xilinx XST" "xflow" "" "make" "-f \\1"
nil "mkdir \\1" "./" "work/" "Makefile" "xilinx"
("^ERROR:HDLParsers:[0-9]+ - \"\\([^ \t\n]+\\)\" Line \\([0-9]+\\)\." 1 2 nil) ("" 0)
nil)
)
"*List of available VHDL compilers and their properties.
Each list entry specifies the following items for a compiler:
Compiler:
Compiler name : name used in option `vhdl-compiler' to choose compiler
Compile command : command used for source file compilation
Compile options : compile options (\"\\1\" inserts library name)
Make command : command used for compilation using a Makefile
Make options : make options (\"\\1\" inserts Makefile name)
Generate Makefile: use built-in function or command to generate a Makefile
\(\"\\1\" inserts Makefile name, \"\\2\" inserts library name)
Library command : command to create library directory \(\"\\1\" inserts
library directory, \"\\2\" inserts library name)
Compile directory: where compilation is run and the Makefile is placed
Library directory: directory of default library
Makefile name : name of Makefile (default is \"Makefile\")
ID string : compiler identification string (see `vhdl-project-alist')
Error message:
Regexp : regular expression to match error messages (*)
File subexp index: index of subexpression that matches the file name
Line subexp index: index of subexpression that matches the line number
Column subexp idx: index of subexpression that matches the column number
File message:
Regexp : regular expression to match a file name message
File subexp index: index of subexpression that matches the file name
Unit-to-file name mapping: mapping of library unit names to names of files
generated by the compiler (used for Makefile generation)
To string : string a name is mapped to (\"\\1\" inserts the unit name,
\"\\2\" inserts the entity name for architectures,
\"\\3\" inserts the library name)
Case adjustment : adjust case of inserted unit names
\(*) The regular expression must match the error message starting from the
beginning of the line (but not necessarily to the end of the line).
Compile options allows insertion of the library name (see `vhdl-project-alist')
in order to set the compilers library option (e.g. \"vcom -work my_lib\").
For Makefile generation, the built-in function can be used (requires
specification of the unit-to-file name mapping). Alternatively, an
external command can be specified. Work directory allows specification of
an alternative \"work\" library path (e.g. \"WORK/\" instead of \"work/\",
used for Makefile generation). To use another library name than \"work\",
customize `vhdl-project-alist'. The library command is inserted in Makefiles
to automatically create the library directory if not existent.
Compile options, compile directory, library directory, and Makefile name are
overwritten by the project settings if a project is defined (see
`vhdl-project-alist'). Directory paths are relative to the source file
directory.
Some compilers do not include the file name in the error message, but print
out a file name message in advance. In this case, set \"File Subexp Index\"
under \"Error Message\" to 0 and fill out the \"File Message\" entries.
If no file name at all is printed out, set both \"File Message\" entries to 0
\(a default file name message will be printed out instead, does not work in
XEmacs).
A compiler is selected for syntax analysis (`\\[vhdl-compile]') by
assigning its name to option `vhdl-compiler'.
Please send any missing or erroneous compiler properties to the maintainer for
updating.
NOTE: Activate new error and file message regexps and reflect the new setting
in the choice list of option `vhdl-compiler' by restarting Emacs."
:type '(repeat
(list :tag "Compiler" :indent 2
(string :tag "Compiler name ")
(string :tag "Compile command ")
(string :tag "Compile options " "-work \\1")
(string :tag "Make command " "make")
(string :tag "Make options " "-f \\1")
(choice :tag "Generate Makefile "
(const :tag "Built-in function" nil)
(string :tag "Command" "vmake \\2 > \\1"))
(string :tag "Library command " "mkdir \\1")
(directory :tag "Compile directory "
:validate vhdl-widget-directory-validate "./")
(directory :tag "Library directory "
:validate vhdl-widget-directory-validate "work/")
(file :tag "Makefile name " "Makefile")
(string :tag "ID string ")
(list :tag "Error message" :indent 4
(regexp :tag "Regexp ")
(choice :tag "File subexp "
(integer :tag "Index")
(const :tag "No file name" nil))
(integer :tag "Line subexp index")
(choice :tag "Column subexp "
(integer :tag "Index")
(const :tag "No column number" nil)))
(list :tag "File message" :indent 4
(regexp :tag "Regexp ")
(integer :tag "File subexp index"))
(choice :tag "Unit-to-file name mapping"
:format "%t: %[Value Menu%] %v\n"
(const :tag "Not defined" nil)
(list :tag "To string" :indent 4
(string :tag "Entity " "\\1.vhd")
(string :tag "Architecture " "\\2_\\1.vhd")
(string :tag "Configuration " "\\1.vhd")
(string :tag "Package " "\\1.vhd")
(string :tag "Package Body " "\\1_body.vhd")
(choice :tag "Case adjustment "
(const :tag "None" identity)
(const :tag "Upcase" upcase)
(const :tag "Downcase" downcase))))))
:set (lambda (variable value)
(vhdl-custom-set variable value 'vhdl-update-mode-menu))
:group 'vhdl-compile)
(defcustom vhdl-compiler "GHDL"
"*Specifies the VHDL compiler to be used for syntax analysis.
Select a compiler name from the ones defined in option `vhdl-compiler-alist'."
:type (let ((alist vhdl-compiler-alist) list)
(while alist
(push (list 'const (caar alist)) list)
(setq alist (cdr alist)))
(append '(choice) (nreverse list)))
:group 'vhdl-compile)
(defcustom vhdl-compile-use-local-error-regexp nil
"*Non-nil means use buffer-local `compilation-error-regexp-alist'.
In this case, only error message regexps for VHDL compilers are active if
compilation is started from a VHDL buffer. Otherwise, the error message
regexps are appended to the predefined global regexps, and all regexps are
active all the time. Note that by doing that, the predefined global regexps
might result in erroneous parsing of error messages for some VHDL compilers.
NOTE: Activate the new setting by restarting Emacs."
:type 'boolean
:group 'vhdl-compile)
(defcustom vhdl-makefile-default-targets '("all" "clean" "library")
"*List of default target names in Makefiles.
Automatically generated Makefiles include three default targets to compile
the entire design, clean the entire design and to create the design library.
This option allows to change the names of these targets to avoid conflicts
with other user Makefiles."
:type '(list (string :tag "Compile entire design")
(string :tag "Clean entire design ")
(string :tag "Create design library"))
:group 'vhdl-compile)
(defcustom vhdl-makefile-generation-hook nil
"*Functions to run at the end of Makefile generation.
Allows to insert user specific parts into a Makefile.
Example:
\(lambda nil
\(re-search-backward \"^# Rule for compiling entire design\")
\(insert \"# My target\\n\\n.MY_TARGET :\\n\\n\\n\"))"
:type 'hook
:group 'vhdl-compile)
(defcustom vhdl-default-library "work"
"*Name of default library.
Is overwritten by project settings if a project is active."
:type 'string
:group 'vhdl-compile)
(defgroup vhdl-project nil
"Customizations for projects."
:group 'vhdl)
(defcustom vhdl-project-alist
'(("Example 1" "Source files in two directories, custom library name, VHDL'87"
"~/example1/" ("src/system/" "src/components/") ""
(("ModelSim" "-87 \\2" "-f \\1 top_level" nil)
("Synopsys" "-vhdl87 \\2" "-f \\1 top_level" ((".*/datapath/.*" . "-optimize \\3") (".*_tb\\.vhd" . nil))))
"lib/" "example3_lib" "lib/example3/" "Makefile_\\2" "")
("Example 2" "Individual source files, multiple compilers in different directories"
"$EXAMPLE2/" ("vhdl/system.vhd" "vhdl/component_*.vhd") ""
nil "\\1/" "work" "\\1/work/" "Makefile" "")
("Example 3" "Source files in a directory tree, multiple compilers in same directory"
"/home/me/example3/" ("-r ./*/vhdl/") "/CVS/"
nil "./" "work" "work-\\1/" "Makefile-\\1" "\
-------------------------------------------------------------------------------
-- This is a multi-line project description
-- that can be used as a project dependent part of the file header.
"))
"*List of projects and their properties.
Name : name used in option `vhdl-project' to choose project
Title : title of project (single-line string)
Default directory: default project directory (absolute path)
Sources : a) source files : path + \"/\" + file name
b) directory : path + \"/\"
c) directory tree: \"-r \" + path + \"/\"
Exclude regexp : matches file/directory names to be excluded as sources
Compile options : project-specific options for each compiler
Compiler name : name of compiler for which these options are valid
Compile options: project-specific compiler options
(\"\\1\" inserts library name, \"\\2\" default options)
Make options: project-specific make options
(\"\\1\" inserts Makefile name, \"\\2\" default options)
Exceptions : file-specific exceptions
File name regexp: matches file names for which exceptions are valid
- Options : file-specific compiler options string
(\"\\1\" inserts library name, \"\\2\" default options,
\"\\3\" project-specific options)
- Do not compile: do not compile this file (in Makefile)
Compile directory: where compilation is run and the Makefile is placed
\(\"\\1\" inserts compiler ID string)
Library name : name of library (default is \"work\")
Library directory: path to library (\"\\1\" inserts compiler ID string)
Makefile name : name of Makefile
(\"\\1\" inserts compiler ID string, \"\\2\" library name)
Description : description of project (multi-line string)
Project title and description are used to insert into the file header (see
option `vhdl-file-header').
The default directory must have an absolute path (use `M-TAB' for completion).
All other paths can be absolute or relative to the default directory. All
paths must end with '/'.
The design units found in the sources (files and directories) are shown in the
hierarchy browser. Path and file name can contain wildcards `*' and `?' as
well as \"./\" and \"../\" (\"sh\" syntax). Paths can also be absolute.
Environment variables (e.g. \"$EXAMPLE2\") are resolved. If no sources are
specified, the default directory is taken as source directory. Otherwise,
the default directory is only taken as source directory if there is a sources
entry with the empty string or \"./\". Exclude regexp allows to filter out
specific file and directory names from the list of sources (e.g. CVS
directories).
Files are compiled in the compile directory. Makefiles are also placed into
the compile directory. Library directory specifies which directory the
compiler compiles into (used to generate the Makefile).
Since different compile/library directories and Makefiles may exist for
different compilers within one project, these paths and names allow the
insertion of a compiler-dependent ID string (defined in `vhdl-compiler-alist').
Compile options, compile directory, library directory, and Makefile name
overwrite the settings of the current compiler.
File-specific compiler options (highest priority) overwrite project-specific
options which overwrite default options (lowest priority). Lower priority
options can be inserted in higher priority options. This allows to reuse
default options (e.g. \"-file\") in project- or file-specific options (e.g.
\"-93 -file\").
NOTE: Reflect the new setting in the choice list of option `vhdl-project'
by restarting Emacs."
:type `(repeat
(list :tag "Project" :indent 2
(string :tag "Name ")
(string :tag "Title ")
(directory :tag "Default directory"
:validate vhdl-widget-directory-validate
,(abbreviate-file-name default-directory))
(repeat :tag "Sources " :indent 4
(directory :format " %v" "./"))
(regexp :tag "Exclude regexp ")
(repeat
:tag "Compile options " :indent 4
(list :tag "Compiler" :indent 6
,(let ((alist vhdl-compiler-alist) list)
(while alist
(push (list 'const (caar alist)) list)
(setq alist (cdr alist)))
(append '(choice :tag "Compiler name")
(nreverse list)))
(string :tag "Compile options" "\\2")
(string :tag "Make options " "\\2")
(repeat
:tag "Exceptions " :indent 8
(cons :format "%v"
(regexp :tag "File name regexp ")
(choice :format "%[Value Menu%] %v"
(string :tag "Options" "\\3")
(const :tag "Do not compile" nil))))))
(directory :tag "Compile directory"
:validate vhdl-widget-directory-validate "./")
(string :tag "Library name " "work")
(directory :tag "Library directory"
:validate vhdl-widget-directory-validate "work/")
(file :tag "Makefile name " "Makefile")
(string :tag "Description: (type `C-j' for newline)"
:format "%t\n%v\n")))
:set (lambda (variable value)
(vhdl-custom-set variable value
'vhdl-update-mode-menu
'vhdl-speedbar-refresh))
:group 'vhdl-project)
(defcustom vhdl-project nil
"*Specifies the default for the current project.
Select a project name from the ones defined in option `vhdl-project-alist'.
Is used to determine the project title and description to be inserted in file
headers and the source files/directories to be scanned in the hierarchy
browser. The current project can also be changed temporarily in the menu."
:type (let ((alist vhdl-project-alist) list)
(while alist
(push (list 'const (caar alist)) list)
(setq alist (cdr alist)))
(append '(choice (const :tag "None" nil) (const :tag "--"))
(nreverse list)))
:group 'vhdl-project)
(defcustom vhdl-project-file-name '("\\1.prj")
"*List of file names/paths for importing/exporting project setups.
\"\\1\" is replaced by the project name (SPC is replaced by `_'), \"\\2\" is
replaced by the user name (allows to have user-specific project setups).
The first entry is used as file name to import/export individual project
setups. All entries are used to automatically import project setups at
startup (see option `vhdl-project-auto-load'). Projects loaded from the
first entry are automatically made current. Hint: specify local project
setups in first entry, global setups in following entries; loading a local
project setup will make it current, while loading the global setups
is done without changing the current project.
Names can also have an absolute path (i.e. project setups can be stored
in global directories)."
:type '(repeat (string :tag "File name" "\\1.prj"))
:group 'vhdl-project)
(defcustom vhdl-project-auto-load '(startup)
"*Automatically load project setups from files.
All project setup files that match the file names specified in option
`vhdl-project-file-name' are automatically loaded. The project of the
\(alphabetically) last loaded setup of the first `vhdl-project-file-name'
entry is activated.
A project setup file can be obtained by exporting a project (see menu).
At startup: project setup file is loaded at Emacs startup"
:type '(set (const :tag "At startup" startup))
:group 'vhdl-project)
(defcustom vhdl-project-sort t
"*Non-nil means projects are displayed in alphabetical order."
:type 'boolean
:group 'vhdl-project)
(defgroup vhdl-style nil
"Customizations for coding styles."
:group 'vhdl
:group 'vhdl-template
:group 'vhdl-port
:group 'vhdl-compose)
(defcustom vhdl-standard '(93 nil)
"*VHDL standards used.
Basic standard:
VHDL'87 : IEEE Std 1076-1987
VHDL'93/02 : IEEE Std 1076-1993/2002
VHDL'08 : IEEE Std 1076-2008
Additional standards:
VHDL-AMS : IEEE Std 1076.1 (analog-mixed-signal)
Math packages: IEEE Std 1076.2 (`math_real', `math_complex')
NOTE: Activate the new setting in a VHDL buffer by using the menu entry
\"Activate Options\"."
:type '(list (choice :tag "Basic standard"
(const :tag "VHDL'87" 87)
(const :tag "VHDL'93/02" 93)
(const :tag "VHDL'08" 08))
(set :tag "Additional standards" :indent 2
(const :tag "VHDL-AMS" ams)
(const :tag "Math packages" math)))
:set (lambda (variable value)
(vhdl-custom-set variable value
'vhdl-template-map-init
'vhdl-mode-abbrev-table-init
'vhdl-template-construct-alist-init
'vhdl-template-package-alist-init
'vhdl-update-mode-menu
'vhdl-words-init 'vhdl-font-lock-init))
:group 'vhdl-style)
(defcustom vhdl-basic-offset 2
"*Amount of basic offset used for indentation.
This value is used by + and - symbols in `vhdl-offsets-alist'."
:type 'integer
:group 'vhdl-style)
(defcustom vhdl-upper-case-keywords nil
"*Non-nil means convert keywords to upper case.
This is done when typed or expanded or by the fix case functions."
:type 'boolean
:set (lambda (variable value)
(vhdl-custom-set variable value 'vhdl-abbrev-list-init))
:group 'vhdl-style)
(defcustom vhdl-upper-case-types nil
"*Non-nil means convert standardized types to upper case.
This is done when expanded or by the fix case functions."
:type 'boolean
:set (lambda (variable value)
(vhdl-custom-set variable value 'vhdl-abbrev-list-init))
:group 'vhdl-style)
(defcustom vhdl-upper-case-attributes nil
"*Non-nil means convert standardized attributes to upper case.
This is done when expanded or by the fix case functions."
:type 'boolean
:set (lambda (variable value)
(vhdl-custom-set variable value 'vhdl-abbrev-list-init))
:group 'vhdl-style)
(defcustom vhdl-upper-case-enum-values nil
"*Non-nil means convert standardized enumeration values to upper case.
This is done when expanded or by the fix case functions."
:type 'boolean
:set (lambda (variable value)
(vhdl-custom-set variable value 'vhdl-abbrev-list-init))
:group 'vhdl-style)
(defcustom vhdl-upper-case-constants t
"*Non-nil means convert standardized constants to upper case.
This is done when expanded."
:type 'boolean
:set (lambda (variable value)
(vhdl-custom-set variable value 'vhdl-abbrev-list-init))
:group 'vhdl-style)
(defcustom vhdl-use-direct-instantiation 'standard
"*Non-nil means use VHDL'93 direct component instantiation.
Never : never
Standard: only in VHDL standards that allow it (VHDL'93 and higher)
Always : always"
:type '(choice (const :tag "Never" never)
(const :tag "Standard" standard)
(const :tag "Always" always))
:group 'vhdl-style)
(defcustom vhdl-array-index-record-field-in-sensitivity-list t
"*Non-nil means include array indices / record fields in sensitivity list.
If a signal read in a process is a record field or pointed to by an array
index, the record field or array index is included with the record name in
the sensitivity list (e.g. \"in1(0)\", \"in2.f0\").
Otherwise, only the record name is included (e.g. \"in1\", \"in2\")."
:type 'boolean
:group 'vhdl-style)
(defgroup vhdl-naming nil
"Customizations for naming conventions."
:group 'vhdl)
(defcustom vhdl-entity-file-name '(".*" . "\\&")
(concat
"*Specifies how the entity file name is obtained.
The entity file name can be obtained by modifying the entity name (e.g.
attaching or stripping off a substring). The file extension is automatically
taken from the file name of the current buffer."
vhdl-name-doc-string)
:type '(cons (regexp :tag "From regexp")
(string :tag "To string "))
:group 'vhdl-naming
:group 'vhdl-compose)
(defcustom vhdl-architecture-file-name '("\\(.*\\) \\(.*\\)" . "\\1_\\2")
(concat
"*Specifies how the architecture file name is obtained.
The architecture file name can be obtained by modifying the entity
and/or architecture name (e.g. attaching or stripping off a substring). The
file extension is automatically taken from the file name of the current
buffer. The string that is matched against the regexp is the concatenation
of the entity and the architecture name separated by a space. This gives
access to both names (see default setting as example)."
vhdl-name-doc-string)
:type '(cons (regexp :tag "From regexp")
(string :tag "To string "))
:group 'vhdl-naming
:group 'vhdl-compose)
(defcustom vhdl-configuration-file-name '(".*" . "\\&")
(concat
"*Specifies how the configuration file name is obtained.
The configuration file name can be obtained by modifying the configuration
name (e.g. attaching or stripping off a substring). The file extension is
automatically taken from the file name of the current buffer."
vhdl-name-doc-string)
:type '(cons (regexp :tag "From regexp")
(string :tag "To string "))
:group 'vhdl-naming
:group 'vhdl-compose)
(defcustom vhdl-package-file-name '(".*" . "\\&")
(concat
"*Specifies how the package file name is obtained.
The package file name can be obtained by modifying the package name (e.g.
attaching or stripping off a substring). The file extension is automatically
taken from the file name of the current buffer. Package files can be created
in a different directory by prepending a relative or absolute path to the
file name."
vhdl-name-doc-string)
:type '(cons (regexp :tag "From regexp")
(string :tag "To string "))
:group 'vhdl-naming
:group 'vhdl-compose)
(defcustom vhdl-file-name-case 'identity
"*Specifies how to change case for obtaining file names.
When deriving a file name from a VHDL unit name, case can be changed as
follows:
As Is: case is not changed (taken as is)
Lower Case: whole name is changed to lower case
Upper Case: whole name is changed to upper case
Capitalize: first letter of each word in name is capitalized"
:type '(choice (const :tag "As Is" identity)
(const :tag "Lower Case" downcase)
(const :tag "Upper Case" upcase)
(const :tag "Capitalize" capitalize))
:group 'vhdl-naming
:group 'vhdl-compose)
(defgroup vhdl-template nil
"Customizations for electrification."
:group 'vhdl)
(defcustom vhdl-electric-keywords '(vhdl user)
"*Type of keywords for which electrification is enabled.
VHDL keywords: invoke built-in templates
User keywords: invoke user models (see option `vhdl-model-alist')"
:type '(set (const :tag "VHDL keywords" vhdl)
(const :tag "User model keywords" user))
:set (lambda (variable value)
(vhdl-custom-set variable value 'vhdl-mode-abbrev-table-init))
:group 'vhdl-template)
(defcustom vhdl-optional-labels 'process
"*Constructs for which labels are to be queried.
Template generators prompt for optional labels for:
None : no constructs
Processes only: processes only (also procedurals in VHDL-AMS)
All constructs: all constructs with optional labels and keyword END"
:type '(choice (const :tag "None" none)
(const :tag "Processes only" process)
(const :tag "All constructs" all))
:group 'vhdl-template)
(defcustom vhdl-insert-empty-lines 'unit
"*Specifies whether to insert empty lines in some templates.
This improves readability of code. Empty lines are inserted in:
None : no constructs
Design units only: entities, architectures, configurations, packages only
All constructs : also all constructs with BEGIN...END parts
Replaces option `vhdl-additional-empty-lines'."
:type '(choice (const :tag "None" none)
(const :tag "Design units only" unit)
(const :tag "All constructs" all))
:group 'vhdl-template
:group 'vhdl-port
:group 'vhdl-compose)
(defcustom vhdl-argument-list-indent nil
"*Non-nil means indent argument lists relative to opening parenthesis.
That is, argument, association, and port lists start on the same line as the
opening parenthesis and subsequent lines are indented accordingly.
Otherwise, lists start on a new line and are indented as normal code."
:type 'boolean
:group 'vhdl-template
:group 'vhdl-port
:group 'vhdl-compose)
(defcustom vhdl-association-list-with-formals t
"*Non-nil means write association lists with formal parameters.
Templates prompt for formal and actual parameters (ports/generics).
When pasting component instantiations, formals are included.
If nil, only a list of actual parameters is entered."
:type 'boolean
:group 'vhdl-template
:group 'vhdl-port
:group 'vhdl-compose)
(defcustom vhdl-conditions-in-parenthesis nil
"*Non-nil means place parenthesis around condition expressions."
:type 'boolean
:group 'vhdl-template)
(defcustom vhdl-sensitivity-list-all t
"*Non-nil means use 'all' keyword in sensitivity list."
:type 'boolean
:group 'vhdl-template)
(defcustom vhdl-zero-string "'0'"
"*String to use for a logic zero."
:type 'string
:group 'vhdl-template)
(defcustom vhdl-one-string "'1'"
"*String to use for a logic one."
:type 'string
:group 'vhdl-template)
(defgroup vhdl-header nil
"Customizations for file header."
:group 'vhdl-template
:group 'vhdl-compose)
(defcustom vhdl-file-header "\
-------------------------------------------------------------------------------
-- Title : <title string>
-- Project : <project>
-------------------------------------------------------------------------------
-- File : <filename>
-- Author : <author>
-- Company : <company>
-- Created : <date>
-- Last update: <date>
-- Platform : <platform>
-- Standard : <standard>
<projectdesc>-------------------------------------------------------------------------------
-- Description: <cursor>
<copyright>-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- <date> 1.0 <login>\tCreated
-------------------------------------------------------------------------------
"
"*String or file to insert as file header.
If the string specifies an existing file name, the contents of the file is
inserted, otherwise the string itself is inserted as file header.
Type `C-j' for newlines.
If the header contains RCS keywords, they may be written as <RCS>Keyword<RCS>
if the header needs to be version controlled.