extern "/Users/calebkim/learning/calyx/primitives/binary_operators.sv" {
  comb primitive std_fp_add<"share"=1>[WIDTH, INT_WIDTH, FRAC_WIDTH](@data left: WIDTH, @data right: WIDTH) -> (out: WIDTH);
  comb primitive std_fp_sub<"share"=1>[WIDTH, INT_WIDTH, FRAC_WIDTH](@data left: WIDTH, @data right: WIDTH) -> (out: WIDTH);
  primitive std_fp_mult_pipe<"state_share"=1>[WIDTH, INT_WIDTH, FRAC_WIDTH](@clk clk: 1, @reset reset: 1, @write_together @static(3) @go go: 1, @write_together @data left: WIDTH, @write_together @data right: WIDTH) -> (@stable out: WIDTH, @done done: 1);
  primitive std_fp_div_pipe<"state_share"=1>[WIDTH, INT_WIDTH, FRAC_WIDTH](@clk clk: 1, @reset reset: 1, @write_together @go go: 1, @write_together @data left: WIDTH, @write_together @data right: WIDTH) -> (@stable out_remainder: WIDTH, @stable out_quotient: WIDTH, @done done: 1);
  comb primitive std_fp_gt<"share"=1>[WIDTH, INT_WIDTH, FRAC_WIDTH](@data left: WIDTH, @data right: WIDTH) -> (out: 1);
  comb primitive std_fp_sadd<"share"=1>[WIDTH, INT_WIDTH, FRAC_WIDTH](@data left: WIDTH, @data right: WIDTH) -> (out: WIDTH);
  comb primitive std_fp_ssub<"share"=1>[WIDTH, INT_WIDTH, FRAC_WIDTH](@data left: WIDTH, @data right: WIDTH) -> (out: WIDTH);
  primitive std_fp_smult_pipe<"state_share"=1>[WIDTH, INT_WIDTH, FRAC_WIDTH](@clk clk: 1, @reset reset: 1, @write_together @static(3) @go go: 1, @write_together @data left: WIDTH, @write_together @data right: WIDTH) -> (@stable out: WIDTH, @done done: 1);
  primitive std_fp_sdiv_pipe<"state_share"=1>[WIDTH, INT_WIDTH, FRAC_WIDTH](@clk clk: 1, @reset reset: 1, @write_together @go go: 1, @write_together @data left: WIDTH, @write_together @data right: WIDTH) -> (@stable out_remainder: WIDTH, @stable out_quotient: WIDTH, @done done: 1);
  comb primitive std_fp_sgt<"share"=1>[WIDTH, INT_WIDTH, FRAC_WIDTH](@data left: WIDTH, @data right: WIDTH) -> (out: 1);
  comb primitive std_fp_slt<"share"=1>[WIDTH, INT_WIDTH, FRAC_WIDTH](@data left: WIDTH, @data right: WIDTH) -> (out: 1);
  primitive std_mult_pipe<"state_share"=1>[WIDTH](@clk clk: 1, @reset reset: 1, @write_together @static(3) @go go: 1, @write_together @data left: WIDTH, @write_together @data right: WIDTH) -> (@stable out: WIDTH, @done done: 1);
  primitive std_div_pipe<"state_share"=1>[WIDTH](@clk clk: 1, @reset reset: 1, @write_together @go go: 1, @write_together @data left: WIDTH, @write_together @data right: WIDTH) -> (@stable out_quotient: WIDTH, @stable out_remainder: WIDTH, @done done: 1);
  comb primitive std_sadd<"share"=1>[WIDTH](@data left: WIDTH, @data right: WIDTH) -> (out: WIDTH);
  comb primitive std_ssub<"share"=1>[WIDTH](@data left: WIDTH, @data right: WIDTH) -> (out: WIDTH);
  primitive std_smult_pipe<"state_share"=1>[WIDTH](@clk clk: 1, @reset reset: 1, @write_together @static(3) @go go: 1, @write_together @data left: WIDTH, @write_together @data right: WIDTH) -> (@stable out: WIDTH, @done done: 1);
  primitive std_sdiv_pipe[WIDTH](@clk clk: 1, @reset reset: 1, @write_together @go go: 1, @write_together @data left: WIDTH, @write_together @data right: WIDTH) -> (out_quotient: WIDTH, out_remainder: WIDTH, @done done: 1);
  comb primitive std_sgt<"share"=1>[WIDTH](@data left: WIDTH, @data right: WIDTH) -> (out: 1);
  comb primitive std_slt<"share"=1>[WIDTH](@data left: WIDTH, @data right: WIDTH) -> (out: 1);
  comb primitive std_seq<"share"=1>[WIDTH](@data left: WIDTH, @data right: WIDTH) -> (out: 1);
  comb primitive std_sneq<"share"=1>[WIDTH](@data left: WIDTH, @data right: WIDTH) -> (out: 1);
  comb primitive std_sge<"share"=1>[WIDTH](@data left: WIDTH, @data right: WIDTH) -> (out: 1);
  comb primitive std_sle<"share"=1>[WIDTH](@data left: WIDTH, @data right: WIDTH) -> (out: 1);
  comb primitive std_slsh<"share"=1>[WIDTH](@data left: WIDTH, @data right: WIDTH) -> (out: WIDTH);
  comb primitive std_srsh<"share"=1>[WIDTH](@data left: WIDTH, @data right: WIDTH) -> (out: WIDTH);
}
extern "/Users/calebkim/learning/calyx/primitives/sync.sv" {
  primitive std_sync_reg[WIDTH](@write_together in_0: WIDTH, @write_together(2) in_1: WIDTH, read_en_0: 1, read_en_1: 1, @write_together write_en_0: 1, @write_together(2) write_en_1: 1, @clk clk: 1, @reset reset: 1) -> (out_0: WIDTH, out_1: WIDTH, write_done_0: 1, write_done_1: 1, read_done_0: 1, read_done_1: 1, peek: WIDTH);
}
extern "/Users/calebkim/learning/calyx/primitives/core.sv" {
  comb primitive std_slice<"share"=1>[IN_WIDTH, OUT_WIDTH](@data in: IN_WIDTH) -> (out: OUT_WIDTH);
  comb primitive std_pad<"share"=1>[IN_WIDTH, OUT_WIDTH](@data in: IN_WIDTH) -> (out: OUT_WIDTH);
  comb primitive std_cat<"share"=1>[LEFT_WIDTH, RIGHT_WIDTH, OUT_WIDTH](@data left: LEFT_WIDTH, @data right: RIGHT_WIDTH) -> (out: OUT_WIDTH);
  comb primitive std_not<"share"=1>[WIDTH](@data in: WIDTH) -> (out: WIDTH);
  comb primitive std_and<"share"=1>[WIDTH](@data left: WIDTH, @data right: WIDTH) -> (out: WIDTH);
  comb primitive std_or<"share"=1>[WIDTH](@data left: WIDTH, @data right: WIDTH) -> (out: WIDTH);
  comb primitive std_xor<"share"=1>[WIDTH](@data left: WIDTH, @data right: WIDTH) -> (out: WIDTH);
  comb primitive std_sub<"share"=1>[WIDTH](@data left: WIDTH, @data right: WIDTH) -> (out: WIDTH);
  comb primitive std_gt<"share"=1>[WIDTH](@data left: WIDTH, @data right: WIDTH) -> (out: 1);
  comb primitive std_lt<"share"=1>[WIDTH](@data left: WIDTH, @data right: WIDTH) -> (out: 1);
  comb primitive std_eq<"share"=1>[WIDTH](@data left: WIDTH, @data right: WIDTH) -> (out: 1);
  comb primitive std_neq<"share"=1>[WIDTH](@data left: WIDTH, @data right: WIDTH) -> (out: 1);
  comb primitive std_ge<"share"=1>[WIDTH](@data left: WIDTH, @data right: WIDTH) -> (out: 1);
  comb primitive std_le<"share"=1>[WIDTH](@data left: WIDTH, @data right: WIDTH) -> (out: 1);
  comb primitive std_lsh<"share"=1>[WIDTH](@data left: WIDTH, @data right: WIDTH) -> (out: WIDTH);
  comb primitive std_rsh<"share"=1>[WIDTH](@data left: WIDTH, @data right: WIDTH) -> (out: WIDTH);
  comb primitive std_mux<"share"=1>[WIDTH](@data cond: 1, @data tru: WIDTH, @data fal: WIDTH) -> (out: WIDTH);
  primitive std_mem_d1[WIDTH, SIZE, IDX_SIZE](@read_together addr0: IDX_SIZE, @write_together @data write_data: WIDTH, @write_together @static @go write_en: 1, @clk clk: 1, @reset reset: 1) -> (@read_together read_data: WIDTH, @done done: 1);
  primitive std_mem_d2[WIDTH, D0_SIZE, D1_SIZE, D0_IDX_SIZE, D1_IDX_SIZE](@read_together @write_together(2) addr0: D0_IDX_SIZE, @read_together @write_together(2) addr1: D1_IDX_SIZE, @write_together @data write_data: WIDTH, @write_together @static @go write_en: 1, @clk clk: 1, @reset reset: 1) -> (@read_together read_data: WIDTH, @done done: 1);
  primitive std_mem_d3[WIDTH, D0_SIZE, D1_SIZE, D2_SIZE, D0_IDX_SIZE, D1_IDX_SIZE, D2_IDX_SIZE](@read_together @write_together(2) addr0: D0_IDX_SIZE, @read_together @write_together(2) addr1: D1_IDX_SIZE, @read_together @write_together(2) addr2: D2_IDX_SIZE, @write_together @data write_data: WIDTH, @write_together @static @go write_en: 1, @clk clk: 1, @reset reset: 1) -> (@read_together read_data: WIDTH, @done done: 1);
  primitive std_mem_d4[WIDTH, D0_SIZE, D1_SIZE, D2_SIZE, D3_SIZE, D0_IDX_SIZE, D1_IDX_SIZE, D2_IDX_SIZE, D3_IDX_SIZE](@read_together @write_together(2) addr0: D0_IDX_SIZE, @read_together @write_together(2) addr1: D1_IDX_SIZE, @read_together @write_together(2) addr2: D2_IDX_SIZE, @read_together @write_together(2) addr3: D3_IDX_SIZE, @write_together @data write_data: WIDTH, @write_together @static @go write_en: 1, @clk clk: 1) -> (@read_together read_data: WIDTH, @done done: 1);
}
  primitive undef<"share"=1>[WIDTH]() -> (out: WIDTH){ 
    assign out = 'x;
 };
  comb primitive std_const<"share"=1>[WIDTH, VALUE]() -> (out: WIDTH){ 
    assign out = VALUE;
 };
  comb primitive std_wire<"share"=1>[WIDTH](@data in: WIDTH) -> (out: WIDTH){ 
    assign out = in;
 };
  comb primitive std_add<"share"=1>[WIDTH](@data left: WIDTH, @data right: WIDTH) -> (out: WIDTH){ 
  assign out = left + right;
 };
  primitive std_reg<"state_share"=1>[WIDTH](@write_together @data in: WIDTH, @write_together @static @go write_en: 1, @clk clk: 1, @reset reset: 1) -> (@stable out: WIDTH, @done done: 1){ 
  always_ff @(posedge clk) begin
    if (reset) begin
       out <= 0;
       done <= 0;
    end else if (write_en) begin
      out <= in;
      done <= 1'd1;
    end else done <= 1'd0;
  end
 };
component main(@go go: 1, @clk clk: 1, @reset reset: 1) -> (@done done: 1) {
  cells {
    @external @data in_0 = std_mem_d1(32, 18, 32);
    @external @data in_1 = std_mem_d1(32, 18, 32);
    @external @data out = std_mem_d1(32, 1, 32);
    @data idx_0 = std_reg(32);
    @data idx_1 = std_reg(32);
    @data point_0 = std_reg(32);
    @data point_1 = std_reg(32);
    @data val_0 = std_reg(32);
    @data val_1 = std_reg(32);
    @data val_out = std_reg(32);
    @control lt_0 = std_lt(32);
    @data lt_0_reg = std_reg(1);
    @control lt_1 = std_lt(32);
    @data lt_1_reg = std_reg(1);
    @control incr_0 = std_add(32);
    @control incr_1 = std_add(32);
    @data add = std_add(32);
    @data mult = std_smult_pipe(32);
    @control fwd_0 = std_lt(32);
    @control fwd_1 = std_lt(32);
    @control eq = std_eq(1);
    @control signal = std_or(1);
    @data no_use_0 = std_reg(1);
    @data no_use_1 = std_reg(1);
    @data flag = std_reg(1);
    @data flag_reg = std_reg(1);
    @data sign = std_reg(1);
    @control eq0 = std_eq(1);
    @generated s = std_wire(1);
    @generated bar = std_reg(1);
    @generated bar0 = std_reg(1);
    @generated comb_reg = std_reg(1);
    @generated comb_reg0 = std_reg(1);
    @generated comb_reg1 = std_reg(1);
    @generated comb_reg2 = std_reg(1);
    @generated comb_reg3 = std_reg(1);
  }
  wires {
    group wait_compute {
      flag_reg.in = 1'd1;
      flag_reg.write_en = flag.out ? 1'd1;
      wait_compute[done] = flag_reg.done;
    }
    group initialize_idx {
      idx_0.in = in_0.read_data;
      in_0.addr0 = 32'd0;
      idx_0.write_en = 1'd1;
      idx_1.in = in_1.read_data;
      in_1.addr0 = 32'd0;
      idx_1.write_en = 1'd1;
      initialize_idx[done] = idx_0.done & idx_1.done ? 1'd1;
    }
    group initialize_val {
      val_0.in = in_0.read_data;
      in_0.addr0 = 32'd1;
      val_0.write_en = 1'd1;
      val_1.in = in_1.read_data;
      in_1.addr0 = 32'd1;
      val_1.write_en = 1'd1;
      initialize_val[done] = val_0.done & val_1.done ? 1'd1;
    }
    group compute_product {
      mult.go = 1'd1;
      mult.left = val_0.out;
      mult.right = val_1.out;
      val_out.in = mult.done ? mult.out;
      val_out.write_en = mult.done ? 1'd1;
      compute_product[done] = val_out.done;
    }
    group barrier {
      bar.in = 1'd1;
      bar.write_en = 1'd1;
      barrier[done] = s.out;
    }
    group barrier0 {
      bar0.in = 1'd1;
      bar0.write_en = 1'd1;
      barrier0[done] = s.out;
    }
    static<1> group in_barrier0 {
      eq0.left = sign.out;
      eq0.right = 1'd1;
      comb_reg.in = eq0.out;
      comb_reg.write_en = 1'd1;
    }
    static<1> group has_computing_job0 {
      eq.left = flag.out;
      eq.right = 1'd1;
      comb_reg0.in = eq.out;
      comb_reg0.write_en = 1'd1;
    }
    static<1> group chase_00 {
      lt_0.left = idx_0.out;
      lt_0.right = idx_1.out;
      comb_reg1.in = lt_0.out;
      comb_reg1.write_en = 1'd1;
    }
    static<1> group chase_10 {
      lt_0.left = idx_1.out;
      lt_0.right = idx_0.out;
      comb_reg2.in = lt_0.out;
      comb_reg2.write_en = 1'd1;
    }
    static<1> group comp0 {
      fwd_0.left = idx_0.out;
      fwd_0.right = 32'd16;
      fwd_1.left = idx_1.out;
      fwd_1.right = 32'd16;
      signal.left = fwd_0.out;
      signal.right = fwd_1.out;
      comb_reg3.in = signal.out;
      comb_reg3.write_en = 1'd1;
    }
    static<1> group chase_0_reg0 {
      lt_0.left = idx_0.out;
      lt_0.right = idx_1.out;
      lt_0_reg.in = lt_0.out;
      lt_0_reg.write_en = 1'd1;
    }
    static<1> group forward_pointer_00 {
      incr_0.left = 32'd2;
      incr_0.right = point_0.out;
      point_0.in = incr_0.out;
      point_0.write_en = 1'd1;
    }
    static<1> group fwd_idx_00 {
      idx_0.in = in_0.read_data;
      in_0.addr0 = point_0.out;
      idx_0.write_en = 1'd1;
    }
    static<1> group val_to_reg_00 {
      incr_0.left = 32'd1;
      incr_0.right = point_0.out;
      val_0.in = in_0.read_data;
      in_0.addr0 = incr_0.out;
      val_0.write_en = 1'd1;
    }
    static<1> group sign_complete0 {
      sign.in = 1'd0;
      sign.write_en = 1'd1;
    }
    static<1> group clear1 {
      bar.in = 1'd0;
      bar.write_en = 1'd1;
    }
    static<1> group chase_1_reg0 {
      lt_0.left = idx_1.out;
      lt_0.right = idx_0.out;
      lt_0_reg.in = lt_0.out;
      lt_0_reg.write_en = 1'd1;
    }
    static<1> group forward_pointer_10 {
      incr_0.left = 32'd2;
      incr_0.right = point_1.out;
      point_1.in = incr_0.out;
      point_1.write_en = 1'd1;
    }
    static<1> group fwd_idx_10 {
      idx_1.in = in_1.read_data;
      in_1.addr0 = point_1.out;
      idx_1.write_en = 1'd1;
    }
    static<1> group val_to_reg_10 {
      incr_0.left = 32'd1;
      incr_0.right = point_1.out;
      val_1.in = in_1.read_data;
      in_1.addr0 = incr_0.out;
      val_1.write_en = 1'd1;
    }
    static<1> group sign_complete1 {
      sign.in = 1'd0;
      sign.write_en = 1'd1;
    }
    static<1> group clear2 {
      bar.in = 1'd0;
      bar.write_en = 1'd1;
    }
    static<2> group my_group {
      flag.in = %0 ? 1'd1;
      flag.write_en = %0 ? 1'd1;
      sign.in = %1 ? 1'd1;
      sign.write_en = %1 ? 1'd1;
    }
    static<1> group forward_pointer_01 {
      incr_0.left = 32'd2;
      incr_0.right = point_0.out;
      point_0.in = incr_0.out;
      point_0.write_en = 1'd1;
    }
    static<1> group fwd_idx_01 {
      idx_0.in = in_0.read_data;
      in_0.addr0 = point_0.out;
      idx_0.write_en = 1'd1;
    }
    static<1> group val_to_reg_01 {
      incr_0.left = 32'd1;
      incr_0.right = point_0.out;
      val_0.in = in_0.read_data;
      in_0.addr0 = incr_0.out;
      val_0.write_en = 1'd1;
    }
    static<1> group add_to_out0 {
      add.left = out.read_data;
      out.addr0 = 32'd0;
      add.right = val_out.out;
      out.write_data = add.out;
      out.write_en = 1'd1;
    }
    static<1> group signal_complete0 {
      flag.in = 1'd0;
      flag.write_en = 1'd1;
    }
    static<1> group clear00 {
      bar0.in = 1'd0;
      bar0.write_en = 1'd1;
    }
    static<1> group add_to_out1 {
      add.left = out.read_data;
      out.addr0 = 32'd0;
      add.right = val_out.out;
      out.write_data = add.out;
      out.write_en = 1'd1;
    }
    s.in = bar.out & bar0.out ? 1'd1;
  }

  control {
    seq {
      initialize_idx;
      initialize_val;
      par {
        seq {
          comp0;
          while comb_reg3.out {
            seq {
              chase_0_reg0;
              if lt_0_reg.out {
                seq {
                  chase_00;
                  while comb_reg1.out {
                    static<3> seq  {
                      static<2> seq  {
                        forward_pointer_00;
                        fwd_idx_00;
                      }
                      chase_00;
                    }
                  }
                  val_to_reg_00;
                  in_barrier0;
                  if comb_reg.out {
                    seq {
                      sign_complete0;
                      barrier;
                      clear1;
                    }
                  }
                }
              } else {
                seq {
                  chase_1_reg0;
                  if lt_0_reg.out {
                    seq {
                      chase_10;
                      while comb_reg2.out {
                        static<3> seq  {
                          static<2> seq  {
                            forward_pointer_10;
                            fwd_idx_10;
                          }
                          chase_10;
                        }
                      }
                      val_to_reg_10;
                      in_barrier0;
                      if comb_reg.out {
                        seq {
                          sign_complete1;
                          barrier;
                          clear2;
                        }
                      }
                    }
                  } else {
                    seq  {
                      my_group;
                      forward_pointer_01;
                      static<2> seq {
                        fwd_idx_01;
                        val_to_reg_01;
                      }
                    }
                  }
                }
              }
              comp0;
            }
          }
        }
        seq {
          comp0;
          while comb_reg3.out {
            seq {
              has_computing_job0;
              if comb_reg0.out {
                seq {
                  compute_product;
                  add_to_out0;
                  signal_complete0;
                  barrier0;
                  clear00;
                }
              } else {
                wait_compute;
              }
              comp0;
            }
          }
        }
      }
      compute_product;
      add_to_out1;
    }
  }
}