From 6326407583c18fefa0befb117733ee987b0c712e Mon Sep 17 00:00:00 2001 From: Sven Dildick Date: Tue, 22 Sep 2020 22:30:42 -0500 Subject: [PATCH 1/2] Remove CSCCommonTrigger --- DQM/L1TMonitor/python/L1TCSCTF_cff.py | 5 - DQM/L1TMonitor/python/L1TMonitor_cff.py | 4 +- .../CSCTFRawToDigi/python/csctfpacker_cfi.py | 5 +- .../python/csctfunpacker_cfi.py | 5 +- L1Trigger/CSCCommonTrigger/BuildFile.xml | 5 - .../interface/CSCFrontRearLUT.h | 20 - .../interface/CSCPatternLUT.h | 32 - L1Trigger/CSCCommonTrigger/interface/vlib.h | 398 ------ L1Trigger/CSCCommonTrigger/interface/vmac.h | 209 --- .../CSCCommonTrigger/src/CSCFrontRearLUT.cc | 39 - .../CSCCommonTrigger/src/CSCPatternLUT.cc | 8 - L1Trigger/CSCCommonTrigger/src/vlib.cc | 1216 ----------------- L1Trigger/CSCTrackFinder/BuildFile.xml | 2 +- L1Trigger/CSCTrackFinder/doc/convert_vpp | 165 --- .../CSCTrackFinder/python/csctfDigis_cfi.py | 2 +- .../python/csctfTrackDigis_cfi.py | 2 +- .../src/CSCSectorReceiverLUT.cc | 5 +- .../src/CSCSectorReceiverMiniLUT.cc | 3 +- L1Trigger/CSCTriggerPrimitives/BuildFile.xml | 2 +- L1Trigger/CSCTriggerPrimitives/README.md | 2 +- .../interface/CSCPatternBank.h | 13 + .../interface/CSCPatternLUT.h | 21 + .../plugins/BuildFile.xml | 1 - .../python/CSCCommonTrigger_cfi.py | 0 .../python/cscTriggerPrimitiveDigis_cfi.py | 2 +- .../src/CSCPatternBank.cc | 7 + .../test/macros/CCLUTLinearFitWriter.cpp | 1 - .../python/L1MuonEmulator_cff.py | 1 - L1Trigger/L1TMuon/BuildFile.xml | 2 +- L1Trigger/L1TMuon/python/simDigis_cff.py | 1 - L1Trigger/L1TMuon/src/GeometryTranslator.cc | 4 +- .../L1TMuonEndCap/test/tools/MakeCoordLUT.cc | 4 - L1Trigger/L1TMuonOverlap/BuildFile.xml | 2 +- .../L1TMuonOverlap/src/AngleConverter.cc | 4 +- Utilities/ReleaseScripts/scripts/git-publish | 2 +- 35 files changed, 61 insertions(+), 2133 deletions(-) delete mode 100644 DQM/L1TMonitor/python/L1TCSCTF_cff.py delete mode 100644 L1Trigger/CSCCommonTrigger/BuildFile.xml delete mode 100644 L1Trigger/CSCCommonTrigger/interface/CSCFrontRearLUT.h delete mode 100644 L1Trigger/CSCCommonTrigger/interface/CSCPatternLUT.h delete mode 100644 L1Trigger/CSCCommonTrigger/interface/vlib.h delete mode 100644 L1Trigger/CSCCommonTrigger/interface/vmac.h delete mode 100644 L1Trigger/CSCCommonTrigger/src/CSCFrontRearLUT.cc delete mode 100644 L1Trigger/CSCCommonTrigger/src/CSCPatternLUT.cc delete mode 100644 L1Trigger/CSCCommonTrigger/src/vlib.cc delete mode 100755 L1Trigger/CSCTrackFinder/doc/convert_vpp create mode 100644 L1Trigger/CSCTriggerPrimitives/interface/CSCPatternLUT.h rename L1Trigger/{CSCCommonTrigger => CSCTriggerPrimitives}/python/CSCCommonTrigger_cfi.py (100%) diff --git a/DQM/L1TMonitor/python/L1TCSCTF_cff.py b/DQM/L1TMonitor/python/L1TCSCTF_cff.py deleted file mode 100644 index 7d1d8ea85ecc1..0000000000000 --- a/DQM/L1TMonitor/python/L1TCSCTF_cff.py +++ /dev/null @@ -1,5 +0,0 @@ -import FWCore.ParameterSet.Config as cms - -from DQM.L1TMonitor.L1TCSCTF_cfi import * -from L1Trigger.CSCCommonTrigger.CSCCommonTrigger_cfi import * - diff --git a/DQM/L1TMonitor/python/L1TMonitor_cff.py b/DQM/L1TMonitor/python/L1TMonitor_cff.py index 6cd15c56c94f9..a5d6760452788 100644 --- a/DQM/L1TMonitor/python/L1TMonitor_cff.py +++ b/DQM/L1TMonitor/python/L1TMonitor_cff.py @@ -52,8 +52,8 @@ # CSCTPG DQM module # not run in L1T - do we need it? FIXME -# CSCTF DQM module -from DQM.L1TMonitor.L1TCSCTF_cff import * +# CSCTF DQM module +from DQM.L1TMonitor.L1TCSCTF_cfi import * # RPC DQM module - non-standard name of the module from DQM.L1TMonitor.L1TRPCTF_cfi import * diff --git a/EventFilter/CSCTFRawToDigi/python/csctfpacker_cfi.py b/EventFilter/CSCTFRawToDigi/python/csctfpacker_cfi.py index 524552d2beae1..2a26a1d68b8ac 100644 --- a/EventFilter/CSCTFRawToDigi/python/csctfpacker_cfi.py +++ b/EventFilter/CSCTFRawToDigi/python/csctfpacker_cfi.py @@ -1,11 +1,8 @@ import FWCore.ParameterSet.Config as cms -from L1Trigger.CSCCommonTrigger.CSCCommonTrigger_cfi import * +from L1Trigger.CSCTriggerPrimitives.CSCCommonTrigger_cfi import * csctfpacker = cms.EDProducer("CSCTFPacker", CSCCommonTrigger, - # the above "using" statement is equivalent to settings below: - # int32 MinBX = 3 - # int32 MaxBX = 9 zeroSuppression = cms.bool(True), outputFile = cms.string(''), lctProducer = cms.InputTag("simCscTriggerPrimitiveDigis","MPCSORTED"), diff --git a/EventFilter/CSCTFRawToDigi/python/csctfunpacker_cfi.py b/EventFilter/CSCTFRawToDigi/python/csctfunpacker_cfi.py index d70c710cc8ac5..c3d5e8a9abb97 100644 --- a/EventFilter/CSCTFRawToDigi/python/csctfunpacker_cfi.py +++ b/EventFilter/CSCTFRawToDigi/python/csctfunpacker_cfi.py @@ -1,6 +1,6 @@ import FWCore.ParameterSet.Config as cms -from L1Trigger.CSCCommonTrigger.CSCCommonTrigger_cfi import * +from L1Trigger.CSCTriggerPrimitives.CSCCommonTrigger_cfi import * csctfunpacker = cms.EDProducer("CSCTFUnpacker", CSCCommonTrigger, # Set all values to 0 if you trust hardware settings @@ -14,9 +14,6 @@ mappingFile = cms.string(''), # Agreement in CSC community to shift and reverse ME-1 strips as opposed to hardware swapME1strips = cms.bool(False), - # the above "using" statement is equivalent to setting of LCT time window below: - # int32 MinBX = 3 - # int32 MaxBX = 9 # Specify label of the module which produces raw CSCTF data producer = cms.InputTag("rawDataCollector") ) diff --git a/L1Trigger/CSCCommonTrigger/BuildFile.xml b/L1Trigger/CSCCommonTrigger/BuildFile.xml deleted file mode 100644 index b7e30ce6eda8b..0000000000000 --- a/L1Trigger/CSCCommonTrigger/BuildFile.xml +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/L1Trigger/CSCCommonTrigger/interface/CSCFrontRearLUT.h b/L1Trigger/CSCCommonTrigger/interface/CSCFrontRearLUT.h deleted file mode 100644 index 0d21602008284..0000000000000 --- a/L1Trigger/CSCCommonTrigger/interface/CSCFrontRearLUT.h +++ /dev/null @@ -1,20 +0,0 @@ -#ifndef L1Trigger_CSCFrontRearLUT_h -#define L1Trigger_CSCFrontRearLUT_h - -/** - * \class CSCFrontRearLUT - * \author L.Gray - * - * Ported from ORCA, factored out of CSCSectorReceiverLUT - */ - -class CSCFrontRearLUT { -public: - /** - * This is a function which uses the variables to return the front/rear bit. - * The calculation is done by considering how the chambers overlap each other. - */ - static unsigned getFRBit(int sector, int subsector, int station, int cscid); -}; - -#endif diff --git a/L1Trigger/CSCCommonTrigger/interface/CSCPatternLUT.h b/L1Trigger/CSCCommonTrigger/interface/CSCPatternLUT.h deleted file mode 100644 index da7f8a046109d..0000000000000 --- a/L1Trigger/CSCCommonTrigger/interface/CSCPatternLUT.h +++ /dev/null @@ -1,32 +0,0 @@ -#ifndef L1Trigger_CSCPatternLUT_h -#define L1Trigger_CSCPatternLUT_h - -/** - *\class CSCPatternLUT - *\author L. Gray (UF) - * - * This class is a static interface to the CLCT Pattern LUT. - * This was factored out of the Sector Receiver since it is used in - * parts of the trigger primitive generator (I think). - */ -#include - -class CSCPatternLUT { -public: - static double get2007Position(int pattern); - -private: - /** - * Fill the pattern lookup table. This table holds the average position - * and bend for each pattern. The position is used to further improve - * the phi resolution, and the bend is passed on to the track finding code - * to allow it to better determine the tracks. - * These were determined from Monte Carlo by running 100,000 events through - * the code and finding the offset for each pattern type. - * Note that the positions are unitless-- they are in "pattern widths" - * meaning that they are in 1/2 strips for high pt patterns and distrips - * for low pt patterns. BHT 26 June 2001 - */ -}; - -#endif diff --git a/L1Trigger/CSCCommonTrigger/interface/vlib.h b/L1Trigger/CSCCommonTrigger/interface/vlib.h deleted file mode 100644 index ae9a827cc91da..0000000000000 --- a/L1Trigger/CSCCommonTrigger/interface/vlib.h +++ /dev/null @@ -1,398 +0,0 @@ -#ifndef RVALS -#define RVALS 2 // max bits in reg/wire divided by 32 -#endif -/** -Verilog++ SP. -\author A. Madorsky -*/ - -#ifndef _VLIB_H_FILE_ -#define _VLIB_H_FILE_ - -#include -#include -#include -#include -#include -#include - -#define MAXARG 2000 - -typedef unsigned long long int rval; -#define Sizeofrval sizeof(rval) - -class module; - -enum SignalMode { mnone = 0, mreg, mwire, minput, moutput, minout, mnum, mtemp }; - -class Signal { -public: - Signal(); - Signal(rval); - Signal(int); - Signal(unsigned int); - Signal(const char*); - Signal(int bits, rval value); - void create(); - void init(int, int, const char*); - void init(const char* rname) { init(0, 0, rname); }; - void init(Signal* shost, int h, int l, const char* rname); - void makemask(); -#ifdef VGEN - std::string& getname() { return name; }; - std::string& getorname() { return orname; }; - std::string& getcatname(); - void setname(std::string& rname) { name = rname; }; - void setorname(std::string& rname) { orname = rname; }; - void setbrackets(const char* l, const char* r) { - lb = l; - rb = r; - }; -#endif - rval getr() { return r; }; - int getint() { return (unsigned int)r; }; - int getl() { return l; }; - int geth() { return h; }; - rval getmask() { return mask; }; - void setr(rval rv) { r = rv & mask; }; - void setrc(rval rv) { rc = rv & mask; }; - void sethlmask(int high, int low, rval imask) { - h = high; - l = low; - mask = imask; - }; - // bool getbool(){return (r != 0);}; - bool getbool() { return (getval() != 0); }; - int getposedge() { return pedge; }; - int getnegedge() { return nedge; }; - int getchange() { return change; }; - void setchange(int ch) { change = ch; }; - void setposedge(int ch) { pedge = ch; }; - void setnegedge(int ch) { nedge = ch; }; - void setalwaysn(int n) { alwaysn = (n == -1) ? 0 : n; }; - int getalwaysn() { return alwaysn; }; - void setprintable(int p) { printable = p; }; - rval getval(); - - Signal set(Signal); - Signal asgn(Signal); - Signal operator=(Signal); - - Signal operator+(Signal); - Signal operator-(Signal); - Signal operator*(Signal); - Signal operator/(Signal); - Signal operator%(Signal); - Signal operator^(Signal); - Signal operator>>(Signal); - Signal operator<<(Signal); - Signal operator&(Signal); - Signal operator&&(Signal); - Signal operator|(Signal); - Signal operator||(Signal); - - Signal operator<(Signal); - Signal operator>(Signal); - Signal operator<=(Signal); - Signal operator>=(Signal); - Signal operator==(Signal); - Signal operator!=(Signal); - - Signal operator!(); - Signal operator~(); - Signal* operator&(); - Signal operator++() { return *this = *this + 1; }; - Signal operator--() { return *this = *this - 1; }; - Signal operator++(int) { - return *this = *this + 1; - }; // postfix operators require some work (different names for operations and assignment printing?) - Signal operator--(int) { return *this = *this - 1; }; - - friend Signal ror(Signal); - friend Signal rxor(Signal); - friend Signal rand(Signal); - - Signal operator()(Signal, Signal); - Signal operator()(Signal); - - Signal operator,(Signal); - - friend std::ostream& operator<<(std::ostream& stream, Signal s); - - void input(int, int, const char*); - void input(const char* rname) { input(0, 0, rname); }; - void clock(const char* rname); - - void output(int, int, const char*); - void output(const char* rname) { output(0, 0, rname); }; - void output(int high, int low, const char* rname, module* parent); - void output(const char* rname, module* parent); - - void inout(int, int, const char*); - void inout(const char* rname) { inout(0, 0, rname); }; - - void reg(int, int, const char*); - void initreg(int, int, const char*); - void reg(const char* rname) { reg(0, 0, rname); }; - - void wire(int, int, const char*); - void wire(int, int, const char*, int); - void wire(const char* rname) { wire(0, 0, rname); }; - -protected: - rval r; // value holder - rval rc; // current value holder - int h, l; // high and low bit numbers - int hostl; // low bit of host - rval mask; // bit mask -#ifdef VGEN - std::string name; - std::string orname; - std::string lb, rb; // to distinguish between expression and variable - std::string obname; - std::string catname; -#endif - Signal* host; // this Signal is a portion of the host - Signal* ca1; - Signal* ca2; // arguments of the comma operator - int pedge, nedge, change; - Signal* source; // pointer to source object - Signal* outhost; - Signal* outreg; - int alwaysn; - int inited; - int printable; - int mode; // none, reg, wire, input, output, inout -}; - -class parameter : public Signal { -public: - parameter(const char* rname, Signal arg); - operator int() { return (unsigned int)r; }; - -protected: - void init(int, int, const char*); - void operator=(Signal arg); -}; - -class memory { -public: - memory() { r = nullptr; }; - ~memory(); - void reg(int, int, int, int, const char*); - void reg(int nup, int ndown, const char* rname) { reg(0, 0, nup, ndown, rname); }; -#ifdef VGEN - Signal operator[](Signal); -#else - Signal& operator[](Signal); -#endif - -protected: -#ifdef VGEN - std::string name; -#endif - Signal* r; - int up, down; -}; - -class module { -public: - module(); - virtual ~module(); - void create(); - void vendmodule(); - void vbeginmodule(); - - virtual void operator()(){}; - - void init(const char*, const char*); - void init(const char*, const char*, module* fixt); - void init(const char*, const char*, int); - Signal posedge(Signal); - Signal negedge(Signal); - void pushswitch(Signal arg) { - switcharg[switchn] = arg; - switchn++; - }; - Signal getswitch() { return switcharg[switchn - 1]; }; - void popswitch() { switchn--; } - Signal* AddOutReg(Signal arg); - Signal ifelse(Signal, Signal, Signal); - void setchange(int c) { change = c; } - int getchange() { return change; } -#ifdef VGEN - void PrintHeader(); -#endif -protected: -#ifdef VGEN - std::string name; - std::streambuf* outbuf; - std::ofstream vfile; -#endif - std::string instname; - int OuterIndPos; - Signal switcharg[10]; - int switchn; - int oldenmarg; - Signal* outreg[1000]; - int outregn; - void (*runperiod)(); - module* tfixt; - int change; - int itern; // number of iterations, for diagnostics - rval passn; // number of pass -}; - -class function : public module { -public: - function(){}; - void init(int, int, const char*); - void vendfunction(); - void vbeginfunction(); - void makemask(int hpar, int lpar); - -protected: -#ifdef VGEN - string retname; -#endif - int h, l; - rval mask; - int OldChange; - Signal result; -}; - -#define MAXSTIM 10000 - -class globcontrol { -public: - globcontrol(); -#ifdef VGEN - void AddParameter(string ln) { - pars[npar] = ln; - npar++; - }; - void AddDeclarator(string ln) { - decls[ndecl] = ln; - ndecl++; - }; - void AddComment(string ln) { - ln += "\n"; - decls[ndecl] = ln; - ndecl++; - }; - void AddIO(string ln); - void Print(); - string& PrintIO(bool col); - void Indent() { - indpos++; - PrepMargin(); - }; - void Outdent() { - indpos--; - PrepMargin(); - }; - string& getmargin() { - int t = nomargin; - nomargin = 0; - return (t) ? zeromargin : margin; - }; - int getpos() { return indpos; }; - void setpos(int pos) { - indpos = pos; - PrepMargin(); - }; - void setprintassign(int y) { pa = y; }; - int printassign() { return pa; }; - void enablemargin(int i) { nomargin = !i; }; - int getenablemargin() { return !nomargin; }; - void setFileOpen(int fo) { VFileOpen = fo; }; - int getFileOpen() { return VFileOpen; }; -#endif - void alwaysstart() { - alwayscnt = 0; - alwaysn++; - if (alwaysn == 0 || alwaysn == -1) - alwaysn = 1; - }; - void alwayspush() { - if (alwayscnt >= 0) - alwayscnt++; - }; - void alwayspop() { - if (alwayscnt > 0) - alwayscnt--; - if (alwayscnt == 0) - alwayscnt = -1; - }; - int alwaysget() { return (alwayscnt > 0); }; - int getalwaysn() { return (alwayscnt > 0) ? alwaysn : (-1); }; - - void setchange(int i); - int getchange() { return change; }; - void setparent(module* rparent) { parent = rparent; }; - module* getparent() { return parent; }; - void setfunction(int i) { functiondecl = i; }; - int getfunction() { - int t = functiondecl; - functiondecl = 0; - return t; - }; - int getce() { return ce; }; - int setce(int c) { - ce = c; - return 1; - }; - char* constant(int bits, char* val); - char* constant(int bits, int val); - void passn_inc() { passn++; }; - rval getpassn() { return passn; } - -protected: -#ifdef VGEN - string pars[MAXARG]; - int npar; - - string decls[MAXARG]; - int ndecl; - - string dios[MAXARG]; - int ndio; - - int indpos; - string margin, zeromargin; - void PrepMargin(); - int nomargin; - - int pa; - string outln; -#endif - int functiondecl; - - int alwayscnt; - int alwaysn; - - int change; - module* parent; - - int VFileOpen; // shows if the comments can be written into the file, or they need to be added to declarators - int ce; // clock can be processed - char constring[RVALS * 32 + 32]; // string for text variables - rval passn; // pass number -}; - -#ifdef VGEN -#define beginsystem -#define endsystem exit(0); -#else -#define beginsystem \ - glc.setce(0); \ - glc.passn_inc(); \ - do { \ - glc.setchange(0); -#define endsystem \ - } \ - while (glc.getchange() ? 1 : glc.getce() ? 0 : glc.setce(1)) \ - ; -#endif - -#endif diff --git a/L1Trigger/CSCCommonTrigger/interface/vmac.h b/L1Trigger/CSCCommonTrigger/interface/vmac.h deleted file mode 100644 index 9c2cc70fb9608..0000000000000 --- a/L1Trigger/CSCCommonTrigger/interface/vmac.h +++ /dev/null @@ -1,209 +0,0 @@ -/** -Verilog++ SP. -\author A. Madorsky -*/ - - -#ifndef _VMAC_H_FILE_ -#define _VMAC_H_FILE_ - -#include "L1Trigger/CSCCommonTrigger/interface/vlib.h" - -extern globcontrol glc; - -#ifdef VGEN - #define For(par1, par2, par3) glc.setprintassign(0); std::cout << glc.getmargin() << "for (" << flush; std::cout << (par1).getname() << "; " << flush; glc.setprintassign(0); std::cout << (par2).getname() << "; " << flush; glc.setprintassign(0); std::cout << (par3).getname(); std::cout << ") " << flush; glc.setprintassign(1); glc.enablemargin(0); -#else - #define For(par1, par2, par3) for ((par1); ((par2).getbool()); (par3)) -#endif - -#ifdef VGEN - #define If(par) glc.setprintassign(0); std::cout << glc.getmargin() << "if (" << flush; std::cout << (par).getname(); std::cout << ") " << flush; glc.setprintassign(1); glc.enablemargin(0); -#else - #define If(par) if ((par).getbool()) -#endif - -#ifdef VGEN - #define Else std::cout << glc.getmargin() << "else " << flush; glc.enablemargin(0); -#else - #define Else else -#endif - -#define begin vbegin() -#ifdef VGEN - #define vbegin() glc.enablemargin(1); std::cout << "\n" << glc.getmargin() << "begin\n" << flush; glc.Indent(); -#else - #define vbegin() { glc.alwayspush(); -#endif - -#define end vend() -#ifdef VGEN - #define vend() glc.Outdent(); std::cout << glc.getmargin() << "end\n" << flush; -#else - #define vend() glc.alwayspop(); } -#endif - -#ifdef VGEN - #define always(par) std::cout << glc.getmargin() << "always @(" << (par).getorname() << ") " << flush; glc.enablemargin(0); -#else - #define always(par) glc.alwaysstart(); if ((par).getchange()) -#endif - -#ifdef VGEN - #define assign std::cout << glc.getmargin() << "assign " << flush; glc.enablemargin(0); -#else - #define assign -#endif - -#ifdef VGEN - #define deassign(par) std::cout << glc.getmargin() << "deassign " << flush; std::cout << (par).getname() << ";\n" << flush; glc.enablemargin(1); -#else - #define deassign(par) ; -#endif - -#ifdef VGEN - #define begincase(par) glc.setprintassign(0); std::cout << glc.getmargin() << "case (" << flush; std::cout << (par).getcatname() << flush; std::cout << ")\n" << flush; glc.setprintassign(1); glc.Indent(); -#else -#define begincase(par) pushswitch((par)); if (0) {} -#endif - -#define endcase vendcase() -#ifdef VGEN - #define vendcase() glc.Outdent(); std::cout << glc.getmargin() << "endcase\n" << flush; -#else - #define vendcase() popswitch(); -#endif - -#ifdef VGEN - #define case1(par) \ - cout << glc.getmargin(); \ - glc.setprintassign(0); std::cout << ((Signal)(par)).getcatname(); \ - cout << " : " << flush; glc.setprintassign(1); glc.enablemargin(0); -#else - #define case1(par) else if ((getswitch() == (par)).getbool()) -#endif - -#ifdef VGEN - #define case2(par1, par2) \ - glc.setprintassign(0); \ - cout << glc.getmargin(); \ - glc.setprintassign(0); std::cout << ((Signal)(par1)).getcatname(); std::cout << ", "; \ - glc.setprintassign(0); std::cout << ((Signal)(par2)).getcatname();\ - cout << " : " << flush; glc.setprintassign(1); glc.enablemargin(0); -#else - #define case2(par1, par2) else if ( (getswitch() == (par1)).getbool() || (getswitch() == (par2)).getbool()) -#endif - -#ifdef VGEN - #define case3(par1, par2, par3) \ - glc.setprintassign(0); \ - cout << glc.getmargin(); \ - glc.setprintassign(0); std::cout << ((Signal)(par1)).getcatname(); std::cout << ", "; \ - glc.setprintassign(0); std::cout << ((Signal)(par2)).getcatname(); std::cout << ", "; \ - glc.setprintassign(0); std::cout << ((Signal)(par3)).getcatname(); \ - cout << " : " << flush; glc.setprintassign(1); glc.enablemargin(0); -#else - #define case3(par1, par2, par3) else if ( (getswitch() == (par1)).getbool() || (getswitch() == (par2)).getbool() || (getswitch() == (par3)).getbool()) -#endif - - -#define Default vdefault() -#ifdef VGEN - #define vdefault() std::cout << glc.getmargin(); std::cout << "default : " << flush; glc.enablemargin(0); -#else - #define vdefault() else -#endif - -#define beginmodule vbeginmodule(); -#define endmodule vendmodule(); - -#ifdef VGEN -#define modulebody -#else -#define modulebody \ -if (glc.getpassn() != passn) \ -{ \ -/* cout << itern << " " << instname << std::endl; */\ - itern = 0; \ -} \ -passn = glc.getpassn(); \ -if (!glc.getparent()->getchange()) \ -{ \ - outregn = 0; \ - return; \ -} \ -else \ -{ \ - itern++; \ -} - -#endif - -#define beginfunction vbeginfunction(); -#define endfunction vendfunction(); return (result); - -#ifdef VGEN -#define functionbody -#else -//#define functionbody if (!glc.getparent()->getchange()) {vendfunction(); return (result);} -#define functionbody -#endif - - -#if (__GNUC__==2)||defined(_MSC_VER) -#define or || -#endif -#define makereg this - -#define endperiod glc.ResetEvents(); - -#ifdef VGEN - #define comment(par) if (glc.getFileOpen()) {std::cout << glc.getmargin(); std::cout << (par) << "\n" << flush;} else glc.AddComment((string)(par)); -#else - #define comment(par) -#endif - -#ifdef VGEN - #define printv(par) std::cout << (par) << flush; -#else - #define printv(par) -#endif - - -#ifdef VGEN - #define initio glc.setparent(this); glc.setFileOpen(0); -#else - #define initio glc.setparent(this); glc.getparent()->setchange(0); -#endif - -// these macros are different for all possible types of initializations, -// because not all compilers yet support ISO C99 variadic macros (macros with variable number of parameters) -// At the moment of writing, only GNU C++ compiler supports them. -#define Reg(cl) cl.reg(#cl) -#define Reg_(cl, h, l) cl.reg(h, l, #cl) -#define Reg__(cl, h, l, t, b) cl.reg(h, l, t, b, #cl); - -#define Wire(cl) cl.wire(#cl) -#define Wire_(cl, h, l) cl.wire(h, l, #cl) -#define Wire__(cl, h, l, t, b) for (int __wi__ = b; __wi__ <= t; __wi__++) cl[__wi__].wire(h, l, #cl, __wi__) - -#define Input(cl) cl.input(#cl) -#define Input_(cl, h, l) cl.input(h, l, #cl) -#define Clock(cl) cl.clock(#cl) - -#define Output(cl) cl.output(#cl) -#define Output_(cl, h, l) cl.output(h, l, #cl) - -#define OutReg(cl) cl.output(#cl, makereg) -#define OutReg_(cl, h, l) cl.output(h, l, #cl, makereg) - -#define Inout(cl) cl.inout(#cl) -#define Inout_(cl, h, l) cl.inout(h, l, #cl) - -#define Module(md) md.init(#md, #md) -#define Module_(md, fn) md.init(#md, #fn) - -#define cns(b,v) glc.constant(b,v) - -#endif - diff --git a/L1Trigger/CSCCommonTrigger/src/CSCFrontRearLUT.cc b/L1Trigger/CSCCommonTrigger/src/CSCFrontRearLUT.cc deleted file mode 100644 index 864d5c9ea8621..0000000000000 --- a/L1Trigger/CSCCommonTrigger/src/CSCFrontRearLUT.cc +++ /dev/null @@ -1,39 +0,0 @@ -#include - -unsigned CSCFrontRearLUT::getFRBit(int sector, int subsector, int station, int cscid) { - unsigned dc = 0, sector_type = 0; - unsigned fr_table[16][6] = {{0, 1, 1, 0, 1, 0}, - {1, 0, 0, 1, 0, 1}, - {0, 1, 1, 0, 1, 0}, - {0, 0, 1, 1, 1, 0}, - {1, 1, 0, 0, 0, 1}, - {0, 0, 1, 1, 1, 0}, - {1, 1, 0, 0, dc, dc}, - {0, 0, 1, 1, dc, dc}, - {1, 1, 0, 0, dc, dc}, - {dc, dc, dc, dc, 1, 0}, // cscid 10-12 are me1a - {dc, dc, dc, dc, 0, 1}, - {dc, dc, dc, dc, 1, 0}, - {dc, dc, dc, dc, dc, dc}, - {dc, dc, dc, dc, dc, dc}, - {dc, dc, dc, dc, dc, dc}, - {dc, dc, dc, dc, dc, dc}}; - - switch (station) { - case 1: - sector_type = 4 + subsector; - break; - case 2: - sector_type = 1 - (sector % 2); - break; - case 3: - sector_type = 3 - (sector % 2); - break; - case 4: - sector_type = 3 - (sector % 2); - break; - //default: - //std::cout << "+++ Error: unforeseen station " << stn << "in GetFRBit +++"; // replace with message logger or exception - } - return fr_table[cscid - 1][sector_type]; -} diff --git a/L1Trigger/CSCCommonTrigger/src/CSCPatternLUT.cc b/L1Trigger/CSCCommonTrigger/src/CSCPatternLUT.cc deleted file mode 100644 index f93ff91279cc6..0000000000000 --- a/L1Trigger/CSCCommonTrigger/src/CSCPatternLUT.cc +++ /dev/null @@ -1,8 +0,0 @@ -#include - -double CSCPatternLUT::get2007Position(int pattern) { - double PositionList[CSCConstants::NUM_CLCT_PATTERNS] = { - 0.0, 0.0, -0.60, 0.60, -0.64, 0.64, -0.23, 0.23, -0.21, 0.21, 0.0}; // offset in the strip number for each pattern - - return PositionList[pattern]; -} diff --git a/L1Trigger/CSCCommonTrigger/src/vlib.cc b/L1Trigger/CSCCommonTrigger/src/vlib.cc deleted file mode 100644 index 37396ee499ceb..0000000000000 --- a/L1Trigger/CSCCommonTrigger/src/vlib.cc +++ /dev/null @@ -1,1216 +0,0 @@ -// Alexander Madorsky, University of Florida/Physics. - -#include - -globcontrol glc; - -char const* obnames[] = {"none ", "reg ", "wire ", "input ", "output ", "inout ", "num ", "temp "}; - -#define dbgmsg(a) std::cerr << a << " Set breakpoint at " << __FILE__ << ":" << __LINE__ << "\n"; - -// Signal class -------------------------------------------------------------------------- - -void Signal::create() { -#ifdef VGEN - name = ""; - orname = ""; - obname = ""; - lb = "("; - rb = ")"; -#endif - - outhost = host = outreg = ca1 = ca2 = nullptr; - inited = printable = r = rc = l = pedge = nedge = change = alwaysn = mode = 0; - h = 8 * Sizeofrval - 1; - mask = (rval)(-1); - hostl = -1; -} - -Signal::Signal() { create(); } - -Signal::Signal(int bits, rval value) { - create(); -#ifdef VGEN - ostringstream sval; - sval << dec << bits << "'d" << value; - Signal::init(bits - 1, 0, sval.str().c_str()); -#else - Signal::init(bits - 1, 0, ""); -#endif - r = rc = value & mask; -} - -Signal::Signal(const char* sval) { - create(); - mode = mnum; - std::string val = sval; - int bits; - unsigned int i; - char radix; - rval value = 0; - int dig; - - sscanf(val.c_str(), "%d'%c", &bits, &radix); - switch (radix) { - case 'h': - case 'H': - // sscanf (val.c_str(), "%d'%c%x", &bits, &radix, &value); - for (i = 0; val[i] != 'h' && val[i] != 'H'; ++i) - ; - for (; i < val.length(); ++i) { - switch (val[i]) { - case '0': - case '1': - case '2': - case '3': - case '4': - case '5': - case '6': - case '7': - case '8': - case '9': - dig = val[i] - '0'; - break; - case 'a': - case 'b': - case 'c': - case 'd': - case 'e': - case 'f': - dig = val[i] - 'a' + 10; - break; - case 'A': - case 'B': - case 'C': - case 'D': - case 'E': - case 'F': - dig = val[i] - 'A' + 10; - break; - default: - dig = -1; - break; - } - if (dig >= 0) { - value = value << 4; - value = value | dig; - } - } - - break; - case 'd': - case 'D': - sscanf(val.c_str(), "%d'%c%d", &bits, &radix, reinterpret_cast(&value)); - break; - case 'o': - case 'O': - // sscanf (val.c_str(), "%d'%c%o", &bits, &radix, &value); - for (i = 0; val[i] != 'o' && val[i] != 'O'; ++i) - ; - for (; i < val.length(); ++i) { - switch (val[i]) { - case '0': - case '1': - case '2': - case '3': - case '4': - case '5': - case '6': - case '7': - dig = val[i] - '0'; - break; - default: - dig = -1; - break; - } - if (dig >= 0) { - value = value << 3; - value = value | dig; - } - } - - break; - - case 'b': - case 'B': - - for (i = 0; val[i] != 'b' && val[i] != 'B'; ++i) - ; - for (; i < val.length(); ++i) { - switch (val[i]) { - case '0': - value = value << 1; - break; - case '1': - value = value << 1; - value = value | 1; - break; - } - } - break; - } - Signal::init(bits - 1, 0, val.c_str()); - rc = value & mask; - r = rc; -} - -Signal::Signal(rval n) { - create(); - mode = mnum; -#ifdef VGEN - ostringstream ln; - ln << dec << n; - init(8 * Sizeofrval - 1, 0, ln.str().c_str()); -#else - init(8 * Sizeofrval - 1, 0, ""); -#endif - inited = 0; - rc = n; - r = n; -} - -Signal::Signal(int n) { - create(); - mode = mnum; -#ifdef VGEN - ostringstream ln; - ln << dec << n; - init(Sizeofrval * 8 - 1, 0, ln.str().c_str()); -#else - init(Sizeofrval * 8 - 1, 0, ""); -#endif - inited = 0; - r = (rval)n; - rc = r; -} - -Signal::Signal(unsigned int n) { - create(); - mode = mnum; -#ifdef VGEN - ostringstream ln; - ln << dec << n; - init(Sizeofrval * 8 - 1, 0, ln.str().c_str()); -#else - init(Sizeofrval * 8 - 1, 0, ""); -#endif - inited = 0; - r = (rval)n; - rc = r; -} - -void Signal::makemask() { - mask = (1LL << (h - l + 1)) - 1LL; - if (mask == 0LL) - mask = ~mask; -} - -void Signal::init(int high, int low, const char* rname) { -#ifdef VGEN - name = rname; - orname = rname; - lb = ""; - rb = ""; -#endif - if (!inited) { - h = high; - l = low; - makemask(); - inited = 1; - } - source = this; -} - -void Signal::init(Signal* shost, int high, int low, const char* rname) { - host = shost; -#ifdef VGEN - name = rname; - orname = rname; - lb = ""; - rb = ""; -#endif - h = high; - l = low; - makemask(); - source = this; - if (host) { - rc = (host->getr() >> (l - host->getl())) & mask; - r = rc; - } - change = pedge = nedge = 0; -} - -#ifdef VGEN -string& Signal::getcatname() { - if (lb[0] == '{') - catname = lb + name + rb; - else - catname = name; - return catname; -} -#endif - -// unary operators ------------------------------------- - -#ifdef VGEN -#define unop(op, cop) \ - Signal Signal::op() { \ - Signal t; \ - t.name = #cop + lb + name + rb; \ - printable = 0; \ - t.r = mask & (cop getval()); \ - return t; \ - } -#else -#define unop(op, cop) \ - Signal Signal::op() { \ - Signal t; \ - t.init(h, l, ""); \ - t.r = mask & (cop getval()); \ - return t; \ - } -#endif - -unop(operator!, !) unop(operator~, ~) - - Signal* Signal::operator&() { -#ifdef VGEN - printable = 0; -#endif - return this; -} - -// binary operators ------------------------------------ -#ifdef VGEN -#define binop(op, cop) \ - Signal Signal::op(Signal arg) { \ - Signal t; \ - t.name = lb + name + rb + " " + #cop + " " + arg.lb + arg.name + arg.rb; \ - printable = arg.printable = 0; \ - t.r = (getval() cop arg.getval()); \ - return t; \ - } -#else -#define binop(op, cop) \ - Signal Signal::op(Signal arg) { \ - Signal t; \ - int ln = h - l; \ - int aln = arg.h - arg.l; \ - t.init((ln > aln) ? ln : aln, 0, ""); \ - t.r = t.mask & (getval() cop arg.getval()); \ - return t; \ - } -#endif - -binop(operator+, +) binop(operator-, -) binop(operator*, *) binop(operator/, /) binop(operator%, %) binop(operator^, ^) - binop(operator<<, <<) binop(operator>>, >>) binop(operator&, &) binop(operator&&, &&) binop(operator|, |) - - Signal Signal::operator||(Signal arg) { - Signal t; -#ifdef VGEN - t.name = lb + name + rb + " || " + arg.lb + arg.name + arg.rb; - t.orname = orname + " or " + arg.orname; - printable = arg.printable = 0; -#else - int ln = h - l; - int aln = arg.h - arg.l; - t.init((ln > aln) ? ln : aln, 0, ""); -#endif - t.r = t.mask & (getval() || arg.getval()); - t.change = change || arg.change; - return t; -} - -Signal Signal::operator,(Signal arg) { - Signal t; -#ifdef VGEN - t.name = name + ", " + arg.name; - t.lb = "{"; - t.rb = "}"; - printable = arg.printable = 0; -#else - t.ca1 = this; - t.ca2 = arg.source; - t.init(h - l + arg.h - arg.l + 1, 0, ""); -#endif - t.r = (((getval() << (arg.h - arg.l + 1)) & (~(arg.mask))) | arg.getval()) & t.mask; - return t; -} - -// comparison operators --------------------------------------------------- - -#ifdef VGEN -#define compop(op, cop) \ - Signal Signal::op(Signal arg) { \ - Signal t; \ - t.name = lb + name + rb + " " + #cop + " " + arg.lb + arg.name + arg.rb; \ - printable = arg.printable = 0; \ - t.r = (getval() cop arg.getval()); \ - return t; \ - } -#else -#define compop(op, cop) \ - Signal Signal::op(Signal arg) { \ - Signal t; \ - t.init(""); \ - t.r = (getval() cop arg.getval()); \ - return t; \ - } -#endif - -compop(operator>, >) compop(operator<, <) compop(operator<=, <=) compop(operator>=, >=) compop(operator==, ==) - compop(operator!=, !=) - - // reduction operators -------------------------------------------------------------- - Signal ror(Signal arg) { - Signal t; - rval tr; -#ifdef VGEN - t.name = "|" + arg.lb + arg.name + arg.rb; - arg.printable = 0; -#else - t.init(""); -#endif - tr = (arg.getval()) & arg.mask; - t.r = (tr != 0) ? 1 : 0; - return t; -} - -Signal rand(Signal arg) { - Signal t; - rval tr; -#ifdef VGEN - t.name = "&" + arg.lb + arg.name + arg.rb; - arg.printable = 0; -#else - t.init(""); -#endif - tr = (arg.getval()) & arg.mask; - t.r = (tr == arg.mask) ? 1 : 0; - return t; -} - -Signal rxor(Signal arg) { - Signal t; - rval tr; - int i; -#ifdef VGEN - t.name = "^" + arg.lb + arg.name + arg.rb; - arg.printable = 0; -#else - t.init(""); -#endif - tr = (arg.getval()) & arg.mask; - t.r = 0; - for (i = 0; i < arg.h - arg.l + 1; ++i) { - t.r = ((tr & 1) != 0) ? !t.r : t.r; - tr = tr >> 1; - } - t.r = t.r & 1; - return t; -} - -// blocking assignment operator ----------------------------------------------------- - -rval Signal::getval() { return (getalwaysn() == glc.getalwaysn()) ? rc : r; } - -Signal Signal::operator=(Signal other) { -#ifndef VGEN -#ifdef _VDEBUG - switch (mode) { - case moutput: - if (glc.getalwaysn() == -1 && outreg != NULL) - dbgmsg("Assigning output-reg outside always block."); - if (glc.getalwaysn() != -1 && outreg == NULL) - dbgmsg("Assigning non-reg output inside always block."); - break; - - case minout: - if (glc.getalwaysn() != -1) - dbgmsg("Assigning inout inside always block."); - break; - - case minput: - dbgmsg("Assigning to input is not allowed."); - return other; - - case mreg: - if (glc.getalwaysn() == -1) - dbgmsg("Assigning reg outside always block."); - break; - - case mwire: - if (glc.getalwaysn() != -1) - dbgmsg("Assigning wire inside always block."); - break; - } -#endif -#endif - return asgn(other); -} - -Signal Signal::set(Signal other) { -#ifdef VGEN - glc.setprintassign(0); -#endif - return asgn(other); -} - -Signal Signal::asgn(Signal other) { - Signal t; - -#ifdef VGEN - t.name = lb + name + rb + " = " + other.getcatname(); - if (glc.printassign()) - std::cout << glc.getmargin() << t.name << ";\n" << flush; -#endif - rval hr, portionr, portionmask, otr; - int shn; - - otr = other.getval() & mask; - - if (otr != r) { - setalwaysn(glc.getalwaysn()); - glc.setchange(1); - } - - rc = otr; - if (host) // is this a portion of the other register? - { - hr = host->rc; - if (hostl > 0) - shn = (hostl - host->getl()); - else - shn = (l - host->getl()); - portionr = rc << shn; - portionmask = mask << shn; - host->set((hr & (~portionmask)) | portionr); - } - - if (ca1 != nullptr && ca2 != nullptr) // is this a concatenation of the two registers? - { - ca2->set(other); - ca1->set(other >> (ca2->h - ca2->l + 1)); - } - if (outhost != nullptr && outhost != this && (mode == moutput || mode == minout)) { - outhost->set(other); - } - if (outreg) { - outreg->set(other); - } - - t.h = h; - t.l = l; - t.mask = mask; - t.pedge = pedge; - t.nedge = nedge; - t.change = change; - t.r = rc; -#ifdef VGEN - glc.setprintassign(1); -#endif - return t; -} - -// bit selection operator ----------------------------------------------- - -Signal Signal::operator()(Signal hn, Signal ln) { - Signal t; -#ifdef VGEN - string bname; - if (hn.getname().compare(ln.getname()) != 0) - bname = name + "[" + hn.getname() + ":" + ln.getname() + "]"; - else - bname = name + "[" + hn.getname() + "]"; - hn.printable = ln.printable = 0; - t.init(this, 0, 0, bname.c_str()); -#else - t.init(this, (unsigned)hn.getval(), (unsigned)ln.getval(), ""); -#endif - t.rc = (getval() >> (t.l - l)) & t.mask; - t.r = t.rc; - return t; -} - -Signal Signal::operator()(Signal n) { return (*this)(n, n); } - -// insertion operator --------------------------------------------------- -std::ostream& operator<<(std::ostream& stream, Signal s) { - stream << s.getr(); - s.setprintable(0); - return stream; -} - -// input ----------------------------------------------------------------------------- -void Signal::input(int high, int low, const char* rname) { -#ifdef VGEN - if (lb == "{") - glc.AddIO(lb + name + rb); - else - glc.AddIO(name); -#else -#ifdef _VDEBUG - if (h - l != high - low && - inited) // inited is analysed in case the passed parameter is a temp var. Actually, every operator should return temp with the proper mask,h,l inherited from operands - { - dbgmsg("Different port length for input argument: declared [" << high << ":" << low << "], passed: [" << h << ":" - << l << "]. "); - } -#endif -#endif - Signal::init(high, low, rname); - if (high >= low) { - h = high; - l = low; - } else { - h = low; - l = high; - } - mode = minput; -#ifdef VGEN - obname = obnames[mode]; - ostringstream ln; - glc.AddParameter(name); - if (h == l) - ln << obname << name << ";\n"; - else - ln << obname << "[" << dec << h << ":" << l << "] " << name << ";\n"; - glc.AddDeclarator(ln.str()); - printable = 0; -#else - outreg = glc.getparent()->AddOutReg((Signal)(*this)); - r = r & outreg->getmask(); - if (outreg->getr() != r) { - change = 1; - glc.getparent()->setchange(1); - if (r == 1 && outreg->getr() == 0) - pedge = 1; - else - pedge = 0; - if (r == 0 && outreg->getr() == 1) - nedge = 1; - else - nedge = 0; - } else - change = pedge = nedge = 0; - outreg->setr(r); - outreg->setrc(r); - outhost = host = nullptr; -#endif -} - -// clock input -------------------------------------------------------------- -void Signal::clock(const char* rname) { -#ifdef VGEN - if (lb == "{") - glc.AddIO(lb + name + rb); - else - glc.AddIO(name); -#else -#ifdef _VDEBUG - if (h - l != 0 && - inited) // inited is analysed in case the passed parameter is a temp var. Actually, every operator should return temp with the proper mask,h,l inherited from operands - { - dbgmsg("Different port length for clock argument: declared [" << 0 << ":" << 0 << "], passed: [" << h << ":" << l - << "]. "); - } -#endif -#endif - Signal::init(0, 0, rname); - h = l = 0; - mode = minput; -#ifdef VGEN - obname = obnames[mode]; - ostringstream ln; - glc.AddParameter(name); - if (h == l) - ln << obname << name << ";\n"; - else - ln << obname << "[" << dec << h << ":" << l << "] " << name << ";\n"; - glc.AddDeclarator(ln.str()); - printable = 0; -#else - outreg = glc.getparent()->AddOutReg((Signal)(*this)); - if (rc != r) { - change = 1; - glc.getparent()->setchange(1); - if (rc == 1 && r == 0) - pedge = 1; - else - pedge = 0; - if (rc == 0 && r == 1) - nedge = 1; - else - nedge = 0; - } else - change = pedge = nedge = 0; - outreg->setr(r); - outreg->setrc(r); - outhost = host = nullptr; -#endif -} - -// output ----------------------------------------------------------------------------- - -void Signal::output(int high, int low, const char* rname) { -#ifdef VGEN - if (lb == "{") - glc.AddIO(lb + name + rb); - else - glc.AddIO(name); -#else -#ifdef _VDEBUG - if (h - l != high - low) { - dbgmsg("Different port length for output argument: declared [" << high << ":" << low << "], passed: [" << h << ":" - << l << "]. "); - } - if (mode == mreg) { - dbgmsg("Using reg as output."); - } -#endif -#endif - hostl = l; - Signal::init(high, low, rname); - if (high >= low) { - h = high; - l = low; - } else { - h = low; - l = high; - } - mode = moutput; -#ifdef VGEN - obname = obnames[mode]; - ostringstream ln; - glc.AddParameter(name); - if (h == l) - ln << obname << name << ";\n"; - else - ln << obname << "[" << dec << h << ":" << l << "] " << name << ";\n"; - glc.AddDeclarator(ln.str()); - printable = 0; -#endif -} - -void Signal::output(int high, int low, const char* rname, module* parent) { - output(high, low, rname); -#ifdef VGEN - ostringstream ln; - if (h == l) - ln << "reg " << name << ";\n"; - else - ln << "reg [" << dec << h << ":" << l << "] " << name << ";\n"; - glc.AddDeclarator(ln.str()); -#else - outreg = parent->AddOutReg((Signal)(*this)); - setr(outreg->getr()); - setchange(outreg->getchange()); - setposedge(outreg->getposedge()); - setnegedge(outreg->getnegedge()); -#endif -} - -void Signal::output(const char* rname, module* parent) { output(0, 0, rname, parent); } - -// inout ----------------------------------------------------------------------------- - -void Signal::inout(int high, int low, const char* rname) { -#ifdef VGEN - if (lb == "{") - glc.AddIO(lb + name + rb); - else - glc.AddIO(name); -#else -#ifdef _VDEBUG - if (h - l != high - low) { - dbgmsg("Different port length for inout argument: declared [" << high << ":" << low << "], passed: [" << h << ":" - << l << "]. "); - } -#endif -#endif - hostl = l; - Signal::init(high, low, rname); - if (high >= low) { - h = high; - l = low; - } else { - h = low; - l = high; - } - mode = minout; -#ifdef VGEN - obname = obnames[mode]; - ostringstream ln; - glc.AddParameter(name); - if (h == l) - ln << obname << name << ";\n"; - else - ln << obname << "[" << dec << h << ":" << l << "] " << name << ";\n"; - glc.AddDeclarator(ln.str()); - printable = 0; -#endif -} - -// reg ------------------------------------------------------------------------------- - -void Signal::reg(int high, int low, const char* rname) { - initreg(high, low, rname); -#ifdef VGEN - if (h == l) - cout << glc.getmargin() << obname << name << ";\n" << flush; - else - std::cout << glc.getmargin() << obname << "[" << dec << h << ":" << l << "] " << name << ";\n" << flush; -#endif -} - -void Signal::initreg(int high, int low, const char* rname) { - Signal::init(high, low, rname); - mode = mreg; -#ifdef VGEN - obname = obnames[mode]; -#endif - change = (r != rc); - if (change) - glc.getparent()->setchange(1); - pedge = (rc == 1 && r == 0); - nedge = (rc == 0 && r == 1); - r = rc; -} - -// parameter class ------------------------------------------------------------------------------- - -parameter::parameter(const char* rname, Signal arg) : Signal() { -#ifdef VGEN - obname = "parameter "; -#endif - init(Sizeofrval * 8 - 1, 0, rname); - operator=(arg); -} - -void parameter::init(int h, int l, const char* rname) { - Signal::init(h, l, rname); - change = pedge = nedge = 0; - -#ifdef VGEN - cout << glc.getmargin() << obname << name << flush; -#endif -} - -void parameter::operator=(Signal arg) { - r = arg.getr(); -#ifdef VGEN - cout << " = " << arg.getname() << ";\n" << flush; -#endif -} - -// wire ------------------------------------------------------------------------------- - -void Signal::wire(int high, int low, const char* rname) { - Signal::init(high, low, rname); - mode = mwire; - outhost = this; - change = (r != rc); - if (change && glc.getparent()) - glc.getparent()->setchange(1); - pedge = (rc == 1 && r == 0); - nedge = (rc == 0 && r == 1); - r = rc; -#ifdef VGEN - obname = obnames[mode]; - if (h == l) - cout << glc.getmargin() << obname << name << ";\n" << flush; - else - std::cout << glc.getmargin() << obname << "[" << dec << h << ":" << l << "] " << name << ";\n" << flush; -#endif -} - -void Signal::wire(int high, int low, const char* rname, int i) { -#ifdef VGEN - ostringstream instnamestream; - instnamestream << rname << dec << i; - // init(high, low, instnamestream.str().c_str()); - wire(high, low, instnamestream.str().c_str()); -#else - wire(high, low, rname); -#endif -} - -// memory class ----------------------------------------------------------------------------- - -void memory::reg(int high, int low, int nup, int ndown, const char* rname) { - int i; - if (nup > ndown) { - up = nup; - down = ndown; - } else { - up = ndown; - down = nup; - } - if (r == nullptr) { - r = new Signal[up - down + 1]; - for (i = 0; i <= up - down; ++i) { - r[i].initreg(high, low, ""); - r[i].setr(0); - } - } else { - for (i = 0; i <= up - down; ++i) { - r[i].initreg(high, low, ""); - } - } -#ifdef VGEN - name = rname; - if (high == low) - std::cout << glc.getmargin() << "reg " << name << " [" << dec << up << ":" << down << "]" - << ";\n" - << flush; - else - std::cout << glc.getmargin() << "reg " - << "[" << dec << high << ":" << low << "] " << name << " [" << dec << up << ":" << down << "]" - << ";\n" - << flush; -#endif -} - -memory::~memory() { - if (r != nullptr) - delete[] r; - r = nullptr; -} - -#ifdef VGEN -Signal memory::operator[](Signal i) -#else -Signal& memory::operator[](Signal i) -#endif -{ -#ifdef VGEN - string ln; - ln = name + "[" + i.getname() + "]"; - r[0].setname(ln); - r[0].setorname(ln); - return r[0]; -#else - rval ind = i.getval(); -#ifdef _VDEBUG - if (ind < down || ind > up) { - dbgmsg("Memory index out of range: index: " << ind << ", range: [" << up << ":" << down << "]. "); - return r[down]; - } else -#endif - return r[ind - down]; -#endif -} - -// module class ------------------------------------------------------------------------- - -void module::create() { - for (unsigned int i = 0; i < sizeof(outreg) / sizeof(Signal*); ++i) - outreg[i] = nullptr; - outregn = 0; - runperiod = nullptr; -} - -module::module() { create(); } - -module::~module() { - for (unsigned int i = 0; i < sizeof(outreg) / sizeof(Signal*); ++i) { - if (outreg[i] != nullptr) - delete outreg[i]; - } -} - -void module::init(const char* mname, const char* iname) { -#ifdef VGEN - name = mname; - instname = iname; -#endif -} - -void module::init(const char* mname, const char* iname, module* fixt) { -#ifdef VGEN - name = mname; - instname = iname; -#endif - tfixt = fixt; -} - -void module::init(const char* mname, const char* iname, int index) { -#ifdef VGEN - name = mname; - ostringstream instnamestream; - instnamestream << iname << dec << index; - instname = instnamestream.str().c_str(); -#endif -} - -#ifdef VGEN -void module::PrintHeader() { - char* username = NULL; - struct tm* newtime; - time_t aclock; - time(&aclock); - newtime = localtime(&aclock); - username = std::getenv("USER"); - if (username == NULL || strlen(username) < 2) - username = std::getenv("USERNAME"); - if (username == NULL || strlen(username) < 2) - username = std::getenv("LOGNAME"); - cout << "// This Verilog HDL source file was automatically generated" << std::endl; - cout << "// by C++ model based on VPP library. Modification of this file" << std::endl; - cout << "// is possible, but if you want to keep it in sync with the C++" << std::endl; - cout << "// model, please modify the model and re-generate this file." << std::endl; - cout << "// VPP library web-page: http://www.phys.ufl.edu/~madorsky/vpp/" << std::endl; - cout << std::endl; - if (username != NULL) - cout << "// Author : " << username << std::endl; - cout << "// File name : " << name << ".v" << std::endl; - cout << "// Timestamp : " << asctime(newtime) << std::endl << flush; -} -#endif - -void module::vbeginmodule() { - switchn = 0; -#ifdef VGEN - string filename = name + ".v"; - cout << glc.getmargin() << name << " " << instname << std::endl << flush; - cout << glc.getmargin() << "(" << glc.PrintIO(true).c_str() << std::endl << flush; - cout << glc.getmargin() << ");\n" << flush; - vfile.open(filename.c_str()); - outbuf = std::cout.rdbuf(vfile.rdbuf()); - OuterIndPos = glc.getpos(); - oldenmarg = glc.getenablemargin(); - glc.enablemargin(1); - glc.setpos(0); - PrintHeader(); - cout << glc.getmargin() << "module " << name << std::endl << glc.getmargin() << "(" << flush; - glc.setfunction(0); - glc.Print(); - glc.setFileOpen(1); -#endif -} - -void module::vendmodule() { -#ifdef VGEN - glc.Outdent(); - cout << glc.getmargin() << "endmodule\n" << flush; - glc.setpos(OuterIndPos); - cout.rdbuf(outbuf); - vfile.close(); - glc.enablemargin(oldenmarg); -#endif - outregn = 0; -} - -Signal module::posedge(Signal arg) { - Signal t; -#ifdef VGEN - string ln = ""; - ln = "posedge " + arg.getname(); - t.init(NULL, 0, 0, ln.c_str()); -#else - t.init(nullptr, 0, 0, ""); -#endif - if (arg.getposedge()) - glc.setce(0); - t.setchange(arg.getposedge()); - return t; -} - -Signal module::negedge(Signal arg) { - Signal t; -#ifdef VGEN - string ln = ""; - ln = "negedge " + arg.getname(); - t.init(NULL, 0, 0, ln.c_str()); -#else - t.init(nullptr, 0, 0, ""); -#endif - if (arg.getnegedge()) - glc.setce(0); - t.setchange(arg.getnegedge()); - return t; -} - -Signal* module::AddOutReg(Signal arg) { - if (outreg[outregn] == nullptr) { - outreg[outregn] = new Signal; - outreg[outregn]->setr(0); - } - outreg[outregn]->reg(arg.geth(), arg.getl(), ""); - outregn++; - return outreg[outregn - 1]; -} - -Signal module::ifelse(Signal condition, Signal iftrue, Signal iffalse) { -#ifdef VGEN - Signal t; - string ln; - ln = "(" + condition.getname() + ") ? " + iftrue.getname() + " : " + iffalse.getname(); - t.setname(ln); - return t; -#else - if (condition.getbool()) - return iftrue; - else - return iffalse; -#endif -} - -// function class ------------------------------------------------------------- - -void function::makemask(int hpar, int lpar) { - //int i; - unsigned int lng = hpar - lpar + 1; - - if (lng < Sizeofrval * 8) - mask = (1LL << lng) - 1; - else - mask = (rval)(-1); -} - -void function::init(int high, int low, const char* rname) { -#ifdef VGEN - name = rname; - cout << "`include " << '"' << name << ".v" << '"' << "\n" << flush; -#endif - if (high >= low) { - h = high; - l = low; - } else { - h = low; - l = high; - } - makemask(h, l); -} - -void function::vbeginfunction() { -#ifdef VGEN - string filename = name + ".v"; - retname = name + "(" + glc.PrintIO(false) + ")"; - vfile.open(filename.c_str()); - outbuf = std::cout.rdbuf(vfile.rdbuf()); - OuterIndPos = glc.getpos(); - oldenmarg = glc.getenablemargin(); - glc.enablemargin(1); - glc.setpos(0); - PrintHeader(); - cout << glc.getmargin() << "function [" << dec << h << ":" << l << "] " << name << ";\n" << flush; - glc.setfunction(1); - glc.Print(); - glc.setFileOpen(1); - result.setname(name); - result.setbrackets("", ""); -#endif - switchn = 0; - OldChange = glc.getchange(); -} - -void function::vendfunction() { - result.sethlmask(h, l, mask); - result.setr(result.getr() & mask); - glc.setchange(OldChange); -#ifdef VGEN - glc.Outdent(); - cout << glc.getmargin() << "endfunction\n" << flush; - glc.setpos(OuterIndPos); - cout.rdbuf(outbuf); - result.setname(retname); - result.setbrackets("", ""); - vfile.close(); - glc.enablemargin(oldenmarg); -#endif - outregn = 0; -} - -// globcontrol class -------------------------------------------------------------------- - -globcontrol::globcontrol() { -#ifdef VGEN - nomargin = 0; - ndio = 0; - npar = 0; - ndecl = 0; - indpos = 0; - pa = 1; - zeromargin = ""; - VFileOpen = 0; -#endif - alwayscnt = -1; - alwaysn = 1; - change = 0; -} - -#ifdef VGEN -void globcontrol::Print() { - int i; - - if (functiondecl == 0) { - Indent(); - for (i = 0; i < npar; ++i) { - cout << std::endl; - cout << getmargin(); - cout << pars[i]; - if (i != npar - 1) - std::cout << ","; - } - Outdent(); - cout << std::endl << getmargin() << ");\n"; - } - Indent(); - cout << "\n"; - - for (i = 0; i < ndecl; ++i) { - cout << glc.getmargin() << decls[i]; - } - npar = ndecl = 0; - cout << "\n" << flush; -} - -string& globcontrol::PrintIO(bool col) { - int i; - - if (col) - Indent(); - outln = ""; - if (ndio > 0) { - for (i = 0; i < ndio; ++i) { - if (col) { - outln += "\n"; - outln += getmargin(); - } - outln += dios[i]; - if (i < ndio - 1) - outln += ","; - } - } - ndio = 0; - if (col) - Outdent(); - return outln; -} - -void globcontrol::PrepMargin() { - int i; - margin = ""; - for (i = 0; i < indpos; ++i) { - margin += " "; - } -} - -void globcontrol::AddIO(std::string ln) { - dios[ndio] = ln; - ndio++; -} -#endif - -void globcontrol::setchange(int i) { change = i; } - -char* globcontrol::constant(int bits, char* value) { - sprintf(constring, "%d%s", bits, value); - return constring; -} - -char* globcontrol::constant(int bits, int value) { - sprintf(constring, "%d'd%u", bits, (unsigned)value); - return constring; -} diff --git a/L1Trigger/CSCTrackFinder/BuildFile.xml b/L1Trigger/CSCTrackFinder/BuildFile.xml index 3247dd45ea553..224b49b71d918 100644 --- a/L1Trigger/CSCTrackFinder/BuildFile.xml +++ b/L1Trigger/CSCTrackFinder/BuildFile.xml @@ -1,7 +1,7 @@ - + diff --git a/L1Trigger/CSCTrackFinder/doc/convert_vpp b/L1Trigger/CSCTrackFinder/doc/convert_vpp deleted file mode 100755 index 526434eaeca75..0000000000000 --- a/L1Trigger/CSCTrackFinder/doc/convert_vpp +++ /dev/null @@ -1,165 +0,0 @@ -#!/bin/csh -f -# this script converts Madorsky's version of SP core firmware to CMSSW version -# First version March 1, 2008 DA -# - -# initial stuff not in script: -echo "This script will convert Alex Madorskys SP verilog++ core" -echo "to something compatible with the conventions in CMSSW" -echo " " -echo "Assumptions:" -echo "- assumes Architecture.h is on line 1 else line 9 for SPvpp.cc" -echo "- make sure you delete vmac.h from any SPvpp header files (i.e. L1MuCSC_SPvpp_fsu.cpp)" -echo " " - -# put translated files into convert/ subdirectory -rm -rf convert -mkdir convert - -# defin quote -set q = '"' -# defin slash -set s = '/' -# defin lbra, rbra -set lbra = '<' -set rbra = '>' - -# First take care of .cpp files: -foreach i (L1MuCSC_*.cpp) -#foreach i (L1MuCSC_SPvpp_eu2b2.cpp) - echo "processing "$i":" - set name = `echo $i | awk '{s = substr($1,1,length($1)-4); print s}'` -# echo " "$name - set newname = `echo $name | awk '{s = substr($1,9,length($1)); print s}'` -# echo " newname: "$newname - - rm -f junk* - -# rename class - sed -e "s/L1MuCSC_//" $i > junk - -# remove architecture.h, assuming it is first line - if ( $newname != SPvpp ) then - sed -e "1,1 d" junk > junk2 - else - sed -e "9,9 d" junk > junk2 - endif - -# change directories for includes, and put in brackets - sed -e "s_\"$q"Trigger/L1CSCTrackFinder_\"$lbra"L1Trigger/CSCTrackFinder_" junk2 > junk3 - sed -e "/^#/s/\"$q"/\"$rbra"/" junk3 > junk4 - -# change directory for vmac - sed -e "s_L1Trigger/CSCTrackFinder/src/vmac_L1Trigger/CSCCommonTrigger/interface/vmac_" junk4 > junk5 - -# copy to directory with new filename and change file extension - cp junk5 convert/$newname.cc - -end - -# Now vlib.cc -foreach i (vlib.cpp) - echo "processing "$i":" - set name = `echo $i | awk '{s = substr($1,1,length($1)-4); print s}'` -# echo " "$name - set newname = `echo $name | awk '{s = substr($1,1,length($1)); print s}'` -# echo " newname: "$newname - - rm -f junk* - -# change directories for includes, and put in brackets - sed -e "/^#/s_\"$q"vlib_\"$lbra"L1Trigger/CSCCommonTrigger/interface/vlib_" $i > junk - sed -e "1,6 s/\"$q"/\"$rbra"/" junk > junk2 - -# change directory for vmac - sed -e "s_L1Trigger/CSCTrackFinder/src/vmac_L1Trigger/CSCCommonTrigger/interface/vmac_" junk2 > junk3 - -# remove extraneous ";" - sed -e "/^unop/ s/);/)/" junk3 > junk4 - sed -e "/^binop/ s/);/)/" junk4 > junk5 - sed -e "/^compop/ s/);/)/" junk5 > junk6 - sed -e "s/};/}/" junk6 > junk7 - - -# copy to directory with new filename and change file extension - cp junk7 convert/$newname.cc - -end - -# Next take care of .h files: -foreach i (L1MuCSC_*.h) -#foreach i (L1MuCSC_SPvpp.h) - echo "processing "$i":" - set name = `echo $i | awk '{s = substr($1,1,length($1)-2); print s}'` -# echo " "$name - set newname = `echo $name | awk '{s = substr($1,9,length($1)); print s}'` -# echo " newname: "$newname - - rm -f junk* - -# rename class - sed -e "s/L1MuCSC_//" $i > junk - -# change directories for includes, and put in brackets - sed -e "s_\"$q"Trigger/L1CSCTrackFinder_\"$lbra"L1Trigger/CSCTrackFinder_" junk > junk2 - sed -e "/^#/s/\"$q"/\"$rbra"/" junk2 > junk3 - -# change directory for vlib - sed -e "s_L1Trigger/CSCTrackFinder/src/vlib_L1Trigger/CSCCommonTrigger/interface/vlib_" junk3 > junk4 - -# now make sure header files wrapped in ifndef - set chk = `grep ifndef junk4` - set add = `echo $chk | awk '{s = substr($1,2,7); print s}'` - if ( $add != ifndef ) then - cp junk4 junk5 - echo "#ifndef _FILE_"$newname"_FILE_" > junkH - echo "#define _FILE_"$newname"_FILE_" >> junkH - echo "#endif" > junkT - cat junkH junk5 junkT > junk4 - endif - -# copy to directory with new filename - cp junk4 convert/$newname.h - -end - -# now other cases - -foreach i (vlib.h) - echo "processing "$i":" - set name = `echo $i | awk '{s = substr($1,1,length($1)-2); print s}'` -# echo " "$name - set newname = `echo $name | awk '{s = substr($1,1,length($1)); print s}'` -# echo " newname: "$newname - - rm -f junk* - cp $i junk - -# now make sure RVALS defined - set chk = `grep "define RVALS" $i` - set add = `echo $chk | awk '{s = substr($1,2,7); print s}'` - if ( $add != define ) then - cp junk junk2 - echo "#ifndef RVALS" > junkH - echo "#define RVALS 2 // max bits in reg/wire divided by 32" >> junkH - echo "#endif" >>junkH - cat junkH junk2 > junk - endif - -# copy to directory with new filename - cp junk convert/$newname.h - -end - -# do nothing -cp spbits.h convert/ -cp vmac.h convert/ - - - -echo " " -echo "Everything copied to convert/" -echo "- Add ';' to end of line 25 of vlib.cc" -echo "- Now move vmac.h to L1Trigger/CSCCommonTrigger/interface/vmac.h" -echo "- Now move vlib.h to L1Trigger/CSCCommonTrigger/interface/vlib.h" -echo "- Now move vlib.cc to L1Trigger/CSCCommonTrigger/src/vlib.cc" diff --git a/L1Trigger/CSCTrackFinder/python/csctfDigis_cfi.py b/L1Trigger/CSCTrackFinder/python/csctfDigis_cfi.py index 964467b734627..f2563cea2cbec 100644 --- a/L1Trigger/CSCTrackFinder/python/csctfDigis_cfi.py +++ b/L1Trigger/CSCTrackFinder/python/csctfDigis_cfi.py @@ -1,6 +1,6 @@ import FWCore.ParameterSet.Config as cms -from L1Trigger.CSCCommonTrigger.CSCCommonTrigger_cfi import * +from L1Trigger.CSCTriggerPrimitives.CSCCommonTrigger_cfi import * csctfDigis = cms.EDProducer("CSCTFCandidateProducer", CSCTrackProducer = cms.untracked.InputTag("csctfTrackDigis"), MuonSorter = cms.PSet( diff --git a/L1Trigger/CSCTrackFinder/python/csctfTrackDigis_cfi.py b/L1Trigger/CSCTrackFinder/python/csctfTrackDigis_cfi.py index b35beffa84f03..2da479125836c 100644 --- a/L1Trigger/CSCTrackFinder/python/csctfTrackDigis_cfi.py +++ b/L1Trigger/CSCTrackFinder/python/csctfTrackDigis_cfi.py @@ -11,7 +11,7 @@ def _modifyCsctfTrackDigisForRun2( object ) : object.SectorProcessor.initializeFromPSet = False -from L1Trigger.CSCCommonTrigger.CSCCommonTrigger_cfi import * +from L1Trigger.CSCTriggerPrimitives.CSCCommonTrigger_cfi import * csctfTrackDigis = cms.EDProducer("CSCTFTrackProducer", DTproducer = cms.untracked.InputTag("dtTriggerPrimitiveDigis"), DtDirectProd = cms.untracked.InputTag("csctfunpacker","DT"), diff --git a/L1Trigger/CSCTrackFinder/src/CSCSectorReceiverLUT.cc b/L1Trigger/CSCTrackFinder/src/CSCSectorReceiverLUT.cc index 50a415bb5b641..48010e6643421 100644 --- a/L1Trigger/CSCTrackFinder/src/CSCSectorReceiverLUT.cc +++ b/L1Trigger/CSCTrackFinder/src/CSCSectorReceiverLUT.cc @@ -1,7 +1,6 @@ #include #include -#include -#include +#include #include #include #include @@ -143,7 +142,7 @@ lclphidat CSCSectorReceiverLUT::calcLocalPhi(const lclphiadd& theadd) const { double patternOffset; - patternOffset = CSCPatternLUT::get2007Position((theadd.pattern_type << 3) + theadd.clct_pattern); + patternOffset = CSCPatternBank::getLegacyPosition((theadd.pattern_type << 3) + theadd.clct_pattern); // The phiL value stored is for the center of the half-/di-strip. if (theadd.strip < 2 * CSCConstants::MAX_NUM_STRIPS) diff --git a/L1Trigger/CSCTrackFinder/src/CSCSectorReceiverMiniLUT.cc b/L1Trigger/CSCTrackFinder/src/CSCSectorReceiverMiniLUT.cc index 9fec1508456b3..d62ad2a736810 100644 --- a/L1Trigger/CSCTrackFinder/src/CSCSectorReceiverMiniLUT.cc +++ b/L1Trigger/CSCTrackFinder/src/CSCSectorReceiverMiniLUT.cc @@ -1,5 +1,4 @@ -#include -#include +#include #include #include #include diff --git a/L1Trigger/CSCTriggerPrimitives/BuildFile.xml b/L1Trigger/CSCTriggerPrimitives/BuildFile.xml index 778727f9a5bdb..183788a0c9df1 100644 --- a/L1Trigger/CSCTriggerPrimitives/BuildFile.xml +++ b/L1Trigger/CSCTriggerPrimitives/BuildFile.xml @@ -8,7 +8,7 @@ - + diff --git a/L1Trigger/CSCTriggerPrimitives/README.md b/L1Trigger/CSCTriggerPrimitives/README.md index bbad22d9da23a..b0540c7ca99a8 100644 --- a/L1Trigger/CSCTriggerPrimitives/README.md +++ b/L1Trigger/CSCTriggerPrimitives/README.md @@ -77,7 +77,7 @@ A important property of ALCTs/CLCTs/LCTs is the timing, given by the bunch cross The emulator in CMSSW uses the same convention. However, for a long time the emulator would set BX0 to 6 for ALCT, CLCT and LCT. The convention in CMSSW was changed in this [pull request](https://github.com/cms-sw/cmssw/pull/22288) for the entire trigger system. In older CMSSW releases (e.g. CMSSW_10_1_X and earlier) you will find ALCTs, CLCTs and LCTs at BX0 = 6. -ALCTs constructed with the ALCT processor have BX0=8 throughout the simulation. However, right before they are read out, the BX0 is shifted by -5 BX to BX0=3 so that they agree with the firmware. CLCTs constructed with the CLCT processor have BX0=7. However, when they are used in the `CSCMotherboard` to be correlated to ALCTs, they are shifted by +1 BX to BX0=8. That ensures that ALCT and CLCT timing follow the same definition in the correlation algorithm. LCTs constructed with the `CSCMotherboard` have BX0=8. The central timing, among various other system settings, is hard-coded in [CSCConstants](https://github.com/cms-sw/cmssw/blob/master/L1Trigger/CSCCommonTrigger/interface/CSCConstants.h). +ALCTs constructed with the ALCT processor have BX0=8 throughout the simulation. However, right before they are read out, the BX0 is shifted by -5 BX to BX0=3 so that they agree with the firmware. CLCTs constructed with the CLCT processor have BX0=7. However, when they are used in the `CSCMotherboard` to be correlated to ALCTs, they are shifted by +1 BX to BX0=8. That ensures that ALCT and CLCT timing follow the same definition in the correlation algorithm. LCTs constructed with the `CSCMotherboard` have BX0=8. The central timing, among various other system settings, is hard-coded in CSCConstants.h. ## History diff --git a/L1Trigger/CSCTriggerPrimitives/interface/CSCPatternBank.h b/L1Trigger/CSCTriggerPrimitives/interface/CSCPatternBank.h index dd7fad145e2c4..de2a2e71cb47e 100644 --- a/L1Trigger/CSCTriggerPrimitives/interface/CSCPatternBank.h +++ b/L1Trigger/CSCTriggerPrimitives/interface/CSCPatternBank.h @@ -37,6 +37,19 @@ class CSCPatternBank { // Use during Run-1 and Run-2 static const LCTPatterns clct_pattern_legacy_; + /** + * Fill the pattern lookup table. This table holds the average position + * and bend for each pattern. The position is used to further improve + * the phi resolution, and the bend is passed on to the track finding code + * to allow it to better determine the tracks. + * These were determined from Monte Carlo by running 100,000 events through + * the code and finding the offset for each pattern type. + * Note that the positions are unitless-- they are in "pattern widths" + * meaning that they are in 1/2 strips for high pt patterns and distrips + * for low pt patterns. BHT 26 June 2001 + */ + static double getLegacyPosition(int pattern); + // New patterns for Run-3 static const LCTPatterns clct_pattern_run3_; diff --git a/L1Trigger/CSCTriggerPrimitives/interface/CSCPatternLUT.h b/L1Trigger/CSCTriggerPrimitives/interface/CSCPatternLUT.h new file mode 100644 index 0000000000000..9e4c2ed388e4d --- /dev/null +++ b/L1Trigger/CSCTriggerPrimitives/interface/CSCPatternLUT.h @@ -0,0 +1,21 @@ +#ifndef L1Trigger_CSCPatternLUT_h +#define L1Trigger_CSCPatternLUT_h + +/** + *\class CSCPatternLUT + *\author L. Gray (UF) + * + * This class is a static interface to the CLCT Pattern LUT. + * This was factored out of the Sector Receiver since it is used in + * parts of the trigger primitive generator (I think). + */ +#include + +class CSCPatternLUT { +public: + static double get2007Position(int pattern); + +private: +}; + +#endif diff --git a/L1Trigger/CSCTriggerPrimitives/plugins/BuildFile.xml b/L1Trigger/CSCTriggerPrimitives/plugins/BuildFile.xml index 210406f850d44..a844fba67b58a 100644 --- a/L1Trigger/CSCTriggerPrimitives/plugins/BuildFile.xml +++ b/L1Trigger/CSCTriggerPrimitives/plugins/BuildFile.xml @@ -7,7 +7,6 @@ - diff --git a/L1Trigger/CSCCommonTrigger/python/CSCCommonTrigger_cfi.py b/L1Trigger/CSCTriggerPrimitives/python/CSCCommonTrigger_cfi.py similarity index 100% rename from L1Trigger/CSCCommonTrigger/python/CSCCommonTrigger_cfi.py rename to L1Trigger/CSCTriggerPrimitives/python/CSCCommonTrigger_cfi.py diff --git a/L1Trigger/CSCTriggerPrimitives/python/cscTriggerPrimitiveDigis_cfi.py b/L1Trigger/CSCTriggerPrimitives/python/cscTriggerPrimitiveDigis_cfi.py index 310c57369ddba..35dbd0a94d5ea 100644 --- a/L1Trigger/CSCTriggerPrimitives/python/cscTriggerPrimitiveDigis_cfi.py +++ b/L1Trigger/CSCTriggerPrimitives/python/cscTriggerPrimitiveDigis_cfi.py @@ -1,6 +1,6 @@ import FWCore.ParameterSet.Config as cms -from L1Trigger.CSCCommonTrigger.CSCCommonTrigger_cfi import * +from L1Trigger.CSCTriggerPrimitives.CSCCommonTrigger_cfi import * # Default parameters for CSCTriggerPrimitives generator # ===================================================== cscTriggerPrimitiveDigis = cms.EDProducer("CSCTriggerPrimitivesProducer", diff --git a/L1Trigger/CSCTriggerPrimitives/src/CSCPatternBank.cc b/L1Trigger/CSCTriggerPrimitives/src/CSCPatternBank.cc index 6ce2ad109a81a..e32427f914594 100644 --- a/L1Trigger/CSCTriggerPrimitives/src/CSCPatternBank.cc +++ b/L1Trigger/CSCTriggerPrimitives/src/CSCPatternBank.cc @@ -28,6 +28,13 @@ const CSCPatternBank::LCTPatterns CSCPatternBank::alct_pattern_r1_ = { // Collision pattern B {{0, 1, 1, 0, 0}, {0, 1, 1, 0, 0}, {0, 0, 1, 0, 0}, {0, 0, 1, 0, 0}, {0, 0, 1, 1, 0}, {0, 0, 1, 1, 0}}}; +double CSCPatternBank::getLegacyPosition(int pattern) { + double PositionList[CSCConstants::NUM_CLCT_PATTERNS] = { + 0.0, 0.0, -0.60, 0.60, -0.64, 0.64, -0.23, 0.23, -0.21, 0.21, 0.0}; // offset in the strip number for each pattern + + return PositionList[pattern]; +} + const int CSCPatternBank::clct_pattern_offset_[CSCConstants::CLCT_PATTERN_WIDTH] = { -5, -4, -3, -2, -1, 0, 1, 2, 3, 4, 5}; diff --git a/L1Trigger/CSCTriggerPrimitives/test/macros/CCLUTLinearFitWriter.cpp b/L1Trigger/CSCTriggerPrimitives/test/macros/CCLUTLinearFitWriter.cpp index 60d7fdd359fef..5bda4446a8d7b 100644 --- a/L1Trigger/CSCTriggerPrimitives/test/macros/CCLUTLinearFitWriter.cpp +++ b/L1Trigger/CSCTriggerPrimitives/test/macros/CCLUTLinearFitWriter.cpp @@ -2,7 +2,6 @@ * Authors: William Nash (original), Sven Dildick (adapted) */ -#include "L1Trigger/CSCCommonTrigger/interface/CSCConstants.h" #include "L1Trigger/CSCTriggerPrimitives/interface/CSCPatternBank.h" #include diff --git a/L1Trigger/Configuration/python/L1MuonEmulator_cff.py b/L1Trigger/Configuration/python/L1MuonEmulator_cff.py index c51fbfd3aad65..4c3b9472345de 100644 --- a/L1Trigger/Configuration/python/L1MuonEmulator_cff.py +++ b/L1Trigger/Configuration/python/L1MuonEmulator_cff.py @@ -4,7 +4,6 @@ from L1Trigger.DTTrigger.dtTriggerPrimitiveDigis_cfi import * from L1Trigger.DTTrackFinder.dttfDigis_cfi import * # CSC Trigger -from L1Trigger.CSCCommonTrigger.CSCCommonTrigger_cfi import * from L1Trigger.CSCTriggerPrimitives.cscTriggerPrimitiveDigis_cfi import * from L1Trigger.CSCTrackFinder.csctfTrackDigis_cfi import * from L1Trigger.CSCTrackFinder.csctfDigis_cfi import * diff --git a/L1Trigger/L1TMuon/BuildFile.xml b/L1Trigger/L1TMuon/BuildFile.xml index c87138329ea13..aae7229fef984 100644 --- a/L1Trigger/L1TMuon/BuildFile.xml +++ b/L1Trigger/L1TMuon/BuildFile.xml @@ -9,7 +9,7 @@ - + diff --git a/L1Trigger/L1TMuon/python/simDigis_cff.py b/L1Trigger/L1TMuon/python/simDigis_cff.py index 2aaae7634b403..f37e557f4c5fa 100644 --- a/L1Trigger/L1TMuon/python/simDigis_cff.py +++ b/L1Trigger/L1TMuon/python/simDigis_cff.py @@ -13,7 +13,6 @@ #simDtTriggerPrimitiveDigis.debug = cms.untracked.bool(True) # - CSC TP emulator -from L1Trigger.CSCCommonTrigger.CSCCommonTrigger_cfi import * import L1Trigger.CSCTriggerPrimitives.cscTriggerPrimitiveDigis_cfi simCscTriggerPrimitiveDigis = L1Trigger.CSCTriggerPrimitives.cscTriggerPrimitiveDigis_cfi.cscTriggerPrimitiveDigis.clone( CSCComparatorDigiProducer = 'simMuonCSCDigis:MuonCSCComparatorDigi', diff --git a/L1Trigger/L1TMuon/src/GeometryTranslator.cc b/L1Trigger/L1TMuon/src/GeometryTranslator.cc index 1a5c7e0647854..a2d21348b9cb7 100644 --- a/L1Trigger/L1TMuon/src/GeometryTranslator.cc +++ b/L1Trigger/L1TMuon/src/GeometryTranslator.cc @@ -13,7 +13,7 @@ #include "L1Trigger/DTUtilities/interface/DTTrigGeom.h" #include "DataFormats/L1TMuon/interface/CSCConstants.h" -#include "L1Trigger/CSCCommonTrigger/interface/CSCPatternLUT.h" +#include "L1Trigger/CSCTriggerPrimitives/interface/CSCPatternBank.h" #include "L1Trigger/L1TMuon/interface/MuonTriggerPrimitive.h" @@ -247,7 +247,7 @@ GlobalPoint GeometryTranslator::getCSCSpecificPoint(const TriggerPrimitive& tp) double offset = 0.0; switch (1) { case 1: - offset = CSCPatternLUT::get2007Position(pattern); + offset = CSCPatternBank::getLegacyPosition(pattern); } const unsigned halfstrip_offs = static_cast(0.5 + halfstrip + offset); const unsigned strip = halfstrip_offs / 2 + 1; // geom starts from 1 diff --git a/L1Trigger/L1TMuonEndCap/test/tools/MakeCoordLUT.cc b/L1Trigger/L1TMuonEndCap/test/tools/MakeCoordLUT.cc index 3dc957487c884..0a5de70d30ecb 100644 --- a/L1Trigger/L1TMuonEndCap/test/tools/MakeCoordLUT.cc +++ b/L1Trigger/L1TMuonEndCap/test/tools/MakeCoordLUT.cc @@ -27,10 +27,6 @@ #include "Geometry/CSCGeometry/interface/CSCLayerGeometry.h" #include "Geometry/Records/interface/MuonGeometryRecord.h" -//#include "DataFormats/L1TMuon/interface/CSCConstants.h" -//#include "L1Trigger/CSCCommonTrigger/interface/CSCPatternLUT.h" -//#include "L1Trigger/CSCTrackFinder/interface/CSCSectorReceiverLUT.h" - #include "helper.h" class MakeCoordLUT : public edm::EDAnalyzer { diff --git a/L1Trigger/L1TMuonOverlap/BuildFile.xml b/L1Trigger/L1TMuonOverlap/BuildFile.xml index 99dbaa9e93a3d..3eb0515c366f6 100644 --- a/L1Trigger/L1TMuonOverlap/BuildFile.xml +++ b/L1Trigger/L1TMuonOverlap/BuildFile.xml @@ -9,5 +9,5 @@ - + diff --git a/L1Trigger/L1TMuonOverlap/src/AngleConverter.cc b/L1Trigger/L1TMuonOverlap/src/AngleConverter.cc index 4c6eae666228f..3bded865e4b43 100644 --- a/L1Trigger/L1TMuonOverlap/src/AngleConverter.cc +++ b/L1Trigger/L1TMuonOverlap/src/AngleConverter.cc @@ -6,7 +6,7 @@ #include "FWCore/Utilities/interface/Transition.h" #include "DataFormats/L1TMuon/interface/CSCConstants.h" -#include "L1Trigger/CSCCommonTrigger/interface/CSCPatternLUT.h" +#include "L1Trigger/CSCTriggerPrimitives/interface/CSCPatternBank.h" #include "L1Trigger/DTUtilities/interface/DTTrigGeom.h" @@ -453,7 +453,7 @@ int AngleConverter::getGlobalEta(unsigned int rawid, const CSCCorrelatedLCTDigi double offset = 0.0; switch (1) { case 1: - offset = CSCPatternLUT::get2007Position(pattern); + offset = CSCPatternBank::getLegacyPosition(pattern); } const unsigned halfstrip_offs = unsigned(0.5 + halfstrip + offset); const unsigned strip = halfstrip_offs / 2 + 1; // geom starts from 1 diff --git a/Utilities/ReleaseScripts/scripts/git-publish b/Utilities/ReleaseScripts/scripts/git-publish index 1aded34ab031e..bbcc7be572d94 100755 --- a/Utilities/ReleaseScripts/scripts/git-publish +++ b/Utilities/ReleaseScripts/scripts/git-publish @@ -555,7 +555,7 @@ CMSSW_CATEGORIES={"Operations": ["Configuration/Applications", "L1TriggerConfig/L1GeometryProducers", "L1TriggerConfig/L1GtConfigProducers", "L1TriggerConfig/L1ScalesProducers", "L1TriggerConfig/RCTConfigProducers", "L1TriggerConfig/RPCTriggerConfig", "L1TriggerOffline/Configuration", - "L1TriggerOffline/L1Analyzer", "L1Trigger/CSCCommonTrigger", + "L1TriggerOffline/L1Analyzer", "L1Trigger/CSCTrackFinder", "L1Trigger/CSCTriggerPrimitives", "L1Trigger/Configuration", "L1Trigger/DTBti", "L1Trigger/DTSectorCollector", "L1Trigger/DTTrackFinder", "L1Trigger/DTTraco", "L1Trigger/DTTrigger", From 850f2b0387e2c2d9ff3bc448552587b5def1cd84 Mon Sep 17 00:00:00 2001 From: Sven Dildick Date: Tue, 22 Sep 2020 22:53:57 -0500 Subject: [PATCH 2/2] Remove obsolete file --- .../interface/CSCPatternLUT.h | 21 ------------------- 1 file changed, 21 deletions(-) delete mode 100644 L1Trigger/CSCTriggerPrimitives/interface/CSCPatternLUT.h diff --git a/L1Trigger/CSCTriggerPrimitives/interface/CSCPatternLUT.h b/L1Trigger/CSCTriggerPrimitives/interface/CSCPatternLUT.h deleted file mode 100644 index 9e4c2ed388e4d..0000000000000 --- a/L1Trigger/CSCTriggerPrimitives/interface/CSCPatternLUT.h +++ /dev/null @@ -1,21 +0,0 @@ -#ifndef L1Trigger_CSCPatternLUT_h -#define L1Trigger_CSCPatternLUT_h - -/** - *\class CSCPatternLUT - *\author L. Gray (UF) - * - * This class is a static interface to the CLCT Pattern LUT. - * This was factored out of the Sector Receiver since it is used in - * parts of the trigger primitive generator (I think). - */ -#include - -class CSCPatternLUT { -public: - static double get2007Position(int pattern); - -private: -}; - -#endif