diff --git a/Configuration/StandardSequences/python/SimL1EmulatorRepack_CalouGT_cff.py b/Configuration/StandardSequences/python/SimL1EmulatorRepack_CalouGT_cff.py index 731664cd89fd3..030a44286178d 100644 --- a/Configuration/StandardSequences/python/SimL1EmulatorRepack_CalouGT_cff.py +++ b/Configuration/StandardSequences/python/SimL1EmulatorRepack_CalouGT_cff.py @@ -122,7 +122,8 @@ def _print(ignored): ) -SimL1Emulator = cms.Sequence() -stage2L1Trigger.toReplaceWith(SimL1Emulator, cms.Sequence(unpackEcal+unpackHcal+unpackCSC+unpackDT+unpackRPC+unpackEmtf+unpackCsctf+unpackBmtf+unpackGtStage2 - +SimL1EmulatorCore+packCaloStage2 - +packGtStage2+rawDataCollector)) +SimL1EmulatorTask = cms.Task() +stage2L1Trigger.toReplaceWith(SimL1EmulatorTask, cms.Task(unpackEcal,unpackHcal,unpackCSC,unpackDT,unpackRPC,unpackEmtf,unpackCsctf,unpackBmtf,unpackGtStage2 + ,SimL1EmulatorCoreTask,packCaloStage2 + ,packGtStage2,rawDataCollector)) +SimL1Emulator = cms.Sequence(SimL1EmulatorTask) diff --git a/Configuration/StandardSequences/python/SimL1EmulatorRepack_Full2015Data_cff.py b/Configuration/StandardSequences/python/SimL1EmulatorRepack_Full2015Data_cff.py index 37ab83947121b..1e489c545bcf3 100644 --- a/Configuration/StandardSequences/python/SimL1EmulatorRepack_Full2015Data_cff.py +++ b/Configuration/StandardSequences/python/SimL1EmulatorRepack_Full2015Data_cff.py @@ -95,7 +95,8 @@ def _print(ignored): ) -SimL1Emulator = cms.Sequence() -stage2L1Trigger.toReplaceWith(SimL1Emulator, cms.Sequence(unpackEcal+unpackHcal+unpackCSC+unpackDT+unpackRPC+unpackDttf+unpackCsctf - +simHcalTriggerPrimitiveDigis+SimL1EmulatorCore+packCaloStage2 - +packGmtStage2+packGtStage2+rawDataCollector)) +SimL1EmulatorTask = cms.Task() +stage2L1Trigger.toReplaceWith(SimL1EmulatorTask, cms.Task(unpackEcal,unpackHcal,unpackCSC,unpackDT,unpackRPC,unpackDttf,unpackCsctf + ,simHcalTriggerPrimitiveDigis,SimL1EmulatorCoreTask,packCaloStage2 + ,packGmtStage2,packGtStage2,rawDataCollector)) +SimL1Emulator = cms.Sequence(SimL1EmulatorTask) diff --git a/Configuration/StandardSequences/python/SimL1EmulatorRepack_FullMC_cff.py b/Configuration/StandardSequences/python/SimL1EmulatorRepack_FullMC_cff.py index 99fa9933d2cd1..a24d0ece093f6 100644 --- a/Configuration/StandardSequences/python/SimL1EmulatorRepack_FullMC_cff.py +++ b/Configuration/StandardSequences/python/SimL1EmulatorRepack_FullMC_cff.py @@ -101,16 +101,17 @@ def _print(ignored): ] ) -SimL1Emulator = cms.Sequence() -stage2L1Trigger.toReplaceWith(SimL1Emulator, cms.Sequence(unpackRPC - + unpackDT - + unpackCSC - + unpackEcal - + unpackHcal - #+ simEcalTriggerPrimitiveDigis - + simHcalTriggerPrimitiveDigis - + SimL1EmulatorCore - + packCaloStage2 - + packGmtStage2 - + packGtStage2 - + rawDataCollector)) +SimL1EmulatorTask = cms.Task() +stage2L1Trigger.toReplaceWith(SimL1EmulatorTask, cms.Task(unpackRPC + , unpackDT + , unpackCSC + , unpackEcal + , unpackHcal + #, simEcalTriggerPrimitiveDigis + , simHcalTriggerPrimitiveDigis + , SimL1EmulatorCoreTask + , packCaloStage2 + , packGmtStage2 + , packGtStage2 + , rawDataCollector)) +SimL1Emulator = cms.Sequence(SimL1EmulatorTask) diff --git a/Configuration/StandardSequences/python/SimL1EmulatorRepack_FullSimTP_cff.py b/Configuration/StandardSequences/python/SimL1EmulatorRepack_FullSimTP_cff.py index 1bc0d61031e77..90f8d42cc5513 100644 --- a/Configuration/StandardSequences/python/SimL1EmulatorRepack_FullSimTP_cff.py +++ b/Configuration/StandardSequences/python/SimL1EmulatorRepack_FullSimTP_cff.py @@ -113,9 +113,11 @@ def _print(ignored): ] ) -SimL1Emulator = cms.Sequence() -stage2L1Trigger.toReplaceWith(SimL1Emulator, cms.Sequence(unpackEcal+unpackHcal+unpackCSC+unpackDT+unpackRPC+unpackEmtf+unpackCsctf+unpackBmtf - +simEcalTriggerPrimitiveDigis - +simHcalTriggerPrimitiveDigis - +SimL1EmulatorCore+packCaloStage2 - +packGmtStage2+packGtStage2+rawDataCollector)) + +SimL1EmulatorTask = cms.Task() +stage2L1Trigger.toReplaceWith(SimL1EmulatorTask, cms.Task(unpackEcal,unpackHcal,unpackCSC,unpackDT,unpackRPC,unpackEmtf,unpackCsctf,unpackBmtf + ,simEcalTriggerPrimitiveDigis + ,simHcalTriggerPrimitiveDigis + ,SimL1EmulatorCoreTask,packCaloStage2 + ,packGmtStage2,packGtStage2,rawDataCollector)) +SimL1Emulator = cms.Sequence(SimL1EmulatorTask) diff --git a/Configuration/StandardSequences/python/SimL1EmulatorRepack_Full_cff.py b/Configuration/StandardSequences/python/SimL1EmulatorRepack_Full_cff.py index 61671c9438141..ed16decddc813 100644 --- a/Configuration/StandardSequences/python/SimL1EmulatorRepack_Full_cff.py +++ b/Configuration/StandardSequences/python/SimL1EmulatorRepack_Full_cff.py @@ -151,10 +151,10 @@ def _print(ignored): ) -SimL1Emulator = cms.Sequence() -stage2L1Trigger.toReplaceWith(SimL1Emulator, cms.Sequence(unpackEcal+unpackHcal+unpackCSC+unpackDT+unpackRPC+unpackRPCTwinMux+unpackTwinMux+unpackOmtf+unpackEmtf+unpackCsctf+unpackBmtf - +unpackLayer1 - +unpackTcds - +SimL1EmulatorCore+packCaloStage2 - +packGmtStage2+packGtStage2+rawDataCollector)) - +SimL1EmulatorTask = cms.Task() +stage2L1Trigger.toReplaceWith(SimL1EmulatorTask, cms.Task(unpackEcal,unpackHcal,unpackCSC,unpackDT,unpackRPC,unpackRPCTwinMux,unpackTwinMux,unpackOmtf,unpackEmtf,unpackCsctf,unpackBmtf + ,unpackLayer1 + ,unpackTcds + ,SimL1EmulatorCoreTask,packCaloStage2 + ,packGmtStage2,packGtStage2,rawDataCollector)) +SimL1Emulator = cms.Sequence(SimL1EmulatorTask) diff --git a/Configuration/StandardSequences/python/SimL1EmulatorRepack_GCTGT_cff.py b/Configuration/StandardSequences/python/SimL1EmulatorRepack_GCTGT_cff.py index 1059887102998..834b4249888f3 100644 --- a/Configuration/StandardSequences/python/SimL1EmulatorRepack_GCTGT_cff.py +++ b/Configuration/StandardSequences/python/SimL1EmulatorRepack_GCTGT_cff.py @@ -93,14 +93,15 @@ ## construct SimL1Emulator sequence ## -SimL1Emulator = cms.Sequence( - unpackGtDigis + - unpackCastorDigis + - L1TCaloStage1_PPFromRaw + - newGtDigis + - packGctDigis + - packL1tDigis + - packL1Gt + - packL1GtEvm + +SimL1EmulatorTask = cms.Task( + unpackGtDigis , + unpackCastorDigis , + L1TCaloStage1_PPFromRawTask , + newGtDigis , + packGctDigis , + packL1tDigis , + packL1Gt , + packL1GtEvm , rawDataCollector ) +SimL1Emulator = cms.Sequence(SimL1EmulatorTask) diff --git a/Configuration/StandardSequences/python/SimL1EmulatorRepack_GT1_cff.py b/Configuration/StandardSequences/python/SimL1EmulatorRepack_GT1_cff.py index 5ebda5cfdb837..dc026fb5bc2d6 100644 --- a/Configuration/StandardSequences/python/SimL1EmulatorRepack_GT1_cff.py +++ b/Configuration/StandardSequences/python/SimL1EmulatorRepack_GT1_cff.py @@ -67,12 +67,13 @@ ## construct SimL1Emulator sequence ## -SimL1Emulator = cms.Sequence( - unpackGctDigis + - unpackGtDigis + - unpackCastorDigis + - newGtDigis + - packL1Gt + - packL1GtEvm + +SimL1EmulatorTask = cms.Task( + unpackGctDigis , + unpackGtDigis , + unpackCastorDigis , + newGtDigis , + packL1Gt , + packL1GtEvm , rawDataCollector ) +SimL1Emulator = cms.Sequence(SimL1EmulatorTask) diff --git a/Configuration/StandardSequences/python/SimL1EmulatorRepack_GT2_cff.py b/Configuration/StandardSequences/python/SimL1EmulatorRepack_GT2_cff.py index ca74888766662..a7d613c973bad 100644 --- a/Configuration/StandardSequences/python/SimL1EmulatorRepack_GT2_cff.py +++ b/Configuration/StandardSequences/python/SimL1EmulatorRepack_GT2_cff.py @@ -76,13 +76,14 @@ ## construct SimL1Emulator sequence ## -SimL1Emulator = cms.Sequence( - unpackGctStage1 + - unpackGctDigis + - unpackGtDigis + - unpackCastorDigis + - newGtDigis + - packL1Gt + - packL1GtEvm + +SimL1EmulatorTask = cms.Task( + unpackGctStage1 , + unpackGctDigis , + unpackGtDigis , + unpackCastorDigis , + newGtDigis , + packL1Gt , + packL1GtEvm , rawDataCollector ) +SimL1Emulator = cms.Sequence(SimL1EmulatorTask) diff --git a/Configuration/StandardSequences/python/SimL1EmulatorRepack_GT_cff.py b/Configuration/StandardSequences/python/SimL1EmulatorRepack_GT_cff.py index 35624825f3423..10fdf032e54a0 100644 --- a/Configuration/StandardSequences/python/SimL1EmulatorRepack_GT_cff.py +++ b/Configuration/StandardSequences/python/SimL1EmulatorRepack_GT_cff.py @@ -61,13 +61,13 @@ ) ) -SimL1Emulator = cms.Sequence( +SimL1EmulatorTask = cms.Task( unpackGctDigis - + unpackGtDigis - + unpackCastorDigis - + simGtDigis - + l1GtPack - + l1GtEvmPack - + rawDataCollector + , unpackGtDigis + , unpackCastorDigis + , simGtDigis + , l1GtPack + , l1GtEvmPack + , rawDataCollector ) - +SimL1Emulator = cms.Sequence(SimL1EmulatorTask) diff --git a/Configuration/StandardSequences/python/SimL1EmulatorRepack_uGT_cff.py b/Configuration/StandardSequences/python/SimL1EmulatorRepack_uGT_cff.py index 88a8bbcdc7a25..77d42a519bd52 100644 --- a/Configuration/StandardSequences/python/SimL1EmulatorRepack_uGT_cff.py +++ b/Configuration/StandardSequences/python/SimL1EmulatorRepack_uGT_cff.py @@ -57,10 +57,11 @@ def _print(ignored): ) -SimL1Emulator = cms.Sequence() -stage2L1Trigger.toReplaceWith(SimL1Emulator, cms.Sequence(unpackGtStage2 - +unpackTcds - +SimL1TechnicalTriggers - +SimL1TGlobal - +packGtStage2 - +rawDataCollector)) +SimL1EmulatorTask = cms.Task() +stage2L1Trigger.toReplaceWith(SimL1EmulatorTask, cms.Task(unpackGtStage2 + ,unpackTcds + ,SimL1TechnicalTriggersTask + ,SimL1TGlobalTask + ,packGtStage2 + ,rawDataCollector)) +SimL1Emulator = cms.Sequence(SimL1EmulatorTask) diff --git a/HLTrigger/Configuration/python/CustomConfigs.py b/HLTrigger/Configuration/python/CustomConfigs.py index ad05255cc1650..13bec695fdeeb 100644 --- a/HLTrigger/Configuration/python/CustomConfigs.py +++ b/HLTrigger/Configuration/python/CustomConfigs.py @@ -146,7 +146,7 @@ def L1REPACK(process,sequence="Full"): getattr(process,path).insert(0,process.SimL1Emulator) # special L1T cleanup - for obj in ('SimL1TCalorimeter','SimL1TMuonCommon','SimL1TMuon','SimL1TechnicalTriggers','SimL1EmulatorCore','ecalDigiSequence','hcalDigiSequence','calDigi','me0TriggerPseudoDigiSequence','hgcalTriggerGeometryESProducer'): + for obj in ('SimL1TCalorimeter','SimL1TMuonCommon','SimL1TMuon','SimL1TechnicalTriggers','SimL1EmulatorCore','ecalDigiSequence','hcalDigiSequence','calDigi','me0TriggerPseudoDigiTask','hgcalTriggerGeometryESProducer'): if hasattr(process,obj): delattr(process,obj) diff --git a/L1Trigger/Configuration/python/SimL1Emulator_cff.py b/L1Trigger/Configuration/python/SimL1Emulator_cff.py index 6c569717f224c..1bd9a6634046d 100644 --- a/L1Trigger/Configuration/python/SimL1Emulator_cff.py +++ b/L1Trigger/Configuration/python/SimL1Emulator_cff.py @@ -37,14 +37,16 @@ from L1Trigger.L1TGlobal.simDigis_cff import * # define a core which can be extented in customizations: -SimL1EmulatorCore = cms.Sequence( - SimL1TCalorimeter + - SimL1TMuon + - SimL1TechnicalTriggers + - SimL1TGlobal - ) +SimL1EmulatorCoreTask = cms.Task( + SimL1TCalorimeterTask, + SimL1TMuonTask, + SimL1TechnicalTriggersTask, + SimL1TGlobalTask +) +SimL1EmulatorCore = cms.Sequence(SimL1EmulatorCoreTask) -SimL1Emulator = cms.Sequence( SimL1EmulatorCore ) +SimL1EmulatorTask = cms.Task(SimL1EmulatorCoreTask) +SimL1Emulator = cms.Sequence( SimL1EmulatorTask ) # # Emulators are configured from DB (GlobalTags) @@ -58,9 +60,9 @@ # Customisation for the phase2_hgcal era. Includes the HGCAL L1 trigger from L1Trigger.L1THGCal.hgcalTriggerPrimitives_cff import * -_phase2_siml1emulator = SimL1Emulator.copy() -_phase2_siml1emulator += hgcalTriggerPrimitives +_phase2_siml1emulator = SimL1EmulatorTask.copy() +_phase2_siml1emulator.add(hgcalTriggerPrimitivesTask) from Configuration.Eras.Modifier_phase2_hgcal_cff import phase2_hgcal from Configuration.Eras.Modifier_phase2_hgcalV9_cff import phase2_hgcalV9 -phase2_hgcal.toReplaceWith( SimL1Emulator , _phase2_siml1emulator ) +phase2_hgcal.toReplaceWith( SimL1EmulatorTask , _phase2_siml1emulator ) diff --git a/L1Trigger/Configuration/python/SimL1TechnicalTriggers_cff.py b/L1Trigger/Configuration/python/SimL1TechnicalTriggers_cff.py index 7de50754eac94..aa1013eac6c8d 100644 --- a/L1Trigger/Configuration/python/SimL1TechnicalTriggers_cff.py +++ b/L1Trigger/Configuration/python/SimL1TechnicalTriggers_cff.py @@ -4,7 +4,8 @@ import L1Trigger.L1TGlobal.simGtExtFakeProd_cfi simGtExtFakeStage2Digis = L1Trigger.L1TGlobal.simGtExtFakeProd_cfi.simGtExtFakeProd.clone() -SimL1TechnicalTriggers = cms.Sequence(simGtExtFakeStage2Digis) +SimL1TechnicalTriggersTask = cms.Task(simGtExtFakeStage2Digis) +SimL1TechnicalTriggers = cms.Sequence(SimL1TechnicalTriggersTask) # BSC Technical Trigger @@ -26,8 +27,8 @@ simCastorTechTrigDigis = SimCalorimetry.CastorTechTrigProducer.castorTTRecord_cfi.simCastorTTRecord.clone() from Configuration.Eras.Modifier_stage2L1Trigger_cff import stage2L1Trigger -(~stage2L1Trigger).toReplaceWith(SimL1TechnicalTriggers, cms.Sequence( - simBscDigis + - simRpcTechTrigDigis + - simHcalTechTrigDigis + +(~stage2L1Trigger).toReplaceWith(SimL1TechnicalTriggersTask, cms.Task( + simBscDigis, + simRpcTechTrigDigis, + simHcalTechTrigDigis, simCastorTechTrigDigis )) diff --git a/L1Trigger/L1TCalorimeter/python/L1TCaloStage1_PPFromRaw_cff.py b/L1Trigger/L1TCalorimeter/python/L1TCaloStage1_PPFromRaw_cff.py index 4f910cad344dc..7263a33ea31a4 100644 --- a/L1Trigger/L1TCalorimeter/python/L1TCaloStage1_PPFromRaw_cff.py +++ b/L1Trigger/L1TCalorimeter/python/L1TCaloStage1_PPFromRaw_cff.py @@ -43,9 +43,10 @@ # the sequence -L1TCaloStage1_PPFromRaw = cms.Sequence( +L1TCaloStage1_PPFromRawTask = cms.Task( L1TRerunHCALTP_FromRAW - +ecalDigis - +simRctDigis - +L1TCaloStage1 + ,ecalDigis + ,simRctDigis + ,L1TCaloStage1Task ) +L1TCaloStage1_PPFromRaw = cms.Sequence(L1TCaloStage1_PPFromRawTask) diff --git a/L1Trigger/L1TCalorimeter/python/L1TCaloStage1_cff.py b/L1Trigger/L1TCalorimeter/python/L1TCaloStage1_cff.py index a6c86ea979693..72e0b97482b4d 100644 --- a/L1Trigger/L1TCalorimeter/python/L1TCaloStage1_cff.py +++ b/L1Trigger/L1TCalorimeter/python/L1TCaloStage1_cff.py @@ -41,9 +41,10 @@ 0.952755905512, 0.96062992126, 0.968503937008, 0.976377952756, 0.984251968504, 0.992125984252, 1.0, ) -L1TCaloStage1 = cms.Sequence( - simRctUpgradeFormatDigis + - simCaloStage1Digis + - simCaloStage1FinalDigis + +L1TCaloStage1Task = cms.Task( + simRctUpgradeFormatDigis, + simCaloStage1Digis, + simCaloStage1FinalDigis, simCaloStage1LegacyFormatDigis ) +L1TCaloStage1 = cms.Sequence(L1TCaloStage1Task) diff --git a/L1Trigger/L1TCalorimeter/python/L1TCaloStage2_PPFromRaw_cff.py b/L1Trigger/L1TCalorimeter/python/L1TCaloStage2_PPFromRaw_cff.py index 89404680c558d..196d8881f1bcb 100644 --- a/L1Trigger/L1TCalorimeter/python/L1TCaloStage2_PPFromRaw_cff.py +++ b/L1Trigger/L1TCalorimeter/python/L1TCaloStage2_PPFromRaw_cff.py @@ -10,7 +10,8 @@ caloStage2Layer1Digis.hcalToken = cms.InputTag('simHcalTriggerPrimitiveDigis') # the sequence -L1TCaloStage2_PPFromRaw = cms.Sequence( +L1TCaloStage2_PPFromRawTask = cms.Task( L1TRerunHCALTP_FromRAW - +L1TCaloStage2 + ,L1TCaloStage2Task ) +L1TCaloStage2_PPFromRaw = cms.Sequence(L1TCaloStage2_PPFromRawTask) diff --git a/L1Trigger/L1TCalorimeter/python/L1TCaloStage2_cff.py b/L1Trigger/L1TCalorimeter/python/L1TCaloStage2_cff.py index 72b0380681312..3ca104ba4dad4 100644 --- a/L1Trigger/L1TCalorimeter/python/L1TCaloStage2_cff.py +++ b/L1Trigger/L1TCalorimeter/python/L1TCaloStage2_cff.py @@ -3,7 +3,8 @@ from L1Trigger.L1TCalorimeter.caloStage2Layer1Digis_cfi import * from L1Trigger.L1TCalorimeter.caloStage2Digis_cfi import * -L1TCaloStage2 = cms.Sequence( +L1TCaloStage2Task = cms.Task( caloStage2Layer1Digis + caloStage2Digis ) +L1TCaloStage2 = cms.Sequence(L1TCaloStage2Task) diff --git a/L1Trigger/L1TCalorimeter/python/L1TRerunHCALTP_FromRaw_cff.py b/L1Trigger/L1TCalorimeter/python/L1TRerunHCALTP_FromRaw_cff.py index 7a3fafab78f99..bda292c6aed1f 100644 --- a/L1Trigger/L1TCalorimeter/python/L1TRerunHCALTP_FromRaw_cff.py +++ b/L1Trigger/L1TCalorimeter/python/L1TRerunHCALTP_FromRaw_cff.py @@ -10,7 +10,7 @@ HcalTPGCoderULUT.LUTGenerationMode = cms.bool(True) -L1TRerunHCALTP_FromRAW = cms.Sequence( +L1TRerunHCALTP_FromRAW = cms.Task( hcalDigis - * simHcalTriggerPrimitiveDigis + , simHcalTriggerPrimitiveDigis ) diff --git a/L1Trigger/L1TCalorimeter/python/simDigis_cff.py b/L1Trigger/L1TCalorimeter/python/simDigis_cff.py index e994a3400f194..977104f8b73a8 100644 --- a/L1Trigger/L1TCalorimeter/python/simDigis_cff.py +++ b/L1Trigger/L1TCalorimeter/python/simDigis_cff.py @@ -15,7 +15,8 @@ simGctDigis = L1Trigger.GlobalCaloTrigger.gctDigis_cfi.gctDigis.clone( inputLabel = 'simRctDigis' ) -SimL1TCalorimeter = cms.Sequence(simRctDigis + simGctDigis) +SimL1TCalorimeterTask = cms.Task(simRctDigis, simGctDigis) +SimL1TCalorimeter = cms.Sequence(SimL1TCalorimeterTask) # # Stage-1 Trigger @@ -30,7 +31,7 @@ from L1Trigger.L1TCalorimeter.caloConfigStage1PP_cfi import * from Configuration.Eras.Modifier_stage1L1Trigger_cff import stage1L1Trigger from Configuration.Eras.Modifier_stage2L1Trigger_cff import stage2L1Trigger -(stage1L1Trigger & ~stage2L1Trigger).toReplaceWith(SimL1TCalorimeter, cms.Sequence(simRctDigis + simRctUpgradeFormatDigis + simCaloStage1Digis + simCaloStage1FinalDigis + simCaloStage1LegacyFormatDigis)) +(stage1L1Trigger & ~stage2L1Trigger).toReplaceWith(SimL1TCalorimeterTask, cms.Task(simRctDigis, simRctUpgradeFormatDigis, simCaloStage1Digis, simCaloStage1FinalDigis, simCaloStage1LegacyFormatDigis)) # # Stage-2 Trigger @@ -41,7 +42,7 @@ # - layer1 from L1Trigger/L1TCaloLayer1 package from L1Trigger.L1TCaloLayer1.simCaloStage2Layer1Digis_cfi import simCaloStage2Layer1Digis from L1Trigger.L1TCalorimeter.simCaloStage2Digis_cfi import simCaloStage2Digis -stage2L1Trigger.toReplaceWith(SimL1TCalorimeter, cms.Sequence( simCaloStage2Layer1Digis + simCaloStage2Digis )) +stage2L1Trigger.toReplaceWith(SimL1TCalorimeterTask, cms.Task( simCaloStage2Layer1Digis, simCaloStage2Digis )) def _modifyStage2L1TriggerCaloParams(process): from CondCore.CondDB.CondDB_cfi import CondDB diff --git a/L1Trigger/L1TGlobal/python/simDigis_cff.py b/L1Trigger/L1TGlobal/python/simDigis_cff.py index 4ff0f4484a8b1..f28ba03a69d2f 100644 --- a/L1Trigger/L1TGlobal/python/simDigis_cff.py +++ b/L1Trigger/L1TGlobal/python/simDigis_cff.py @@ -22,7 +22,8 @@ 'simCastorTechTrigDigis' ] ) -SimL1TGlobal = cms.Sequence(simGtDigis) +SimL1TGlobalTask = cms.Task(simGtDigis) +SimL1TGlobal = cms.Sequence(SimL1TGlobalTask) # # Stage-2 Trigger @@ -32,4 +33,4 @@ # from L1Trigger.L1TGlobal.simGtStage2Digis_cfi import * from Configuration.Eras.Modifier_stage2L1Trigger_cff import stage2L1Trigger -stage2L1Trigger.toReplaceWith(SimL1TGlobal, cms.Sequence(simGtStage2Digis)) +stage2L1Trigger.toReplaceWith(SimL1TGlobalTask, cms.Task(simGtStage2Digis)) diff --git a/L1Trigger/L1THGCal/python/hgcalBackEndLayer1_cff.py b/L1Trigger/L1THGCal/python/hgcalBackEndLayer1_cff.py index 568c21ab9d703..b93d9ef86ed01 100644 --- a/L1Trigger/L1THGCal/python/hgcalBackEndLayer1_cff.py +++ b/L1Trigger/L1THGCal/python/hgcalBackEndLayer1_cff.py @@ -4,5 +4,5 @@ from L1Trigger.L1THGCal.hgcalBackEndLayer1Producer_cfi import * -hgcalBackEndLayer1 = cms.Sequence(hgcalBackEndLayer1Producer) +hgcalBackEndLayer1 = cms.Task(hgcalBackEndLayer1Producer) diff --git a/L1Trigger/L1THGCal/python/hgcalBackEndLayer2_cff.py b/L1Trigger/L1THGCal/python/hgcalBackEndLayer2_cff.py index eb374009e1898..e8578130e05fc 100644 --- a/L1Trigger/L1THGCal/python/hgcalBackEndLayer2_cff.py +++ b/L1Trigger/L1THGCal/python/hgcalBackEndLayer2_cff.py @@ -4,5 +4,5 @@ from L1Trigger.L1THGCal.hgcalBackEndLayer2Producer_cfi import * -hgcalBackEndLayer2 = cms.Sequence(hgcalBackEndLayer2Producer) +hgcalBackEndLayer2 = cms.Task(hgcalBackEndLayer2Producer) diff --git a/L1Trigger/L1THGCal/python/hgcalConcentrator_cff.py b/L1Trigger/L1THGCal/python/hgcalConcentrator_cff.py index 562d754e18f8c..6626e48c64ee2 100644 --- a/L1Trigger/L1THGCal/python/hgcalConcentrator_cff.py +++ b/L1Trigger/L1THGCal/python/hgcalConcentrator_cff.py @@ -4,5 +4,5 @@ from L1Trigger.L1THGCal.hgcalConcentratorProducer_cfi import * -hgcalConcentrator = cms.Sequence(hgcalConcentratorProducer) +hgcalConcentrator = cms.Task(hgcalConcentratorProducer) diff --git a/L1Trigger/L1THGCal/python/hgcalTowerMap_cff.py b/L1Trigger/L1THGCal/python/hgcalTowerMap_cff.py index 08545d65b87f6..48037134dd8ea 100644 --- a/L1Trigger/L1THGCal/python/hgcalTowerMap_cff.py +++ b/L1Trigger/L1THGCal/python/hgcalTowerMap_cff.py @@ -4,5 +4,5 @@ from L1Trigger.L1THGCal.hgcalTowerMapProducer_cfi import * -hgcalTowerMap = cms.Sequence(hgcalTowerMapProducer) +hgcalTowerMap = cms.Task(hgcalTowerMapProducer) diff --git a/L1Trigger/L1THGCal/python/hgcalTower_cff.py b/L1Trigger/L1THGCal/python/hgcalTower_cff.py index ff693afd31217..ca1faadb6523b 100644 --- a/L1Trigger/L1THGCal/python/hgcalTower_cff.py +++ b/L1Trigger/L1THGCal/python/hgcalTower_cff.py @@ -4,5 +4,5 @@ from L1Trigger.L1THGCal.hgcalTowerProducer_cfi import * -hgcalTower = cms.Sequence(hgcalTowerProducer) +hgcalTower = cms.Task(hgcalTowerProducer) diff --git a/L1Trigger/L1THGCal/python/hgcalTriggerPrimitives_cff.py b/L1Trigger/L1THGCal/python/hgcalTriggerPrimitives_cff.py index bf6347c9c4f2f..5f68158fb2b0f 100644 --- a/L1Trigger/L1THGCal/python/hgcalTriggerPrimitives_cff.py +++ b/L1Trigger/L1THGCal/python/hgcalTriggerPrimitives_cff.py @@ -9,7 +9,8 @@ from L1Trigger.L1THGCal.hgcalTower_cff import * -hgcalTriggerPrimitives = cms.Sequence(hgcalVFE*hgcalConcentrator*hgcalBackEndLayer1*hgcalBackEndLayer2*hgcalTowerMap*hgcalTower) +hgcalTriggerPrimitivesTask = cms.Task(hgcalVFE, hgcalConcentrator, hgcalBackEndLayer1, hgcalBackEndLayer2, hgcalTowerMap, hgcalTower) +hgcalTriggerPrimitives = cms.Sequence(hgcalTriggerPrimitivesTask) from Configuration.Eras.Modifier_phase2_hgcalV9_cff import phase2_hgcalV9 from L1Trigger.L1THGCal.customTriggerGeometry import custom_geometry_V9 @@ -23,5 +24,5 @@ def _fakeHGCalDigiAlias(process): from EventFilter.HGCalRawToDigi.HGCDigiConverter_cfi import HGCDigiConverter as _HGCDigiConverter process.simHGCalUnsuppressedDigis = _HGCDigiConverter.clone() - process.hgcalTriggerPrimitives.insert(0,process.simHGCalUnsuppressedDigis) + process.hgcalTriggerPrimitivesTask.add(process.simHGCalUnsuppressedDigis) doFakeHGCalDigiAlias = convertHGCalDigisSim.makeProcessModifier(_fakeHGCalDigiAlias) diff --git a/L1Trigger/L1THGCal/python/hgcalVFE_cff.py b/L1Trigger/L1THGCal/python/hgcalVFE_cff.py index dc8e77bcfd929..b8380c01cf50b 100644 --- a/L1Trigger/L1THGCal/python/hgcalVFE_cff.py +++ b/L1Trigger/L1THGCal/python/hgcalVFE_cff.py @@ -3,6 +3,5 @@ from L1Trigger.L1THGCal.hgcalTriggerGeometryESProducer_cfi import * from L1Trigger.L1THGCal.hgcalVFEProducer_cfi import * - -hgcalVFE = cms.Sequence(hgcalVFEProducer) +hgcalVFE = cms.Task(hgcalVFEProducer) diff --git a/L1Trigger/L1THGCalUtilities/python/hgcalTriggerChains.py b/L1Trigger/L1THGCalUtilities/python/hgcalTriggerChains.py index 432ae33aef58d..1f03b8ab08eb8 100644 --- a/L1Trigger/L1THGCalUtilities/python/hgcalTriggerChains.py +++ b/L1Trigger/L1THGCalUtilities/python/hgcalTriggerChains.py @@ -39,12 +39,13 @@ def register_chain(self, vfe, concentrator, backend1, backend2, ntuple=''): def create_sequences(self, process): - tmp = cms.SequencePlaceholder("tmp") - vfe_sequence = cms.Sequence(tmp) - concentrator_sequence = cms.Sequence(tmp) - backend1_sequence = cms.Sequence(tmp) - backend2_sequence = cms.Sequence(tmp) - ntuple_sequence = cms.Sequence(tmp) + tmp = cms.TaskPlaceholder("tmp") + tmpseq = cms.SequencePlaceholder("tmp") + vfe_task = cms.Task(tmp) + concentrator_task = cms.Task(tmp) + backend1_task = cms.Task(tmp) + backend2_task = cms.Task(tmp) + ntuple_sequence = cms.Sequence(tmpseq) for vfe,concentrator,backend1,backend2,ntuple in self.chain: concentrator_name = '{0}{1}'.format(vfe, concentrator) backend1_name = '{0}{1}{2}'.format(vfe, concentrator, backend1) @@ -53,27 +54,27 @@ def create_sequences(self, process): ntuple_inputs = [concentrator_name, backend1_name, backend2_name] if not hasattr(process, vfe): setattr(process, vfe, self.vfe[vfe](process)) - vfe_sequence *= getattr(process, vfe) + vfe_task.add(getattr(process, vfe)) if not hasattr(process, concentrator_name): setattr(process, concentrator_name, self.concentrator[concentrator](process, vfe)) - concentrator_sequence *= getattr(process, concentrator_name) + concentrator_task.add(getattr(process, concentrator_name)) if not hasattr(process, backend1_name): setattr(process, backend1_name, self.backend1[backend1](process, concentrator_name)) - backend1_sequence *= getattr(process, backend1_name) + backend1_task.add(getattr(process, backend1_name)) if not hasattr(process, backend2_name): setattr(process, backend2_name, self.backend2[backend2](process, backend1_name)) - backend2_sequence *= getattr(process, backend2_name) + backend2_task.add(getattr(process, backend2_name)) if ntuple!='' and not hasattr(process, ntuple_name): setattr(process, ntuple_name, self.ntuple[ntuple](process, ntuple_inputs)) ntuple_sequence *= getattr(process, ntuple_name) - vfe_sequence.remove(tmp) - concentrator_sequence.remove(tmp) - backend1_sequence.remove(tmp) - backend2_sequence.remove(tmp) - ntuple_sequence.remove(tmp) - process.globalReplace('hgcalVFE', vfe_sequence) - process.globalReplace('hgcalConcentrator', concentrator_sequence) - process.globalReplace('hgcalBackEndLayer1', backend1_sequence) - process.globalReplace('hgcalBackEndLayer2', backend2_sequence) + vfe_task.remove(tmp) + concentrator_task.remove(tmp) + backend1_task.remove(tmp) + backend2_task.remove(tmp) + ntuple_task.remove(tmpseq) + process.globalReplace('hgcalVFE', vfe_task) + process.globalReplace('hgcalConcentrator', concentrator_task) + process.globalReplace('hgcalBackEndLayer1', backend1_task) + process.globalReplace('hgcalBackEndLayer2', backend2_task) process.globalReplace('hgcalTriggerNtuples', ntuple_sequence) return process diff --git a/L1Trigger/L1TMuon/python/simDigis_cff.py b/L1Trigger/L1TMuon/python/simDigis_cff.py index cffde6d9fe12f..37f7b3a697234 100644 --- a/L1Trigger/L1TMuon/python/simDigis_cff.py +++ b/L1Trigger/L1TMuon/python/simDigis_cff.py @@ -20,7 +20,8 @@ CSCWireDigiProducer = 'simMuonCSCDigis:MuonCSCWireDigi' ) -SimL1TMuonCommon = cms.Sequence(simDtTriggerPrimitiveDigis + simCscTriggerPrimitiveDigis) +SimL1TMuonCommonTask = cms.Task(simDtTriggerPrimitiveDigis, simCscTriggerPrimitiveDigis) +SimL1TMuonCommon = cms.Sequence(SimL1TMuonCommonTask) # # Legacy Trigger: @@ -66,7 +67,8 @@ ) # # -SimL1TMuon = cms.Sequence(SimL1TMuonCommon + simCsctfTrackDigis + simCsctfDigis + simDttfDigis + simRpcTriggerDigis + simGmtDigis) +SimL1TMuonTask = cms.Task(SimL1TMuonCommonTask, simCsctfTrackDigis, simCsctfDigis, simDttfDigis, simRpcTriggerDigis, simGmtDigis) +SimL1TMuon = cms.Sequence(SimL1TMuonTask) # # Stage-2 Trigger @@ -80,11 +82,11 @@ from Configuration.Eras.Modifier_stage2L1Trigger_cff import stage2L1Trigger # # -stage2L1Trigger.toReplaceWith(SimL1TMuon, cms.Sequence(SimL1TMuonCommon + simTwinMuxDigis + simBmtfDigis + simEmtfDigis + simOmtfDigis + simGmtCaloSumDigis + simGmtStage2Digis)) +stage2L1Trigger.toReplaceWith(SimL1TMuonTask, cms.Task(SimL1TMuonCommonTask, simTwinMuxDigis, simBmtfDigis, simEmtfDigis, simOmtfDigis, simGmtCaloSumDigis, simGmtStage2Digis)) from L1Trigger.ME0Trigger.me0TriggerPseudoDigis_cff import * -_phase2_SimL1TMuon = SimL1TMuon.copy() -_phase2_SimL1TMuon += me0TriggerPseudoDigiSequence +_phase2_SimL1TMuonTask = SimL1TMuonTask.copy() +_phase2_SimL1TMuonTask.add(me0TriggerPseudoDigiTask) from Configuration.Eras.Modifier_phase2_muon_cff import phase2_muon -(stage2L1Trigger & phase2_muon).toReplaceWith( SimL1TMuon, _phase2_SimL1TMuon ) +(stage2L1Trigger & phase2_muon).toReplaceWith( SimL1TMuonTask, _phase2_SimL1TMuonTask ) diff --git a/L1Trigger/ME0Trigger/python/me0TriggerPseudoDigis_cff.py b/L1Trigger/ME0Trigger/python/me0TriggerPseudoDigis_cff.py index 42e52dcb267d8..af600b6c54339 100644 --- a/L1Trigger/ME0Trigger/python/me0TriggerPseudoDigis_cff.py +++ b/L1Trigger/ME0Trigger/python/me0TriggerPseudoDigis_cff.py @@ -27,8 +27,8 @@ me0TriggerPseudoDigis.algo_psets[1].algo_pset.maxPhiAdditional = cms.double(maxPhi) me0TriggerPseudoDigis.algo_psets[1].algo_pset.maxPhiSeeds = cms.double(maxPhi) -me0TriggerPseudoDigiSequence = cms.Sequence( - simMuonME0PseudoReDigisCoarse * - me0RecHitsCoarse * +me0TriggerPseudoDigiTask = cms.Task( + simMuonME0PseudoReDigisCoarse, + me0RecHitsCoarse, me0TriggerPseudoDigis )