Clash.Intel.DDR: Quartus Verilog errors on uselib macro

[DigitalBrains1]

The DDR primitives in Clash.Intel.DDR use the libraries key to generate the following line in the generated Verilog and SystemVerilog:

  `uselib lib=altera_mf

These primitives currently appear to be the only case where such a uselib line is generated. But Quartus Prime Lite 23.1.1 errors out on it with text macro "uselib" is undefined:

Critical Warning (10191): Verilog HDL Compiler Directive warning at topEntity.v(16): text macro "uselib" is undefined
Error (10170): Verilog HDL syntax error at topEntity.v(16) near text: "=";  expecting ".", or "(". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error (10112): Ignored design unit "topEntity" at topEntity.v(6) due to previous errors

For Quartus to succesfully synthesise the DDR primitive in either Verilog or SystemVerilog, the uselib macro should just be omitted. However, if you want to simulate a design, the Questa Intel Starter FPGA Edition that is shipped with Quartus Prime Lite does require the uselib macro. Using a GUI-based flow, this means you need to omit the uselib line, let Quartus do Analysis & Elaboration, add the uselib line, click Tools -> Run Simulation Tool -> RTL Simulation, and simulate your design.

Fortunately, we can do better. It turns out Quartus defines a macro called ALTERA_RESERVED_QIS which is defined in Quartus but not in Questa. Therefore I suggest that when -fclash-hdlsyn Quartus is used, we generate the following instead:

  `ifndef ALTERA_RESERVED_QIS
  `uselib lib=altera_mf
  `endif

The branch quartus-uselib allows to experiment with this issue. It fixes bugs in the DDR primitives (which will be part of a PR soon) and adds this proposed functionality with -fclash-hdlsyn Quartus. The following file is a reproducer with a test bench that works correctly in Questa:

Reproducer

{-# OPTIONS_GHC -Wno-orphans #-}

module IntelVerilogDDR where

import Clash.Explicit.Prelude
import Clash.Explicit.Testbench
import Clash.Intel.DDR

createDomain vSystem{vName="DDR", vPeriod=5000}

topEntity ::
  Clock System ->
  Signal DDR (BitVector 8) ->
  Signal System (BitVector 8, BitVector 8)
topEntity clk = altddioIn (SSymbol @"Arria II GX") clk noReset enableGen
{-# OPAQUE topEntity #-}

testBench ::
  Signal System Bool
testBench = done
 where
  inp = register clkDDR noReset enableGen 0 $ inp + 1
  out = topEntity clk inp
  expected = (0,0) :> (0,0) :> (1,2) :> (3,4) :> (5,6) :> (7,8) :> Nil
  done = outputVerifier' clk noReset expected out
  (clk, clkDDR) = biTbClockGen $ not <$> done
{-# OPAQUE testBench #-}