diff --git a/t1/src/OtherUnit.scala b/t1/src/OtherUnit.scala
index dd92d056d..ba85d9980 100644
--- a/t1/src/OtherUnit.scala
+++ b/t1/src/OtherUnit.scala
@@ -133,7 +133,7 @@ class OtherUnit(val parameter: OtherUnitParam) extends VFUModule with Serializab
       selectSource2
     )
   ).asUInt
-  val popCountResult: UInt = popCount.resp + request.popInit(7, 0)
+  val popCountResult: UInt = popCount.resp + request.popInit
   val result:         UInt = Mux1H(
     resultSelect,
     Seq(ffo.resp.bits, popCountResult, indexRes, clipResult, request.src.head, request.src(1))
diff --git a/t1/src/mask/MaskUnit.scala b/t1/src/mask/MaskUnit.scala
index 938ead9ba..70ac5b0f4 100644
--- a/t1/src/mask/MaskUnit.scala
+++ b/t1/src/mask/MaskUnit.scala
@@ -720,7 +720,7 @@ class MaskUnit(val parameter: T1Parameter)
   val readTypeRequestDeq: Bool =
     (anyReadFire && groupReadFinish) || (readIssueStageValid && readIssueStageState.needRead === 0.U)
 
-  val compressUnitResultQueue: QueueIO[CompressOutput] = Queue.io(new CompressOutput(compressParam), 2, flow = true)
+  val compressUnitResultQueue: QueueIO[CompressOutput] = Queue.io(new CompressOutput(compressParam), 4, flow = true)
 
   val noSourceValid:        Bool = noSource && counterValid &&
     (instReg.vl.orR || (mvRd && !readVS1Reg.sendToExecution))