Performance of rocket-chip

[cassebas]

Hi rocket-chip guys,
First off thank you for this project:-)

I have a question about a performance evaluation I'm doing using rocket-chip. I'm running a 32-bit single-threaded core on an FPGA, specifically on a Genesys2 dev board. I'm using the vivado-risc-v enviroment as build enviroment for generating the bitstream that goes into the FPGA. I have asked the author of this platform this same question, but I do not yet have a good explanation.

I'm running benchmarks from the TacleBench benchmark suite. An example is the dijkstra algorithm. I've extended the program with a performance counter that counts the number of cycles spent.

I would expect the number of cycles to vary somewhat, because of the DDR3 RAM among perhaps other things. But the strange thing is, that sometimes after a reset of the CPU, the performance is way off and it stays way off until I push the reset button again.

I run the benchmark many times, say 100 times and then reset the CPU, and continue. I get two different distributions of performance (in terms of execution cycles), where one is way slower than the other one. This is shown in the following bar plot:

So what I do is:

• [push reset button] run dijkstra 100 times
• [push reset button] run dijkstra 100 times
• [push reset button] run dijkstra 100 times
• etc

Sometimes a reset causes the CPU to be slower.

Do you have any idea what might be causing this behavior? Could it be something in de rocket-chip design that could create such different behavior?

Thank you in advance for any ideas!