Proxy Read and Write from Memory with AXI

[testsgmr]

Hello all,

I am trying to proxy the memory Read and Write requests between rocket chip and memory with a custom IP. My IP has one AXI master interface(memory side)and one AXI slave interface(Rocket side). I assumed that size of the read and write requests is the same as a cache line, i.e., when core wants to read something from memory, it will read a cache line(64Byte), and when core wants to write something to memory, it will write a cache line(64Byte). But, when I used ILA to check the traces, I saw that core did not write to memory using AXI burst and write each block in one transaction. Are my assumptions wrong?

Thank you in advance

[jerryz123]

Not sure how you integrated your AXI device. I believe the existing AXI interface to simulated external memory performs burst reads and writes.