diff --git a/core/src/main/scala/chisel3/Annotation.scala b/core/src/main/scala/chisel3/Annotation.scala
index c8ac462d2e9..545ea480598 100644
--- a/core/src/main/scala/chisel3/Annotation.scala
+++ b/core/src/main/scala/chisel3/Annotation.scala
@@ -4,7 +4,7 @@ package chisel3.experimental
 
 import scala.language.existentials
 import chisel3.internal.{Builder, InstanceId, LegacyModule}
-import chisel3.{CompileOptions, Data}
+import chisel3.{CompileOptions, Data, RawModule}
 import firrtl.Transform
 import firrtl.annotations._
 import firrtl.options.Unserializable
@@ -78,7 +78,7 @@ object doNotDedup {
     * @param module The module to be marked
     * @return Unmodified signal `module`
     */
-   def apply[T <: LegacyModule](module: T)(implicit compileOptions: CompileOptions): Unit = {
+   def apply[T <: RawModule](module: T)(implicit compileOptions: CompileOptions): Unit = {
     annotate(new ChiselAnnotation { def toFirrtl = NoDedupAnnotation(module.toNamed) })
   }
 }
diff --git a/core/src/main/scala/chisel3/Module.scala b/core/src/main/scala/chisel3/Module.scala
index 236f528ecd8..27b38d0c825 100644
--- a/core/src/main/scala/chisel3/Module.scala
+++ b/core/src/main/scala/chisel3/Module.scala
@@ -6,15 +6,14 @@ import scala.collection.immutable.ListMap
 import scala.collection.mutable.{ArrayBuffer, HashMap}
 import scala.collection.JavaConversions._
 import scala.language.experimental.macros
-
 import java.util.IdentityHashMap
 
 import chisel3.internal._
 import chisel3.internal.Builder._
 import chisel3.internal.firrtl._
-import chisel3.internal.sourceinfo.{InstTransform, SourceInfo}
+import chisel3.internal.sourceinfo.{InstTransform, SourceInfo, UnlocatableSourceInfo}
 import chisel3.experimental.BaseModule
-import _root_.firrtl.annotations.{ModuleName, ModuleTarget, IsModule}
+import _root_.firrtl.annotations.{IsModule, ModuleName, ModuleTarget}
 
 object Module extends SourceInfoDoc {
   /** A wrapper method that all Module instantiations must be wrapped in
@@ -87,6 +86,43 @@ object Module extends SourceInfoDoc {
   def currentModule: Option[BaseModule] = Builder.currentModule
 }
 
+/** Abstract base class for Modules, which behave much like Verilog modules.
+  * These may contain both logic and state which are written in the Module
+  * body (constructor).
+  * This abstract base class includes an implicit clock and reset.
+  *
+  * @note Module instantiations must be wrapped in a Module() call.
+  */
+abstract class Module(implicit moduleCompileOptions: CompileOptions) extends RawModule {
+  // Implicit clock and reset pins
+  final val clock: Clock = IO(Input(Clock())).suggestName("clock")
+  final val reset: Reset = IO(Input(mkReset)).suggestName("reset")
+
+  // These are to be phased out
+  protected var override_clock: Option[Clock] = None
+  protected var override_reset: Option[Bool] = None
+
+  private[chisel3] def mkReset: Reset = {
+    // Top module and compatibility mode use Bool for reset
+    val inferReset = _parent.isDefined && moduleCompileOptions.inferModuleReset
+    if (inferReset) Reset() else Bool()
+  }
+
+  // Setup ClockAndReset
+  Builder.currentClock = Some(clock)
+  Builder.currentReset = Some(reset)
+  Builder.clearPrefix()
+
+  private[chisel3] override def initializeInParent(parentCompileOptions: CompileOptions): Unit = {
+    implicit val sourceInfo = UnlocatableSourceInfo
+
+    super.initializeInParent(parentCompileOptions)
+    clock := override_clock.getOrElse(Builder.forcedClock)
+    reset := override_reset.getOrElse(Builder.forcedReset)
+  }
+}
+
+
 package experimental {
 
   object IO {
@@ -145,7 +181,7 @@ package internal {
       if (!compileOptions.explicitInvalidate) {
         pushCommand(DefInvalid(sourceInfo, clonePorts.ref))
       }
-      if (proto.isInstanceOf[MultiIOModule]) {
+      if (proto.isInstanceOf[Module]) {
         clonePorts("clock") := Module.clock
         clonePorts("reset") := Module.reset
       }
diff --git a/core/src/main/scala/chisel3/RawModule.scala b/core/src/main/scala/chisel3/RawModule.scala
index 9f0a24d64fc..bb84c444088 100644
--- a/core/src/main/scala/chisel3/RawModule.scala
+++ b/core/src/main/scala/chisel3/RawModule.scala
@@ -142,47 +142,14 @@ abstract class RawModule(implicit moduleCompileOptions: CompileOptions)
   }
 }
 
-trait RequireAsyncReset extends MultiIOModule {
+trait RequireAsyncReset extends Module {
   override private[chisel3] def mkReset: AsyncReset = AsyncReset()
 }
 
-trait RequireSyncReset extends MultiIOModule {
+trait RequireSyncReset extends Module {
   override private[chisel3] def mkReset: Bool = Bool()
 }
 
-/** Abstract base class for Modules, which behave much like Verilog modules.
-  * These may contain both logic and state which are written in the Module
-  * body (constructor).
-  * This abstract base class includes an implicit clock and reset.
-  *
-  * @note Module instantiations must be wrapped in a Module() call.
-  */
-abstract class MultiIOModule(implicit moduleCompileOptions: CompileOptions)
-    extends RawModule {
-  // Implicit clock and reset pins
-  final val clock: Clock = IO(Input(Clock())).autoSeed("clock")
-  final val reset: Reset = IO(Input(mkReset)).autoSeed("reset")
-
-  private[chisel3] def mkReset: Reset = {
-    // Top module and compatibility mode use Bool for reset
-    val inferReset = _parent.isDefined && moduleCompileOptions.inferModuleReset
-    if (inferReset) Reset() else Bool()
-  }
-
-  // Setup ClockAndReset
-  Builder.currentClock = Some(clock)
-  Builder.currentReset = Some(reset)
-  Builder.clearPrefix()
-
-  private[chisel3] override def initializeInParent(parentCompileOptions: CompileOptions): Unit = {
-    implicit val sourceInfo = UnlocatableSourceInfo
-
-    super.initializeInParent(parentCompileOptions)
-    clock := Builder.forcedClock
-    reset := Builder.forcedReset
-  }
-}
-
 package internal {
 
   /** Legacy Module class that restricts IOs to just io, clock, and reset, and provides a constructor
@@ -192,12 +159,7 @@ package internal {
     * IO), the clock and reset constructors will be phased out. Recommendation is to wrap the module
     * in a withClock/withReset/withClockAndReset block, or directly hook up clock or reset IO pins.
     */
-  abstract class LegacyModule(implicit moduleCompileOptions: CompileOptions)
-    extends MultiIOModule {
-    // These are to be phased out
-    protected var override_clock: Option[Clock] = None
-    protected var override_reset: Option[Bool] = None
-
+  abstract class LegacyModule(implicit moduleCompileOptions: CompileOptions) extends Module {
     // IO for this Module. At the Scala level (pre-FIRRTL transformations),
     // connections in and out of a Module may only go through `io` elements.
     @deprecated("Removed for causing issues in Scala 2.12+. You remain free to define io Bundles " +
@@ -233,18 +195,5 @@ package internal {
 
       super.generateComponent()
     }
-
-    private[chisel3] override def initializeInParent(parentCompileOptions: CompileOptions): Unit = {
-      // Don't generate source info referencing parents inside a module, since this interferes with
-      // module de-duplication in FIRRTL emission.
-      implicit val sourceInfo = UnlocatableSourceInfo
-
-      if (!parentCompileOptions.explicitInvalidate) {
-        pushCommand(DefInvalid(sourceInfo, _io.ref))
-      }
-
-      clock := override_clock.getOrElse(Builder.forcedClock)
-      reset := override_reset.getOrElse(Builder.forcedReset)
-    }
   }
 }
diff --git a/core/src/main/scala/chisel3/core/package.scala b/core/src/main/scala/chisel3/core/package.scala
index 1da4ba97749..fa29f2443df 100644
--- a/core/src/main/scala/chisel3/core/package.scala
+++ b/core/src/main/scala/chisel3/core/package.scala
@@ -66,13 +66,13 @@ package object core {
   type RawModule = chisel3.RawModule
   @deprecated("Avoid importing from chisel3.core, these are not public APIs and may change at any time. " +
     "Use chisel3.MultiIOModule instead. This alias will be removed in 3.4.", "since the beginning of time")
-  type MultiIOModule = chisel3.MultiIOModule
+  type MultiIOModule = chisel3.Module
   @deprecated("Avoid importing from chisel3.core, these are not public APIs and may change at any time. " +
     " Use chisel3.RawModule instead. This alias will be removed in 3.4.", "since the beginning of time")
   type UserModule = chisel3.RawModule
   @deprecated("Avoid importing from chisel3.core, these are not public APIs and may change at any time. " +
     "Use chisel3.MultiIOModule instead. This alias will be removed in 3.4.", "since the beginning of time")
-  type ImplicitModule = chisel3.MultiIOModule
+  type ImplicitModule = chisel3.Module
 
   @deprecated("Use the version in chisel3._", "3.2")
   val Bits = chisel3.Bits
diff --git a/core/src/main/scala/chisel3/package.scala b/core/src/main/scala/chisel3/package.scala
index fb83c9d9ab5..d5a4bfae5ef 100644
--- a/core/src/main/scala/chisel3/package.scala
+++ b/core/src/main/scala/chisel3/package.scala
@@ -167,7 +167,8 @@ package object chisel3 {
 
   type InstanceId = internal.InstanceId
 
-  type Module = chisel3.internal.LegacyModule
+  @deprecated("MultiIOModule is now just Module", "Chisel 3.5")
+  type MultiIOModule = chisel3.Module
 
   /** Implicit for custom Printable string interpolator */
   implicit class PrintableHelper(val sc: StringContext) extends AnyVal {
diff --git a/src/main/scala/chisel3/aop/injecting/InjectingAspect.scala b/src/main/scala/chisel3/aop/injecting/InjectingAspect.scala
index f9aaceb1841..39590b9365e 100644
--- a/src/main/scala/chisel3/aop/injecting/InjectingAspect.scala
+++ b/src/main/scala/chisel3/aop/injecting/InjectingAspect.scala
@@ -2,7 +2,7 @@
 
 package chisel3.aop.injecting
 
-import chisel3.{Module, ModuleAspect, MultiIOModule, RawModule, experimental, withClockAndReset}
+import chisel3.{Module, ModuleAspect, RawModule, withClockAndReset}
 import chisel3.aop._
 import chisel3.internal.{Builder, DynamicContext}
 import chisel3.internal.firrtl.DefModule
@@ -63,7 +63,7 @@ abstract class InjectorAspect[T <: RawModule, M <: RawModule](
     RunFirrtlTransformAnnotation(new InjectingTransform) +: modules.map { module =>
       val (chiselIR, _) = Builder.build(Module(new ModuleAspect(module) {
         module match {
-          case x: MultiIOModule => withClockAndReset(x.clock, x.reset) { injection(module) }
+          case x: Module => withClockAndReset(x.clock, x.reset) { injection(module) }
           case x: RawModule => injection(module)
         }
       }), dynamicContext)
diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala
index c6459455ca1..032d731dcdd 100644
--- a/src/main/scala/chisel3/util/Decoupled.scala
+++ b/src/main/scala/chisel3/util/Decoupled.scala
@@ -21,7 +21,7 @@ abstract class ReadyValidIO[+T <: Data](gen: T) extends Bundle
 {
   // Compatibility hack for rocket-chip
   private val genType = (DataMirror.internal.isSynthesizable(gen), chisel3.internal.Builder.currentModule) match {
-    case (true, Some(module: MultiIOModule))
+    case (true, Some(module: Module))
         if !module.compileOptions.declaredTypeMustBeUnbound => chiselTypeOf(gen)
     case _ => gen
   }
diff --git a/src/test/scala/chiselTests/AnalogIntegrationSpec.scala b/src/test/scala/chiselTests/AnalogIntegrationSpec.scala
index 258b22f98f8..3af54d1dc36 100644
--- a/src/test/scala/chiselTests/AnalogIntegrationSpec.scala
+++ b/src/test/scala/chiselTests/AnalogIntegrationSpec.scala
@@ -31,15 +31,19 @@ class AnalogBlackBox(index: Int) extends BlackBox(Map("index" -> index)) {
   val io = IO(new AnalogBlackBoxIO(1))
 }
 
+trait AnalogBlackBoxModuleIntf extends Module {
+  def io: AnalogBlackBoxIO
+}
+
 // AnalogBlackBox wrapper, which extends Module to present the common io._ interface
-class AnalogBlackBoxModule(index: Int) extends Module {
+class AnalogBlackBoxModule(index: Int) extends AnalogBlackBoxModuleIntf {
   val io = IO(new AnalogBlackBoxIO(1))
   val impl = Module(new AnalogBlackBox(index))
   io <> impl.io
 }
 
 // Wraps up n blackboxes, connecing their buses and simply forwarding their ports up
-class AnalogBlackBoxWrapper(n: Int, idxs: Seq[Int]) extends Module {
+class AnalogBlackBoxWrapper(n: Int, idxs: Seq[Int]) extends AnalogBlackBoxModuleIntf {
   require(n > 0)
   val io = IO(new AnalogBlackBoxIO(n))
   val bbs = idxs.map(i => Module(new AnalogBlackBoxModule(i)))
diff --git a/src/test/scala/chiselTests/AutoClonetypeSpec.scala b/src/test/scala/chiselTests/AutoClonetypeSpec.scala
index 6c5fd2617d3..b791297d0fd 100644
--- a/src/test/scala/chiselTests/AutoClonetypeSpec.scala
+++ b/src/test/scala/chiselTests/AutoClonetypeSpec.scala
@@ -198,7 +198,7 @@ class AutoClonetypeSpec extends ChiselFlatSpec with Utils {
   }
 
   "Wrapped IO construction without parent reference" should "not fail for autoclonetype" in {
-    class TestModule extends MultiIOModule {
+    class TestModule extends Module {
       def thunk[T](f: => T): T = f
       val works = thunk(IO(new Bundle {
         val x = Output(UInt(3.W))
@@ -208,7 +208,7 @@ class AutoClonetypeSpec extends ChiselFlatSpec with Utils {
   }
 
   "Wrapped IO construction with parent references" should "not fail for autoclonetype" in {
-    class TestModule(blah: Int) extends MultiIOModule {
+    class TestModule(blah: Int) extends Module {
       // Note that this currently fails only if f: =>T on Scala 2.11.12
       // This works successfully with 2.12.11
       def thunk[T](f: => T): T = f
diff --git a/src/test/scala/chiselTests/BoringUtilsSpec.scala b/src/test/scala/chiselTests/BoringUtilsSpec.scala
index 0500ac2394c..398595811fb 100644
--- a/src/test/scala/chiselTests/BoringUtilsSpec.scala
+++ b/src/test/scala/chiselTests/BoringUtilsSpec.scala
@@ -71,7 +71,7 @@ class BoringUtilsSpec extends ChiselFlatSpec with ChiselRunners {
     out := x
   }
 
-  class Top(val width: Int) extends MultiIOModule {
+  class Top(val width: Int) extends Module {
     /* From the perspective of deduplication, all sources are identical and all sinks are identical. */
     val sources = Seq.fill(3)(Module(new Source))
     val sinks = Seq.fill(6)(Module(new Sink))
diff --git a/src/test/scala/chiselTests/CloneModuleSpec.scala b/src/test/scala/chiselTests/CloneModuleSpec.scala
index 7f3ef854c66..e54ef1c27e9 100644
--- a/src/test/scala/chiselTests/CloneModuleSpec.scala
+++ b/src/test/scala/chiselTests/CloneModuleSpec.scala
@@ -8,7 +8,7 @@ import chisel3.util.{Queue, EnqIO, DeqIO, QueueIO, log2Ceil}
 import chisel3.experimental.{CloneModuleAsRecord, IO}
 import chisel3.testers.BasicTester
 
-class MultiIOQueue[T <: Data](gen: T, val entries: Int) extends MultiIOModule {
+class MultiIOQueue[T <: Data](gen: T, val entries: Int) extends Module {
   val clk = IO(Input(Clock()))
   val rst = IO(Input(Reset()))
   val enq = IO(Flipped(EnqIO(gen)))
diff --git a/src/test/scala/chiselTests/DataPrint.scala b/src/test/scala/chiselTests/DataPrint.scala
index beb92f0dcf1..b5f96c4d379 100644
--- a/src/test/scala/chiselTests/DataPrint.scala
+++ b/src/test/scala/chiselTests/DataPrint.scala
@@ -34,7 +34,7 @@ class DataPrintSpec extends ChiselFlatSpec with Matchers {
     } }
   }
 
-  class BoundDataModule extends MultiIOModule {  // not in the test to avoid anon naming suffixes
+  class BoundDataModule extends Module {  // not in the test to avoid anon naming suffixes
     Wire(UInt()).toString should be("UInt(Wire in BoundDataModule)")
     Reg(SInt()).toString should be("SInt(Reg in BoundDataModule)")
     val io = IO(Output(Bool()))  // needs a name so elaboration doesn't fail
@@ -44,7 +44,7 @@ class DataPrintSpec extends ChiselFlatSpec with Matchers {
     (2.U + 2.U).toString should be("UInt<2>(OpResult in BoundDataModule)")
     Wire(Vec(3, UInt(2.W))).toString should be ("UInt<2>[3](Wire in BoundDataModule)")
 
-    class InnerModule extends MultiIOModule {
+    class InnerModule extends Module {
       val io = IO(Output(new Bundle {
         val a = UInt(4.W)
       }))
diff --git a/src/test/scala/chiselTests/Direction.scala b/src/test/scala/chiselTests/Direction.scala
index 570abc68b72..39ff1f0ed2a 100644
--- a/src/test/scala/chiselTests/Direction.scala
+++ b/src/test/scala/chiselTests/Direction.scala
@@ -131,7 +131,7 @@ class DirectionSpec extends ChiselPropSpec with Matchers with Utils {
   import chisel3.experimental.{DataMirror, Direction}
 
   property("Directions should be preserved through cloning and binding of Bundles") {
-    ChiselStage.elaborate(new MultiIOModule {
+    ChiselStage.elaborate(new Module {
       class MyBundle extends Bundle {
         val foo = Input(UInt(8.W))
         val bar = Output(UInt(8.W))
@@ -164,11 +164,11 @@ class DirectionSpec extends ChiselPropSpec with Matchers with Utils {
       for ((data, dir) <- actualDirs) {
         DataMirror.directionOf(data) shouldBe (dir)
       }
-    }.asInstanceOf[MultiIOModule]) // The cast works around weird reflection behavior (bug?)
+    }.asInstanceOf[Module]) // The cast works around weird reflection behavior (bug?)
   }
 
   property("Directions should be preserved through cloning and binding of Vecs") {
-    ChiselStage.elaborate(new MultiIOModule {
+    ChiselStage.elaborate(new Module {
       val a = Vec(1, Input(UInt(8.W)))
       val b = Vec(1, a)
       val c = Vec(1, Flipped(a))
@@ -197,7 +197,7 @@ class DirectionSpec extends ChiselPropSpec with Matchers with Utils {
       for ((data, dir) <- actualDirs) {
         DataMirror.directionOf(data) shouldBe (dir)
       }
-    }.asInstanceOf[MultiIOModule]) // The cast works around weird reflection behavior (bug?)
+    }.asInstanceOf[Module]) // The cast works around weird reflection behavior (bug?)
   }
 
   property("Using Vec and Flipped together should calculate directions properly") {
diff --git a/src/test/scala/chiselTests/DriverSpec.scala b/src/test/scala/chiselTests/DriverSpec.scala
index e78185a1d7d..3a78683bd7f 100644
--- a/src/test/scala/chiselTests/DriverSpec.scala
+++ b/src/test/scala/chiselTests/DriverSpec.scala
@@ -19,7 +19,7 @@ class DummyModule extends Module {
   io.out := io.in
 }
 
-class TypeErrorModule extends chisel3.MultiIOModule {
+class TypeErrorModule extends chisel3.Module {
   val in = IO(Input(UInt(1.W)))
   val out = IO(Output(SInt(1.W)))
   out := in
diff --git a/src/test/scala/chiselTests/Module.scala b/src/test/scala/chiselTests/Module.scala
index 03239785fdb..932c94a59da 100644
--- a/src/test/scala/chiselTests/Module.scala
+++ b/src/test/scala/chiselTests/Module.scala
@@ -143,7 +143,7 @@ class ModuleSpec extends ChiselPropSpec with Utils {
   property("DataMirror.modulePorts should work") {
     ChiselStage.elaborate(new Module {
       val io = IO(new Bundle { })
-      val m = Module(new chisel3.MultiIOModule {
+      val m = Module(new chisel3.Module {
         val a = IO(UInt(8.W))
         val b = IO(Bool())
       })
diff --git a/src/test/scala/chiselTests/MultiIOModule.scala b/src/test/scala/chiselTests/MultiIOModule.scala
index d9eda807202..9abf324b0b8 100644
--- a/src/test/scala/chiselTests/MultiIOModule.scala
+++ b/src/test/scala/chiselTests/MultiIOModule.scala
@@ -5,7 +5,7 @@ package chiselTests
 import chisel3._
 import chisel3.testers.BasicTester
 
-class MultiIOPlusOne extends MultiIOModule {
+class MultiIOPlusOne extends Module {
   val in  = IO(Input(UInt(32.W)))
   val out = IO(Output(UInt(32.W)))
 
@@ -20,20 +20,20 @@ class MultiIOTester extends BasicTester {
 }
 
 // Demonstrate multiple IOs with inheritance where the IO is assigned to internally
-trait LiteralOutputTrait extends MultiIOModule {
+trait LiteralOutputTrait extends Module {
   val myLiteralIO = IO(Output(UInt(32.W)))
   myLiteralIO := 2.U
 }
 
 // Demonstrate multiple IOs with inheritance where the IO is not assigned
 // (and must be assigned by what extends this trait).
-trait MultiIOTrait extends MultiIOModule {
+trait MultiIOTrait extends Module {
   val myTraitIO = IO(Output(UInt(32.W)))
 }
 
 // Composition of the two above traits, example of IO composition directly using multiple top-level
 // IOs rather than indirectly by constraining the type of the single .io field.
-class ComposedMultiIOModule extends MultiIOModule
+class ComposedMultiIOModule extends Module
     with LiteralOutputTrait with MultiIOTrait {
   val topModuleIO = IO(Input(UInt(32.W)))
   myTraitIO := topModuleIO
diff --git a/src/test/scala/chiselTests/NamingAnnotationTest.scala b/src/test/scala/chiselTests/NamingAnnotationTest.scala
index 43ec837da22..2226a48a71b 100644
--- a/src/test/scala/chiselTests/NamingAnnotationTest.scala
+++ b/src/test/scala/chiselTests/NamingAnnotationTest.scala
@@ -9,7 +9,7 @@ import chisel3.stage.ChiselStage
 
 import scala.collection.mutable.ListBuffer
 
-trait NamedModuleTester extends MultiIOModule {
+trait NamedModuleTester extends Module {
   val expectedNameMap = ListBuffer[(InstanceId, String)]()
   val expectedModuleNameMap = ListBuffer[(Module, String)]()
 
diff --git a/src/test/scala/chiselTests/QueueSpec.scala b/src/test/scala/chiselTests/QueueSpec.scala
index ad14ea15ca3..9dc7f1207f0 100644
--- a/src/test/scala/chiselTests/QueueSpec.scala
+++ b/src/test/scala/chiselTests/QueueSpec.scala
@@ -272,7 +272,7 @@ class QueueSpec extends ChiselPropSpec {
   }
 
   property("Queue.irrevocable should elaborate") {
-    class IrrevocableQueue extends MultiIOModule {
+    class IrrevocableQueue extends Module {
       val in = Wire(Decoupled(Bool()))
       val iQueue = Queue.irrevocable(in, 1)
     }
diff --git a/src/test/scala/chiselTests/ResetSpec.scala b/src/test/scala/chiselTests/ResetSpec.scala
index 77c90814eb4..0e535964fe2 100644
--- a/src/test/scala/chiselTests/ResetSpec.scala
+++ b/src/test/scala/chiselTests/ResetSpec.scala
@@ -73,14 +73,14 @@ class ResetSpec extends ChiselFlatSpec with Utils {
   behavior of "Users"
 
   they should "be able to force implicit reset to be synchronous" in {
-    val fir = ChiselStage.emitChirrtl(new MultiIOModule with RequireSyncReset {
+    val fir = ChiselStage.emitChirrtl(new Module with RequireSyncReset {
       reset shouldBe a [Bool]
     })
     fir should include ("input reset : UInt<1>")
   }
 
   they should "be able to force implicit reset to be asynchronous" in {
-    val fir = ChiselStage.emitChirrtl(new MultiIOModule with RequireAsyncReset {
+    val fir = ChiselStage.emitChirrtl(new Module with RequireAsyncReset {
       reset shouldBe an [AsyncReset]
     })
     fir should include ("input reset : AsyncReset")
@@ -88,8 +88,8 @@ class ResetSpec extends ChiselFlatSpec with Utils {
 
   "Chisel" should "error if sync and async modules are nested" in {
     a [ChiselException] should be thrownBy extractCause[ChiselException] {
-      ChiselStage.elaborate(new MultiIOModule with RequireAsyncReset {
-        val mod = Module(new MultiIOModule with RequireSyncReset)
+      ChiselStage.elaborate(new Module with RequireAsyncReset {
+        val mod = Module(new Module with RequireSyncReset)
       })
     }
   }
diff --git a/src/test/scala/chiselTests/StrongEnum.scala b/src/test/scala/chiselTests/StrongEnum.scala
index d742903c7a9..bf0eb2fe452 100644
--- a/src/test/scala/chiselTests/StrongEnum.scala
+++ b/src/test/scala/chiselTests/StrongEnum.scala
@@ -77,7 +77,7 @@ class CastFromNonLit extends Module {
 class CastFromNonLitWidth(w: Option[Int] = None) extends Module {
   val width = if (w.isDefined) w.get.W else UnknownWidth()
 
-  override val io = IO(new Bundle {
+  val io = IO(new Bundle {
     val in = Input(UInt(width))
     val out = Output(EnumExample())
   })
diff --git a/src/test/scala/chiselTests/Util.scala b/src/test/scala/chiselTests/Util.scala
index d5929dcbb49..e8354b8d34b 100644
--- a/src/test/scala/chiselTests/Util.scala
+++ b/src/test/scala/chiselTests/Util.scala
@@ -20,7 +20,7 @@ trait AbstractPassthroughModule extends RawModule {
 }
 
 class PassthroughModule extends Module with AbstractPassthroughModule
-class PassthroughMultiIOModule extends MultiIOModule with AbstractPassthroughModule
+class PassthroughMultiIOModule extends Module with AbstractPassthroughModule
 class PassthroughRawModule extends RawModule with AbstractPassthroughModule
 
 case class ScalaIntervalSimulator(intervalRange: IntervalRange) {
diff --git a/src/test/scala/chiselTests/experimental/ForceNames.scala b/src/test/scala/chiselTests/experimental/ForceNames.scala
index d4ad4d677af..b3534f1155d 100644
--- a/src/test/scala/chiselTests/experimental/ForceNames.scala
+++ b/src/test/scala/chiselTests/experimental/ForceNames.scala
@@ -14,7 +14,7 @@ import logger.{LogLevel, LogLevelAnnotation}
 
 /** Object containing Modules used for testing */
 object ForceNamesHierarchy {
-  class WrapperExample extends MultiIOModule {
+  class WrapperExample extends Module {
     val in = IO(Input(UInt(3.W)))
     val out = IO(Output(UInt(3.W)))
     val inst = Module(new Wrapper)
@@ -22,7 +22,7 @@ object ForceNamesHierarchy {
     out := inst.out
     forceName(out, "outt")
   }
-  class Wrapper extends MultiIOModule with InlineInstance {
+  class Wrapper extends Module with InlineInstance {
     val in = IO(Input(UInt(3.W)))
     val out = IO(Output(UInt(3.W)))
     val inst = Module(new MyLeaf)
@@ -30,12 +30,12 @@ object ForceNamesHierarchy {
     inst.in := in
     out := inst.out
   }
-  class MyLeaf extends MultiIOModule {
+  class MyLeaf extends Module {
     val in = IO(Input(UInt(3.W)))
     val out = IO(Output(UInt(3.W)))
     out := in
   }
-  class RenamePortsExample extends MultiIOModule {
+  class RenamePortsExample extends Module {
     val in = IO(Input(UInt(3.W)))
     val out = IO(Output(UInt(3.W)))
     val inst = Module(new MyLeaf)
@@ -43,13 +43,13 @@ object ForceNamesHierarchy {
     out := inst.out
     forceName(inst.in, "inn")
   }
-  class ConflictingName extends MultiIOModule {
+  class ConflictingName extends Module {
     val in = IO(Input(UInt(3.W)))
     val out = IO(Output(UInt(3.W)))
     out := in
     forceName(out, "in")
   }
-  class BundleName extends MultiIOModule {
+  class BundleName extends Module {
     val in = IO(new Bundle {
       val a = Input(UInt(3.W))
       val b = Input(UInt(3.W))
diff --git a/src/test/scala/chiselTests/experimental/ProgrammaticPortsSpec.scala b/src/test/scala/chiselTests/experimental/ProgrammaticPortsSpec.scala
index ffbdb81483f..ffe3a37f6ae 100644
--- a/src/test/scala/chiselTests/experimental/ProgrammaticPortsSpec.scala
+++ b/src/test/scala/chiselTests/experimental/ProgrammaticPortsSpec.scala
@@ -52,12 +52,11 @@ class ProgrammaticPortsSpec extends ChiselFlatSpec with Utils {
     doTest(new PortsWinTester)
   }
 
-  "LegacyModule" should "ignore suggestName on ports" in {
+  "Module" should "ignore suggestName on clock and reset" in {
     doTest(new Module with NamedModuleTester {
       val io = IO(new Bundle {
         val foo = Output(UInt(8.W))
       })
-      expectName(io.suggestName("cheese"), "io")
       expectName(clock.suggestName("tart"), "clock")
       expectName(reset.suggestName("teser"), "reset")
     })
@@ -65,7 +64,7 @@ class ProgrammaticPortsSpec extends ChiselFlatSpec with Utils {
 
   "SuggestName collisions on ports" should "be illegal" in {
     a [ChiselException] should be thrownBy extractCause[ChiselException] {
-      ChiselStage.elaborate(new MultiIOModule {
+      ChiselStage.elaborate(new Module {
         val foo = IO(UInt(8.W)).suggestName("apple")
         val bar = IO(UInt(8.W)).suggestName("apple")
       })
diff --git a/src/test/scala/chiselTests/naming/NamePluginSpec.scala b/src/test/scala/chiselTests/naming/NamePluginSpec.scala
index 5e7133d1842..3a539bd4df8 100644
--- a/src/test/scala/chiselTests/naming/NamePluginSpec.scala
+++ b/src/test/scala/chiselTests/naming/NamePluginSpec.scala
@@ -11,7 +11,7 @@ class NamePluginSpec extends ChiselFlatSpec with Utils {
   implicit val minimumScalaVersion: Int = 12
 
   "Scala plugin" should "name internally scoped components" in {
-    class Test extends MultiIOModule {
+    class Test extends Module {
       { val mywire = Wire(UInt(3.W))}
     }
     aspectTest(() => new Test) {
@@ -20,8 +20,8 @@ class NamePluginSpec extends ChiselFlatSpec with Utils {
   }
 
   "Scala plugin" should "name internally scoped instances" in {
-    class Inner extends MultiIOModule { }
-    class Test extends MultiIOModule {
+    class Inner extends Module { }
+    class Test extends Module {
       { val myinstance = Module(new Inner) }
     }
     aspectTest(() => new Test) {
@@ -30,7 +30,7 @@ class NamePluginSpec extends ChiselFlatSpec with Utils {
   }
 
   "Scala plugin" should "interact with prefixing" in {
-    class Test extends MultiIOModule {
+    class Test extends Module {
       def builder() = {
         val wire = Wire(UInt(3.W))
       }
@@ -47,7 +47,7 @@ class NamePluginSpec extends ChiselFlatSpec with Utils {
   }
 
   "Scala plugin" should "interact with prefixing so last val name wins" in {
-    class Test extends MultiIOModule {
+    class Test extends Module {
       def builder() = {
         val wire1 = Wire(UInt(3.W))
         val wire2 = Wire(UInt(3.W))
@@ -71,7 +71,7 @@ class NamePluginSpec extends ChiselFlatSpec with Utils {
 
   "Naming on option" should "work" in {
 
-    class Test extends MultiIOModule {
+    class Test extends Module {
       def builder(): Option[UInt] = {
         val a = Wire(UInt(3.W))
         Some(a)
@@ -88,7 +88,7 @@ class NamePluginSpec extends ChiselFlatSpec with Utils {
 
   "Naming on iterables" should "work" in {
 
-    class Test extends MultiIOModule {
+    class Test extends Module {
       def builder(): Seq[UInt] = {
         val a = Wire(UInt(3.W))
         val b = Wire(UInt(3.W))
@@ -108,7 +108,7 @@ class NamePluginSpec extends ChiselFlatSpec with Utils {
 
   "Naming on nested iterables" should "work" in {
 
-    class Test extends MultiIOModule {
+    class Test extends Module {
       def builder(): Seq[Seq[UInt]] = {
         val a = Wire(UInt(3.W))
         val b = Wire(UInt(3.W))
@@ -137,7 +137,7 @@ class NamePluginSpec extends ChiselFlatSpec with Utils {
   "Naming on custom case classes" should "not work" in {
     case class Container(a: UInt, b: UInt)
 
-    class Test extends MultiIOModule {
+    class Test extends Module {
       def builder(): Container = {
         val a = Wire(UInt(3.W))
         val b = Wire(UInt(3.W))
@@ -167,7 +167,7 @@ class NamePluginSpec extends ChiselFlatSpec with Utils {
   }
 
   "Multiple names on a non-IO" should "get the first name" in {
-    class Test extends MultiIOModule {
+    class Test extends Module {
       {
         val a = Wire(UInt(3.W))
         val b = a
@@ -234,7 +234,7 @@ class NamePluginSpec extends ChiselFlatSpec with Utils {
 
 
   "autoSeed" should "override automatic naming for non-IO" in {
-    class Test extends MultiIOModule {
+    class Test extends Module {
       {
         val a = Wire(UInt(3.W))
         a.autoSeed("b")
@@ -248,7 +248,7 @@ class NamePluginSpec extends ChiselFlatSpec with Utils {
   }
 
   "Unapply assignments" should "still be named" in {
-    class Test extends MultiIOModule {
+    class Test extends Module {
       {
         val (a, b) = (Wire(UInt(3.W)), Wire(UInt(3.W)))
       }
@@ -261,7 +261,7 @@ class NamePluginSpec extends ChiselFlatSpec with Utils {
   }
 
   "Unapply assignments" should "not override already named things" in {
-    class Test extends MultiIOModule {
+    class Test extends Module {
       {
         val x = Wire(UInt(3.W))
         val (a, b) = (x, Wire(UInt(3.W)))
@@ -276,7 +276,7 @@ class NamePluginSpec extends ChiselFlatSpec with Utils {
 
   "Case class unapply assignments" should "be named" in {
     case class Foo(x: UInt, y: UInt)
-    class Test extends MultiIOModule {
+    class Test extends Module {
       {
         def func() = Foo(Wire(UInt(3.W)), Wire(UInt(3.W)))
         val Foo(a, b) = func()
@@ -291,7 +291,7 @@ class NamePluginSpec extends ChiselFlatSpec with Utils {
 
   "Complex unapply assignments" should "be named" in {
     case class Foo(x: UInt, y: UInt)
-    class Test extends MultiIOModule {
+    class Test extends Module {
       {
         val w = Wire(UInt(3.W))
         def func() = {
@@ -320,7 +320,7 @@ class NamePluginSpec extends ChiselFlatSpec with Utils {
   }
 
   "Nested val declarations" should "all be named" in {
-    class Test extends MultiIOModule {
+    class Test extends Module {
       {
         val a = {
           val b = {
diff --git a/src/test/scala/chiselTests/naming/PrefixSpec.scala b/src/test/scala/chiselTests/naming/PrefixSpec.scala
index 83408dea52e..0712692dc17 100644
--- a/src/test/scala/chiselTests/naming/PrefixSpec.scala
+++ b/src/test/scala/chiselTests/naming/PrefixSpec.scala
@@ -10,7 +10,7 @@ import chiselTests.{ChiselPropSpec, Utils}
 class PrefixSpec extends ChiselPropSpec with Utils {
   implicit val minimumMajorVersion: Int = 12
   property("Scala plugin should interact with prefixing so last plugin name wins?") {
-    class Test extends MultiIOModule {
+    class Test extends Module {
       def builder(): UInt = {
         val wire1 = Wire(UInt(3.W))
         val wire2 = Wire(UInt(3.W))
@@ -34,7 +34,7 @@ class PrefixSpec extends ChiselPropSpec with Utils {
   }
 
   property("Nested prefixes should work") {
-    class Test extends MultiIOModule {
+    class Test extends Module {
       def builder2(): UInt = {
         val wire1 = Wire(UInt(3.W))
         val wire2 = Wire(UInt(3.W))
@@ -68,7 +68,7 @@ class PrefixSpec extends ChiselPropSpec with Utils {
   }
 
   property("Prefixing seeded with signal") {
-    class Test extends MultiIOModule {
+    class Test extends Module {
       def builder(): UInt = {
         val wire = Wire(UInt(3.W))
         wire := 3.U
@@ -93,7 +93,7 @@ class PrefixSpec extends ChiselPropSpec with Utils {
 
   property("Automatic prefixing should work") {
 
-    class Test extends MultiIOModule {
+    class Test extends Module {
       def builder(): UInt = {
         val a = Wire(UInt(3.W))
         val b = Wire(UInt(3.W))
@@ -113,7 +113,7 @@ class PrefixSpec extends ChiselPropSpec with Utils {
 
   property("No prefixing annotation on defs should work") {
 
-    class Test extends MultiIOModule {
+    class Test extends Module {
       def builder(): UInt = noPrefix {
         val a = Wire(UInt(3.W))
         val b = Wire(UInt(3.W))
@@ -130,7 +130,7 @@ class PrefixSpec extends ChiselPropSpec with Utils {
 
   property("Prefixing on temps should work") {
 
-    class Test extends MultiIOModule {
+    class Test extends Module {
       def builder(): UInt = {
         val a = Wire(UInt(3.W))
         val b = Wire(UInt(3.W))
@@ -149,13 +149,13 @@ class PrefixSpec extends ChiselPropSpec with Utils {
   }
 
   property("Prefixing should not leak into child modules") {
-    class Child extends MultiIOModule {
+    class Child extends Module {
       {
         val wire = Wire(UInt())
       }
     }
 
-    class Test extends MultiIOModule {
+    class Test extends Module {
       {
         val child = prefix("InTest") {
           Module(new Child)
@@ -169,13 +169,13 @@ class PrefixSpec extends ChiselPropSpec with Utils {
   }
 
   property("Prefixing should not leak into child modules, example 2") {
-    class Child extends MultiIOModule {
+    class Child extends Module {
       {
         val wire = Wire(UInt())
       }
     }
 
-    class Test extends MultiIOModule {
+    class Test extends Module {
       val x = IO(Input(UInt(3.W)))
       val y = {
         lazy val module = new Child
@@ -189,13 +189,13 @@ class PrefixSpec extends ChiselPropSpec with Utils {
   }
 
   property("Instance names should not be added to prefix") {
-    class Child(tpe: UInt) extends MultiIOModule {
+    class Child(tpe: UInt) extends Module {
       {
         val io = IO(Input(tpe))
       }
     }
 
-    class Test extends MultiIOModule {
+    class Test extends Module {
       {
         lazy val module = {
           val x = UInt(3.W)
@@ -212,7 +212,7 @@ class PrefixSpec extends ChiselPropSpec with Utils {
 
 
   property("Prefixing should not be caused by nested Iterable[Iterable[Any]]") {
-    class Test extends MultiIOModule {
+    class Test extends Module {
       {
         val iia = {
           val wire = Wire(UInt(3.W))
@@ -227,7 +227,7 @@ class PrefixSpec extends ChiselPropSpec with Utils {
   }
 
   property("Prefixing should be caused by nested Iterable[Iterable[Data]]") {
-    class Test extends MultiIOModule {
+    class Test extends Module {
       {
         val iia = {
           val wire = Wire(UInt(3.W))
@@ -242,7 +242,7 @@ class PrefixSpec extends ChiselPropSpec with Utils {
   }
 
   property("Prefixing should be the prefix during the last call to autoName/suggestName") {
-    class Test extends MultiIOModule {
+    class Test extends Module {
       {
         val wire = {
           val x = Wire(UInt(3.W)).suggestName("mywire")
@@ -258,7 +258,7 @@ class PrefixSpec extends ChiselPropSpec with Utils {
   }
 
   property("Prefixing have intuitive behavior") {
-    class Test extends MultiIOModule {
+    class Test extends Module {
       {
         val wire = {
           val x = Wire(UInt(3.W)).suggestName("mywire")
@@ -274,7 +274,7 @@ class PrefixSpec extends ChiselPropSpec with Utils {
   }
 
   property("Prefixing on connection to subfields work") {
-    class Test extends MultiIOModule {
+    class Test extends Module {
       {
         val wire = Wire(new Bundle {
           val x = UInt(3.W)
@@ -301,12 +301,12 @@ class PrefixSpec extends ChiselPropSpec with Utils {
   }
 
   property("Prefixing on connection to IOs should work") {
-    class Child extends MultiIOModule {
+    class Child extends Module {
       val in = IO(Input(UInt(3.W)))
       val out = IO(Output(UInt(3.W)))
       out := RegNext(in)
     }
-    class Test extends MultiIOModule {
+    class Test extends Module {
       {
         val child = Module(new Child)
         child.in := RegNext(3.U)
@@ -324,12 +324,12 @@ class PrefixSpec extends ChiselPropSpec with Utils {
   }
 
   property("Prefixing on bulk connects should work") {
-    class Child extends MultiIOModule {
+    class Child extends Module {
       val in = IO(Input(UInt(3.W)))
       val out = IO(Output(UInt(3.W)))
       out := RegNext(in)
     }
-    class Test extends MultiIOModule {
+    class Test extends Module {
       {
         val child = Module(new Child)
         child.in <> RegNext(3.U)
@@ -347,7 +347,7 @@ class PrefixSpec extends ChiselPropSpec with Utils {
   }
 
   property("Connections should use the non-prefixed name of the connected Data") {
-    class Test extends MultiIOModule {
+    class Test extends Module {
       prefix("foo") {
         val x = Wire(UInt(8.W))
         x := {
@@ -364,7 +364,7 @@ class PrefixSpec extends ChiselPropSpec with Utils {
   }
 
   property("Connections to aggregate fields should use the non-prefixed aggregate name") {
-    class Test extends MultiIOModule {
+    class Test extends Module {
       prefix("foo") {
         val x = Wire(new Bundle { val bar = UInt(8.W) })
         x.bar := {
@@ -382,7 +382,7 @@ class PrefixSpec extends ChiselPropSpec with Utils {
 
 
   property("Prefixing with wires in recursive functions should grow linearly") {
-    class Test extends MultiIOModule {
+    class Test extends Module {
       def func(bools: Seq[Bool]): Bool = {
         if (bools.isEmpty) true.B
         else {
diff --git a/src/test/scala/chiselTests/stage/ChiselMainSpec.scala b/src/test/scala/chiselTests/stage/ChiselMainSpec.scala
index a11b8a44688..0fc42fc6289 100644
--- a/src/test/scala/chiselTests/stage/ChiselMainSpec.scala
+++ b/src/test/scala/chiselTests/stage/ChiselMainSpec.scala
@@ -24,7 +24,7 @@ object ChiselMainSpec {
   }
 
   /** A module that connects two of the same types together */
-  class SameTypesModule extends MultiIOModule {
+  class SameTypesModule extends Module {
     val in = IO(Input(UInt(1.W)))
     val out = IO(Output(UInt(1.W)))
     out := in
diff --git a/src/test/scala/chiselTests/stage/ChiselStageSpec.scala b/src/test/scala/chiselTests/stage/ChiselStageSpec.scala
index fb5698a6e0e..98bbb2eac12 100644
--- a/src/test/scala/chiselTests/stage/ChiselStageSpec.scala
+++ b/src/test/scala/chiselTests/stage/ChiselStageSpec.scala
@@ -15,13 +15,13 @@ import firrtl.options.Dependency
 
 object ChiselStageSpec {
 
-  class Bar extends MultiIOModule {
+  class Bar extends Module {
     val in = IO(Input(UInt(4.W)))
     val out = IO(Output(UInt(4.W)))
     out := ~in
   }
 
-  class Foo extends MultiIOModule {
+  class Foo extends Module {
     val addr = IO(Input(UInt(4.W)))
     val out = IO(Output(Bool()))
     val memory = SyncReadMem(8, Bool())
diff --git a/src/test/scala/chiselTests/util/CatSpec.scala b/src/test/scala/chiselTests/util/CatSpec.scala
index 2e52fe63cb3..5565ca512ba 100644
--- a/src/test/scala/chiselTests/util/CatSpec.scala
+++ b/src/test/scala/chiselTests/util/CatSpec.scala
@@ -10,7 +10,7 @@ import chiselTests.ChiselFlatSpec
 
 object CatSpec {
 
-  class JackIsATypeSystemGod extends MultiIOModule {
+  class JackIsATypeSystemGod extends Module {
     val in  = IO(Input (Vec(0, UInt(8.W))))
     val out = IO(Output(UInt(8.W)))