AArch64: incorrect register access information for cmp instruction

[chironxie]

The capstone reports writing register w11 in instruction cmp w11, #0x3d. But from ARMv8 spec, w11 is just a source register and will not be written.
branch: master and 4.0.2

 0  7f f5 00 71  cmp    w11, #0x3d
        op_count: 2
                operands[0].type: REG = w11
                operands[0].access: WRITE
                operands[1].type: IMM = 0x3d
                operands[1].access: READ
        Update-flags: True
        Registers modified: nzcv w11