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instruction_set.html
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<!DOCTYPE html><head><title>Pickle RISC instruction set</title><style type="text/css">
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</style></head><body><h1>Pickle RISC instruction set</h1><section><h2>Overview</h2><table class="encoding"><colgroup><col><col span="16"></colgroup><thead><tr><th>15</th><th>14</th><th>13</th><th>12</th><th>11</th><th>10</th><th>9</th><th>8</th><th>7</th><th>6</th><th>5</th><th>4</th><th>3</th><th>2</th><th>1</th><th>0</th><th class="title"></th></tr></thead><tbody><tr><td colspan="2"><code>00</code></td><td colspan="2"><code>00</code></td><td colspan="8"><var>immediate</var><br>8b unsigned int</td><td colspan="4"><var>r</var><br>register</td><th class="title"><a href="#instruction-addi">Add immediate to register</a></th></tr><tr><td colspan="2"><code>00</code></td><td colspan="2"><code>01</code></td><td colspan="8"><var>immediate</var><br>8b unsigned int</td><td colspan="4"><var>r</var><br>register</td><th class="title"><a href="#instruction-subi">Subtract immediate from register</a></th></tr><tr><td colspan="2"><code>00</code></td><td colspan="2"><code>10</code></td><td colspan="8"><var>immediate</var><br>8b unsigned int</td><td colspan="4"><var>r</var><br>register</td><th class="title"><a href="#instruction-cmpi">Compare immediate with register</a></th></tr><tr><td colspan="2"><code>00</code></td><td colspan="2"><code>11</code></td><td colspan="8"><var>immediate</var><br>8b unsigned int</td><td colspan="4"><var>rd</var><br>register</td><th class="title"><a href="#instruction-addipc">Add immediate to program counter</a></th></tr><tr><td colspan="3"><code>010</code></td><td colspan="1"><code>0</code></td><td colspan="8"><var>immediate</var><br>8b unsigned int</td><td colspan="4"><var>rd</var><br>register</td><th class="title"><a href="#instruction-ldi">Load immediate</a></th></tr><tr><td colspan="3"><code>010</code></td><td colspan="1"><code>1</code></td><td colspan="8"><var>immediate</var><br>8b unsigned int</td><td colspan="4"><var>rd</var><br>register</td><th class="title"><a href="#instruction-ldui">Load upper immediate</a></th></tr><tr><td colspan="3"><code>011</code></td><td colspan="5"><code>00000</code></td><td colspan="4"><var>rs</var><br>register</td><td colspan="4"><var>rd</var><br>register</td><th class="title"><a href="#instruction-add">Add</a></th></tr><tr><td colspan="3"><code>011</code></td><td colspan="5"><code>00001</code></td><td colspan="4"><var>rs</var><br>register</td><td colspan="4"><var>rd</var><br>register</td><th class="title"><a href="#instruction-addc">Add with carry</a></th></tr><tr><td colspan="3"><code>011</code></td><td colspan="5"><code>00010</code></td><td colspan="4"><var>rs</var><br>register</td><td colspan="4"><var>rd</var><br>register</td><th class="title"><a href="#instruction-sub">Subtract</a></th></tr><tr><td colspan="3"><code>011</code></td><td colspan="5"><code>00011</code></td><td colspan="4"><var>rs</var><br>register</td><td colspan="4"><var>rd</var><br>register</td><th class="title"><a href="#instruction-subc">Subtract with carry</a></th></tr><tr><td colspan="3"><code>011</code></td><td colspan="5"><code>00100</code></td><td colspan="4"><var>rs</var><br>register</td><td colspan="4"><var>rd</var><br>register</td><th class="title"><a href="#instruction-rsub">Reverse subtract</a></th></tr><tr><td colspan="3"><code>011</code></td><td colspan="5"><code>00101</code></td><td colspan="4"><var>rs</var><br>register</td><td colspan="4"><var>rd</var><br>register</td><th class="title"><a href="#instruction-rsubc">Reverse subtract with carry</a></th></tr><tr><td colspan="3"><code>011</code></td><td colspan="5"><code>00110</code></td><td colspan="4"><var>rs</var><br>register</td><td colspan="4"><var>rd</var><br>register</td><th class="title"><a href="#instruction-cmp">Compare value</a></th></tr><tr><td colspan="3"><code>011</code></td><td colspan="5"><code>00111</code></td><td colspan="4"><var>rs</var><br>register</td><td colspan="4"><var>rd</var><br>register</td><th class="title"><a href="#instruction-and">Bitwise and</a></th></tr><tr><td colspan="3"><code>011</code></td><td colspan="5"><code>01000</code></td><td colspan="4"><var>rs</var><br>register</td><td colspan="4"><var>rd</var><br>register</td><th class="title"><a href="#instruction-or">Bitwise or</a></th></tr><tr><td colspan="3"><code>011</code></td><td colspan="5"><code>01001</code></td><td colspan="4"><var>rs</var><br>register</td><td colspan="4"><var>rd</var><br>register</td><th class="title"><a href="#instruction-xor">Bitwise exclusive or</a></th></tr><tr><td colspan="3"><code>011</code></td><td colspan="5"><code>01010</code></td><td colspan="4"><var>rs</var><br>register</td><td colspan="4"><var>rd</var><br>register</td><th class="title"><a href="#instruction-upsample">Upsample two 8bit values to 16bit</a></th></tr><tr><td colspan="3"><code>011</code></td><td colspan="5"><code>01011</code></td><td colspan="4"><var>rs</var><br>register</td><td colspan="4"><var>rd</var><br>register</td><th class="title"><a href="#instruction-not">Bitwise negation</a></th></tr><tr><td colspan="3"><code>011</code></td><td colspan="5"><code>01100</code></td><td colspan="4"><var>rs</var><br>register</td><td colspan="4"><var>rd</var><br>register</td><th class="title"><a href="#instruction-shr">Shift right by 1 bit</a></th></tr><tr><td colspan="3"><code>011</code></td><td colspan="5"><code>01101</code></td><td colspan="4"><var>rs</var><br>register</td><td colspan="4"><var>rd</var><br>register</td><th class="title"><a href="#instruction-shrc">Shift right by 1 bit with carry</a></th></tr><tr><td colspan="3"><code>011</code></td><td colspan="5"><code>01110</code></td><td colspan="4"><var>rs</var><br>register</td><td colspan="4"><var>rd</var><br>register</td><th class="title"><a href="#instruction-shra">Shift right by 1 bit arithmetic</a></th></tr><tr><td colspan="3"><code>011</code></td><td colspan="5"><code>01111</code></td><td colspan="4"><var>rs</var><br>register</td><td colspan="4"><var>rd</var><br>register</td><th class="title"><a href="#instruction-shr8">Shift right by 8 bits</a></th></tr><tr><td colspan="3"><code>011</code></td><td colspan="2"><code>10</code></td><td colspan="3"><code>000</code></td><td colspan="4"><var>rs</var><br>register</td><td colspan="4"><var>rd</var><br>register</td><th class="title"><a href="#instruction-mvz">Move value if zero</a></th></tr><tr><td colspan="3"><code>011</code></td><td colspan="2"><code>10</code></td><td colspan="3"><code>001</code></td><td colspan="4"><var>rs</var><br>register</td><td colspan="4"><var>rd</var><br>register</td><th class="title"><a href="#instruction-mvnz">Move value if not zero</a></th></tr><tr><td colspan="3"><code>011</code></td><td colspan="2"><code>10</code></td><td colspan="3"><code>010</code></td><td colspan="4"><var>rs</var><br>register</td><td colspan="4"><var>rd</var><br>register</td><th class="title"><a href="#instruction-mvc">Move value if carry</a></th></tr><tr><td colspan="3"><code>011</code></td><td colspan="2"><code>10</code></td><td colspan="3"><code>011</code></td><td colspan="4"><var>rs</var><br>register</td><td colspan="4"><var>rd</var><br>register</td><th class="title"><a href="#instruction-mvnc">Move value if not carry</a></th></tr><tr><td colspan="3"><code>011</code></td><td colspan="2"><code>10</code></td><td colspan="3"><code>100</code></td><td colspan="4"><var>rs</var><br>register</td><td colspan="4"><var>rd</var><br>register</td><th class="title"><a href="#instruction-mvn">Move value if negative</a></th></tr><tr><td colspan="3"><code>011</code></td><td colspan="2"><code>10</code></td><td colspan="3"><code>101</code></td><td colspan="4"><var>rs</var><br>register</td><td colspan="4"><var>rd</var><br>register</td><th class="title"><a href="#instruction-mvnn">Move value if not negative</a></th></tr><tr><td colspan="3"><code>011</code></td><td colspan="2"><code>10</code></td><td colspan="3"><code>110</code></td><td colspan="4"><var>rs</var><br>register</td><td colspan="4"><var>rd</var><br>register</td><th class="title"><a href="#instruction-mvo">Move value if overflow</a></th></tr><tr><td colspan="3"><code>011</code></td><td colspan="2"><code>10</code></td><td colspan="3"><code>111</code></td><td colspan="4"><var>rs</var><br>register</td><td colspan="4"><var>rd</var><br>register</td><th class="title"><a href="#instruction-mvno">Move value if not overflow</a></th></tr><tr><td colspan="3"><code>011</code></td><td colspan="5"><code>11000</code></td><td colspan="4"><var>rs</var><br>register</td><td colspan="4"><var>rd</var><br>register</td><th class="title"><a href="#instruction-mv">Move value</a></th></tr><tr><td colspan="3"><code>011</code></td><td colspan="5"><code>11001</code></td><td colspan="4"><var>address</var><br>register</td><td colspan="4"><var>rd</var><br>register</td><th class="title"><a href="#instruction-ld_inc">Load with post-increment</a></th></tr><tr><td colspan="3"><code>011</code></td><td colspan="5"><code>11010</code></td><td colspan="4"><var>address</var><br>register</td><td colspan="4"><var>rs</var><br>register</td><th class="title"><a href="#instruction-st_inc">Store with post-increment</a></th></tr><tr><td colspan="2"><code>10</code></td><td colspan="1"><code>0</code></td><td colspan="5"><var>offset</var><br>5b unsigned int</td><td colspan="4"><var>address</var><br>register</td><td colspan="4"><var>rd</var><br>register</td><th class="title"><a href="#instruction-ld">Load with offset</a></th></tr><tr><td colspan="2"><code>10</code></td><td colspan="1"><code>1</code></td><td colspan="5"><var>offset</var><br>5b unsigned int</td><td colspan="4"><var>address</var><br>register</td><td colspan="4"><var>rs</var><br>register</td><th class="title"><a href="#instruction-st">Store with offset</a></th></tr><tr><td colspan="3"><code>110</code></td><td colspan="1"><code>0</code></td><td colspan="12"><var>offset</var><br>12b signed int</td><th class="title"><a href="#instruction-j">Relative jump</a></th></tr><tr><td colspan="3"><code>110</code></td><td colspan="1"><code>1</code></td><td colspan="12"><var>offset</var><br>12b signed int</td><th class="title"><a href="#instruction-jl">Relative jump and link</a></th></tr><tr><td colspan="4"><code>1110</code></td><td colspan="1"><code>0</code></td><td colspan="3"><var>cr</var><br>control reg</td><td class="placeholder" colspan="4"></td><td colspan="4"><var>rd</var><br>register</td><th class="title"><a href="#instruction-ldcr">Load from control register</a></th></tr><tr><td colspan="4"><code>1110</code></td><td colspan="1"><code>1</code></td><td colspan="3"><var>cr</var><br>control reg</td><td class="placeholder" colspan="4"></td><td colspan="4"><var>rs</var><br>register</td><th class="title"><a href="#instruction-stcr">Store to control register</a></th></tr><tr><td colspan="5"><code>11110</code></td><td colspan="3"><code>000</code></td><td colspan="8"><var>offset</var><br>8b signed int</td><th class="title"><a href="#instruction-bz">Branch if zero</a></th></tr><tr><td colspan="5"><code>11110</code></td><td colspan="3"><code>001</code></td><td colspan="8"><var>offset</var><br>8b signed int</td><th class="title"><a href="#instruction-bnz">Branch if not zero</a></th></tr><tr><td colspan="5"><code>11110</code></td><td colspan="3"><code>010</code></td><td colspan="8"><var>offset</var><br>8b signed int</td><th class="title"><a href="#instruction-bc">Branch if carry</a></th></tr><tr><td colspan="5"><code>11110</code></td><td colspan="3"><code>011</code></td><td colspan="8"><var>offset</var><br>8b signed int</td><th class="title"><a href="#instruction-bnc">Branch if not carry</a></th></tr><tr><td colspan="5"><code>11110</code></td><td colspan="3"><code>100</code></td><td colspan="8"><var>offset</var><br>8b signed int</td><th class="title"><a href="#instruction-bn">Branch if negative</a></th></tr><tr><td colspan="5"><code>11110</code></td><td colspan="3"><code>101</code></td><td colspan="8"><var>offset</var><br>8b signed int</td><th class="title"><a href="#instruction-bnn">Branch if not negative</a></th></tr><tr><td colspan="5"><code>11110</code></td><td colspan="3"><code>110</code></td><td colspan="8"><var>offset</var><br>8b signed int</td><th class="title"><a href="#instruction-bo">Branch if overflow</a></th></tr><tr><td colspan="5"><code>11110</code></td><td colspan="3"><code>111</code></td><td colspan="8"><var>offset</var><br>8b signed int</td><th class="title"><a href="#instruction-bno">Branch if not overflow</a></th></tr><tr><td colspan="5"><code>11111</code></td><td colspan="3"><code>000</code></td><td colspan="8"><var>code</var><br>8b unsigned int</td><th class="title"><a href="#instruction-syscall">Syscall</a></th></tr><tr><td colspan="5"><code>11111</code></td><td colspan="3"><code>001</code></td><td class="placeholder" colspan="4"></td><td colspan="4"><var>address</var><br>register</td><th class="title"><a href="#instruction-ja">Absolute jump</a></th></tr><tr><td colspan="5"><code>11111</code></td><td colspan="3"><code>010</code></td><td class="placeholder" colspan="4"></td><td colspan="4"><var>address</var><br>register</td><th class="title"><a href="#instruction-jla">Absolute jump and link</a></th></tr><tr><td colspan="5"><code>11111</code></td><td colspan="3"><code>011</code></td><td colspan="4"><var>address</var><br>register</td><td colspan="4"><var>rd</var><br>register</td><th class="title"><a href="#instruction-ldp">Load from program memory</a></th></tr><tr><td colspan="5"><code>11111</code></td><td colspan="3"><code>100</code></td><td colspan="4"><var>address</var><br>register</td><td colspan="4"><var>rs</var><br>register</td><th class="title"><a href="#instruction-st_cond">Store to memory conditional</a></th></tr><tr><td colspan="5"><code>11111</code></td><td colspan="3"><code>101</code></td><td class="placeholder" colspan="8"></td><th class="title"><a href="#instruction-reti">Return from interrupt</a></th></tr><tr><td colspan="5"><code>11111</code></td><td colspan="3"><code>111</code></td><td class="placeholder" colspan="8"></td><th class="title"><a href="#instruction-break">Break</a></th></tr></tbody></table></section><section><h2>Instructions</h2><section id="instruction-addi"><h3>addi: Add immediate to register</h3><h4>Encoding</h4><table class="encoding"><thead><tr><th>15</th><th>14</th><th>13</th><th>12</th><th>11</th><th>10</th><th>9</th><th>8</th><th>7</th><th>6</th><th>5</th><th>4</th><th>3</th><th>2</th><th>1</th><th>0</th></tr></thead><tbody><tr><td><code>0</code></td><td><code>0</code></td><td><code>0</code></td><td><code>0</code></td><td colspan="8"><var>immediate</var><br>8b unsigned int</td><td colspan="4"><var>r</var><br>register</td></tr></tbody></table><h4>Assembler syntax</h4><p><code class="asm"><span class="mnemonic">addi</span> <var>r</var>, <var>immediate</var></code></p><h4>Pseudocode</h4><p><code class="pseudocode"><var>r</var> += <var>immediate</var></code></p></section><section id="instruction-subi"><h3>subi: Subtract immediate from register</h3><h4>Encoding</h4><table class="encoding"><thead><tr><th>15</th><th>14</th><th>13</th><th>12</th><th>11</th><th>10</th><th>9</th><th>8</th><th>7</th><th>6</th><th>5</th><th>4</th><th>3</th><th>2</th><th>1</th><th>0</th></tr></thead><tbody><tr><td><code>0</code></td><td><code>0</code></td><td><code>0</code></td><td><code>1</code></td><td colspan="8"><var>immediate</var><br>8b unsigned int</td><td colspan="4"><var>r</var><br>register</td></tr></tbody></table><h4>Assembler syntax</h4><p><code class="asm"><span class="mnemonic">subi</span> <var>r</var>, <var>immediate</var></code></p><h4>Pseudocode</h4><p><code class="pseudocode"><var>r</var> += <var>immediate</var></code></p></section><section id="instruction-cmpi"><h3>cmpi: Compare immediate with register</h3><h4>Encoding</h4><table class="encoding"><thead><tr><th>15</th><th>14</th><th>13</th><th>12</th><th>11</th><th>10</th><th>9</th><th>8</th><th>7</th><th>6</th><th>5</th><th>4</th><th>3</th><th>2</th><th>1</th><th>0</th></tr></thead><tbody><tr><td><code>0</code></td><td><code>0</code></td><td><code>1</code></td><td><code>0</code></td><td colspan="8"><var>immediate</var><br>8b unsigned int</td><td colspan="4"><var>r</var><br>register</td></tr></tbody></table><h4>Assembler syntax</h4><p><code class="asm"><span class="mnemonic">cmpi</span> <var>r</var>, <var>immediate</var></code></p><h4>Pseudocode</h4><p><code class="pseudocode">ignore_value(<var>r</var> - <var>immediate</var>)</code></p></section><section id="instruction-addipc"><h3>addipc: Add immediate to program counter</h3><h4>Encoding</h4><table class="encoding"><thead><tr><th>15</th><th>14</th><th>13</th><th>12</th><th>11</th><th>10</th><th>9</th><th>8</th><th>7</th><th>6</th><th>5</th><th>4</th><th>3</th><th>2</th><th>1</th><th>0</th></tr></thead><tbody><tr><td><code>0</code></td><td><code>0</code></td><td><code>1</code></td><td><code>1</code></td><td colspan="8"><var>immediate</var><br>8b unsigned int</td><td colspan="4"><var>rd</var><br>register</td></tr></tbody></table><h4>Assembler syntax</h4><p><code class="asm"><span class="mnemonic">addipc</span> <var>rd</var>, <var>immediate</var></code></p><h4>Pseudocode</h4><p><code class="pseudocode">r = Pc + <var>immediate</var></code></p></section><section id="instruction-ldi"><h3>ldi: Load immediate</h3><h4>Encoding</h4><table class="encoding"><thead><tr><th>15</th><th>14</th><th>13</th><th>12</th><th>11</th><th>10</th><th>9</th><th>8</th><th>7</th><th>6</th><th>5</th><th>4</th><th>3</th><th>2</th><th>1</th><th>0</th></tr></thead><tbody><tr><td><code>0</code></td><td><code>1</code></td><td><code>0</code></td><td><code>0</code></td><td colspan="8"><var>immediate</var><br>8b unsigned int</td><td colspan="4"><var>rd</var><br>register</td></tr></tbody></table><h4>Assembler syntax</h4><p><code class="asm"><span class="mnemonic">ldi</span> <var>rd</var>, <var>immediate</var></code></p><h4>Pseudocode</h4><p><code class="pseudocode">r = <var>immediate</var></code></p></section><section id="instruction-ldui"><h3>ldui: Load upper immediate</h3><h4>Encoding</h4><table class="encoding"><thead><tr><th>15</th><th>14</th><th>13</th><th>12</th><th>11</th><th>10</th><th>9</th><th>8</th><th>7</th><th>6</th><th>5</th><th>4</th><th>3</th><th>2</th><th>1</th><th>0</th></tr></thead><tbody><tr><td><code>0</code></td><td><code>1</code></td><td><code>0</code></td><td><code>1</code></td><td colspan="8"><var>immediate</var><br>8b unsigned int</td><td colspan="4"><var>rd</var><br>register</td></tr></tbody></table><h4>Assembler syntax</h4><p><code class="asm"><span class="mnemonic">ldui</span> <var>rd</var>, <var>immediate</var></code></p><h4>Pseudocode</h4><p><code class="pseudocode">r = <var>immediate</var> << <span class="number">8</span></code></p></section><section id="instruction-add"><h3>add: Add</h3><h4>Encoding</h4><table class="encoding"><thead><tr><th>15</th><th>14</th><th>13</th><th>12</th><th>11</th><th>10</th><th>9</th><th>8</th><th>7</th><th>6</th><th>5</th><th>4</th><th>3</th><th>2</th><th>1</th><th>0</th></tr></thead><tbody><tr><td><code>0</code></td><td><code>1</code></td><td><code>1</code></td><td><code>0</code></td><td><code>0</code></td><td><code>0</code></td><td><code>0</code></td><td><code>0</code></td><td colspan="4"><var>rs</var><br>register</td><td colspan="4"><var>rd</var><br>register</td></tr></tbody></table><h4>Assembler syntax</h4><p><code class="asm"><span class="mnemonic">add</span> <var>rd</var>, <var>rs</var></code></p><h4>Pseudocode</h4><p><code class="pseudocode"><var>rd</var> = <var>rd</var> + <var>rs</var></code></p></section><section id="instruction-addc"><h3>addc: Add with carry</h3><h4>Encoding</h4><table class="encoding"><thead><tr><th>15</th><th>14</th><th>13</th><th>12</th><th>11</th><th>10</th><th>9</th><th>8</th><th>7</th><th>6</th><th>5</th><th>4</th><th>3</th><th>2</th><th>1</th><th>0</th></tr></thead><tbody><tr><td><code>0</code></td><td><code>1</code></td><td><code>1</code></td><td><code>0</code></td><td><code>0</code></td><td><code>0</code></td><td><code>0</code></td><td><code>1</code></td><td colspan="4"><var>rs</var><br>register</td><td colspan="4"><var>rd</var><br>register</td></tr></tbody></table><h4>Assembler syntax</h4><p><code class="asm"><span class="mnemonic">addc</span> <var>rd</var>, <var>rs</var></code></p><h4>Pseudocode</h4><p><code class="pseudocode"><var>rd</var> = <var>rd</var> + <var>rs</var> + carry</code></p></section><section id="instruction-sub"><h3>sub: Subtract</h3><h4>Encoding</h4><table class="encoding"><thead><tr><th>15</th><th>14</th><th>13</th><th>12</th><th>11</th><th>10</th><th>9</th><th>8</th><th>7</th><th>6</th><th>5</th><th>4</th><th>3</th><th>2</th><th>1</th><th>0</th></tr></thead><tbody><tr><td><code>0</code></td><td><code>1</code></td><td><code>1</code></td><td><code>0</code></td><td><code>0</code></td><td><code>0</code></td><td><code>1</code></td><td><code>0</code></td><td colspan="4"><var>rs</var><br>register</td><td colspan="4"><var>rd</var><br>register</td></tr></tbody></table><h4>Assembler syntax</h4><p><code class="asm"><span class="mnemonic">sub</span> <var>rd</var>, <var>rs</var></code></p><h4>Pseudocode</h4><p><code class="pseudocode"><var>rd</var> = <var>rd</var> - <var>rs</var></code></p></section><section id="instruction-subc"><h3>subc: Subtract with carry</h3><h4>Encoding</h4><table class="encoding"><thead><tr><th>15</th><th>14</th><th>13</th><th>12</th><th>11</th><th>10</th><th>9</th><th>8</th><th>7</th><th>6</th><th>5</th><th>4</th><th>3</th><th>2</th><th>1</th><th>0</th></tr></thead><tbody><tr><td><code>0</code></td><td><code>1</code></td><td><code>1</code></td><td><code>0</code></td><td><code>0</code></td><td><code>0</code></td><td><code>1</code></td><td><code>1</code></td><td colspan="4"><var>rs</var><br>register</td><td colspan="4"><var>rd</var><br>register</td></tr></tbody></table><h4>Assembler syntax</h4><p><code class="asm"><span class="mnemonic">subc</span> <var>rd</var>, <var>rs</var></code></p><h4>Pseudocode</h4><p><code class="pseudocode"><var>rd</var> = <var>rd</var> - <var>rs</var> + carry</code></p></section><section id="instruction-rsub"><h3>rsub: Reverse subtract</h3><h4>Encoding</h4><table class="encoding"><thead><tr><th>15</th><th>14</th><th>13</th><th>12</th><th>11</th><th>10</th><th>9</th><th>8</th><th>7</th><th>6</th><th>5</th><th>4</th><th>3</th><th>2</th><th>1</th><th>0</th></tr></thead><tbody><tr><td><code>0</code></td><td><code>1</code></td><td><code>1</code></td><td><code>0</code></td><td><code>0</code></td><td><code>1</code></td><td><code>0</code></td><td><code>0</code></td><td colspan="4"><var>rs</var><br>register</td><td colspan="4"><var>rd</var><br>register</td></tr></tbody></table><h4>Assembler syntax</h4><p><code class="asm"><span class="mnemonic">rsub</span> <var>rd</var>, <var>rs</var></code></p><h4>Pseudocode</h4><p><code class="pseudocode"><var>rd</var> = <var>rs</var> - <var>rd</var></code></p></section><section id="instruction-rsubc"><h3>rsubc: Reverse subtract with carry</h3><h4>Encoding</h4><table class="encoding"><thead><tr><th>15</th><th>14</th><th>13</th><th>12</th><th>11</th><th>10</th><th>9</th><th>8</th><th>7</th><th>6</th><th>5</th><th>4</th><th>3</th><th>2</th><th>1</th><th>0</th></tr></thead><tbody><tr><td><code>0</code></td><td><code>1</code></td><td><code>1</code></td><td><code>0</code></td><td><code>0</code></td><td><code>1</code></td><td><code>0</code></td><td><code>1</code></td><td colspan="4"><var>rs</var><br>register</td><td colspan="4"><var>rd</var><br>register</td></tr></tbody></table><h4>Assembler syntax</h4><p><code class="asm"><span class="mnemonic">rsubc</span> <var>rd</var>, <var>rs</var></code></p><h4>Pseudocode</h4><p><code class="pseudocode"><var>rd</var> = <var>rs</var> - <var>rd</var> + carry</code></p></section><section id="instruction-cmp"><h3>cmp: Compare value</h3><h4>Encoding</h4><table class="encoding"><thead><tr><th>15</th><th>14</th><th>13</th><th>12</th><th>11</th><th>10</th><th>9</th><th>8</th><th>7</th><th>6</th><th>5</th><th>4</th><th>3</th><th>2</th><th>1</th><th>0</th></tr></thead><tbody><tr><td><code>0</code></td><td><code>1</code></td><td><code>1</code></td><td><code>0</code></td><td><code>0</code></td><td><code>1</code></td><td><code>1</code></td><td><code>0</code></td><td colspan="4"><var>rs</var><br>register</td><td colspan="4"><var>rd</var><br>register</td></tr></tbody></table><h4>Assembler syntax</h4><p><code class="asm"><span class="mnemonic">cmp</span> <var>rd</var>, <var>rs</var></code></p><h4>Pseudocode</h4><p><code class="pseudocode">ignore_value(<var>rd</var> - <var>rs</var>)</code></p></section><section id="instruction-and"><h3>and: Bitwise and</h3><h4>Encoding</h4><table class="encoding"><thead><tr><th>15</th><th>14</th><th>13</th><th>12</th><th>11</th><th>10</th><th>9</th><th>8</th><th>7</th><th>6</th><th>5</th><th>4</th><th>3</th><th>2</th><th>1</th><th>0</th></tr></thead><tbody><tr><td><code>0</code></td><td><code>1</code></td><td><code>1</code></td><td><code>0</code></td><td><code>0</code></td><td><code>1</code></td><td><code>1</code></td><td><code>1</code></td><td colspan="4"><var>rs</var><br>register</td><td colspan="4"><var>rd</var><br>register</td></tr></tbody></table><h4>Assembler syntax</h4><p><code class="asm"><span class="mnemonic">and</span> <var>rd</var>, <var>rs</var></code></p><h4>Pseudocode</h4><p><code class="pseudocode"><var>rd</var> = <var>rd</var> & <var>rs</var></code></p></section><section id="instruction-or"><h3>or: Bitwise or</h3><h4>Encoding</h4><table class="encoding"><thead><tr><th>15</th><th>14</th><th>13</th><th>12</th><th>11</th><th>10</th><th>9</th><th>8</th><th>7</th><th>6</th><th>5</th><th>4</th><th>3</th><th>2</th><th>1</th><th>0</th></tr></thead><tbody><tr><td><code>0</code></td><td><code>1</code></td><td><code>1</code></td><td><code>0</code></td><td><code>1</code></td><td><code>0</code></td><td><code>0</code></td><td><code>0</code></td><td colspan="4"><var>rs</var><br>register</td><td colspan="4"><var>rd</var><br>register</td></tr></tbody></table><h4>Assembler syntax</h4><p><code class="asm"><span class="mnemonic">or</span> <var>rd</var>, <var>rs</var></code></p><h4>Pseudocode</h4><p><code class="pseudocode"><var>rd</var> = <var>rd</var> | <var>rs</var></code></p></section><section id="instruction-xor"><h3>xor: Bitwise exclusive or</h3><h4>Encoding</h4><table class="encoding"><thead><tr><th>15</th><th>14</th><th>13</th><th>12</th><th>11</th><th>10</th><th>9</th><th>8</th><th>7</th><th>6</th><th>5</th><th>4</th><th>3</th><th>2</th><th>1</th><th>0</th></tr></thead><tbody><tr><td><code>0</code></td><td><code>1</code></td><td><code>1</code></td><td><code>0</code></td><td><code>1</code></td><td><code>0</code></td><td><code>0</code></td><td><code>1</code></td><td colspan="4"><var>rs</var><br>register</td><td colspan="4"><var>rd</var><br>register</td></tr></tbody></table><h4>Assembler syntax</h4><p><code class="asm"><span class="mnemonic">xor</span> <var>rd</var>, <var>rs</var></code></p><h4>Pseudocode</h4><p><code class="pseudocode"><var>rd</var> = <var>rd</var> ^ <var>rs</var></code></p></section><section id="instruction-upsample"><h3>upsample: Upsample two 8bit values to 16bit</h3><h4>Encoding</h4><table class="encoding"><thead><tr><th>15</th><th>14</th><th>13</th><th>12</th><th>11</th><th>10</th><th>9</th><th>8</th><th>7</th><th>6</th><th>5</th><th>4</th><th>3</th><th>2</th><th>1</th><th>0</th></tr></thead><tbody><tr><td><code>0</code></td><td><code>1</code></td><td><code>1</code></td><td><code>0</code></td><td><code>1</code></td><td><code>0</code></td><td><code>1</code></td><td><code>0</code></td><td colspan="4"><var>rs</var><br>register</td><td colspan="4"><var>rd</var><br>register</td></tr></tbody></table><h4>Assembler syntax</h4><p><code class="asm"><span class="mnemonic">upsample</span> <var>rd</var>, <var>rs</var></code></p><h4>Pseudocode</h4><p><code class="pseudocode"><var>rd</var> = (<var>rd</var> & <span class="number">0xff</span>) | (<var>rs</var> << <span class="number">8</span>)</code></p></section><section id="instruction-not"><h3>not: Bitwise negation</h3><h4>Encoding</h4><table class="encoding"><thead><tr><th>15</th><th>14</th><th>13</th><th>12</th><th>11</th><th>10</th><th>9</th><th>8</th><th>7</th><th>6</th><th>5</th><th>4</th><th>3</th><th>2</th><th>1</th><th>0</th></tr></thead><tbody><tr><td><code>0</code></td><td><code>1</code></td><td><code>1</code></td><td><code>0</code></td><td><code>1</code></td><td><code>0</code></td><td><code>1</code></td><td><code>1</code></td><td colspan="4"><var>rs</var><br>register</td><td colspan="4"><var>rd</var><br>register</td></tr></tbody></table><h4>Assembler syntax</h4><p><code class="asm"><span class="mnemonic">not</span> <var>rd</var>, <var>rs</var></code></p><h4>Pseudocode</h4><p><code class="pseudocode"><var>rd</var> = ~<var>rs</var></code></p></section><section id="instruction-shr"><h3>shr: Shift right by 1 bit</h3><h4>Encoding</h4><table class="encoding"><thead><tr><th>15</th><th>14</th><th>13</th><th>12</th><th>11</th><th>10</th><th>9</th><th>8</th><th>7</th><th>6</th><th>5</th><th>4</th><th>3</th><th>2</th><th>1</th><th>0</th></tr></thead><tbody><tr><td><code>0</code></td><td><code>1</code></td><td><code>1</code></td><td><code>0</code></td><td><code>1</code></td><td><code>1</code></td><td><code>0</code></td><td><code>0</code></td><td colspan="4"><var>rs</var><br>register</td><td colspan="4"><var>rd</var><br>register</td></tr></tbody></table><h4>Assembler syntax</h4><p><code class="asm"><span class="mnemonic">shr</span> <var>rd</var>, <var>rs</var></code></p><h4>Pseudocode</h4><p><code class="pseudocode"><var>rd</var> = <var>rs</var> >> <span class="number">1</span></code></p></section><section id="instruction-shrc"><h3>shrc: Shift right by 1 bit with carry</h3><h4>Encoding</h4><table class="encoding"><thead><tr><th>15</th><th>14</th><th>13</th><th>12</th><th>11</th><th>10</th><th>9</th><th>8</th><th>7</th><th>6</th><th>5</th><th>4</th><th>3</th><th>2</th><th>1</th><th>0</th></tr></thead><tbody><tr><td><code>0</code></td><td><code>1</code></td><td><code>1</code></td><td><code>0</code></td><td><code>1</code></td><td><code>1</code></td><td><code>0</code></td><td><code>1</code></td><td colspan="4"><var>rs</var><br>register</td><td colspan="4"><var>rd</var><br>register</td></tr></tbody></table><h4>Assembler syntax</h4><p><code class="asm"><span class="mnemonic">shrc</span> <var>rd</var>, <var>rs</var></code></p><h4>Pseudocode</h4><p><code class="pseudocode"><var>rd</var> = (<var>rs</var> >> <span class="number">1</span>) | (carry << <span class="number">15</span>)</code></p></section><section id="instruction-shra"><h3>shra: Shift right by 1 bit arithmetic</h3><h4>Encoding</h4><table class="encoding"><thead><tr><th>15</th><th>14</th><th>13</th><th>12</th><th>11</th><th>10</th><th>9</th><th>8</th><th>7</th><th>6</th><th>5</th><th>4</th><th>3</th><th>2</th><th>1</th><th>0</th></tr></thead><tbody><tr><td><code>0</code></td><td><code>1</code></td><td><code>1</code></td><td><code>0</code></td><td><code>1</code></td><td><code>1</code></td><td><code>1</code></td><td><code>0</code></td><td colspan="4"><var>rs</var><br>register</td><td colspan="4"><var>rd</var><br>register</td></tr></tbody></table><h4>Assembler syntax</h4><p><code class="asm"><span class="mnemonic">shra</span> <var>rd</var>, <var>rs</var></code></p><h4>Pseudocode</h4><p><code class="pseudocode"><var>rd</var> = (<var>rs</var> >> <span class="number">1</span>) | (<var>rs</var> & <span class="number">0x8000</span>)</code></p></section><section id="instruction-shr8"><h3>shr8: Shift right by 8 bits</h3><h4>Encoding</h4><table class="encoding"><thead><tr><th>15</th><th>14</th><th>13</th><th>12</th><th>11</th><th>10</th><th>9</th><th>8</th><th>7</th><th>6</th><th>5</th><th>4</th><th>3</th><th>2</th><th>1</th><th>0</th></tr></thead><tbody><tr><td><code>0</code></td><td><code>1</code></td><td><code>1</code></td><td><code>0</code></td><td><code>1</code></td><td><code>1</code></td><td><code>1</code></td><td><code>1</code></td><td colspan="4"><var>rs</var><br>register</td><td colspan="4"><var>rd</var><br>register</td></tr></tbody></table><h4>Assembler syntax</h4><p><code class="asm"><span class="mnemonic">shr8</span> <var>rd</var>, <var>rs</var></code></p><h4>Pseudocode</h4><p><code class="pseudocode"><var>rd</var> = <var>rs</var> >> <span class="number">8</span></code></p></section><section id="instruction-mvz"><h3>mvz: Move value if zero</h3><h4>Encoding</h4><table class="encoding"><thead><tr><th>15</th><th>14</th><th>13</th><th>12</th><th>11</th><th>10</th><th>9</th><th>8</th><th>7</th><th>6</th><th>5</th><th>4</th><th>3</th><th>2</th><th>1</th><th>0</th></tr></thead><tbody><tr><td><code>0</code></td><td><code>1</code></td><td><code>1</code></td><td><code>1</code></td><td><code>0</code></td><td><code>0</code></td><td><code>0</code></td><td><code>0</code></td><td colspan="4"><var>rs</var><br>register</td><td colspan="4"><var>rd</var><br>register</td></tr></tbody></table><h4>Assembler syntax</h4><p><code class="asm"><span class="mnemonic">mvz</span> <var>rd</var>, <var>rs</var></code></p><h4>Pseudocode</h4><p><code class="pseudocode"><span class="keyword">if</span> zero: <var>rd</var> = <var>rs</var></code></p></section><section id="instruction-mvnz"><h3>mvnz: Move value if not zero</h3><h4>Encoding</h4><table class="encoding"><thead><tr><th>15</th><th>14</th><th>13</th><th>12</th><th>11</th><th>10</th><th>9</th><th>8</th><th>7</th><th>6</th><th>5</th><th>4</th><th>3</th><th>2</th><th>1</th><th>0</th></tr></thead><tbody><tr><td><code>0</code></td><td><code>1</code></td><td><code>1</code></td><td><code>1</code></td><td><code>0</code></td><td><code>0</code></td><td><code>0</code></td><td><code>1</code></td><td colspan="4"><var>rs</var><br>register</td><td colspan="4"><var>rd</var><br>register</td></tr></tbody></table><h4>Assembler syntax</h4><p><code class="asm"><span class="mnemonic">mvnz</span> <var>rd</var>, <var>rs</var></code></p><h4>Pseudocode</h4><p><code class="pseudocode"><span class="keyword">if</span> <span class="mnemonic">not</span> zero: <var>rd</var> = <var>rs</var></code></p></section><section id="instruction-mvc"><h3>mvc: Move value if carry</h3><h4>Encoding</h4><table class="encoding"><thead><tr><th>15</th><th>14</th><th>13</th><th>12</th><th>11</th><th>10</th><th>9</th><th>8</th><th>7</th><th>6</th><th>5</th><th>4</th><th>3</th><th>2</th><th>1</th><th>0</th></tr></thead><tbody><tr><td><code>0</code></td><td><code>1</code></td><td><code>1</code></td><td><code>1</code></td><td><code>0</code></td><td><code>0</code></td><td><code>1</code></td><td><code>0</code></td><td colspan="4"><var>rs</var><br>register</td><td colspan="4"><var>rd</var><br>register</td></tr></tbody></table><h4>Assembler syntax</h4><p><code class="asm"><span class="mnemonic">mvc</span> <var>rd</var>, <var>rs</var></code></p><h4>Pseudocode</h4><p><code class="pseudocode"><span class="keyword">if</span> carry: <var>rd</var> = <var>rs</var></code></p></section><section id="instruction-mvnc"><h3>mvnc: Move value if not carry</h3><h4>Encoding</h4><table class="encoding"><thead><tr><th>15</th><th>14</th><th>13</th><th>12</th><th>11</th><th>10</th><th>9</th><th>8</th><th>7</th><th>6</th><th>5</th><th>4</th><th>3</th><th>2</th><th>1</th><th>0</th></tr></thead><tbody><tr><td><code>0</code></td><td><code>1</code></td><td><code>1</code></td><td><code>1</code></td><td><code>0</code></td><td><code>0</code></td><td><code>1</code></td><td><code>1</code></td><td colspan="4"><var>rs</var><br>register</td><td colspan="4"><var>rd</var><br>register</td></tr></tbody></table><h4>Assembler syntax</h4><p><code class="asm"><span class="mnemonic">mvnc</span> <var>rd</var>, <var>rs</var></code></p><h4>Pseudocode</h4><p><code class="pseudocode"><span class="keyword">if</span> <span class="mnemonic">not</span> carry: <var>rd</var> = <var>rs</var></code></p></section><section id="instruction-mvn"><h3>mvn: Move value if negative</h3><h4>Encoding</h4><table class="encoding"><thead><tr><th>15</th><th>14</th><th>13</th><th>12</th><th>11</th><th>10</th><th>9</th><th>8</th><th>7</th><th>6</th><th>5</th><th>4</th><th>3</th><th>2</th><th>1</th><th>0</th></tr></thead><tbody><tr><td><code>0</code></td><td><code>1</code></td><td><code>1</code></td><td><code>1</code></td><td><code>0</code></td><td><code>1</code></td><td><code>0</code></td><td><code>0</code></td><td colspan="4"><var>rs</var><br>register</td><td colspan="4"><var>rd</var><br>register</td></tr></tbody></table><h4>Assembler syntax</h4><p><code class="asm"><span class="mnemonic">mvn</span> <var>rd</var>, <var>rs</var></code></p><h4>Pseudocode</h4><p><code class="pseudocode"><span class="keyword">if</span> negative: <var>rd</var> = <var>rs</var></code></p></section><section id="instruction-mvnn"><h3>mvnn: Move value if not negative</h3><h4>Encoding</h4><table class="encoding"><thead><tr><th>15</th><th>14</th><th>13</th><th>12</th><th>11</th><th>10</th><th>9</th><th>8</th><th>7</th><th>6</th><th>5</th><th>4</th><th>3</th><th>2</th><th>1</th><th>0</th></tr></thead><tbody><tr><td><code>0</code></td><td><code>1</code></td><td><code>1</code></td><td><code>1</code></td><td><code>0</code></td><td><code>1</code></td><td><code>0</code></td><td><code>1</code></td><td colspan="4"><var>rs</var><br>register</td><td colspan="4"><var>rd</var><br>register</td></tr></tbody></table><h4>Assembler syntax</h4><p><code class="asm"><span class="mnemonic">mvnn</span> <var>rd</var>, <var>rs</var></code></p><h4>Pseudocode</h4><p><code class="pseudocode"><span class="keyword">if</span> <span class="mnemonic">not</span> negative: <var>rd</var> = <var>rs</var></code></p></section><section id="instruction-mvo"><h3>mvo: Move value if overflow</h3><h4>Encoding</h4><table class="encoding"><thead><tr><th>15</th><th>14</th><th>13</th><th>12</th><th>11</th><th>10</th><th>9</th><th>8</th><th>7</th><th>6</th><th>5</th><th>4</th><th>3</th><th>2</th><th>1</th><th>0</th></tr></thead><tbody><tr><td><code>0</code></td><td><code>1</code></td><td><code>1</code></td><td><code>1</code></td><td><code>0</code></td><td><code>1</code></td><td><code>1</code></td><td><code>0</code></td><td colspan="4"><var>rs</var><br>register</td><td colspan="4"><var>rd</var><br>register</td></tr></tbody></table><h4>Assembler syntax</h4><p><code class="asm"><span class="mnemonic">mvo</span> <var>rd</var>, <var>rs</var></code></p><h4>Pseudocode</h4><p><code class="pseudocode"><span class="keyword">if</span> overflow: <var>rd</var> = <var>rs</var></code></p></section><section id="instruction-mvno"><h3>mvno: Move value if not overflow</h3><h4>Encoding</h4><table class="encoding"><thead><tr><th>15</th><th>14</th><th>13</th><th>12</th><th>11</th><th>10</th><th>9</th><th>8</th><th>7</th><th>6</th><th>5</th><th>4</th><th>3</th><th>2</th><th>1</th><th>0</th></tr></thead><tbody><tr><td><code>0</code></td><td><code>1</code></td><td><code>1</code></td><td><code>1</code></td><td><code>0</code></td><td><code>1</code></td><td><code>1</code></td><td><code>1</code></td><td colspan="4"><var>rs</var><br>register</td><td colspan="4"><var>rd</var><br>register</td></tr></tbody></table><h4>Assembler syntax</h4><p><code class="asm"><span class="mnemonic">mvno</span> <var>rd</var>, <var>rs</var></code></p><h4>Pseudocode</h4><p><code class="pseudocode"><span class="keyword">if</span> <span class="mnemonic">not</span> overflow: <var>rd</var> = <var>rs</var></code></p></section><section id="instruction-mv"><h3>mv: Move value</h3><h4>Encoding</h4><table class="encoding"><thead><tr><th>15</th><th>14</th><th>13</th><th>12</th><th>11</th><th>10</th><th>9</th><th>8</th><th>7</th><th>6</th><th>5</th><th>4</th><th>3</th><th>2</th><th>1</th><th>0</th></tr></thead><tbody><tr><td><code>0</code></td><td><code>1</code></td><td><code>1</code></td><td><code>1</code></td><td><code>1</code></td><td><code>0</code></td><td><code>0</code></td><td><code>0</code></td><td colspan="4"><var>rs</var><br>register</td><td colspan="4"><var>rd</var><br>register</td></tr></tbody></table><h4>Assembler syntax</h4><p><code class="asm"><span class="mnemonic">mv</span> <var>rd</var>, <var>rs</var></code></p><h4>Pseudocode</h4><p><code class="pseudocode"><var>rd</var> = <var>rs</var></code></p></section><section id="instruction-ld_inc"><h3>ld_inc: Load with post-increment</h3><h4>Encoding</h4><table class="encoding"><thead><tr><th>15</th><th>14</th><th>13</th><th>12</th><th>11</th><th>10</th><th>9</th><th>8</th><th>7</th><th>6</th><th>5</th><th>4</th><th>3</th><th>2</th><th>1</th><th>0</th></tr></thead><tbody><tr><td><code>0</code></td><td><code>1</code></td><td><code>1</code></td><td><code>1</code></td><td><code>1</code></td><td><code>0</code></td><td><code>0</code></td><td><code>1</code></td><td colspan="4"><var>address</var><br>register</td><td colspan="4"><var>rd</var><br>register</td></tr></tbody></table><h4>Assembler syntax</h4><p><code class="asm"><span class="mnemonic">ld_inc</span> <var>rd</var>, <var>address</var></code></p><h4>Pseudocode</h4><p><code class="pseudocode"><var>rd</var> = memory[<var>address</var>]
<var>address</var> += <span class="number">1</span></code></p></section><section id="instruction-st_inc"><h3>st_inc: Store with post-increment</h3><h4>Encoding</h4><table class="encoding"><thead><tr><th>15</th><th>14</th><th>13</th><th>12</th><th>11</th><th>10</th><th>9</th><th>8</th><th>7</th><th>6</th><th>5</th><th>4</th><th>3</th><th>2</th><th>1</th><th>0</th></tr></thead><tbody><tr><td><code>0</code></td><td><code>1</code></td><td><code>1</code></td><td><code>1</code></td><td><code>1</code></td><td><code>0</code></td><td><code>1</code></td><td><code>0</code></td><td colspan="4"><var>address</var><br>register</td><td colspan="4"><var>rs</var><br>register</td></tr></tbody></table><h4>Assembler syntax</h4><p><code class="asm"><span class="mnemonic">st_inc</span> <var>rs</var>, <var>address</var></code></p><h4>Pseudocode</h4><p><code class="pseudocode">memory[<var>address</var>] = <var>rs</var>
<var>address</var> += <span class="number">1</span></code></p></section><section id="instruction-ld"><h3>ld: Load with offset</h3><h4>Encoding</h4><table class="encoding"><thead><tr><th>15</th><th>14</th><th>13</th><th>12</th><th>11</th><th>10</th><th>9</th><th>8</th><th>7</th><th>6</th><th>5</th><th>4</th><th>3</th><th>2</th><th>1</th><th>0</th></tr></thead><tbody><tr><td><code>1</code></td><td><code>0</code></td><td><code>0</code></td><td colspan="5"><var>offset</var><br>5b unsigned int</td><td colspan="4"><var>address</var><br>register</td><td colspan="4"><var>rd</var><br>register</td></tr></tbody></table><h4>Assembler syntax</h4><p><code class="asm"><span class="mnemonic">ld</span> <var>rd</var>, <var>address</var>, <var>offset</var></code></p><h4>Pseudocode</h4><p><code class="pseudocode"><var>rd</var> = memory[<var>address</var> + <var>offset</var>]</code></p></section><section id="instruction-st"><h3>st: Store with offset</h3><h4>Encoding</h4><table class="encoding"><thead><tr><th>15</th><th>14</th><th>13</th><th>12</th><th>11</th><th>10</th><th>9</th><th>8</th><th>7</th><th>6</th><th>5</th><th>4</th><th>3</th><th>2</th><th>1</th><th>0</th></tr></thead><tbody><tr><td><code>1</code></td><td><code>0</code></td><td><code>1</code></td><td colspan="5"><var>offset</var><br>5b unsigned int</td><td colspan="4"><var>address</var><br>register</td><td colspan="4"><var>rs</var><br>register</td></tr></tbody></table><h4>Assembler syntax</h4><p><code class="asm"><span class="mnemonic">st</span> <var>rs</var>, <var>address</var>, <var>offset</var></code></p><h4>Pseudocode</h4><p><code class="pseudocode">memory[<var>address</var> + <var>offset</var>] = <var>rs</var></code></p></section><section id="instruction-j"><h3>j: Relative jump</h3><h4>Encoding</h4><table class="encoding"><thead><tr><th>15</th><th>14</th><th>13</th><th>12</th><th>11</th><th>10</th><th>9</th><th>8</th><th>7</th><th>6</th><th>5</th><th>4</th><th>3</th><th>2</th><th>1</th><th>0</th></tr></thead><tbody><tr><td><code>1</code></td><td><code>1</code></td><td><code>0</code></td><td><code>0</code></td><td colspan="12"><var>offset</var><br>12b signed int</td></tr></tbody></table><h4>Assembler syntax</h4><p><code class="asm"><span class="mnemonic">j</span> <var>offset</var></code></p><h4>Pseudocode</h4><p><code class="pseudocode">Pc += <var>offset</var></code></p></section><section id="instruction-jl"><h3>jl: Relative jump and link</h3><h4>Encoding</h4><table class="encoding"><thead><tr><th>15</th><th>14</th><th>13</th><th>12</th><th>11</th><th>10</th><th>9</th><th>8</th><th>7</th><th>6</th><th>5</th><th>4</th><th>3</th><th>2</th><th>1</th><th>0</th></tr></thead><tbody><tr><td><code>1</code></td><td><code>1</code></td><td><code>0</code></td><td><code>1</code></td><td colspan="12"><var>offset</var><br>12b signed int</td></tr></tbody></table><h4>Assembler syntax</h4><p><code class="asm"><span class="mnemonic">jl</span> <var>offset</var></code></p><h4>Pseudocode</h4><p><code class="pseudocode">r1 = Pc
Pc += <var>offset</var></code></p></section><section id="instruction-ldcr"><h3>ldcr: Load from control register</h3><h4>Encoding</h4><table class="encoding"><thead><tr><th>15</th><th>14</th><th>13</th><th>12</th><th>11</th><th>10</th><th>9</th><th>8</th><th>7</th><th>6</th><th>5</th><th>4</th><th>3</th><th>2</th><th>1</th><th>0</th></tr></thead><tbody><tr><td><code>1</code></td><td><code>1</code></td><td><code>1</code></td><td><code>0</code></td><td><code>0</code></td><td colspan="3"><var>cr</var><br>control reg</td><td class="placeholder" colspan="4"></td><td colspan="4"><var>rd</var><br>register</td></tr></tbody></table><h4>Assembler syntax</h4><p><code class="asm"><span class="mnemonic">ldcr</span> <var>rd</var>, <var>cr</var></code></p><h4>Pseudocode</h4><p><code class="pseudocode"><var>rd</var> = <var>cr</var></code></p></section><section id="instruction-stcr"><h3>stcr: Store to control register</h3><h4>Encoding</h4><table class="encoding"><thead><tr><th>15</th><th>14</th><th>13</th><th>12</th><th>11</th><th>10</th><th>9</th><th>8</th><th>7</th><th>6</th><th>5</th><th>4</th><th>3</th><th>2</th><th>1</th><th>0</th></tr></thead><tbody><tr><td><code>1</code></td><td><code>1</code></td><td><code>1</code></td><td><code>0</code></td><td><code>1</code></td><td colspan="3"><var>cr</var><br>control reg</td><td class="placeholder" colspan="4"></td><td colspan="4"><var>rs</var><br>register</td></tr></tbody></table><h4>Assembler syntax</h4><p><code class="asm"><span class="mnemonic">stcr</span> <var>cr</var>, <var>rs</var></code></p><h4>Pseudocode</h4><p><code class="pseudocode"><var>cr</var> = <var>rs</var></code></p></section><section id="instruction-bz"><h3>bz: Branch if zero</h3><h4>Encoding</h4><table class="encoding"><thead><tr><th>15</th><th>14</th><th>13</th><th>12</th><th>11</th><th>10</th><th>9</th><th>8</th><th>7</th><th>6</th><th>5</th><th>4</th><th>3</th><th>2</th><th>1</th><th>0</th></tr></thead><tbody><tr><td><code>1</code></td><td><code>1</code></td><td><code>1</code></td><td><code>1</code></td><td><code>0</code></td><td><code>0</code></td><td><code>0</code></td><td><code>0</code></td><td colspan="8"><var>offset</var><br>8b signed int</td></tr></tbody></table><h4>Assembler syntax</h4><p><code class="asm"><span class="mnemonic">bz</span> <var>offset</var></code></p><h4>Pseudocode</h4><p><code class="pseudocode"><span class="keyword">if</span> zero: Pc += <var>offset</var></code></p></section><section id="instruction-bnz"><h3>bnz: Branch if not zero</h3><h4>Encoding</h4><table class="encoding"><thead><tr><th>15</th><th>14</th><th>13</th><th>12</th><th>11</th><th>10</th><th>9</th><th>8</th><th>7</th><th>6</th><th>5</th><th>4</th><th>3</th><th>2</th><th>1</th><th>0</th></tr></thead><tbody><tr><td><code>1</code></td><td><code>1</code></td><td><code>1</code></td><td><code>1</code></td><td><code>0</code></td><td><code>0</code></td><td><code>0</code></td><td><code>1</code></td><td colspan="8"><var>offset</var><br>8b signed int</td></tr></tbody></table><h4>Assembler syntax</h4><p><code class="asm"><span class="mnemonic">bnz</span> <var>offset</var></code></p><h4>Pseudocode</h4><p><code class="pseudocode"><span class="keyword">if</span> !zero: Pc += <var>offset</var></code></p></section><section id="instruction-bc"><h3>bc: Branch if carry</h3><h4>Encoding</h4><table class="encoding"><thead><tr><th>15</th><th>14</th><th>13</th><th>12</th><th>11</th><th>10</th><th>9</th><th>8</th><th>7</th><th>6</th><th>5</th><th>4</th><th>3</th><th>2</th><th>1</th><th>0</th></tr></thead><tbody><tr><td><code>1</code></td><td><code>1</code></td><td><code>1</code></td><td><code>1</code></td><td><code>0</code></td><td><code>0</code></td><td><code>1</code></td><td><code>0</code></td><td colspan="8"><var>offset</var><br>8b signed int</td></tr></tbody></table><h4>Assembler syntax</h4><p><code class="asm"><span class="mnemonic">bc</span> <var>offset</var></code></p><h4>Pseudocode</h4><p><code class="pseudocode"><span class="keyword">if</span> carry: Pc += <var>offset</var></code></p></section><section id="instruction-bnc"><h3>bnc: Branch if not carry</h3><h4>Encoding</h4><table class="encoding"><thead><tr><th>15</th><th>14</th><th>13</th><th>12</th><th>11</th><th>10</th><th>9</th><th>8</th><th>7</th><th>6</th><th>5</th><th>4</th><th>3</th><th>2</th><th>1</th><th>0</th></tr></thead><tbody><tr><td><code>1</code></td><td><code>1</code></td><td><code>1</code></td><td><code>1</code></td><td><code>0</code></td><td><code>0</code></td><td><code>1</code></td><td><code>1</code></td><td colspan="8"><var>offset</var><br>8b signed int</td></tr></tbody></table><h4>Assembler syntax</h4><p><code class="asm"><span class="mnemonic">bnc</span> <var>offset</var></code></p><h4>Pseudocode</h4><p><code class="pseudocode"><span class="keyword">if</span> !carry: Pc += <var>offset</var></code></p></section><section id="instruction-bn"><h3>bn: Branch if negative</h3><h4>Encoding</h4><table class="encoding"><thead><tr><th>15</th><th>14</th><th>13</th><th>12</th><th>11</th><th>10</th><th>9</th><th>8</th><th>7</th><th>6</th><th>5</th><th>4</th><th>3</th><th>2</th><th>1</th><th>0</th></tr></thead><tbody><tr><td><code>1</code></td><td><code>1</code></td><td><code>1</code></td><td><code>1</code></td><td><code>0</code></td><td><code>1</code></td><td><code>0</code></td><td><code>0</code></td><td colspan="8"><var>offset</var><br>8b signed int</td></tr></tbody></table><h4>Assembler syntax</h4><p><code class="asm"><span class="mnemonic">bn</span> <var>offset</var></code></p><h4>Pseudocode</h4><p><code class="pseudocode"><span class="keyword">if</span> negative: Pc += <var>offset</var></code></p></section><section id="instruction-bnn"><h3>bnn: Branch if not negative</h3><h4>Encoding</h4><table class="encoding"><thead><tr><th>15</th><th>14</th><th>13</th><th>12</th><th>11</th><th>10</th><th>9</th><th>8</th><th>7</th><th>6</th><th>5</th><th>4</th><th>3</th><th>2</th><th>1</th><th>0</th></tr></thead><tbody><tr><td><code>1</code></td><td><code>1</code></td><td><code>1</code></td><td><code>1</code></td><td><code>0</code></td><td><code>1</code></td><td><code>0</code></td><td><code>1</code></td><td colspan="8"><var>offset</var><br>8b signed int</td></tr></tbody></table><h4>Assembler syntax</h4><p><code class="asm"><span class="mnemonic">bnn</span> <var>offset</var></code></p><h4>Pseudocode</h4><p><code class="pseudocode"><span class="keyword">if</span> !negative: Pc += <var>offset</var></code></p></section><section id="instruction-bo"><h3>bo: Branch if overflow</h3><h4>Encoding</h4><table class="encoding"><thead><tr><th>15</th><th>14</th><th>13</th><th>12</th><th>11</th><th>10</th><th>9</th><th>8</th><th>7</th><th>6</th><th>5</th><th>4</th><th>3</th><th>2</th><th>1</th><th>0</th></tr></thead><tbody><tr><td><code>1</code></td><td><code>1</code></td><td><code>1</code></td><td><code>1</code></td><td><code>0</code></td><td><code>1</code></td><td><code>1</code></td><td><code>0</code></td><td colspan="8"><var>offset</var><br>8b signed int</td></tr></tbody></table><h4>Assembler syntax</h4><p><code class="asm"><span class="mnemonic">bo</span> <var>offset</var></code></p><h4>Pseudocode</h4><p><code class="pseudocode"><span class="keyword">if</span> overflow: Pc += <var>offset</var></code></p></section><section id="instruction-bno"><h3>bno: Branch if not overflow</h3><h4>Encoding</h4><table class="encoding"><thead><tr><th>15</th><th>14</th><th>13</th><th>12</th><th>11</th><th>10</th><th>9</th><th>8</th><th>7</th><th>6</th><th>5</th><th>4</th><th>3</th><th>2</th><th>1</th><th>0</th></tr></thead><tbody><tr><td><code>1</code></td><td><code>1</code></td><td><code>1</code></td><td><code>1</code></td><td><code>0</code></td><td><code>1</code></td><td><code>1</code></td><td><code>1</code></td><td colspan="8"><var>offset</var><br>8b signed int</td></tr></tbody></table><h4>Assembler syntax</h4><p><code class="asm"><span class="mnemonic">bno</span> <var>offset</var></code></p><h4>Pseudocode</h4><p><code class="pseudocode"><span class="keyword">if</span> !overflow: Pc += <var>offset</var></code></p></section><section id="instruction-syscall"><h3>syscall: Syscall</h3><h4>Encoding</h4><table class="encoding"><thead><tr><th>15</th><th>14</th><th>13</th><th>12</th><th>11</th><th>10</th><th>9</th><th>8</th><th>7</th><th>6</th><th>5</th><th>4</th><th>3</th><th>2</th><th>1</th><th>0</th></tr></thead><tbody><tr><td><code>1</code></td><td><code>1</code></td><td><code>1</code></td><td><code>1</code></td><td><code>1</code></td><td><code>0</code></td><td><code>0</code></td><td><code>0</code></td><td colspan="8"><var>code</var><br>8b unsigned int</td></tr></tbody></table><h4>Assembler syntax</h4><p><code class="asm"><span class="mnemonic">syscall</span> <var>code</var></code></p></section><section id="instruction-ja"><h3>ja: Absolute jump</h3><h4>Encoding</h4><table class="encoding"><thead><tr><th>15</th><th>14</th><th>13</th><th>12</th><th>11</th><th>10</th><th>9</th><th>8</th><th>7</th><th>6</th><th>5</th><th>4</th><th>3</th><th>2</th><th>1</th><th>0</th></tr></thead><tbody><tr><td><code>1</code></td><td><code>1</code></td><td><code>1</code></td><td><code>1</code></td><td><code>1</code></td><td><code>0</code></td><td><code>0</code></td><td><code>1</code></td><td class="placeholder" colspan="4"></td><td colspan="4"><var>address</var><br>register</td></tr></tbody></table><h4>Assembler syntax</h4><p><code class="asm"><span class="mnemonic">ja</span> <var>address</var></code></p><h4>Pseudocode</h4><p><code class="pseudocode">Pc = <var>address</var></code></p></section><section id="instruction-jla"><h3>jla: Absolute jump and link</h3><h4>Encoding</h4><table class="encoding"><thead><tr><th>15</th><th>14</th><th>13</th><th>12</th><th>11</th><th>10</th><th>9</th><th>8</th><th>7</th><th>6</th><th>5</th><th>4</th><th>3</th><th>2</th><th>1</th><th>0</th></tr></thead><tbody><tr><td><code>1</code></td><td><code>1</code></td><td><code>1</code></td><td><code>1</code></td><td><code>1</code></td><td><code>0</code></td><td><code>1</code></td><td><code>0</code></td><td class="placeholder" colspan="4"></td><td colspan="4"><var>address</var><br>register</td></tr></tbody></table><h4>Assembler syntax</h4><p><code class="asm"><span class="mnemonic">jla</span> <var>address</var></code></p><h4>Pseudocode</h4><p><code class="pseudocode">r1 = Pc
Pc = <var>address</var></code></p></section><section id="instruction-ldp"><h3>ldp: Load from program memory</h3><h4>Encoding</h4><table class="encoding"><thead><tr><th>15</th><th>14</th><th>13</th><th>12</th><th>11</th><th>10</th><th>9</th><th>8</th><th>7</th><th>6</th><th>5</th><th>4</th><th>3</th><th>2</th><th>1</th><th>0</th></tr></thead><tbody><tr><td><code>1</code></td><td><code>1</code></td><td><code>1</code></td><td><code>1</code></td><td><code>1</code></td><td><code>0</code></td><td><code>1</code></td><td><code>1</code></td><td colspan="4"><var>address</var><br>register</td><td colspan="4"><var>rd</var><br>register</td></tr></tbody></table><h4>Assembler syntax</h4><p><code class="asm"><span class="mnemonic">ldp</span> <var>rd</var>, <var>address</var></code></p><h4>Pseudocode</h4><p><code class="pseudocode"><var>rd</var> = program_memory[<var>address</var>]</code></p></section><section id="instruction-st_cond"><h3>st_cond: Store to memory conditional</h3><h4>Encoding</h4><table class="encoding"><thead><tr><th>15</th><th>14</th><th>13</th><th>12</th><th>11</th><th>10</th><th>9</th><th>8</th><th>7</th><th>6</th><th>5</th><th>4</th><th>3</th><th>2</th><th>1</th><th>0</th></tr></thead><tbody><tr><td><code>1</code></td><td><code>1</code></td><td><code>1</code></td><td><code>1</code></td><td><code>1</code></td><td><code>1</code></td><td><code>0</code></td><td><code>0</code></td><td colspan="4"><var>address</var><br>register</td><td colspan="4"><var>rs</var><br>register</td></tr></tbody></table><h4>Assembler syntax</h4><p><code class="asm"><span class="mnemonic">st_cond</span> <var>address</var>, <var>rs</var></code></p></section><section id="instruction-reti"><h3>reti: Return from interrupt</h3><h4>Encoding</h4><table class="encoding"><thead><tr><th>15</th><th>14</th><th>13</th><th>12</th><th>11</th><th>10</th><th>9</th><th>8</th><th>7</th><th>6</th><th>5</th><th>4</th><th>3</th><th>2</th><th>1</th><th>0</th></tr></thead><tbody><tr><td><code>1</code></td><td><code>1</code></td><td><code>1</code></td><td><code>1</code></td><td><code>1</code></td><td><code>1</code></td><td><code>0</code></td><td><code>1</code></td><td class="placeholder" colspan="8"></td></tr></tbody></table><h4>Assembler syntax</h4><p><code class="asm"><span class="mnemonic">reti</span> </code></p></section><section id="instruction-break"><h3>break: Break</h3><h4>Encoding</h4><table class="encoding"><thead><tr><th>15</th><th>14</th><th>13</th><th>12</th><th>11</th><th>10</th><th>9</th><th>8</th><th>7</th><th>6</th><th>5</th><th>4</th><th>3</th><th>2</th><th>1</th><th>0</th></tr></thead><tbody><tr><td><code>1</code></td><td><code>1</code></td><td><code>1</code></td><td><code>1</code></td><td><code>1</code></td><td><code>1</code></td><td><code>1</code></td><td><code>1</code></td><td class="placeholder" colspan="8"></td></tr></tbody></table><h4>Assembler syntax</h4><p><code class="asm"><span class="mnemonic">break</span> </code></p></section></section></body>