This repository has been archived by the owner on Jun 25, 2023. It is now read-only.
-
Notifications
You must be signed in to change notification settings - Fork 0
/
signed4bits_3funCal_disAddSubMul.v
127 lines (104 loc) · 3.27 KB
/
signed4bits_3funCal_disAddSubMul.v
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
//=======================================================
// This code is generated by Terasic System Builder
//=======================================================
module signed4bits_3funCal_disAddSubMul(
//////////// SEG7 //////////
output [7:0] HEX0,
output [7:0] HEX1,
output [7:0] HEX2,
output [7:0] HEX3,
output [7:0] HEX4,
output [7:0] HEX5,
//////////// KEY //////////
input [1:0] KEY,
//////////// LED //////////
output [9:0] LEDR,
//////////// SW //////////
input [9:0] SW
);
//=======================================================
// REG/WIRE declarations
//=======================================================
// this is signed 4bits adder/substractor/multiplier
wire signed [4:0] numA, numB; // for calculation
wire [3:0] numA_ten, numA_digit; // for display
wire [3:0] numB_ten, numB_digit;
wire signed [5:0] num_Add, num_Sub;
wire [3:0] num_Add_ten, num_Add_digit;
wire [3:0] num_Sub_ten, num_Sub_digit;
wire signed [9:0] num_Mul;
wire [3:0] num_Mul_hundred, num_Mul_ten, num_Mul_digit;
reg [3:0] digit0, digit1, digit2, digit3, digit4, digit5;
//=======================================================
// Structural coding
//=======================================================
/*
KEY0 | UNPRESSED | PRESSED | UNPRESSED | PRESSED |
KEY1 | UNPRESSED | UNPRESSED | PRESSED | PRESSED |
FUNC | DISPLAY | ADD | SUB | MUL |
*/
assign numA = SW[4]?32-SW[3:0]:SW[3:0];
assign numB = SW[9]?32-SW[8:5]:SW[9:5];
assign numA_digit = SW[3:0]%10;
assign numA_ten = SW[3:0]/10;
assign numB_digit = SW[8:5]%10;
assign numB_ten = SW[8:5]/10;
assign num_Add = numB + numA;
assign num_Sub = numB - numA;
assign num_Mul = numB * numA;
assign num_Add_ten = num_Add[5]?(32-num_Add[4:0])/10:num_Add/10;
assign num_Add_digit = num_Add[5]?(32-num_Add[4:0])%10:num_Add%10;
assign num_Sub_ten = num_Sub[5]?(32-num_Sub[4:0])/10:num_Sub/10;
assign num_Sub_digit = num_Sub[5]?(32-num_Sub[4:0])%10:num_Sub%10;
assign num_Mul_hundred = num_Mul[9]?(512-num_Mul[8:0])/100:num_Mul/100;
assign num_Mul_ten = num_Mul[9]?((512-num_Mul[8:0])%100)/10:(num_Mul%100)/10;
assign num_Mul_digit = num_Mul[9]?((512-num_Mul[8:0])%100)%10:(num_Mul%100)%10;
always @(KEY[0] or KEY[1])
begin
if (KEY[0] && KEY[1]) // input mode: not pressed key 0,1
begin
digit5 = SW[9]?4'hf:4'he;
digit4 = numB_ten;
digit3 = numB_digit;
digit2 = SW[4]?4'hf:4'he;
digit1 = numA_ten;
digit0 = numA_digit;
end
else if (!KEY[0] && KEY[1]) // add mode: pressed key 0
begin
digit5 = 4'he;
digit4 = 4'he;
digit3 = 4'he;
digit2 = num_Add[5]?4'hf:4'he;
digit1 = num_Add_ten;
digit0 = num_Add_digit;
end
else if (KEY[0] && !KEY[1]) // sub mode: pressed key 1
begin
digit5 = 4'he;
digit4 = 4'he;
digit3 = 4'he;
digit2 = num_Sub[5]?4'hf:4'he;
digit1 = num_Sub_ten;
digit0 = num_Sub_digit;
end
else if (!KEY[0] && !KEY[1]) // mul mode: pressed key 0,1
begin
digit5 = 4'he;
digit4 = 4'he;
digit3 = num_Mul[9]?4'hf:4'he;
digit2 = num_Mul_hundred;
digit1 = num_Mul_ten;
digit0 = num_Mul_digit;
end
end
SEG7_LUT_6 u_seg(
.oSEG0(HEX0),
.oSEG1(HEX1),
.oSEG2(HEX2),
.oSEG3(HEX3),
.oSEG4(HEX4),
.oSEG5(HEX5),
.iDIG ({ digit5, digit4, digit3, digit2, digit1, digit0})
);
endmodule