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finalProject.pow.rpt
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PowerPlay Power Analyzer report for finalProject
Tue Apr 19 12:52:53 2016
Quartus II 64-Bit Version 15.0.0 Build 145 04/22/2015 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Parallel Compilation
3. PowerPlay Power Analyzer Summary
4. PowerPlay Power Analyzer Settings
5. Indeterminate Toggle Rates
6. Operating Conditions Used
7. Thermal Power Dissipation by Block
8. Thermal Power Dissipation by Block Type
9. Thermal Power Dissipation by Hierarchy
10. Core Dynamic Thermal Power Dissipation by Clock Domain
11. Current Drawn from Voltage Supplies Summary
12. VCCIO Supply Current Drawn by I/O Bank
13. VCCIO Supply Current Drawn by Voltage
14. Confidence Metric Details
15. Signal Activities
16. PowerPlay Power Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, the Altera Quartus II License Agreement,
the Altera MegaCore Function License Agreement, or other
applicable license agreement, including, without limitation,
that your use is for the sole purpose of programming logic
devices manufactured by Altera and sold by Altera or its
authorized distributors. Please refer to the applicable
agreement for further details.
+------------------------------------------+
; Parallel Compilation ;
+----------------------------+-------------+
; Processors ; Number ;
+----------------------------+-------------+
; Number detected on machine ; 8 ;
; Maximum allowed ; 4 ;
; ; ;
; Average used ; 1.00 ;
; Maximum used ; 4 ;
; ; ;
; Usage by Processor ; % Time Used ;
; Processor 1 ; 100.0% ;
; Processors 2-4 ; < 0.1% ;
; Processors 5-8 ; 0.0% ;
+----------------------------+-------------+
+-------------------------------------------------------------------------------------------+
; PowerPlay Power Analyzer Summary ;
+----------------------------------------+--------------------------------------------------+
; PowerPlay Power Analyzer Status ; Successful - Tue Apr 19 12:52:53 2016 ;
; Quartus II 64-Bit Version ; 15.0.0 Build 145 04/22/2015 SJ Full Version ;
; Revision Name ; finalProject ;
; Top-level Entity Name ; finalProjectTopLevel ;
; Family ; Cyclone IV E ;
; Device ; EP4CE115F29C7 ;
; Power Models ; Final ;
; Total Thermal Power Dissipation ; 167.71 mW ;
; Core Dynamic Thermal Power Dissipation ; 1.16 mW ;
; Core Static Thermal Power Dissipation ; 101.96 mW ;
; I/O Thermal Power Dissipation ; 64.59 mW ;
; Power Estimation Confidence ; Low: user provided insufficient toggle rate data ;
+----------------------------------------+--------------------------------------------------+
+------------------------------------------------------------------------------------------------------------------------------------+
; PowerPlay Power Analyzer Settings ;
+----------------------------------------------------------------------------+---------------------------------------+---------------+
; Option ; Setting ; Default Value ;
+----------------------------------------------------------------------------+---------------------------------------+---------------+
; Use smart compilation ; Off ; Off ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
; Enable compact report table ; Off ; Off ;
; Default Power Input I/O Toggle Rate ; 12.5% ; 12.5% ;
; Preset Cooling Solution ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; ;
; Board thermal model ; None (CONSERVATIVE) ; ;
; Default Power Toggle Rate ; 12.5% ; 12.5% ;
; Use vectorless estimation ; On ; On ;
; Use Input Files ; Off ; Off ;
; Filter Glitches in VCD File Reader ; On ; On ;
; Power Analyzer Report Signal Activity ; Off ; Off ;
; Power Analyzer Report Power Dissipation ; Off ; Off ;
; Device Power Characteristics ; TYPICAL ; TYPICAL ;
; Automatically Compute Junction Temperature ; On ; On ;
; Specified Junction Temperature ; 25 ; 25 ;
; Ambient Temperature ; 25 ; 25 ;
; Use Custom Cooling Solution ; Off ; Off ;
; Board Temperature ; 25 ; 25 ;
+----------------------------------------------------------------------------+---------------------------------------+---------------+
+----------------------------------------------------------------------------------------------------------------------------------------------+
; Indeterminate Toggle Rates ;
+----------------------------------------------------------------------------------------------------------------+-----------------------------+
; Node ; Reason ;
+----------------------------------------------------------------------------------------------------------------+-----------------------------+
; nios_system:nios_system|nios_system_sdram_pll:sdram_pll|nios_system_sdram_pll_altpll_lqa2:sd1|wire_pll7_clk[0] ; No valid clock domain found ;
; nios_system:nios_system|nios_system_sdram_pll:sdram_pll|nios_system_sdram_pll_altpll_lqa2:sd1|wire_pll7_clk[1] ; No valid clock domain found ;
; KEY[1] ; No valid clock domain found ;
; KEY[2] ; No valid clock domain found ;
; OTG_INT ; No valid clock domain found ;
; OTG_DATA[0] ; No valid clock domain found ;
; OTG_DATA[1] ; No valid clock domain found ;
; OTG_DATA[2] ; No valid clock domain found ;
; OTG_DATA[3] ; No valid clock domain found ;
; OTG_DATA[4] ; No valid clock domain found ;
; OTG_DATA[5] ; No valid clock domain found ;
; OTG_DATA[6] ; No valid clock domain found ;
; OTG_DATA[7] ; No valid clock domain found ;
; OTG_DATA[8] ; No valid clock domain found ;
; OTG_DATA[9] ; No valid clock domain found ;
; OTG_DATA[10] ; No valid clock domain found ;
; OTG_DATA[11] ; No valid clock domain found ;
; OTG_DATA[12] ; No valid clock domain found ;
; OTG_DATA[13] ; No valid clock domain found ;
; OTG_DATA[14] ; No valid clock domain found ;
; OTG_DATA[15] ; No valid clock domain found ;
; DRAM_DQ[0] ; No valid clock domain found ;
; DRAM_DQ[1] ; No valid clock domain found ;
; DRAM_DQ[2] ; No valid clock domain found ;
; DRAM_DQ[3] ; No valid clock domain found ;
; DRAM_DQ[4] ; No valid clock domain found ;
; DRAM_DQ[5] ; No valid clock domain found ;
; DRAM_DQ[6] ; No valid clock domain found ;
; DRAM_DQ[7] ; No valid clock domain found ;
; DRAM_DQ[8] ; No valid clock domain found ;
; DRAM_DQ[9] ; No valid clock domain found ;
; DRAM_DQ[10] ; No valid clock domain found ;
; DRAM_DQ[11] ; No valid clock domain found ;
; DRAM_DQ[12] ; No valid clock domain found ;
; DRAM_DQ[13] ; No valid clock domain found ;
; DRAM_DQ[14] ; No valid clock domain found ;
; DRAM_DQ[15] ; No valid clock domain found ;
; DRAM_DQ[16] ; No valid clock domain found ;
; DRAM_DQ[17] ; No valid clock domain found ;
; DRAM_DQ[18] ; No valid clock domain found ;
; DRAM_DQ[19] ; No valid clock domain found ;
; DRAM_DQ[20] ; No valid clock domain found ;
; DRAM_DQ[21] ; No valid clock domain found ;
; DRAM_DQ[22] ; No valid clock domain found ;
; DRAM_DQ[23] ; No valid clock domain found ;
; DRAM_DQ[24] ; No valid clock domain found ;
; DRAM_DQ[25] ; No valid clock domain found ;
; DRAM_DQ[26] ; No valid clock domain found ;
; DRAM_DQ[27] ; No valid clock domain found ;
; DRAM_DQ[28] ; No valid clock domain found ;
; DRAM_DQ[29] ; No valid clock domain found ;
; DRAM_DQ[30] ; No valid clock domain found ;
; DRAM_DQ[31] ; No valid clock domain found ;
; KEY[0] ; No valid clock domain found ;
; CLOCK_50 ; No valid clock domain found ;
; KEY[3] ; No valid clock domain found ;
+----------------------------------------------------------------------------------------------------------------+-----------------------------+
+-------------------------------------------------------------------------+
; Operating Conditions Used ;
+---------------------------------------------+---------------------------+
; Setting ; Value ;
+---------------------------------------------+---------------------------+
; Device power characteristics ; Typical ;
; ; ;
; Voltages ; ;
; VCCINT ; 1.20 V ;
; VCCA ; 2.50 V ;
; VCCD ; 1.20 V ;
; 2.5 V I/O Standard ; 2.5 V ;
; ; ;
; Auto computed junction temperature ; 26.1 degrees Celsius ;
; Ambient temperature ; 25.0 degrees Celsius ;
; Junction-to-Case thermal resistance ; 3.90 degrees Celsius/Watt ;
; Case-to-Heat Sink thermal resistance ; 0.10 degrees Celsius/Watt ;
; Heat Sink-to-Ambient thermal resistance ; 2.50 degrees Celsius/Watt ;
; ; ;
; Board model used ; None ;
+---------------------------------------------+---------------------------+
+----------------------------------------------------------------------------------------------------------------------------------------------+
; Thermal Power Dissipation by Block ;
+------------+------------+---------------------+-----------------------------+--------------------------------+-------------------------------+
; Block Name ; Block Type ; Total Thermal Power ; Block Thermal Dynamic Power ; Block Thermal Static Power (1) ; Routing Thermal Dynamic Power ;
+------------+------------+---------------------+-----------------------------+--------------------------------+-------------------------------+
(1) The "Thermal Power Dissipation by Block" Table has been hidden. To show this table, please select the "Write power dissipation by block to report file" option under "PowerPlay Power Analyzer Settings".
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Thermal Power Dissipation by Block Type ;
+---------------------+-----------------------------------+-----------------------------+--------------------------------+-------------------------------+-----------------------------------------------------------+
; Block Type ; Total Thermal Power by Block Type ; Block Thermal Dynamic Power ; Block Thermal Static Power (1) ; Routing Thermal Dynamic Power ; Block Average Toggle Rate (millions of transitions / sec) ;
+---------------------+-----------------------------------+-----------------------------+--------------------------------+-------------------------------+-----------------------------------------------------------+
; JTAG ; 0.02 mW ; 0.00 mW ; -- ; 0.02 mW ; 6.875 ;
; PLL ; 0.00 mW ; 0.00 mW ; -- ; 0.00 mW ; 0.000 ;
; M9K ; 0.00 mW ; 0.00 mW ; -- ; 0.00 mW ; 0.069 ;
; Combinational cell ; 0.07 mW ; 0.05 mW ; -- ; 0.02 mW ; 0.097 ;
; Clock control block ; 0.82 mW ; 0.00 mW ; -- ; 0.82 mW ; 2.000 ;
; Register cell ; 0.25 mW ; 0.16 mW ; -- ; 0.09 mW ; 0.141 ;
; I/O register ; 0.00 mW ; 0.00 mW ; -- ; 0.00 mW ; 0.000 ;
; I/O ; 34.59 mW ; 0.08 mW ; 34.52 mW ; 0.00 mW ; 0.201 ;
+---------------------+-----------------------------------+-----------------------------+--------------------------------+-------------------------------+-----------------------------------------------------------+
(1) The "Block Thermal Static Power" for all block types except Pins and the Voltage Regulator, if one exists, is part of the "Core Static Thermal Power Dissipation" value found on the PowerPlay Power Analyzer-->Summary report panel. The "Core Static Thermal Power Dissipation" also contains the thermal static power dissipated by the routing.
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Thermal Power Dissipation by Hierarchy ;
+------------------------------------------------------------------------------------------------------------------------------+--------------------------------------+---------------------------------+-----------------------------------+-----------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Compilation Hierarchy Node ; Total Thermal Power by Hierarchy (1) ; Block Thermal Dynamic Power (1) ; Block Thermal Static Power (1)(2) ; Routing Thermal Dynamic Power (1) ; Full Hierarchy Name ;
+------------------------------------------------------------------------------------------------------------------------------+--------------------------------------+---------------------------------+-----------------------------------+-----------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; |finalProjectTopLevel ; 35.75 mW (35.43 mW) ; 0.29 mW (0.08 mW) ; 34.52 mW (34.52 mW) ; 0.95 mW (0.83 mW) ; |finalProjectTopLevel ;
; |hard_block:auto_generated_inst ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|hard_block:auto_generated_inst ;
; |sld_hub:auto_hub ; 0.15 mW (0.00 mW) ; 0.11 mW (0.00 mW) ; -- ; 0.05 mW (0.00 mW) ; |finalProjectTopLevel|sld_hub:auto_hub ;
; |alt_sld_fab:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:instrumentation_fabric ; 0.15 mW (0.00 mW) ; 0.11 mW (0.00 mW) ; -- ; 0.05 mW (0.00 mW) ; |finalProjectTopLevel|sld_hub:auto_hub|alt_sld_fab:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:instrumentation_fabric ;
; |alt_sld_fab_alt_sld_fab:alt_sld_fab ; 0.15 mW (0.01 mW) ; 0.11 mW (0.00 mW) ; -- ; 0.05 mW (0.00 mW) ; |finalProjectTopLevel|sld_hub:auto_hub|alt_sld_fab:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab ;
; |alt_sld_fab_alt_sld_fab_sldfabric:sldfabric ; 0.15 mW (0.00 mW) ; 0.10 mW (0.00 mW) ; -- ; 0.04 mW (0.00 mW) ; |finalProjectTopLevel|sld_hub:auto_hub|alt_sld_fab:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric ;
; |sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub ; 0.15 mW (0.11 mW) ; 0.10 mW (0.07 mW) ; -- ; 0.04 mW (0.03 mW) ; |finalProjectTopLevel|sld_hub:auto_hub|alt_sld_fab:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub ;
; |sld_rom_sr:hub_info_reg ; 0.01 mW (0.01 mW) ; 0.01 mW (0.01 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|sld_hub:auto_hub|alt_sld_fab:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|sld_rom_sr:hub_info_reg ;
; |sld_shadow_jsm:shadow_jsm ; 0.03 mW (0.03 mW) ; 0.02 mW (0.02 mW) ; -- ; 0.01 mW (0.01 mW) ; |finalProjectTopLevel|sld_hub:auto_hub|alt_sld_fab:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|sld_shadow_jsm:shadow_jsm ;
; |sld_jtag_interface_mod:\jtag_interface_mod_gen:device_family_mod_inst ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|sld_hub:auto_hub|sld_jtag_interface_mod:\jtag_interface_mod_gen:device_family_mod_inst ;
; |Color_Mapper8Bit:color_instance ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|Color_Mapper8Bit:color_instance ;
; |GameController:gameControllerInst ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|GameController:gameControllerInst ;
; |HexDriver:hex_inst_0 ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|HexDriver:hex_inst_0 ;
; |HexDriver:hex_inst_1 ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|HexDriver:hex_inst_1 ;
; |hpi_io_intf:hpi_io_inst ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|hpi_io_intf:hpi_io_inst ;
; |nios_system:nios_system ; 0.18 mW (0.00 mW) ; 0.11 mW (0.00 mW) ; -- ; 0.07 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system ;
; |nios_system_jtag_uart_0:jtag_uart_0 ; 0.06 mW (0.00 mW) ; 0.04 mW (0.00 mW) ; -- ; 0.02 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_jtag_uart_0:jtag_uart_0 ;
; |alt_jtag_atlantic:nios_system_jtag_uart_0_alt_jtag_atlantic ; 0.06 mW (0.06 mW) ; 0.04 mW (0.04 mW) ; -- ; 0.02 mW (0.02 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:nios_system_jtag_uart_0_alt_jtag_atlantic ;
; |altera_sld_agent_endpoint:inst ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:nios_system_jtag_uart_0_alt_jtag_atlantic|altera_sld_agent_endpoint:inst ;
; |nios_system_jtag_uart_0_scfifo_r:the_nios_system_jtag_uart_0_scfifo_r ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_jtag_uart_0:jtag_uart_0|nios_system_jtag_uart_0_scfifo_r:the_nios_system_jtag_uart_0_scfifo_r ;
; |scfifo:rfifo ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_jtag_uart_0:jtag_uart_0|nios_system_jtag_uart_0_scfifo_r:the_nios_system_jtag_uart_0_scfifo_r|scfifo:rfifo ;
; |scfifo_jr21:auto_generated ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_jtag_uart_0:jtag_uart_0|nios_system_jtag_uart_0_scfifo_r:the_nios_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated ;
; |a_dpfifo_q131:dpfifo ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_jtag_uart_0:jtag_uart_0|nios_system_jtag_uart_0_scfifo_r:the_nios_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo ;
; |a_fefifo_7cf:fifo_state ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_jtag_uart_0:jtag_uart_0|nios_system_jtag_uart_0_scfifo_r:the_nios_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state ;
; |cntr_do7:count_usedw ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_jtag_uart_0:jtag_uart_0|nios_system_jtag_uart_0_scfifo_r:the_nios_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw ;
; |dpram_nl21:FIFOram ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_jtag_uart_0:jtag_uart_0|nios_system_jtag_uart_0_scfifo_r:the_nios_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram ;
; |altsyncram_r1m1:altsyncram1 ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_jtag_uart_0:jtag_uart_0|nios_system_jtag_uart_0_scfifo_r:the_nios_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1 ;
; |cntr_1ob:rd_ptr_count ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_jtag_uart_0:jtag_uart_0|nios_system_jtag_uart_0_scfifo_r:the_nios_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count ;
; |cntr_1ob:wr_ptr ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_jtag_uart_0:jtag_uart_0|nios_system_jtag_uart_0_scfifo_r:the_nios_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr ;
; |nios_system_jtag_uart_0_scfifo_w:the_nios_system_jtag_uart_0_scfifo_w ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_jtag_uart_0:jtag_uart_0|nios_system_jtag_uart_0_scfifo_w:the_nios_system_jtag_uart_0_scfifo_w ;
; |scfifo:wfifo ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_jtag_uart_0:jtag_uart_0|nios_system_jtag_uart_0_scfifo_w:the_nios_system_jtag_uart_0_scfifo_w|scfifo:wfifo ;
; |scfifo_jr21:auto_generated ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_jtag_uart_0:jtag_uart_0|nios_system_jtag_uart_0_scfifo_w:the_nios_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated ;
; |a_dpfifo_q131:dpfifo ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_jtag_uart_0:jtag_uart_0|nios_system_jtag_uart_0_scfifo_w:the_nios_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo ;
; |a_fefifo_7cf:fifo_state ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_jtag_uart_0:jtag_uart_0|nios_system_jtag_uart_0_scfifo_w:the_nios_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state ;
; |cntr_do7:count_usedw ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_jtag_uart_0:jtag_uart_0|nios_system_jtag_uart_0_scfifo_w:the_nios_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw ;
; |dpram_nl21:FIFOram ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_jtag_uart_0:jtag_uart_0|nios_system_jtag_uart_0_scfifo_w:the_nios_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram ;
; |altsyncram_r1m1:altsyncram1 ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_jtag_uart_0:jtag_uart_0|nios_system_jtag_uart_0_scfifo_w:the_nios_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1 ;
; |cntr_1ob:rd_ptr_count ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_jtag_uart_0:jtag_uart_0|nios_system_jtag_uart_0_scfifo_w:the_nios_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count ;
; |cntr_1ob:wr_ptr ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_jtag_uart_0:jtag_uart_0|nios_system_jtag_uart_0_scfifo_w:the_nios_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr ;
; |nios_system_keycode:keycode ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_keycode:keycode ;
; |nios_system_mm_interconnect_0:mm_interconnect_0 ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0 ;
; |nios_system_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|nios_system_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter ;
; |nios_system_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_001 ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|nios_system_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_001 ;
; |nios_system_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_002 ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|nios_system_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_002 ;
; |nios_system_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_003 ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|nios_system_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_003 ;
; |nios_system_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_004 ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|nios_system_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_004 ;
; |nios_system_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_005 ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|nios_system_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_005 ;
; |nios_system_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_006 ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|nios_system_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_006 ;
; |nios_system_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_007 ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|nios_system_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_007 ;
; |nios_system_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_008 ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|nios_system_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_008 ;
; |nios_system_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_009 ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|nios_system_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_009 ;
; |nios_system_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_010 ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|nios_system_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_010 ;
; |nios_system_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_011 ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|nios_system_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_011 ;
; |nios_system_mm_interconnect_0_cmd_demux:cmd_demux ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|nios_system_mm_interconnect_0_cmd_demux:cmd_demux ;
; |nios_system_mm_interconnect_0_cmd_demux_001:cmd_demux_001 ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|nios_system_mm_interconnect_0_cmd_demux_001:cmd_demux_001 ;
; |nios_system_mm_interconnect_0_cmd_mux_001:cmd_mux_001 ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|nios_system_mm_interconnect_0_cmd_mux_001:cmd_mux_001 ;
; |altera_merlin_arbitrator:arb ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|nios_system_mm_interconnect_0_cmd_mux_001:cmd_mux_001|altera_merlin_arbitrator:arb ;
; |nios_system_mm_interconnect_0_cmd_mux_001:cmd_mux_002 ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|nios_system_mm_interconnect_0_cmd_mux_001:cmd_mux_002 ;
; |altera_merlin_arbitrator:arb ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|nios_system_mm_interconnect_0_cmd_mux_001:cmd_mux_002|altera_merlin_arbitrator:arb ;
; |nios_system_mm_interconnect_0_cmd_mux_001:cmd_mux_003 ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|nios_system_mm_interconnect_0_cmd_mux_001:cmd_mux_003 ;
; |altera_merlin_arbitrator:arb ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|nios_system_mm_interconnect_0_cmd_mux_001:cmd_mux_003|altera_merlin_arbitrator:arb ;
; |nios_system_mm_interconnect_0_cmd_mux_001:cmd_mux_004 ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|nios_system_mm_interconnect_0_cmd_mux_001:cmd_mux_004 ;
; |altera_merlin_arbitrator:arb ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|nios_system_mm_interconnect_0_cmd_mux_001:cmd_mux_004|altera_merlin_arbitrator:arb ;
; |nios_system_mm_interconnect_0_cmd_mux_001:cmd_mux_011 ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|nios_system_mm_interconnect_0_cmd_mux_001:cmd_mux_011 ;
; |altera_merlin_arbitrator:arb ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|nios_system_mm_interconnect_0_cmd_mux_001:cmd_mux_011|altera_merlin_arbitrator:arb ;
; |altera_avalon_st_handshake_clock_crosser:crosser ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser ;
; |altera_avalon_st_clock_crosser:clock_xer ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer ;
; |altera_std_synchronizer:in_to_out_synchronizer ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer ;
; |altera_std_synchronizer:out_to_in_synchronizer ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:out_to_in_synchronizer ;
; |altera_avalon_st_handshake_clock_crosser:crosser_001 ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser_001 ;
; |altera_avalon_st_clock_crosser:clock_xer ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer ;
; |altera_std_synchronizer:in_to_out_synchronizer ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer ;
; |altera_std_synchronizer:out_to_in_synchronizer ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:out_to_in_synchronizer ;
; |altera_avalon_st_handshake_clock_crosser:crosser_002 ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser_002 ;
; |altera_avalon_st_clock_crosser:clock_xer ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer ;
; |altera_std_synchronizer:in_to_out_synchronizer ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer ;
; |altera_std_synchronizer:out_to_in_synchronizer ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:out_to_in_synchronizer ;
; |altera_avalon_st_handshake_clock_crosser:crosser_003 ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser_003 ;
; |altera_avalon_st_clock_crosser:clock_xer ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer ;
; |altera_std_synchronizer:in_to_out_synchronizer ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer ;
; |altera_std_synchronizer:out_to_in_synchronizer ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:out_to_in_synchronizer ;
; |altera_merlin_slave_agent:jtag_uart_0_avalon_jtag_slave_agent ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:jtag_uart_0_avalon_jtag_slave_agent ;
; |altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo ;
; |altera_merlin_slave_translator:jtag_uart_0_avalon_jtag_slave_translator ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:jtag_uart_0_avalon_jtag_slave_translator ;
; |altera_merlin_slave_agent:keycode_s1_agent ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:keycode_s1_agent ;
; |altera_avalon_sc_fifo:keycode_s1_agent_rsp_fifo ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:keycode_s1_agent_rsp_fifo ;
; |altera_merlin_slave_translator:keycode_s1_translator ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:keycode_s1_translator ;
; |altera_merlin_master_agent:nios2_qsys_0_data_master_agent ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_agent:nios2_qsys_0_data_master_agent ;
; |altera_merlin_master_translator:nios2_qsys_0_data_master_translator ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_translator:nios2_qsys_0_data_master_translator ;
; |altera_merlin_slave_agent:nios2_qsys_0_debug_mem_slave_agent ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:nios2_qsys_0_debug_mem_slave_agent ;
; |altera_avalon_sc_fifo:nios2_qsys_0_debug_mem_slave_agent_rsp_fifo ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:nios2_qsys_0_debug_mem_slave_agent_rsp_fifo ;
; |altera_merlin_slave_translator:nios2_qsys_0_debug_mem_slave_translator ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:nios2_qsys_0_debug_mem_slave_translator ;
; |altera_merlin_master_translator:nios2_qsys_0_instruction_master_translator ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_translator:nios2_qsys_0_instruction_master_translator ;
; |altera_merlin_slave_agent:onchip_memory2_0_s1_agent ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:onchip_memory2_0_s1_agent ;
; |altera_avalon_sc_fifo:onchip_memory2_0_s1_agent_rsp_fifo ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:onchip_memory2_0_s1_agent_rsp_fifo ;
; |altera_merlin_slave_translator:onchip_memory2_0_s1_translator ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:onchip_memory2_0_s1_translator ;
; |altera_merlin_slave_agent:otg_hpi_address_s1_agent ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:otg_hpi_address_s1_agent ;
; |altera_avalon_sc_fifo:otg_hpi_address_s1_agent_rsp_fifo ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:otg_hpi_address_s1_agent_rsp_fifo ;
; |altera_merlin_slave_translator:otg_hpi_address_s1_translator ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:otg_hpi_address_s1_translator ;
; |altera_merlin_slave_agent:otg_hpi_cs_s1_agent ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:otg_hpi_cs_s1_agent ;
; |altera_avalon_sc_fifo:otg_hpi_cs_s1_agent_rsp_fifo ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:otg_hpi_cs_s1_agent_rsp_fifo ;
; |altera_merlin_slave_translator:otg_hpi_cs_s1_translator ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:otg_hpi_cs_s1_translator ;
; |altera_merlin_slave_agent:otg_hpi_data_s1_agent ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:otg_hpi_data_s1_agent ;
; |altera_avalon_sc_fifo:otg_hpi_data_s1_agent_rsp_fifo ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:otg_hpi_data_s1_agent_rsp_fifo ;
; |altera_merlin_slave_translator:otg_hpi_data_s1_translator ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:otg_hpi_data_s1_translator ;
; |altera_merlin_slave_agent:otg_hpi_r_s1_agent ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:otg_hpi_r_s1_agent ;
; |altera_avalon_sc_fifo:otg_hpi_r_s1_agent_rsp_fifo ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:otg_hpi_r_s1_agent_rsp_fifo ;
; |altera_merlin_slave_translator:otg_hpi_r_s1_translator ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:otg_hpi_r_s1_translator ;
; |altera_merlin_slave_agent:otg_hpi_w_s1_agent ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:otg_hpi_w_s1_agent ;
; |altera_avalon_sc_fifo:otg_hpi_w_s1_agent_rsp_fifo ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:otg_hpi_w_s1_agent_rsp_fifo ;
; |altera_merlin_slave_translator:otg_hpi_w_s1_translator ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:otg_hpi_w_s1_translator ;
; |nios_system_mm_interconnect_0_router:router ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|nios_system_mm_interconnect_0_router:router ;
; |nios_system_mm_interconnect_0_router_001:router_001 ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|nios_system_mm_interconnect_0_router_001:router_001 ;
; |nios_system_mm_interconnect_0_router_002:router_002 ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|nios_system_mm_interconnect_0_router_002:router_002 ;
; |nios_system_mm_interconnect_0_router_003:router_003 ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|nios_system_mm_interconnect_0_router_003:router_003 ;
; |nios_system_mm_interconnect_0_router_003:router_004 ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|nios_system_mm_interconnect_0_router_003:router_004 ;
; |nios_system_mm_interconnect_0_router_003:router_005 ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|nios_system_mm_interconnect_0_router_003:router_005 ;
; |nios_system_mm_interconnect_0_router_003:router_006 ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|nios_system_mm_interconnect_0_router_003:router_006 ;
; |nios_system_mm_interconnect_0_router_002:router_007 ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|nios_system_mm_interconnect_0_router_002:router_007 ;
; |nios_system_mm_interconnect_0_router_002:router_008 ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|nios_system_mm_interconnect_0_router_002:router_008 ;
; |nios_system_mm_interconnect_0_router_002:router_009 ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|nios_system_mm_interconnect_0_router_002:router_009 ;
; |nios_system_mm_interconnect_0_router_002:router_010 ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|nios_system_mm_interconnect_0_router_002:router_010 ;
; |nios_system_mm_interconnect_0_router_002:router_011 ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|nios_system_mm_interconnect_0_router_002:router_011 ;
; |nios_system_mm_interconnect_0_router_002:router_012 ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|nios_system_mm_interconnect_0_router_002:router_012 ;
; |nios_system_mm_interconnect_0_router_003:router_013 ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|nios_system_mm_interconnect_0_router_003:router_013 ;
; |nios_system_mm_interconnect_0_rsp_demux_001:rsp_demux_002 ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|nios_system_mm_interconnect_0_rsp_demux_001:rsp_demux_002 ;
; |nios_system_mm_interconnect_0_rsp_demux_001:rsp_demux_003 ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|nios_system_mm_interconnect_0_rsp_demux_001:rsp_demux_003 ;
; |nios_system_mm_interconnect_0_rsp_demux_001:rsp_demux_004 ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|nios_system_mm_interconnect_0_rsp_demux_001:rsp_demux_004 ;
; |nios_system_mm_interconnect_0_rsp_demux_001:rsp_demux_011 ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|nios_system_mm_interconnect_0_rsp_demux_001:rsp_demux_011 ;
; |nios_system_mm_interconnect_0_rsp_mux:rsp_mux ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|nios_system_mm_interconnect_0_rsp_mux:rsp_mux ;
; |altera_merlin_arbitrator:arb ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|nios_system_mm_interconnect_0_rsp_mux:rsp_mux|altera_merlin_arbitrator:arb ;
; |nios_system_mm_interconnect_0_rsp_mux_001:rsp_mux_001 ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|nios_system_mm_interconnect_0_rsp_mux_001:rsp_mux_001 ;
; |altera_merlin_arbitrator:arb ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|nios_system_mm_interconnect_0_rsp_mux_001:rsp_mux_001|altera_merlin_arbitrator:arb ;
; |altera_merlin_slave_agent:sdram_pll_pll_slave_agent ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:sdram_pll_pll_slave_agent ;
; |altera_avalon_sc_fifo:sdram_pll_pll_slave_agent_rsp_fifo ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sdram_pll_pll_slave_agent_rsp_fifo ;
; |altera_merlin_slave_translator:sdram_pll_pll_slave_translator ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:sdram_pll_pll_slave_translator ;
; |altera_merlin_slave_agent:sdram_s1_agent ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:sdram_s1_agent ;
; |altera_avalon_sc_fifo:sdram_s1_agent_rdata_fifo ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sdram_s1_agent_rdata_fifo ;
; |altera_avalon_sc_fifo:sdram_s1_agent_rsp_fifo ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sdram_s1_agent_rsp_fifo ;
; |altera_merlin_slave_agent:sysid_qsys_0_control_slave_agent ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:sysid_qsys_0_control_slave_agent ;
; |altera_avalon_sc_fifo:sysid_qsys_0_control_slave_agent_rsp_fifo ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sysid_qsys_0_control_slave_agent_rsp_fifo ;
; |altera_merlin_slave_translator:sysid_qsys_0_control_slave_translator ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:sysid_qsys_0_control_slave_translator ;
; |nios_system_nios2_qsys_0:nios2_qsys_0 ; 0.11 mW (0.00 mW) ; 0.06 mW (0.00 mW) ; -- ; 0.05 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_nios2_qsys_0:nios2_qsys_0 ;
; |nios_system_nios2_qsys_0_cpu:cpu ; 0.11 mW (0.00 mW) ; 0.06 mW (0.00 mW) ; -- ; 0.05 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_nios2_qsys_0:nios2_qsys_0|nios_system_nios2_qsys_0_cpu:cpu ;
; |nios_system_nios2_qsys_0_cpu_register_bank_a_module:nios_system_nios2_qsys_0_cpu_register_bank_a ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_nios2_qsys_0:nios2_qsys_0|nios_system_nios2_qsys_0_cpu:cpu|nios_system_nios2_qsys_0_cpu_register_bank_a_module:nios_system_nios2_qsys_0_cpu_register_bank_a ;
; |altsyncram:the_altsyncram ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_nios2_qsys_0:nios2_qsys_0|nios_system_nios2_qsys_0_cpu:cpu|nios_system_nios2_qsys_0_cpu_register_bank_a_module:nios_system_nios2_qsys_0_cpu_register_bank_a|altsyncram:the_altsyncram ;
; |altsyncram_6mc1:auto_generated ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_nios2_qsys_0:nios2_qsys_0|nios_system_nios2_qsys_0_cpu:cpu|nios_system_nios2_qsys_0_cpu_register_bank_a_module:nios_system_nios2_qsys_0_cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_6mc1:auto_generated ;
; |nios_system_nios2_qsys_0_cpu_register_bank_b_module:nios_system_nios2_qsys_0_cpu_register_bank_b ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_nios2_qsys_0:nios2_qsys_0|nios_system_nios2_qsys_0_cpu:cpu|nios_system_nios2_qsys_0_cpu_register_bank_b_module:nios_system_nios2_qsys_0_cpu_register_bank_b ;
; |altsyncram:the_altsyncram ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_nios2_qsys_0:nios2_qsys_0|nios_system_nios2_qsys_0_cpu:cpu|nios_system_nios2_qsys_0_cpu_register_bank_b_module:nios_system_nios2_qsys_0_cpu_register_bank_b|altsyncram:the_altsyncram ;
; |altsyncram_6mc1:auto_generated ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_nios2_qsys_0:nios2_qsys_0|nios_system_nios2_qsys_0_cpu:cpu|nios_system_nios2_qsys_0_cpu_register_bank_b_module:nios_system_nios2_qsys_0_cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_6mc1:auto_generated ;
; |nios_system_nios2_qsys_0_cpu_nios2_oci:the_nios_system_nios2_qsys_0_cpu_nios2_oci ; 0.11 mW (0.00 mW) ; 0.06 mW (0.00 mW) ; -- ; 0.05 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_nios2_qsys_0:nios2_qsys_0|nios_system_nios2_qsys_0_cpu:cpu|nios_system_nios2_qsys_0_cpu_nios2_oci:the_nios_system_nios2_qsys_0_cpu_nios2_oci ;
; |nios_system_nios2_qsys_0_cpu_debug_slave_wrapper:the_nios_system_nios2_qsys_0_cpu_debug_slave_wrapper ; 0.07 mW (0.00 mW) ; 0.05 mW (0.00 mW) ; -- ; 0.02 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_nios2_qsys_0:nios2_qsys_0|nios_system_nios2_qsys_0_cpu:cpu|nios_system_nios2_qsys_0_cpu_nios2_oci:the_nios_system_nios2_qsys_0_cpu_nios2_oci|nios_system_nios2_qsys_0_cpu_debug_slave_wrapper:the_nios_system_nios2_qsys_0_cpu_debug_slave_wrapper ;
; |sld_virtual_jtag_basic:nios_system_nios2_qsys_0_cpu_debug_slave_phy ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_nios2_qsys_0:nios2_qsys_0|nios_system_nios2_qsys_0_cpu:cpu|nios_system_nios2_qsys_0_cpu_nios2_oci:the_nios_system_nios2_qsys_0_cpu_nios2_oci|nios_system_nios2_qsys_0_cpu_debug_slave_wrapper:the_nios_system_nios2_qsys_0_cpu_debug_slave_wrapper|sld_virtual_jtag_basic:nios_system_nios2_qsys_0_cpu_debug_slave_phy ;
; |sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_nios2_qsys_0:nios2_qsys_0|nios_system_nios2_qsys_0_cpu:cpu|nios_system_nios2_qsys_0_cpu_nios2_oci:the_nios_system_nios2_qsys_0_cpu_nios2_oci|nios_system_nios2_qsys_0_cpu_debug_slave_wrapper:the_nios_system_nios2_qsys_0_cpu_debug_slave_wrapper|sld_virtual_jtag_basic:nios_system_nios2_qsys_0_cpu_debug_slave_phy|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst ;
; |sld_jtag_endpoint_adapter:jtag_signal_adapter ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_nios2_qsys_0:nios2_qsys_0|nios_system_nios2_qsys_0_cpu:cpu|nios_system_nios2_qsys_0_cpu_nios2_oci:the_nios_system_nios2_qsys_0_cpu_nios2_oci|nios_system_nios2_qsys_0_cpu_debug_slave_wrapper:the_nios_system_nios2_qsys_0_cpu_debug_slave_wrapper|sld_virtual_jtag_basic:nios_system_nios2_qsys_0_cpu_debug_slave_phy|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst|sld_jtag_endpoint_adapter:jtag_signal_adapter ;
; |nios_system_nios2_qsys_0_cpu_debug_slave_sysclk:the_nios_system_nios2_qsys_0_cpu_debug_slave_sysclk ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_nios2_qsys_0:nios2_qsys_0|nios_system_nios2_qsys_0_cpu:cpu|nios_system_nios2_qsys_0_cpu_nios2_oci:the_nios_system_nios2_qsys_0_cpu_nios2_oci|nios_system_nios2_qsys_0_cpu_debug_slave_wrapper:the_nios_system_nios2_qsys_0_cpu_debug_slave_wrapper|nios_system_nios2_qsys_0_cpu_debug_slave_sysclk:the_nios_system_nios2_qsys_0_cpu_debug_slave_sysclk ;
; |altera_std_synchronizer:the_altera_std_synchronizer3 ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_nios2_qsys_0:nios2_qsys_0|nios_system_nios2_qsys_0_cpu:cpu|nios_system_nios2_qsys_0_cpu_nios2_oci:the_nios_system_nios2_qsys_0_cpu_nios2_oci|nios_system_nios2_qsys_0_cpu_debug_slave_wrapper:the_nios_system_nios2_qsys_0_cpu_debug_slave_wrapper|nios_system_nios2_qsys_0_cpu_debug_slave_sysclk:the_nios_system_nios2_qsys_0_cpu_debug_slave_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3 ;
; |altera_std_synchronizer:the_altera_std_synchronizer4 ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_nios2_qsys_0:nios2_qsys_0|nios_system_nios2_qsys_0_cpu:cpu|nios_system_nios2_qsys_0_cpu_nios2_oci:the_nios_system_nios2_qsys_0_cpu_nios2_oci|nios_system_nios2_qsys_0_cpu_debug_slave_wrapper:the_nios_system_nios2_qsys_0_cpu_debug_slave_wrapper|nios_system_nios2_qsys_0_cpu_debug_slave_sysclk:the_nios_system_nios2_qsys_0_cpu_debug_slave_sysclk|altera_std_synchronizer:the_altera_std_synchronizer4 ;
; |nios_system_nios2_qsys_0_cpu_debug_slave_tck:the_nios_system_nios2_qsys_0_cpu_debug_slave_tck ; 0.07 mW (0.07 mW) ; 0.05 mW (0.04 mW) ; -- ; 0.02 mW (0.02 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_nios2_qsys_0:nios2_qsys_0|nios_system_nios2_qsys_0_cpu:cpu|nios_system_nios2_qsys_0_cpu_nios2_oci:the_nios_system_nios2_qsys_0_cpu_nios2_oci|nios_system_nios2_qsys_0_cpu_debug_slave_wrapper:the_nios_system_nios2_qsys_0_cpu_debug_slave_wrapper|nios_system_nios2_qsys_0_cpu_debug_slave_tck:the_nios_system_nios2_qsys_0_cpu_debug_slave_tck ;
; |altera_std_synchronizer:the_altera_std_synchronizer1 ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_nios2_qsys_0:nios2_qsys_0|nios_system_nios2_qsys_0_cpu:cpu|nios_system_nios2_qsys_0_cpu_nios2_oci:the_nios_system_nios2_qsys_0_cpu_nios2_oci|nios_system_nios2_qsys_0_cpu_debug_slave_wrapper:the_nios_system_nios2_qsys_0_cpu_debug_slave_wrapper|nios_system_nios2_qsys_0_cpu_debug_slave_tck:the_nios_system_nios2_qsys_0_cpu_debug_slave_tck|altera_std_synchronizer:the_altera_std_synchronizer1 ;
; |altera_std_synchronizer:the_altera_std_synchronizer2 ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_nios2_qsys_0:nios2_qsys_0|nios_system_nios2_qsys_0_cpu:cpu|nios_system_nios2_qsys_0_cpu_nios2_oci:the_nios_system_nios2_qsys_0_cpu_nios2_oci|nios_system_nios2_qsys_0_cpu_debug_slave_wrapper:the_nios_system_nios2_qsys_0_cpu_debug_slave_wrapper|nios_system_nios2_qsys_0_cpu_debug_slave_tck:the_nios_system_nios2_qsys_0_cpu_debug_slave_tck|altera_std_synchronizer:the_altera_std_synchronizer2 ;
; |nios_system_nios2_qsys_0_cpu_nios2_avalon_reg:the_nios_system_nios2_qsys_0_cpu_nios2_avalon_reg ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_nios2_qsys_0:nios2_qsys_0|nios_system_nios2_qsys_0_cpu:cpu|nios_system_nios2_qsys_0_cpu_nios2_oci:the_nios_system_nios2_qsys_0_cpu_nios2_oci|nios_system_nios2_qsys_0_cpu_nios2_avalon_reg:the_nios_system_nios2_qsys_0_cpu_nios2_avalon_reg ;
; |nios_system_nios2_qsys_0_cpu_nios2_oci_break:the_nios_system_nios2_qsys_0_cpu_nios2_oci_break ; 0.01 mW (0.01 mW) ; 0.01 mW (0.01 mW) ; -- ; 0.01 mW (0.01 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_nios2_qsys_0:nios2_qsys_0|nios_system_nios2_qsys_0_cpu:cpu|nios_system_nios2_qsys_0_cpu_nios2_oci:the_nios_system_nios2_qsys_0_cpu_nios2_oci|nios_system_nios2_qsys_0_cpu_nios2_oci_break:the_nios_system_nios2_qsys_0_cpu_nios2_oci_break ;
; |nios_system_nios2_qsys_0_cpu_nios2_oci_debug:the_nios_system_nios2_qsys_0_cpu_nios2_oci_debug ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_nios2_qsys_0:nios2_qsys_0|nios_system_nios2_qsys_0_cpu:cpu|nios_system_nios2_qsys_0_cpu_nios2_oci:the_nios_system_nios2_qsys_0_cpu_nios2_oci|nios_system_nios2_qsys_0_cpu_nios2_oci_debug:the_nios_system_nios2_qsys_0_cpu_nios2_oci_debug ;
; |altera_std_synchronizer:the_altera_std_synchronizer ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_nios2_qsys_0:nios2_qsys_0|nios_system_nios2_qsys_0_cpu:cpu|nios_system_nios2_qsys_0_cpu_nios2_oci:the_nios_system_nios2_qsys_0_cpu_nios2_oci|nios_system_nios2_qsys_0_cpu_nios2_oci_debug:the_nios_system_nios2_qsys_0_cpu_nios2_oci_debug|altera_std_synchronizer:the_altera_std_synchronizer ;
; |nios_system_nios2_qsys_0_cpu_nios2_oci_dtrace:the_nios_system_nios2_qsys_0_cpu_nios2_oci_dtrace ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_nios2_qsys_0:nios2_qsys_0|nios_system_nios2_qsys_0_cpu:cpu|nios_system_nios2_qsys_0_cpu_nios2_oci:the_nios_system_nios2_qsys_0_cpu_nios2_oci|nios_system_nios2_qsys_0_cpu_nios2_oci_dtrace:the_nios_system_nios2_qsys_0_cpu_nios2_oci_dtrace ;
; |nios_system_nios2_qsys_0_cpu_nios2_oci_fifo:the_nios_system_nios2_qsys_0_cpu_nios2_oci_fifo ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_nios2_qsys_0:nios2_qsys_0|nios_system_nios2_qsys_0_cpu:cpu|nios_system_nios2_qsys_0_cpu_nios2_oci:the_nios_system_nios2_qsys_0_cpu_nios2_oci|nios_system_nios2_qsys_0_cpu_nios2_oci_fifo:the_nios_system_nios2_qsys_0_cpu_nios2_oci_fifo ;
; |nios_system_nios2_qsys_0_cpu_nios2_ocimem:the_nios_system_nios2_qsys_0_cpu_nios2_ocimem ; 0.02 mW (0.02 mW) ; 0.01 mW (0.01 mW) ; -- ; 0.02 mW (0.02 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_nios2_qsys_0:nios2_qsys_0|nios_system_nios2_qsys_0_cpu:cpu|nios_system_nios2_qsys_0_cpu_nios2_oci:the_nios_system_nios2_qsys_0_cpu_nios2_oci|nios_system_nios2_qsys_0_cpu_nios2_ocimem:the_nios_system_nios2_qsys_0_cpu_nios2_ocimem ;
; |nios_system_nios2_qsys_0_cpu_ociram_sp_ram_module:nios_system_nios2_qsys_0_cpu_ociram_sp_ram ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_nios2_qsys_0:nios2_qsys_0|nios_system_nios2_qsys_0_cpu:cpu|nios_system_nios2_qsys_0_cpu_nios2_oci:the_nios_system_nios2_qsys_0_cpu_nios2_oci|nios_system_nios2_qsys_0_cpu_nios2_ocimem:the_nios_system_nios2_qsys_0_cpu_nios2_ocimem|nios_system_nios2_qsys_0_cpu_ociram_sp_ram_module:nios_system_nios2_qsys_0_cpu_ociram_sp_ram ;
; |altsyncram:the_altsyncram ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_nios2_qsys_0:nios2_qsys_0|nios_system_nios2_qsys_0_cpu:cpu|nios_system_nios2_qsys_0_cpu_nios2_oci:the_nios_system_nios2_qsys_0_cpu_nios2_oci|nios_system_nios2_qsys_0_cpu_nios2_ocimem:the_nios_system_nios2_qsys_0_cpu_nios2_ocimem|nios_system_nios2_qsys_0_cpu_ociram_sp_ram_module:nios_system_nios2_qsys_0_cpu_ociram_sp_ram|altsyncram:the_altsyncram ;
; |altsyncram_4a31:auto_generated ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_nios2_qsys_0:nios2_qsys_0|nios_system_nios2_qsys_0_cpu:cpu|nios_system_nios2_qsys_0_cpu_nios2_oci:the_nios_system_nios2_qsys_0_cpu_nios2_oci|nios_system_nios2_qsys_0_cpu_nios2_ocimem:the_nios_system_nios2_qsys_0_cpu_nios2_ocimem|nios_system_nios2_qsys_0_cpu_ociram_sp_ram_module:nios_system_nios2_qsys_0_cpu_ociram_sp_ram|altsyncram:the_altsyncram|altsyncram_4a31:auto_generated ;
; |nios_system_onchip_memory2_0:onchip_memory2_0 ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_onchip_memory2_0:onchip_memory2_0 ;
; |altsyncram:the_altsyncram ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_onchip_memory2_0:onchip_memory2_0|altsyncram:the_altsyncram ;
; |altsyncram_86d1:auto_generated ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_onchip_memory2_0:onchip_memory2_0|altsyncram:the_altsyncram|altsyncram_86d1:auto_generated ;
; |nios_system_otg_hpi_address:otg_hpi_address ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_otg_hpi_address:otg_hpi_address ;
; |nios_system_otg_hpi_cs:otg_hpi_cs ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_otg_hpi_cs:otg_hpi_cs ;
; |nios_system_otg_hpi_data:otg_hpi_data ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_otg_hpi_data:otg_hpi_data ;
; |nios_system_otg_hpi_cs:otg_hpi_r ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_otg_hpi_cs:otg_hpi_r ;
; |nios_system_otg_hpi_cs:otg_hpi_w ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_otg_hpi_cs:otg_hpi_w ;
; |altera_reset_controller:rst_controller ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|altera_reset_controller:rst_controller ;
; |altera_reset_synchronizer:alt_rst_sync_uq1 ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1 ;
; |altera_reset_controller:rst_controller_001 ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|altera_reset_controller:rst_controller_001 ;
; |altera_reset_synchronizer:alt_rst_req_sync_uq1 ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_req_sync_uq1 ;
; |altera_reset_synchronizer:alt_rst_sync_uq1 ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1 ;
; |altera_reset_controller:rst_controller_002 ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|altera_reset_controller:rst_controller_002 ;
; |altera_reset_synchronizer:alt_rst_sync_uq1 ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1 ;
; |nios_system_sdram:sdram ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_sdram:sdram ;
; |nios_system_sdram_input_efifo_module:the_nios_system_sdram_input_efifo_module ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_sdram:sdram|nios_system_sdram_input_efifo_module:the_nios_system_sdram_input_efifo_module ;
; |nios_system_sdram_pll:sdram_pll ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_sdram_pll:sdram_pll ;
; |nios_system_sdram_pll_altpll_lqa2:sd1 ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_sdram_pll:sdram_pll|nios_system_sdram_pll_altpll_lqa2:sd1 ;
; |nios_system_sdram_pll_stdsync_sv6:stdsync2 ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_sdram_pll:sdram_pll|nios_system_sdram_pll_stdsync_sv6:stdsync2 ;
; |nios_system_sdram_pll_dffpipe_l2c:dffpipe3 ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|nios_system:nios_system|nios_system_sdram_pll:sdram_pll|nios_system_sdram_pll_stdsync_sv6:stdsync2|nios_system_sdram_pll_dffpipe_l2c:dffpipe3 ;
; |vga_controller:vgasync_instance ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |finalProjectTopLevel|vga_controller:vgasync_instance ;
+------------------------------------------------------------------------------------------------------------------------------+--------------------------------------+---------------------------------+-----------------------------------+-----------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
(1) Value in parentheses is the power consumed at that level of hierarchy. Value not in parentheses is the power consumed at that level of hierarchy plus the power consumed by all levels of hierarchy below it.
(2) The "Block Thermal Static Power" for all levels of hierarchy except the top-level hierarchy is part of the "Core Static Thermal Power Dissipation" value found on the PowerPlay Power Analyzer-->Summary report panel. The "Core Static Thermal Power Dissipation" also contains the thermal static power dissipated by the routing.
+------------------------------------------------------------------------+
; Core Dynamic Thermal Power Dissipation by Clock Domain ;
+---------------------+-----------------------+--------------------------+
; Clock Domain ; Clock Frequency (MHz) ; Total Core Dynamic Power ;
+---------------------+-----------------------+--------------------------+
; altera_reserved_tck ; 10.00 ; 1.16 ;
; No clock domain ; 0.00 ; 0.00 ;
+---------------------+-----------------------+--------------------------+
+------------------------------------------------------------------------------------------------------------------------------------+
; Current Drawn from Voltage Supplies Summary ;
+----------------+-------------------------+---------------------------+--------------------------+----------------------------------+
; Voltage Supply ; Total Current Drawn (1) ; Dynamic Current Drawn (1) ; Static Current Drawn (1) ; Minimum Power Supply Current (2) ;
+----------------+-------------------------+---------------------------+--------------------------+----------------------------------+
; VCCINT ; 35.48 mA ; 0.98 mA ; 34.51 mA ; 35.48 mA ;
; VCCIO ; 12.46 mA ; 0.02 mA ; 12.44 mA ; 12.46 mA ;
; VCCA ; 35.56 mA ; 0.00 mA ; 35.56 mA ; 35.56 mA ;
; VCCD ; 4.23 mA ; 0.00 mA ; 4.23 mA ; 4.23 mA ;
+----------------+-------------------------+---------------------------+--------------------------+----------------------------------+
(1) Currents reported in columns "Total Current Drawn", "Dynamic Current Drawn", and "Static Current Drawn" are sufficient for user operation of the device.
(2) Currents reported in column "Minimum Power Supply Current" are sufficient for power-up, configuration, and user operation of the device.
+-----------------------------------------------------------------------------------------------+
; VCCIO Supply Current Drawn by I/O Bank ;
+----------+---------------+---------------------+-----------------------+----------------------+
; I/O Bank ; VCCIO Voltage ; Total Current Drawn ; Dynamic Current Drawn ; Static Current Drawn ;
+----------+---------------+---------------------+-----------------------+----------------------+
; 1 ; 2.5V ; 1.62 mA ; 0.02 mA ; 1.59 mA ;
; 2 ; 2.5V ; 1.63 mA ; 0.00 mA ; 1.63 mA ;
; 3 ; 2.5V ; 1.50 mA ; 0.00 mA ; 1.50 mA ;
; 4 ; 2.5V ; 1.50 mA ; 0.00 mA ; 1.50 mA ;
; 5 ; 2.5V ; 1.53 mA ; 0.00 mA ; 1.53 mA ;
; 6 ; 2.5V ; 1.53 mA ; 0.00 mA ; 1.53 mA ;
; 7 ; 2.5V ; 1.51 mA ; 0.00 mA ; 1.51 mA ;
; 8 ; 2.5V ; 1.64 mA ; 0.00 mA ; 1.64 mA ;
+----------+---------------+---------------------+-----------------------+----------------------+
+-----------------------------------------------------------------------------------------------------------------------------------+
; VCCIO Supply Current Drawn by Voltage ;
+---------------+-------------------------+---------------------------+--------------------------+----------------------------------+
; VCCIO Voltage ; Total Current Drawn (1) ; Dynamic Current Drawn (1) ; Static Current Drawn (1) ; Minimum Power Supply Current (2) ;
+---------------+-------------------------+---------------------------+--------------------------+----------------------------------+
; 2.5V ; 12.46 mA ; 0.02 mA ; 12.44 mA ; 12.46 mA ;
+---------------+-------------------------+---------------------------+--------------------------+----------------------------------+
(1) Currents reported in columns "Total Current Drawn", "Dynamic Current Drawn", and "Static Current Drawn" are sufficient for user operation of the device.
(2) Currents reported in column "Minimum Power Supply Current" are sufficient for power-up, configuration, and user operation of the device.
+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; Confidence Metric Details ;
+----------------------------------------------------------------------------------------+--------------+-------------+---------------+---------------+
; Data Source ; Total ; Pin ; Registered ; Combinational ;
+----------------------------------------------------------------------------------------+--------------+-------------+---------------+---------------+
; Simulation (from file) ; ; ; ; ;
; -- Number of signals with Toggle Rate from Simulation ; 0 (0.0%) ; 0 (0.0%) ; 0 (0.0%) ; 0 (0.0%) ;
; -- Number of signals with Static Probability from Simulation ; 0 (0.0%) ; 0 (0.0%) ; 0 (0.0%) ; 0 (0.0%) ;
; ; ; ; ; ;
; Node, entity or clock assignment ; ; ; ; ;
; -- Number of signals with Toggle Rate from Node, entity or clock assignment ; 1 (0.0%) ; 1 (0.5%) ; 0 (0.0%) ; 0 (0.0%) ;
; -- Number of signals with Static Probability from Node, entity or clock assignment ; 1 (0.0%) ; 1 (0.5%) ; 0 (0.0%) ; 0 (0.0%) ;
; ; ; ; ; ;
; Vectorless estimation ; ; ; ; ;
; -- Number of signals with Toggle Rate from Vectorless estimation ; 5922 (99.0%) ; 127 (68.6%) ; 2245 (100.0%) ; 3550 (99.9%) ;
; -- Number of signals with Zero toggle rate, from Vectorless estimation ; 347 (5.8%) ; 11 (5.9%) ; 128 (5.7%) ; 208 (5.9%) ;
; -- Number of signals with Static Probability from Vectorless estimation ; 5922 (99.0%) ; 127 (68.6%) ; 2245 (100.0%) ; 3550 (99.9%) ;
; ; ; ; ; ;
; Default assignment ; ; ; ; ;
; -- Number of signals with Toggle Rate from Default assignment ; 2 (0.0%) ; 2 (1.1%) ; 0 (0.0%) ; 0 (0.0%) ;
; -- Number of signals with Static Probability from Default assignment ; 59 (1.0%) ; 57 (30.8%) ; 0 (0.0%) ; 2 (0.1%) ;
; ; ; ; ; ;
; Assumed 0 ; ; ; ; ;
; -- Number of signals with Toggle Rate assumed 0 ; 57 (1.0%) ; 55 (29.7%) ; 0 (0.0%) ; 2 (0.1%) ;
+----------------------------------------------------------------------------------------+--------------+-------------+---------------+---------------+
+---------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Activities ;
+--------+------+---------------------------------------------+-------------------------+--------------------+--------------------------------+
; Signal ; Type ; Toggle Rate (millions of transitions / sec) ; Toggle Rate Data Source ; Static Probability ; Static Probability Data Source ;
+--------+------+---------------------------------------------+-------------------------+--------------------+--------------------------------+
(1) The "Signal Activity" Table has been hidden. To show this table, please select the "Write signal activities to report file" option under "PowerPlay Power Analyzer Settings".
+-----------------------------------+
; PowerPlay Power Analyzer Messages ;
+-----------------------------------+
Info: *******************************************************************
Info: Running Quartus II 64-Bit PowerPlay Power Analyzer
Info: Version 15.0.0 Build 145 04/22/2015 SJ Full Version
Info: Processing started: Tue Apr 19 12:52:42 2016
Info: Command: quartus_pow --read_settings_files=off --write_settings_files=off finalProject -c finalProject
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Info (332164): Evaluating HDL-embedded SDC commands
Info (332165): Entity alt_jtag_atlantic
Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|jupdate}] -to [get_registers {*|alt_jtag_atlantic:*|jupdate1*}]
Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}]
Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}]
Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}]
Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}]
Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}]
Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}]
Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}]
Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}]
Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|read}] -to [get_registers {*|alt_jtag_atlantic:*|read1*}]
Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|read_req}]
Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rvalid}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}]
Info (332166): set_false_path -from [get_registers {*|t_dav}] -to [get_registers {*|alt_jtag_atlantic:*|tck_t_dav}]
Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|user_saw_rvalid}] -to [get_registers {*|alt_jtag_atlantic:*|rvalid0*}]
Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}]
Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}]
Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}]
Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}]
Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}]
Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}]
Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}]
Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}]
Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write}] -to [get_registers {*|alt_jtag_atlantic:*|write1*}]
Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write_stalled}] -to [get_registers {*|alt_jtag_atlantic:*|t_ena*}]
Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write_stalled}] -to [get_registers {*|alt_jtag_atlantic:*|t_pause*}]
Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write_valid}]
Info (332165): Entity altera_avalon_st_clock_crosser
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
Info (332165): Entity altera_std_synchronizer
Info (332166): set_false_path -to [get_keepers {*altera_std_synchronizer:*|din_s1}]
Info (332165): Entity sld_hub
Info (332166): create_clock -name altera_reserved_tck [get_ports {altera_reserved_tck}] -period 10MHz
Info (332166): set_clock_groups -asynchronous -group {altera_reserved_tck}
Info (332104): Reading SDC File: 'nios_system/synthesis/submodules/altera_reset_controller.sdc'
Info (332104): Reading SDC File: 'nios_system/synthesis/submodules/nios_system_nios2_qsys_0_cpu.sdc'
Warning (332060): Node: CLOCK_50 was determined to be a clock but was found without an associated clock assignment.
Info (13166): Register colorValue[5] is being clocked by CLOCK_50
Warning (332060): Node: vga_controller:vgasync_instance|clkdiv was determined to be a clock but was found without an associated clock assignment.
Info (13166): Register vga_controller:vgasync_instance|vs is being clocked by vga_controller:vgasync_instance|clkdiv
Warning (332056): PLL cross checking found inconsistent PLL clock settings:
Warning (332056): Node: nios_system|sdram_pll|sd1|pll7|clk[0] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000
Warning (332056): Node: nios_system|sdram_pll|sd1|pll7|clk[1] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000
Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command.
Critical Warning (332169): From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold)
Critical Warning (332169): From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold)
Critical Warning (332169): From altera_reserved_tck (Fall) to altera_reserved_tck (Fall) (setup and hold)
Info (223000): Starting Vectorless Power Activity Estimation
Warning (222013): Relative toggle rates could not be calculated because no clock domain could be identified for some nodes
Info (223001): Completed Vectorless Power Activity Estimation
Info (218000): Using Advanced I/O Power to simulate I/O buffers with the specified board trace model
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (215049): Average toggle rate for this design is 0.121 millions of transitions / sec
Info (215031): Total thermal power estimate for the design is 167.71 mW
Info: Quartus II 64-Bit PowerPlay Power Analyzer was successful. 0 errors, 10 warnings
Info: Peak virtual memory: 802 megabytes
Info: Processing ended: Tue Apr 19 12:52:54 2016
Info: Elapsed time: 00:00:12
Info: Total CPU time (on all processors): 00:00:11