Stack alignment not handled

[ivq]

Summary

The ARM-M architecture may require that all exceptions are entered with 8-byte stack alignment. However, this is not handled by
current implementation, leading to potential incorrect stack pointer being reported.

Details

The ARMv6-M arch requires 8-byte stack alignment, see B1.5.7 of DDI0419E, the ARMv6-M Architecture Reference Manual.
The ARMv7-M arch may requires 8-byte stack alignment depending on implementation or runtime configuration. See B1.5.7 of DDI0403E.e, the Armv7-M Architecture Reference Manual.
The ARMv8-M arch requires 8-byte stack alignment, see B3.19, R_PBVF of DDI0553B.x, the ARMv8-M Architecture Reference Manual.

How to test

The following snippet can be used to trigger the bug.

// SPDX-License-Identifier: MIT
// Copyright (c) 2025 Chien Wong <[email protected]>
void __attribute__((naked)) test_sp_align_trigger_fault(void)
{
    __asm volatile(
        ".syntax unified    \n"
        // sp should be 8-byte aligned when this function is called by C code, assert this.
        "mov r0, sp         \n"
        "lsls r0, r0, #30   \n"
        "beq 1f             \n"
        "b .                \n"
        "1:                 \n"
        // set pattern for checking in cmbacktrace output
        "movs r0, #0xe0     \n"
        "movs r1, #0xe1     \n"
        "movs r2, #0xe2     \n"
        "movs r3, #0xe3     \n"
        // this op makes sp no more 8-byte aligned, but only 4-byte aligned
        "push {r4}          \n"
        // record sp for checking in cmbacktrace output
        "mov r12, sp        \n"
        // trigger fault
        "udf #0xee          \n"
    );
}

After this function is called, CmBacktrace should print context information when the fault is triggered.
The printed value of stack pointer and r12 should be identical. However, the current implementation will fail the test.

Fix

See #90.