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This is to collect current paint points with the gateware design.
I will start to add some, feel free to add your own, if you find any
CSRs completely ignore clock domains. In practice this is almost always fine, but still not nice.
Every peripheral is added as a submodule to the peripheral connector. This has multiple downsides:
Peripherals are not found where you would expect them in things like usage reports.
ClockDomains work very unintuitive. If you DomainRenamer a module that contains a peripheral, the peripheral will not be renamed.
There can be DriverConflicts, for example in the case of SocMemory. SocMemory creates a read port in the peripheral to allow reading the memory, but if one also needs to a read port in the gateware, you will get a DriverConflict, because that read port is added in the place where you obtain the read port (and there is a additional one in the PeripheralConnector).
Its hard to generically add non local ClockDomains. This is probably more of a nmigen painpoint, but we feel it, because of the PeripheralConnector implementation. To avoid the DriverConflicts from point 2., one can add the read port needed by the gateware to the PeripheralConnector aswell. To make DomainRenamer on the gateware side user of the ReadPort work however one needs to create a ClockDomain when creating a read port and assign that ClockDomain to the read port domain. Finally by driving that ClockDomain from the given domain (or by default "sync") DomainRenamer works again. For this however the ClockDomain needs a unique name because it can not be local (it needs to be visible in the PeripheralConnector.
Some elaboration order problems have very involved solutions. For example the elaboration of the peripheral support logic (the PeripheralConnector and others) needs to happend after everything else is elaborated. This is currently solved by making it possible to add hooks which then can inject fragments after everything else is done. This is very magic and is completely seperate from how the rest of nmigen works, so something else would be nice here.
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This is to collect current paint points with the gateware design.
I will start to add some, feel free to add your own, if you find any
DomainRenamer
a module that contains a peripheral, the peripheral will not be renamed.SocMemory
.SocMemory
creates a read port in the peripheral to allow reading the memory, but if one also needs to a read port in the gateware, you will get a DriverConflict, because that read port is added in the place where you obtain the read port (and there is a additional one in thePeripheralConnector
).ClockDomains
. This is probably more of a nmigen painpoint, but we feel it, because of thePeripheralConnector
implementation. To avoid theDriverConflicts
from point 2., one can add the read port needed by the gateware to thePeripheralConnector
aswell. To makeDomainRenamer
on the gateware side user of theReadPort
work however one needs to create aClockDomain
when creating a read port and assign thatClockDomain
to the read port domain. Finally by driving thatClockDomain
from the given domain (or by default"sync"
)DomainRenamer
works again. For this however theClockDomain
needs a unique name because it can not be local (it needs to be visible in thePeripheralConnector
.PeripheralConnector
and others) needs to happend after everything else is elaborated. This is currently solved by making it possible to add hooks which then can inject fragments after everything else is done. This is very magic and is completely seperate from how the rest of nmigen works, so something else would be nice here.Beta Was this translation helpful? Give feedback.
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