diff --git a/crates/mipsevm/Cargo.toml b/crates/mipsevm/Cargo.toml
index c8cb63e..fdf6a4f 100644
--- a/crates/mipsevm/Cargo.toml
+++ b/crates/mipsevm/Cargo.toml
@@ -20,3 +20,6 @@ tracing = "0.1.37"
[dev-dependencies]
rand = "0.8.5"
revm = "3.3.0"
+
+[features]
+tracing = []
diff --git a/crates/mipsevm/open_mips_tests/LICENSE b/crates/mipsevm/open_mips_tests/LICENSE
new file mode 100644
index 0000000..65c5ca8
--- /dev/null
+++ b/crates/mipsevm/open_mips_tests/LICENSE
@@ -0,0 +1,165 @@
+ GNU LESSER GENERAL PUBLIC LICENSE
+ Version 3, 29 June 2007
+
+ Copyright (C) 2007 Free Software Foundation, Inc.
+ Everyone is permitted to copy and distribute verbatim copies
+ of this license document, but changing it is not allowed.
+
+
+ This version of the GNU Lesser General Public License incorporates
+the terms and conditions of version 3 of the GNU General Public
+License, supplemented by the additional permissions listed below.
+
+ 0. Additional Definitions.
+
+ As used herein, "this License" refers to version 3 of the GNU Lesser
+General Public License, and the "GNU GPL" refers to version 3 of the GNU
+General Public License.
+
+ "The Library" refers to a covered work governed by this License,
+other than an Application or a Combined Work as defined below.
+
+ An "Application" is any work that makes use of an interface provided
+by the Library, but which is not otherwise based on the Library.
+Defining a subclass of a class defined by the Library is deemed a mode
+of using an interface provided by the Library.
+
+ A "Combined Work" is a work produced by combining or linking an
+Application with the Library. The particular version of the Library
+with which the Combined Work was made is also called the "Linked
+Version".
+
+ The "Minimal Corresponding Source" for a Combined Work means the
+Corresponding Source for the Combined Work, excluding any source code
+for portions of the Combined Work that, considered in isolation, are
+based on the Application, and not on the Linked Version.
+
+ The "Corresponding Application Code" for a Combined Work means the
+object code and/or source code for the Application, including any data
+and utility programs needed for reproducing the Combined Work from the
+Application, but excluding the System Libraries of the Combined Work.
+
+ 1. Exception to Section 3 of the GNU GPL.
+
+ You may convey a covered work under sections 3 and 4 of this License
+without being bound by section 3 of the GNU GPL.
+
+ 2. Conveying Modified Versions.
+
+ If you modify a copy of the Library, and, in your modifications, a
+facility refers to a function or data to be supplied by an Application
+that uses the facility (other than as an argument passed when the
+facility is invoked), then you may convey a copy of the modified
+version:
+
+ a) under this License, provided that you make a good faith effort to
+ ensure that, in the event an Application does not supply the
+ function or data, the facility still operates, and performs
+ whatever part of its purpose remains meaningful, or
+
+ b) under the GNU GPL, with none of the additional permissions of
+ this License applicable to that copy.
+
+ 3. Object Code Incorporating Material from Library Header Files.
+
+ The object code form of an Application may incorporate material from
+a header file that is part of the Library. You may convey such object
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+
+ a) Give prominent notice with each copy of the object code that the
+ Library is used in it and that the Library and its use are
+ covered by this License.
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+ b) Accompany the object code with a copy of the GNU GPL and this license
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+ 4. Combined Works.
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+ You may convey a Combined Work under terms of your choice that,
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+the following:
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+ a) Give prominent notice with each copy of the Combined Work that
+ the Library is used in it and that the Library and its use are
+ covered by this License.
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+ c) For a Combined Work that displays copyright notices during
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+ d) Do one of the following:
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+ Corresponding Source.
+
+ 1) Use a suitable shared library mechanism for linking with the
+ Library. A suitable mechanism is one that (a) uses at run time
+ a copy of the Library already present on the user's computer
+ system, and (b) will operate properly with a modified version
+ of the Library that is interface-compatible with the Linked
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+
+ e) Provide Installation Information, but only if you would otherwise
+ be required to provide such information under section 6 of the
+ GNU GPL, and only to the extent that such information is
+ necessary to install and execute a modified version of the
+ Combined Work produced by recombining or relinking the
+ Application with a modified version of the Linked Version. (If
+ you use option 4d0, the Installation Information must accompany
+ the Minimal Corresponding Source and Corresponding Application
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+ Information in the manner specified by section 6 of the GNU GPL
+ for conveying Corresponding Source.)
+
+ 5. Combined Libraries.
+
+ You may place library facilities that are a work based on the
+Library side by side in a single library together with other library
+facilities that are not Applications and are not covered by this
+License, and convey such a combined library under terms of your
+choice, if you do both of the following:
+
+ a) Accompany the combined library with a copy of the same work based
+ on the Library, uncombined with any other library facilities,
+ conveyed under the terms of this License.
+
+ b) Give prominent notice with the combined library that part of it
+ is a work based on the Library, and explaining where to find the
+ accompanying uncombined form of the same work.
+
+ 6. Revised Versions of the GNU Lesser General Public License.
+
+ The Free Software Foundation may publish revised and/or new versions
+of the GNU Lesser General Public License from time to time. Such new
+versions will be similar in spirit to the present version, but may
+differ in detail to address new problems or concerns.
+
+ Each version is given a distinguishing version number. If the
+Library as you received it specifies that a certain numbered version
+of the GNU Lesser General Public License "or any later version"
+applies to it, you have the option of following the terms and
+conditions either of that published version or of any later version
+published by the Free Software Foundation. If the Library as you
+received it does not specify a version number of the GNU Lesser
+General Public License, you may choose any version of the GNU Lesser
+General Public License ever published by the Free Software Foundation.
+
+ If the Library as you received it specifies that a proxy can decide
+whether future versions of the GNU Lesser General Public License shall
+apply, that proxy's public statement of acceptance of any version is
+permanent authorization for you to choose that version for the
+Library.
diff --git a/crates/mipsevm/open_mips_tests/README.md b/crates/mipsevm/open_mips_tests/README.md
new file mode 100644
index 0000000..db69c9d
--- /dev/null
+++ b/crates/mipsevm/open_mips_tests/README.md
@@ -0,0 +1,10 @@
+# OpenMIPS test vectors
+
+Tests from https://github.com/grantae/OpenMIPS/tree/d606b35e9d5260aef20de2a58660c8303a681e9c/software/test/macro/tests
+
+OpenMIPS is licensed LGPLv3 (as seen in the root of the repository), see [`LICENSE`](./LICENSE) file.
+Note that some build-system files from 2014/2015 in that repository by the same author are marked as BSD licensed,
+but the build-system is not used here.
+
+Requires https://github.com/sergev/LiteBSD/releases/download/tools/gcc-4.8.1-mips-macosx.tgz to build
+
diff --git a/crates/mipsevm/open_mips_tests/maketests.py b/crates/mipsevm/open_mips_tests/maketests.py
new file mode 100755
index 0000000..56118b1
--- /dev/null
+++ b/crates/mipsevm/open_mips_tests/maketests.py
@@ -0,0 +1,37 @@
+#!/usr/bin/env python3
+import os
+import sys
+import tempfile
+from capstone import *
+from elftools.elf.elffile import ELFFile
+md = Cs(CS_ARCH_MIPS, CS_MODE_32 + CS_MODE_BIG_ENDIAN)
+
+def maketest(d, out):
+ with tempfile.NamedTemporaryFile() as nf:
+ print("building", d, "->", out)
+ # which mips is go
+ ret = os.system("mips-linux-gnu-as -defsym big_endian=1 -march=mips32r2 -o %s %s" % (nf.name, d))
+ assert(ret == 0)
+ nf.seek(0)
+ elffile = ELFFile(nf)
+ #print(elffile)
+ for sec in elffile.iter_sections():
+ #print(sec, sec.name, sec.data())
+ if sec.name == ".test":
+ with open(out, "wb") as f:
+ # jump to 0xdead0000 when done
+ #data = b"\x24\x1f\xde\xad\x00\x1f\xfc\x00" + sec.data()
+ data = sec.data()
+ for dd in md.disasm(data, 0):
+ print(dd)
+ f.write(data)
+
+if __name__ == "__main__":
+ os.makedirs("/tmp/mips", exist_ok=True)
+ if len(sys.argv) > 2:
+ maketest(sys.argv[1], sys.argv[2])
+ else:
+ for d in os.listdir("test/"):
+ if not d.endswith(".asm"):
+ continue
+ maketest("test/"+d, "test/bin/"+(d.replace(".asm", ".bin")))
diff --git a/crates/mipsevm/open_mips_tests/test/add.asm b/crates/mipsevm/open_mips_tests/test/add.asm
new file mode 100644
index 0000000..b4c8d1d
--- /dev/null
+++ b/crates/mipsevm/open_mips_tests/test/add.asm
@@ -0,0 +1,42 @@
+###############################################################################
+# File : add.asm
+# Project : MIPS32 MUX
+# Author: : Grant Ayers (ayers@cs.stanford.edu)
+#
+# Standards/Formatting:
+# MIPS gas, soft tab, 80 column
+#
+# Description:
+# Test the functionality of the 'add' instruction.
+#
+###############################################################################
+
+
+ .section .test, "x"
+ .balign 4
+ .set noreorder
+ .global test
+ .ent test
+test:
+ lui $s0, 0xbfff # Load the base address 0xbffffff0
+ ori $s0, 0xfff0
+ ori $s1, $0, 1 # Prepare the 'done' status
+
+ #### Test code start ####
+
+ lui $t0, 0xffff # A = 0xfffffffd (-3)
+ ori $t0, 0xfffd
+ ori $t1, $0, 0x3 # B = 0x3
+ add $t2, $t0, $t1 # C = A + B = 0
+ sltiu $v0, $t2, 1 # D = 1 if C == 0
+
+ #### Test code end ####
+
+ sw $v0, 8($s0) # Set the test result
+ sw $s1, 4($s0) # Set 'done'
+
+$done:
+ jr $ra
+ nop
+
+ .end test
diff --git a/crates/mipsevm/open_mips_tests/test/addi.asm b/crates/mipsevm/open_mips_tests/test/addi.asm
new file mode 100644
index 0000000..bb54e8a
--- /dev/null
+++ b/crates/mipsevm/open_mips_tests/test/addi.asm
@@ -0,0 +1,42 @@
+###############################################################################
+# File : addi.asm
+# Project : MIPS32 MUX
+# Author : Grant Ayers (ayers@cs.stanford.edu)
+#
+# Standards/Formatting:
+# MIPS gas, soft tab, 80 column
+#
+# Description:
+# Test the functionality of the 'addi' instruction.
+#
+###############################################################################
+
+
+ .section .test, "x"
+ .balign 4
+ .set noreorder
+ .global test
+ .ent test
+test:
+ lui $s0, 0xbfff # Load the base address 0xbffffff0
+ ori $s0, 0xfff0
+ ori $s1, $0, 1 # Prepare the 'done' status
+
+ #### Test code start ####
+
+ lui $t0, 0xffff # A = 0xfffffffd (-3)
+ ori $t0, 0xfffd
+ addi $t1, $t0, 5 # B = A + 5 = 2
+ addi $t2, $t1, 0xfffe # C = B + -2 = 0
+ sltiu $v0, $t2, 1 # D = 1 if C == 0
+
+ #### Test code end ####
+
+ sw $v0, 8($s0) # Set the test result
+ sw $s1, 4($s0) # Set 'done'
+
+$done:
+ jr $ra
+ nop
+
+ .end test
diff --git a/crates/mipsevm/open_mips_tests/test/addiu.asm b/crates/mipsevm/open_mips_tests/test/addiu.asm
new file mode 100644
index 0000000..12362f6
--- /dev/null
+++ b/crates/mipsevm/open_mips_tests/test/addiu.asm
@@ -0,0 +1,42 @@
+###############################################################################
+# File : addiu.asm
+# Project : MIPS32 MUX
+# Author : Grant Ayers (ayers@cs.stanford.edu)
+#
+# Standards/Formatting:
+# MIPS gas, soft tab, 80 column
+#
+# Description:
+# Test the functionality of the 'addiu' instruction.
+#
+###############################################################################
+
+
+ .section .test, "x"
+ .balign 4
+ .set noreorder
+ .global test
+ .ent test
+test:
+ lui $s0, 0xbfff # Load the base address 0xbffffff0
+ ori $s0, 0xfff0
+ ori $s1, $0, 1 # Prepare the 'done' status
+
+ #### Test code start ####
+
+ lui $t0, 0xffff # A = 0xfffffffd (-3)
+ ori $t0, 0xfffd
+ addiu $t1, $t0, 5 # B = A + 5 = 2
+ addiu $t2, $t1, 0xfffe # C = B + -2 = 0
+ sltiu $v0, $t2, 1 # D = 1 if C == 0
+
+ #### Test code end ####
+
+ sw $v0, 8($s0) # Set the test result
+ sw $s1, 4($s0) # Set 'done'
+
+$done:
+ jr $ra
+ nop
+
+ .end test
diff --git a/crates/mipsevm/open_mips_tests/test/addu.asm b/crates/mipsevm/open_mips_tests/test/addu.asm
new file mode 100644
index 0000000..3818824
--- /dev/null
+++ b/crates/mipsevm/open_mips_tests/test/addu.asm
@@ -0,0 +1,42 @@
+###############################################################################
+# File : addu.asm
+# Project : MIPS32 MUX
+# Author : Grant Ayers (ayers@cs.stanford.edu)
+#
+# Standards/Formatting:
+# MIPS gas, soft tab, 80 column
+#
+# Description:
+# Test the functionality of the 'addu' instruction.
+#
+###############################################################################
+
+
+ .section .test, "x"
+ .balign 4
+ .set noreorder
+ .global test
+ .ent test
+test:
+ lui $s0, 0xbfff # Load the base address 0xbffffff0
+ ori $s0, 0xfff0
+ ori $s1, $0, 1 # Prepare the 'done' status
+
+ #### Test code start ####
+
+ lui $t0, 0xffff # A = 0xfffffffd (-3)
+ ori $t0, 0xfffd
+ ori $t1, $0, 0x3 # B = 0x3
+ addu $t2, $t0, $t1 # C = A + B = 0
+ sltiu $v0, $t2, 1 # D = 1 if C == 0
+
+ #### Test code end ####
+
+ sw $v0, 8($s0) # Set the test result
+ sw $s1, 4($s0) # Set 'done'
+
+$done:
+ jr $ra
+ nop
+
+ .end test
diff --git a/crates/mipsevm/open_mips_tests/test/and.asm b/crates/mipsevm/open_mips_tests/test/and.asm
new file mode 100644
index 0000000..181616f
--- /dev/null
+++ b/crates/mipsevm/open_mips_tests/test/and.asm
@@ -0,0 +1,46 @@
+###############################################################################
+# File : and.asm
+# Project : MIPS32 MUX
+# Author: : Grant Ayers (ayers@cs.stanford.edu)
+#
+# Standards/Formatting:
+# MIPS gas, soft tab, 80 column
+#
+# Description:
+# Test the functionality of the 'and' instruction.
+#
+###############################################################################
+
+
+ .section .test, "x"
+ .balign 4
+ .set noreorder
+ .global test
+ .ent test
+test:
+ lui $s0, 0xbfff # Load the base address 0xbffffff0
+ ori $s0, 0xfff0
+ ori $s1, $0, 1 # Prepare the 'done' status
+
+ #### Test code start ####
+
+ lui $t0, 0xdeaf # A = 0xdeafbeef
+ lui $t1, 0xaaaa # B = 0xaaaaaaaa
+ lui $t2, 0x5555 # C = 0x55555555
+ ori $t0, 0xbeef
+ ori $t1, 0xaaaa
+ ori $t2, 0x5555
+ and $t3, $t0, $t1 # D = A & B = 0x8aaaaaaa
+ and $t4, $t2, $t3 # E = B & D = 0
+ sltiu $v0, $t4, 1
+
+ #### Test code end ####
+
+ sw $v0, 8($s0) # Set the test result
+ sw $s1, 4($s0) # Set 'done'
+
+$done:
+ jr $ra
+ nop
+
+ .end test
diff --git a/crates/mipsevm/open_mips_tests/test/andi.asm b/crates/mipsevm/open_mips_tests/test/andi.asm
new file mode 100644
index 0000000..f87fa17
--- /dev/null
+++ b/crates/mipsevm/open_mips_tests/test/andi.asm
@@ -0,0 +1,41 @@
+###############################################################################
+# File : andi.asm
+# Project : MIPS32 MUX
+# Author: : Grant Ayers (ayers@cs.stanford.edu)
+#
+# Standards/Formatting:
+# MIPS gas, soft tab, 80 column
+#
+# Description:
+# Test the functionality of the 'andi' instruction.
+#
+###############################################################################
+
+
+ .section .test, "x"
+ .balign 4
+ .set noreorder
+ .global test
+ .ent test
+test:
+ lui $s0, 0xbfff # Load the base address 0xbffffff0
+ ori $s0, 0xfff0
+ ori $s1, $0, 1 # Prepare the 'done' status
+
+ #### Test code start ####
+
+ ori $t0, $0, 0xcafe # A = 0xcafe
+ andi $t1, $t0, 0xaaaa # B = A & 0xaaaa = 0x8aaa
+ andi $t2, $t1, 0x5555 # C = B & 0x5555 = 0
+ sltiu $v0, $t2, 1
+
+ #### Test code end ####
+
+ sw $v0, 8($s0) # Set the test result
+ sw $s1, 4($s0) # Set 'done'
+
+$done:
+ jr $ra
+ nop
+
+ .end test
diff --git a/crates/mipsevm/open_mips_tests/test/beq.asm b/crates/mipsevm/open_mips_tests/test/beq.asm
new file mode 100644
index 0000000..029f9e1
--- /dev/null
+++ b/crates/mipsevm/open_mips_tests/test/beq.asm
@@ -0,0 +1,54 @@
+###############################################################################
+# File : beq.asm
+# Project : MIPS32 MUX
+# Author: : Grant Ayers (ayers@cs.stanford.edu)
+#
+# Standards/Formatting:
+# MIPS gas, soft tab, 80 column
+#
+# Description:
+# Test the functionality of the 'beq' instruction.
+#
+###############################################################################
+
+
+ .section .test, "x"
+ .balign 4
+ .set noreorder
+ .global test
+ .ent test
+test:
+ lui $s0, 0xbfff # Load the base address 0xbffffff0
+ ori $s0, 0xfff0
+ ori $s1, $0, 1 # Prepare the 'done' status
+
+ #### Test code start ####
+
+ ori $t0, $0, 0xcafe
+ ori $t1, $0, 0xcafe
+ ori $v0, $0, 0 # The test result starts as a failure
+ beq $t0, $v0, $finish # No branch
+ nop
+ beq $t0, $t1, $target
+ nop
+
+$finish:
+ sw $v0, 8($s0)
+ sw $s1, 4($s0)
+
+$done:
+ jr $ra
+ nop
+ j $finish # Early-by-1 branch detection
+
+$target:
+ nop
+ ori $v0, $0, 1 # Set the result to pass
+ beq $0, $0, $finish # Late-by-1 branch detection (result not stored)
+ nop
+ j $finish
+ nop
+
+ #### Test code end ####
+
+ .end test
diff --git a/crates/mipsevm/open_mips_tests/test/bgez.asm b/crates/mipsevm/open_mips_tests/test/bgez.asm
new file mode 100644
index 0000000..fd2b08f
--- /dev/null
+++ b/crates/mipsevm/open_mips_tests/test/bgez.asm
@@ -0,0 +1,52 @@
+###############################################################################
+# File : bgez.asm
+# Project : MIPS32 MUX
+# Author: : Grant Ayers (ayers@cs.stanford.edu)
+#
+# Standards/Formatting:
+# MIPS gas, soft tab, 80 column
+#
+# Description:
+# Test the functionality of the 'bgez' instruction.
+#
+###############################################################################
+
+
+ .section .test, "x"
+ .balign 4
+ .set noreorder
+ .global test
+ .ent test
+test:
+ lui $s0, 0xbfff # Load the base address 0xbffffff0
+ ori $s0, 0xfff0
+ ori $s1, $0, 1 # Prepare the 'done' status
+
+ #### Test code start ####
+
+ lui $t0, 0xffff
+ bgez $t0, $finish # No branch
+ nop
+ bgez $s1, $target
+ nop
+
+$finish:
+ sw $v0, 8($s0)
+ sw $s1, 4($s0)
+
+$done:
+ jr $ra
+ nop
+ j $finish # Early-by-1 branch detection
+
+$target:
+ nop
+ ori $v0, $0, 1 # Set the result to pass
+ bgez $0, $finish # Late-by-1 branch detection (result not stored)
+ nop
+ j $finish # Broken branch recovery
+ nop
+
+ #### Test code end ####
+
+ .end test
diff --git a/crates/mipsevm/open_mips_tests/test/bgtz.asm b/crates/mipsevm/open_mips_tests/test/bgtz.asm
new file mode 100644
index 0000000..86af4e9
--- /dev/null
+++ b/crates/mipsevm/open_mips_tests/test/bgtz.asm
@@ -0,0 +1,53 @@
+###############################################################################
+# File : bgtz.asm
+# Project : MIPS32 MUX
+# Author: : Grant Ayers (ayers@cs.stanford.edu)
+#
+# Standards/Formatting:
+# MIPS gas, soft tab, 80 column
+#
+# Description:
+# Test the functionality of the 'bgtz' instruction.
+#
+###############################################################################
+
+
+ .section .test, "x"
+ .balign 4
+ .set noreorder
+ .global test
+ .ent test
+test:
+ lui $s0, 0xbfff # Load the base address 0xbffffff0
+ ori $s0, 0xfff0
+ ori $s1, $0, 1 # Prepare the 'done' status
+
+ #### Test code start ####
+
+ ori $v0, $0, 0 # The test result starts as a failure
+ lui $t0, 0xffff
+ bgtz $t0, $finish # No branch
+ nop
+ bgtz $s1, $target
+ nop
+
+$finish:
+ sw $v0, 8($s0)
+ sw $s1, 4($s0)
+
+$done:
+ jr $ra
+ nop
+ j $finish # Early-by-1 branch detection
+
+$target:
+ nop
+ ori $v0, $0, 1 # Set the result to pass
+ bgtz $s1, $finish # Late-by-1 branch detection (result not stored)
+ nop
+ j $finish # Broken branch recovery
+ nop
+
+ #### Test code end ####
+
+ .end test
diff --git a/crates/mipsevm/open_mips_tests/test/bin/add.bin b/crates/mipsevm/open_mips_tests/test/bin/add.bin
new file mode 100644
index 0000000..56fa8a1
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@@ -0,0 +1,52 @@
+###############################################################################
+# File : blez.asm
+# Project : MIPS32 MUX
+# Author: : Grant Ayers (ayers@cs.stanford.edu)
+#
+# Standards/Formatting:
+# MIPS gas, soft tab, 80 column
+#
+# Description:
+# Test the functionality of the 'blez' instruction.
+#
+###############################################################################
+
+
+ .section .test, "x"
+ .balign 4
+ .set noreorder
+ .global test
+ .ent test
+test:
+ lui $s0, 0xbfff # Load the base address 0xbffffff0
+ ori $s0, 0xfff0
+ ori $s1, $0, 1 # Prepare the 'done' status
+
+ #### Test code start ####
+
+ ori $v0, $0, 0 # The test result starts as a failure
+ blez $s1, $finish # No branch
+ lui $t0, 0xffff
+ blez $t0, $target
+ nop
+
+$finish:
+ sw $v0, 8($s0)
+ sw $s1, 4($s0)
+
+$done:
+ jr $ra
+ nop
+ j $finish # Early-by-1 branch detection
+
+$target:
+ nop
+ ori $v0, $0, 1 # Set the result to pass
+ blez $0, $finish # Late-by-1 branch detection (result not stored)
+ nop
+ j $finish
+ nop
+
+ #### Test code end ####
+
+ .end test
diff --git a/crates/mipsevm/open_mips_tests/test/bltz.asm b/crates/mipsevm/open_mips_tests/test/bltz.asm
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index 0000000..349bfab
--- /dev/null
+++ b/crates/mipsevm/open_mips_tests/test/bltz.asm
@@ -0,0 +1,54 @@
+###############################################################################
+# File : bltz.asm
+# Project : MIPS32 MUX
+# Author: : Grant Ayers (ayers@cs.stanford.edu)
+#
+# Standards/Formatting:
+# MIPS gas, soft tab, 80 column
+#
+# Description:
+# Test the functionality of the 'bltz' instruction.
+#
+###############################################################################
+
+
+ .section .test, "x"
+ .balign 4
+ .set noreorder
+ .global test
+ .ent test
+test:
+ lui $s0, 0xbfff # Load the base address 0xbffffff0
+ ori $s0, 0xfff0
+ ori $s1, $0, 1 # Prepare the 'done' status
+
+ #### Test code start ####
+
+ ori $v0, $0, 0 # The test result starts as a failure
+ bltz $0, $finish # No branch
+ nop
+ bltz $s1, $finish # No branch
+ lui $t0, 0xffff
+ bltz $t0, $target
+ nop
+
+$finish:
+ sw $v0, 8($s0)
+ sw $s1, 4($s0)
+
+$done:
+ jr $ra
+ nop
+ j $finish # Early-by-1 branch detection
+
+$target:
+ nop
+ ori $v0, $0, 1 # Set the result to pass
+ bltz $t0, $finish # Late-by-1 branch detection (result not stored)
+ nop
+ j $finish # Broken branch recovery
+ nop
+
+ #### Test code end ####
+
+ .end test
diff --git a/crates/mipsevm/open_mips_tests/test/bne.asm b/crates/mipsevm/open_mips_tests/test/bne.asm
new file mode 100644
index 0000000..9b93767
--- /dev/null
+++ b/crates/mipsevm/open_mips_tests/test/bne.asm
@@ -0,0 +1,54 @@
+###############################################################################
+# File : bne.asm
+# Project : MIPS32 MUX
+# Author: : Grant Ayers (ayers@cs.stanford.edu)
+#
+# Standards/Formatting:
+# MIPS gas, soft tab, 80 column
+#
+# Description:
+# Test the functionality of the 'bne' instruction.
+#
+###############################################################################
+
+
+ .section .test, "x"
+ .balign 4
+ .set noreorder
+ .global test
+ .ent test
+test:
+ lui $s0, 0xbfff # Load the base address 0xbffffff0
+ ori $s0, 0xfff0
+ ori $s1, $0, 1 # Prepare the 'done' status
+
+ #### Test code start ####
+
+ ori $t0, $0, 0xcafe
+ ori $t1, $0, 0xcafe
+ ori $v0, $0, 0 # The test result starts as a failure
+ bne $t0, $t1, $finish # No branch
+ nop
+ bne $t0, $v0, $target
+ nop
+
+$finish:
+ sw $v0, 8($s0)
+ sw $s1, 4($s0)
+
+$done:
+ jr $ra
+ nop
+ j $finish # Early-by-1 branch detection
+
+$target:
+ nop
+ ori $v0, $0, 1 # Set the result to pass
+ bne $t0, $0, $finish # Late-by-1 branch detection (result not stored)
+ nop
+ j $finish
+ nop
+
+ #### Test code end ####
+
+ .end test
diff --git a/crates/mipsevm/open_mips_tests/test/brk.asm b/crates/mipsevm/open_mips_tests/test/brk.asm
new file mode 100644
index 0000000..0bcefe5
--- /dev/null
+++ b/crates/mipsevm/open_mips_tests/test/brk.asm
@@ -0,0 +1,26 @@
+.section .test, "x"
+ .balign 4
+ .set noreorder
+ .global test
+ .ent test
+
+test:
+ li $v0, 4045
+ syscall
+ lui $t0, 0x4000
+ subu $v0, $v0, $t0
+ sltiu $v0, $v0, 1
+
+# save results
+ lui $s0, 0xbfff # Load the base address 0xbffffff0
+ ori $s0, 0xfff0
+ ori $s1, $0, 1 # Prepare the 'done' status
+
+ sw $v0, 8($s0) # Set the test result
+ sw $s1, 4($s0) # Set 'done'
+
+$done:
+ jr $ra
+ nop
+
+ .end test
diff --git a/crates/mipsevm/open_mips_tests/test/clo.asm b/crates/mipsevm/open_mips_tests/test/clo.asm
new file mode 100644
index 0000000..fff666e
--- /dev/null
+++ b/crates/mipsevm/open_mips_tests/test/clo.asm
@@ -0,0 +1,63 @@
+###############################################################################
+# File : clo.asm
+# Project : MIPS32 MUX
+# Author: : Grant Ayers (ayers@cs.stanford.edu)
+#
+# Standards/Formatting:
+# MIPS gas, soft tab, 80 column
+#
+# Description:
+# Test the functionality of the 'clo' instruction.
+#
+###############################################################################
+
+
+ .section .test, "x"
+ .balign 4
+ .set noreorder
+ .global test
+ .ent test
+test:
+ lui $s0, 0xbfff # Load the base address 0xbffffff0
+ ori $s0, 0xfff0
+ ori $s1, $0, 1 # Prepare the 'done' status
+
+ #### Test code start ####
+
+ lui $t2, 0xffff # 32
+ ori $t2, 0xffff
+ lui $t3, 0xffff # 18
+ ori $t3, 0xc000
+ lui $t4, 0xf800 # 5
+ lui $t5, 0xf000 # 4
+ lui $t6, 0x7fff # 0
+ ori $t7, $0, 0 # 0
+ clo $s2, $t2
+ clo $s3, $t3
+ clo $s4, $t4
+ clo $s5, $t5
+ clo $s6, $t6
+ clo $s7, $t7
+ addiu $s2, -32
+ addiu $s3, -18
+ addiu $s4, -5
+ addiu $s5, -4
+ addiu $s6, 0
+ addiu $s7, 0
+ or $v1, $s2, $s3
+ or $v1, $v1, $s4
+ or $v1, $v1, $s5
+ or $v1, $v1, $s6
+ or $v1, $v1, $s7
+ sltiu $v0, $v1, 1
+
+ #### Test code end ####
+
+ sw $v0, 8($s0) # Set the test result
+ sw $s1, 4($s0) # Set 'done'
+
+$done:
+ jr $ra
+ nop
+
+ .end test
diff --git a/crates/mipsevm/open_mips_tests/test/clone.asm b/crates/mipsevm/open_mips_tests/test/clone.asm
new file mode 100644
index 0000000..d34e5ec
--- /dev/null
+++ b/crates/mipsevm/open_mips_tests/test/clone.asm
@@ -0,0 +1,26 @@
+.section .test, "x"
+ .balign 4
+ .set noreorder
+ .global test
+ .ent test
+
+test:
+ li $v0, 4120
+ syscall
+ li $t0, 0x1
+ subu $v0, $v0, $t0
+ sltiu $v0, $v0, 1
+
+# save results
+ lui $s0, 0xbfff # Load the base address 0xbffffff0
+ ori $s0, 0xfff0
+ ori $s1, $0, 1 # Prepare the 'done' status
+
+ sw $v0, 8($s0) # Set the test result
+ sw $s1, 4($s0) # Set 'done'
+
+$done:
+ jr $ra
+ nop
+
+ .end test
diff --git a/crates/mipsevm/open_mips_tests/test/clz.asm b/crates/mipsevm/open_mips_tests/test/clz.asm
new file mode 100644
index 0000000..554cca2
--- /dev/null
+++ b/crates/mipsevm/open_mips_tests/test/clz.asm
@@ -0,0 +1,62 @@
+###############################################################################
+# File : clz.asm
+# Project : MIPS32 MUX
+# Author: : Grant Ayers (ayers@cs.stanford.edu)
+#
+# Standards/Formatting:
+# MIPS gas, soft tab, 80 column
+#
+# Description:
+# Test the functionality of the 'clz' instruction.
+#
+###############################################################################
+
+
+ .section .test, "x"
+ .balign 4
+ .set noreorder
+ .global test
+ .ent test
+test:
+ lui $s0, 0xbfff # Load the base address 0xbffffff0
+ ori $s0, 0xfff0
+ ori $s1, $0, 1 # Prepare the 'done' status
+
+ #### Test code start ####
+
+ lui $t2, 0xffff # 0
+ ori $t2, 0xffff
+ ori $t3, $0, 0x0100 # 23
+ lui $t4, 0x0700 # 5
+ lui $t5, 0x0f00 # 4
+ lui $t6, 0x7fff # 1
+ ori $t7, $0, 0 # 32
+ clz $s2, $t2
+ clz $s3, $t3
+ clz $s4, $t4
+ clz $s5, $t5
+ clz $s6, $t6
+ clz $s7, $t7
+ addiu $s2, 0
+ addiu $s3, -23
+ addiu $s4, -5
+ addiu $s5, -4
+ addiu $s6, -1
+ addiu $s7, -32
+ or $v1, $s2, $s3
+ or $v1, $v1, $s4
+ or $v1, $v1, $s5
+ or $v1, $v1, $s6
+ or $v1, $v1, $s7
+ sltiu $v0, $v1, 1
+
+ #### Test code end ####
+
+ sw $v0, 8($s0) # Set the test result
+ sw $s1, 4($s0) # Set 'done'
+
+$done:
+ jr $ra
+ nop
+
+ .end test
diff --git a/crates/mipsevm/open_mips_tests/test/div.asm b/crates/mipsevm/open_mips_tests/test/div.asm
new file mode 100644
index 0000000..422ad8b
--- /dev/null
+++ b/crates/mipsevm/open_mips_tests/test/div.asm
@@ -0,0 +1,53 @@
+###############################################################################
+# File : div.asm
+# Project : MIPS32 MUX
+# Author: : Grant Ayers (ayers@cs.stanford.edu)
+#
+# Standards/Formatting:
+# MIPS gas, soft tab, 80 column
+#
+# Description:
+# Test the functionality of the 'div' instruction.
+#
+###############################################################################
+
+
+ .section .test, "x"
+ .balign 4
+ .set noreorder
+ .global test
+ .ent test
+test:
+ lui $s0, 0xbfff # Load the base address 0xbffffff0
+ ori $s0, 0xfff0
+ ori $s1, $0, 1 # Prepare the 'done' status
+
+ #### Test code start ####
+
+ lui $t0, 0x1234
+ ori $t0, 0x5678
+ lui $t1, 0xc001
+ ori $t1, 0xcafe
+ div $t1, $t0 # 0xfffffffd (q), 0xf69ece66 (r)
+ mfhi $t2
+ mflo $t3
+ lui $t4, 0xf69e
+ ori $t4, 0xce66
+ lui $t5, 0xffff
+ ori $t5, 0xfffd
+ subu $t6, $t2, $t4
+ subu $t7, $t3, $t5
+ sltiu $v0, $t6, 1
+ sltiu $v1, $t7, 1
+ and $v0, $v0, $v1
+
+ #### Test code end ####
+
+ sw $v0, 8($s0) # Set the test result
+ sw $s1, 4($s0) # Set 'done'
+
+$done:
+ jr $ra
+ nop
+
+ .end test
diff --git a/crates/mipsevm/open_mips_tests/test/divu.asm b/crates/mipsevm/open_mips_tests/test/divu.asm
new file mode 100644
index 0000000..0b85664
--- /dev/null
+++ b/crates/mipsevm/open_mips_tests/test/divu.asm
@@ -0,0 +1,53 @@
+###############################################################################
+# File : divu.asm
+# Project : MIPS32 MUX
+# Author: : Grant Ayers (ayers@cs.stanford.edu)
+#
+# Standards/Formatting:
+# MIPS gas, soft tab, 80 column
+#
+# Description:
+# Test the functionality of the 'divu' instruction.
+#
+###############################################################################
+
+
+ .section .test, "x"
+ .balign 4
+ .set noreorder
+ .global test
+ .ent test
+test:
+ lui $s0, 0xbfff # Load the base address 0xbffffff0
+ ori $s0, 0xfff0
+ ori $s1, $0, 1 # Prepare the 'done' status
+
+ #### Test code start ####
+
+ lui $t0, 0x1234
+ ori $t0, 0x5678
+ lui $t1, 0xc001
+ ori $t1, 0xcafe
+ divu $t1, $t0 # 0xa (q), 0x09f66a4e (r)
+ mfhi $t2
+ mflo $t3
+ lui $t4, 0x09f6
+ ori $t4, 0x6a4e
+ lui $t5, 0x0000
+ ori $t5, 0x000a
+ subu $t6, $t2, $t4
+ subu $t7, $t3, $t5
+ sltiu $v0, $t6, 1
+ sltiu $v1, $t7, 1
+ and $v0, $v0, $v1
+
+ #### Test code end ####
+
+ sw $v0, 8($s0) # Set the test result
+ sw $s1, 4($s0) # Set 'done'
+
+$done:
+ jr $ra
+ nop
+
+ .end test
diff --git a/crates/mipsevm/open_mips_tests/test/exit_group.asm b/crates/mipsevm/open_mips_tests/test/exit_group.asm
new file mode 100644
index 0000000..5792168
--- /dev/null
+++ b/crates/mipsevm/open_mips_tests/test/exit_group.asm
@@ -0,0 +1,29 @@
+.section .test, "x"
+ .balign 4
+ .set noreorder
+ .global test
+ .ent test
+
+test:
+ li $a0, 1
+ li $v0, 4246
+ syscall
+
+ # Unreachable ....
+ # set test result to fail.
+ # Test runner should short-circuit before reaching this point.
+ li $v0, 0
+
+ # save results
+ lui $s0, 0xbfff # Load the base address 0xbffffff0
+ ori $s0, 0xfff0
+ ori $s1, $0, 1 # Prepare the 'done' status
+
+ sw $v0, 8($s0) # Set the test result
+ sw $s1, 4($s0) # Set 'done'
+
+$done:
+ jr $ra
+ nop
+
+ .end test
diff --git a/crates/mipsevm/open_mips_tests/test/fcntl.asm b/crates/mipsevm/open_mips_tests/test/fcntl.asm
new file mode 100644
index 0000000..451e90a
--- /dev/null
+++ b/crates/mipsevm/open_mips_tests/test/fcntl.asm
@@ -0,0 +1,27 @@
+.section .test, "x"
+ .balign 4
+ .set noreorder
+ .global test
+ .ent test
+
+test:
+ # fnctl(0, 3)
+ li $v0, 4055
+ li $a0, 0x0
+ li $a1, 0x3
+ syscall
+ sltiu $v0, $v0, 1
+
+# save results
+ lui $s0, 0xbfff # Load the base address 0xbffffff0
+ ori $s0, 0xfff0
+ ori $s1, $0, 1 # Prepare the 'done' status
+
+ sw $v0, 8($s0) # Set the test result
+ sw $s1, 4($s0) # Set 'done'
+
+$done:
+ jr $ra
+ nop
+
+ .end test
diff --git a/crates/mipsevm/open_mips_tests/test/j.asm b/crates/mipsevm/open_mips_tests/test/j.asm
new file mode 100644
index 0000000..96fbde2
--- /dev/null
+++ b/crates/mipsevm/open_mips_tests/test/j.asm
@@ -0,0 +1,45 @@
+###############################################################################
+# File : j.asm
+# Project : MIPS32 MUX
+# Author: : Grant Ayers (ayers@cs.stanford.edu)
+#
+# Standards/Formatting:
+# MIPS gas, soft tab, 80 column
+#
+# Description:
+# Test the functionality of the 'j' instruction.
+#
+###############################################################################
+
+
+ .section .test, "x"
+ .balign 4
+ .set noreorder
+ .global test
+ .ent test
+test:
+ lui $s0, 0xbfff # Load the base address 0xbffffff0
+ ori $s0, 0xfff0
+ ori $s1, $0, 1 # Prepare the 'done' status
+
+ #### Test code start ####
+
+ j $target
+ ori $v0, $0, 0 # The test result starts as a failure
+
+$finish:
+ sw $v0, 8($s0)
+ sw $s1, 4($s0)
+ jr $ra
+ nop
+ j $finish # Early-by-1 detection
+
+$target:
+ nop
+ ori $v0, $0, 1 # Set the result to pass
+ j $finish # Late-by 1 detection (result not written)
+ nop
+
+ #### Test code end ####
+
+ .end test
diff --git a/crates/mipsevm/open_mips_tests/test/jal.asm b/crates/mipsevm/open_mips_tests/test/jal.asm
new file mode 100644
index 0000000..584022c
--- /dev/null
+++ b/crates/mipsevm/open_mips_tests/test/jal.asm
@@ -0,0 +1,47 @@
+###############################################################################
+# File : jal.asm
+# Project : MIPS32 MUX
+# Author: : Grant Ayers (ayers@cs.stanford.edu)
+#
+# Standards/Formatting:
+# MIPS gas, soft tab, 80 column
+#
+# Description:
+# Test the functionality of the 'jal' instruction.
+#
+###############################################################################
+
+
+ .section .test, "x"
+ .balign 4
+ .set noreorder
+ .global test
+ .ent test
+test:
+ lui $s0, 0xbfff # Load the base address 0xbffffff0
+ ori $s0, 0xfff0
+ ori $s1, $0, 1 # Prepare the 'done' status
+
+ #### Test code start ####
+
+ ori $v1, $ra, 0 # Save $ra
+ jal $target
+ ori $v0, $0, 0 # The test result starts as a failure
+
+$finish:
+ sw $v0, 8($s0)
+ ori $ra, $v1, 0 # Restore $ra
+ sw $s1, 4($s0)
+ jr $ra
+ nop
+ j $finish # Early-by-1 detection
+
+$target:
+ nop
+ ori $v0, $0, 1 # Set the result to pass
+ jr $ra
+ nop
+
+ #### Test code end ####
+
+ .end test
diff --git a/crates/mipsevm/open_mips_tests/test/jalr.asm b/crates/mipsevm/open_mips_tests/test/jalr.asm
new file mode 100644
index 0000000..c8c03d0
--- /dev/null
+++ b/crates/mipsevm/open_mips_tests/test/jalr.asm
@@ -0,0 +1,48 @@
+###############################################################################
+# File : jalr.asm
+# Project : MIPS32 MUX
+# Author: : Grant Ayers (ayers@cs.stanford.edu)
+#
+# Standards/Formatting:
+# MIPS gas, soft tab, 80 column
+#
+# Description:
+# Test the functionality of the 'jalr' instruction.
+#
+###############################################################################
+
+
+ .section .test, "x"
+ .balign 4
+ .set noreorder
+ .global test
+ .ent test
+test:
+ lui $s0, 0xbfff # Load the base address 0xbffffff0
+ ori $s0, 0xfff0
+ ori $s1, $0, 1 # Prepare the 'done' status
+
+ #### Test code start ####
+
+ ori $v1, $ra, 0 # Save $ra
+ la $t0, $target
+ jalr $t0
+ ori $v0, $0, 0 # The test result starts as a failure
+
+$finish:
+ sw $v0, 8($s0)
+ ori $ra, $v1, 0 # Restore $ra
+ sw $s1, 4($s0)
+ jr $ra
+ nop
+ j $finish # Early-by-1 detection
+
+$target:
+ nop
+ ori $v0, $0, 1 # Set the result to pass
+ jr $ra
+ nop
+
+ #### Test code end ####
+
+ .end test
diff --git a/crates/mipsevm/open_mips_tests/test/jr.asm b/crates/mipsevm/open_mips_tests/test/jr.asm
new file mode 100644
index 0000000..3832702
--- /dev/null
+++ b/crates/mipsevm/open_mips_tests/test/jr.asm
@@ -0,0 +1,46 @@
+###############################################################################
+# File : jr.asm
+# Project : MIPS32 MUX
+# Author: : Grant Ayers (ayers@cs.stanford.edu)
+#
+# Standards/Formatting:
+# MIPS gas, soft tab, 80 column
+#
+# Description:
+# Test the functionality of the 'jr' instruction.
+#
+###############################################################################
+
+
+ .section .test, "x"
+ .balign 4
+ .set noreorder
+ .global test
+ .ent test
+test:
+ lui $s0, 0xbfff # Load the base address 0xbffffff0
+ ori $s0, 0xfff0
+ ori $s1, $0, 1 # Prepare the 'done' status
+
+ #### Test code start ####
+
+ la $t0, $target
+ jr $t0
+ ori $v0, $0, 0 # The test result starts as a failure
+
+$finish:
+ sw $v0, 8($s0)
+ sw $s1, 4($s0)
+ jr $ra
+ nop
+ j $finish # Early-by-1 detection
+
+$target:
+ nop
+ ori $v0, $0, 1 # Set the result to pass
+ j $finish
+ nop
+
+ #### Test code end ####
+
+ .end test
diff --git a/crates/mipsevm/open_mips_tests/test/lb.asm b/crates/mipsevm/open_mips_tests/test/lb.asm
new file mode 100644
index 0000000..9b44d3e
--- /dev/null
+++ b/crates/mipsevm/open_mips_tests/test/lb.asm
@@ -0,0 +1,116 @@
+###############################################################################
+# File : lb.asm
+# Project : MIPS32 MUX
+# Author: : Grant Ayers (ayers@cs.stanford.edu)
+#
+# Standards/Formatting:
+# MIPS gas, soft tab, 80 column
+#
+# Description:
+# Test the functionality of the 'lb' instruction.
+#
+###############################################################################
+
+
+ .section .test, "x"
+ .balign 4
+ .set noreorder
+ .global test
+ .ent test
+test:
+ lui $s0, 0xbfff # Load the base address 0xbffffff0
+ ori $s0, 0xfff0
+ ori $s1, $0, 1 # Prepare the 'done' status
+
+ #### Test code start ####
+
+ lui $t0, 0xbfc0 # Load address 0xbfc007fc (last word in 2KB starting
+ ori $t0, 0x07fc # from 0xbfc00000)
+ lui $t1, 0xc001
+ ori $t1, 0x7afe
+ sw $t1, 0($t0)
+ lb $t2, 0($t0)
+ lb $t3, 1($t0)
+ lb $t4, 2($t0)
+ lb $t5, 3($t0)
+ .ifdef big_endian
+ lui $t6, 0xffff
+ ori $t6, 0xffc0
+ lui $t7, 0x0000
+ ori $t7, 0x0001
+ lui $t8, 0x0000
+ ori $t8, 0x007a
+ lui $t9, 0xffff
+ ori $t9, 0xfffe
+ .else
+ lui $t6, 0xffff
+ ori $t6, 0xfffe
+ lui $t7, 0x0000
+ ori $t7, 0x007a
+ lui $t8, 0x0000
+ ori $t8, 0x0001
+ lui $t9, 0xffff
+ ori $t9, 0xffc0
+ .endif
+ subu $v1, $t2, $t6
+ sltiu $v0, $v1, 1
+ subu $v1, $t3, $t7
+ sltiu $v1, $v1, 1
+ and $v0, $v0, $v1
+ subu $v1, $t4, $t8
+ sltiu $v1, $v1, 1
+ and $v0, $v0, $v1
+ subu $v1, $t5, $t9
+ sltiu $v1, $v1, 1
+ and $v0, $v0, $v1
+
+ # Repeat with halves swapped (sign extension corner cases)
+ lui $t1, 0x7afe
+ ori $t1, 0xc001
+ sw $t1, 0($t0)
+ lb $t2, 0($t0)
+ lb $t3, 1($t0)
+ lb $t4, 2($t0)
+ lb $t5, 3($t0)
+ .ifdef big_endian
+ lui $t6, 0x0000
+ ori $t6, 0x007a
+ lui $t7, 0xffff
+ ori $t7, 0xfffe
+ lui $t8, 0xffff
+ ori $t8, 0xffc0
+ lui $t9, 0x0000
+ ori $t9, 0x0001
+ .else
+ lui $t6, 0x0000
+ ori $t6, 0x0001
+ lui $t7, 0xffff
+ ori $t7, 0xffc0
+ lui $t8, 0xffff
+ ori $t8, 0xfffe
+ lui $t9, 0x0000
+ ori $t9, 0x007a
+ .endif
+ subu $v1, $t2, $t6
+ sltiu $v1, $v1, 1
+ and $v0, $v0, $v1
+ subu $v1, $t3, $t7
+ sltiu $v1, $v1, 1
+ and $v0, $v0, $v1
+ subu $v1, $t4, $t8
+ sltiu $v1, $v1, 1
+ and $v0, $v0, $v1
+ subu $v1, $t5, $t9
+ sltiu $v1, $v1, 1
+ and $v0, $v0, $v1
+
+ #### Test code end ####
+
+ sw $v0, 8($s0) # Set the test result
+ sw $s1, 4($s0) # Set 'done'
+
+$done:
+ jr $ra
+ nop
+
+ .end test
diff --git a/crates/mipsevm/open_mips_tests/test/lbu.asm b/crates/mipsevm/open_mips_tests/test/lbu.asm
new file mode 100644
index 0000000..9cda9fd
--- /dev/null
+++ b/crates/mipsevm/open_mips_tests/test/lbu.asm
@@ -0,0 +1,68 @@
+###############################################################################
+# File : lbu.asm
+# Project : MIPS32 MUX
+# Author: : Grant Ayers (ayers@cs.stanford.edu)
+#
+# Standards/Formatting:
+# MIPS gas, soft tab, 80 column
+#
+# Description:
+# Test the functionality of the 'lbu' instruction.
+#
+###############################################################################
+
+
+ .section .test, "x"
+ .balign 4
+ .set noreorder
+ .global test
+ .ent test
+test:
+ lui $s0, 0xbfff # Load the base address 0xbffffff0
+ ori $s0, 0xfff0
+ ori $s1, $0, 1 # Prepare the 'done' status
+
+ #### Test code start ####
+
+ lui $t0, 0xbfc0 # Load address 0xbfc007fc (last word in 2KB starting
+ ori $t0, 0x07fc # from 0xbfc00000)
+ lui $t1, 0xc001
+ ori $t1, 0x7afe
+ sw $t1, 0($t0)
+ lbu $t2, 0($t0)
+ lbu $t3, 1($t0)
+ lbu $t4, 2($t0)
+ lbu $t5, 3($t0)
+ .ifdef big_endian
+ ori $t6, $0, 0x00c0
+ ori $t7, $0, 0x0001
+ ori $t8, $0, 0x007a
+ ori $t9, $0, 0x00fe
+ .else
+ ori $t6, $0, 0x00fe
+ ori $t7, $0, 0x007a
+ ori $t8, $0, 0x0001
+ ori $t9, $0, 0x00c0
+ .endif
+ subu $v1, $t2, $t6
+ sltiu $v0, $v1, 1
+ subu $v1, $t3, $t7
+ sltiu $v1, $v1, 1
+ and $v0, $v0, $v1
+ subu $v1, $t4, $t8
+ sltiu $v1, $v1, 1
+ and $v0, $v0, $v1
+ subu $v1, $t5, $t9
+ sltiu $v1, $v1, 1
+ and $v0, $v0, $v1
+
+ #### Test code end ####
+
+ sw $v0, 8($s0) # Set the test result
+ sw $s1, 4($s0) # Set 'done'
+
+$done:
+ jr $ra
+ nop
+
+ .end test
diff --git a/crates/mipsevm/open_mips_tests/test/lh.asm b/crates/mipsevm/open_mips_tests/test/lh.asm
new file mode 100644
index 0000000..8b4d4b2
--- /dev/null
+++ b/crates/mipsevm/open_mips_tests/test/lh.asm
@@ -0,0 +1,84 @@
+###############################################################################
+# File : lh.asm
+# Project : MIPS32 MUX
+# Author: : Grant Ayers (ayers@cs.stanford.edu)
+#
+# Standards/Formatting:
+# MIPS gas, soft tab, 80 column
+#
+# Description:
+# Test the functionality of the 'lh' instruction.
+#
+###############################################################################
+
+
+ .section .test, "x"
+ .balign 4
+ .set noreorder
+ .global test
+ .ent test
+test:
+ lui $s0, 0xbfff # Load the base address 0xbffffff0
+ ori $s0, 0xfff0
+ ori $s1, $0, 1 # Prepare the 'done' status
+
+ #### Test code start ####
+
+ lui $t0, 0xbfc0 # Load address 0xbfc007fc (last word in 2KB starting
+ ori $t0, 0x07fc # from 0xbfc00000)
+ lui $t1, 0x7001
+ ori $t1, 0xcafe
+ sw $t1, 0($t0)
+ lh $t2, 0($t0)
+ lh $t3, 2($t0)
+ .ifdef big_endian
+ lui $t4, 0x0000
+ ori $t4, 0x7001
+ lui $t5, 0xffff
+ ori $t5, 0xcafe
+ .else
+ lui $t4, 0xffff
+ ori $t4, 0xcafe
+ lui $t5, 0x0000
+ ori $t5, 0x7001
+ .endif
+ subu $v1, $t2, $t4
+ sltiu $v0, $v1, 1
+ subu $v1, $t3, $t5
+ sltiu $v1, $v1, 1
+ and $v0, $v0, $v1
+
+ # Repeat with halves swapped (sign extension corner cases)
+ lui $t1, 0xcafe
+ ori $t1, 0x7001
+ sw $t1, 0($t0)
+ lh $t2, 0($t0)
+ lh $t3, 2($t0)
+ .ifdef big_endian
+ lui $t4, 0xffff
+ ori $t4, 0xcafe
+ lui $t5, 0x0000
+ ori $t5, 0x7001
+ .else
+ lui $t4, 0x0000
+ ori $t4, 0x7001
+ lui $t5, 0xffff
+ ori $t5, 0xcafe
+ .endif
+ subu $v1, $t2, $t4
+ sltiu $v1, $v1, 1
+ and $v0, $v0, $v1
+ subu $v1, $t3, $t5
+ sltiu $v1, $v1, 1
+ and $v0, $v0, $v1
+
+ #### Test code end ####
+
+ sw $v0, 8($s0) # Set the test result
+ sw $s1, 4($s0) # Set 'done'
+
+$done:
+ jr $ra
+ nop
+
+ .end test
diff --git a/crates/mipsevm/open_mips_tests/test/lhu.asm b/crates/mipsevm/open_mips_tests/test/lhu.asm
new file mode 100644
index 0000000..615ae37
--- /dev/null
+++ b/crates/mipsevm/open_mips_tests/test/lhu.asm
@@ -0,0 +1,76 @@
+###############################################################################
+# File : lhu.asm
+# Project : MIPS32 MUX
+# Author: : Grant Ayers (ayers@cs.stanford.edu)
+#
+# Standards/Formatting:
+# MIPS gas, soft tab, 80 column
+#
+# Description:
+# Test the functionality of the 'lhu' instruction.
+#
+###############################################################################
+
+
+ .section .test, "x"
+ .balign 4
+ .set noreorder
+ .global test
+ .ent test
+test:
+ lui $s0, 0xbfff # Load the base address 0xbffffff0
+ ori $s0, 0xfff0
+ ori $s1, $0, 1 # Prepare the 'done' status
+
+ #### Test code start ####
+
+ lui $t0, 0xbfc0 # Load address 0xbfc007fc (last word in 2KB starting
+ ori $t0, 0x07fc # from 0xbfc00000)
+ lui $t1, 0x7001
+ ori $t1, 0xcafe
+ sw $t1, 0($t0)
+ lhu $t2, 0($t0)
+ lhu $t3, 2($t0)
+ .ifdef big_endian
+ ori $t4, $0, 0x7001
+ ori $t5, $0, 0xcafe
+ .else
+ ori $t4, $0, 0xcafe
+ ori $t5, $0, 0x7001
+ .endif
+ subu $v1, $t2, $t4
+ sltiu $v0, $v1, 1
+ subu $v1, $t3, $t5
+ sltiu $v1, $v1, 1
+ and $v0, $v0, $v1
+
+ # Repeat with halves swapped (sign extension corner cases)
+ lui $t1, 0xcafe
+ ori $t1, 0x7001
+ sw $t1, 0($t0)
+ lhu $t2, 0($t0)
+ lhu $t3, 2($t0)
+ .ifdef big_endian
+ ori $t4, $0, 0xcafe
+ ori $t5, $0, 0x7001
+ .else
+ ori $t4, $0, 0x7001
+ ori $t5, $0, 0xcafe
+ .endif
+ subu $v1, $t2, $t4
+ sltiu $v1, $v1, 1
+ and $v0, $v0, $v1
+ subu $v1, $t3, $t5
+ sltiu $v1, $v1, 1
+ and $v0, $v0, $v1
+
+ #### Test code end ####
+
+ sw $v0, 8($s0) # Set the test result
+ sw $s1, 4($s0) # Set 'done'
+
+$done:
+ jr $ra
+ nop
+
+ .end test
diff --git a/crates/mipsevm/open_mips_tests/test/lui.asm b/crates/mipsevm/open_mips_tests/test/lui.asm
new file mode 100644
index 0000000..f7934d9
--- /dev/null
+++ b/crates/mipsevm/open_mips_tests/test/lui.asm
@@ -0,0 +1,38 @@
+###############################################################################
+# File : lui.asm
+# Project : MIPS32 MUX
+# Author: : Grant Ayers (ayers@cs.stanford.edu)
+#
+# Standards/Formatting:
+# MIPS gas, soft tab, 80 column
+#
+# Description:
+# Test the functionality of the 'lui' instruction.
+#
+###############################################################################
+
+
+ .section .test, "x"
+ .balign 4
+ .set noreorder
+ .global test
+ .ent test
+test:
+ lui $s0, 0xbfff # Load the base address 0xbffffff0
+ ori $s0, 0xfff0
+ ori $s1, $0, 1 # Prepare the 'done' status
+
+ #### Test code start ####
+
+ ori $v0, $0, 1
+
+ #### Test code end ####
+
+ sw $v0, 8($s0) # Set the test result
+ sw $s1, 4($s0) # Set 'done'
+
+$done:
+ jr $ra
+ nop
+
+ .end test
diff --git a/crates/mipsevm/open_mips_tests/test/lw.asm b/crates/mipsevm/open_mips_tests/test/lw.asm
new file mode 100644
index 0000000..bba415b
--- /dev/null
+++ b/crates/mipsevm/open_mips_tests/test/lw.asm
@@ -0,0 +1,43 @@
+###############################################################################
+# File : lw.asm
+# Project : MIPS32 MUX
+# Author: : Grant Ayers (ayers@cs.stanford.edu)
+#
+# Standards/Formatting:
+# MIPS gas, soft tab, 80 column
+#
+# Description:
+# Test the functionality of the 'lw' instruction.
+#
+###############################################################################
+
+
+ .section .test, "x"
+ .balign 4
+ .set noreorder
+ .global test
+ .ent test
+test:
+ lui $s0, 0xbfff # Load the base address 0xbffffff0
+ ori $s0, 0xfff0
+ ori $s1, $0, 1 # Prepare the 'done' status
+
+ #### Test code start ####
+
+ lui $t0, 0xbfc0 # Load a valid address (last word in 2KB starting
+ ori $t0, 0x07fc # from 0xbfc00000)
+ sw $0, 0($t0)
+ ori $t1, $0, 1
+ sw $t1, 0($t0)
+ lw $v0, 0($t0)
+
+ #### Test code end ####
+
+ sw $v0, 8($s0) # Set the test result
+ sw $s1, 4($s0) # Set 'done'
+
+$done:
+ jr $ra
+ nop
+
+ .end test
diff --git a/crates/mipsevm/open_mips_tests/test/lwl.asm b/crates/mipsevm/open_mips_tests/test/lwl.asm
new file mode 100644
index 0000000..e7455de
--- /dev/null
+++ b/crates/mipsevm/open_mips_tests/test/lwl.asm
@@ -0,0 +1,82 @@
+###############################################################################
+# File : lwl.asm
+# Project : MIPS32 MUX
+# Author: : Grant Ayers (ayers@cs.stanford.edu)
+#
+# Standards/Formatting:
+# MIPS gas, soft tab, 80 column
+#
+# Description:
+# Test the functionality of the 'lwl' instruction.
+#
+###############################################################################
+
+
+ .section .test, "x"
+ .balign 4
+ .set noreorder
+ .global test
+ .ent test
+test:
+ lui $s0, 0xbfff # Load the base address 0xbffffff0
+ ori $s0, 0xfff0
+ ori $s1, $0, 1 # Prepare the 'done' status
+
+ #### Test code start ####
+
+ lui $t0, 0xbfc0 # Load address 0xbfc007fc (last word in 2KB starting
+ ori $t0, 0x07fc # from 0xbfc00000)
+ lui $t1, 0xc001 # Memory word is 0xc001cafe
+ ori $t1, 0xcafe
+ sw $t1, 0($t0)
+ lui $t2, 0xdeaf # Register word is 0xdeafbeef
+ ori $t2, 0xbeef
+ or $t3, $0, $t2
+ or $t4, $0, $t2
+ or $t5, $0, $t2
+ or $t6, $0, $t2
+ lwl $t3, 0($t0)
+ lwl $t4, 1($t0)
+ lwl $t5, 2($t0)
+ lwl $t6, 3($t0)
+ .ifdef big_endian
+ lui $s3, 0xc001 # 0xc001cafe
+ ori $s3, 0xcafe
+ lui $s4, 0x01ca # 0x01cafeef
+ ori $s4, 0xfeef
+ lui $s5, 0xcafe # 0xcafebeef
+ ori $s5, 0xbeef
+ lui $s6, 0xfeaf # 0xfeafbeef
+ ori $s6, 0xbeef
+ .else
+ lui $s3, 0xfeaf # 0xfeafbeef
+ ori $s3, 0xbeef
+ lui $s4, 0xcafe # 0xcafebeef
+ ori $s4, 0xbeef
+ lui $s5, 0x01ca # 0x01cafeef
+ ori $s5, 0xfeef
+ lui $s6, 0xc001 # 0xc001cafe
+ ori $s6, 0xcafe
+ .endif
+ subu $s2, $t3, $s3
+ sltiu $v0, $s2, 1
+ subu $s2, $t4, $s4
+ sltiu $v1, $s2, 1
+ and $v0, $v0, $v1
+ subu $s2, $t5, $s5
+ sltiu $v1, $s2, 1
+ and $v0, $v0, $v1
+ subu $s2, $t6, $s6
+ sltiu $v1, $s2, 1
+ and $v0, $v0, $v1
+
+ #### Test code end ####
+
+ sw $v0, 8($s0) # Set the test result
+ sw $s1, 4($s0) # Set 'done'
+
+$done:
+ jr $ra
+ nop
+
+ .end test
diff --git a/crates/mipsevm/open_mips_tests/test/lwr.asm b/crates/mipsevm/open_mips_tests/test/lwr.asm
new file mode 100644
index 0000000..a07ab0d
--- /dev/null
+++ b/crates/mipsevm/open_mips_tests/test/lwr.asm
@@ -0,0 +1,82 @@
+###############################################################################
+# File : lwr.asm
+# Project : MIPS32 MUX
+# Author: : Grant Ayers (ayers@cs.stanford.edu)
+#
+# Standards/Formatting:
+# MIPS gas, soft tab, 80 column
+#
+# Description:
+# Test the functionality of the 'lwr' instruction.
+#
+###############################################################################
+
+
+ .section .test, "x"
+ .balign 4
+ .set noreorder
+ .global test
+ .ent test
+test:
+ lui $s0, 0xbfff # Load the base address 0xbffffff0
+ ori $s0, 0xfff0
+ ori $s1, $0, 1 # Prepare the 'done' status
+
+ #### Test code start ####
+
+ lui $t0, 0xbfc0 # Load address 0xbfc007fc (last word in 2KB starting
+ ori $t0, 0x07fc # from 0xbfc00000)
+ lui $t1, 0xc001 # Memory word is 0xc001cafe
+ ori $t1, 0xcafe
+ sw $t1, 0($t0)
+ lui $t2, 0xdeaf # Register word is 0xdeafbeef
+ ori $t2, 0xbeef
+ or $t3, $0, $t2
+ or $t4, $0, $t2
+ or $t5, $0, $t2
+ or $t6, $0, $t2
+ lwr $t3, 0($t0)
+ lwr $t4, 1($t0)
+ lwr $t5, 2($t0)
+ lwr $t6, 3($t0)
+ .ifdef big_endian
+ lui $s3, 0xdeaf # 0xdeafbec0
+ ori $s3, 0xbec0
+ lui $s4, 0xdeaf # 0xdeafc001
+ ori $s4, 0xc001
+ lui $s5, 0xdec0 # 0xdec001ca
+ ori $s5, 0x01ca
+ lui $s6, 0xc001 # 0xc001cafe
+ ori $s6, 0xcafe
+ .else
+ lui $s3, 0xc001 # 0xc001cafe
+ ori $s3, 0xcafe
+ lui $s4, 0xdec0 # 0xdec001ca
+ ori $s4, 0x01ca
+ lui $s5, 0xdeaf # 0xdeafc001
+ ori $s5, 0xc001
+ lui $s6, 0xdeaf # 0xdeafbec0
+ ori $s6, 0xbec0
+ .endif
+ subu $s2, $t3, $s3
+ sltiu $v0, $s2, 1
+ subu $s2, $t4, $s4
+ sltiu $v1, $s2, 1
+ and $v0, $v0, $v1
+ subu $s2, $t5, $s5
+ sltiu $v1, $s2, 1
+ and $v0, $v0, $v1
+ subu $s2, $t6, $s6
+ sltiu $v1, $s2, 1
+ and $v0, $v0, $v1
+
+ #### Test code end ####
+
+ sw $v0, 8($s0) # Set the test result
+ sw $s1, 4($s0) # Set 'done'
+
+$done:
+ jr $ra
+ nop
+
+ .end test
diff --git a/crates/mipsevm/open_mips_tests/test/mfthi.asm b/crates/mipsevm/open_mips_tests/test/mfthi.asm
new file mode 100644
index 0000000..890f6fd
--- /dev/null
+++ b/crates/mipsevm/open_mips_tests/test/mfthi.asm
@@ -0,0 +1,43 @@
+###############################################################################
+# File : mfthi.asm
+# Project : MIPS32 MUX
+# Author: : Grant Ayers (ayers@cs.stanford.edu)
+#
+# Standards/Formatting:
+# MIPS gas, soft tab, 80 column
+#
+# Description:
+# Test the functionality of the 'mthi' and 'mfhi' instructions.
+#
+###############################################################################
+
+
+ .section .test, "x"
+ .balign 4
+ .set noreorder
+ .global test
+ .ent test
+test:
+ lui $s0, 0xbfff # Load the base address 0xbffffff0
+ ori $s0, 0xfff0
+ ori $s1, $0, 1 # Prepare the 'done' status
+
+ #### Test code start ####
+
+ lui $t0, 0xdeaf
+ ori $t0, 0xbeef
+ mthi $t0
+ mfhi $t1
+ subu $v1, $t0, $t1
+ sltiu $v0, $v1, 1
+
+ #### Test code end ####
+
+ sw $v0, 8($s0) # Set the test result
+ sw $s1, 4($s0) # Set 'done'
+
+$done:
+ jr $ra
+ nop
+
+ .end test
diff --git a/crates/mipsevm/open_mips_tests/test/mftlo.asm b/crates/mipsevm/open_mips_tests/test/mftlo.asm
new file mode 100644
index 0000000..abbbfe4
--- /dev/null
+++ b/crates/mipsevm/open_mips_tests/test/mftlo.asm
@@ -0,0 +1,43 @@
+###############################################################################
+# File : mftlo.asm
+# Project : MIPS32 MUX
+# Author: : Grant Ayers (ayers@cs.stanford.edu)
+#
+# Standards/Formatting:
+# MIPS gas, soft tab, 80 column
+#
+# Description:
+# Test the functionality of the 'mtlo' and 'mflo' instructions.
+#
+###############################################################################
+
+
+ .section .test, "x"
+ .balign 4
+ .set noreorder
+ .global test
+ .ent test
+test:
+ lui $s0, 0xbfff # Load the base address 0xbffffff0
+ ori $s0, 0xfff0
+ ori $s1, $0, 1 # Prepare the 'done' status
+
+ #### Test code start ####
+
+ lui $t0, 0xdeaf
+ ori $t0, 0xbeef
+ mtlo $t0
+ mflo $t1
+ subu $v1, $t0, $t1
+ sltiu $v0, $v1, 1
+
+ #### Test code end ####
+
+ sw $v0, 8($s0) # Set the test result
+ sw $s1, 4($s0) # Set 'done'
+
+$done:
+ jr $ra
+ nop
+
+ .end test
diff --git a/crates/mipsevm/open_mips_tests/test/mmap.asm b/crates/mipsevm/open_mips_tests/test/mmap.asm
new file mode 100644
index 0000000..347678f
--- /dev/null
+++ b/crates/mipsevm/open_mips_tests/test/mmap.asm
@@ -0,0 +1,28 @@
+.section .test, "x"
+ .balign 4
+ .set noreorder
+ .global test
+ .ent test
+
+test:
+ li $v0, 4090
+ lui $a0, 0x3000
+ li $a1, 4096
+ syscall
+ lui $t0, 0x3000
+ subu $v0, $v0, $t0
+ sltiu $v0, $v0, 1
+
+ # save results
+ lui $s0, 0xbfff # Load the base address 0xbffffff0
+ ori $s0, 0xfff0
+ ori $s1, $0, 1 # Prepare the 'done' status
+
+ sw $v0, 8($s0) # Set the test result
+ sw $s1, 4($s0) # Set 'done'
+
+$done:
+ jr $ra
+ nop
+
+ .end test
diff --git a/crates/mipsevm/open_mips_tests/test/movn.asm b/crates/mipsevm/open_mips_tests/test/movn.asm
new file mode 100644
index 0000000..1ca6892
--- /dev/null
+++ b/crates/mipsevm/open_mips_tests/test/movn.asm
@@ -0,0 +1,46 @@
+###############################################################################
+# File : movn.asm
+# Project : MIPS32 MUX
+# Author: : Grant Ayers (ayers@cs.stanford.edu)
+#
+# Standards/Formatting:
+# MIPS gas, soft tab, 80 column
+#
+# Description:
+# Test the functionality of the 'movn' instruction.
+#
+###############################################################################
+
+
+ .section .test, "x"
+ .balign 4
+ .set noreorder
+ .global test
+ .ent test
+test:
+ lui $s0, 0xbfff # Load the base address 0xbffffff0
+ ori $s0, 0xfff0
+ ori $s1, $0, 1 # Prepare the 'done' status
+
+ #### Test code start ####
+
+ lui $t0, 0xdeaf
+ ori $t0, $t0, 0xbeef
+ ori $t1, $0, 0
+ movn $t2, $t0, $s1 # $t2 gets 0xdeafbeef
+ movn $t1, $t0, $0 # $t1 remains 0
+ subu $t3, $t2, $t0
+ sltiu $v0, $t3, 1
+ sltiu $v1, $t1, 1
+ and $v0, $v0, $v1
+
+ #### Test code end ####
+
+ sw $v0, 8($s0) # Set the test result
+ sw $s1, 4($s0) # Set 'done'
+
+$done:
+ jr $ra
+ nop
+
+ .end test
diff --git a/crates/mipsevm/open_mips_tests/test/movz.asm b/crates/mipsevm/open_mips_tests/test/movz.asm
new file mode 100644
index 0000000..1c7e0bd
--- /dev/null
+++ b/crates/mipsevm/open_mips_tests/test/movz.asm
@@ -0,0 +1,46 @@
+###############################################################################
+# File : movz.asm
+# Project : MIPS32 MUX
+# Author: : Grant Ayers (ayers@cs.stanford.edu)
+#
+# Standards/Formatting:
+# MIPS gas, soft tab, 80 column
+#
+# Description:
+# Test the functionality of the 'movz' instruction.
+#
+###############################################################################
+
+
+ .section .test, "x"
+ .balign 4
+ .set noreorder
+ .global test
+ .ent test
+test:
+ lui $s0, 0xbfff # Load the base address 0xbffffff0
+ ori $s0, 0xfff0
+ ori $s1, $0, 1 # Prepare the 'done' status
+
+ #### Test code start ####
+
+ lui $t0, 0xdeaf
+ ori $t0, $t0, 0xbeef
+ ori $t2, $0, 0
+ movz $t2, $t0, $s0 # $t2 remains 0
+ movz $t1, $t0, $0 # $t1 gets 0xdeafbeef
+ subu $t3, $t1, $t0
+ sltiu $v0, $t3, 1
+ sltiu $v1, $t2, 1
+ and $v0, $v0, $v1
+
+ #### Test code end ####
+
+ sw $v0, 8($s0) # Set the test result
+ sw $s1, 4($s0) # Set 'done'
+
+$done:
+ jr $ra
+ nop
+
+ .end test
diff --git a/crates/mipsevm/open_mips_tests/test/mul.asm b/crates/mipsevm/open_mips_tests/test/mul.asm
new file mode 100644
index 0000000..dbfc1cf
--- /dev/null
+++ b/crates/mipsevm/open_mips_tests/test/mul.asm
@@ -0,0 +1,46 @@
+###############################################################################
+# File : mul.asm
+# Project : MIPS32 MUX
+# Author: : Grant Ayers (ayers@cs.stanford.edu)
+#
+# Standards/Formatting:
+# MIPS gas, soft tab, 80 column
+#
+# Description:
+# Test the functionality of the 'mul' instruction.
+#
+###############################################################################
+
+
+ .section .test, "x"
+ .balign 4
+ .set noreorder
+ .global test
+ .ent test
+test:
+ lui $s0, 0xbfff # Load the base address 0xbffffff0
+ ori $s0, 0xfff0
+ ori $s1, $0, 1 # Prepare the 'done' status
+
+ #### Test code start ####
+
+ lui $t0, 0x1234
+ ori $t0, 0x5678
+ lui $t1, 0xc001
+ ori $t1, 0xcafe
+ mul $t2, $t0, $t1 # 0xb2a07b10
+ lui $t3, 0xb2a0
+ ori $t3, 0x7b10
+ subu $t4, $t2, $t3
+ sltiu $v0, $t4, 1
+
+ #### Test code end ####
+
+ sw $v0, 8($s0) # Set the test result
+ sw $s1, 4($s0) # Set 'done'
+
+$done:
+ jr $ra
+ nop
+
+ .end test
diff --git a/crates/mipsevm/open_mips_tests/test/mult.asm b/crates/mipsevm/open_mips_tests/test/mult.asm
new file mode 100644
index 0000000..58b65dd
--- /dev/null
+++ b/crates/mipsevm/open_mips_tests/test/mult.asm
@@ -0,0 +1,53 @@
+###############################################################################
+# File : mult.asm
+# Project : MIPS32 MUX
+# Author: : Grant Ayers (ayers@cs.stanford.edu)
+#
+# Standards/Formatting:
+# MIPS gas, soft tab, 80 column
+#
+# Description:
+# Test the functionality of the 'mult' instruction.
+#
+###############################################################################
+
+
+ .section .test, "x"
+ .balign 4
+ .set noreorder
+ .global test
+ .ent test
+test:
+ lui $s0, 0xbfff # Load the base address 0xbffffff0
+ ori $s0, 0xfff0
+ ori $s1, $0, 1 # Prepare the 'done' status
+
+ #### Test code start ####
+
+ lui $t0, 0x1234
+ ori $t0, 0x5678
+ lui $t1, 0xc001
+ ori $t1, 0xcafe
+ mult $t0, $t1 # 0xfb730b05b2a07b10
+ mfhi $t2
+ mflo $t3
+ lui $t4, 0xfb73
+ ori $t4, 0x0b05
+ lui $t5, 0xb2a0
+ ori $t5, 0x7b10
+ subu $t6, $t2, $t4
+ subu $t7, $t3, $t5
+ sltiu $v0, $t6, 1
+ sltiu $v1, $t7, 1
+ and $v0, $v0, $v1
+
+ #### Test code end ####
+
+ sw $v0, 8($s0) # Set the test result
+ sw $s1, 4($s0) # Set 'done'
+
+$done:
+ jr $ra
+ nop
+
+ .end test
diff --git a/crates/mipsevm/open_mips_tests/test/multu.asm b/crates/mipsevm/open_mips_tests/test/multu.asm
new file mode 100644
index 0000000..9000511
--- /dev/null
+++ b/crates/mipsevm/open_mips_tests/test/multu.asm
@@ -0,0 +1,53 @@
+###############################################################################
+# File : multu.asm
+# Project : MIPS32 MUX
+# Author: : Grant Ayers (ayers@cs.stanford.edu)
+#
+# Standards/Formatting:
+# MIPS gas, soft tab, 80 column
+#
+# Description:
+# Test the functionality of the 'multu' instruction.
+#
+###############################################################################
+
+
+ .section .test, "x"
+ .balign 4
+ .set noreorder
+ .global test
+ .ent test
+test:
+ lui $s0, 0xbfff # Load the base address 0xbffffff0
+ ori $s0, 0xfff0
+ ori $s1, $0, 1 # Prepare the 'done' status
+
+ #### Test code start ####
+
+ lui $t0, 0x1234
+ ori $t0, 0x5678
+ lui $t1, 0xc001
+ ori $t1, 0xcafe
+ multu $t0, $t1 # 0x0da7617db2a07b10
+ mfhi $t2
+ mflo $t3
+ lui $t4, 0x0da7
+ ori $t4, 0x617d
+ lui $t5, 0xb2a0
+ ori $t5, 0x7b10
+ subu $t6, $t2, $t4
+ subu $t7, $t3, $t5
+ sltiu $v0, $t6, 1
+ sltiu $v1, $t7, 1
+ and $v0, $v0, $v1
+
+ #### Test code end ####
+
+ sw $v0, 8($s0) # Set the test result
+ sw $s1, 4($s0) # Set 'done'
+
+$done:
+ jr $ra
+ nop
+
+ .end test
diff --git a/crates/mipsevm/open_mips_tests/test/nor.asm b/crates/mipsevm/open_mips_tests/test/nor.asm
new file mode 100644
index 0000000..1ad0aca
--- /dev/null
+++ b/crates/mipsevm/open_mips_tests/test/nor.asm
@@ -0,0 +1,45 @@
+###############################################################################
+# File : nor.asm
+# Project : MIPS32 MUX
+# Author: : Grant Ayers (ayers@cs.stanford.edu)
+#
+# Standards/Formatting:
+# MIPS gas, soft tab, 80 column
+#
+# Description:
+# Test the functionality of the 'nor' instruction.
+#
+###############################################################################
+
+
+ .section .test, "x"
+ .balign 4
+ .set noreorder
+ .global test
+ .ent test
+test:
+ lui $s0, 0xbfff # Load the base address 0xbffffff0
+ ori $s0, 0xfff0
+ ori $s1, $0, 1 # Prepare the 'done' status
+
+ #### Test code start ####
+
+ lui $t0, 0xdeaf # A = 0xdeafbeef
+ ori $t0, $t0, 0xbeef
+ lui $t1, 0x3141 # B = 0x31415926
+ ori $t1, $t1, 0x5926
+ lui $t2, 0xffff # C = 0xfffffffe
+ ori $t2, $t2, 0xfffe
+ nor $t3, $t0, $t1 # D = nor(A,B) = 0x00100010
+ nor $v0, $t2, $t3 # E = nor(C,D) = 0x1
+
+ #### Test code end ####
+
+ sw $v0, 8($s0) # Set the test result
+ sw $s1, 4($s0) # Set 'done'
+
+$done:
+ jr $ra
+ nop
+
+ .end test
diff --git a/crates/mipsevm/open_mips_tests/test/oracle.asm b/crates/mipsevm/open_mips_tests/test/oracle.asm
new file mode 100644
index 0000000..c306f6d
--- /dev/null
+++ b/crates/mipsevm/open_mips_tests/test/oracle.asm
@@ -0,0 +1,110 @@
+.section .test, "x"
+ .balign 4
+ .set noreorder
+ .global test
+ .ent test
+
+# load hash at 0x30001000
+# 0x47173285 a8d7341e 5e972fc6 77286384 f802f8ef 42a5ec5f 03bbfa25 4cb01fad = keccak("hello world")
+# 0x02173285 a8d7341e 5e972fc6 77286384 f802f8ef 42a5ec5f 03bbfa25 4cb01fad = keccak("hello world").key
+test:
+ lui $s0, 0x3000
+ ori $s0, 0x1000
+
+ lui $t0, 0x0217
+ ori $t0, 0x3285
+ sw $t0, 0($s0)
+ lui $t0, 0xa8d7
+ ori $t0, 0x341e
+ sw $t0, 4($s0)
+ lui $t0, 0x5e97
+ ori $t0, 0x2fc6
+ sw $t0, 8($s0)
+ lui $t0, 0x7728
+ ori $t0, 0x6384
+ sw $t0, 0xc($s0)
+ lui $t0, 0xf802
+ ori $t0, 0xf8ef
+ sw $t0, 0x10($s0)
+ lui $t0, 0x42a5
+ ori $t0, 0xec5f
+ sw $t0, 0x14($s0)
+ lui $t0, 0x03bb
+ ori $t0, 0xfa25
+ sw $t0, 0x18($s0)
+ lui $t0, 0x4cb0
+ ori $t0, 0x1fad
+ sw $t0, 0x1c($s0)
+
+# preimage request - write(fdPreimageWrite, preimageData, 32)
+ li $a0, 6
+ li $a1, 0x30001000
+ li $t0, 8
+ li $a2, 4
+$writeloop:
+ li $v0, 4004
+ syscall
+ addiu $a1, $a1, 4
+ addiu $t0, $t0, -1
+ bnez $t0, $writeloop
+ nop
+
+# preimage response to 0x30002000 - read(fdPreimageRead, addr, count)
+# read preimage length
+ li $a0, 5
+ li $a1, 0x31000000
+ li $a2, 4
+ li $v0, 4003
+ syscall
+ li $a1, 0x31000004
+ li $v0, 4003
+ syscall
+# read the preimage data
+ li $a1, 0x31000008
+ li $t0, 3
+$readloop:
+ li $v0, 4003
+ syscall
+ addiu $a1, $a1, 4
+ addiu $t0, $t0, -1
+ bnez $t0, $readloop
+ nop
+# reading the pre-image stream at EOF should have no effect
+ li $a1, 0x31000008
+ li $v0, 4003
+ syscall
+
+# length at 0x31000000. We also check that the lower 32 bits are zero
+ lui $s1, 0x3100
+ lw $t0, 0($s1)
+ sltiu $t6, $t0, 1
+ li $s1, 0x31000004
+ lw $t0, 0($s1)
+# should be len("hello world") == 11
+ li $t4, 11
+ subu $t5, $t0, $t4
+ sltiu $v0, $t5, 1
+ and $v0, $v0, $t6
+
+# data at 0x31000008
+ lw $t0, 4($s1)
+ lui $t4, 0x6865
+ ori $t4, 0x6c6c
+ subu $t5, $t0, $t4
+ sltiu $v1, $t5, 1
+
+ and $v0, $v0, $v1
+
+# save results
+ lui $s0, 0xbfff # Load the base address 0xbffffff0
+ ori $s0, 0xfff0
+ ori $s1, $0, 1 # Prepare the 'done' status
+
+ sw $v0, 8($s0) # Set the test result
+ sw $s1, 4($s0) # Set 'done'
+
+$done:
+ jr $ra
+ nop
+
+ .end test
diff --git a/crates/mipsevm/open_mips_tests/test/oracle_unaligned_read.asm b/crates/mipsevm/open_mips_tests/test/oracle_unaligned_read.asm
new file mode 100644
index 0000000..df47f44
--- /dev/null
+++ b/crates/mipsevm/open_mips_tests/test/oracle_unaligned_read.asm
@@ -0,0 +1,137 @@
+.section .test, "x"
+ .balign 4
+ .set noreorder
+ .global test
+ .ent test
+
+# load hash at 0x30001000
+# 0x47173285 a8d7341e 5e972fc6 77286384 f802f8ef 42a5ec5f 03bbfa25 4cb01fad = keccak("hello world")
+# 0x02173285 a8d7341e 5e972fc6 77286384 f802f8ef 42a5ec5f 03bbfa25 4cb01fad = keccak("hello world").key
+test:
+ lui $s0, 0x3000
+ ori $s0, 0x1000
+
+ lui $t0, 0x0217
+ ori $t0, 0x3285
+ sw $t0, 0($s0)
+ lui $t0, 0xa8d7
+ ori $t0, 0x341e
+ sw $t0, 4($s0)
+ lui $t0, 0x5e97
+ ori $t0, 0x2fc6
+ sw $t0, 8($s0)
+ lui $t0, 0x7728
+ ori $t0, 0x6384
+ sw $t0, 0xc($s0)
+ lui $t0, 0xf802
+ ori $t0, 0xf8ef
+ sw $t0, 0x10($s0)
+ lui $t0, 0x42a5
+ ori $t0, 0xec5f
+ sw $t0, 0x14($s0)
+ lui $t0, 0x03bb
+ ori $t0, 0xfa25
+ sw $t0, 0x18($s0)
+ lui $t0, 0x4cb0
+ ori $t0, 0x1fad
+ sw $t0, 0x1c($s0)
+
+# preimage request - write(fdPreimageWrite, preimageData, 32)
+ li $a0, 6
+ li $a1, 0x30001000
+ li $t0, 8
+ li $a2, 4
+$writeloop:
+ li $v0, 4004
+ syscall
+ addiu $a1, $a1, 4
+ addiu $t0, $t0, -1
+ bnez $t0, $writeloop
+ nop
+
+# preimage response to 0x30002000 - read(fdPreimageRead, addr, count)
+# read preimage length to unaligned addr. This will read only up to the nearest aligned byte so we have to read again.
+ li $a0, 5
+ li $a1, 0x31000001
+ li $a2, 4
+ li $v0, 4003
+ syscall
+ li $a1, 0x31000004
+ li $v0, 4003
+ syscall
+ li $a1, 0x31000008
+ li $a2, 1
+ li $v0, 4003
+ syscall
+# read the preimage data
+ li $a1, 0x31000009
+ li $t0, 11
+$readloop:
+ li $v0, 4003
+ li $a2, 4
+ syscall
+ addu $a1, $a1, $v0
+ subu $t0, $t0, $v0
+ bnez $t0, $readloop
+ nop
+
+# length at 0x31000001. We also check that the lower 32 bits are zero
+ li $s1, 0x31000001
+ lb $t0, 0($s1)
+ lb $t2, 1($s1)
+ sll $t2, $t2, 8
+ or $t0, $t0, $t2
+ lb $t2, 2($s1)
+ sll $t2, $t2, 16
+ or $t0, $t0, $t2
+# assert len[0:3] == 0
+ sltiu $v0, $t0, 1
+
+# assert len[4:8] == 0
+ addiu $s1, $s1, 3
+ lw $t1, 0($s1)
+ sltiu $v1, $t1, 1
+ and $v0, $v0, $v1
+
+# assert len[8:9] == 11
+ addiu $s1, $s1, 4
+ lb $t2, 0($s1)
+ li $t4, 11
+ subu $t5, $t2, $t4
+ sltiu $v1, $t5, 1
+ and $v0, $v0, $v1
+
+# data at 0x31000009
+ addiu $s1, $s1, 1
+ lb $t0, 0($s1)
+ lb $t2, 1($s1)
+ sll $t0, $t0, 8
+ or $t0, $t0, $t2
+ lb $t2, 2($s1)
+ sll $t0, $t0, 8
+ or $t0, $t0, $t2
+ lb $t2, 3($s1)
+ sll $t0, $t0, 8
+ or $t0, $t0, $t2
+
+ #lw $t0, 0($s1)
+ lui $t4, 0x6865
+ ori $t4, 0x6c6c
+ subu $t5, $t0, $t4
+ sltiu $v1, $t5, 1
+
+ and $v0, $v0, $v1
+
+# save results
+ lui $s0, 0xbfff # Load the base address 0xbffffff0
+ ori $s0, 0xfff0
+ ori $s1, $0, 1 # Prepare the 'done' status
+
+ sw $v0, 8($s0) # Set the test result
+ sw $s1, 4($s0) # Set 'done'
+
+$done:
+ jr $ra
+ nop
+
+ .end test
diff --git a/crates/mipsevm/open_mips_tests/test/oracle_unaligned_write.asm b/crates/mipsevm/open_mips_tests/test/oracle_unaligned_write.asm
new file mode 100644
index 0000000..d11ef9c
--- /dev/null
+++ b/crates/mipsevm/open_mips_tests/test/oracle_unaligned_write.asm
@@ -0,0 +1,127 @@
+.section .test, "x"
+ .balign 4
+ .set noreorder
+ .global test
+ .ent test
+
+# load hash at 0x30001000
+# 0x47173285 a8d7341e 5e972fc6 77286384 f802f8ef 42a5ec5f 03bbfa25 4cb01fad = keccak("hello world")
+# 0x02173285 a8d7341e 5e972fc6 77286384 f802f8ef 42a5ec5f 03bbfa25 4cb01fad = keccak("hello world").key
+test:
+ lui $s0, 0x3000
+ ori $s0, 0x1000
+
+ lui $t0, 0x0217
+ ori $t0, 0x3285
+ sw $t0, 0($s0)
+ lui $t0, 0xa8d7
+ ori $t0, 0x341e
+ sw $t0, 4($s0)
+ lui $t0, 0x5e97
+ ori $t0, 0x2fc6
+ sw $t0, 8($s0)
+ lui $t0, 0x7728
+ ori $t0, 0x6384
+ sw $t0, 0xc($s0)
+ lui $t0, 0xf802
+ ori $t0, 0xf8ef
+ sw $t0, 0x10($s0)
+ lui $t0, 0x42a5
+ ori $t0, 0xec5f
+ sw $t0, 0x14($s0)
+ lui $t0, 0x03bb
+ ori $t0, 0xfa25
+ sw $t0, 0x18($s0)
+ lui $t0, 0x4cb0
+ ori $t0, 0x1fad
+ sw $t0, 0x1c($s0)
+
+# preimage request - write(fdPreimageWrite, preimageData, 32)
+# create stuffed buffer containing the first byte of the hash - [garbage, hash[0], garbage]
+ lui $s1, 0x3200
+ ori $s1, 0x0000
+ lui $t0, 0xFFFF
+ ori $t0, 0x02FF
+ sw $t0, 0($s1)
+
+# initial unaligned write for stuffed buffer
+ li $a0, 6
+ li $a1, 0x32000002
+ li $a2, 1
+ li $v0, 4004
+ syscall
+
+# write 3 bytes for realignment
+ li $a0, 6
+ li $a1, 0x30001001
+ li $a2, 3
+ li $v0, 4004
+ syscall
+
+ li $a0, 6
+ li $a1, 0x30001004
+ li $t0, 7
+ li $a2, 4
+$writeloop:
+ li $v0, 4004
+ syscall
+ addiu $a1, $a1, 4
+ addiu $t0, $t0, -1
+ bnez $t0, $writeloop
+ nop
+
+# preimage response to 0x30002000 - read(fdPreimageRead, addr, count)
+# read preimage length
+ li $a0, 5
+ li $a1, 0x31000000
+ li $a2, 4
+ li $v0, 4003
+ syscall
+ li $a1, 0x31000004
+ li $v0, 4003
+ syscall
+# read the preimage data
+ li $a1, 0x31000008
+ li $t0, 3
+$readloop:
+ li $v0, 4003
+ syscall
+ addiu $a1, $a1, 4
+ addiu $t0, $t0, -1
+ bnez $t0, $readloop
+ nop
+
+# length at 0x31000000. We also check that the lower 32 bits are zero
+ lui $s1, 0x3100
+ lw $t0, 0($s1)
+ sltiu $t6, $t0, 1
+ li $s1, 0x31000004
+ lw $t0, 0($s1)
+# should be len("hello world") == 11
+ li $t4, 11
+ subu $t5, $t0, $t4
+ sltiu $v0, $t5, 1
+ and $v0, $v0, $t6
+
+# data at 0x31000008
+ lw $t0, 4($s1)
+ lui $t4, 0x6865
+ ori $t4, 0x6c6c
+ subu $t5, $t0, $t4
+ sltiu $v1, $t5, 1
+
+ and $v0, $v0, $v1
+
+# save results
+ lui $s0, 0xbfff # Load the base address 0xbffffff0
+ ori $s0, 0xfff0
+ ori $s1, $0, 1 # Prepare the 'done' status
+
+ sw $v0, 8($s0) # Set the test result
+ sw $s1, 4($s0) # Set 'done'
+
+$done:
+ jr $ra
+ nop
+
+ .end test
diff --git a/crates/mipsevm/open_mips_tests/test/ori.asm b/crates/mipsevm/open_mips_tests/test/ori.asm
new file mode 100644
index 0000000..5b1f9e4
--- /dev/null
+++ b/crates/mipsevm/open_mips_tests/test/ori.asm
@@ -0,0 +1,38 @@
+###############################################################################
+# File : ori.asm
+# Project : MIPS32 MUX
+# Author: : Grant Ayers (ayers@cs.stanford.edu)
+#
+# Standards/Formatting:
+# MIPS gas, soft tab, 80 column
+#
+# Description:
+# Test the functionality of the 'ori' instruction.
+#
+###############################################################################
+
+
+ .section .test, "x"
+ .balign 4
+ .set noreorder
+ .global test
+ .ent test
+test:
+ lui $s0, 0xbfff # Load the base address 0xbffffff0
+ ori $s0, 0xfff0
+ ori $s1, $0, 1 # Prepare the 'done' status
+
+ #### Test code start ####
+
+ ori $v0, $s1, 0
+
+ #### Test code end ####
+
+ sw $v0, 8($s0) # Set the test result
+ sw $s1, 4($s0) # Set 'done'
+
+$done:
+ jr $ra
+ nop
+
+ .end test
diff --git a/crates/mipsevm/open_mips_tests/test/sb.asm b/crates/mipsevm/open_mips_tests/test/sb.asm
new file mode 100644
index 0000000..ad11c17
--- /dev/null
+++ b/crates/mipsevm/open_mips_tests/test/sb.asm
@@ -0,0 +1,58 @@
+###############################################################################
+# File : sb.asm
+# Project : MIPS32 MUX
+# Author: : Grant Ayers (ayers@cs.stanford.edu)
+#
+# Standards/Formatting:
+# MIPS gas, soft tab, 80 column
+#
+# Description:
+# Test the functionality of the 'sb' instruction.
+#
+###############################################################################
+
+
+ .section .test, "x"
+ .balign 4
+ .set noreorder
+ .global test
+ .ent test
+test:
+ lui $s0, 0xbfff # Load the base address 0xbffffff0
+ ori $s0, 0xfff0
+ ori $s1, $0, 1 # Prepare the 'done' status
+
+ #### Test code start ####
+
+ lui $t0, 0xbfc0 # Load address 0xbfc007fc (last word in 2KB starting
+ ori $t0, 0x07fc # from 0xbfc00000)
+ sw $0, 0($t0)
+ ori $t1, $0, 0xc0
+ ori $t2, $0, 0x01
+ ori $t3, $0, 0xca
+ ori $t4, $0, 0xfe
+ sb $t1, 0($t0)
+ sb $t2, 1($t0)
+ sb $t3, 2($t0)
+ sb $t4, 3($t0)
+ lw $t5, 0($t0)
+ .ifdef big_endian
+ lui $t6, 0xc001
+ ori $t6, 0xcafe
+ .else
+ lui $t6, 0xfeca
+ ori $t6, 0x01c0
+ .endif
+ subu $t7, $t5, $t6
+ sltiu $v0, $t7, 1
+
+ #### Test code end ####
+
+ sw $v0, 8($s0) # Set the test result
+ sw $s1, 4($s0) # Set 'done'
+
+$done:
+ jr $ra
+ nop
+
+ .end test
diff --git a/crates/mipsevm/open_mips_tests/test/sh.asm b/crates/mipsevm/open_mips_tests/test/sh.asm
new file mode 100644
index 0000000..2f72960
--- /dev/null
+++ b/crates/mipsevm/open_mips_tests/test/sh.asm
@@ -0,0 +1,54 @@
+###############################################################################
+# File : sh.asm
+# Project : MIPS32 MUX
+# Author: : Grant Ayers (ayers@cs.stanford.edu)
+#
+# Standards/Formatting:
+# MIPS gas, soft tab, 80 column
+#
+# Description:
+# Test the functionality of the 'sh' instruction.
+#
+###############################################################################
+
+
+ .section .test, "x"
+ .balign 4
+ .set noreorder
+ .global test
+ .ent test
+test:
+ lui $s0, 0xbfff # Load the base address 0xbffffff0
+ ori $s0, 0xfff0
+ ori $s1, $0, 1 # Prepare the 'done' status
+
+ #### Test code start ####
+
+ lui $t0, 0xbfc0 # Load address 0xbfc007fc (last word in 2KB starting
+ ori $t0, 0x07fc # from 0xbfc00000)
+ sw $0, 0($t0)
+ ori $t1, $0, 0xc001
+ ori $t2, $0, 0xcafe
+ sh $t1, 0($t0)
+ sh $t2, 2($t0)
+ lw $t3, 0($t0)
+ .ifdef big_endian
+ lui $t4, 0xc001
+ ori $t4, 0xcafe
+ .else
+ lui $t4, 0xcafe
+ ori $t4, 0xc001
+ .endif
+ subu $t5, $t3, $t4
+ sltiu $v0, $t5, 1
+
+ #### Test code end ####
+
+ sw $v0, 8($s0) # Set the test result
+ sw $s1, 4($s0) # Set 'done'
+
+$done:
+ jr $ra
+ nop
+
+ .end test
diff --git a/crates/mipsevm/open_mips_tests/test/sll.asm b/crates/mipsevm/open_mips_tests/test/sll.asm
new file mode 100644
index 0000000..854063c
--- /dev/null
+++ b/crates/mipsevm/open_mips_tests/test/sll.asm
@@ -0,0 +1,44 @@
+###############################################################################
+# File : sll.asm
+# Project : MIPS32 MUX
+# Author: : Grant Ayers (ayers@cs.stanford.edu)
+#
+# Standards/Formatting:
+# MIPS gas, soft tab, 80 column
+#
+# Description:
+# Test the functionality of the 'sll' instruction.
+#
+###############################################################################
+
+
+ .section .test, "x"
+ .balign 4
+ .set noreorder
+ .global test
+ .ent test
+test:
+ lui $s0, 0xbfff # Load the base address 0xbffffff0
+ ori $s0, 0xfff0
+ ori $s1, $0, 1 # Prepare the 'done' status
+
+ #### Test code start ####
+
+ lui $t0, 0xdeaf # A = 0xdeafbeef
+ ori $t0, 0xbeef
+ sll $t1, $t0, 4 # B = 0xdeafbeef << 4 = 0xeafbeef0
+ lui $t2, 0xeafb # C = 0xeafbeef0
+ ori $t2, 0xeef0
+ subu $t3, $t1, $t2
+ sltiu $v0, $t3, 1
+
+ #### Test code end ####
+
+ sw $v0, 8($s0) # Set the test result
+ sw $s1, 4($s0) # Set 'done'
+
+$done:
+ jr $ra
+ nop
+
+ .end test
diff --git a/crates/mipsevm/open_mips_tests/test/sllv.asm b/crates/mipsevm/open_mips_tests/test/sllv.asm
new file mode 100644
index 0000000..e1284e2
--- /dev/null
+++ b/crates/mipsevm/open_mips_tests/test/sllv.asm
@@ -0,0 +1,45 @@
+###############################################################################
+# File : sllv.asm
+# Project : MIPS32 MUX
+# Author: : Grant Ayers (ayers@cs.stanford.edu)
+#
+# Standards/Formatting:
+# MIPS gas, soft tab, 80 column
+#
+# Description:
+# Test the functionality of the 'sllv' instruction.
+#
+###############################################################################
+
+
+ .section .test, "x"
+ .balign 4
+ .set noreorder
+ .global test
+ .ent test
+test:
+ lui $s0, 0xbfff # Load the base address 0xbffffff0
+ ori $s0, 0xfff0
+ ori $s1, $0, 1 # Prepare the 'done' status
+
+ #### Test code start ####
+
+ lui $t0, 0xdeaf # A = 0xdeafbeef
+ ori $t0, 0xbeef
+ ori $t1, $0, 12
+ sllv $t2, $t0, $t1 # B = 0xdeafbeef << 12 = 0xfbeef000
+ lui $t3, 0xfbee
+ ori $t3, 0xf000
+ subu $t4, $t2, $t3
+ sltiu $v0, $t4, 1
+
+ #### Test code end ####
+
+ sw $v0, 8($s0) # Set the test result
+ sw $s1, 4($s0) # Set 'done'
+
+$done:
+ jr $ra
+ nop
+
+ .end test
diff --git a/crates/mipsevm/open_mips_tests/test/slt.asm b/crates/mipsevm/open_mips_tests/test/slt.asm
new file mode 100644
index 0000000..9b98a78
--- /dev/null
+++ b/crates/mipsevm/open_mips_tests/test/slt.asm
@@ -0,0 +1,40 @@
+###############################################################################
+# File : slt.asm
+# Project : MIPS32 MUX
+# Author: : Grant Ayers (ayers@cs.stanford.edu)
+#
+# Standards/Formatting:
+# MIPS gas, soft tab, 80 column
+#
+# Description:
+# Test the functionality of the 'slt' instruction.
+#
+###############################################################################
+
+
+ .section .test, "x"
+ .balign 4
+ .set noreorder
+ .global test
+ .ent test
+test:
+ lui $s0, 0xbfff # Load the base address 0xbffffff0
+ ori $s0, 0xfff0
+ ori $s1, $0, 1 # Prepare the 'done' status
+
+ #### Test code start ####
+
+ lui $t0, 0xffff
+ ori $t0, 0xffff
+ slt $v0, $t0, $s1
+
+ #### Test code end ####
+
+ sw $v0, 8($s0) # Set the test result
+ sw $s1, 4($s0) # Set 'done'
+
+$done:
+ jr $ra
+ nop
+
+ .end test
diff --git a/crates/mipsevm/open_mips_tests/test/slti.asm b/crates/mipsevm/open_mips_tests/test/slti.asm
new file mode 100644
index 0000000..62fb7ce
--- /dev/null
+++ b/crates/mipsevm/open_mips_tests/test/slti.asm
@@ -0,0 +1,41 @@
+###############################################################################
+# File : slti.asm
+# Project : MIPS32 MUX
+# Author: : Grant Ayers (ayers@cs.stanford.edu)
+#
+# Standards/Formatting:
+# MIPS gas, soft tab, 80 column
+#
+# Description:
+# Test the functionality of the 'slti' instruction.
+#
+###############################################################################
+
+
+ .section .test, "x"
+ .balign 4
+ .set noreorder
+ .global test
+ .ent test
+test:
+ lui $s0, 0xbfff # Load the base address 0xbffffff0
+ ori $s0, 0xfff0
+ ori $s1, $0, 1 # Prepare the 'done' status
+
+ #### Test code start ####
+
+ lui $t0, 0x8000
+ slti $v0, $t0, 0xffff
+ slti $v1, $t0, 0
+ and $v0, $v0, $v1
+
+ #### Test code end ####
+
+ sw $v0, 8($s0) # Set the test result
+ sw $s1, 4($s0) # Set 'done'
+
+$done:
+ jr $ra
+ nop
+
+ .end test
diff --git a/crates/mipsevm/open_mips_tests/test/sltiu.asm b/crates/mipsevm/open_mips_tests/test/sltiu.asm
new file mode 100644
index 0000000..fc3b17a
--- /dev/null
+++ b/crates/mipsevm/open_mips_tests/test/sltiu.asm
@@ -0,0 +1,41 @@
+###############################################################################
+# File : sltiu.asm
+# Project : MIPS32 MUX
+# Author: : Grant Ayers (ayers@cs.stanford.edu)
+#
+# Standards/Formatting:
+# MIPS gas, soft tab, 80 column
+#
+# Description:
+# Test the functionality of the 'sltiu' instruction.
+#
+###############################################################################
+
+
+ .section .test, "x"
+ .balign 4
+ .set noreorder
+ .global test
+ .ent test
+test:
+ lui $s0, 0xbfff # Load the base address 0xbffffff0
+ ori $s0, 0xfff0
+ ori $s1, $0, 1 # Prepare the 'done' status
+
+ #### Test code start ####
+
+ lui $t0, 0x8000
+ sltiu $v0, $t0, 0xffff
+ sltiu $v1, $0, 0xffff
+ and $v0, $v0, $v1
+
+ #### Test code end ####
+
+ sw $v0, 8($s0) # Set the test result
+ sw $s1, 4($s0) # Set 'done'
+
+$done:
+ jr $ra
+ nop
+
+ .end test
diff --git a/crates/mipsevm/open_mips_tests/test/sltu.asm b/crates/mipsevm/open_mips_tests/test/sltu.asm
new file mode 100644
index 0000000..eeba898
--- /dev/null
+++ b/crates/mipsevm/open_mips_tests/test/sltu.asm
@@ -0,0 +1,40 @@
+###############################################################################
+# File : sltu.asm
+# Project : MIPS32 MUX
+# Author: : Grant Ayers (ayers@cs.stanford.edu)
+#
+# Standards/Formatting:
+# MIPS gas, soft tab, 80 column
+#
+# Description:
+# Test the functionality of the 'sltu' instruction.
+#
+###############################################################################
+
+
+ .section .test, "x"
+ .balign 4
+ .set noreorder
+ .global test
+ .ent test
+test:
+ lui $s0, 0xbfff # Load the base address 0xbffffff0
+ ori $s0, 0xfff0
+ ori $s1, $0, 1 # Prepare the 'done' status
+
+ #### Test code start ####
+
+ lui $t0, 0xffff
+ ori $t0, 0xffff
+ sltu $v0, $s1, $t0
+
+ #### Test code end ####
+
+ sw $v0, 8($s0) # Set the test result
+ sw $s1, 4($s0) # Set 'done'
+
+$done:
+ jr $ra
+ nop
+
+ .end test
diff --git a/crates/mipsevm/open_mips_tests/test/sra.asm b/crates/mipsevm/open_mips_tests/test/sra.asm
new file mode 100644
index 0000000..69ef4d8
--- /dev/null
+++ b/crates/mipsevm/open_mips_tests/test/sra.asm
@@ -0,0 +1,44 @@
+###############################################################################
+# File : sra.asm
+# Project : MIPS32 MUX
+# Author: : Grant Ayers (ayers@cs.stanford.edu)
+#
+# Standards/Formatting:
+# MIPS gas, soft tab, 80 column
+#
+# Description:
+# Test the functionality of the 'sra' instruction.
+#
+###############################################################################
+
+
+ .section .test, "x"
+ .balign 4
+ .set noreorder
+ .global test
+ .ent test
+test:
+ lui $s0, 0xbfff # Load the base address 0xbffffff0
+ ori $s0, 0xfff0
+ ori $s1, $0, 1 # Prepare the 'done' status
+
+ #### Test code start ####
+
+ lui $t0, 0xdeaf # A = 0xdeafbeef
+ ori $t0, 0xbeef
+ sra $t1, $t0, 4 # B = 0xdeafbeef >> 4 = 0xfdeafbee
+ lui $t2, 0xfdea # C = 0xfdeafbee
+ ori $t2, 0xfbee
+ subu $t3, $t1, $t2 # D = B - C = 0
+ sltiu $v0, $t3, 1
+
+ #### Test code end ####
+
+ sw $v0, 8($s0) # Set the test result
+ sw $s1, 4($s0) # Set 'done'
+
+$done:
+ jr $ra
+ nop
+
+ .end test
diff --git a/crates/mipsevm/open_mips_tests/test/srav.asm b/crates/mipsevm/open_mips_tests/test/srav.asm
new file mode 100644
index 0000000..77b9983
--- /dev/null
+++ b/crates/mipsevm/open_mips_tests/test/srav.asm
@@ -0,0 +1,45 @@
+###############################################################################
+# File : srav.asm
+# Project : MIPS32 MUX
+# Author: : Grant Ayers (ayers@cs.stanford.edu)
+#
+# Standards/Formatting:
+# MIPS gas, soft tab, 80 column
+#
+# Description:
+# Test the functionality of the 'srav' instruction.
+#
+###############################################################################
+
+
+ .section .test, "x"
+ .balign 4
+ .set noreorder
+ .global test
+ .ent test
+test:
+ lui $s0, 0xbfff # Load the base address 0xbffffff0
+ ori $s0, 0xfff0
+ ori $s1, $0, 1 # Prepare the 'done' status
+
+ #### Test code start ####
+
+ lui $t0, 0xdeaf # A = 0xdeafbeef
+ ori $t0, 0xbeef
+ ori $t1, $0, 12
+ srav $t2, $t0, $t1 # B = 0xdeafbeef >> 12 = 0xfffdeafb
+ lui $t3, 0xfffd
+ ori $t3, 0xeafb
+ subu $t4, $t2, $t3
+ sltiu $v0, $t4, 1
+
+ #### Test code end ####
+
+ sw $v0, 8($s0) # Set the test result
+ sw $s1, 4($s0) # Set 'done'
+
+$done:
+ jr $ra
+ nop
+
+ .end test
diff --git a/crates/mipsevm/open_mips_tests/test/srl.asm b/crates/mipsevm/open_mips_tests/test/srl.asm
new file mode 100644
index 0000000..1a7d61d
--- /dev/null
+++ b/crates/mipsevm/open_mips_tests/test/srl.asm
@@ -0,0 +1,44 @@
+###############################################################################
+# File : srl.asm
+# Project : MIPS32 MUX
+# Author: : Grant Ayers (ayers@cs.stanford.edu)
+#
+# Standards/Formatting:
+# MIPS gas, soft tab, 80 column
+#
+# Description:
+# Test the functionality of the 'srl' instruction.
+#
+###############################################################################
+
+
+ .section .test, "x"
+ .balign 4
+ .set noreorder
+ .global test
+ .ent test
+test:
+ lui $s0, 0xbfff # Load the base address 0xbffffff0
+ ori $s0, 0xfff0
+ ori $s1, $0, 1 # Prepare the 'done' status
+
+ #### Test code start ####
+
+ lui $t0, 0xdeaf # A = 0xdeafbeef
+ ori $t0, 0xbeef
+ srl $t1, $t0, 4 # B = 0xdeafbeef >> 4 = 0x0deafbee
+ lui $t2, 0x0dea
+ ori $t2, 0xfbee
+ subu $t3, $t1, $t2 # D = B - C = 0
+ sltiu $v0, $t3, 1
+
+ #### Test code end ####
+
+ sw $v0, 8($s0) # Set the test result
+ sw $s1, 4($s0) # Set 'done'
+
+$done:
+ jr $ra
+ nop
+
+ .end test
diff --git a/crates/mipsevm/open_mips_tests/test/srlv.asm b/crates/mipsevm/open_mips_tests/test/srlv.asm
new file mode 100644
index 0000000..42b4ad1
--- /dev/null
+++ b/crates/mipsevm/open_mips_tests/test/srlv.asm
@@ -0,0 +1,45 @@
+###############################################################################
+# File : srlv.asm
+# Project : MIPS32 MUX
+# Author: : Grant Ayers (ayers@cs.stanford.edu)
+#
+# Standards/Formatting:
+# MIPS gas, soft tab, 80 column
+#
+# Description:
+# Test the functionality of the 'srlv' instruction.
+#
+###############################################################################
+
+
+ .section .test, "x"
+ .balign 4
+ .set noreorder
+ .global test
+ .ent test
+test:
+ lui $s0, 0xbfff # Load the base address 0xbffffff0
+ ori $s0, 0xfff0
+ ori $s1, $0, 1 # Prepare the 'done' status
+
+ #### Test code start ####
+
+ lui $t0, 0xdeaf # A = 0xdeafbeef
+ ori $t0, 0xbeef
+ ori $t1, $0, 12
+ srlv $t2, $t0, $t1 # B = 0xdeafbeef >> 12 = 0x000deafb
+ lui $t3, 0x000d
+ ori $t3, 0xeafb
+ subu $t4, $t2, $t3
+ sltiu $v0, $t4, 1
+
+ #### Test code end ####
+
+ sw $v0, 8($s0) # Set the test result
+ sw $s1, 4($s0) # Set 'done'
+
+$done:
+ jr $ra
+ nop
+
+ .end test
diff --git a/crates/mipsevm/open_mips_tests/test/sub.asm b/crates/mipsevm/open_mips_tests/test/sub.asm
new file mode 100644
index 0000000..279a72b
--- /dev/null
+++ b/crates/mipsevm/open_mips_tests/test/sub.asm
@@ -0,0 +1,44 @@
+###############################################################################
+# File : sub.asm
+# Project : MIPS32 MUX
+# Author: : Grant Ayers (ayers@cs.stanford.edu)
+#
+# Standards/Formatting:
+# MIPS gas, soft tab, 80 column
+#
+# Description:
+# Test the functionality of the 'sub' instruction.
+#
+###############################################################################
+
+
+ .section .test, "x"
+ .balign 4
+ .set noreorder
+ .global test
+ .ent test
+test:
+ lui $s0, 0xbfff # Load the base address 0xbffffff0
+ ori $s0, 0xfff0
+ ori $s1, $0, 1 # Prepare the 'done' status
+
+ #### Test code start ####
+
+ lui $t0, 0xffff # A = 0xfffffffd (-3)
+ ori $t0, 0xfffd
+ sub $t1, $t0, $t0 # B = A - A = 0
+ sub $t2, $t1, $t0 # C = B - A = 0 - A = 3
+ ori $t3, $0, 3 # D = 2
+ sub $t4, $t2, $t3 # E = C - D = C - 2 = 0
+ sltiu $v0, $t4, 1
+
+ #### Test code end ####
+
+ sw $v0, 8($s0) # Set the test result
+ sw $s1, 4($s0) # Set 'done'
+
+$done:
+ jr $ra
+ nop
+
+ .end test
diff --git a/crates/mipsevm/open_mips_tests/test/subu.asm b/crates/mipsevm/open_mips_tests/test/subu.asm
new file mode 100644
index 0000000..de707cc
--- /dev/null
+++ b/crates/mipsevm/open_mips_tests/test/subu.asm
@@ -0,0 +1,46 @@
+###############################################################################
+# File : subu.asm
+# Project : MIPS32 MUX
+# Author: : Grant Ayers (ayers@cs.stanford.edu)
+#
+# Standards/Formatting:
+# MIPS gas, soft tab, 80 column
+#
+# Description:
+# Test the functionality of the 'subu' instruction.
+#
+###############################################################################
+
+
+ .section .test, "x"
+ .balign 4
+ .set noreorder
+ .global test
+ .ent test
+test:
+ lui $s0, 0xbfff # Load the base address 0xbffffff0
+ ori $s0, 0xfff0
+ ori $s1, $0, 1 # Prepare the 'done' status
+
+ #### Test code start ####
+
+ lui $t0, 0xffff # A = 0xfffffffd (-3)
+ ori $t0, 0xfffd
+ ori $t1, $0, 4 # B = 4
+ subu $t2, $t0, $t1 # C = A - B = 0xfffffff9 (-7)
+ lui $t3, 0xffff # D = 0xfffffff8 (like -8 mod 2^32)
+ ori $t3, 0xfff8
+ subu $t4, $t2, $t3 # F = C - D = 1
+ subu $t5, $t4, $s1 # G = F - 1 = 0
+ sltiu $v0, $t5, 1
+
+ #### Test code end ####
+
+ sw $v0, 8($s0) # Set the test result
+ sw $s1, 4($s0) # Set 'done'
+
+$done:
+ jr $ra
+ nop
+
+ .end test
diff --git a/crates/mipsevm/open_mips_tests/test/swl.asm b/crates/mipsevm/open_mips_tests/test/swl.asm
new file mode 100644
index 0000000..cf4c15c
--- /dev/null
+++ b/crates/mipsevm/open_mips_tests/test/swl.asm
@@ -0,0 +1,85 @@
+###############################################################################
+# File : swl.asm
+# Project : MIPS32 MUX
+# Author: : Grant Ayers (ayers@cs.stanford.edu)
+#
+# Standards/Formatting:
+# MIPS gas, soft tab, 80 column
+#
+# Description:
+# Test the functionality of the 'swl' instruction.
+#
+###############################################################################
+
+
+ .section .test, "x"
+ .balign 4
+ .set noreorder
+ .global test
+ .ent test
+test:
+ lui $s0, 0xbfff # Load the base address 0xbffffff0
+ ori $s0, 0xfff0
+ ori $s1, $0, 1 # Prepare the 'done' status
+
+ #### Test code start ####
+
+ lui $t0, 0xbfc0 # Load address 0xbfc007ec (last four words in 2KB starting
+ ori $t0, 0x07ec # from 0xbfc00000)
+ lui $t1, 0xc001 # Memory word is 0xc001cafe
+ ori $t1, 0xcafe
+ sw $t1, 0($t0)
+ sw $t1, 4($t0)
+ sw $t1, 8($t0)
+ sw $t1, 12($t0)
+ lui $t2, 0xdeaf # Register word is 0xdeafbeef
+ ori $t2, 0xbeef
+ swl $t2, 0($t0)
+ swl $t2, 5($t0)
+ swl $t2, 10($t0)
+ swl $t2, 15($t0)
+ lw $s2, 0($t0)
+ lw $s3, 4($t0)
+ lw $s4, 8($t0)
+ lw $s5, 12($t0)
+ .ifdef big_endian
+ lui $t3, 0xdeaf # 0xdeafbeef
+ ori $t3, 0xbeef
+ lui $t4, 0xc0de # 0xc0deafbe
+ ori $t4, 0xafbe
+ lui $t5, 0xc001 # 0xc001deaf
+ ori $t5, 0xdeaf
+ lui $t6, 0xc001 # 0xc001cade
+ ori $t6, 0xcade
+ .else
+ lui $t3, 0xc001 # 0xc001cade
+ ori $t3, 0xcade
+ lui $t4, 0xc001 # 0xc001deaf
+ ori $t4, 0xdeaf
+ lui $t5, 0xc0de # 0xc0deafbe
+ ori $t5, 0xafbe
+ lui $t6, 0xdeaf # 0xdeafbeef
+ ori $t6, 0xbeef
+ .endif
+ subu $t7, $s2, $t3
+ sltiu $v0, $t7, 1
+ subu $t7, $s3, $t4
+ sltiu $v1, $t7, 1
+ and $v0, $v0, $v1
+ subu $t7, $s4, $t5
+ sltiu $v1, $t7, 1
+ and $v0, $v0, $v1
+ subu $t7, $s5, $t6
+ sltiu $v1, $t7, 1
+ and $v0, $v0, $v1
+
+ #### Test code end ####
+
+ sw $v0, 8($s0) # Set the test result
+ sw $s1, 4($s0) # Set 'done'
+
+$done:
+ jr $ra
+ nop
+
+ .end test
diff --git a/crates/mipsevm/open_mips_tests/test/swr.asm b/crates/mipsevm/open_mips_tests/test/swr.asm
new file mode 100644
index 0000000..c402d7e
--- /dev/null
+++ b/crates/mipsevm/open_mips_tests/test/swr.asm
@@ -0,0 +1,85 @@
+###############################################################################
+# File : swr.asm
+# Project : MIPS32 MUX
+# Author: : Grant Ayers (ayers@cs.stanford.edu)
+#
+# Standards/Formatting:
+# MIPS gas, soft tab, 80 column
+#
+# Description:
+# Test the functionality of the 'swr' instruction.
+#
+###############################################################################
+
+
+ .section .test, "x"
+ .balign 4
+ .set noreorder
+ .global test
+ .ent test
+test:
+ lui $s0, 0xbfff # Load the base address 0xbffffff0
+ ori $s0, 0xfff0
+ ori $s1, $0, 1 # Prepare the 'done' status
+
+ #### Test code start ####
+
+ lui $t0, 0xbfc0 # Load address 0xbfc007ec (last four words in 2KB starting
+ ori $t0, 0x07ec # from 0xbfc00000)
+ lui $t1, 0xc001 # Memory words are 0xc001cafe
+ ori $t1, 0xcafe
+ sw $t1, 0($t0)
+ sw $t1, 4($t0)
+ sw $t1, 8($t0)
+ sw $t1, 12($t0)
+ lui $t2, 0xdeaf # Register word is 0xdeafbeef
+ ori $t2, 0xbeef
+ swr $t2, 0($t0)
+ swr $t2, 5($t0)
+ swr $t2, 10($t0)
+ swr $t2, 15($t0)
+ lw $s2, 0($t0)
+ lw $s3, 4($t0)
+ lw $s4, 8($t0)
+ lw $s5, 12($t0)
+ .ifdef big_endian
+ lui $t3, 0xef01 # 0xef01cafe
+ ori $t3, 0xcafe
+ lui $t4, 0xbeef # 0xbeefcafe
+ ori $t4, 0xcafe
+ lui $t5, 0xafbe # 0xafbeeffe
+ ori $t5, 0xeffe
+ lui $t6, 0xdeaf # 0xdeafbeef
+ ori $t6, 0xbeef
+ .else
+ lui $t3, 0xdeaf # 0xdeafbeef
+ ori $t3, 0xbeef
+ lui $t4, 0xafbe # 0xafbeeffe
+ ori $t4, 0xeffe
+ lui $t5, 0xbeef # 0xbeefcafe
+ ori $t5, 0xcafe
+ lui $t6, 0xef01 # 0xef01cafe
+ ori $t6, 0xcafe
+ .endif
+ subu $t7, $s2, $t3
+ sltiu $v0, $t7, 1
+ subu $t7, $s3, $t4
+ sltiu $v1, $t7, 1
+ and $v0, $v0, $v1
+ subu $t7, $s4, $t5
+ sltiu $v1, $t7, 1
+ and $v0, $v0, $v1
+ subu $t7, $s5, $t6
+ sltiu $v1, $t7, 1
+ and $v0, $v0, $v1
+
+ #### Test code end ####
+
+ sw $v0, 8($s0) # Set the test result
+ sw $s1, 4($s0) # Set 'done'
+
+$done:
+ jr $ra
+ nop
+
+ .end test
diff --git a/crates/mipsevm/open_mips_tests/test/xor.asm b/crates/mipsevm/open_mips_tests/test/xor.asm
new file mode 100644
index 0000000..dd9a376
--- /dev/null
+++ b/crates/mipsevm/open_mips_tests/test/xor.asm
@@ -0,0 +1,47 @@
+###############################################################################
+# File : xor.asm
+# Project : MIPS32 MUX
+# Author: : Grant Ayers (ayers@cs.stanford.edu)
+#
+# Standards/Formatting:
+# MIPS gas, soft tab, 80 column
+#
+# Description:
+# Test the functionality of the 'xor' instruction.
+#
+###############################################################################
+
+
+ .section .test, "x"
+ .balign 4
+ .set noreorder
+ .global test
+ .ent test
+test:
+ lui $s0, 0xbfff # Load the base address 0xbffffff0
+ ori $s0, 0xfff0
+ ori $s1, $0, 1 # Prepare the 'done' status
+
+ #### Test code start ####
+
+ lui $t0, 0xdeaf # A = 0xdeafbeef
+ ori $t0, 0xbeef
+ lui $t1, 0x3141 # B = 0x31415926
+ ori $t1, 0x5926
+ lui $t2, 0xefee # C = 0xefeee7c8
+ ori $t2, 0xe7c8
+ xor $t3, $t0, $t1 # D = xor(A,B) = 0xefeee7c8
+ xor $t4, $t2, $t3 # E = xor(C,D) = 0x1
+ xor $t5, $t4, $s1 # F = xor(E,1) = 0
+ sltiu $v0, $t5, 1
+
+ #### Test code end ####
+
+ sw $v0, 8($s0) # Set the test result
+ sw $s1, 4($s0) # Set 'done'
+
+$done:
+ jr $ra
+ nop
+
+ .end test
diff --git a/crates/mipsevm/open_mips_tests/test/xori.asm b/crates/mipsevm/open_mips_tests/test/xori.asm
new file mode 100644
index 0000000..33f1f2d
--- /dev/null
+++ b/crates/mipsevm/open_mips_tests/test/xori.asm
@@ -0,0 +1,42 @@
+###############################################################################
+# File : xori.asm
+# Project : MIPS32 MUX
+# Author: : Grant Ayers (ayers@cs.stanford.edu)
+#
+# Standards/Formatting:
+# MIPS gas, soft tab, 80 column
+#
+# Description:
+# Test the functionality of the 'xori' instruction.
+#
+###############################################################################
+
+
+ .section .test, "x"
+ .balign 4
+ .set noreorder
+ .global test
+ .ent test
+test:
+ lui $s0, 0xbfff # Load the base address 0xbffffff0
+ ori $s0, 0xfff0
+ ori $s1, $0, 1 # Prepare the 'done' status
+
+ #### Test code start ####
+
+ ori $t0, $0, 0xdeaf # A = 0xdeaf
+ xori $t1, $t0, 0x3141 # B = xor(A, 0x3141) = 0xefee
+ xori $t2, $t1, 0xefef # C = xor(B, 0xefef) = 0x1
+ xori $t3, $t2, 1 # D = xor(C, 1) = 0
+ sltiu $v0, $t3, 1
+
+ #### Test code end ####
+
+ sw $v0, 8($s0) # Set the test result
+ sw $s1, 4($s0) # Set 'done'
+
+$done:
+ jr $ra
+ nop
+
+ .end test
diff --git a/crates/mipsevm/src/mips/instrumented.rs b/crates/mipsevm/src/mips/instrumented.rs
index 340bc71..ac5aa9b 100644
--- a/crates/mipsevm/src/mips/instrumented.rs
+++ b/crates/mipsevm/src/mips/instrumented.rs
@@ -8,15 +8,15 @@ use std::io::{BufWriter, Write};
pub(crate) const MIPS_EBADF: u32 = 0x9;
pub(crate) const MIPS_EINVAL: u32 = 0x16;
-pub struct InstrumentedState {
+pub struct InstrumentedState {
/// The inner [State] of the MIPS thread context.
pub(crate) state: State,
/// The MIPS thread context's stdout buffer.
/// TODO(clabby): Prob not the best place for this.
- pub(crate) std_out: BufWriter,
+ pub(crate) std_out: BufWriter,
/// The MIPS thread context's stderr buffer.
/// TODO(clabby): Prob not the best place for this.
- pub(crate) std_err: BufWriter,
+ pub(crate) std_err: BufWriter,
/// The last address we accessed in memory.
pub(crate) last_mem_access: Address,
/// Whether or not the memory proof generation is enabled.
@@ -34,16 +34,17 @@ pub struct InstrumentedState {
pub(crate) last_preimage_offset: u32,
}
-impl InstrumentedState
+impl InstrumentedState
where
- W: Write,
+ O: Write,
+ E: Write,
P: PreimageOracle,
{
- pub fn new(state: State, oracle: P, std_out: W, std_in: W) -> Self {
+ pub fn new(state: State, oracle: P, std_out: O, std_err: E) -> Self {
Self {
state,
std_out: BufWriter::new(std_out),
- std_err: BufWriter::new(std_in),
+ std_err: BufWriter::new(std_err),
last_mem_access: 0,
mem_proof_enabled: false,
mem_proof: [0; 28 * 32],
@@ -57,7 +58,7 @@ where
/// Step the MIPS emulator forward one instruction.
///
/// ### Returns
- /// - Ok(Some(witness)): The [StepWitness] for the current step.
+ /// - Ok(Some(witness)): The [StepWitness] for the current
/// - Err(_): An error occurred while processing the instruction step in the MIPS emulator.
pub fn step(&mut self, proof: bool) -> Result> {
self.mem_proof_enabled = proof;
@@ -80,7 +81,7 @@ where
})
}
- self.mips_step()?;
+ self.inner_step()?;
if proof {
witness = witness.map(|mut wit| {
@@ -97,3 +98,108 @@ where
Ok(witness)
}
}
+
+#[cfg(test)]
+mod test {
+ use crate::PreimageOracle;
+
+ /// Used in tests to write the results to
+ const BASE_ADDR_END: u32 = 0xBF_FF_FF_F0;
+
+ /// Used as the return-address for tests
+ const END_ADDR: u32 = 0xA7_EF_00_D0;
+
+ struct StaticOracle;
+
+ impl PreimageOracle for StaticOracle {
+ fn hint(&mut self, _value: &[u8]) {
+ // noop
+ }
+
+ fn get(&self, _key: alloy_primitives::B256) -> anyhow::Result<&[u8]> {
+ // noop
+ Ok(&[])
+ }
+ }
+
+ mod open_mips {
+ use super::*;
+ use crate::{Address, InstrumentedState, Memory, State};
+ use std::{
+ cell::RefCell,
+ fs,
+ io::{self, BufReader},
+ path::PathBuf,
+ rc::Rc,
+ };
+
+ #[test]
+ // #[ignore]
+ fn open_mips_tests() {
+ let tests_path = PathBuf::from(std::env::current_dir().unwrap())
+ .join("open_mips_tests")
+ .join("test")
+ .join("bin");
+ let test_files = fs::read_dir(tests_path).unwrap();
+
+ for f in test_files.into_iter() {
+ if let Ok(f) = f {
+ let file_name = String::from(f.file_name().to_str().unwrap());
+ if file_name.starts_with("oracle") {
+ dbg!("Skipping oracle test");
+ continue;
+ }
+
+ // Short circuit early for `exit_group.bin`
+ let exit_group = file_name == "exit_group.bin";
+
+ let program_mem = fs::read(f.path()).unwrap();
+
+ let mut state = {
+ let mut state = State::default();
+ state.pc = 0;
+ state.next_pc = 4;
+ state.memory = Rc::new(RefCell::new(Memory::default()));
+ state
+ };
+ state
+ .memory
+ .borrow_mut()
+ .set_memory_range(0, BufReader::new(program_mem.as_slice()))
+ .unwrap();
+
+ // Set the return address ($ra) to jump into when the test completes.
+ state.registers[31] = END_ADDR;
+
+ let mut ins =
+ InstrumentedState::new(state, StaticOracle {}, io::stdout(), io::stderr());
+
+ for _ in 0..1000 {
+ if ins.state.pc == END_ADDR {
+ break;
+ }
+ if exit_group && ins.state.exited {
+ break;
+ }
+ ins.step(false).unwrap();
+ }
+
+ if exit_group {
+ assert_ne!(END_ADDR, ins.state.pc, "must not reach end");
+ assert!(ins.state.exited, "must exit");
+ assert_eq!(1, ins.state.exit_code, "must exit with 1");
+ } else {
+ assert_eq!(END_ADDR, ins.state.pc, "must reach end");
+ let mut state = ins.state.memory.borrow_mut();
+ let (done, result) = (
+ state.get_memory((BASE_ADDR_END + 4) as Address).unwrap(),
+ state.get_memory((BASE_ADDR_END + 8) as Address).unwrap(),
+ );
+ assert_eq!(done, 1, "must set done to 1");
+ assert_eq!(result, 1, "must have success result {:?}", f.file_name());
+ }
+ }
+ }
+ }
+ }
+}
diff --git a/crates/mipsevm/src/mips/mips_vm.rs b/crates/mipsevm/src/mips/mips_vm.rs
index ccd9abd..c8972e7 100644
--- a/crates/mipsevm/src/mips/mips_vm.rs
+++ b/crates/mipsevm/src/mips/mips_vm.rs
@@ -14,9 +14,10 @@ use std::{
rc::Rc,
};
-impl InstrumentedState
+impl InstrumentedState
where
- W: Write,
+ O: Write,
+ E: Write,
P: PreimageOracle,
{
/// Read the preimage for the given key and offset from the [PreimageOracle] server.
@@ -28,7 +29,7 @@ where
/// ### Returns
/// - `Ok((data, data_len))`: The preimage data and length.
/// - `Err(_)`: An error occurred while fetching the preimage.
- pub fn read_preimage(&mut self, key: B256, offset: u32) -> Result<(B256, usize)> {
+ pub(crate) fn read_preimage(&mut self, key: B256, offset: u32) -> Result<(B256, usize)> {
if key != self.last_preimage_key {
self.last_preimage_key = key;
let data = self.preimage_oracle.get(key)?;
@@ -58,7 +59,7 @@ where
///
/// ### Returns
/// - A [Result] indicating if the operation was successful.
- pub fn track_mem_access(&mut self, effective_address: Address) -> Result<()> {
+ pub(crate) fn track_mem_access(&mut self, effective_address: Address) -> Result<()> {
if self.mem_proof_enabled && self.last_mem_access != effective_address {
if self.last_mem_access != Address::MAX {
anyhow::bail!("Unexpected diffrent memory access at {:x}, already have access at {:x} buffered", effective_address, self.last_mem_access);
@@ -78,7 +79,7 @@ where
///
/// ### Returns
/// - A [Result] indicating if the step was successful.
- pub fn mips_step(&mut self) -> Result<()> {
+ pub(crate) fn inner_step(&mut self) -> Result<()> {
if self.state.exited {
return Ok(());
}
@@ -210,7 +211,7 @@ where
///
/// ### Returns
/// - A [Result] indicating if the syscall dispatch was successful.
- pub fn handle_syscall(&mut self) -> Result<()> {
+ pub(crate) fn handle_syscall(&mut self) -> Result<()> {
let mut v0 = 0;
let mut v1 = 0;
@@ -303,14 +304,12 @@ where
a1 as Address,
a2 as u64,
);
- std::io::copy(
- &mut reader,
- if matches!(fd, Fd::Stdout) {
- &mut self.std_out
- } else {
- &mut self.std_err
- },
- )?;
+ let writer: &mut dyn Write = if matches!(fd, Fd::Stdout) {
+ &mut self.std_out
+ } else {
+ &mut self.std_err
+ };
+ std::io::copy(&mut reader, writer)?;
v0 = a2;
}
Ok(Fd::HintWrite) => {
@@ -419,7 +418,7 @@ where
///
/// ### Returns
/// - A [Result] indicating if the branch dispatch was successful.
- pub fn handle_branch(
+ pub(crate) fn handle_branch(
&mut self,
opcode: u32,
instruction: u32,
@@ -480,7 +479,13 @@ where
///
/// ### Returns
/// - A [Result] indicating if the branch dispatch was successful.
- pub fn handle_hi_lo(&mut self, fun: u32, rs: u32, rt: u32, store_reg: u32) -> Result<()> {
+ pub(crate) fn handle_hi_lo(
+ &mut self,
+ fun: u32,
+ rs: u32,
+ rt: u32,
+ store_reg: u32,
+ ) -> Result<()> {
let val = match fun {
0x10 => {
// mfhi
@@ -502,7 +507,7 @@ where
}
0x18 => {
// mult
- let acc = (rs as i64) as u64 * (rt as i64) as u64;
+ let acc = ((rs as i32) as i64) as u64 * ((rt as i32) as i64) as u64;
self.state.hi = (acc >> 32) as u32;
self.state.lo = acc as u32;
0
@@ -547,7 +552,7 @@ where
///
/// ### Returns
/// - A [Result] indicating if the branch dispatch was successful.
- pub fn handle_jump(&mut self, link_reg: u32, dest: u32) -> Result<()> {
+ pub(crate) fn handle_jump(&mut self, link_reg: u32, dest: u32) -> Result<()> {
if self.state.next_pc != self.state.pc + 4 {
anyhow::bail!("Unexpected jump in delay slot at {:x}", self.state.pc);
}
@@ -570,7 +575,7 @@ where
///
/// ### Returns
/// - A [Result] indicating if the branch dispatch was successful.
- pub fn handle_rd(&mut self, store_reg: u32, val: u32, conditional: bool) -> Result<()> {
+ pub(crate) fn handle_rd(&mut self, store_reg: u32, val: u32, conditional: bool) -> Result<()> {
if store_reg >= 32 {
anyhow::bail!("Invalid register index {}", store_reg);
}
@@ -595,7 +600,7 @@ where
/// ### Returns
/// - `Ok(n)` - The result of the instruction execution.
/// - `Err(_)`: An error occurred while executing the instruction.
- pub fn execute(&mut self, instruction: u32, rs: u32, rt: u32, mem: u32) -> Result {
+ pub(crate) fn execute(&mut self, instruction: u32, rs: u32, rt: u32, mem: u32) -> Result {
// Opcodes in MIPS are 6 bits in size, and stored in the high-order bits of the big-endian
// instruction.
let opcode = instruction >> 26;
@@ -621,9 +626,9 @@ where
match fun {
// sll
- 0 => Ok(rt << (instruction >> 6) & 0x1F),
+ 0 => Ok(rt << ((instruction >> 6) & 0x1F)),
// srl
- 2 => Ok(rt >> (instruction >> 6) & 0x1F),
+ 2 => Ok(rt >> ((instruction >> 6) & 0x1F)),
// sra
3 => {
let shamt = (instruction >> 6) & 0x1F;