diff --git a/src/ansys/aedt/core/hfss3dlayout.py b/src/ansys/aedt/core/hfss3dlayout.py index 2e0fb0770a3..a0868120710 100644 --- a/src/ansys/aedt/core/hfss3dlayout.py +++ b/src/ansys/aedt/core/hfss3dlayout.py @@ -689,13 +689,15 @@ def create_pin_port(self, name, x=0, y=0, rotation=0, top_layer=None, bottom_lay return False @pyaedt_function_handler(portname="name") - def delete_port(self, name): + def delete_port(self, name, remove_geometry=True): """Delete a port. Parameters ---------- name : str Name of the port. + remove_geometry : bool, optional + Whether to remove geometry. The default is ``True``. Returns ------- @@ -705,8 +707,13 @@ def delete_port(self, name): References ---------- >>> oModule.Delete + >>> oModule.DeleteExcitations """ - self.oexcitation.Delete(name) + if remove_geometry: + self.oexcitation.Delete(name) + else: + self.oexcitation.DeleteExcitation(name) + for bound in self.boundaries: if bound.name == name: self.boundaries.remove(bound) diff --git a/tests/system/general/test_41_3dlayout_modeler.py b/tests/system/general/test_41_3dlayout_modeler.py index 53277fd743a..b54296bab67 100644 --- a/tests/system/general/test_41_3dlayout_modeler.py +++ b/tests/system/general/test_41_3dlayout_modeler.py @@ -354,6 +354,12 @@ def test_14a_create_coaxial_port(self): port = self.aedtapp.create_coax_port("port_via", 0.5, "Top", "Lower") assert port.name == "Port2" assert port.props["Radial Extent Factor"] == "0.5" + self.aedtapp.delete_port(name=port.name, remove_geometry=False) + assert len(self.aedtapp.port_list) == 0 + self.aedtapp.odesign.Undo() + self.aedtapp.delete_port(name=port.name) + assert len(self.aedtapp.port_list) == 0 + self.aedtapp.odesign.Undo() def test_14_create_setup(self): setup_name = "RFBoardSetup"